aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h')
-rw-r--r--arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h32
1 files changed, 3 insertions, 29 deletions
diff --git a/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h b/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h
index c2c3da9444f..fc160101dea 100644
--- a/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h
+++ b/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h
@@ -1,4 +1,4 @@
1/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. 1/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
2 * 2 *
3 * This program is free software; you can redistribute it and/or modify 3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and 4 * it under the terms of the GNU General Public License version 2 and
@@ -68,6 +68,7 @@ do { \
68#define FL_CACHEABLE (1 << 3) 68#define FL_CACHEABLE (1 << 3)
69#define FL_TEX0 (1 << 12) 69#define FL_TEX0 (1 << 12)
70#define FL_OFFSET(va) (((va) & 0xFFF00000) >> 20) 70#define FL_OFFSET(va) (((va) & 0xFFF00000) >> 20)
71#define FL_NG (1 << 17)
71 72
72/* Second-level page table bits */ 73/* Second-level page table bits */
73#define SL_BASE_MASK_LARGE 0xFFFF0000 74#define SL_BASE_MASK_LARGE 0xFFFF0000
@@ -81,6 +82,7 @@ do { \
81#define SL_CACHEABLE (1 << 3) 82#define SL_CACHEABLE (1 << 3)
82#define SL_TEX0 (1 << 6) 83#define SL_TEX0 (1 << 6)
83#define SL_OFFSET(va) (((va) & 0xFF000) >> 12) 84#define SL_OFFSET(va) (((va) & 0xFF000) >> 12)
85#define SL_NG (1 << 11)
84 86
85/* Memory type and cache policy attributes */ 87/* Memory type and cache policy attributes */
86#define MT_SO 0 88#define MT_SO 0
@@ -623,20 +625,6 @@ do { \
623#define SET_INDEX(b, c, v) SET_CONTEXT_FIELD(b, c, V2PSR, INDEX, v) 625#define SET_INDEX(b, c, v) SET_CONTEXT_FIELD(b, c, V2PSR, INDEX, v)
624 626
625 627
626/* V2Pxx UW UR PW PR */
627#define SET_V2PUW_INDEX(b, c, v) SET_CONTEXT_FIELD(b, c, V2PUW, V2Pxx_INDEX, v)
628#define SET_V2PUW_VA(b, c, v) SET_CONTEXT_FIELD(b, c, V2PUW, V2Pxx_VA, v)
629
630#define SET_V2PUR_INDEX(b, c, v) SET_CONTEXT_FIELD(b, c, V2PUR, V2Pxx_INDEX, v)
631#define SET_V2PUR_VA(b, c, v) SET_CONTEXT_FIELD(b, c, V2PUR, V2Pxx_VA, v)
632
633#define SET_V2PPW_INDEX(b, c, v) SET_CONTEXT_FIELD(b, c, V2PPW, V2Pxx_INDEX, v)
634#define SET_V2PPW_VA(b, c, v) SET_CONTEXT_FIELD(b, c, V2PPW, V2Pxx_VA, v)
635
636#define SET_V2PPR_INDEX(b, c, v) SET_CONTEXT_FIELD(b, c, V2PPR, V2Pxx_INDEX, v)
637#define SET_V2PPR_VA(b, c, v) SET_CONTEXT_FIELD(b, c, V2PPR, V2Pxx_VA, v)
638
639
640/* Context Register getters */ 628/* Context Register getters */
641/* ACTLR */ 629/* ACTLR */
642#define GET_CFERE(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, CFERE) 630#define GET_CFERE(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, CFERE)
@@ -824,20 +812,6 @@ do { \
824#define GET_INDEX(b, c) GET_CONTEXT_FIELD(b, c, V2PSR, INDEX) 812#define GET_INDEX(b, c) GET_CONTEXT_FIELD(b, c, V2PSR, INDEX)
825 813
826 814
827/* V2Pxx UW UR PW PR */
828#define GET_V2PUW_INDEX(b, c) GET_CONTEXT_FIELD(b, c, V2PUW, V2Pxx_INDEX)
829#define GET_V2PUW_VA(b, c) GET_CONTEXT_FIELD(b, c, V2PUW, V2Pxx_VA)
830
831#define GET_V2PUR_INDEX(b, c) GET_CONTEXT_FIELD(b, c, V2PUR, V2Pxx_INDEX)
832#define GET_V2PUR_VA(b, c) GET_CONTEXT_FIELD(b, c, V2PUR, V2Pxx_VA)
833
834#define GET_V2PPW_INDEX(b, c) GET_CONTEXT_FIELD(b, c, V2PPW, V2Pxx_INDEX)
835#define GET_V2PPW_VA(b, c) GET_CONTEXT_FIELD(b, c, V2PPW, V2Pxx_VA)
836
837#define GET_V2PPR_INDEX(b, c) GET_CONTEXT_FIELD(b, c, V2PPR, V2Pxx_INDEX)
838#define GET_V2PPR_VA(b, c) GET_CONTEXT_FIELD(b, c, V2PPR, V2Pxx_VA)
839
840
841/* Global Registers */ 815/* Global Registers */
842#define M2VCBR_N (0xFF000) 816#define M2VCBR_N (0xFF000)
843#define CBACR_N (0xFF800) 817#define CBACR_N (0xFF800)