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-rw-r--r--arch/arm/mach-msm/acpuclock-arm11.c525
-rw-r--r--arch/arm/mach-msm/acpuclock.h32
-rw-r--r--arch/arm/mach-msm/board-msm7x27.c162
-rw-r--r--arch/arm/mach-msm/board-msm8960.c91
-rw-r--r--arch/arm/mach-msm/board-msm8x60.c93
-rw-r--r--arch/arm/mach-msm/devices-msm8960.c85
-rw-r--r--arch/arm/mach-msm/idle.S36
-rw-r--r--arch/arm/mach-msm/include/mach/entry-macro-qgic.S88
-rw-r--r--arch/arm/mach-msm/include/mach/entry-macro-vic.S37
-rw-r--r--arch/arm/mach-msm/include/mach/gpio.h26
-rw-r--r--arch/arm/mach-msm/include/mach/io.h36
-rw-r--r--arch/arm/mach-msm/include/mach/memory.h35
-rw-r--r--arch/arm/mach-msm/include/mach/mmc.h37
-rw-r--r--arch/arm/mach-msm/include/mach/msm_fb.h147
-rw-r--r--arch/arm/mach-msm/include/mach/system.h28
-rw-r--r--arch/arm/mach-msm/include/mach/vmalloc.h22
16 files changed, 1480 insertions, 0 deletions
diff --git a/arch/arm/mach-msm/acpuclock-arm11.c b/arch/arm/mach-msm/acpuclock-arm11.c
new file mode 100644
index 00000000000..805d4ee53f7
--- /dev/null
+++ b/arch/arm/mach-msm/acpuclock-arm11.c
@@ -0,0 +1,525 @@
1/* arch/arm/mach-msm/acpuclock.c
2 *
3 * MSM architecture clock driver
4 *
5 * Copyright (C) 2007 Google, Inc.
6 * Copyright (c) 2007 QUALCOMM Incorporated
7 * Author: San Mehat <san@android.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20#include <linux/kernel.h>
21#include <linux/init.h>
22#include <linux/list.h>
23#include <linux/errno.h>
24#include <linux/string.h>
25#include <linux/delay.h>
26#include <linux/clk.h>
27#include <linux/cpufreq.h>
28#include <linux/mutex.h>
29#include <linux/io.h>
30#include <mach/board.h>
31#include <mach/msm_iomap.h>
32
33#include "proc_comm.h"
34#include "acpuclock.h"
35
36
37#define A11S_CLK_CNTL_ADDR (MSM_CSR_BASE + 0x100)
38#define A11S_CLK_SEL_ADDR (MSM_CSR_BASE + 0x104)
39#define A11S_VDD_SVS_PLEVEL_ADDR (MSM_CSR_BASE + 0x124)
40
41/*
42 * ARM11 clock configuration for specific ACPU speeds
43 */
44
45#define ACPU_PLL_TCXO -1
46#define ACPU_PLL_0 0
47#define ACPU_PLL_1 1
48#define ACPU_PLL_2 2
49#define ACPU_PLL_3 3
50
51#define PERF_SWITCH_DEBUG 0
52#define PERF_SWITCH_STEP_DEBUG 0
53
54struct clock_state
55{
56 struct clkctl_acpu_speed *current_speed;
57 struct mutex lock;
58 uint32_t acpu_switch_time_us;
59 uint32_t max_speed_delta_khz;
60 uint32_t vdd_switch_time_us;
61 unsigned long power_collapse_khz;
62 unsigned long wait_for_irq_khz;
63};
64
65static struct clk *ebi1_clk;
66static struct clock_state drv_state = { 0 };
67
68static void __init acpuclk_init(void);
69
70/* MSM7201A Levels 3-6 all correspond to 1.2V, level 7 corresponds to 1.325V. */
71enum {
72 VDD_0 = 0,
73 VDD_1 = 1,
74 VDD_2 = 2,
75 VDD_3 = 3,
76 VDD_4 = 3,
77 VDD_5 = 3,
78 VDD_6 = 3,
79 VDD_7 = 7,
80 VDD_END
81};
82
83struct clkctl_acpu_speed {
84 unsigned int a11clk_khz;
85 int pll;
86 unsigned int a11clk_src_sel;
87 unsigned int a11clk_src_div;
88 unsigned int ahbclk_khz;
89 unsigned int ahbclk_div;
90 int vdd;
91 unsigned int axiclk_khz;
92 unsigned long lpj; /* loops_per_jiffy */
93/* Index in acpu_freq_tbl[] for steppings. */
94 short down;
95 short up;
96};
97
98/*
99 * ACPU speed table. Complete table is shown but certain speeds are commented
100 * out to optimized speed switching. Initialize loops_per_jiffy to 0.
101 *
102 * Table stepping up/down is optimized for 256mhz jumps while staying on the
103 * same PLL.
104 */
105#if (0)
106static struct clkctl_acpu_speed acpu_freq_tbl[] = {
107 { 19200, ACPU_PLL_TCXO, 0, 0, 19200, 0, VDD_0, 30720, 0, 0, 8 },
108 { 61440, ACPU_PLL_0, 4, 3, 61440, 0, VDD_0, 30720, 0, 0, 8 },
109 { 81920, ACPU_PLL_0, 4, 2, 40960, 1, VDD_0, 61440, 0, 0, 8 },
110 { 96000, ACPU_PLL_1, 1, 7, 48000, 1, VDD_0, 61440, 0, 0, 9 },
111 { 122880, ACPU_PLL_0, 4, 1, 61440, 1, VDD_3, 61440, 0, 0, 8 },
112 { 128000, ACPU_PLL_1, 1, 5, 64000, 1, VDD_3, 61440, 0, 0, 12 },
113 { 176000, ACPU_PLL_2, 2, 5, 88000, 1, VDD_3, 61440, 0, 0, 11 },
114 { 192000, ACPU_PLL_1, 1, 3, 64000, 2, VDD_3, 61440, 0, 0, 12 },
115 { 245760, ACPU_PLL_0, 4, 0, 81920, 2, VDD_4, 61440, 0, 0, 12 },
116 { 256000, ACPU_PLL_1, 1, 2, 128000, 2, VDD_5, 128000, 0, 0, 12 },
117 { 264000, ACPU_PLL_2, 2, 3, 88000, 2, VDD_5, 128000, 0, 6, 13 },
118 { 352000, ACPU_PLL_2, 2, 2, 88000, 3, VDD_5, 128000, 0, 6, 13 },
119 { 384000, ACPU_PLL_1, 1, 1, 128000, 2, VDD_6, 128000, 0, 5, -1 },
120 { 528000, ACPU_PLL_2, 2, 1, 132000, 3, VDD_7, 128000, 0, 11, -1 },
121 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
122};
123#else /* Table of freq we currently use. */
124static struct clkctl_acpu_speed acpu_freq_tbl[] = {
125 { 19200, ACPU_PLL_TCXO, 0, 0, 19200, 0, VDD_0, 30720, 0, 0, 4 },
126 { 122880, ACPU_PLL_0, 4, 1, 61440, 1, VDD_3, 61440, 0, 0, 4 },
127 { 128000, ACPU_PLL_1, 1, 5, 64000, 1, VDD_3, 61440, 0, 0, 6 },
128 { 176000, ACPU_PLL_2, 2, 5, 88000, 1, VDD_3, 61440, 0, 0, 5 },
129 { 245760, ACPU_PLL_0, 4, 0, 81920, 2, VDD_4, 61440, 0, 0, 5 },
130 { 352000, ACPU_PLL_2, 2, 2, 88000, 3, VDD_5, 128000, 0, 3, 7 },
131 { 384000, ACPU_PLL_1, 1, 1, 128000, 2, VDD_6, 128000, 0, 2, -1 },
132 { 528000, ACPU_PLL_2, 2, 1, 132000, 3, VDD_7, 128000, 0, 5, -1 },
133 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
134};
135#endif
136
137
138#ifdef CONFIG_CPU_FREQ_TABLE
139static struct cpufreq_frequency_table freq_table[] = {
140 { 0, 122880 },
141 { 1, 128000 },
142 { 2, 245760 },
143 { 3, 384000 },
144 { 4, 528000 },
145 { 5, CPUFREQ_TABLE_END },
146};
147#endif
148
149static int pc_pll_request(unsigned id, unsigned on)
150{
151 int res;
152 on = !!on;
153
154#if PERF_SWITCH_DEBUG
155 if (on)
156 printk(KERN_DEBUG "Enabling PLL %d\n", id);
157 else
158 printk(KERN_DEBUG "Disabling PLL %d\n", id);
159#endif
160
161 res = msm_proc_comm(PCOM_CLKCTL_RPC_PLL_REQUEST, &id, &on);
162 if (res < 0)
163 return res;
164
165#if PERF_SWITCH_DEBUG
166 if (on)
167 printk(KERN_DEBUG "PLL %d enabled\n", id);
168 else
169 printk(KERN_DEBUG "PLL %d disabled\n", id);
170#endif
171 return res;
172}
173
174
175/*----------------------------------------------------------------------------
176 * ARM11 'owned' clock control
177 *---------------------------------------------------------------------------*/
178
179unsigned long acpuclk_power_collapse(void) {
180 int ret = acpuclk_get_rate();
181 ret *= 1000;
182 if (ret > drv_state.power_collapse_khz)
183 acpuclk_set_rate(drv_state.power_collapse_khz, 1);
184 return ret;
185}
186
187unsigned long acpuclk_get_wfi_rate(void)
188{
189 return drv_state.wait_for_irq_khz;
190}
191
192unsigned long acpuclk_wait_for_irq(void) {
193 int ret = acpuclk_get_rate();
194 ret *= 1000;
195 if (ret > drv_state.wait_for_irq_khz)
196 acpuclk_set_rate(drv_state.wait_for_irq_khz, 1);
197 return ret;
198}
199
200static int acpuclk_set_vdd_level(int vdd)
201{
202 uint32_t current_vdd;
203
204 current_vdd = readl(A11S_VDD_SVS_PLEVEL_ADDR) & 0x07;
205
206#if PERF_SWITCH_DEBUG
207 printk(KERN_DEBUG "acpuclock: Switching VDD from %u -> %d\n",
208 current_vdd, vdd);
209#endif
210 writel((1 << 7) | (vdd << 3), A11S_VDD_SVS_PLEVEL_ADDR);
211 udelay(drv_state.vdd_switch_time_us);
212 if ((readl(A11S_VDD_SVS_PLEVEL_ADDR) & 0x7) != vdd) {
213#if PERF_SWITCH_DEBUG
214 printk(KERN_ERR "acpuclock: VDD set failed\n");
215#endif
216 return -EIO;
217 }
218
219#if PERF_SWITCH_DEBUG
220 printk(KERN_DEBUG "acpuclock: VDD switched\n");
221#endif
222 return 0;
223}
224
225/* Set proper dividers for the given clock speed. */
226static void acpuclk_set_div(const struct clkctl_acpu_speed *hunt_s) {
227 uint32_t reg_clkctl, reg_clksel, clk_div;
228
229 /* AHB_CLK_DIV */
230 clk_div = (readl(A11S_CLK_SEL_ADDR) >> 1) & 0x03;
231 /*
232 * If the new clock divider is higher than the previous, then
233 * program the divider before switching the clock
234 */
235 if (hunt_s->ahbclk_div > clk_div) {
236 reg_clksel = readl(A11S_CLK_SEL_ADDR);
237 reg_clksel &= ~(0x3 << 1);
238 reg_clksel |= (hunt_s->ahbclk_div << 1);
239 writel(reg_clksel, A11S_CLK_SEL_ADDR);
240 }
241 if ((readl(A11S_CLK_SEL_ADDR) & 0x01) == 0) {
242 /* SRC0 */
243
244 /* Program clock source */
245 reg_clkctl = readl(A11S_CLK_CNTL_ADDR);
246 reg_clkctl &= ~(0x07 << 4);
247 reg_clkctl |= (hunt_s->a11clk_src_sel << 4);
248 writel(reg_clkctl, A11S_CLK_CNTL_ADDR);
249
250 /* Program clock divider */
251 reg_clkctl = readl(A11S_CLK_CNTL_ADDR);
252 reg_clkctl &= ~0xf;
253 reg_clkctl |= hunt_s->a11clk_src_div;
254 writel(reg_clkctl, A11S_CLK_CNTL_ADDR);
255
256 /* Program clock source selection */
257 reg_clksel = readl(A11S_CLK_SEL_ADDR);
258 reg_clksel |= 1; /* CLK_SEL_SRC1NO == SRC1 */
259 writel(reg_clksel, A11S_CLK_SEL_ADDR);
260 } else {
261 /* SRC1 */
262
263 /* Program clock source */
264 reg_clkctl = readl(A11S_CLK_CNTL_ADDR);
265 reg_clkctl &= ~(0x07 << 12);
266 reg_clkctl |= (hunt_s->a11clk_src_sel << 12);
267 writel(reg_clkctl, A11S_CLK_CNTL_ADDR);
268
269 /* Program clock divider */
270 reg_clkctl = readl(A11S_CLK_CNTL_ADDR);
271 reg_clkctl &= ~(0xf << 8);
272 reg_clkctl |= (hunt_s->a11clk_src_div << 8);
273 writel(reg_clkctl, A11S_CLK_CNTL_ADDR);
274
275 /* Program clock source selection */
276 reg_clksel = readl(A11S_CLK_SEL_ADDR);
277 reg_clksel &= ~1; /* CLK_SEL_SRC1NO == SRC0 */
278 writel(reg_clksel, A11S_CLK_SEL_ADDR);
279 }
280
281 /*
282 * If the new clock divider is lower than the previous, then
283 * program the divider after switching the clock
284 */
285 if (hunt_s->ahbclk_div < clk_div) {
286 reg_clksel = readl(A11S_CLK_SEL_ADDR);
287 reg_clksel &= ~(0x3 << 1);
288 reg_clksel |= (hunt_s->ahbclk_div << 1);
289 writel(reg_clksel, A11S_CLK_SEL_ADDR);
290 }
291}
292
293int acpuclk_set_rate(unsigned long rate, int for_power_collapse)
294{
295 uint32_t reg_clkctl;
296 struct clkctl_acpu_speed *cur_s, *tgt_s, *strt_s;
297 int rc = 0;
298 unsigned int plls_enabled = 0, pll;
299
300 strt_s = cur_s = drv_state.current_speed;
301
302 WARN_ONCE(cur_s == NULL, "acpuclk_set_rate: not initialized\n");
303 if (cur_s == NULL)
304 return -ENOENT;
305
306 if (rate == (cur_s->a11clk_khz * 1000))
307 return 0;
308
309 for (tgt_s = acpu_freq_tbl; tgt_s->a11clk_khz != 0; tgt_s++) {
310 if (tgt_s->a11clk_khz == (rate / 1000))
311 break;
312 }
313
314 if (tgt_s->a11clk_khz == 0)
315 return -EINVAL;
316
317 /* Choose the highest speed speed at or below 'rate' with same PLL. */
318 if (for_power_collapse && tgt_s->a11clk_khz < cur_s->a11clk_khz) {
319 while (tgt_s->pll != ACPU_PLL_TCXO && tgt_s->pll != cur_s->pll)
320 tgt_s--;
321 }
322
323 if (strt_s->pll != ACPU_PLL_TCXO)
324 plls_enabled |= 1 << strt_s->pll;
325
326 if (!for_power_collapse) {
327 mutex_lock(&drv_state.lock);
328 if (strt_s->pll != tgt_s->pll && tgt_s->pll != ACPU_PLL_TCXO) {
329 rc = pc_pll_request(tgt_s->pll, 1);
330 if (rc < 0) {
331 pr_err("PLL%d enable failed (%d)\n",
332 tgt_s->pll, rc);
333 goto out;
334 }
335 plls_enabled |= 1 << tgt_s->pll;
336 }
337 /* Increase VDD if needed. */
338 if (tgt_s->vdd > cur_s->vdd) {
339 if ((rc = acpuclk_set_vdd_level(tgt_s->vdd)) < 0) {
340 printk(KERN_ERR "Unable to switch ACPU vdd\n");
341 goto out;
342 }
343 }
344 }
345
346 /* Set wait states for CPU between frequency changes */
347 reg_clkctl = readl(A11S_CLK_CNTL_ADDR);
348 reg_clkctl |= (100 << 16); /* set WT_ST_CNT */
349 writel(reg_clkctl, A11S_CLK_CNTL_ADDR);
350
351#if PERF_SWITCH_DEBUG
352 printk(KERN_INFO "acpuclock: Switching from ACPU rate %u -> %u\n",
353 strt_s->a11clk_khz * 1000, tgt_s->a11clk_khz * 1000);
354#endif
355
356 while (cur_s != tgt_s) {
357 /*
358 * Always jump to target freq if within 256mhz, regulardless of
359 * PLL. If differnece is greater, use the predefinied
360 * steppings in the table.
361 */
362 int d = abs((int)(cur_s->a11clk_khz - tgt_s->a11clk_khz));
363 if (d > drv_state.max_speed_delta_khz) {
364 /* Step up or down depending on target vs current. */
365 int clk_index = tgt_s->a11clk_khz > cur_s->a11clk_khz ?
366 cur_s->up : cur_s->down;
367 if (clk_index < 0) { /* This should not happen. */
368 printk(KERN_ERR "cur:%u target: %u\n",
369 cur_s->a11clk_khz, tgt_s->a11clk_khz);
370 rc = -EINVAL;
371 goto out;
372 }
373 cur_s = &acpu_freq_tbl[clk_index];
374 } else {
375 cur_s = tgt_s;
376 }
377#if PERF_SWITCH_STEP_DEBUG
378 printk(KERN_DEBUG "%s: STEP khz = %u, pll = %d\n",
379 __FUNCTION__, cur_s->a11clk_khz, cur_s->pll);
380#endif
381 if (!for_power_collapse&& cur_s->pll != ACPU_PLL_TCXO
382 && !(plls_enabled & (1 << cur_s->pll))) {
383 rc = pc_pll_request(cur_s->pll, 1);
384 if (rc < 0) {
385 pr_err("PLL%d enable failed (%d)\n",
386 cur_s->pll, rc);
387 goto out;
388 }
389 plls_enabled |= 1 << cur_s->pll;
390 }
391
392 acpuclk_set_div(cur_s);
393 drv_state.current_speed = cur_s;
394 /* Re-adjust lpj for the new clock speed. */
395 loops_per_jiffy = cur_s->lpj;
396 udelay(drv_state.acpu_switch_time_us);
397 }
398
399 /* Nothing else to do for power collapse. */
400 if (for_power_collapse)
401 return 0;
402
403 /* Disable PLLs we are not using anymore. */
404 plls_enabled &= ~(1 << tgt_s->pll);
405 for (pll = ACPU_PLL_0; pll <= ACPU_PLL_2; pll++)
406 if (plls_enabled & (1 << pll)) {
407 rc = pc_pll_request(pll, 0);
408 if (rc < 0) {
409 pr_err("PLL%d disable failed (%d)\n", pll, rc);
410 goto out;
411 }
412 }
413
414 /* Change the AXI bus frequency if we can. */
415 if (strt_s->axiclk_khz != tgt_s->axiclk_khz) {
416 rc = clk_set_rate(ebi1_clk, tgt_s->axiclk_khz * 1000);
417 if (rc < 0)
418 pr_err("Setting AXI min rate failed!\n");
419 }
420
421 /* Drop VDD level if we can. */
422 if (tgt_s->vdd < strt_s->vdd) {
423 if (acpuclk_set_vdd_level(tgt_s->vdd) < 0)
424 printk(KERN_ERR "acpuclock: Unable to drop ACPU vdd\n");
425 }
426
427#if PERF_SWITCH_DEBUG
428 printk(KERN_DEBUG "%s: ACPU speed change complete\n", __FUNCTION__);
429#endif
430out:
431 if (!for_power_collapse)
432 mutex_unlock(&drv_state.lock);
433 return rc;
434}
435
436static void __init acpuclk_init(void)
437{
438 struct clkctl_acpu_speed *speed;
439 uint32_t div, sel;
440 int rc;
441
442 /*
443 * Determine the rate of ACPU clock
444 */
445
446 if (!(readl(A11S_CLK_SEL_ADDR) & 0x01)) { /* CLK_SEL_SRC1N0 */
447 /* CLK_SRC0_SEL */
448 sel = (readl(A11S_CLK_CNTL_ADDR) >> 12) & 0x7;
449 /* CLK_SRC0_DIV */
450 div = (readl(A11S_CLK_CNTL_ADDR) >> 8) & 0x0f;
451 } else {
452 /* CLK_SRC1_SEL */
453 sel = (readl(A11S_CLK_CNTL_ADDR) >> 4) & 0x07;
454 /* CLK_SRC1_DIV */
455 div = readl(A11S_CLK_CNTL_ADDR) & 0x0f;
456 }
457
458 for (speed = acpu_freq_tbl; speed->a11clk_khz != 0; speed++) {
459 if (speed->a11clk_src_sel == sel
460 && (speed->a11clk_src_div == div))
461 break;
462 }
463 if (speed->a11clk_khz == 0) {
464 printk(KERN_WARNING "Warning - ACPU clock reports invalid speed\n");
465 return;
466 }
467
468 drv_state.current_speed = speed;
469
470 rc = clk_set_rate(ebi1_clk, speed->axiclk_khz * 1000);
471 if (rc < 0)
472 pr_err("Setting AXI min rate failed!\n");
473
474 printk(KERN_INFO "ACPU running at %d KHz\n", speed->a11clk_khz);
475}
476
477unsigned long acpuclk_get_rate(void)
478{
479 WARN_ONCE(drv_state.current_speed == NULL,
480 "acpuclk_get_rate: not initialized\n");
481 if (drv_state.current_speed)
482 return drv_state.current_speed->a11clk_khz;
483 else
484 return 0;
485}
486
487uint32_t acpuclk_get_switch_time(void)
488{
489 return drv_state.acpu_switch_time_us;
490}
491
492/*----------------------------------------------------------------------------
493 * Clock driver initialization
494 *---------------------------------------------------------------------------*/
495
496/* Initialize the lpj field in the acpu_freq_tbl. */
497static void __init lpj_init(void)
498{
499 int i;
500 const struct clkctl_acpu_speed *base_clk = drv_state.current_speed;
501 for (i = 0; acpu_freq_tbl[i].a11clk_khz; i++) {
502 acpu_freq_tbl[i].lpj = cpufreq_scale(loops_per_jiffy,
503 base_clk->a11clk_khz,
504 acpu_freq_tbl[i].a11clk_khz);
505 }
506}
507
508void __init msm_acpu_clock_init(struct msm_acpu_clock_platform_data *clkdata)
509{
510 pr_info("acpu_clock_init()\n");
511
512 ebi1_clk = clk_get(NULL, "ebi1_clk");
513
514 mutex_init(&drv_state.lock);
515 drv_state.acpu_switch_time_us = clkdata->acpu_switch_time_us;
516 drv_state.max_speed_delta_khz = clkdata->max_speed_delta_khz;
517 drv_state.vdd_switch_time_us = clkdata->vdd_switch_time_us;
518 drv_state.power_collapse_khz = clkdata->power_collapse_khz;
519 drv_state.wait_for_irq_khz = clkdata->wait_for_irq_khz;
520 acpuclk_init();
521 lpj_init();
522#ifdef CONFIG_CPU_FREQ_TABLE
523 cpufreq_frequency_table_get_attr(freq_table, smp_processor_id());
524#endif
525}
diff --git a/arch/arm/mach-msm/acpuclock.h b/arch/arm/mach-msm/acpuclock.h
new file mode 100644
index 00000000000..415de2eb9a5
--- /dev/null
+++ b/arch/arm/mach-msm/acpuclock.h
@@ -0,0 +1,32 @@
1/* arch/arm/mach-msm/acpuclock.h
2 *
3 * MSM architecture clock driver header
4 *
5 * Copyright (C) 2007 Google, Inc.
6 * Copyright (c) 2007 QUALCOMM Incorporated
7 * Author: San Mehat <san@android.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20#ifndef __ARCH_ARM_MACH_MSM_ACPUCLOCK_H
21#define __ARCH_ARM_MACH_MSM_ACPUCLOCK_H
22
23int acpuclk_set_rate(unsigned long rate, int for_power_collapse);
24unsigned long acpuclk_get_rate(void);
25uint32_t acpuclk_get_switch_time(void);
26unsigned long acpuclk_wait_for_irq(void);
27unsigned long acpuclk_power_collapse(void);
28unsigned long acpuclk_get_wfi_rate(void);
29
30
31#endif
32
diff --git a/arch/arm/mach-msm/board-msm7x27.c b/arch/arm/mach-msm/board-msm7x27.c
new file mode 100644
index 00000000000..c03f269e2e4
--- /dev/null
+++ b/arch/arm/mach-msm/board-msm7x27.c
@@ -0,0 +1,162 @@
1/*
2 * Copyright (C) 2007 Google, Inc.
3 * Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved.
4 * Author: Brian Swetland <swetland@google.com>
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/platform_device.h>
20#include <linux/input.h>
21#include <linux/io.h>
22#include <linux/delay.h>
23#include <linux/power_supply.h>
24
25#include <mach/hardware.h>
26#include <asm/mach-types.h>
27#include <asm/mach/arch.h>
28#include <asm/mach/map.h>
29#include <asm/mach/flash.h>
30#include <asm/setup.h>
31#ifdef CONFIG_CACHE_L2X0
32#include <asm/hardware/cache-l2x0.h>
33#endif
34
35#include <mach/vreg.h>
36#include <mach/mpp.h>
37#include <mach/gpio.h>
38#include <mach/board.h>
39#include <mach/msm_iomap.h>
40
41#include <linux/mtd/nand.h>
42#include <linux/mtd/partitions.h>
43
44#include "devices.h"
45#include "socinfo.h"
46#include "clock.h"
47
48static struct resource smc91x_resources[] = {
49 [0] = {
50 .start = 0x9C004300,
51 .end = 0x9C0043ff,
52 .flags = IORESOURCE_MEM,
53 },
54 [1] = {
55 .start = MSM_GPIO_TO_INT(132),
56 .end = MSM_GPIO_TO_INT(132),
57 .flags = IORESOURCE_IRQ,
58 },
59};
60
61static struct platform_device smc91x_device = {
62 .name = "smc91x",
63 .id = 0,
64 .num_resources = ARRAY_SIZE(smc91x_resources),
65 .resource = smc91x_resources,
66};
67
68static struct platform_device *devices[] __initdata = {
69 &msm_device_uart3,
70 &msm_device_smd,
71 &msm_device_dmov,
72 &msm_device_nand,
73 &smc91x_device,
74};
75
76extern struct sys_timer msm_timer;
77
78static void __init msm7x2x_init_irq(void)
79{
80 msm_init_irq();
81}
82
83static void __init msm7x2x_init(void)
84{
85 if (socinfo_init() < 0)
86 BUG();
87
88 if (machine_is_msm7x25_ffa() || machine_is_msm7x27_ffa()) {
89 smc91x_resources[0].start = 0x98000300;
90 smc91x_resources[0].end = 0x980003ff;
91 smc91x_resources[1].start = MSM_GPIO_TO_INT(85);
92 smc91x_resources[1].end = MSM_GPIO_TO_INT(85);
93 if (gpio_tlmm_config(GPIO_CFG(85, 0,
94 GPIO_INPUT,
95 GPIO_PULL_DOWN,
96 GPIO_2MA),
97 GPIO_ENABLE)) {
98 printk(KERN_ERR
99 "%s: Err: Config GPIO-85 INT\n",
100 __func__);
101 }
102 }
103
104 platform_add_devices(devices, ARRAY_SIZE(devices));
105}
106
107static void __init msm7x2x_map_io(void)
108{
109 msm_map_common_io();
110 /* Technically dependent on the SoC but using machine_is
111 * macros since socinfo is not available this early and there
112 * are plans to restructure the code which will eliminate the
113 * need for socinfo.
114 */
115 if (machine_is_msm7x27_surf() || machine_is_msm7x27_ffa())
116 msm_clock_init(msm_clocks_7x27, msm_num_clocks_7x27);
117
118 if (machine_is_msm7x25_surf() || machine_is_msm7x25_ffa())
119 msm_clock_init(msm_clocks_7x25, msm_num_clocks_7x25);
120
121#ifdef CONFIG_CACHE_L2X0
122 if (machine_is_msm7x27_surf() || machine_is_msm7x27_ffa()) {
123 /* 7x27 has 256KB L2 cache:
124 64Kb/Way and 4-Way Associativity;
125 R/W latency: 3 cycles;
126 evmon/parity/share disabled. */
127 l2x0_init(MSM_L2CC_BASE, 0x00068012, 0xfe000000);
128 }
129#endif
130}
131
132MACHINE_START(MSM7X27_SURF, "QCT MSM7x27 SURF")
133 .boot_params = PLAT_PHYS_OFFSET + 0x100,
134 .map_io = msm7x2x_map_io,
135 .init_irq = msm7x2x_init_irq,
136 .init_machine = msm7x2x_init,
137 .timer = &msm_timer,
138MACHINE_END
139
140MACHINE_START(MSM7X27_FFA, "QCT MSM7x27 FFA")
141 .boot_params = PLAT_PHYS_OFFSET + 0x100,
142 .map_io = msm7x2x_map_io,
143 .init_irq = msm7x2x_init_irq,
144 .init_machine = msm7x2x_init,
145 .timer = &msm_timer,
146MACHINE_END
147
148MACHINE_START(MSM7X25_SURF, "QCT MSM7x25 SURF")
149 .boot_params = PLAT_PHYS_OFFSET + 0x100,
150 .map_io = msm7x2x_map_io,
151 .init_irq = msm7x2x_init_irq,
152 .init_machine = msm7x2x_init,
153 .timer = &msm_timer,
154MACHINE_END
155
156MACHINE_START(MSM7X25_FFA, "QCT MSM7x25 FFA")
157 .boot_params = PLAT_PHYS_OFFSET + 0x100,
158 .map_io = msm7x2x_map_io,
159 .init_irq = msm7x2x_init_irq,
160 .init_machine = msm7x2x_init,
161 .timer = &msm_timer,
162MACHINE_END
diff --git a/arch/arm/mach-msm/board-msm8960.c b/arch/arm/mach-msm/board-msm8960.c
new file mode 100644
index 00000000000..35c7ceeb3f2
--- /dev/null
+++ b/arch/arm/mach-msm/board-msm8960.c
@@ -0,0 +1,91 @@
1/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
15 * 02110-1301, USA.
16 *
17 */
18#include <linux/kernel.h>
19#include <linux/platform_device.h>
20#include <linux/io.h>
21#include <linux/irq.h>
22#include <linux/clkdev.h>
23
24#include <asm/mach-types.h>
25#include <asm/mach/arch.h>
26#include <asm/hardware/gic.h>
27
28#include <mach/board.h>
29#include <mach/msm_iomap.h>
30
31#include "devices.h"
32
33static void __init msm8960_map_io(void)
34{
35 msm_map_msm8960_io();
36}
37
38static void __init msm8960_init_irq(void)
39{
40 unsigned int i;
41 gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
42 (void *)MSM_QGIC_CPU_BASE);
43
44 /* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
45 writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
46
47 if (machine_is_msm8960_rumi3())
48 writel(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET);
49
50 /* FIXME: Not installing AVS_SVICINT and AVS_SVICINTSWDONE yet
51 * as they are configured as level, which does not play nice with
52 * handle_percpu_irq.
53 */
54 for (i = GIC_PPI_START; i < GIC_SPI_START; i++) {
55 if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE)
56 irq_set_handler(i, handle_percpu_irq);
57 }
58}
59
60static struct platform_device *sim_devices[] __initdata = {
61 &msm8960_device_uart_gsbi2,
62};
63
64static struct platform_device *rumi3_devices[] __initdata = {
65 &msm8960_device_uart_gsbi5,
66};
67
68static void __init msm8960_sim_init(void)
69{
70 platform_add_devices(sim_devices, ARRAY_SIZE(sim_devices));
71}
72
73static void __init msm8960_rumi3_init(void)
74{
75 platform_add_devices(rumi3_devices, ARRAY_SIZE(rumi3_devices));
76}
77
78MACHINE_START(MSM8960_SIM, "QCT MSM8960 SIMULATOR")
79 .map_io = msm8960_map_io,
80 .init_irq = msm8960_init_irq,
81 .timer = &msm_timer,
82 .init_machine = msm8960_sim_init,
83MACHINE_END
84
85MACHINE_START(MSM8960_RUMI3, "QCT MSM8960 RUMI3")
86 .map_io = msm8960_map_io,
87 .init_irq = msm8960_init_irq,
88 .timer = &msm_timer,
89 .init_machine = msm8960_rumi3_init,
90MACHINE_END
91
diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c
new file mode 100644
index 00000000000..1163b6fd05d
--- /dev/null
+++ b/arch/arm/mach-msm/board-msm8x60.c
@@ -0,0 +1,93 @@
1/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
15 * 02110-1301, USA.
16 *
17 */
18
19#include <linux/kernel.h>
20#include <linux/platform_device.h>
21#include <linux/io.h>
22#include <linux/irq.h>
23
24#include <asm/mach-types.h>
25#include <asm/mach/arch.h>
26#include <asm/hardware/gic.h>
27
28#include <mach/board.h>
29#include <mach/msm_iomap.h>
30
31
32static void __init msm8x60_map_io(void)
33{
34 msm_map_msm8x60_io();
35}
36
37static void __init msm8x60_init_irq(void)
38{
39 unsigned int i;
40
41 gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
42 (void *)MSM_QGIC_CPU_BASE);
43
44 /* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
45 writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
46
47 /* RUMI does not adhere to GIC spec by enabling STIs by default.
48 * Enable/clear is supposed to be RO for STIs, but is RW on RUMI.
49 */
50 if (!machine_is_msm8x60_sim())
51 writel(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET);
52
53 /* FIXME: Not installing AVS_SVICINT and AVS_SVICINTSWDONE yet
54 * as they are configured as level, which does not play nice with
55 * handle_percpu_irq.
56 */
57 for (i = GIC_PPI_START; i < GIC_SPI_START; i++) {
58 if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE)
59 irq_set_handler(i, handle_percpu_irq);
60 }
61}
62
63static void __init msm8x60_init(void)
64{
65}
66
67MACHINE_START(MSM8X60_RUMI3, "QCT MSM8X60 RUMI3")
68 .map_io = msm8x60_map_io,
69 .init_irq = msm8x60_init_irq,
70 .init_machine = msm8x60_init,
71 .timer = &msm_timer,
72MACHINE_END
73
74MACHINE_START(MSM8X60_SURF, "QCT MSM8X60 SURF")
75 .map_io = msm8x60_map_io,
76 .init_irq = msm8x60_init_irq,
77 .init_machine = msm8x60_init,
78 .timer = &msm_timer,
79MACHINE_END
80
81MACHINE_START(MSM8X60_SIM, "QCT MSM8X60 SIMULATOR")
82 .map_io = msm8x60_map_io,
83 .init_irq = msm8x60_init_irq,
84 .init_machine = msm8x60_init,
85 .timer = &msm_timer,
86MACHINE_END
87
88MACHINE_START(MSM8X60_FFA, "QCT MSM8X60 FFA")
89 .map_io = msm8x60_map_io,
90 .init_irq = msm8x60_init_irq,
91 .init_machine = msm8x60_init,
92 .timer = &msm_timer,
93MACHINE_END
diff --git a/arch/arm/mach-msm/devices-msm8960.c b/arch/arm/mach-msm/devices-msm8960.c
new file mode 100644
index 00000000000..d9e1f26475d
--- /dev/null
+++ b/arch/arm/mach-msm/devices-msm8960.c
@@ -0,0 +1,85 @@
1/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
15 * 02110-1301, USA.
16 */
17
18#include <linux/kernel.h>
19#include <linux/platform_device.h>
20
21#include <linux/dma-mapping.h>
22#include <mach/irqs-8960.h>
23#include <mach/board.h>
24
25#include "devices.h"
26
27#define MSM_GSBI2_PHYS 0x16100000
28#define MSM_UART2DM_PHYS (MSM_GSBI2_PHYS + 0x40000)
29
30#define MSM_GSBI5_PHYS 0x16400000
31#define MSM_UART5DM_PHYS (MSM_GSBI5_PHYS + 0x40000)
32
33static struct resource resources_uart_gsbi2[] = {
34 {
35 .start = GSBI2_UARTDM_IRQ,
36 .end = GSBI2_UARTDM_IRQ,
37 .flags = IORESOURCE_IRQ,
38 },
39 {
40 .start = MSM_UART2DM_PHYS,
41 .end = MSM_UART2DM_PHYS + PAGE_SIZE - 1,
42 .name = "uart_resource",
43 .flags = IORESOURCE_MEM,
44 },
45 {
46 .start = MSM_GSBI2_PHYS,
47 .end = MSM_GSBI2_PHYS + PAGE_SIZE - 1,
48 .name = "gsbi_resource",
49 .flags = IORESOURCE_MEM,
50 },
51};
52
53struct platform_device msm8960_device_uart_gsbi2 = {
54 .name = "msm_serial",
55 .id = 0,
56 .num_resources = ARRAY_SIZE(resources_uart_gsbi2),
57 .resource = resources_uart_gsbi2,
58};
59
60static struct resource resources_uart_gsbi5[] = {
61 {
62 .start = GSBI5_UARTDM_IRQ,
63 .end = GSBI5_UARTDM_IRQ,
64 .flags = IORESOURCE_IRQ,
65 },
66 {
67 .start = MSM_UART5DM_PHYS,
68 .end = MSM_UART5DM_PHYS + PAGE_SIZE - 1,
69 .name = "uart_resource",
70 .flags = IORESOURCE_MEM,
71 },
72 {
73 .start = MSM_GSBI5_PHYS,
74 .end = MSM_GSBI5_PHYS + PAGE_SIZE - 1,
75 .name = "gsbi_resource",
76 .flags = IORESOURCE_MEM,
77 },
78};
79
80struct platform_device msm8960_device_uart_gsbi5 = {
81 .name = "msm_serial",
82 .id = 0,
83 .num_resources = ARRAY_SIZE(resources_uart_gsbi5),
84 .resource = resources_uart_gsbi5,
85};
diff --git a/arch/arm/mach-msm/idle.S b/arch/arm/mach-msm/idle.S
new file mode 100644
index 00000000000..6a94f052713
--- /dev/null
+++ b/arch/arm/mach-msm/idle.S
@@ -0,0 +1,36 @@
1/* arch/arm/mach-msm/include/mach/idle.S
2 *
3 * Idle processing for MSM7K - work around bugs with SWFI.
4 *
5 * Copyright (c) 2007 QUALCOMM Incorporated.
6 * Copyright (C) 2007 Google, Inc.
7 *
8 * This software is licensed under the terms of the GNU General Public
9 * License version 2, as published by the Free Software Foundation, and
10 * may be copied, distributed, and modified under those terms.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 */
18
19#include <linux/linkage.h>
20#include <asm/assembler.h>
21
22ENTRY(arch_idle)
23#ifdef CONFIG_MSM7X00A_IDLE
24 mrc p15, 0, r1, c1, c0, 0 /* read current CR */
25 bic r0, r1, #(1 << 2) /* clear dcache bit */
26 bic r0, r0, #(1 << 12) /* clear icache bit */
27 mcr p15, 0, r0, c1, c0, 0 /* disable d/i cache */
28
29 mov r0, #0 /* prepare wfi value */
30 mcr p15, 0, r0, c7, c10, 0 /* flush the cache */
31 mcr p15, 0, r0, c7, c10, 4 /* memory barrier */
32 mcr p15, 0, r0, c7, c0, 4 /* wait for interrupt */
33
34 mcr p15, 0, r1, c1, c0, 0 /* restore d/i cache */
35#endif
36 mov pc, lr
diff --git a/arch/arm/mach-msm/include/mach/entry-macro-qgic.S b/arch/arm/mach-msm/include/mach/entry-macro-qgic.S
new file mode 100644
index 00000000000..12467157afb
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/entry-macro-qgic.S
@@ -0,0 +1,88 @@
1/*
2 * Low-level IRQ helper macros
3 *
4 * Copyright (c) 2010, Code Aurora Forum. All rights reserved.
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <mach/hardware.h>
12#include <asm/hardware/gic.h>
13
14 .macro disable_fiq
15 .endm
16
17 .macro get_irqnr_preamble, base, tmp
18 ldr \base, =gic_cpu_base_addr
19 ldr \base, [\base]
20 .endm
21
22 .macro arch_ret_to_user, tmp1, tmp2
23 .endm
24
25 /*
26 * The interrupt numbering scheme is defined in the
27 * interrupt controller spec. To wit:
28 *
29 * Migrated the code from ARM MP port to be more consistent
30 * with interrupt processing , the following still holds true
31 * however, all interrupts are treated the same regardless of
32 * if they are local IPI or PPI
33 *
34 * Interrupts 0-15 are IPI
35 * 16-31 are PPI
36 * (16-18 are the timers)
37 * 32-1020 are global
38 * 1021-1022 are reserved
39 * 1023 is "spurious" (no interrupt)
40 *
41 * A simple read from the controller will tell us the number of the
42 * highest priority enabled interrupt. We then just need to check
43 * whether it is in the valid range for an IRQ (0-1020 inclusive).
44 *
45 * Base ARM code assumes that the local (private) peripheral interrupts
46 * are not valid, we treat them differently, in that the privates are
47 * handled like normal shared interrupts with the exception that only
48 * one processor can register the interrupt and the handler must be
49 * the same for all processors.
50 */
51
52 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
53
54 ldr \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 =srcCPU,
55 9-0 =int # */
56
57 bic \irqnr, \irqstat, #0x1c00 @mask src
58 cmp \irqnr, #15
59 ldr \tmp, =1021
60 cmpcc \irqnr, \irqnr
61 cmpne \irqnr, \tmp
62 cmpcs \irqnr, \irqnr
63
64 .endm
65
66 /* We assume that irqstat (the raw value of the IRQ acknowledge
67 * register) is preserved from the macro above.
68 * If there is an IPI, we immediately signal end of interrupt on the
69 * controller, since this requires the original irqstat value which
70 * we won't easily be able to recreate later.
71 */
72 .macro test_for_ipi, irqnr, irqstat, base, tmp
73 bic \irqnr, \irqstat, #0x1c00
74 cmp \irqnr, #16
75 strcc \irqstat, [\base, #GIC_CPU_EOI]
76 cmpcs \irqnr, \irqnr
77 .endm
78
79 /* As above, this assumes that irqstat and base are preserved.. */
80
81 .macro test_for_ltirq, irqnr, irqstat, base, tmp
82 bic \irqnr, \irqstat, #0x1c00
83 mov \tmp, #0
84 cmp \irqnr, #16
85 moveq \tmp, #1
86 streq \irqstat, [\base, #GIC_CPU_EOI]
87 cmp \tmp, #0
88 .endm
diff --git a/arch/arm/mach-msm/include/mach/entry-macro-vic.S b/arch/arm/mach-msm/include/mach/entry-macro-vic.S
new file mode 100644
index 00000000000..70563ed11b3
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/entry-macro-vic.S
@@ -0,0 +1,37 @@
1/*
2 * Copyright (C) 2007 Google, Inc.
3 * Author: Brian Swetland <swetland@google.com>
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 */
15
16#include <mach/msm_iomap.h>
17
18 .macro disable_fiq
19 .endm
20
21 .macro get_irqnr_preamble, base, tmp
22 @ enable imprecise aborts
23 cpsie a
24 mov \base, #MSM_VIC_BASE
25 .endm
26
27 .macro arch_ret_to_user, tmp1, tmp2
28 .endm
29
30 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
31 @ 0xD0 has irq# or old irq# if the irq has been handled
32 @ 0xD4 has irq# or -1 if none pending *but* if you just
33 @ read 0xD4 you never get the first irq for some reason
34 ldr \irqnr, [\base, #0xD0]
35 ldr \irqnr, [\base, #0xD4]
36 cmp \irqnr, #0xffffffff
37 .endm
diff --git a/arch/arm/mach-msm/include/mach/gpio.h b/arch/arm/mach-msm/include/mach/gpio.h
new file mode 100644
index 00000000000..36ad50d3bfa
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/gpio.h
@@ -0,0 +1,26 @@
1/*
2 * Copyright (C) 2007 Google, Inc.
3 * Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved.
4 * Author: Mike Lockwood <lockwood@android.com>
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16#ifndef __ASM_ARCH_MSM_GPIO_H
17#define __ASM_ARCH_MSM_GPIO_H
18
19#include <asm-generic/gpio.h>
20
21#define gpio_get_value __gpio_get_value
22#define gpio_set_value __gpio_set_value
23#define gpio_cansleep __gpio_cansleep
24#define gpio_to_irq __gpio_to_irq
25
26#endif /* __ASM_ARCH_MSM_GPIO_H */
diff --git a/arch/arm/mach-msm/include/mach/io.h b/arch/arm/mach-msm/include/mach/io.h
new file mode 100644
index 00000000000..dc1b928745e
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/io.h
@@ -0,0 +1,36 @@
1/* arch/arm/mach-msm/include/mach/io.h
2 *
3 * Copyright (C) 2007 Google, Inc.
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 */
15
16#ifndef __ASM_ARM_ARCH_IO_H
17#define __ASM_ARM_ARCH_IO_H
18
19#define IO_SPACE_LIMIT 0xffffffff
20
21#define __arch_ioremap __msm_ioremap
22#define __arch_iounmap __iounmap
23
24void __iomem *__msm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype);
25
26#define __io(a) __typesafe_io(a)
27#define __mem_pci(a) (a)
28
29void msm_map_qsd8x50_io(void);
30void msm_map_msm7x30_io(void);
31void msm_map_msm8x60_io(void);
32void msm_map_msm8960_io(void);
33
34extern unsigned int msm_shared_ram_phys;
35
36#endif
diff --git a/arch/arm/mach-msm/include/mach/memory.h b/arch/arm/mach-msm/include/mach/memory.h
new file mode 100644
index 00000000000..f2f8d299ba9
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/memory.h
@@ -0,0 +1,35 @@
1/* arch/arm/mach-msm/include/mach/memory.h
2 *
3 * Copyright (C) 2007 Google, Inc.
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 */
15
16#ifndef __ASM_ARCH_MEMORY_H
17#define __ASM_ARCH_MEMORY_H
18
19/* physical offset of RAM */
20#if defined(CONFIG_ARCH_QSD8X50) && defined(CONFIG_MSM_SOC_REV_A)
21#define PLAT_PHYS_OFFSET UL(0x00000000)
22#elif defined(CONFIG_ARCH_QSD8X50)
23#define PLAT_PHYS_OFFSET UL(0x20000000)
24#elif defined(CONFIG_ARCH_MSM7X30)
25#define PLAT_PHYS_OFFSET UL(0x00200000)
26#elif defined(CONFIG_ARCH_MSM8X60)
27#define PLAT_PHYS_OFFSET UL(0x40200000)
28#elif defined(CONFIG_ARCH_MSM8960)
29#define PLAT_PHYS_OFFSET UL(0x40200000)
30#else
31#define PLAT_PHYS_OFFSET UL(0x10000000)
32#endif
33
34#endif
35
diff --git a/arch/arm/mach-msm/include/mach/mmc.h b/arch/arm/mach-msm/include/mach/mmc.h
new file mode 100644
index 00000000000..5631b51cec4
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/mmc.h
@@ -0,0 +1,37 @@
1/*
2 * arch/arm/include/asm/mach/mmc.h
3 */
4#ifndef ASMARM_MACH_MMC_H
5#define ASMARM_MACH_MMC_H
6
7#include <linux/mmc/host.h>
8#include <linux/mmc/card.h>
9#include <linux/mmc/sdio_func.h>
10
11struct embedded_sdio_data {
12 struct sdio_cis cis;
13 struct sdio_cccr cccr;
14 struct sdio_embedded_func *funcs;
15 int num_funcs;
16};
17
18struct msm_mmc_gpio {
19 unsigned no;
20 const char *name;
21};
22
23struct msm_mmc_gpio_data {
24 struct msm_mmc_gpio *gpio;
25 u8 size;
26};
27
28struct msm_mmc_platform_data {
29 unsigned int ocr_mask; /* available voltages */
30 u32 (*translate_vdd)(struct device *, unsigned int);
31 unsigned int (*status)(struct device *);
32 struct embedded_sdio_data *embedded_sdio;
33 int (*register_status_notify)(void (*callback)(int card_present, void *dev_id), void *dev_id);
34 struct msm_mmc_gpio_data *gpio_data;
35};
36
37#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_fb.h b/arch/arm/mach-msm/include/mach/msm_fb.h
new file mode 100644
index 00000000000..1f4fc81b3d8
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/msm_fb.h
@@ -0,0 +1,147 @@
1/* arch/arm/mach-msm/include/mach/msm_fb.h
2 *
3 * Internal shared definitions for various MSM framebuffer parts.
4 *
5 * Copyright (C) 2007 Google Incorporated
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#ifndef _MSM_FB_H_
18#define _MSM_FB_H_
19
20#include <linux/device.h>
21
22struct mddi_info;
23
24struct msm_fb_data {
25 int xres; /* x resolution in pixels */
26 int yres; /* y resolution in pixels */
27 int width; /* disply width in mm */
28 int height; /* display height in mm */
29 unsigned output_format;
30};
31
32struct msmfb_callback {
33 void (*func)(struct msmfb_callback *);
34};
35
36enum {
37 MSM_MDDI_PMDH_INTERFACE,
38 MSM_MDDI_EMDH_INTERFACE,
39 MSM_EBI2_INTERFACE,
40};
41
42#define MSMFB_CAP_PARTIAL_UPDATES (1 << 0)
43
44struct msm_panel_data {
45 /* turns off the fb memory */
46 int (*suspend)(struct msm_panel_data *);
47 /* turns on the fb memory */
48 int (*resume)(struct msm_panel_data *);
49 /* turns off the panel */
50 int (*blank)(struct msm_panel_data *);
51 /* turns on the panel */
52 int (*unblank)(struct msm_panel_data *);
53 void (*wait_vsync)(struct msm_panel_data *);
54 void (*request_vsync)(struct msm_panel_data *, struct msmfb_callback *);
55 void (*clear_vsync)(struct msm_panel_data *);
56 /* from the enum above */
57 unsigned interface_type;
58 /* data to be passed to the fb driver */
59 struct msm_fb_data *fb_data;
60
61 /* capabilities supported by the panel */
62 uint32_t caps;
63};
64
65struct msm_mddi_client_data {
66 void (*suspend)(struct msm_mddi_client_data *);
67 void (*resume)(struct msm_mddi_client_data *);
68 void (*activate_link)(struct msm_mddi_client_data *);
69 void (*remote_write)(struct msm_mddi_client_data *, uint32_t val,
70 uint32_t reg);
71 uint32_t (*remote_read)(struct msm_mddi_client_data *, uint32_t reg);
72 void (*auto_hibernate)(struct msm_mddi_client_data *, int);
73 /* custom data that needs to be passed from the board file to a
74 * particular client */
75 void *private_client_data;
76 struct resource *fb_resource;
77 /* from the list above */
78 unsigned interface_type;
79};
80
81struct msm_mddi_platform_data {
82 unsigned int clk_rate;
83 void (*power_client)(struct msm_mddi_client_data *, int on);
84
85 /* fixup the mfr name, product id */
86 void (*fixup)(uint16_t *mfr_name, uint16_t *product_id);
87
88 struct resource *fb_resource; /*optional*/
89 /* number of clients in the list that follows */
90 int num_clients;
91 /* array of client information of clients */
92 struct {
93 unsigned product_id; /* mfr id in top 16 bits, product id
94 * in lower 16 bits
95 */
96 char *name; /* the device name will be the platform
97 * device name registered for the client,
98 * it should match the name of the associated
99 * driver
100 */
101 unsigned id; /* id for mddi client device node, will also
102 * be used as device id of panel devices, if
103 * the client device will have multiple panels
104 * space must be left here for them
105 */
106 void *client_data; /* required private client data */
107 unsigned int clk_rate; /* optional: if the client requires a
108 * different mddi clk rate
109 */
110 } client_platform_data[];
111};
112
113struct mdp_blit_req;
114struct fb_info;
115struct mdp_device {
116 struct device dev;
117 void (*dma)(struct mdp_device *mpd, uint32_t addr,
118 uint32_t stride, uint32_t w, uint32_t h, uint32_t x,
119 uint32_t y, struct msmfb_callback *callback, int interface);
120 void (*dma_wait)(struct mdp_device *mdp);
121 int (*blit)(struct mdp_device *mdp, struct fb_info *fb,
122 struct mdp_blit_req *req);
123 void (*set_grp_disp)(struct mdp_device *mdp, uint32_t disp_id);
124};
125
126struct class_interface;
127int register_mdp_client(struct class_interface *class_intf);
128
129/**** private client data structs go below this line ***/
130
131struct msm_mddi_bridge_platform_data {
132 /* from board file */
133 int (*init)(struct msm_mddi_bridge_platform_data *,
134 struct msm_mddi_client_data *);
135 int (*uninit)(struct msm_mddi_bridge_platform_data *,
136 struct msm_mddi_client_data *);
137 /* passed to panel for use by the fb driver */
138 int (*blank)(struct msm_mddi_bridge_platform_data *,
139 struct msm_mddi_client_data *);
140 int (*unblank)(struct msm_mddi_bridge_platform_data *,
141 struct msm_mddi_client_data *);
142 struct msm_fb_data fb_data;
143};
144
145
146
147#endif
diff --git a/arch/arm/mach-msm/include/mach/system.h b/arch/arm/mach-msm/include/mach/system.h
new file mode 100644
index 00000000000..d2e83f42ba1
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/system.h
@@ -0,0 +1,28 @@
1/* arch/arm/mach-msm/include/mach/system.h
2 *
3 * Copyright (C) 2007 Google, Inc.
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 */
15
16#include <mach/hardware.h>
17
18void arch_idle(void);
19
20static inline void arch_reset(char mode, const char *cmd)
21{
22 for (;;) ; /* depends on IPC w/ other core */
23}
24
25/* low level hardware reset hook -- for example, hitting the
26 * PSHOLD line on the PMIC to hard reset the system
27 */
28extern void (*msm_hw_reset_hook)(void);
diff --git a/arch/arm/mach-msm/include/mach/vmalloc.h b/arch/arm/mach-msm/include/mach/vmalloc.h
new file mode 100644
index 00000000000..d138448eff1
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/vmalloc.h
@@ -0,0 +1,22 @@
1/* arch/arm/mach-msm/include/mach/vmalloc.h
2 *
3 * Copyright (C) 2007 Google, Inc.
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 */
15
16#ifndef __ASM_ARCH_MSM_VMALLOC_H
17#define __ASM_ARCH_MSM_VMALLOC_H
18
19#define VMALLOC_END 0xd0000000UL
20
21#endif
22
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-02 15:22:36 -0400