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-rw-r--r--arch/arm/mach-lpc32xx/phy3250.c149
1 files changed, 52 insertions, 97 deletions
diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c
index 7f7401ec748..540106cdb9e 100644
--- a/arch/arm/mach-lpc32xx/phy3250.c
+++ b/arch/arm/mach-lpc32xx/phy3250.c
@@ -1,8 +1,9 @@
1/* 1/*
2 * arch/arm/mach-lpc32xx/phy3250.c 2 * Platform support for LPC32xx SoC
3 * 3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com> 4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 * 5 *
6 * Copyright (C) 2012 Roland Stigge <stigge@antcom.de>
6 * Copyright (C) 2010 NXP Semiconductors 7 * Copyright (C) 2010 NXP Semiconductors
7 * 8 *
8 * This program is free software; you can redistribute it and/or modify 9 * This program is free software; you can redistribute it and/or modify
@@ -25,11 +26,16 @@
25#include <linux/device.h> 26#include <linux/device.h>
26#include <linux/spi/spi.h> 27#include <linux/spi/spi.h>
27#include <linux/spi/eeprom.h> 28#include <linux/spi/eeprom.h>
28#include <linux/leds.h>
29#include <linux/gpio.h> 29#include <linux/gpio.h>
30#include <linux/amba/bus.h> 30#include <linux/amba/bus.h>
31#include <linux/amba/clcd.h> 31#include <linux/amba/clcd.h>
32#include <linux/amba/pl022.h> 32#include <linux/amba/pl022.h>
33#include <linux/of.h>
34#include <linux/of_address.h>
35#include <linux/of_irq.h>
36#include <linux/of_platform.h>
37#include <linux/clk.h>
38#include <linux/amba/pl08x.h>
33 39
34#include <asm/setup.h> 40#include <asm/setup.h>
35#include <asm/mach-types.h> 41#include <asm/mach-types.h>
@@ -47,7 +53,6 @@
47#define SPI0_CS_GPIO LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5) 53#define SPI0_CS_GPIO LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5)
48#define LCD_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 0) 54#define LCD_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 0)
49#define BKL_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 4) 55#define BKL_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 4)
50#define LED_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 1)
51 56
52/* 57/*
53 * AMBA LCD controller 58 * AMBA LCD controller
@@ -150,9 +155,6 @@ static struct clcd_board lpc32xx_clcd_data = {
150 .remove = lpc32xx_clcd_remove, 155 .remove = lpc32xx_clcd_remove,
151}; 156};
152 157
153static AMBA_AHB_DEVICE(lpc32xx_clcd, "dev:clcd", 0,
154 LPC32XX_LCD_BASE, { IRQ_LPC32XX_LCD }, &lpc32xx_clcd_data);
155
156/* 158/*
157 * AMBA SSP (SPI) 159 * AMBA SSP (SPI)
158 */ 160 */
@@ -180,8 +182,11 @@ static struct pl022_ssp_controller lpc32xx_ssp0_data = {
180 .enable_dma = 0, 182 .enable_dma = 0,
181}; 183};
182 184
183static AMBA_APB_DEVICE(lpc32xx_ssp0, "dev:ssp0", 0, 185static struct pl022_ssp_controller lpc32xx_ssp1_data = {
184 LPC32XX_SSP0_BASE, { IRQ_LPC32XX_SSP0 }, &lpc32xx_ssp0_data); 186 .bus_id = 1,
187 .num_chipselect = 1,
188 .enable_dma = 0,
189};
185 190
186/* AT25 driver registration */ 191/* AT25 driver registration */
187static int __init phy3250_spi_board_register(void) 192static int __init phy3250_spi_board_register(void)
@@ -221,73 +226,20 @@ static int __init phy3250_spi_board_register(void)
221} 226}
222arch_initcall(phy3250_spi_board_register); 227arch_initcall(phy3250_spi_board_register);
223 228
224static struct i2c_board_info __initdata phy3250_i2c_board_info[] = { 229static struct pl08x_platform_data pl08x_pd = {
225 {
226 I2C_BOARD_INFO("pcf8563", 0x51),
227 },
228};
229
230static struct gpio_led phy_leds[] = {
231 {
232 .name = "led0",
233 .gpio = LED_GPIO,
234 .active_low = 1,
235 .default_trigger = "heartbeat",
236 },
237};
238
239static struct gpio_led_platform_data led_data = {
240 .leds = phy_leds,
241 .num_leds = ARRAY_SIZE(phy_leds),
242};
243
244static struct platform_device lpc32xx_gpio_led_device = {
245 .name = "leds-gpio",
246 .id = -1,
247 .dev.platform_data = &led_data,
248}; 230};
249 231
250static struct platform_device *phy3250_devs[] __initdata = { 232static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = {
251 &lpc32xx_rtc_device, 233 OF_DEV_AUXDATA("arm,pl022", 0x20084000, "dev:ssp0", &lpc32xx_ssp0_data),
252 &lpc32xx_tsc_device, 234 OF_DEV_AUXDATA("arm,pl022", 0x2008C000, "dev:ssp1", &lpc32xx_ssp1_data),
253 &lpc32xx_i2c0_device, 235 OF_DEV_AUXDATA("arm,pl110", 0x31040000, "dev:clcd", &lpc32xx_clcd_data),
254 &lpc32xx_i2c1_device, 236 OF_DEV_AUXDATA("arm,pl080", 0x31000000, "pl08xdmac", &pl08x_pd),
255 &lpc32xx_i2c2_device, 237 { }
256 &lpc32xx_watchdog_device,
257 &lpc32xx_gpio_led_device,
258 &lpc32xx_adc_device,
259 &lpc32xx_ohci_device,
260 &lpc32xx_net_device,
261}; 238};
262 239
263static struct amba_device *amba_devs[] __initdata = { 240static void __init lpc3250_machine_init(void)
264 &lpc32xx_clcd_device,
265 &lpc32xx_ssp0_device,
266};
267
268/*
269 * Board specific functions
270 */
271static void __init phy3250_board_init(void)
272{ 241{
273 u32 tmp; 242 u32 tmp;
274 int i;
275
276 lpc32xx_gpio_init();
277
278 /* Register GPIOs used on this board */
279 if (gpio_request(SPI0_CS_GPIO, "spi0 cs"))
280 printk(KERN_ERR "Error requesting gpio %u",
281 SPI0_CS_GPIO);
282 else if (gpio_direction_output(SPI0_CS_GPIO, 1))
283 printk(KERN_ERR "Error setting gpio %u to output",
284 SPI0_CS_GPIO);
285
286 /* Setup network interface for RMII mode */
287 tmp = __raw_readl(LPC32XX_CLKPWR_MACCLK_CTRL);
288 tmp &= ~LPC32XX_CLKPWR_MACCTRL_PINS_MSK;
289 tmp |= LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS;
290 __raw_writel(tmp, LPC32XX_CLKPWR_MACCLK_CTRL);
291 243
292 /* Setup SLC NAND controller muxing */ 244 /* Setup SLC NAND controller muxing */
293 __raw_writel(LPC32XX_CLKPWR_NANDCLK_SEL_SLC, 245 __raw_writel(LPC32XX_CLKPWR_NANDCLK_SEL_SLC,
@@ -300,6 +252,12 @@ static void __init phy3250_board_init(void)
300 tmp |= LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16; 252 tmp |= LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16;
301 __raw_writel(tmp, LPC32XX_CLKPWR_LCDCLK_CTRL); 253 __raw_writel(tmp, LPC32XX_CLKPWR_LCDCLK_CTRL);
302 254
255 /* Set up USB power */
256 tmp = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
257 tmp |= LPC32XX_CLKPWR_USBCTRL_HCLK_EN |
258 LPC32XX_CLKPWR_USBCTRL_USBI2C_EN;
259 __raw_writel(tmp, LPC32XX_CLKPWR_USB_CTRL);
260
303 /* Set up I2C pull levels */ 261 /* Set up I2C pull levels */
304 tmp = __raw_readl(LPC32XX_CLKPWR_I2C_CLK_CTRL); 262 tmp = __raw_readl(LPC32XX_CLKPWR_I2C_CLK_CTRL);
305 tmp |= LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE | 263 tmp |= LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE |
@@ -321,54 +279,51 @@ static void __init phy3250_board_init(void)
321 /* 279 /*
322 * AMBA peripheral clocks need to be enabled prior to AMBA device 280 * AMBA peripheral clocks need to be enabled prior to AMBA device
323 * detection or a data fault will occur, so enable the clocks 281 * detection or a data fault will occur, so enable the clocks
324 * here. However, we don't want to enable them if the peripheral 282 * here.
325 * isn't included in the image
326 */ 283 */
327#ifdef CONFIG_FB_ARMCLCD
328 tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL); 284 tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL);
329 __raw_writel((tmp | LPC32XX_CLKPWR_LCDCTRL_CLK_EN), 285 __raw_writel((tmp | LPC32XX_CLKPWR_LCDCTRL_CLK_EN),
330 LPC32XX_CLKPWR_LCDCLK_CTRL); 286 LPC32XX_CLKPWR_LCDCLK_CTRL);
331#endif 287
332#ifdef CONFIG_SPI_PL022
333 tmp = __raw_readl(LPC32XX_CLKPWR_SSP_CLK_CTRL); 288 tmp = __raw_readl(LPC32XX_CLKPWR_SSP_CLK_CTRL);
334 __raw_writel((tmp | LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN), 289 __raw_writel((tmp | LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN),
335 LPC32XX_CLKPWR_SSP_CLK_CTRL); 290 LPC32XX_CLKPWR_SSP_CLK_CTRL);
336#endif
337 291
338 platform_add_devices(phy3250_devs, ARRAY_SIZE(phy3250_devs)); 292 tmp = __raw_readl(LPC32XX_CLKPWR_DMA_CLK_CTRL);
339 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { 293 __raw_writel((tmp | LPC32XX_CLKPWR_DMACLKCTRL_CLK_EN),
340 struct amba_device *d = amba_devs[i]; 294 LPC32XX_CLKPWR_DMA_CLK_CTRL);
341 amba_device_register(d, &iomem_resource);
342 }
343 295
344 /* Test clock needed for UDA1380 initial init */ 296 /* Test clock needed for UDA1380 initial init */
345 __raw_writel(LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC | 297 __raw_writel(LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC |
346 LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN, 298 LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN,
347 LPC32XX_CLKPWR_TEST_CLK_SEL); 299 LPC32XX_CLKPWR_TEST_CLK_SEL);
348 300
349 i2c_register_board_info(0, phy3250_i2c_board_info, 301 of_platform_populate(NULL, of_default_bus_match_table,
350 ARRAY_SIZE(phy3250_i2c_board_info)); 302 lpc32xx_auxdata_lookup, NULL);
351}
352
353static int __init lpc32xx_display_uid(void)
354{
355 u32 uid[4];
356
357 lpc32xx_get_uid(uid);
358
359 printk(KERN_INFO "LPC32XX unique ID: %08x%08x%08x%08x\n",
360 uid[3], uid[2], uid[1], uid[0]);
361 303
362 return 1; 304 /* Register GPIOs used on this board */
305 if (gpio_request(SPI0_CS_GPIO, "spi0 cs"))
306 printk(KERN_ERR "Error requesting gpio %u",
307 SPI0_CS_GPIO);
308 else if (gpio_direction_output(SPI0_CS_GPIO, 1))
309 printk(KERN_ERR "Error setting gpio %u to output",
310 SPI0_CS_GPIO);
363} 311}
364arch_initcall(lpc32xx_display_uid);
365 312
366MACHINE_START(PHY3250, "Phytec 3250 board with the LPC3250 Microcontroller") 313static char const *lpc32xx_dt_compat[] __initdata = {
367 /* Maintainer: Kevin Wells, NXP Semiconductors */ 314 "nxp,lpc3220",
315 "nxp,lpc3230",
316 "nxp,lpc3240",
317 "nxp,lpc3250",
318 NULL
319};
320
321DT_MACHINE_START(LPC32XX_DT, "LPC32XX SoC (Flattened Device Tree)")
368 .atag_offset = 0x100, 322 .atag_offset = 0x100,
369 .map_io = lpc32xx_map_io, 323 .map_io = lpc32xx_map_io,
370 .init_irq = lpc32xx_init_irq, 324 .init_irq = lpc32xx_init_irq,
371 .timer = &lpc32xx_timer, 325 .timer = &lpc32xx_timer,
372 .init_machine = phy3250_board_init, 326 .init_machine = lpc3250_machine_init,
327 .dt_compat = lpc32xx_dt_compat,
373 .restart = lpc23xx_restart, 328 .restart = lpc23xx_restart,
374MACHINE_END 329MACHINE_END