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-rw-r--r--arch/arm/mach-lpc32xx/include/mach/board.h24
-rw-r--r--arch/arm/mach-lpc32xx/include/mach/debug-macro.S2
-rw-r--r--arch/arm/mach-lpc32xx/include/mach/entry-macro.S6
-rw-r--r--arch/arm/mach-lpc32xx/include/mach/gpio-lpc32xx.h50
-rw-r--r--arch/arm/mach-lpc32xx/include/mach/gpio.h76
-rw-r--r--arch/arm/mach-lpc32xx/include/mach/hardware.h2
-rw-r--r--arch/arm/mach-lpc32xx/include/mach/irqs.h2
-rw-r--r--arch/arm/mach-lpc32xx/include/mach/platform.h66
8 files changed, 105 insertions, 123 deletions
diff --git a/arch/arm/mach-lpc32xx/include/mach/board.h b/arch/arm/mach-lpc32xx/include/mach/board.h
deleted file mode 100644
index 52531ca7bd1..00000000000
--- a/arch/arm/mach-lpc32xx/include/mach/board.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * arm/arch/mach-lpc32xx/include/mach/board.h
3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 *
6 * Copyright (C) 2010 NXP Semiconductors
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#ifndef __ASM_ARCH_BOARD_H
20#define __ASM_ARCH_BOARD_H
21
22extern u32 lpc32xx_return_iram_size(void);
23
24#endif /* __ASM_ARCH_BOARD_H */
diff --git a/arch/arm/mach-lpc32xx/include/mach/debug-macro.S b/arch/arm/mach-lpc32xx/include/mach/debug-macro.S
index 351bd6c8490..629e744aeb9 100644
--- a/arch/arm/mach-lpc32xx/include/mach/debug-macro.S
+++ b/arch/arm/mach-lpc32xx/include/mach/debug-macro.S
@@ -20,7 +20,7 @@
20 * Debug output is hardcoded to standard UART 5 20 * Debug output is hardcoded to standard UART 5
21*/ 21*/
22 22
23 .macro addruart, rp, rv, tmp 23 .macro addruart, rp, rv
24 ldreq \rp, =0x40090000 24 ldreq \rp, =0x40090000
25 ldrne \rv, =0xF4090000 25 ldrne \rv, =0xF4090000
26 .endm 26 .endm
diff --git a/arch/arm/mach-lpc32xx/include/mach/entry-macro.S b/arch/arm/mach-lpc32xx/include/mach/entry-macro.S
index 24ca11b377c..b725f6c9397 100644
--- a/arch/arm/mach-lpc32xx/include/mach/entry-macro.S
+++ b/arch/arm/mach-lpc32xx/include/mach/entry-macro.S
@@ -21,10 +21,16 @@
21 21
22#define LPC32XX_INTC_MASKED_STATUS_OFS 0x8 22#define LPC32XX_INTC_MASKED_STATUS_OFS 0x8
23 23
24 .macro disable_fiq
25 .endm
26
24 .macro get_irqnr_preamble, base, tmp 27 .macro get_irqnr_preamble, base, tmp
25 ldr \base, =IO_ADDRESS(LPC32XX_MIC_BASE) 28 ldr \base, =IO_ADDRESS(LPC32XX_MIC_BASE)
26 .endm 29 .endm
27 30
31 .macro arch_ret_to_user, tmp1, tmp2
32 .endm
33
28/* 34/*
29 * Return IRQ number in irqnr. Also return processor Z flag status in CPSR 35 * Return IRQ number in irqnr. Also return processor Z flag status in CPSR
30 * as set if an interrupt is pending. 36 * as set if an interrupt is pending.
diff --git a/arch/arm/mach-lpc32xx/include/mach/gpio-lpc32xx.h b/arch/arm/mach-lpc32xx/include/mach/gpio-lpc32xx.h
deleted file mode 100644
index a544e962a81..00000000000
--- a/arch/arm/mach-lpc32xx/include/mach/gpio-lpc32xx.h
+++ /dev/null
@@ -1,50 +0,0 @@
1/*
2 * Author: Kevin Wells <kevin.wells@nxp.com>
3 *
4 * Copyright (C) 2010 NXP Semiconductors
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#ifndef __MACH_GPIO_LPC32XX_H
18#define __MACH_GPIO_LPC32XX_H
19
20/*
21 * Note!
22 * Muxed GP pins need to be setup to the GP state in the board level
23 * code prior to using this driver.
24 * GPI pins : 28xP3 group
25 * GPO pins : 24xP3 group
26 * GPIO pins: 8xP0 group, 24xP1 group, 13xP2 group, 6xP3 group
27 */
28
29#define LPC32XX_GPIO_P0_MAX 8
30#define LPC32XX_GPIO_P1_MAX 24
31#define LPC32XX_GPIO_P2_MAX 13
32#define LPC32XX_GPIO_P3_MAX 6
33#define LPC32XX_GPI_P3_MAX 29
34#define LPC32XX_GPO_P3_MAX 24
35
36#define LPC32XX_GPIO_P0_GRP 0
37#define LPC32XX_GPIO_P1_GRP (LPC32XX_GPIO_P0_GRP + LPC32XX_GPIO_P0_MAX)
38#define LPC32XX_GPIO_P2_GRP (LPC32XX_GPIO_P1_GRP + LPC32XX_GPIO_P1_MAX)
39#define LPC32XX_GPIO_P3_GRP (LPC32XX_GPIO_P2_GRP + LPC32XX_GPIO_P2_MAX)
40#define LPC32XX_GPI_P3_GRP (LPC32XX_GPIO_P3_GRP + LPC32XX_GPIO_P3_MAX)
41#define LPC32XX_GPO_P3_GRP (LPC32XX_GPI_P3_GRP + LPC32XX_GPI_P3_MAX)
42
43/*
44 * A specific GPIO can be selected with this macro
45 * ie, GPIO_05 can be selected with LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5)
46 * See the LPC32x0 User's guide for GPIO group numbers
47 */
48#define LPC32XX_GPIO(x, y) ((x) + (y))
49
50#endif /* __MACH_GPIO_LPC32XX_H */
diff --git a/arch/arm/mach-lpc32xx/include/mach/gpio.h b/arch/arm/mach-lpc32xx/include/mach/gpio.h
index 0052e7a7617..67d03da1eee 100644
--- a/arch/arm/mach-lpc32xx/include/mach/gpio.h
+++ b/arch/arm/mach-lpc32xx/include/mach/gpio.h
@@ -1,6 +1,74 @@
1#ifndef __MACH_GPIO_H 1/*
2#define __MACH_GPIO_H 2 * arch/arm/mach-lpc32xx/include/mach/gpio.h
3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 *
6 * Copyright (C) 2010 NXP Semiconductors
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
3 18
4#include "gpio-lpc32xx.h" 19#ifndef __ASM_ARCH_GPIO_H
20#define __ASM_ARCH_GPIO_H
5 21
6#endif /* __MACH_GPIO_H */ 22#include <asm-generic/gpio.h>
23
24/*
25 * Note!
26 * Muxed GP pins need to be setup to the GP state in the board level
27 * code prior to using this driver.
28 * GPI pins : 28xP3 group
29 * GPO pins : 24xP3 group
30 * GPIO pins: 8xP0 group, 24xP1 group, 13xP2 group, 6xP3 group
31 */
32
33#define LPC32XX_GPIO_P0_MAX 8
34#define LPC32XX_GPIO_P1_MAX 24
35#define LPC32XX_GPIO_P2_MAX 13
36#define LPC32XX_GPIO_P3_MAX 6
37#define LPC32XX_GPI_P3_MAX 28
38#define LPC32XX_GPO_P3_MAX 24
39
40#define LPC32XX_GPIO_P0_GRP 0
41#define LPC32XX_GPIO_P1_GRP (LPC32XX_GPIO_P0_GRP + LPC32XX_GPIO_P0_MAX)
42#define LPC32XX_GPIO_P2_GRP (LPC32XX_GPIO_P1_GRP + LPC32XX_GPIO_P1_MAX)
43#define LPC32XX_GPIO_P3_GRP (LPC32XX_GPIO_P2_GRP + LPC32XX_GPIO_P2_MAX)
44#define LPC32XX_GPI_P3_GRP (LPC32XX_GPIO_P3_GRP + LPC32XX_GPIO_P3_MAX)
45#define LPC32XX_GPO_P3_GRP (LPC32XX_GPI_P3_GRP + LPC32XX_GPI_P3_MAX)
46
47/*
48 * A specific GPIO can be selected with this macro
49 * ie, GPIO_05 can be selected with LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5)
50 * See the LPC32x0 User's guide for GPIO group numbers
51 */
52#define LPC32XX_GPIO(x, y) ((x) + (y))
53
54static inline int gpio_get_value(unsigned gpio)
55{
56 return __gpio_get_value(gpio);
57}
58
59static inline void gpio_set_value(unsigned gpio, int value)
60{
61 __gpio_set_value(gpio, value);
62}
63
64static inline int gpio_cansleep(unsigned gpio)
65{
66 return __gpio_cansleep(gpio);
67}
68
69static inline int gpio_to_irq(unsigned gpio)
70{
71 return __gpio_to_irq(gpio);
72}
73
74#endif
diff --git a/arch/arm/mach-lpc32xx/include/mach/hardware.h b/arch/arm/mach-lpc32xx/include/mach/hardware.h
index 69065de97a3..33e1dde37bd 100644
--- a/arch/arm/mach-lpc32xx/include/mach/hardware.h
+++ b/arch/arm/mach-lpc32xx/include/mach/hardware.h
@@ -25,7 +25,7 @@
25/* 25/*
26 * This macro relies on fact that for all HW i/o addresses bits 20-23 are 0 26 * This macro relies on fact that for all HW i/o addresses bits 20-23 are 0
27 */ 27 */
28#define IO_ADDRESS(x) IOMEM(((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) |\ 28#define IO_ADDRESS(x) (((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) |\
29 IO_BASE) 29 IO_BASE)
30 30
31#define io_p2v(x) ((void __iomem *) (unsigned long) IO_ADDRESS(x)) 31#define io_p2v(x) ((void __iomem *) (unsigned long) IO_ADDRESS(x))
diff --git a/arch/arm/mach-lpc32xx/include/mach/irqs.h b/arch/arm/mach-lpc32xx/include/mach/irqs.h
index 9e3b90df32e..2667f52e3b0 100644
--- a/arch/arm/mach-lpc32xx/include/mach/irqs.h
+++ b/arch/arm/mach-lpc32xx/include/mach/irqs.h
@@ -61,7 +61,7 @@
61 */ 61 */
62#define IRQ_LPC32XX_JTAG_COMM_TX LPC32XX_SIC1_IRQ(1) 62#define IRQ_LPC32XX_JTAG_COMM_TX LPC32XX_SIC1_IRQ(1)
63#define IRQ_LPC32XX_JTAG_COMM_RX LPC32XX_SIC1_IRQ(2) 63#define IRQ_LPC32XX_JTAG_COMM_RX LPC32XX_SIC1_IRQ(2)
64#define IRQ_LPC32XX_GPI_28 LPC32XX_SIC1_IRQ(4) 64#define IRQ_LPC32XX_GPI_11 LPC32XX_SIC1_IRQ(4)
65#define IRQ_LPC32XX_TS_P LPC32XX_SIC1_IRQ(6) 65#define IRQ_LPC32XX_TS_P LPC32XX_SIC1_IRQ(6)
66#define IRQ_LPC32XX_TS_IRQ LPC32XX_SIC1_IRQ(7) 66#define IRQ_LPC32XX_TS_IRQ LPC32XX_SIC1_IRQ(7)
67#define IRQ_LPC32XX_TS_AUX LPC32XX_SIC1_IRQ(8) 67#define IRQ_LPC32XX_TS_AUX LPC32XX_SIC1_IRQ(8)
diff --git a/arch/arm/mach-lpc32xx/include/mach/platform.h b/arch/arm/mach-lpc32xx/include/mach/platform.h
index b5612a1d183..14ea8d1aadb 100644
--- a/arch/arm/mach-lpc32xx/include/mach/platform.h
+++ b/arch/arm/mach-lpc32xx/include/mach/platform.h
@@ -515,7 +515,6 @@
515/* 515/*
516 * clkpwr_timers_pwms_clk_ctrl_1 register definitions 516 * clkpwr_timers_pwms_clk_ctrl_1 register definitions
517 */ 517 */
518#define LPC32XX_CLKPWR_TMRPWMCLK_MPWM_EN 0x40
519#define LPC32XX_CLKPWR_TMRPWMCLK_TIMER3_EN 0x20 518#define LPC32XX_CLKPWR_TMRPWMCLK_TIMER3_EN 0x20
520#define LPC32XX_CLKPWR_TMRPWMCLK_TIMER2_EN 0x10 519#define LPC32XX_CLKPWR_TMRPWMCLK_TIMER2_EN 0x10
521#define LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN 0x08 520#define LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN 0x08
@@ -592,42 +591,42 @@
592/* 591/*
593 * Timer/counter register offsets 592 * Timer/counter register offsets
594 */ 593 */
595#define LPC32XX_TIMER_IR(x) io_p2v((x) + 0x00) 594#define LCP32XX_TIMER_IR(x) io_p2v((x) + 0x00)
596#define LPC32XX_TIMER_TCR(x) io_p2v((x) + 0x04) 595#define LCP32XX_TIMER_TCR(x) io_p2v((x) + 0x04)
597#define LPC32XX_TIMER_TC(x) io_p2v((x) + 0x08) 596#define LCP32XX_TIMER_TC(x) io_p2v((x) + 0x08)
598#define LPC32XX_TIMER_PR(x) io_p2v((x) + 0x0C) 597#define LCP32XX_TIMER_PR(x) io_p2v((x) + 0x0C)
599#define LPC32XX_TIMER_PC(x) io_p2v((x) + 0x10) 598#define LCP32XX_TIMER_PC(x) io_p2v((x) + 0x10)
600#define LPC32XX_TIMER_MCR(x) io_p2v((x) + 0x14) 599#define LCP32XX_TIMER_MCR(x) io_p2v((x) + 0x14)
601#define LPC32XX_TIMER_MR0(x) io_p2v((x) + 0x18) 600#define LCP32XX_TIMER_MR0(x) io_p2v((x) + 0x18)
602#define LPC32XX_TIMER_MR1(x) io_p2v((x) + 0x1C) 601#define LCP32XX_TIMER_MR1(x) io_p2v((x) + 0x1C)
603#define LPC32XX_TIMER_MR2(x) io_p2v((x) + 0x20) 602#define LCP32XX_TIMER_MR2(x) io_p2v((x) + 0x20)
604#define LPC32XX_TIMER_MR3(x) io_p2v((x) + 0x24) 603#define LCP32XX_TIMER_MR3(x) io_p2v((x) + 0x24)
605#define LPC32XX_TIMER_CCR(x) io_p2v((x) + 0x28) 604#define LCP32XX_TIMER_CCR(x) io_p2v((x) + 0x28)
606#define LPC32XX_TIMER_CR0(x) io_p2v((x) + 0x2C) 605#define LCP32XX_TIMER_CR0(x) io_p2v((x) + 0x2C)
607#define LPC32XX_TIMER_CR1(x) io_p2v((x) + 0x30) 606#define LCP32XX_TIMER_CR1(x) io_p2v((x) + 0x30)
608#define LPC32XX_TIMER_CR2(x) io_p2v((x) + 0x34) 607#define LCP32XX_TIMER_CR2(x) io_p2v((x) + 0x34)
609#define LPC32XX_TIMER_CR3(x) io_p2v((x) + 0x38) 608#define LCP32XX_TIMER_CR3(x) io_p2v((x) + 0x38)
610#define LPC32XX_TIMER_EMR(x) io_p2v((x) + 0x3C) 609#define LCP32XX_TIMER_EMR(x) io_p2v((x) + 0x3C)
611#define LPC32XX_TIMER_CTCR(x) io_p2v((x) + 0x70) 610#define LCP32XX_TIMER_CTCR(x) io_p2v((x) + 0x70)
612 611
613/* 612/*
614 * ir register definitions 613 * ir register definitions
615 */ 614 */
616#define LPC32XX_TIMER_CNTR_MTCH_BIT(n) (1 << ((n) & 0x3)) 615#define LCP32XX_TIMER_CNTR_MTCH_BIT(n) (1 << ((n) & 0x3))
617#define LPC32XX_TIMER_CNTR_CAPT_BIT(n) (1 << (4 + ((n) & 0x3))) 616#define LCP32XX_TIMER_CNTR_CAPT_BIT(n) (1 << (4 + ((n) & 0x3)))
618 617
619/* 618/*
620 * tcr register definitions 619 * tcr register definitions
621 */ 620 */
622#define LPC32XX_TIMER_CNTR_TCR_EN 0x1 621#define LCP32XX_TIMER_CNTR_TCR_EN 0x1
623#define LPC32XX_TIMER_CNTR_TCR_RESET 0x2 622#define LCP32XX_TIMER_CNTR_TCR_RESET 0x2
624 623
625/* 624/*
626 * mcr register definitions 625 * mcr register definitions
627 */ 626 */
628#define LPC32XX_TIMER_CNTR_MCR_MTCH(n) (0x1 << ((n) * 3)) 627#define LCP32XX_TIMER_CNTR_MCR_MTCH(n) (0x1 << ((n) * 3))
629#define LPC32XX_TIMER_CNTR_MCR_RESET(n) (0x1 << (((n) * 3) + 1)) 628#define LCP32XX_TIMER_CNTR_MCR_RESET(n) (0x1 << (((n) * 3) + 1))
630#define LPC32XX_TIMER_CNTR_MCR_STOP(n) (0x1 << (((n) * 3) + 2)) 629#define LCP32XX_TIMER_CNTR_MCR_STOP(n) (0x1 << (((n) * 3) + 2))
631 630
632/* 631/*
633 * Standard UART register offsets 632 * Standard UART register offsets
@@ -691,22 +690,5 @@
691#define LPC32XX_GPIO_P1_MUX_SET _GPREG(0x130) 690#define LPC32XX_GPIO_P1_MUX_SET _GPREG(0x130)
692#define LPC32XX_GPIO_P1_MUX_CLR _GPREG(0x134) 691#define LPC32XX_GPIO_P1_MUX_CLR _GPREG(0x134)
693#define LPC32XX_GPIO_P1_MUX_STATE _GPREG(0x138) 692#define LPC32XX_GPIO_P1_MUX_STATE _GPREG(0x138)
694#define LPC32XX_GPIO_P2_MUX_SET _GPREG(0x028)
695#define LPC32XX_GPIO_P2_MUX_CLR _GPREG(0x02C)
696#define LPC32XX_GPIO_P2_MUX_STATE _GPREG(0x030)
697
698/*
699 * USB Otg Registers
700 */
701#define _OTGREG(x) io_p2v(LPC32XX_USB_OTG_BASE + (x))
702#define LPC32XX_USB_OTG_CLK_CTRL _OTGREG(0xFF4)
703#define LPC32XX_USB_OTG_CLK_STAT _OTGREG(0xFF8)
704
705/* USB OTG CLK CTRL bit defines */
706#define LPC32XX_USB_OTG_AHB_M_CLOCK_ON _BIT(4)
707#define LPC32XX_USB_OTG_OTG_CLOCK_ON _BIT(3)
708#define LPC32XX_USB_OTG_I2C_CLOCK_ON _BIT(2)
709#define LPC32XX_USB_OTG_DEV_CLOCK_ON _BIT(1)
710#define LPC32XX_USB_OTG_HOST_CLOCK_ON _BIT(0)
711 693
712#endif 694#endif
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-10 06:06:18 -0500