Patched in Tegra support.

8 files changed, 105 insertions, 123 deletions

diff --git a/arch/arm/mach-lpc32xx/include/mach/board.h b/arch/arm/mach-lpc32xx/include/mach/board.h
deleted file mode 100644
index 52531ca7bd1..00000000000
--- a/arch/arm/mach-lpc32xx/include/mach/board.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * arm/arch/mach-lpc32xx/include/mach/board.h
- *
- * Author: Kevin Wells <kevin.wells@nxp.com>
- *
- * Copyright (C) 2010 NXP Semiconductors
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __ASM_ARCH_BOARD_H
-#define __ASM_ARCH_BOARD_H
-
-extern u32 lpc32xx_return_iram_size(void);
-
-#endif  /* __ASM_ARCH_BOARD_H */
diff --git a/arch/arm/mach-lpc32xx/include/mach/debug-macro.S b/arch/arm/mach-lpc32xx/include/mach/debug-macro.S
index 351bd6c8490..629e744aeb9 100644
--- a/arch/arm/mach-lpc32xx/include/mach/debug-macro.S
+++ b/arch/arm/mach-lpc32xx/include/mach/debug-macro.S
@@ -20,7 +20,7 @@
  * Debug output is hardcoded to standard UART 5
 */
 
-        .macro  addruart, rp, rv, tmp
+        .macro  addruart, rp, rv
         ldreq   \rp, =0x40090000
         ldrne   \rv, =0xF4090000
         .endm
diff --git a/arch/arm/mach-lpc32xx/include/mach/entry-macro.S b/arch/arm/mach-lpc32xx/include/mach/entry-macro.S
index 24ca11b377c..b725f6c9397 100644
--- a/arch/arm/mach-lpc32xx/include/mach/entry-macro.S
+++ b/arch/arm/mach-lpc32xx/include/mach/entry-macro.S
@@ -21,10 +21,16 @@
 
 #define LPC32XX_INTC_MASKED_STATUS_OFS  0x8
 
+        .macro  disable_fiq
+        .endm
+
         .macro  get_irqnr_preamble, base, tmp
         ldr     \base, =IO_ADDRESS(LPC32XX_MIC_BASE)
         .endm
 
+        .macro  arch_ret_to_user, tmp1, tmp2
+        .endm
+
 /*
  * Return IRQ number in irqnr. Also return processor Z flag status in CPSR
  * as set if an interrupt is pending.
diff --git a/arch/arm/mach-lpc32xx/include/mach/gpio-lpc32xx.h b/arch/arm/mach-lpc32xx/include/mach/gpio-lpc32xx.h
deleted file mode 100644
index a544e962a81..00000000000
--- a/arch/arm/mach-lpc32xx/include/mach/gpio-lpc32xx.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * Author: Kevin Wells <kevin.wells@nxp.com>
- *
- * Copyright (C) 2010 NXP Semiconductors
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __MACH_GPIO_LPC32XX_H
-#define __MACH_GPIO_LPC32XX_H
-
-/*
- * Note!
- * Muxed GP pins need to be setup to the GP state in the board level
- * code prior to using this driver.
- * GPI pins : 28xP3 group
- * GPO pins : 24xP3 group
- * GPIO pins: 8xP0 group, 24xP1 group, 13xP2 group, 6xP3 group
- */
-
-#define LPC32XX_GPIO_P0_MAX 8
-#define LPC32XX_GPIO_P1_MAX 24
-#define LPC32XX_GPIO_P2_MAX 13
-#define LPC32XX_GPIO_P3_MAX 6
-#define LPC32XX_GPI_P3_MAX 29
-#define LPC32XX_GPO_P3_MAX 24
-
-#define LPC32XX_GPIO_P0_GRP 0
-#define LPC32XX_GPIO_P1_GRP (LPC32XX_GPIO_P0_GRP + LPC32XX_GPIO_P0_MAX)
-#define LPC32XX_GPIO_P2_GRP (LPC32XX_GPIO_P1_GRP + LPC32XX_GPIO_P1_MAX)
-#define LPC32XX_GPIO_P3_GRP (LPC32XX_GPIO_P2_GRP + LPC32XX_GPIO_P2_MAX)
-#define LPC32XX_GPI_P3_GRP (LPC32XX_GPIO_P3_GRP + LPC32XX_GPIO_P3_MAX)
-#define LPC32XX_GPO_P3_GRP (LPC32XX_GPI_P3_GRP + LPC32XX_GPI_P3_MAX)
-
-/*
- * A specific GPIO can be selected with this macro
- * ie, GPIO_05 can be selected with LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5)
- * See the LPC32x0 User's guide for GPIO group numbers
- */
-#define LPC32XX_GPIO(x, y) ((x) + (y))
-
-#endif /* __MACH_GPIO_LPC32XX_H */
diff --git a/arch/arm/mach-lpc32xx/include/mach/gpio.h b/arch/arm/mach-lpc32xx/include/mach/gpio.h
index 0052e7a7617..67d03da1eee 100644
--- a/arch/arm/mach-lpc32xx/include/mach/gpio.h
+++ b/arch/arm/mach-lpc32xx/include/mach/gpio.h
@@ -1,6 +1,74 @@
-#ifndef __MACH_GPIO_H
-#define __MACH_GPIO_H
+/*
+ * arch/arm/mach-lpc32xx/include/mach/gpio.h
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
 
-#include "gpio-lpc32xx.h"
+#ifndef __ASM_ARCH_GPIO_H
+#define __ASM_ARCH_GPIO_H
 
-#endif /* __MACH_GPIO_H */
+#include <asm-generic/gpio.h>
+
+/*
+ * Note!
+ * Muxed GP pins need to be setup to the GP state in the board level
+ * code prior to using this driver.
+ * GPI pins : 28xP3 group
+ * GPO pins : 24xP3 group
+ * GPIO pins: 8xP0 group, 24xP1 group, 13xP2 group, 6xP3 group
+ */
+
+#define LPC32XX_GPIO_P0_MAX 8
+#define LPC32XX_GPIO_P1_MAX 24
+#define LPC32XX_GPIO_P2_MAX 13
+#define LPC32XX_GPIO_P3_MAX 6
+#define LPC32XX_GPI_P3_MAX 28
+#define LPC32XX_GPO_P3_MAX 24
+
+#define LPC32XX_GPIO_P0_GRP 0
+#define LPC32XX_GPIO_P1_GRP (LPC32XX_GPIO_P0_GRP + LPC32XX_GPIO_P0_MAX)
+#define LPC32XX_GPIO_P2_GRP (LPC32XX_GPIO_P1_GRP + LPC32XX_GPIO_P1_MAX)
+#define LPC32XX_GPIO_P3_GRP (LPC32XX_GPIO_P2_GRP + LPC32XX_GPIO_P2_MAX)
+#define LPC32XX_GPI_P3_GRP (LPC32XX_GPIO_P3_GRP + LPC32XX_GPIO_P3_MAX)
+#define LPC32XX_GPO_P3_GRP (LPC32XX_GPI_P3_GRP + LPC32XX_GPI_P3_MAX)
+
+/*
+ * A specific GPIO can be selected with this macro
+ * ie, GPIO_05 can be selected with LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5)
+ * See the LPC32x0 User's guide for GPIO group numbers
+ */
+#define LPC32XX_GPIO(x, y) ((x) + (y))
+
+static inline int gpio_get_value(unsigned gpio)
+{
+        return __gpio_get_value(gpio);
+}
+
+static inline void gpio_set_value(unsigned gpio, int value)
+{
+        __gpio_set_value(gpio, value);
+}
+
+static inline int gpio_cansleep(unsigned gpio)
+{
+        return __gpio_cansleep(gpio);
+}
+
+static inline int gpio_to_irq(unsigned gpio)
+{
+        return __gpio_to_irq(gpio);
+}
+
+#endif
diff --git a/arch/arm/mach-lpc32xx/include/mach/hardware.h b/arch/arm/mach-lpc32xx/include/mach/hardware.h
index 69065de97a3..33e1dde37bd 100644
--- a/arch/arm/mach-lpc32xx/include/mach/hardware.h
+++ b/arch/arm/mach-lpc32xx/include/mach/hardware.h
@@ -25,7 +25,7 @@
 /*
  * This macro relies on fact that for all HW i/o addresses bits 20-23 are 0
  */
-#define IO_ADDRESS(x)   IOMEM(((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) |\
+#define IO_ADDRESS(x)   (((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) |\
                          IO_BASE)
 
 #define io_p2v(x)       ((void __iomem *) (unsigned long) IO_ADDRESS(x))
diff --git a/arch/arm/mach-lpc32xx/include/mach/irqs.h b/arch/arm/mach-lpc32xx/include/mach/irqs.h
index 9e3b90df32e..2667f52e3b0 100644
--- a/arch/arm/mach-lpc32xx/include/mach/irqs.h
+++ b/arch/arm/mach-lpc32xx/include/mach/irqs.h
@@ -61,7 +61,7 @@
  */
 #define IRQ_LPC32XX_JTAG_COMM_TX        LPC32XX_SIC1_IRQ(1)
 #define IRQ_LPC32XX_JTAG_COMM_RX        LPC32XX_SIC1_IRQ(2)
-#define IRQ_LPC32XX_GPI_28              LPC32XX_SIC1_IRQ(4)
+#define IRQ_LPC32XX_GPI_11              LPC32XX_SIC1_IRQ(4)
 #define IRQ_LPC32XX_TS_P                LPC32XX_SIC1_IRQ(6)
 #define IRQ_LPC32XX_TS_IRQ              LPC32XX_SIC1_IRQ(7)
 #define IRQ_LPC32XX_TS_AUX              LPC32XX_SIC1_IRQ(8)
diff --git a/arch/arm/mach-lpc32xx/include/mach/platform.h b/arch/arm/mach-lpc32xx/include/mach/platform.h
index b5612a1d183..14ea8d1aadb 100644
--- a/arch/arm/mach-lpc32xx/include/mach/platform.h
+++ b/arch/arm/mach-lpc32xx/include/mach/platform.h
@@ -515,7 +515,6 @@
 /*
  * clkpwr_timers_pwms_clk_ctrl_1 register definitions
  */
-#define LPC32XX_CLKPWR_TMRPWMCLK_MPWM_EN        0x40
 #define LPC32XX_CLKPWR_TMRPWMCLK_TIMER3_EN      0x20
 #define LPC32XX_CLKPWR_TMRPWMCLK_TIMER2_EN      0x10
 #define LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN      0x08
@@ -592,42 +591,42 @@
 /*
  * Timer/counter register offsets
  */
-#define LPC32XX_TIMER_IR(x)                     io_p2v((x) + 0x00)
-#define LPC32XX_TIMER_TCR(x)                    io_p2v((x) + 0x04)
-#define LPC32XX_TIMER_TC(x)                     io_p2v((x) + 0x08)
-#define LPC32XX_TIMER_PR(x)                     io_p2v((x) + 0x0C)
-#define LPC32XX_TIMER_PC(x)                     io_p2v((x) + 0x10)
-#define LPC32XX_TIMER_MCR(x)                    io_p2v((x) + 0x14)
-#define LPC32XX_TIMER_MR0(x)                    io_p2v((x) + 0x18)
-#define LPC32XX_TIMER_MR1(x)                    io_p2v((x) + 0x1C)
-#define LPC32XX_TIMER_MR2(x)                    io_p2v((x) + 0x20)
-#define LPC32XX_TIMER_MR3(x)                    io_p2v((x) + 0x24)
-#define LPC32XX_TIMER_CCR(x)                    io_p2v((x) + 0x28)
-#define LPC32XX_TIMER_CR0(x)                    io_p2v((x) + 0x2C)
-#define LPC32XX_TIMER_CR1(x)                    io_p2v((x) + 0x30)
-#define LPC32XX_TIMER_CR2(x)                    io_p2v((x) + 0x34)
-#define LPC32XX_TIMER_CR3(x)                    io_p2v((x) + 0x38)
-#define LPC32XX_TIMER_EMR(x)                    io_p2v((x) + 0x3C)
-#define LPC32XX_TIMER_CTCR(x)                   io_p2v((x) + 0x70)
+#define LCP32XX_TIMER_IR(x)                     io_p2v((x) + 0x00)
+#define LCP32XX_TIMER_TCR(x)                    io_p2v((x) + 0x04)
+#define LCP32XX_TIMER_TC(x)                     io_p2v((x) + 0x08)
+#define LCP32XX_TIMER_PR(x)                     io_p2v((x) + 0x0C)
+#define LCP32XX_TIMER_PC(x)                     io_p2v((x) + 0x10)
+#define LCP32XX_TIMER_MCR(x)                    io_p2v((x) + 0x14)
+#define LCP32XX_TIMER_MR0(x)                    io_p2v((x) + 0x18)
+#define LCP32XX_TIMER_MR1(x)                    io_p2v((x) + 0x1C)
+#define LCP32XX_TIMER_MR2(x)                    io_p2v((x) + 0x20)
+#define LCP32XX_TIMER_MR3(x)                    io_p2v((x) + 0x24)
+#define LCP32XX_TIMER_CCR(x)                    io_p2v((x) + 0x28)
+#define LCP32XX_TIMER_CR0(x)                    io_p2v((x) + 0x2C)
+#define LCP32XX_TIMER_CR1(x)                    io_p2v((x) + 0x30)
+#define LCP32XX_TIMER_CR2(x)                    io_p2v((x) + 0x34)
+#define LCP32XX_TIMER_CR3(x)                    io_p2v((x) + 0x38)
+#define LCP32XX_TIMER_EMR(x)                    io_p2v((x) + 0x3C)
+#define LCP32XX_TIMER_CTCR(x)                   io_p2v((x) + 0x70)
 
 /*
  * ir register definitions
  */
-#define LPC32XX_TIMER_CNTR_MTCH_BIT(n)          (1 << ((n) & 0x3))
-#define LPC32XX_TIMER_CNTR_CAPT_BIT(n)          (1 << (4 + ((n) & 0x3)))
+#define LCP32XX_TIMER_CNTR_MTCH_BIT(n)          (1 << ((n) & 0x3))
+#define LCP32XX_TIMER_CNTR_CAPT_BIT(n)          (1 << (4 + ((n) & 0x3)))
 
 /*
  * tcr register definitions
  */
-#define LPC32XX_TIMER_CNTR_TCR_EN               0x1
-#define LPC32XX_TIMER_CNTR_TCR_RESET            0x2
+#define LCP32XX_TIMER_CNTR_TCR_EN               0x1
+#define LCP32XX_TIMER_CNTR_TCR_RESET            0x2
 
 /*
  * mcr register definitions
  */
-#define LPC32XX_TIMER_CNTR_MCR_MTCH(n)          (0x1 << ((n) * 3))
-#define LPC32XX_TIMER_CNTR_MCR_RESET(n)         (0x1 << (((n) * 3) + 1))
-#define LPC32XX_TIMER_CNTR_MCR_STOP(n)          (0x1 << (((n) * 3) + 2))
+#define LCP32XX_TIMER_CNTR_MCR_MTCH(n)          (0x1 << ((n) * 3))
+#define LCP32XX_TIMER_CNTR_MCR_RESET(n)         (0x1 << (((n) * 3) + 1))
+#define LCP32XX_TIMER_CNTR_MCR_STOP(n)          (0x1 << (((n) * 3) + 2))
 
 /*
  * Standard UART register offsets
@@ -691,22 +690,5 @@
 #define LPC32XX_GPIO_P1_MUX_SET                 _GPREG(0x130)
 #define LPC32XX_GPIO_P1_MUX_CLR                 _GPREG(0x134)
 #define LPC32XX_GPIO_P1_MUX_STATE               _GPREG(0x138)
-#define LPC32XX_GPIO_P2_MUX_SET                 _GPREG(0x028)
-#define LPC32XX_GPIO_P2_MUX_CLR                 _GPREG(0x02C)
-#define LPC32XX_GPIO_P2_MUX_STATE               _GPREG(0x030)
-
-/*
- * USB Otg Registers
- */
-#define _OTGREG(x)                      io_p2v(LPC32XX_USB_OTG_BASE + (x))
-#define LPC32XX_USB_OTG_CLK_CTRL        _OTGREG(0xFF4)
-#define LPC32XX_USB_OTG_CLK_STAT        _OTGREG(0xFF8)
-
-/* USB OTG CLK CTRL bit defines */
-#define LPC32XX_USB_OTG_AHB_M_CLOCK_ON  _BIT(4)
-#define LPC32XX_USB_OTG_OTG_CLOCK_ON    _BIT(3)
-#define LPC32XX_USB_OTG_I2C_CLOCK_ON    _BIT(2)
-#define LPC32XX_USB_OTG_DEV_CLOCK_ON    _BIT(1)
-#define LPC32XX_USB_OTG_HOST_CLOCK_ON   _BIT(0)
 
 #endif