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Diffstat (limited to 'arch/arm/mach-iop13xx/include/mach/iop13xx.h')
-rw-r--r--arch/arm/mach-iop13xx/include/mach/iop13xx.h28
1 files changed, 3 insertions, 25 deletions
diff --git a/arch/arm/mach-iop13xx/include/mach/iop13xx.h b/arch/arm/mach-iop13xx/include/mach/iop13xx.h
index e190dcd7d72..e10e101645d 100644
--- a/arch/arm/mach-iop13xx/include/mach/iop13xx.h
+++ b/arch/arm/mach-iop13xx/include/mach/iop13xx.h
@@ -69,21 +69,11 @@ extern unsigned long get_iop_tick_rate(void);
69 * 0x8000.0000 + 928M 0x2.8000.0000 (ioremap) PCIE outbound memory window 69 * 0x8000.0000 + 928M 0x2.8000.0000 (ioremap) PCIE outbound memory window
70 * 70 *
71 * IO MAP 71 * IO MAP
72 * 0x1000 + 64K 0x0.fffb.1000 0xfec6.1000 PCIX outbound i/o window 72 * 0x00000 + 64K 0x0.fffb.0000 0xfee0.0000 PCIX outbound i/o window
73 * 0x1000 + 64K 0x0.fffd.1000 0xfed7.1000 PCIE outbound i/o window 73 * 0x10000 + 64K 0x0.fffd.0000 0xfee1.0000 PCIE outbound i/o window
74 */ 74 */
75#define IOP13XX_PCIX_IO_WINDOW_SIZE 0x10000UL
76#define IOP13XX_PCIX_LOWER_IO_PA 0xfffb0000UL 75#define IOP13XX_PCIX_LOWER_IO_PA 0xfffb0000UL
77#define IOP13XX_PCIX_LOWER_IO_VA 0xfec60000UL
78#define IOP13XX_PCIX_LOWER_IO_BA 0x0UL /* OIOTVR */ 76#define IOP13XX_PCIX_LOWER_IO_BA 0x0UL /* OIOTVR */
79#define IOP13XX_PCIX_IO_BUS_OFFSET 0x1000UL
80#define IOP13XX_PCIX_UPPER_IO_PA (IOP13XX_PCIX_LOWER_IO_PA +\
81 IOP13XX_PCIX_IO_WINDOW_SIZE - 1)
82#define IOP13XX_PCIX_UPPER_IO_VA (IOP13XX_PCIX_LOWER_IO_VA +\
83 IOP13XX_PCIX_IO_WINDOW_SIZE - 1)
84#define IOP13XX_PCIX_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
85 (IOP13XX_PCIX_LOWER_IO_PA\
86 - IOP13XX_PCIX_LOWER_IO_VA))
87 77
88#define IOP13XX_PCIX_MEM_PHYS_OFFSET 0x100000000ULL 78#define IOP13XX_PCIX_MEM_PHYS_OFFSET 0x100000000ULL
89#define IOP13XX_PCIX_MEM_WINDOW_SIZE 0x3a000000UL 79#define IOP13XX_PCIX_MEM_WINDOW_SIZE 0x3a000000UL
@@ -103,20 +93,8 @@ extern unsigned long get_iop_tick_rate(void);
103 IOP13XX_PCIX_LOWER_MEM_BA) 93 IOP13XX_PCIX_LOWER_MEM_BA)
104 94
105/* PCI-E ranges */ 95/* PCI-E ranges */
106#define IOP13XX_PCIE_IO_WINDOW_SIZE 0x10000UL
107#define IOP13XX_PCIE_LOWER_IO_PA 0xfffd0000UL 96#define IOP13XX_PCIE_LOWER_IO_PA 0xfffd0000UL
108#define IOP13XX_PCIE_LOWER_IO_VA 0xfed70000UL 97#define IOP13XX_PCIE_LOWER_IO_BA 0x10000UL /* OIOTVR */
109#define IOP13XX_PCIE_LOWER_IO_BA 0x0UL /* OIOTVR */
110#define IOP13XX_PCIE_IO_BUS_OFFSET 0x1000UL
111#define IOP13XX_PCIE_UPPER_IO_PA (IOP13XX_PCIE_LOWER_IO_PA +\
112 IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
113#define IOP13XX_PCIE_UPPER_IO_VA (IOP13XX_PCIE_LOWER_IO_VA +\
114 IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
115#define IOP13XX_PCIE_UPPER_IO_BA (IOP13XX_PCIE_LOWER_IO_BA +\
116 IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
117#define IOP13XX_PCIE_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
118 (IOP13XX_PCIE_LOWER_IO_PA\
119 - IOP13XX_PCIE_LOWER_IO_VA))
120 98
121#define IOP13XX_PCIE_MEM_PHYS_OFFSET 0x200000000ULL 99#define IOP13XX_PCIE_MEM_PHYS_OFFSET 0x200000000ULL
122#define IOP13XX_PCIE_MEM_WINDOW_SIZE 0x3a000000UL 100#define IOP13XX_PCIE_MEM_WINDOW_SIZE 0x3a000000UL