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-rw-r--r--arch/arm/mach-imx/Makefile15
-rw-r--r--arch/arm/mach-imx/cache-l2x0.c56
-rw-r--r--arch/arm/mach-imx/mach-armadillo5x0.c18
-rw-r--r--arch/arm/mach-imx/mach-cpuimx35.c2
-rw-r--r--arch/arm/mach-imx/mach-mx1ads.c15
-rw-r--r--arch/arm/mach-imx/mach-mx27_3ds.c2
-rw-r--r--arch/arm/mach-imx/mach-vpr200.c2
-rw-r--r--arch/arm/mach-imx/mm-imx3.c256
-rw-r--r--arch/arm/mach-imx/mm-imx31.c91
-rw-r--r--arch/arm/mach-imx/mm-imx35.c109
-rw-r--r--arch/arm/mach-imx/pm-imx27.c2
11 files changed, 279 insertions, 289 deletions
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 0a5332c694b..116d4b2d281 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -1,16 +1,15 @@
1obj-$(CONFIG_IMX_HAVE_DMA_V1) += dma-v1.o 1obj-$(CONFIG_IMX_HAVE_DMA_V1) += dma-v1.o
2 2
3obj-$(CONFIG_ARCH_MX1) += clock-imx1.o mm-imx1.o 3obj-$(CONFIG_SOC_IMX1) += clock-imx1.o mm-imx1.o
4obj-$(CONFIG_MACH_MX21) += clock-imx21.o mm-imx21.o 4obj-$(CONFIG_SOC_IMX21) += clock-imx21.o mm-imx21.o
5 5
6obj-$(CONFIG_ARCH_MX25) += clock-imx25.o mm-imx25.o ehci-imx25.o cpu-imx25.o 6obj-$(CONFIG_SOC_IMX25) += clock-imx25.o mm-imx25.o ehci-imx25.o cpu-imx25.o
7 7
8obj-$(CONFIG_MACH_MX27) += cpu-imx27.o pm-imx27.o 8obj-$(CONFIG_SOC_IMX27) += cpu-imx27.o pm-imx27.o
9obj-$(CONFIG_MACH_MX27) += clock-imx27.o mm-imx27.o ehci-imx27.o 9obj-$(CONFIG_SOC_IMX27) += clock-imx27.o mm-imx27.o ehci-imx27.o
10 10
11obj-$(CONFIG_SOC_IMX31) += mm-imx31.o cpu-imx31.o clock-imx31.o iomux-imx31.o ehci-imx31.o 11obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clock-imx31.o iomux-imx31.o ehci-imx31.o
12obj-$(CONFIG_SOC_IMX35) += mm-imx35.o cpu-imx35.o clock-imx35.o ehci-imx35.o 12obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clock-imx35.o ehci-imx35.o
13obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o
14 13
15# Support for CMOS sensor interface 14# Support for CMOS sensor interface
16obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o 15obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o
diff --git a/arch/arm/mach-imx/cache-l2x0.c b/arch/arm/mach-imx/cache-l2x0.c
deleted file mode 100644
index e5538a4d7f2..00000000000
--- a/arch/arm/mach-imx/cache-l2x0.c
+++ /dev/null
@@ -1,56 +0,0 @@
1/*
2 * Copyright (C) 2009-2010 Pengutronix
3 * Sascha Hauer <s.hauer@pengutronix.de>
4 * Juergen Beisert <j.beisert@pengutronix.de>
5 *
6 * This program is free software; you can redistribute it and/or modify it under
7 * the terms of the GNU General Public License version 2 as published by the
8 * Free Software Foundation.
9 */
10
11#include <linux/init.h>
12#include <linux/err.h>
13#include <linux/kernel.h>
14
15#include <asm/hardware/cache-l2x0.h>
16
17#include <mach/hardware.h>
18
19static int mxc_init_l2x0(void)
20{
21 void __iomem *l2x0_base;
22 void __iomem *clkctl_base;
23
24 if (!cpu_is_mx31() && !cpu_is_mx35())
25 return 0;
26
27/*
28 * First of all, we must repair broken chip settings. There are some
29 * i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These
30 * misconfigured CPUs will run amok immediately when the L2 cache gets enabled.
31 * Workaraound is to setup the correct register setting prior enabling the
32 * L2 cache. This should not hurt already working CPUs, as they are using the
33 * same value.
34 */
35#define L2_MEM_VAL 0x10
36
37 clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096);
38 if (clkctl_base != NULL) {
39 writel(0x00000515, clkctl_base + L2_MEM_VAL);
40 iounmap(clkctl_base);
41 } else {
42 pr_err("L2 cache: Cannot fix timing. Trying to continue without\n");
43 }
44
45 l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096);
46 if (IS_ERR(l2x0_base)) {
47 printk(KERN_ERR "remapping L2 cache area failed with %ld\n",
48 PTR_ERR(l2x0_base));
49 return 0;
50 }
51
52 l2x0_init(l2x0_base, 0x00030024, 0x00000000);
53
54 return 0;
55}
56early_initcall(mxc_init_l2x0);
diff --git a/arch/arm/mach-imx/mach-armadillo5x0.c b/arch/arm/mach-imx/mach-armadillo5x0.c
index f5b4469310d..e008554e48b 100644
--- a/arch/arm/mach-imx/mach-armadillo5x0.c
+++ b/arch/arm/mach-imx/mach-armadillo5x0.c
@@ -314,25 +314,19 @@ static struct mtd_partition armadillo5x0_nor_flash_partitions[] = {
314 }, 314 },
315}; 315};
316 316
317static struct physmap_flash_data armadillo5x0_nor_flash_pdata = { 317static const struct physmap_flash_data
318 armadillo5x0_nor_flash_pdata __initconst = {
318 .width = 2, 319 .width = 2,
319 .parts = armadillo5x0_nor_flash_partitions, 320 .parts = armadillo5x0_nor_flash_partitions,
320 .nr_parts = ARRAY_SIZE(armadillo5x0_nor_flash_partitions), 321 .nr_parts = ARRAY_SIZE(armadillo5x0_nor_flash_partitions),
321}; 322};
322 323
323static struct resource armadillo5x0_nor_flash_resource = { 324static const struct resource armadillo5x0_nor_flash_resource __initconst = {
324 .flags = IORESOURCE_MEM, 325 .flags = IORESOURCE_MEM,
325 .start = MX31_CS0_BASE_ADDR, 326 .start = MX31_CS0_BASE_ADDR,
326 .end = MX31_CS0_BASE_ADDR + SZ_64M - 1, 327 .end = MX31_CS0_BASE_ADDR + SZ_64M - 1,
327}; 328};
328 329
329static struct platform_device armadillo5x0_nor_flash = {
330 .name = "physmap-flash",
331 .id = -1,
332 .num_resources = 1,
333 .resource = &armadillo5x0_nor_flash_resource,
334};
335
336/* 330/*
337 * FB support 331 * FB support
338 */ 332 */
@@ -514,8 +508,10 @@ static void __init armadillo5x0_init(void)
514 imx31_add_mx3_sdc_fb(&mx3fb_pdata); 508 imx31_add_mx3_sdc_fb(&mx3fb_pdata);
515 509
516 /* Register NOR Flash */ 510 /* Register NOR Flash */
517 mxc_register_device(&armadillo5x0_nor_flash, 511 platform_device_register_resndata(NULL, "physmap-flash", -1,
518 &armadillo5x0_nor_flash_pdata); 512 &armadillo5x0_nor_flash_resource, 1,
513 &armadillo5x0_nor_flash_pdata,
514 sizeof(armadillo5x0_nor_flash_pdata));
519 515
520 /* Register NAND Flash */ 516 /* Register NAND Flash */
521 imx31_add_mxc_nand(&armadillo5x0_nand_board_info); 517 imx31_add_mxc_nand(&armadillo5x0_nand_board_info);
diff --git a/arch/arm/mach-imx/mach-cpuimx35.c b/arch/arm/mach-imx/mach-cpuimx35.c
index 68e8c7aed56..bd4dbeaeabe 100644
--- a/arch/arm/mach-imx/mach-cpuimx35.c
+++ b/arch/arm/mach-imx/mach-cpuimx35.c
@@ -66,7 +66,7 @@ static struct i2c_board_info eukrea_cpuimx35_i2c_devices[] = {
66 I2C_BOARD_INFO("tsc2007", 0x48), 66 I2C_BOARD_INFO("tsc2007", 0x48),
67 .type = "tsc2007", 67 .type = "tsc2007",
68 .platform_data = &tsc2007_info, 68 .platform_data = &tsc2007_info,
69 .irq = gpio_to_irq(TSC2007_IRQGPIO), 69 .irq = IMX_GPIO_TO_IRQ(TSC2007_IRQGPIO),
70 }, 70 },
71}; 71};
72 72
diff --git a/arch/arm/mach-imx/mach-mx1ads.c b/arch/arm/mach-imx/mach-mx1ads.c
index 842859c22de..ebe9a29e30a 100644
--- a/arch/arm/mach-imx/mach-mx1ads.c
+++ b/arch/arm/mach-imx/mach-mx1ads.c
@@ -68,23 +68,16 @@ static const struct imxuart_platform_data uart1_pdata __initconst = {
68 * Physmap flash 68 * Physmap flash
69 */ 69 */
70 70
71static struct physmap_flash_data mx1ads_flash_data = { 71static const struct physmap_flash_data mx1ads_flash_data __initconst = {
72 .width = 4, /* bankwidth in bytes */ 72 .width = 4, /* bankwidth in bytes */
73}; 73};
74 74
75static struct resource flash_resource = { 75static const struct resource flash_resource __initconst = {
76 .start = MX1_CS0_PHYS, 76 .start = MX1_CS0_PHYS,
77 .end = MX1_CS0_PHYS + SZ_32M - 1, 77 .end = MX1_CS0_PHYS + SZ_32M - 1,
78 .flags = IORESOURCE_MEM, 78 .flags = IORESOURCE_MEM,
79}; 79};
80 80
81static struct platform_device flash_device = {
82 .name = "physmap-flash",
83 .id = 0,
84 .resource = &flash_resource,
85 .num_resources = 1,
86};
87
88/* 81/*
89 * I2C 82 * I2C
90 */ 83 */
@@ -125,7 +118,9 @@ static void __init mx1ads_init(void)
125 imx1_add_imx_uart1(&uart1_pdata); 118 imx1_add_imx_uart1(&uart1_pdata);
126 119
127 /* Physmap flash */ 120 /* Physmap flash */
128 mxc_register_device(&flash_device, &mx1ads_flash_data); 121 platform_device_register_resndata(NULL, "physmap-flash", 0,
122 &flash_resource, 1,
123 &mx1ads_flash_data, sizeof(mx1ads_flash_data));
129 124
130 /* I2C */ 125 /* I2C */
131 i2c_register_board_info(0, mx1ads_i2c_devices, 126 i2c_register_board_info(0, mx1ads_i2c_devices,
diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c
index ad7f24fdb9d..b2bc10bdf44 100644
--- a/arch/arm/mach-imx/mach-mx27_3ds.c
+++ b/arch/arm/mach-imx/mach-mx27_3ds.c
@@ -359,7 +359,7 @@ static struct spi_board_info mx27_3ds_spi_devs[] __initdata = {
359 .bus_num = 1, 359 .bus_num = 1,
360 .chip_select = 0, /* SS0 */ 360 .chip_select = 0, /* SS0 */
361 .platform_data = &mc13783_pdata, 361 .platform_data = &mc13783_pdata,
362 .irq = gpio_to_irq(PMIC_INT), 362 .irq = IMX_GPIO_TO_IRQ(PMIC_INT),
363 .mode = SPI_CS_HIGH, 363 .mode = SPI_CS_HIGH,
364 }, { 364 }, {
365 .modalias = "l4f00242t03", 365 .modalias = "l4f00242t03",
diff --git a/arch/arm/mach-imx/mach-vpr200.c b/arch/arm/mach-imx/mach-vpr200.c
index 4f310b38924..69092458f2d 100644
--- a/arch/arm/mach-imx/mach-vpr200.c
+++ b/arch/arm/mach-imx/mach-vpr200.c
@@ -162,7 +162,7 @@ static struct i2c_board_info vpr200_i2c_devices[] = {
162 }, { 162 }, {
163 I2C_BOARD_INFO("mc13892", 0x08), 163 I2C_BOARD_INFO("mc13892", 0x08),
164 .platform_data = &vpr200_pmic, 164 .platform_data = &vpr200_pmic,
165 .irq = gpio_to_irq(GPIO_PMIC_INT), 165 .irq = IMX_GPIO_TO_IRQ(GPIO_PMIC_INT),
166 } 166 }
167}; 167};
168 168
diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c
new file mode 100644
index 00000000000..9f0e82ec339
--- /dev/null
+++ b/arch/arm/mach-imx/mm-imx3.c
@@ -0,0 +1,256 @@
1/*
2 * Copyright (C) 1999,2000 Arm Limited
3 * Copyright (C) 2000 Deep Blue Solutions Ltd
4 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
5 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
6 * - add MX31 specific definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/mm.h>
20#include <linux/init.h>
21#include <linux/err.h>
22
23#include <asm/pgtable.h>
24#include <asm/hardware/cache-l2x0.h>
25#include <asm/mach/map.h>
26
27#include <mach/common.h>
28#include <mach/devices-common.h>
29#include <mach/hardware.h>
30#include <mach/iomux-v3.h>
31#include <mach/irqs.h>
32
33static void imx3_idle(void)
34{
35 unsigned long reg = 0;
36 __asm__ __volatile__(
37 /* disable I and D cache */
38 "mrc p15, 0, %0, c1, c0, 0\n"
39 "bic %0, %0, #0x00001000\n"
40 "bic %0, %0, #0x00000004\n"
41 "mcr p15, 0, %0, c1, c0, 0\n"
42 /* invalidate I cache */
43 "mov %0, #0\n"
44 "mcr p15, 0, %0, c7, c5, 0\n"
45 /* clear and invalidate D cache */
46 "mov %0, #0\n"
47 "mcr p15, 0, %0, c7, c14, 0\n"
48 /* WFI */
49 "mov %0, #0\n"
50 "mcr p15, 0, %0, c7, c0, 4\n"
51 "nop\n" "nop\n" "nop\n" "nop\n"
52 "nop\n" "nop\n" "nop\n"
53 /* enable I and D cache */
54 "mrc p15, 0, %0, c1, c0, 0\n"
55 "orr %0, %0, #0x00001000\n"
56 "orr %0, %0, #0x00000004\n"
57 "mcr p15, 0, %0, c1, c0, 0\n"
58 : "=r" (reg));
59}
60
61static void __iomem *imx3_ioremap(unsigned long phys_addr, size_t size,
62 unsigned int mtype)
63{
64 if (mtype == MT_DEVICE) {
65 /*
66 * Access all peripherals below 0x80000000 as nonshared device
67 * on mx3, but leave l2cc alone. Otherwise cache corruptions
68 * can occur.
69 */
70 if (phys_addr < 0x80000000 &&
71 !addr_in_module(phys_addr, MX3x_L2CC))
72 mtype = MT_DEVICE_NONSHARED;
73 }
74
75 return __arm_ioremap(phys_addr, size, mtype);
76}
77
78void imx3_init_l2x0(void)
79{
80 void __iomem *l2x0_base;
81 void __iomem *clkctl_base;
82
83/*
84 * First of all, we must repair broken chip settings. There are some
85 * i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These
86 * misconfigured CPUs will run amok immediately when the L2 cache gets enabled.
87 * Workaraound is to setup the correct register setting prior enabling the
88 * L2 cache. This should not hurt already working CPUs, as they are using the
89 * same value.
90 */
91#define L2_MEM_VAL 0x10
92
93 clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096);
94 if (clkctl_base != NULL) {
95 writel(0x00000515, clkctl_base + L2_MEM_VAL);
96 iounmap(clkctl_base);
97 } else {
98 pr_err("L2 cache: Cannot fix timing. Trying to continue without\n");
99 }
100
101 l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096);
102 if (IS_ERR(l2x0_base)) {
103 printk(KERN_ERR "remapping L2 cache area failed with %ld\n",
104 PTR_ERR(l2x0_base));
105 return;
106 }
107
108 l2x0_init(l2x0_base, 0x00030024, 0x00000000);
109}
110
111static struct map_desc mx31_io_desc[] __initdata = {
112 imx_map_entry(MX31, X_MEMC, MT_DEVICE),
113 imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED),
114 imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED),
115 imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED),
116 imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED),
117};
118
119/*
120 * This function initializes the memory map. It is called during the
121 * system startup to create static physical to virtual memory mappings
122 * for the IO modules.
123 */
124void __init mx31_map_io(void)
125{
126 iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc));
127}
128
129static struct map_desc mx35_io_desc[] __initdata = {
130 imx_map_entry(MX35, X_MEMC, MT_DEVICE),
131 imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED),
132 imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED),
133 imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED),
134 imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED),
135};
136
137void __init mx35_map_io(void)
138{
139 iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc));
140}
141
142void __init imx31_init_early(void)
143{
144 mxc_set_cpu_type(MXC_CPU_MX31);
145 mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
146 imx_idle = imx3_idle;
147 imx_ioremap = imx3_ioremap;
148}
149
150void __init imx35_init_early(void)
151{
152 mxc_set_cpu_type(MXC_CPU_MX35);
153 mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
154 mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
155 imx_idle = imx3_idle;
156 imx_ioremap = imx3_ioremap;
157}
158
159void __init mx31_init_irq(void)
160{
161 mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR));
162}
163
164void __init mx35_init_irq(void)
165{
166 mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR));
167}
168
169static struct sdma_script_start_addrs imx31_to1_sdma_script __initdata = {
170 .per_2_per_addr = 1677,
171};
172
173static struct sdma_script_start_addrs imx31_to2_sdma_script __initdata = {
174 .ap_2_ap_addr = 423,
175 .ap_2_bp_addr = 829,
176 .bp_2_ap_addr = 1029,
177};
178
179static struct sdma_platform_data imx31_sdma_pdata __initdata = {
180 .fw_name = "sdma-imx31-to2.bin",
181 .script_addrs = &imx31_to2_sdma_script,
182};
183
184void __init imx31_soc_init(void)
185{
186 int to_version = mx31_revision() >> 4;
187
188 imx3_init_l2x0();
189
190 mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0);
191 mxc_register_gpio("imx31-gpio", 1, MX31_GPIO2_BASE_ADDR, SZ_16K, MX31_INT_GPIO2, 0);
192 mxc_register_gpio("imx31-gpio", 2, MX31_GPIO3_BASE_ADDR, SZ_16K, MX31_INT_GPIO3, 0);
193
194 if (to_version == 1) {
195 strncpy(imx31_sdma_pdata.fw_name, "sdma-imx31-to1.bin",
196 strlen(imx31_sdma_pdata.fw_name));
197 imx31_sdma_pdata.script_addrs = &imx31_to1_sdma_script;
198 }
199
200 imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata);
201}
202
203static struct sdma_script_start_addrs imx35_to1_sdma_script __initdata = {
204 .ap_2_ap_addr = 642,
205 .uart_2_mcu_addr = 817,
206 .mcu_2_app_addr = 747,
207 .uartsh_2_mcu_addr = 1183,
208 .per_2_shp_addr = 1033,
209 .mcu_2_shp_addr = 961,
210 .ata_2_mcu_addr = 1333,
211 .mcu_2_ata_addr = 1252,
212 .app_2_mcu_addr = 683,
213 .shp_2_per_addr = 1111,
214 .shp_2_mcu_addr = 892,
215};
216
217static struct sdma_script_start_addrs imx35_to2_sdma_script __initdata = {
218 .ap_2_ap_addr = 729,
219 .uart_2_mcu_addr = 904,
220 .per_2_app_addr = 1597,
221 .mcu_2_app_addr = 834,
222 .uartsh_2_mcu_addr = 1270,
223 .per_2_shp_addr = 1120,
224 .mcu_2_shp_addr = 1048,
225 .ata_2_mcu_addr = 1429,
226 .mcu_2_ata_addr = 1339,
227 .app_2_per_addr = 1531,
228 .app_2_mcu_addr = 770,
229 .shp_2_per_addr = 1198,
230 .shp_2_mcu_addr = 979,
231};
232
233static struct sdma_platform_data imx35_sdma_pdata __initdata = {
234 .fw_name = "sdma-imx35-to2.bin",
235 .script_addrs = &imx35_to2_sdma_script,
236};
237
238void __init imx35_soc_init(void)
239{
240 int to_version = mx35_revision() >> 4;
241
242 imx3_init_l2x0();
243
244 /* i.mx35 has the i.mx31 type gpio */
245 mxc_register_gpio("imx31-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0);
246 mxc_register_gpio("imx31-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0);
247 mxc_register_gpio("imx31-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0);
248
249 if (to_version == 1) {
250 strncpy(imx35_sdma_pdata.fw_name, "sdma-imx35-to1.bin",
251 strlen(imx35_sdma_pdata.fw_name));
252 imx35_sdma_pdata.script_addrs = &imx35_to1_sdma_script;
253 }
254
255 imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata);
256}
diff --git a/arch/arm/mach-imx/mm-imx31.c b/arch/arm/mach-imx/mm-imx31.c
deleted file mode 100644
index b7c55e7db00..00000000000
--- a/arch/arm/mach-imx/mm-imx31.c
+++ /dev/null
@@ -1,91 +0,0 @@
1/*
2 * Copyright (C) 1999,2000 Arm Limited
3 * Copyright (C) 2000 Deep Blue Solutions Ltd
4 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
5 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
6 * - add MX31 specific definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/mm.h>
20#include <linux/init.h>
21#include <linux/err.h>
22
23#include <asm/pgtable.h>
24#include <asm/mach/map.h>
25
26#include <mach/common.h>
27#include <mach/devices-common.h>
28#include <mach/hardware.h>
29#include <mach/iomux-v3.h>
30#include <mach/irqs.h>
31
32static struct map_desc mx31_io_desc[] __initdata = {
33 imx_map_entry(MX31, X_MEMC, MT_DEVICE),
34 imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED),
35 imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED),
36 imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED),
37 imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED),
38};
39
40/*
41 * This function initializes the memory map. It is called during the
42 * system startup to create static physical to virtual memory mappings
43 * for the IO modules.
44 */
45void __init mx31_map_io(void)
46{
47 iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc));
48}
49
50void __init imx31_init_early(void)
51{
52 mxc_set_cpu_type(MXC_CPU_MX31);
53 mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
54}
55
56void __init mx31_init_irq(void)
57{
58 mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR));
59}
60
61static struct sdma_script_start_addrs imx31_to1_sdma_script __initdata = {
62 .per_2_per_addr = 1677,
63};
64
65static struct sdma_script_start_addrs imx31_to2_sdma_script __initdata = {
66 .ap_2_ap_addr = 423,
67 .ap_2_bp_addr = 829,
68 .bp_2_ap_addr = 1029,
69};
70
71static struct sdma_platform_data imx31_sdma_pdata __initdata = {
72 .fw_name = "sdma-imx31-to2.bin",
73 .script_addrs = &imx31_to2_sdma_script,
74};
75
76void __init imx31_soc_init(void)
77{
78 int to_version = mx31_revision() >> 4;
79
80 mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0);
81 mxc_register_gpio("imx31-gpio", 1, MX31_GPIO2_BASE_ADDR, SZ_16K, MX31_INT_GPIO2, 0);
82 mxc_register_gpio("imx31-gpio", 2, MX31_GPIO3_BASE_ADDR, SZ_16K, MX31_INT_GPIO3, 0);
83
84 if (to_version == 1) {
85 strncpy(imx31_sdma_pdata.fw_name, "sdma-imx31-to1.bin",
86 strlen(imx31_sdma_pdata.fw_name));
87 imx31_sdma_pdata.script_addrs = &imx31_to1_sdma_script;
88 }
89
90 imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata);
91}
diff --git a/arch/arm/mach-imx/mm-imx35.c b/arch/arm/mach-imx/mm-imx35.c
deleted file mode 100644
index f49bac7a1ed..00000000000
--- a/arch/arm/mach-imx/mm-imx35.c
+++ /dev/null
@@ -1,109 +0,0 @@
1/*
2 * Copyright (C) 1999,2000 Arm Limited
3 * Copyright (C) 2000 Deep Blue Solutions Ltd
4 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
5 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
6 * - add MX31 specific definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/mm.h>
20#include <linux/init.h>
21#include <linux/err.h>
22
23#include <asm/pgtable.h>
24#include <asm/mach/map.h>
25#include <asm/hardware/cache-l2x0.h>
26
27#include <mach/common.h>
28#include <mach/devices-common.h>
29#include <mach/hardware.h>
30#include <mach/iomux-v3.h>
31#include <mach/irqs.h>
32
33static struct map_desc mx35_io_desc[] __initdata = {
34 imx_map_entry(MX35, X_MEMC, MT_DEVICE),
35 imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED),
36 imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED),
37 imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED),
38 imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED),
39};
40
41void __init mx35_map_io(void)
42{
43 iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc));
44}
45
46void __init imx35_init_early(void)
47{
48 mxc_set_cpu_type(MXC_CPU_MX35);
49 mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
50 mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
51}
52
53void __init mx35_init_irq(void)
54{
55 mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR));
56}
57
58static struct sdma_script_start_addrs imx35_to1_sdma_script __initdata = {
59 .ap_2_ap_addr = 642,
60 .uart_2_mcu_addr = 817,
61 .mcu_2_app_addr = 747,
62 .uartsh_2_mcu_addr = 1183,
63 .per_2_shp_addr = 1033,
64 .mcu_2_shp_addr = 961,
65 .ata_2_mcu_addr = 1333,
66 .mcu_2_ata_addr = 1252,
67 .app_2_mcu_addr = 683,
68 .shp_2_per_addr = 1111,
69 .shp_2_mcu_addr = 892,
70};
71
72static struct sdma_script_start_addrs imx35_to2_sdma_script __initdata = {
73 .ap_2_ap_addr = 729,
74 .uart_2_mcu_addr = 904,
75 .per_2_app_addr = 1597,
76 .mcu_2_app_addr = 834,
77 .uartsh_2_mcu_addr = 1270,
78 .per_2_shp_addr = 1120,
79 .mcu_2_shp_addr = 1048,
80 .ata_2_mcu_addr = 1429,
81 .mcu_2_ata_addr = 1339,
82 .app_2_per_addr = 1531,
83 .app_2_mcu_addr = 770,
84 .shp_2_per_addr = 1198,
85 .shp_2_mcu_addr = 979,
86};
87
88static struct sdma_platform_data imx35_sdma_pdata __initdata = {
89 .fw_name = "sdma-imx35-to2.bin",
90 .script_addrs = &imx35_to2_sdma_script,
91};
92
93void __init imx35_soc_init(void)
94{
95 int to_version = mx35_revision() >> 4;
96
97 /* i.mx35 has the i.mx31 type gpio */
98 mxc_register_gpio("imx31-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0);
99 mxc_register_gpio("imx31-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0);
100 mxc_register_gpio("imx31-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0);
101
102 if (to_version == 1) {
103 strncpy(imx35_sdma_pdata.fw_name, "sdma-imx35-to1.bin",
104 strlen(imx35_sdma_pdata.fw_name));
105 imx35_sdma_pdata.script_addrs = &imx35_to1_sdma_script;
106 }
107
108 imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata);
109}
diff --git a/arch/arm/mach-imx/pm-imx27.c b/arch/arm/mach-imx/pm-imx27.c
index acf17691d2c..e455d2f855b 100644
--- a/arch/arm/mach-imx/pm-imx27.c
+++ b/arch/arm/mach-imx/pm-imx27.c
@@ -11,7 +11,7 @@
11#include <linux/suspend.h> 11#include <linux/suspend.h>
12#include <linux/io.h> 12#include <linux/io.h>
13#include <mach/system.h> 13#include <mach/system.h>
14#include <mach/mx27.h> 14#include <mach/hardware.h>
15 15
16static int mx27_suspend_enter(suspend_state_t state) 16static int mx27_suspend_enter(suspend_state_t state)
17{ 17{
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-23 12:29:36 -0400