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-rw-r--r--arch/arm/mach-exynos4/Kconfig35
-rw-r--r--arch/arm/mach-exynos4/clock.c220
-rw-r--r--arch/arm/mach-exynos4/cpu.c2
-rw-r--r--arch/arm/mach-exynos4/dma.c300
-rw-r--r--arch/arm/mach-exynos4/include/mach/dma.h4
-rw-r--r--arch/arm/mach-exynos4/include/mach/i2c-hdmiphy.h16
-rw-r--r--arch/arm/mach-exynos4/include/mach/irqs.h4
-rw-r--r--arch/arm/mach-exynos4/include/mach/map.h12
-rw-r--r--arch/arm/mach-exynos4/include/mach/pm-core.h8
-rw-r--r--arch/arm/mach-exynos4/include/mach/pmu.h7
-rw-r--r--arch/arm/mach-exynos4/include/mach/regs-pmu.h74
-rw-r--r--arch/arm/mach-exynos4/mach-nuri.c34
-rw-r--r--arch/arm/mach-exynos4/mach-origen.c577
-rw-r--r--arch/arm/mach-exynos4/mach-smdkv310.c49
-rw-r--r--arch/arm/mach-exynos4/mach-universal_c210.c312
-rw-r--r--arch/arm/mach-exynos4/pm.c7
-rw-r--r--arch/arm/mach-exynos4/pmu.c353
17 files changed, 1724 insertions, 290 deletions
diff --git a/arch/arm/mach-exynos4/Kconfig b/arch/arm/mach-exynos4/Kconfig
index c595bb03f41..b6722decff9 100644
--- a/arch/arm/mach-exynos4/Kconfig
+++ b/arch/arm/mach-exynos4/Kconfig
@@ -11,7 +11,7 @@ if ARCH_EXYNOS4
11 11
12config CPU_EXYNOS4210 12config CPU_EXYNOS4210
13 bool 13 bool
14 select S3C_PL330_DMA 14 select SAMSUNG_DMADEV
15 help 15 help
16 Enable EXYNOS4210 CPU support 16 Enable EXYNOS4210 CPU support
17 17
@@ -131,6 +131,14 @@ config MACH_SMDKV310
131 select S3C_DEV_RTC 131 select S3C_DEV_RTC
132 select S3C_DEV_WDT 132 select S3C_DEV_WDT
133 select S3C_DEV_I2C1 133 select S3C_DEV_I2C1
134 select S5P_DEV_FIMC0
135 select S5P_DEV_FIMC1
136 select S5P_DEV_FIMC2
137 select S5P_DEV_FIMC3
138 select S5P_DEV_I2C_HDMIPHY
139 select S5P_DEV_MFC
140 select S5P_DEV_TV
141 select S5P_DEV_USB_EHCI
134 select S3C_DEV_HSMMC 142 select S3C_DEV_HSMMC
135 select S3C_DEV_HSMMC1 143 select S3C_DEV_HSMMC1
136 select S3C_DEV_HSMMC2 144 select S3C_DEV_HSMMC2
@@ -145,6 +153,7 @@ config MACH_SMDKV310
145 select EXYNOS4_SETUP_I2C1 153 select EXYNOS4_SETUP_I2C1
146 select EXYNOS4_SETUP_KEYPAD 154 select EXYNOS4_SETUP_KEYPAD
147 select EXYNOS4_SETUP_SDHCI 155 select EXYNOS4_SETUP_SDHCI
156 select EXYNOS4_SETUP_USB_PHY
148 help 157 help
149 Machine support for Samsung SMDKV310 158 Machine support for Samsung SMDKV310
150 159
@@ -170,19 +179,26 @@ config MACH_UNIVERSAL_C210
170 select S5P_DEV_FIMC1 179 select S5P_DEV_FIMC1
171 select S5P_DEV_FIMC2 180 select S5P_DEV_FIMC2
172 select S5P_DEV_FIMC3 181 select S5P_DEV_FIMC3
182 select S5P_DEV_CSIS0
183 select S5P_DEV_FIMD0
173 select S3C_DEV_HSMMC 184 select S3C_DEV_HSMMC
174 select S3C_DEV_HSMMC2 185 select S3C_DEV_HSMMC2
175 select S3C_DEV_HSMMC3 186 select S3C_DEV_HSMMC3
176 select S3C_DEV_I2C1 187 select S3C_DEV_I2C1
177 select S3C_DEV_I2C3 188 select S3C_DEV_I2C3
178 select S3C_DEV_I2C5 189 select S3C_DEV_I2C5
190 select S5P_DEV_I2C_HDMIPHY
179 select S5P_DEV_MFC 191 select S5P_DEV_MFC
180 select S5P_DEV_ONENAND 192 select S5P_DEV_ONENAND
193 select S5P_DEV_TV
181 select EXYNOS4_DEV_PD 194 select EXYNOS4_DEV_PD
195 select EXYNOS4_SETUP_FIMD0
182 select EXYNOS4_SETUP_I2C1 196 select EXYNOS4_SETUP_I2C1
183 select EXYNOS4_SETUP_I2C3 197 select EXYNOS4_SETUP_I2C3
184 select EXYNOS4_SETUP_I2C5 198 select EXYNOS4_SETUP_I2C5
185 select EXYNOS4_SETUP_SDHCI 199 select EXYNOS4_SETUP_SDHCI
200 select EXYNOS4_SETUP_FIMC
201 select S5P_SETUP_MIPIPHY
186 help 202 help
187 Machine support for Samsung Mobile Universal S5PC210 Reference 203 Machine support for Samsung Mobile Universal S5PC210 Reference
188 Board. 204 Board.
@@ -191,6 +207,8 @@ config MACH_NURI
191 bool "Mobile NURI Board" 207 bool "Mobile NURI Board"
192 select CPU_EXYNOS4210 208 select CPU_EXYNOS4210
193 select S3C_DEV_WDT 209 select S3C_DEV_WDT
210 select S3C_DEV_RTC
211 select S5P_DEV_FIMD0
194 select S3C_DEV_HSMMC 212 select S3C_DEV_HSMMC
195 select S3C_DEV_HSMMC2 213 select S3C_DEV_HSMMC2
196 select S3C_DEV_HSMMC3 214 select S3C_DEV_HSMMC3
@@ -200,6 +218,7 @@ config MACH_NURI
200 select S5P_DEV_MFC 218 select S5P_DEV_MFC
201 select S5P_DEV_USB_EHCI 219 select S5P_DEV_USB_EHCI
202 select EXYNOS4_DEV_PD 220 select EXYNOS4_DEV_PD
221 select EXYNOS4_SETUP_FIMD0
203 select EXYNOS4_SETUP_I2C1 222 select EXYNOS4_SETUP_I2C1
204 select EXYNOS4_SETUP_I2C3 223 select EXYNOS4_SETUP_I2C3
205 select EXYNOS4_SETUP_I2C5 224 select EXYNOS4_SETUP_I2C5
@@ -215,8 +234,22 @@ config MACH_ORIGEN
215 select CPU_EXYNOS4210 234 select CPU_EXYNOS4210
216 select S3C_DEV_RTC 235 select S3C_DEV_RTC
217 select S3C_DEV_WDT 236 select S3C_DEV_WDT
237 select S3C_DEV_HSMMC
218 select S3C_DEV_HSMMC2 238 select S3C_DEV_HSMMC2
239 select S5P_DEV_FIMC0
240 select S5P_DEV_FIMC1
241 select S5P_DEV_FIMC2
242 select S5P_DEV_FIMC3
243 select S5P_DEV_FIMD0
244 select S5P_DEV_I2C_HDMIPHY
245 select S5P_DEV_TV
246 select S5P_DEV_USB_EHCI
247 select EXYNOS4_DEV_PD
248 select SAMSUNG_DEV_BACKLIGHT
249 select SAMSUNG_DEV_PWM
250 select EXYNOS4_SETUP_FIMD0
219 select EXYNOS4_SETUP_SDHCI 251 select EXYNOS4_SETUP_SDHCI
252 select EXYNOS4_SETUP_USB_PHY
220 help 253 help
221 Machine support for ORIGEN based on Samsung EXYNOS4210 254 Machine support for ORIGEN based on Samsung EXYNOS4210
222 255
diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c
index 413c7cc8197..a25c8183675 100644
--- a/arch/arm/mach-exynos4/clock.c
+++ b/arch/arm/mach-exynos4/clock.c
@@ -111,6 +111,11 @@ struct clk clk_sclk_usbphy1 = {
111 .name = "sclk_usbphy1", 111 .name = "sclk_usbphy1",
112}; 112};
113 113
114static struct clk dummy_apb_pclk = {
115 .name = "apb_pclk",
116 .id = -1,
117};
118
114static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable) 119static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
115{ 120{
116 return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable); 121 return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);
@@ -146,6 +151,11 @@ static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
146 return s5p_gatectrl(S5P_CLKGATE_IP_MFC, clk, enable); 151 return s5p_gatectrl(S5P_CLKGATE_IP_MFC, clk, enable);
147} 152}
148 153
154static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable)
155{
156 return s5p_gatectrl(S5P_CLKSRC_MASK_TV, clk, enable);
157}
158
149static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable) 159static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
150{ 160{
151 return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable); 161 return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable);
@@ -186,6 +196,16 @@ static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
186 return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable); 196 return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable);
187} 197}
188 198
199static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
200{
201 return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
202}
203
204static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
205{
206 return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
207}
208
189/* Core list of CMU_CPU side */ 209/* Core list of CMU_CPU side */
190 210
191static struct clksrc_clk clk_mout_apll = { 211static struct clksrc_clk clk_mout_apll = {
@@ -503,13 +523,48 @@ static struct clk init_clocks_off[] = {
503 .enable = exynos4_clk_ip_fsys_ctrl, 523 .enable = exynos4_clk_ip_fsys_ctrl,
504 .ctrlbit = (1 << 9), 524 .ctrlbit = (1 << 9),
505 }, { 525 }, {
506 .name = "pdma", 526 .name = "dac",
507 .devname = "s3c-pl330.0", 527 .devname = "s5p-sdo",
528 .enable = exynos4_clk_ip_tv_ctrl,
529 .ctrlbit = (1 << 2),
530 }, {
531 .name = "mixer",
532 .devname = "s5p-mixer",
533 .enable = exynos4_clk_ip_tv_ctrl,
534 .ctrlbit = (1 << 1),
535 }, {
536 .name = "vp",
537 .devname = "s5p-mixer",
538 .enable = exynos4_clk_ip_tv_ctrl,
539 .ctrlbit = (1 << 0),
540 }, {
541 .name = "hdmi",
542 .devname = "exynos4-hdmi",
543 .enable = exynos4_clk_ip_tv_ctrl,
544 .ctrlbit = (1 << 3),
545 }, {
546 .name = "hdmiphy",
547 .devname = "exynos4-hdmi",
548 .enable = exynos4_clk_hdmiphy_ctrl,
549 .ctrlbit = (1 << 0),
550 }, {
551 .name = "dacphy",
552 .devname = "s5p-sdo",
553 .enable = exynos4_clk_dac_ctrl,
554 .ctrlbit = (1 << 0),
555 }, {
556 .name = "sata",
557 .parent = &clk_aclk_133.clk,
558 .enable = exynos4_clk_ip_fsys_ctrl,
559 .ctrlbit = (1 << 10),
560 }, {
561 .name = "dma",
562 .devname = "dma-pl330.0",
508 .enable = exynos4_clk_ip_fsys_ctrl, 563 .enable = exynos4_clk_ip_fsys_ctrl,
509 .ctrlbit = (1 << 0), 564 .ctrlbit = (1 << 0),
510 }, { 565 }, {
511 .name = "pdma", 566 .name = "dma",
512 .devname = "s3c-pl330.1", 567 .devname = "dma-pl330.1",
513 .enable = exynos4_clk_ip_fsys_ctrl, 568 .enable = exynos4_clk_ip_fsys_ctrl,
514 .ctrlbit = (1 << 1), 569 .ctrlbit = (1 << 1),
515 }, { 570 }, {
@@ -630,6 +685,12 @@ static struct clk init_clocks_off[] = {
630 .enable = exynos4_clk_ip_peril_ctrl, 685 .enable = exynos4_clk_ip_peril_ctrl,
631 .ctrlbit = (1 << 13), 686 .ctrlbit = (1 << 13),
632 }, { 687 }, {
688 .name = "i2c",
689 .devname = "s3c2440-hdmiphy-i2c",
690 .parent = &clk_aclk_100.clk,
691 .enable = exynos4_clk_ip_peril_ctrl,
692 .ctrlbit = (1 << 14),
693 }, {
633 .name = "SYSMMU_MDMA", 694 .name = "SYSMMU_MDMA",
634 .enable = exynos4_clk_ip_image_ctrl, 695 .enable = exynos4_clk_ip_image_ctrl,
635 .ctrlbit = (1 << 5), 696 .ctrlbit = (1 << 5),
@@ -831,6 +892,81 @@ static struct clksrc_sources clkset_mout_mfc = {
831 .nr_sources = ARRAY_SIZE(clkset_mout_mfc_list), 892 .nr_sources = ARRAY_SIZE(clkset_mout_mfc_list),
832}; 893};
833 894
895static struct clk *clkset_sclk_dac_list[] = {
896 [0] = &clk_sclk_vpll.clk,
897 [1] = &clk_sclk_hdmiphy,
898};
899
900static struct clksrc_sources clkset_sclk_dac = {
901 .sources = clkset_sclk_dac_list,
902 .nr_sources = ARRAY_SIZE(clkset_sclk_dac_list),
903};
904
905static struct clksrc_clk clk_sclk_dac = {
906 .clk = {
907 .name = "sclk_dac",
908 .enable = exynos4_clksrc_mask_tv_ctrl,
909 .ctrlbit = (1 << 8),
910 },
911 .sources = &clkset_sclk_dac,
912 .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 8, .size = 1 },
913};
914
915static struct clksrc_clk clk_sclk_pixel = {
916 .clk = {
917 .name = "sclk_pixel",
918 .parent = &clk_sclk_vpll.clk,
919 },
920 .reg_div = { .reg = S5P_CLKDIV_TV, .shift = 0, .size = 4 },
921};
922
923static struct clk *clkset_sclk_hdmi_list[] = {
924 [0] = &clk_sclk_pixel.clk,
925 [1] = &clk_sclk_hdmiphy,
926};
927
928static struct clksrc_sources clkset_sclk_hdmi = {
929 .sources = clkset_sclk_hdmi_list,
930 .nr_sources = ARRAY_SIZE(clkset_sclk_hdmi_list),
931};
932
933static struct clksrc_clk clk_sclk_hdmi = {
934 .clk = {
935 .name = "sclk_hdmi",
936 .enable = exynos4_clksrc_mask_tv_ctrl,
937 .ctrlbit = (1 << 0),
938 },
939 .sources = &clkset_sclk_hdmi,
940 .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 0, .size = 1 },
941};
942
943static struct clk *clkset_sclk_mixer_list[] = {
944 [0] = &clk_sclk_dac.clk,
945 [1] = &clk_sclk_hdmi.clk,
946};
947
948static struct clksrc_sources clkset_sclk_mixer = {
949 .sources = clkset_sclk_mixer_list,
950 .nr_sources = ARRAY_SIZE(clkset_sclk_mixer_list),
951};
952
953static struct clksrc_clk clk_sclk_mixer = {
954 .clk = {
955 .name = "sclk_mixer",
956 .enable = exynos4_clksrc_mask_tv_ctrl,
957 .ctrlbit = (1 << 4),
958 },
959 .sources = &clkset_sclk_mixer,
960 .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 4, .size = 1 },
961};
962
963static struct clksrc_clk *sclk_tv[] = {
964 &clk_sclk_dac,
965 &clk_sclk_pixel,
966 &clk_sclk_hdmi,
967 &clk_sclk_mixer,
968};
969
834static struct clksrc_clk clk_dout_mmc0 = { 970static struct clksrc_clk clk_dout_mmc0 = {
835 .clk = { 971 .clk = {
836 .name = "dout_mmc0", 972 .name = "dout_mmc0",
@@ -1157,6 +1293,71 @@ static struct clk_ops exynos4_fout_apll_ops = {
1157 .get_rate = exynos4_fout_apll_get_rate, 1293 .get_rate = exynos4_fout_apll_get_rate,
1158}; 1294};
1159 1295
1296static u32 vpll_div[][8] = {
1297 { 54000000, 3, 53, 3, 1024, 0, 17, 0 },
1298 { 108000000, 3, 53, 2, 1024, 0, 17, 0 },
1299};
1300
1301static unsigned long exynos4_vpll_get_rate(struct clk *clk)
1302{
1303 return clk->rate;
1304}
1305
1306static int exynos4_vpll_set_rate(struct clk *clk, unsigned long rate)
1307{
1308 unsigned int vpll_con0, vpll_con1 = 0;
1309 unsigned int i;
1310
1311 /* Return if nothing changed */
1312 if (clk->rate == rate)
1313 return 0;
1314
1315 vpll_con0 = __raw_readl(S5P_VPLL_CON0);
1316 vpll_con0 &= ~(0x1 << 27 | \
1317 PLL90XX_MDIV_MASK << PLL46XX_MDIV_SHIFT | \
1318 PLL90XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \
1319 PLL90XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
1320
1321 vpll_con1 = __raw_readl(S5P_VPLL_CON1);
1322 vpll_con1 &= ~(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT | \
1323 PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT | \
1324 PLL4650C_KDIV_MASK << PLL46XX_KDIV_SHIFT);
1325
1326 for (i = 0; i < ARRAY_SIZE(vpll_div); i++) {
1327 if (vpll_div[i][0] == rate) {
1328 vpll_con0 |= vpll_div[i][1] << PLL46XX_PDIV_SHIFT;
1329 vpll_con0 |= vpll_div[i][2] << PLL46XX_MDIV_SHIFT;
1330 vpll_con0 |= vpll_div[i][3] << PLL46XX_SDIV_SHIFT;
1331 vpll_con1 |= vpll_div[i][4] << PLL46XX_KDIV_SHIFT;
1332 vpll_con1 |= vpll_div[i][5] << PLL46XX_MFR_SHIFT;
1333 vpll_con1 |= vpll_div[i][6] << PLL46XX_MRR_SHIFT;
1334 vpll_con0 |= vpll_div[i][7] << 27;
1335 break;
1336 }
1337 }
1338
1339 if (i == ARRAY_SIZE(vpll_div)) {
1340 printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
1341 __func__);
1342 return -EINVAL;
1343 }
1344
1345 __raw_writel(vpll_con0, S5P_VPLL_CON0);
1346 __raw_writel(vpll_con1, S5P_VPLL_CON1);
1347
1348 /* Wait for VPLL lock */
1349 while (!(__raw_readl(S5P_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT)))
1350 continue;
1351
1352 clk->rate = rate;
1353 return 0;
1354}
1355
1356static struct clk_ops exynos4_vpll_ops = {
1357 .get_rate = exynos4_vpll_get_rate,
1358 .set_rate = exynos4_vpll_set_rate,
1359};
1360
1160void __init_or_cpufreq exynos4_setup_clocks(void) 1361void __init_or_cpufreq exynos4_setup_clocks(void)
1161{ 1362{
1162 struct clk *xtal_clk; 1363 struct clk *xtal_clk;
@@ -1214,6 +1415,7 @@ void __init_or_cpufreq exynos4_setup_clocks(void)
1214 clk_fout_apll.ops = &exynos4_fout_apll_ops; 1415 clk_fout_apll.ops = &exynos4_fout_apll_ops;
1215 clk_fout_mpll.rate = mpll; 1416 clk_fout_mpll.rate = mpll;
1216 clk_fout_epll.rate = epll; 1417 clk_fout_epll.rate = epll;
1418 clk_fout_vpll.ops = &exynos4_vpll_ops;
1217 clk_fout_vpll.rate = vpll; 1419 clk_fout_vpll.rate = vpll;
1218 1420
1219 printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld", 1421 printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
@@ -1241,7 +1443,10 @@ void __init_or_cpufreq exynos4_setup_clocks(void)
1241} 1443}
1242 1444
1243static struct clk *clks[] __initdata = { 1445static struct clk *clks[] __initdata = {
1244 /* Nothing here yet */ 1446 &clk_sclk_hdmi27m,
1447 &clk_sclk_hdmiphy,
1448 &clk_sclk_usbphy0,
1449 &clk_sclk_usbphy1,
1245}; 1450};
1246 1451
1247#ifdef CONFIG_PM_SLEEP 1452#ifdef CONFIG_PM_SLEEP
@@ -1275,6 +1480,9 @@ void __init exynos4_register_clocks(void)
1275 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++) 1480 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
1276 s3c_register_clksrc(sysclks[ptr], 1); 1481 s3c_register_clksrc(sysclks[ptr], 1);
1277 1482
1483 for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++)
1484 s3c_register_clksrc(sclk_tv[ptr], 1);
1485
1278 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); 1486 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1279 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); 1487 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1280 1488
@@ -1282,5 +1490,7 @@ void __init exynos4_register_clocks(void)
1282 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 1490 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1283 1491
1284 register_syscore_ops(&exynos4_clock_syscore_ops); 1492 register_syscore_ops(&exynos4_clock_syscore_ops);
1493 s3c24xx_register_clock(&dummy_apb_pclk);
1494
1285 s3c_pwmclk_init(); 1495 s3c_pwmclk_init();
1286} 1496}
diff --git a/arch/arm/mach-exynos4/cpu.c b/arch/arm/mach-exynos4/cpu.c
index 02ec52a9927..2aa3df00368 100644
--- a/arch/arm/mach-exynos4/cpu.c
+++ b/arch/arm/mach-exynos4/cpu.c
@@ -28,6 +28,7 @@
28#include <plat/fimc-core.h> 28#include <plat/fimc-core.h>
29#include <plat/iic-core.h> 29#include <plat/iic-core.h>
30#include <plat/reset.h> 30#include <plat/reset.h>
31#include <plat/tv-core.h>
31 32
32#include <mach/regs-irq.h> 33#include <mach/regs-irq.h>
33#include <mach/regs-pmu.h> 34#include <mach/regs-pmu.h>
@@ -180,6 +181,7 @@ void __init exynos4_map_io(void)
180 s3c_i2c2_setname("s3c2440-i2c"); 181 s3c_i2c2_setname("s3c2440-i2c");
181 182
182 s5p_fb_setname(0, "exynos4-fb"); 183 s5p_fb_setname(0, "exynos4-fb");
184 s5p_hdmi_setname("exynos4-hdmi");
183} 185}
184 186
185void __init exynos4_init_clocks(int xtal) 187void __init exynos4_init_clocks(int xtal)
diff --git a/arch/arm/mach-exynos4/dma.c b/arch/arm/mach-exynos4/dma.c
index 564bb530f33..9667c61e64f 100644
--- a/arch/arm/mach-exynos4/dma.c
+++ b/arch/arm/mach-exynos4/dma.c
@@ -21,151 +21,229 @@
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 */ 22 */
23 23
24#include <linux/platform_device.h>
25#include <linux/dma-mapping.h> 24#include <linux/dma-mapping.h>
25#include <linux/amba/bus.h>
26#include <linux/amba/pl330.h>
26 27
28#include <asm/irq.h>
27#include <plat/devs.h> 29#include <plat/devs.h>
28#include <plat/irqs.h> 30#include <plat/irqs.h>
29 31
30#include <mach/map.h> 32#include <mach/map.h>
31#include <mach/irqs.h> 33#include <mach/irqs.h>
32 34#include <mach/dma.h>
33#include <plat/s3c-pl330-pdata.h>
34 35
35static u64 dma_dmamask = DMA_BIT_MASK(32); 36static u64 dma_dmamask = DMA_BIT_MASK(32);
36 37
37static struct resource exynos4_pdma0_resource[] = { 38struct dma_pl330_peri pdma0_peri[28] = {
38 [0] = { 39 {
39 .start = EXYNOS4_PA_PDMA0, 40 .peri_id = (u8)DMACH_PCM0_RX,
40 .end = EXYNOS4_PA_PDMA0 + SZ_4K, 41 .rqtype = DEVTOMEM,
41 .flags = IORESOURCE_MEM, 42 }, {
42 }, 43 .peri_id = (u8)DMACH_PCM0_TX,
43 [1] = { 44 .rqtype = MEMTODEV,
44 .start = IRQ_PDMA0, 45 }, {
45 .end = IRQ_PDMA0, 46 .peri_id = (u8)DMACH_PCM2_RX,
46 .flags = IORESOURCE_IRQ, 47 .rqtype = DEVTOMEM,
48 }, {
49 .peri_id = (u8)DMACH_PCM2_TX,
50 .rqtype = MEMTODEV,
51 }, {
52 .peri_id = (u8)DMACH_MSM_REQ0,
53 }, {
54 .peri_id = (u8)DMACH_MSM_REQ2,
55 }, {
56 .peri_id = (u8)DMACH_SPI0_RX,
57 .rqtype = DEVTOMEM,
58 }, {
59 .peri_id = (u8)DMACH_SPI0_TX,
60 .rqtype = MEMTODEV,
61 }, {
62 .peri_id = (u8)DMACH_SPI2_RX,
63 .rqtype = DEVTOMEM,
64 }, {
65 .peri_id = (u8)DMACH_SPI2_TX,
66 .rqtype = MEMTODEV,
67 }, {
68 .peri_id = (u8)DMACH_I2S0S_TX,
69 .rqtype = MEMTODEV,
70 }, {
71 .peri_id = (u8)DMACH_I2S0_RX,
72 .rqtype = DEVTOMEM,
73 }, {
74 .peri_id = (u8)DMACH_I2S0_TX,
75 .rqtype = MEMTODEV,
76 }, {
77 .peri_id = (u8)DMACH_UART0_RX,
78 .rqtype = DEVTOMEM,
79 }, {
80 .peri_id = (u8)DMACH_UART0_TX,
81 .rqtype = MEMTODEV,
82 }, {
83 .peri_id = (u8)DMACH_UART2_RX,
84 .rqtype = DEVTOMEM,
85 }, {
86 .peri_id = (u8)DMACH_UART2_TX,
87 .rqtype = MEMTODEV,
88 }, {
89 .peri_id = (u8)DMACH_UART4_RX,
90 .rqtype = DEVTOMEM,
91 }, {
92 .peri_id = (u8)DMACH_UART4_TX,
93 .rqtype = MEMTODEV,
94 }, {
95 .peri_id = (u8)DMACH_SLIMBUS0_RX,
96 .rqtype = DEVTOMEM,
97 }, {
98 .peri_id = (u8)DMACH_SLIMBUS0_TX,
99 .rqtype = MEMTODEV,
100 }, {
101 .peri_id = (u8)DMACH_SLIMBUS2_RX,
102 .rqtype = DEVTOMEM,
103 }, {
104 .peri_id = (u8)DMACH_SLIMBUS2_TX,
105 .rqtype = MEMTODEV,
106 }, {
107 .peri_id = (u8)DMACH_SLIMBUS4_RX,
108 .rqtype = DEVTOMEM,
109 }, {
110 .peri_id = (u8)DMACH_SLIMBUS4_TX,
111 .rqtype = MEMTODEV,
112 }, {
113 .peri_id = (u8)DMACH_AC97_MICIN,
114 .rqtype = DEVTOMEM,
115 }, {
116 .peri_id = (u8)DMACH_AC97_PCMIN,
117 .rqtype = DEVTOMEM,
118 }, {
119 .peri_id = (u8)DMACH_AC97_PCMOUT,
120 .rqtype = MEMTODEV,
47 }, 121 },
48}; 122};
49 123
50static struct s3c_pl330_platdata exynos4_pdma0_pdata = { 124struct dma_pl330_platdata exynos4_pdma0_pdata = {
51 .peri = { 125 .nr_valid_peri = ARRAY_SIZE(pdma0_peri),
52 [0] = DMACH_PCM0_RX, 126 .peri = pdma0_peri,
53 [1] = DMACH_PCM0_TX,
54 [2] = DMACH_PCM2_RX,
55 [3] = DMACH_PCM2_TX,
56 [4] = DMACH_MSM_REQ0,
57 [5] = DMACH_MSM_REQ2,
58 [6] = DMACH_SPI0_RX,
59 [7] = DMACH_SPI0_TX,
60 [8] = DMACH_SPI2_RX,
61 [9] = DMACH_SPI2_TX,
62 [10] = DMACH_I2S0S_TX,
63 [11] = DMACH_I2S0_RX,
64 [12] = DMACH_I2S0_TX,
65 [13] = DMACH_I2S2_RX,
66 [14] = DMACH_I2S2_TX,
67 [15] = DMACH_UART0_RX,
68 [16] = DMACH_UART0_TX,
69 [17] = DMACH_UART2_RX,
70 [18] = DMACH_UART2_TX,
71 [19] = DMACH_UART4_RX,
72 [20] = DMACH_UART4_TX,
73 [21] = DMACH_SLIMBUS0_RX,
74 [22] = DMACH_SLIMBUS0_TX,
75 [23] = DMACH_SLIMBUS2_RX,
76 [24] = DMACH_SLIMBUS2_TX,
77 [25] = DMACH_SLIMBUS4_RX,
78 [26] = DMACH_SLIMBUS4_TX,
79 [27] = DMACH_AC97_MICIN,
80 [28] = DMACH_AC97_PCMIN,
81 [29] = DMACH_AC97_PCMOUT,
82 [30] = DMACH_MAX,
83 [31] = DMACH_MAX,
84 },
85}; 127};
86 128
87static struct platform_device exynos4_device_pdma0 = { 129struct amba_device exynos4_device_pdma0 = {
88 .name = "s3c-pl330", 130 .dev = {
89 .id = 0, 131 .init_name = "dma-pl330.0",
90 .num_resources = ARRAY_SIZE(exynos4_pdma0_resource),
91 .resource = exynos4_pdma0_resource,
92 .dev = {
93 .dma_mask = &dma_dmamask, 132 .dma_mask = &dma_dmamask,
94 .coherent_dma_mask = DMA_BIT_MASK(32), 133 .coherent_dma_mask = DMA_BIT_MASK(32),
95 .platform_data = &exynos4_pdma0_pdata, 134 .platform_data = &exynos4_pdma0_pdata,
96 }, 135 },
136 .res = {
137 .start = EXYNOS4_PA_PDMA0,
138 .end = EXYNOS4_PA_PDMA0 + SZ_4K,
139 .flags = IORESOURCE_MEM,
140 },
141 .irq = {IRQ_PDMA0, NO_IRQ},
142 .periphid = 0x00041330,
97}; 143};
98 144
99static struct resource exynos4_pdma1_resource[] = { 145struct dma_pl330_peri pdma1_peri[25] = {
100 [0] = { 146 {
101 .start = EXYNOS4_PA_PDMA1, 147 .peri_id = (u8)DMACH_PCM0_RX,
102 .end = EXYNOS4_PA_PDMA1 + SZ_4K, 148 .rqtype = DEVTOMEM,
103 .flags = IORESOURCE_MEM, 149 }, {
104 }, 150 .peri_id = (u8)DMACH_PCM0_TX,
105 [1] = { 151 .rqtype = MEMTODEV,
106 .start = IRQ_PDMA1, 152 }, {
107 .end = IRQ_PDMA1, 153 .peri_id = (u8)DMACH_PCM1_RX,
108 .flags = IORESOURCE_IRQ, 154 .rqtype = DEVTOMEM,
155 }, {
156 .peri_id = (u8)DMACH_PCM1_TX,
157 .rqtype = MEMTODEV,
158 }, {
159 .peri_id = (u8)DMACH_MSM_REQ1,
160 }, {
161 .peri_id = (u8)DMACH_MSM_REQ3,
162 }, {
163 .peri_id = (u8)DMACH_SPI1_RX,
164 .rqtype = DEVTOMEM,
165 }, {
166 .peri_id = (u8)DMACH_SPI1_TX,
167 .rqtype = MEMTODEV,
168 }, {
169 .peri_id = (u8)DMACH_I2S0S_TX,
170 .rqtype = MEMTODEV,
171 }, {
172 .peri_id = (u8)DMACH_I2S0_RX,
173 .rqtype = DEVTOMEM,
174 }, {
175 .peri_id = (u8)DMACH_I2S0_TX,
176 .rqtype = MEMTODEV,
177 }, {
178 .peri_id = (u8)DMACH_I2S1_RX,
179 .rqtype = DEVTOMEM,
180 }, {
181 .peri_id = (u8)DMACH_I2S1_TX,
182 .rqtype = MEMTODEV,
183 }, {
184 .peri_id = (u8)DMACH_UART0_RX,
185 .rqtype = DEVTOMEM,
186 }, {
187 .peri_id = (u8)DMACH_UART0_TX,
188 .rqtype = MEMTODEV,
189 }, {
190 .peri_id = (u8)DMACH_UART1_RX,
191 .rqtype = DEVTOMEM,
192 }, {
193 .peri_id = (u8)DMACH_UART1_TX,
194 .rqtype = MEMTODEV,
195 }, {
196 .peri_id = (u8)DMACH_UART3_RX,
197 .rqtype = DEVTOMEM,
198 }, {
199 .peri_id = (u8)DMACH_UART3_TX,
200 .rqtype = MEMTODEV,
201 }, {
202 .peri_id = (u8)DMACH_SLIMBUS1_RX,
203 .rqtype = DEVTOMEM,
204 }, {
205 .peri_id = (u8)DMACH_SLIMBUS1_TX,
206 .rqtype = MEMTODEV,
207 }, {
208 .peri_id = (u8)DMACH_SLIMBUS3_RX,
209 .rqtype = DEVTOMEM,
210 }, {
211 .peri_id = (u8)DMACH_SLIMBUS3_TX,
212 .rqtype = MEMTODEV,
213 }, {
214 .peri_id = (u8)DMACH_SLIMBUS5_RX,
215 .rqtype = DEVTOMEM,
216 }, {
217 .peri_id = (u8)DMACH_SLIMBUS5_TX,
218 .rqtype = MEMTODEV,
109 }, 219 },
110}; 220};
111 221
112static struct s3c_pl330_platdata exynos4_pdma1_pdata = { 222struct dma_pl330_platdata exynos4_pdma1_pdata = {
113 .peri = { 223 .nr_valid_peri = ARRAY_SIZE(pdma1_peri),
114 [0] = DMACH_PCM0_RX, 224 .peri = pdma1_peri,
115 [1] = DMACH_PCM0_TX,
116 [2] = DMACH_PCM1_RX,
117 [3] = DMACH_PCM1_TX,
118 [4] = DMACH_MSM_REQ1,
119 [5] = DMACH_MSM_REQ3,
120 [6] = DMACH_SPI1_RX,
121 [7] = DMACH_SPI1_TX,
122 [8] = DMACH_I2S0S_TX,
123 [9] = DMACH_I2S0_RX,
124 [10] = DMACH_I2S0_TX,
125 [11] = DMACH_I2S1_RX,
126 [12] = DMACH_I2S1_TX,
127 [13] = DMACH_UART0_RX,
128 [14] = DMACH_UART0_TX,
129 [15] = DMACH_UART1_RX,
130 [16] = DMACH_UART1_TX,
131 [17] = DMACH_UART3_RX,
132 [18] = DMACH_UART3_TX,
133 [19] = DMACH_SLIMBUS1_RX,
134 [20] = DMACH_SLIMBUS1_TX,
135 [21] = DMACH_SLIMBUS3_RX,
136 [22] = DMACH_SLIMBUS3_TX,
137 [23] = DMACH_SLIMBUS5_RX,
138 [24] = DMACH_SLIMBUS5_TX,
139 [25] = DMACH_SLIMBUS0AUX_RX,
140 [26] = DMACH_SLIMBUS0AUX_TX,
141 [27] = DMACH_SPDIF,
142 [28] = DMACH_MAX,
143 [29] = DMACH_MAX,
144 [30] = DMACH_MAX,
145 [31] = DMACH_MAX,
146 },
147}; 225};
148 226
149static struct platform_device exynos4_device_pdma1 = { 227struct amba_device exynos4_device_pdma1 = {
150 .name = "s3c-pl330", 228 .dev = {
151 .id = 1, 229 .init_name = "dma-pl330.1",
152 .num_resources = ARRAY_SIZE(exynos4_pdma1_resource),
153 .resource = exynos4_pdma1_resource,
154 .dev = {
155 .dma_mask = &dma_dmamask, 230 .dma_mask = &dma_dmamask,
156 .coherent_dma_mask = DMA_BIT_MASK(32), 231 .coherent_dma_mask = DMA_BIT_MASK(32),
157 .platform_data = &exynos4_pdma1_pdata, 232 .platform_data = &exynos4_pdma1_pdata,
158 }, 233 },
159}; 234 .res = {
160 235 .start = EXYNOS4_PA_PDMA1,
161static struct platform_device *exynos4_dmacs[] __initdata = { 236 .end = EXYNOS4_PA_PDMA1 + SZ_4K,
162 &exynos4_device_pdma0, 237 .flags = IORESOURCE_MEM,
163 &exynos4_device_pdma1, 238 },
239 .irq = {IRQ_PDMA1, NO_IRQ},
240 .periphid = 0x00041330,
164}; 241};
165 242
166static int __init exynos4_dma_init(void) 243static int __init exynos4_dma_init(void)
167{ 244{
168 platform_add_devices(exynos4_dmacs, ARRAY_SIZE(exynos4_dmacs)); 245 amba_device_register(&exynos4_device_pdma0, &iomem_resource);
246 amba_device_register(&exynos4_device_pdma1, &iomem_resource);
169 247
170 return 0; 248 return 0;
171} 249}
diff --git a/arch/arm/mach-exynos4/include/mach/dma.h b/arch/arm/mach-exynos4/include/mach/dma.h
index 81209eb1409..201842a3769 100644
--- a/arch/arm/mach-exynos4/include/mach/dma.h
+++ b/arch/arm/mach-exynos4/include/mach/dma.h
@@ -20,7 +20,7 @@
20#ifndef __MACH_DMA_H 20#ifndef __MACH_DMA_H
21#define __MACH_DMA_H 21#define __MACH_DMA_H
22 22
23/* This platform uses the common S3C DMA API driver for PL330 */ 23/* This platform uses the common DMA API driver for PL330 */
24#include <plat/s3c-dma-pl330.h> 24#include <plat/dma-pl330.h>
25 25
26#endif /* __MACH_DMA_H */ 26#endif /* __MACH_DMA_H */
diff --git a/arch/arm/mach-exynos4/include/mach/i2c-hdmiphy.h b/arch/arm/mach-exynos4/include/mach/i2c-hdmiphy.h
new file mode 100644
index 00000000000..9dbe3179ad5
--- /dev/null
+++ b/arch/arm/mach-exynos4/include/mach/i2c-hdmiphy.h
@@ -0,0 +1,16 @@
1/*
2 * Copyright (C) 2011 Samsung Electronics Co., Ltd.
3 *
4 * S5P series i2c hdmiphy helper definitions
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef PLAT_S5P_I2C_HDMIPHY_H_
12#define PLAT_S5P_I2C_HDMIPHY_H_
13
14#define S5P_I2C_HDMIPHY_BUS_NUM (8)
15
16#endif
diff --git a/arch/arm/mach-exynos4/include/mach/irqs.h b/arch/arm/mach-exynos4/include/mach/irqs.h
index f8952f8f375..62093b9339d 100644
--- a/arch/arm/mach-exynos4/include/mach/irqs.h
+++ b/arch/arm/mach-exynos4/include/mach/irqs.h
@@ -93,7 +93,11 @@
93#define IRQ_2D IRQ_SPI(89) 93#define IRQ_2D IRQ_SPI(89)
94#define IRQ_PCIE IRQ_SPI(90) 94#define IRQ_PCIE IRQ_SPI(90)
95 95
96#define IRQ_MIXER IRQ_SPI(91)
97#define IRQ_HDMI IRQ_SPI(92)
98#define IRQ_IIC_HDMIPHY IRQ_SPI(93)
96#define IRQ_MFC IRQ_SPI(94) 99#define IRQ_MFC IRQ_SPI(94)
100#define IRQ_SDO IRQ_SPI(95)
97 101
98#define IRQ_AUDIO_SS IRQ_SPI(96) 102#define IRQ_AUDIO_SS IRQ_SPI(96)
99#define IRQ_I2S0 IRQ_SPI(97) 103#define IRQ_I2S0 IRQ_SPI(97)
diff --git a/arch/arm/mach-exynos4/include/mach/map.h b/arch/arm/mach-exynos4/include/mach/map.h
index 7073ac73085..1bea7d139bb 100644
--- a/arch/arm/mach-exynos4/include/mach/map.h
+++ b/arch/arm/mach-exynos4/include/mach/map.h
@@ -113,6 +113,12 @@
113 113
114#define EXYNOS4_PA_UART 0x13800000 114#define EXYNOS4_PA_UART 0x13800000
115 115
116#define EXYNOS4_PA_VP 0x12C00000
117#define EXYNOS4_PA_MIXER 0x12C10000
118#define EXYNOS4_PA_SDO 0x12C20000
119#define EXYNOS4_PA_HDMI 0x12D00000
120#define EXYNOS4_PA_IIC_HDMIPHY 0x138E0000
121
116#define EXYNOS4_PA_IIC(x) (0x13860000 + ((x) * 0x10000)) 122#define EXYNOS4_PA_IIC(x) (0x13860000 + ((x) * 0x10000))
117 123
118#define EXYNOS4_PA_ADC 0x13910000 124#define EXYNOS4_PA_ADC 0x13910000
@@ -162,6 +168,12 @@
162#define S5P_PA_TIMER EXYNOS4_PA_TIMER 168#define S5P_PA_TIMER EXYNOS4_PA_TIMER
163#define S5P_PA_EHCI EXYNOS4_PA_EHCI 169#define S5P_PA_EHCI EXYNOS4_PA_EHCI
164 170
171#define S5P_PA_SDO EXYNOS4_PA_SDO
172#define S5P_PA_VP EXYNOS4_PA_VP
173#define S5P_PA_MIXER EXYNOS4_PA_MIXER
174#define S5P_PA_HDMI EXYNOS4_PA_HDMI
175#define S5P_PA_IIC_HDMIPHY EXYNOS4_PA_IIC_HDMIPHY
176
165#define SAMSUNG_PA_KEYPAD EXYNOS4_PA_KEYPAD 177#define SAMSUNG_PA_KEYPAD EXYNOS4_PA_KEYPAD
166 178
167/* UART */ 179/* UART */
diff --git a/arch/arm/mach-exynos4/include/mach/pm-core.h b/arch/arm/mach-exynos4/include/mach/pm-core.h
index 1df3b81f96e..9d8da51e35c 100644
--- a/arch/arm/mach-exynos4/include/mach/pm-core.h
+++ b/arch/arm/mach-exynos4/include/mach/pm-core.h
@@ -14,6 +14,10 @@
14 * it under the terms of the GNU General Public License version 2 as 14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation. 15 * published by the Free Software Foundation.
16*/ 16*/
17
18#ifndef __ASM_ARCH_PM_CORE_H
19#define __ASM_ARCH_PM_CORE_H __FILE__
20
17#include <mach/regs-pmu.h> 21#include <mach/regs-pmu.h>
18 22
19static inline void s3c_pm_debug_init_uart(void) 23static inline void s3c_pm_debug_init_uart(void)
@@ -53,7 +57,9 @@ static inline void s3c_pm_restored_gpios(void)
53 /* nothing here yet */ 57 /* nothing here yet */
54} 58}
55 59
56static inline void s3c_pm_saved_gpios(void) 60static inline void samsung_pm_saved_gpios(void)
57{ 61{
58 /* nothing here yet */ 62 /* nothing here yet */
59} 63}
64
65#endif /* __ASM_ARCH_PM_CORE_H */
diff --git a/arch/arm/mach-exynos4/include/mach/pmu.h b/arch/arm/mach-exynos4/include/mach/pmu.h
index a952904b010..632dd563013 100644
--- a/arch/arm/mach-exynos4/include/mach/pmu.h
+++ b/arch/arm/mach-exynos4/include/mach/pmu.h
@@ -13,6 +13,8 @@
13#ifndef __ASM_ARCH_PMU_H 13#ifndef __ASM_ARCH_PMU_H
14#define __ASM_ARCH_PMU_H __FILE__ 14#define __ASM_ARCH_PMU_H __FILE__
15 15
16#define PMU_TABLE_END NULL
17
16enum sys_powerdown { 18enum sys_powerdown {
17 SYS_AFTR, 19 SYS_AFTR,
18 SYS_LPA, 20 SYS_LPA,
@@ -20,6 +22,11 @@ enum sys_powerdown {
20 NUM_SYS_POWERDOWN, 22 NUM_SYS_POWERDOWN,
21}; 23};
22 24
25struct exynos4_pmu_conf {
26 void __iomem *reg;
27 unsigned int val[NUM_SYS_POWERDOWN];
28};
29
23extern void exynos4_sys_powerdown_conf(enum sys_powerdown mode); 30extern void exynos4_sys_powerdown_conf(enum sys_powerdown mode);
24 31
25#endif /* __ASM_ARCH_PMU_H */ 32#endif /* __ASM_ARCH_PMU_H */
diff --git a/arch/arm/mach-exynos4/include/mach/regs-pmu.h b/arch/arm/mach-exynos4/include/mach/regs-pmu.h
index cdf9b47c303..4fff8e938fe 100644
--- a/arch/arm/mach-exynos4/include/mach/regs-pmu.h
+++ b/arch/arm/mach-exynos4/include/mach/regs-pmu.h
@@ -25,9 +25,10 @@
25 25
26#define S5P_USE_STANDBY_WFI0 (1 << 16) 26#define S5P_USE_STANDBY_WFI0 (1 << 16)
27#define S5P_USE_STANDBY_WFI1 (1 << 17) 27#define S5P_USE_STANDBY_WFI1 (1 << 17)
28#define S5P_USE_STANDBYWFI_ISP_ARM (1 << 18)
28#define S5P_USE_STANDBY_WFE0 (1 << 24) 29#define S5P_USE_STANDBY_WFE0 (1 << 24)
29#define S5P_USE_STANDBY_WFE1 (1 << 25) 30#define S5P_USE_STANDBY_WFE1 (1 << 25)
30#define S5P_USE_MASK ((0x3 << 16) | (0x3 << 24)) 31#define S5P_USE_STANDBYWFE_ISP_ARM (1 << 26)
31 32
32#define S5P_SWRESET S5P_PMUREG(0x0400) 33#define S5P_SWRESET S5P_PMUREG(0x0400)
33 34
@@ -35,15 +36,17 @@
35#define S5P_EINT_WAKEUP_MASK S5P_PMUREG(0x0604) 36#define S5P_EINT_WAKEUP_MASK S5P_PMUREG(0x0604)
36#define S5P_WAKEUP_MASK S5P_PMUREG(0x0608) 37#define S5P_WAKEUP_MASK S5P_PMUREG(0x0608)
37 38
38#define S5P_USBHOST_PHY_CONTROL S5P_PMUREG(0x0708) 39#define S5P_HDMI_PHY_CONTROL S5P_PMUREG(0x0700)
39#define S5P_USBHOST_PHY_ENABLE (1 << 0) 40#define S5P_HDMI_PHY_ENABLE (1 << 0)
41
42#define S5P_DAC_PHY_CONTROL S5P_PMUREG(0x070C)
43#define S5P_DAC_PHY_ENABLE (1 << 0)
40 44
41#define S5P_MIPI_DPHY_CONTROL(n) S5P_PMUREG(0x0710 + (n) * 4) 45#define S5P_MIPI_DPHY_CONTROL(n) S5P_PMUREG(0x0710 + (n) * 4)
42#define S5P_MIPI_DPHY_ENABLE (1 << 0) 46#define S5P_MIPI_DPHY_ENABLE (1 << 0)
43#define S5P_MIPI_DPHY_SRESETN (1 << 1) 47#define S5P_MIPI_DPHY_SRESETN (1 << 1)
44#define S5P_MIPI_DPHY_MRESETN (1 << 2) 48#define S5P_MIPI_DPHY_MRESETN (1 << 2)
45 49
46#define S5P_PMU_SATA_PHY_CONTROL S5P_PMUREG(0x0720)
47#define S5P_INFORM0 S5P_PMUREG(0x0800) 50#define S5P_INFORM0 S5P_PMUREG(0x0800)
48#define S5P_INFORM1 S5P_PMUREG(0x0804) 51#define S5P_INFORM1 S5P_PMUREG(0x0804)
49#define S5P_INFORM2 S5P_PMUREG(0x0808) 52#define S5P_INFORM2 S5P_PMUREG(0x0808)
@@ -76,7 +79,6 @@
76#define S5P_CMU_CLKSTOP_MFC_LOWPWR S5P_PMUREG(0x1148) 79#define S5P_CMU_CLKSTOP_MFC_LOWPWR S5P_PMUREG(0x1148)
77#define S5P_CMU_CLKSTOP_G3D_LOWPWR S5P_PMUREG(0x114C) 80#define S5P_CMU_CLKSTOP_G3D_LOWPWR S5P_PMUREG(0x114C)
78#define S5P_CMU_CLKSTOP_LCD0_LOWPWR S5P_PMUREG(0x1150) 81#define S5P_CMU_CLKSTOP_LCD0_LOWPWR S5P_PMUREG(0x1150)
79#define S5P_CMU_CLKSTOP_LCD1_LOWPWR S5P_PMUREG(0x1154)
80#define S5P_CMU_CLKSTOP_MAUDIO_LOWPWR S5P_PMUREG(0x1158) 82#define S5P_CMU_CLKSTOP_MAUDIO_LOWPWR S5P_PMUREG(0x1158)
81#define S5P_CMU_CLKSTOP_GPS_LOWPWR S5P_PMUREG(0x115C) 83#define S5P_CMU_CLKSTOP_GPS_LOWPWR S5P_PMUREG(0x115C)
82#define S5P_CMU_RESET_CAM_LOWPWR S5P_PMUREG(0x1160) 84#define S5P_CMU_RESET_CAM_LOWPWR S5P_PMUREG(0x1160)
@@ -84,7 +86,6 @@
84#define S5P_CMU_RESET_MFC_LOWPWR S5P_PMUREG(0x1168) 86#define S5P_CMU_RESET_MFC_LOWPWR S5P_PMUREG(0x1168)
85#define S5P_CMU_RESET_G3D_LOWPWR S5P_PMUREG(0x116C) 87#define S5P_CMU_RESET_G3D_LOWPWR S5P_PMUREG(0x116C)
86#define S5P_CMU_RESET_LCD0_LOWPWR S5P_PMUREG(0x1170) 88#define S5P_CMU_RESET_LCD0_LOWPWR S5P_PMUREG(0x1170)
87#define S5P_CMU_RESET_LCD1_LOWPWR S5P_PMUREG(0x1174)
88#define S5P_CMU_RESET_MAUDIO_LOWPWR S5P_PMUREG(0x1178) 89#define S5P_CMU_RESET_MAUDIO_LOWPWR S5P_PMUREG(0x1178)
89#define S5P_CMU_RESET_GPS_LOWPWR S5P_PMUREG(0x117C) 90#define S5P_CMU_RESET_GPS_LOWPWR S5P_PMUREG(0x117C)
90#define S5P_TOP_BUS_LOWPWR S5P_PMUREG(0x1180) 91#define S5P_TOP_BUS_LOWPWR S5P_PMUREG(0x1180)
@@ -92,14 +93,11 @@
92#define S5P_TOP_PWR_LOWPWR S5P_PMUREG(0x1188) 93#define S5P_TOP_PWR_LOWPWR S5P_PMUREG(0x1188)
93#define S5P_LOGIC_RESET_LOWPWR S5P_PMUREG(0x11A0) 94#define S5P_LOGIC_RESET_LOWPWR S5P_PMUREG(0x11A0)
94#define S5P_ONENAND_MEM_LOWPWR S5P_PMUREG(0x11C0) 95#define S5P_ONENAND_MEM_LOWPWR S5P_PMUREG(0x11C0)
95#define S5P_MODIMIF_MEM_LOWPWR S5P_PMUREG(0x11C4)
96#define S5P_G2D_ACP_MEM_LOWPWR S5P_PMUREG(0x11C8) 96#define S5P_G2D_ACP_MEM_LOWPWR S5P_PMUREG(0x11C8)
97#define S5P_USBOTG_MEM_LOWPWR S5P_PMUREG(0x11CC) 97#define S5P_USBOTG_MEM_LOWPWR S5P_PMUREG(0x11CC)
98#define S5P_HSMMC_MEM_LOWPWR S5P_PMUREG(0x11D0) 98#define S5P_HSMMC_MEM_LOWPWR S5P_PMUREG(0x11D0)
99#define S5P_CSSYS_MEM_LOWPWR S5P_PMUREG(0x11D4) 99#define S5P_CSSYS_MEM_LOWPWR S5P_PMUREG(0x11D4)
100#define S5P_SECSS_MEM_LOWPWR S5P_PMUREG(0x11D8) 100#define S5P_SECSS_MEM_LOWPWR S5P_PMUREG(0x11D8)
101#define S5P_PCIE_MEM_LOWPWR S5P_PMUREG(0x11E0)
102#define S5P_SATA_MEM_LOWPWR S5P_PMUREG(0x11E4)
103#define S5P_PAD_RETENTION_DRAM_LOWPWR S5P_PMUREG(0x1200) 101#define S5P_PAD_RETENTION_DRAM_LOWPWR S5P_PMUREG(0x1200)
104#define S5P_PAD_RETENTION_MAUDIO_LOWPWR S5P_PMUREG(0x1204) 102#define S5P_PAD_RETENTION_MAUDIO_LOWPWR S5P_PMUREG(0x1204)
105#define S5P_PAD_RETENTION_GPIO_LOWPWR S5P_PMUREG(0x1220) 103#define S5P_PAD_RETENTION_GPIO_LOWPWR S5P_PMUREG(0x1220)
@@ -120,7 +118,6 @@
120#define S5P_MFC_LOWPWR S5P_PMUREG(0x1388) 118#define S5P_MFC_LOWPWR S5P_PMUREG(0x1388)
121#define S5P_G3D_LOWPWR S5P_PMUREG(0x138C) 119#define S5P_G3D_LOWPWR S5P_PMUREG(0x138C)
122#define S5P_LCD0_LOWPWR S5P_PMUREG(0x1390) 120#define S5P_LCD0_LOWPWR S5P_PMUREG(0x1390)
123#define S5P_LCD1_LOWPWR S5P_PMUREG(0x1394)
124#define S5P_MAUDIO_LOWPWR S5P_PMUREG(0x1398) 121#define S5P_MAUDIO_LOWPWR S5P_PMUREG(0x1398)
125#define S5P_GPS_LOWPWR S5P_PMUREG(0x139C) 122#define S5P_GPS_LOWPWR S5P_PMUREG(0x139C)
126#define S5P_GPS_ALIVE_LOWPWR S5P_PMUREG(0x13A0) 123#define S5P_GPS_ALIVE_LOWPWR S5P_PMUREG(0x13A0)
@@ -156,7 +153,6 @@
156#define S5P_PMU_MFC_CONF S5P_PMUREG(0x3C40) 153#define S5P_PMU_MFC_CONF S5P_PMUREG(0x3C40)
157#define S5P_PMU_G3D_CONF S5P_PMUREG(0x3C60) 154#define S5P_PMU_G3D_CONF S5P_PMUREG(0x3C60)
158#define S5P_PMU_LCD0_CONF S5P_PMUREG(0x3C80) 155#define S5P_PMU_LCD0_CONF S5P_PMUREG(0x3C80)
159#define S5P_PMU_LCD1_CONF S5P_PMUREG(0x3CA0)
160#define S5P_PMU_GPS_CONF S5P_PMUREG(0x3CE0) 156#define S5P_PMU_GPS_CONF S5P_PMUREG(0x3CE0)
161 157
162#define S5P_PMU_SATA_PHY_CONTROL_EN 0x1 158#define S5P_PMU_SATA_PHY_CONTROL_EN 0x1
@@ -165,4 +161,60 @@
165 161
166#define S5P_CHECK_SLEEP 0x00000BAD 162#define S5P_CHECK_SLEEP 0x00000BAD
167 163
164/* Only for EXYNOS4210 */
165#define S5P_USBHOST_PHY_CONTROL S5P_PMUREG(0x0708)
166#define S5P_USBHOST_PHY_ENABLE (1 << 0)
167
168#define S5P_PMU_SATA_PHY_CONTROL S5P_PMUREG(0x0720)
169
170#define S5P_CMU_CLKSTOP_LCD1_LOWPWR S5P_PMUREG(0x1154)
171#define S5P_CMU_RESET_LCD1_LOWPWR S5P_PMUREG(0x1174)
172#define S5P_MODIMIF_MEM_LOWPWR S5P_PMUREG(0x11C4)
173#define S5P_PCIE_MEM_LOWPWR S5P_PMUREG(0x11E0)
174#define S5P_SATA_MEM_LOWPWR S5P_PMUREG(0x11E4)
175#define S5P_LCD1_LOWPWR S5P_PMUREG(0x1394)
176
177#define S5P_PMU_LCD1_CONF S5P_PMUREG(0x3CA0)
178
179/* Only for EXYNOS4212 */
180#define S5P_ISP_ARM_LOWPWR S5P_PMUREG(0x1050)
181#define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR S5P_PMUREG(0x1054)
182#define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR S5P_PMUREG(0x1058)
183#define S5P_CMU_ACLKSTOP_COREBLK_LOWPWR S5P_PMUREG(0x1110)
184#define S5P_CMU_SCLKSTOP_COREBLK_LOWPWR S5P_PMUREG(0x1114)
185#define S5P_CMU_RESET_COREBLK_LOWPWR S5P_PMUREG(0x111C)
186#define S5P_MPLLUSER_SYSCLK_LOWPWR S5P_PMUREG(0x1130)
187#define S5P_CMU_CLKSTOP_ISP_LOWPWR S5P_PMUREG(0x1154)
188#define S5P_CMU_RESET_ISP_LOWPWR S5P_PMUREG(0x1174)
189#define S5P_TOP_BUS_COREBLK_LOWPWR S5P_PMUREG(0x1190)
190#define S5P_TOP_RETENTION_COREBLK_LOWPWR S5P_PMUREG(0x1194)
191#define S5P_TOP_PWR_COREBLK_LOWPWR S5P_PMUREG(0x1198)
192#define S5P_OSCCLK_GATE_LOWPWR S5P_PMUREG(0x11A4)
193#define S5P_LOGIC_RESET_COREBLK_LOWPWR S5P_PMUREG(0x11B0)
194#define S5P_OSCCLK_GATE_COREBLK_LOWPWR S5P_PMUREG(0x11B4)
195#define S5P_HSI_MEM_LOWPWR S5P_PMUREG(0x11C4)
196#define S5P_ROTATOR_MEM_LOWPWR S5P_PMUREG(0x11DC)
197#define S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR S5P_PMUREG(0x123C)
198#define S5P_PAD_ISOLATION_COREBLK_LOWPWR S5P_PMUREG(0x1250)
199#define S5P_GPIO_MODE_COREBLK_LOWPWR S5P_PMUREG(0x1320)
200#define S5P_TOP_ASB_RESET_LOWPWR S5P_PMUREG(0x1344)
201#define S5P_TOP_ASB_ISOLATION_LOWPWR S5P_PMUREG(0x1348)
202#define S5P_ISP_LOWPWR S5P_PMUREG(0x1394)
203#define S5P_DRAM_FREQ_DOWN_LOWPWR S5P_PMUREG(0x13B0)
204#define S5P_DDRPHY_DLLOFF_LOWPWR S5P_PMUREG(0x13B4)
205#define S5P_CMU_SYSCLK_ISP_LOWPWR S5P_PMUREG(0x13B8)
206#define S5P_CMU_SYSCLK_GPS_LOWPWR S5P_PMUREG(0x13BC)
207#define S5P_LPDDR_PHY_DLL_LOCK_LOWPWR S5P_PMUREG(0x13C0)
208
209#define S5P_ARM_L2_0_OPTION S5P_PMUREG(0x2608)
210#define S5P_ARM_L2_1_OPTION S5P_PMUREG(0x2628)
211#define S5P_ONENAND_MEM_OPTION S5P_PMUREG(0x2E08)
212#define S5P_HSI_MEM_OPTION S5P_PMUREG(0x2E28)
213#define S5P_G2D_ACP_MEM_OPTION S5P_PMUREG(0x2E48)
214#define S5P_USBOTG_MEM_OPTION S5P_PMUREG(0x2E68)
215#define S5P_HSMMC_MEM_OPTION S5P_PMUREG(0x2E88)
216#define S5P_CSSYS_MEM_OPTION S5P_PMUREG(0x2EA8)
217#define S5P_SECSS_MEM_OPTION S5P_PMUREG(0x2EC8)
218#define S5P_ROTATOR_MEM_OPTION S5P_PMUREG(0x2F48)
219
168#endif /* __ASM_ARCH_REGS_PMU_H */ 220#endif /* __ASM_ARCH_REGS_PMU_H */
diff --git a/arch/arm/mach-exynos4/mach-nuri.c b/arch/arm/mach-exynos4/mach-nuri.c
index 43be71b799c..bbd13f45415 100644
--- a/arch/arm/mach-exynos4/mach-nuri.c
+++ b/arch/arm/mach-exynos4/mach-nuri.c
@@ -32,10 +32,12 @@
32#include <asm/mach-types.h> 32#include <asm/mach-types.h>
33 33
34#include <plat/adc.h> 34#include <plat/adc.h>
35#include <plat/regs-fb-v4.h>
35#include <plat/regs-serial.h> 36#include <plat/regs-serial.h>
36#include <plat/exynos4.h> 37#include <plat/exynos4.h>
37#include <plat/cpu.h> 38#include <plat/cpu.h>
38#include <plat/devs.h> 39#include <plat/devs.h>
40#include <plat/fb.h>
39#include <plat/sdhci.h> 41#include <plat/sdhci.h>
40#include <plat/ehci.h> 42#include <plat/ehci.h>
41#include <plat/clock.h> 43#include <plat/clock.h>
@@ -199,6 +201,33 @@ static struct platform_device nuri_gpio_keys = {
199 }, 201 },
200}; 202};
201 203
204/* Frame Buffer */
205static struct s3c_fb_pd_win nuri_fb_win0 = {
206 .win_mode = {
207 .left_margin = 64,
208 .right_margin = 16,
209 .upper_margin = 64,
210 .lower_margin = 1,
211 .hsync_len = 48,
212 .vsync_len = 3,
213 .xres = 1280,
214 .yres = 800,
215 .refresh = 60,
216 },
217 .max_bpp = 24,
218 .default_bpp = 16,
219 .virtual_x = 1280,
220 .virtual_y = 800,
221};
222
223static struct s3c_fb_platdata nuri_fb_pdata __initdata = {
224 .win[0] = &nuri_fb_win0,
225 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB |
226 VIDCON0_CLKSEL_LCD,
227 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
228 .setup_gpio = exynos4_fimd0_gpio_setup_24bpp,
229};
230
202static void nuri_lcd_power_on(struct plat_lcd_data *pd, unsigned int power) 231static void nuri_lcd_power_on(struct plat_lcd_data *pd, unsigned int power)
203{ 232{
204 int gpio = EXYNOS4_GPE1(5); 233 int gpio = EXYNOS4_GPE1(5);
@@ -1092,6 +1121,7 @@ static struct platform_device *nuri_devices[] __initdata = {
1092 /* Samsung Platform Devices */ 1121 /* Samsung Platform Devices */
1093 &s3c_device_i2c5, /* PMIC should initialize first */ 1122 &s3c_device_i2c5, /* PMIC should initialize first */
1094 &emmc_fixed_voltage, 1123 &emmc_fixed_voltage,
1124 &s5p_device_fimd0,
1095 &s3c_device_hsmmc0, 1125 &s3c_device_hsmmc0,
1096 &s3c_device_hsmmc2, 1126 &s3c_device_hsmmc2,
1097 &s3c_device_hsmmc3, 1127 &s3c_device_hsmmc3,
@@ -1106,6 +1136,7 @@ static struct platform_device *nuri_devices[] __initdata = {
1106 &s5p_device_mfc_l, 1136 &s5p_device_mfc_l,
1107 &s5p_device_mfc_r, 1137 &s5p_device_mfc_r,
1108 &exynos4_device_pd[PD_MFC], 1138 &exynos4_device_pd[PD_MFC],
1139 &exynos4_device_pd[PD_LCD0],
1109 1140
1110 /* NURI Devices */ 1141 /* NURI Devices */
1111 &nuri_gpio_keys, 1142 &nuri_gpio_keys,
@@ -1142,12 +1173,15 @@ static void __init nuri_machine_init(void)
1142 i2c9_devs[I2C9_MAX17042].irq = gpio_to_irq(EXYNOS4_GPX2(3)); 1173 i2c9_devs[I2C9_MAX17042].irq = gpio_to_irq(EXYNOS4_GPX2(3));
1143 i2c_register_board_info(9, i2c9_devs, ARRAY_SIZE(i2c9_devs)); 1174 i2c_register_board_info(9, i2c9_devs, ARRAY_SIZE(i2c9_devs));
1144 1175
1176 s5p_fimd0_set_platdata(&nuri_fb_pdata);
1177
1145 nuri_ehci_init(); 1178 nuri_ehci_init();
1146 clk_xusbxti.rate = 24000000; 1179 clk_xusbxti.rate = 24000000;
1147 1180
1148 /* Last */ 1181 /* Last */
1149 platform_add_devices(nuri_devices, ARRAY_SIZE(nuri_devices)); 1182 platform_add_devices(nuri_devices, ARRAY_SIZE(nuri_devices));
1150 s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev; 1183 s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
1184 s5p_device_fimd0.dev.parent = &exynos4_device_pd[PD_LCD0].dev;
1151} 1185}
1152 1186
1153MACHINE_START(NURI, "NURI") 1187MACHINE_START(NURI, "NURI")
diff --git a/arch/arm/mach-exynos4/mach-origen.c b/arch/arm/mach-exynos4/mach-origen.c
index ed59f86001a..18909cf6c07 100644
--- a/arch/arm/mach-exynos4/mach-origen.c
+++ b/arch/arm/mach-exynos4/mach-origen.c
@@ -14,16 +14,31 @@
14#include <linux/platform_device.h> 14#include <linux/platform_device.h>
15#include <linux/io.h> 15#include <linux/io.h>
16#include <linux/input.h> 16#include <linux/input.h>
17#include <linux/pwm_backlight.h>
18#include <linux/gpio_keys.h>
19#include <linux/i2c.h>
20#include <linux/regulator/machine.h>
21#include <linux/mfd/max8997.h>
22#include <linux/lcd.h>
17 23
18#include <asm/mach/arch.h> 24#include <asm/mach/arch.h>
19#include <asm/mach-types.h> 25#include <asm/mach-types.h>
20 26
27#include <video/platform_lcd.h>
28
21#include <plat/regs-serial.h> 29#include <plat/regs-serial.h>
30#include <plat/regs-fb-v4.h>
22#include <plat/exynos4.h> 31#include <plat/exynos4.h>
23#include <plat/cpu.h> 32#include <plat/cpu.h>
24#include <plat/devs.h> 33#include <plat/devs.h>
25#include <plat/sdhci.h> 34#include <plat/sdhci.h>
26#include <plat/iic.h> 35#include <plat/iic.h>
36#include <plat/ehci.h>
37#include <plat/clock.h>
38#include <plat/gpio-cfg.h>
39#include <plat/backlight.h>
40#include <plat/pd.h>
41#include <plat/fb.h>
27 42
28#include <mach/map.h> 43#include <mach/map.h>
29 44
@@ -72,19 +87,543 @@ static struct s3c2410_uartcfg origen_uartcfgs[] __initdata = {
72 }, 87 },
73}; 88};
74 89
90static struct regulator_consumer_supply __initdata ldo3_consumer[] = {
91 REGULATOR_SUPPLY("vdd11", "s5p-mipi-csis.0"), /* MIPI */
92};
93static struct regulator_consumer_supply __initdata ldo6_consumer[] = {
94 REGULATOR_SUPPLY("vdd18", "s5p-mipi-csis.0"), /* MIPI */
95};
96static struct regulator_consumer_supply __initdata ldo7_consumer[] = {
97 REGULATOR_SUPPLY("avdd", "alc5625"), /* Realtek ALC5625 */
98};
99static struct regulator_consumer_supply __initdata ldo8_consumer[] = {
100 REGULATOR_SUPPLY("vdd", "s5p-adc"), /* ADC */
101};
102static struct regulator_consumer_supply __initdata ldo9_consumer[] = {
103 REGULATOR_SUPPLY("dvdd", "swb-a31"), /* AR6003 WLAN & CSR 8810 BT */
104};
105static struct regulator_consumer_supply __initdata ldo11_consumer[] = {
106 REGULATOR_SUPPLY("dvdd", "alc5625"), /* Realtek ALC5625 */
107};
108static struct regulator_consumer_supply __initdata ldo14_consumer[] = {
109 REGULATOR_SUPPLY("avdd18", "swb-a31"), /* AR6003 WLAN & CSR 8810 BT */
110};
111static struct regulator_consumer_supply __initdata ldo17_consumer[] = {
112 REGULATOR_SUPPLY("vdd33", "swb-a31"), /* AR6003 WLAN & CSR 8810 BT */
113};
114static struct regulator_consumer_supply __initdata buck1_consumer[] = {
115 REGULATOR_SUPPLY("vdd_arm", NULL), /* CPUFREQ */
116};
117static struct regulator_consumer_supply __initdata buck2_consumer[] = {
118 REGULATOR_SUPPLY("vdd_int", NULL), /* CPUFREQ */
119};
120static struct regulator_consumer_supply __initdata buck3_consumer[] = {
121 REGULATOR_SUPPLY("vdd_g3d", "mali_drm"), /* G3D */
122};
123static struct regulator_consumer_supply __initdata buck7_consumer[] = {
124 REGULATOR_SUPPLY("vcc", "platform-lcd"), /* LCD */
125};
126
127static struct regulator_init_data __initdata max8997_ldo1_data = {
128 .constraints = {
129 .name = "VDD_ABB_3.3V",
130 .min_uV = 3300000,
131 .max_uV = 3300000,
132 .apply_uV = 1,
133 .state_mem = {
134 .disabled = 1,
135 },
136 },
137};
138
139static struct regulator_init_data __initdata max8997_ldo2_data = {
140 .constraints = {
141 .name = "VDD_ALIVE_1.1V",
142 .min_uV = 1100000,
143 .max_uV = 1100000,
144 .apply_uV = 1,
145 .always_on = 1,
146 .state_mem = {
147 .enabled = 1,
148 },
149 },
150};
151
152static struct regulator_init_data __initdata max8997_ldo3_data = {
153 .constraints = {
154 .name = "VMIPI_1.1V",
155 .min_uV = 1100000,
156 .max_uV = 1100000,
157 .apply_uV = 1,
158 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
159 .state_mem = {
160 .disabled = 1,
161 },
162 },
163 .num_consumer_supplies = ARRAY_SIZE(ldo3_consumer),
164 .consumer_supplies = ldo3_consumer,
165};
166
167static struct regulator_init_data __initdata max8997_ldo4_data = {
168 .constraints = {
169 .name = "VDD_RTC_1.8V",
170 .min_uV = 1800000,
171 .max_uV = 1800000,
172 .apply_uV = 1,
173 .always_on = 1,
174 .state_mem = {
175 .disabled = 1,
176 },
177 },
178};
179
180static struct regulator_init_data __initdata max8997_ldo6_data = {
181 .constraints = {
182 .name = "VMIPI_1.8V",
183 .min_uV = 1800000,
184 .max_uV = 1800000,
185 .apply_uV = 1,
186 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
187 .state_mem = {
188 .disabled = 1,
189 },
190 },
191 .num_consumer_supplies = ARRAY_SIZE(ldo6_consumer),
192 .consumer_supplies = ldo6_consumer,
193};
194
195static struct regulator_init_data __initdata max8997_ldo7_data = {
196 .constraints = {
197 .name = "VDD_AUD_1.8V",
198 .min_uV = 1800000,
199 .max_uV = 1800000,
200 .apply_uV = 1,
201 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
202 .state_mem = {
203 .disabled = 1,
204 },
205 },
206 .num_consumer_supplies = ARRAY_SIZE(ldo7_consumer),
207 .consumer_supplies = ldo7_consumer,
208};
209
210static struct regulator_init_data __initdata max8997_ldo8_data = {
211 .constraints = {
212 .name = "VADC_3.3V",
213 .min_uV = 3300000,
214 .max_uV = 3300000,
215 .apply_uV = 1,
216 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
217 .state_mem = {
218 .disabled = 1,
219 },
220 },
221 .num_consumer_supplies = ARRAY_SIZE(ldo8_consumer),
222 .consumer_supplies = ldo8_consumer,
223};
224
225static struct regulator_init_data __initdata max8997_ldo9_data = {
226 .constraints = {
227 .name = "DVDD_SWB_2.8V",
228 .min_uV = 2800000,
229 .max_uV = 2800000,
230 .apply_uV = 1,
231 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
232 .state_mem = {
233 .disabled = 1,
234 },
235 },
236 .num_consumer_supplies = ARRAY_SIZE(ldo9_consumer),
237 .consumer_supplies = ldo9_consumer,
238};
239
240static struct regulator_init_data __initdata max8997_ldo10_data = {
241 .constraints = {
242 .name = "VDD_PLL_1.1V",
243 .min_uV = 1100000,
244 .max_uV = 1100000,
245 .apply_uV = 1,
246 .always_on = 1,
247 .state_mem = {
248 .disabled = 1,
249 },
250 },
251};
252
253static struct regulator_init_data __initdata max8997_ldo11_data = {
254 .constraints = {
255 .name = "VDD_AUD_3V",
256 .min_uV = 3000000,
257 .max_uV = 3000000,
258 .apply_uV = 1,
259 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
260 .state_mem = {
261 .disabled = 1,
262 },
263 },
264 .num_consumer_supplies = ARRAY_SIZE(ldo11_consumer),
265 .consumer_supplies = ldo11_consumer,
266};
267
268static struct regulator_init_data __initdata max8997_ldo14_data = {
269 .constraints = {
270 .name = "AVDD18_SWB_1.8V",
271 .min_uV = 1800000,
272 .max_uV = 1800000,
273 .apply_uV = 1,
274 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
275 .state_mem = {
276 .disabled = 1,
277 },
278 },
279 .num_consumer_supplies = ARRAY_SIZE(ldo14_consumer),
280 .consumer_supplies = ldo14_consumer,
281};
282
283static struct regulator_init_data __initdata max8997_ldo17_data = {
284 .constraints = {
285 .name = "VDD_SWB_3.3V",
286 .min_uV = 3300000,
287 .max_uV = 3300000,
288 .apply_uV = 1,
289 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
290 .state_mem = {
291 .disabled = 1,
292 },
293 },
294 .num_consumer_supplies = ARRAY_SIZE(ldo17_consumer),
295 .consumer_supplies = ldo17_consumer,
296};
297
298static struct regulator_init_data __initdata max8997_ldo21_data = {
299 .constraints = {
300 .name = "VDD_MIF_1.2V",
301 .min_uV = 1200000,
302 .max_uV = 1200000,
303 .apply_uV = 1,
304 .always_on = 1,
305 .state_mem = {
306 .disabled = 1,
307 },
308 },
309};
310
311static struct regulator_init_data __initdata max8997_buck1_data = {
312 .constraints = {
313 .name = "VDD_ARM_1.2V",
314 .min_uV = 950000,
315 .max_uV = 1350000,
316 .always_on = 1,
317 .boot_on = 1,
318 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
319 .state_mem = {
320 .disabled = 1,
321 },
322 },
323 .num_consumer_supplies = ARRAY_SIZE(buck1_consumer),
324 .consumer_supplies = buck1_consumer,
325};
326
327static struct regulator_init_data __initdata max8997_buck2_data = {
328 .constraints = {
329 .name = "VDD_INT_1.1V",
330 .min_uV = 900000,
331 .max_uV = 1100000,
332 .always_on = 1,
333 .boot_on = 1,
334 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
335 .state_mem = {
336 .disabled = 1,
337 },
338 },
339 .num_consumer_supplies = ARRAY_SIZE(buck2_consumer),
340 .consumer_supplies = buck2_consumer,
341};
342
343static struct regulator_init_data __initdata max8997_buck3_data = {
344 .constraints = {
345 .name = "VDD_G3D_1.1V",
346 .min_uV = 900000,
347 .max_uV = 1100000,
348 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
349 REGULATOR_CHANGE_STATUS,
350 .state_mem = {
351 .disabled = 1,
352 },
353 },
354 .num_consumer_supplies = ARRAY_SIZE(buck3_consumer),
355 .consumer_supplies = buck3_consumer,
356};
357
358static struct regulator_init_data __initdata max8997_buck5_data = {
359 .constraints = {
360 .name = "VDDQ_M1M2_1.2V",
361 .min_uV = 1200000,
362 .max_uV = 1200000,
363 .apply_uV = 1,
364 .always_on = 1,
365 .state_mem = {
366 .disabled = 1,
367 },
368 },
369};
370
371static struct regulator_init_data __initdata max8997_buck7_data = {
372 .constraints = {
373 .name = "VDD_LCD_3.3V",
374 .min_uV = 3300000,
375 .max_uV = 3300000,
376 .boot_on = 1,
377 .apply_uV = 1,
378 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
379 .state_mem = {
380 .disabled = 1
381 },
382 },
383 .num_consumer_supplies = ARRAY_SIZE(buck7_consumer),
384 .consumer_supplies = buck7_consumer,
385};
386
387static struct max8997_regulator_data __initdata origen_max8997_regulators[] = {
388 { MAX8997_LDO1, &max8997_ldo1_data },
389 { MAX8997_LDO2, &max8997_ldo2_data },
390 { MAX8997_LDO3, &max8997_ldo3_data },
391 { MAX8997_LDO4, &max8997_ldo4_data },
392 { MAX8997_LDO6, &max8997_ldo6_data },
393 { MAX8997_LDO7, &max8997_ldo7_data },
394 { MAX8997_LDO8, &max8997_ldo8_data },
395 { MAX8997_LDO9, &max8997_ldo9_data },
396 { MAX8997_LDO10, &max8997_ldo10_data },
397 { MAX8997_LDO11, &max8997_ldo11_data },
398 { MAX8997_LDO14, &max8997_ldo14_data },
399 { MAX8997_LDO17, &max8997_ldo17_data },
400 { MAX8997_LDO21, &max8997_ldo21_data },
401 { MAX8997_BUCK1, &max8997_buck1_data },
402 { MAX8997_BUCK2, &max8997_buck2_data },
403 { MAX8997_BUCK3, &max8997_buck3_data },
404 { MAX8997_BUCK5, &max8997_buck5_data },
405 { MAX8997_BUCK7, &max8997_buck7_data },
406};
407
408struct max8997_platform_data __initdata origen_max8997_pdata = {
409 .num_regulators = ARRAY_SIZE(origen_max8997_regulators),
410 .regulators = origen_max8997_regulators,
411
412 .wakeup = true,
413 .buck1_gpiodvs = false,
414 .buck2_gpiodvs = false,
415 .buck5_gpiodvs = false,
416 .irq_base = IRQ_GPIO_END + 1,
417
418 .ignore_gpiodvs_side_effect = true,
419 .buck125_default_idx = 0x0,
420
421 .buck125_gpios[0] = EXYNOS4_GPX0(0),
422 .buck125_gpios[1] = EXYNOS4_GPX0(1),
423 .buck125_gpios[2] = EXYNOS4_GPX0(2),
424
425 .buck1_voltage[0] = 1350000,
426 .buck1_voltage[1] = 1300000,
427 .buck1_voltage[2] = 1250000,
428 .buck1_voltage[3] = 1200000,
429 .buck1_voltage[4] = 1150000,
430 .buck1_voltage[5] = 1100000,
431 .buck1_voltage[6] = 1000000,
432 .buck1_voltage[7] = 950000,
433
434 .buck2_voltage[0] = 1100000,
435 .buck2_voltage[1] = 1100000,
436 .buck2_voltage[2] = 1100000,
437 .buck2_voltage[3] = 1100000,
438 .buck2_voltage[4] = 1000000,
439 .buck2_voltage[5] = 1000000,
440 .buck2_voltage[6] = 1000000,
441 .buck2_voltage[7] = 1000000,
442
443 .buck5_voltage[0] = 1200000,
444 .buck5_voltage[1] = 1200000,
445 .buck5_voltage[2] = 1200000,
446 .buck5_voltage[3] = 1200000,
447 .buck5_voltage[4] = 1200000,
448 .buck5_voltage[5] = 1200000,
449 .buck5_voltage[6] = 1200000,
450 .buck5_voltage[7] = 1200000,
451};
452
453/* I2C0 */
454static struct i2c_board_info i2c0_devs[] __initdata = {
455 {
456 I2C_BOARD_INFO("max8997", (0xCC >> 1)),
457 .platform_data = &origen_max8997_pdata,
458 .irq = IRQ_EINT(4),
459 },
460};
461
462static struct s3c_sdhci_platdata origen_hsmmc0_pdata __initdata = {
463 .cd_type = S3C_SDHCI_CD_INTERNAL,
464 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
465};
466
75static struct s3c_sdhci_platdata origen_hsmmc2_pdata __initdata = { 467static struct s3c_sdhci_platdata origen_hsmmc2_pdata __initdata = {
76 .cd_type = S3C_SDHCI_CD_GPIO, 468 .cd_type = S3C_SDHCI_CD_INTERNAL,
77 .ext_cd_gpio = EXYNOS4_GPK2(2),
78 .ext_cd_gpio_invert = 1,
79 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, 469 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
80}; 470};
81 471
472/* USB EHCI */
473static struct s5p_ehci_platdata origen_ehci_pdata;
474
475static void __init origen_ehci_init(void)
476{
477 struct s5p_ehci_platdata *pdata = &origen_ehci_pdata;
478
479 s5p_ehci_set_platdata(pdata);
480}
481
482static struct gpio_keys_button origen_gpio_keys_table[] = {
483 {
484 .code = KEY_MENU,
485 .gpio = EXYNOS4_GPX1(5),
486 .desc = "gpio-keys: KEY_MENU",
487 .type = EV_KEY,
488 .active_low = 1,
489 .wakeup = 1,
490 .debounce_interval = 1,
491 }, {
492 .code = KEY_HOME,
493 .gpio = EXYNOS4_GPX1(6),
494 .desc = "gpio-keys: KEY_HOME",
495 .type = EV_KEY,
496 .active_low = 1,
497 .wakeup = 1,
498 .debounce_interval = 1,
499 }, {
500 .code = KEY_BACK,
501 .gpio = EXYNOS4_GPX1(7),
502 .desc = "gpio-keys: KEY_BACK",
503 .type = EV_KEY,
504 .active_low = 1,
505 .wakeup = 1,
506 .debounce_interval = 1,
507 }, {
508 .code = KEY_UP,
509 .gpio = EXYNOS4_GPX2(0),
510 .desc = "gpio-keys: KEY_UP",
511 .type = EV_KEY,
512 .active_low = 1,
513 .wakeup = 1,
514 .debounce_interval = 1,
515 }, {
516 .code = KEY_DOWN,
517 .gpio = EXYNOS4_GPX2(1),
518 .desc = "gpio-keys: KEY_DOWN",
519 .type = EV_KEY,
520 .active_low = 1,
521 .wakeup = 1,
522 .debounce_interval = 1,
523 },
524};
525
526static struct gpio_keys_platform_data origen_gpio_keys_data = {
527 .buttons = origen_gpio_keys_table,
528 .nbuttons = ARRAY_SIZE(origen_gpio_keys_table),
529};
530
531static struct platform_device origen_device_gpiokeys = {
532 .name = "gpio-keys",
533 .dev = {
534 .platform_data = &origen_gpio_keys_data,
535 },
536};
537
538static void lcd_hv070wsa_set_power(struct plat_lcd_data *pd, unsigned int power)
539{
540 int ret;
541
542 if (power)
543 ret = gpio_request_one(EXYNOS4_GPE3(4),
544 GPIOF_OUT_INIT_HIGH, "GPE3_4");
545 else
546 ret = gpio_request_one(EXYNOS4_GPE3(4),
547 GPIOF_OUT_INIT_LOW, "GPE3_4");
548
549 gpio_free(EXYNOS4_GPE3(4));
550
551 if (ret)
552 pr_err("failed to request gpio for LCD power: %d\n", ret);
553}
554
555static struct plat_lcd_data origen_lcd_hv070wsa_data = {
556 .set_power = lcd_hv070wsa_set_power,
557};
558
559static struct platform_device origen_lcd_hv070wsa = {
560 .name = "platform-lcd",
561 .dev.parent = &s5p_device_fimd0.dev,
562 .dev.platform_data = &origen_lcd_hv070wsa_data,
563};
564
565static struct s3c_fb_pd_win origen_fb_win0 = {
566 .win_mode = {
567 .left_margin = 64,
568 .right_margin = 16,
569 .upper_margin = 64,
570 .lower_margin = 16,
571 .hsync_len = 48,
572 .vsync_len = 3,
573 .xres = 1024,
574 .yres = 600,
575 },
576 .max_bpp = 32,
577 .default_bpp = 24,
578};
579
580static struct s3c_fb_platdata origen_lcd_pdata __initdata = {
581 .win[0] = &origen_fb_win0,
582 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
583 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
584 .setup_gpio = exynos4_fimd0_gpio_setup_24bpp,
585};
586
82static struct platform_device *origen_devices[] __initdata = { 587static struct platform_device *origen_devices[] __initdata = {
83 &s3c_device_hsmmc2, 588 &s3c_device_hsmmc2,
589 &s3c_device_hsmmc0,
590 &s3c_device_i2c0,
84 &s3c_device_rtc, 591 &s3c_device_rtc,
85 &s3c_device_wdt, 592 &s3c_device_wdt,
593 &s5p_device_ehci,
594 &s5p_device_fimc0,
595 &s5p_device_fimc1,
596 &s5p_device_fimc2,
597 &s5p_device_fimc3,
598 &s5p_device_fimd0,
599 &s5p_device_hdmi,
600 &s5p_device_i2c_hdmiphy,
601 &s5p_device_mixer,
602 &exynos4_device_pd[PD_LCD0],
603 &exynos4_device_pd[PD_TV],
604 &origen_device_gpiokeys,
605 &origen_lcd_hv070wsa,
606};
607
608/* LCD Backlight data */
609static struct samsung_bl_gpio_info origen_bl_gpio_info = {
610 .no = EXYNOS4_GPD0(0),
611 .func = S3C_GPIO_SFN(2),
86}; 612};
87 613
614static struct platform_pwm_backlight_data origen_bl_data = {
615 .pwm_id = 0,
616 .pwm_period_ns = 1000,
617};
618
619static void s5p_tv_setup(void)
620{
621 /* Direct HPD to HDMI chip */
622 gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug");
623 s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3));
624 s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE);
625}
626
88static void __init origen_map_io(void) 627static void __init origen_map_io(void)
89{ 628{
90 s5p_init_io(NULL, 0, S5P_VA_CHIPID); 629 s5p_init_io(NULL, 0, S5P_VA_CHIPID);
@@ -92,10 +631,42 @@ static void __init origen_map_io(void)
92 s3c24xx_init_uarts(origen_uartcfgs, ARRAY_SIZE(origen_uartcfgs)); 631 s3c24xx_init_uarts(origen_uartcfgs, ARRAY_SIZE(origen_uartcfgs));
93} 632}
94 633
634static void __init origen_power_init(void)
635{
636 gpio_request(EXYNOS4_GPX0(4), "PMIC_IRQ");
637 s3c_gpio_cfgpin(EXYNOS4_GPX0(4), S3C_GPIO_SFN(0xf));
638 s3c_gpio_setpull(EXYNOS4_GPX0(4), S3C_GPIO_PULL_NONE);
639}
640
95static void __init origen_machine_init(void) 641static void __init origen_machine_init(void)
96{ 642{
643 origen_power_init();
644
645 s3c_i2c0_set_platdata(NULL);
646 i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs));
647
648 /*
649 * Since sdhci instance 2 can contain a bootable media,
650 * sdhci instance 0 is registered after instance 2.
651 */
97 s3c_sdhci2_set_platdata(&origen_hsmmc2_pdata); 652 s3c_sdhci2_set_platdata(&origen_hsmmc2_pdata);
653 s3c_sdhci0_set_platdata(&origen_hsmmc0_pdata);
654
655 origen_ehci_init();
656 clk_xusbxti.rate = 24000000;
657
658 s5p_tv_setup();
659 s5p_i2c_hdmiphy_set_platdata(NULL);
660
661 s5p_fimd0_set_platdata(&origen_lcd_pdata);
662
98 platform_add_devices(origen_devices, ARRAY_SIZE(origen_devices)); 663 platform_add_devices(origen_devices, ARRAY_SIZE(origen_devices));
664 s5p_device_fimd0.dev.parent = &exynos4_device_pd[PD_LCD0].dev;
665
666 s5p_device_hdmi.dev.parent = &exynos4_device_pd[PD_TV].dev;
667 s5p_device_mixer.dev.parent = &exynos4_device_pd[PD_TV].dev;
668
669 samsung_bl_set(&origen_bl_gpio_info, &origen_bl_data);
99} 670}
100 671
101MACHINE_START(ORIGEN, "ORIGEN") 672MACHINE_START(ORIGEN, "ORIGEN")
diff --git a/arch/arm/mach-exynos4/mach-smdkv310.c b/arch/arm/mach-exynos4/mach-smdkv310.c
index a16eb569a3e..35a763e9a65 100644
--- a/arch/arm/mach-exynos4/mach-smdkv310.c
+++ b/arch/arm/mach-exynos4/mach-smdkv310.c
@@ -37,6 +37,9 @@
37#include <plat/pd.h> 37#include <plat/pd.h>
38#include <plat/gpio-cfg.h> 38#include <plat/gpio-cfg.h>
39#include <plat/backlight.h> 39#include <plat/backlight.h>
40#include <plat/mfc.h>
41#include <plat/ehci.h>
42#include <plat/clock.h>
40 43
41#include <mach/map.h> 44#include <mach/map.h>
42 45
@@ -232,17 +235,36 @@ static struct i2c_board_info i2c_devs1[] __initdata = {
232 {I2C_BOARD_INFO("wm8994", 0x1a),}, 235 {I2C_BOARD_INFO("wm8994", 0x1a),},
233}; 236};
234 237
238/* USB EHCI */
239static struct s5p_ehci_platdata smdkv310_ehci_pdata;
240
241static void __init smdkv310_ehci_init(void)
242{
243 struct s5p_ehci_platdata *pdata = &smdkv310_ehci_pdata;
244
245 s5p_ehci_set_platdata(pdata);
246}
247
235static struct platform_device *smdkv310_devices[] __initdata = { 248static struct platform_device *smdkv310_devices[] __initdata = {
236 &s3c_device_hsmmc0, 249 &s3c_device_hsmmc0,
237 &s3c_device_hsmmc1, 250 &s3c_device_hsmmc1,
238 &s3c_device_hsmmc2, 251 &s3c_device_hsmmc2,
239 &s3c_device_hsmmc3, 252 &s3c_device_hsmmc3,
240 &s3c_device_i2c1, 253 &s3c_device_i2c1,
254 &s5p_device_i2c_hdmiphy,
241 &s3c_device_rtc, 255 &s3c_device_rtc,
242 &s3c_device_wdt, 256 &s3c_device_wdt,
257 &s5p_device_ehci,
258 &s5p_device_fimc0,
259 &s5p_device_fimc1,
260 &s5p_device_fimc2,
261 &s5p_device_fimc3,
243 &exynos4_device_ac97, 262 &exynos4_device_ac97,
244 &exynos4_device_i2s0, 263 &exynos4_device_i2s0,
245 &samsung_device_keypad, 264 &samsung_device_keypad,
265 &s5p_device_mfc,
266 &s5p_device_mfc_l,
267 &s5p_device_mfc_r,
246 &exynos4_device_pd[PD_MFC], 268 &exynos4_device_pd[PD_MFC],
247 &exynos4_device_pd[PD_G3D], 269 &exynos4_device_pd[PD_G3D],
248 &exynos4_device_pd[PD_LCD0], 270 &exynos4_device_pd[PD_LCD0],
@@ -258,6 +280,8 @@ static struct platform_device *smdkv310_devices[] __initdata = {
258 &smdkv310_lcd_lte480wv, 280 &smdkv310_lcd_lte480wv,
259 &smdkv310_smsc911x, 281 &smdkv310_smsc911x,
260 &exynos4_device_ahci, 282 &exynos4_device_ahci,
283 &s5p_device_hdmi,
284 &s5p_device_mixer,
261}; 285};
262 286
263static void __init smdkv310_smsc911x_init(void) 287static void __init smdkv310_smsc911x_init(void)
@@ -294,6 +318,18 @@ static struct platform_pwm_backlight_data smdkv310_bl_data = {
294 .pwm_period_ns = 1000, 318 .pwm_period_ns = 1000,
295}; 319};
296 320
321static void s5p_tv_setup(void)
322{
323 /* direct HPD to HDMI chip */
324 WARN_ON(gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug"));
325 s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3));
326 s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE);
327
328 /* setup dependencies between TV devices */
329 s5p_device_hdmi.dev.parent = &exynos4_device_pd[PD_TV].dev;
330 s5p_device_mixer.dev.parent = &exynos4_device_pd[PD_TV].dev;
331}
332
297static void __init smdkv310_map_io(void) 333static void __init smdkv310_map_io(void)
298{ 334{
299 s5p_init_io(NULL, 0, S5P_VA_CHIPID); 335 s5p_init_io(NULL, 0, S5P_VA_CHIPID);
@@ -301,6 +337,11 @@ static void __init smdkv310_map_io(void)
301 s3c24xx_init_uarts(smdkv310_uartcfgs, ARRAY_SIZE(smdkv310_uartcfgs)); 337 s3c24xx_init_uarts(smdkv310_uartcfgs, ARRAY_SIZE(smdkv310_uartcfgs));
302} 338}
303 339
340static void __init smdkv310_reserve(void)
341{
342 s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
343}
344
304static void __init smdkv310_machine_init(void) 345static void __init smdkv310_machine_init(void)
305{ 346{
306 s3c_i2c1_set_platdata(NULL); 347 s3c_i2c1_set_platdata(NULL);
@@ -313,12 +354,19 @@ static void __init smdkv310_machine_init(void)
313 s3c_sdhci2_set_platdata(&smdkv310_hsmmc2_pdata); 354 s3c_sdhci2_set_platdata(&smdkv310_hsmmc2_pdata);
314 s3c_sdhci3_set_platdata(&smdkv310_hsmmc3_pdata); 355 s3c_sdhci3_set_platdata(&smdkv310_hsmmc3_pdata);
315 356
357 s5p_tv_setup();
358 s5p_i2c_hdmiphy_set_platdata(NULL);
359
316 samsung_keypad_set_platdata(&smdkv310_keypad_data); 360 samsung_keypad_set_platdata(&smdkv310_keypad_data);
317 361
318 samsung_bl_set(&smdkv310_bl_gpio_info, &smdkv310_bl_data); 362 samsung_bl_set(&smdkv310_bl_gpio_info, &smdkv310_bl_data);
319 s5p_fimd0_set_platdata(&smdkv310_lcd0_pdata); 363 s5p_fimd0_set_platdata(&smdkv310_lcd0_pdata);
320 364
365 smdkv310_ehci_init();
366 clk_xusbxti.rate = 24000000;
367
321 platform_add_devices(smdkv310_devices, ARRAY_SIZE(smdkv310_devices)); 368 platform_add_devices(smdkv310_devices, ARRAY_SIZE(smdkv310_devices));
369 s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
322} 370}
323 371
324MACHINE_START(SMDKV310, "SMDKV310") 372MACHINE_START(SMDKV310, "SMDKV310")
@@ -329,6 +377,7 @@ MACHINE_START(SMDKV310, "SMDKV310")
329 .map_io = smdkv310_map_io, 377 .map_io = smdkv310_map_io,
330 .init_machine = smdkv310_machine_init, 378 .init_machine = smdkv310_machine_init,
331 .timer = &exynos4_timer, 379 .timer = &exynos4_timer,
380 .reserve = &smdkv310_reserve,
332MACHINE_END 381MACHINE_END
333 382
334MACHINE_START(SMDKC210, "SMDKC210") 383MACHINE_START(SMDKC210, "SMDKC210")
diff --git a/arch/arm/mach-exynos4/mach-universal_c210.c b/arch/arm/mach-exynos4/mach-universal_c210.c
index b3b5d891100..18cf5c7cf56 100644
--- a/arch/arm/mach-exynos4/mach-universal_c210.c
+++ b/arch/arm/mach-exynos4/mach-universal_c210.c
@@ -13,6 +13,7 @@
13#include <linux/i2c.h> 13#include <linux/i2c.h>
14#include <linux/gpio_keys.h> 14#include <linux/gpio_keys.h>
15#include <linux/gpio.h> 15#include <linux/gpio.h>
16#include <linux/fb.h>
16#include <linux/mfd/max8998.h> 17#include <linux/mfd/max8998.h>
17#include <linux/regulator/machine.h> 18#include <linux/regulator/machine.h>
18#include <linux/regulator/fixed.h> 19#include <linux/regulator/fixed.h>
@@ -31,12 +32,21 @@
31#include <plat/devs.h> 32#include <plat/devs.h>
32#include <plat/iic.h> 33#include <plat/iic.h>
33#include <plat/gpio-cfg.h> 34#include <plat/gpio-cfg.h>
35#include <plat/fb.h>
34#include <plat/mfc.h> 36#include <plat/mfc.h>
35#include <plat/sdhci.h> 37#include <plat/sdhci.h>
36#include <plat/pd.h> 38#include <plat/pd.h>
39#include <plat/regs-fb-v4.h>
40#include <plat/fimc-core.h>
41#include <plat/camport.h>
42#include <plat/mipi_csis.h>
37 43
38#include <mach/map.h> 44#include <mach/map.h>
39 45
46#include <media/v4l2-mediabus.h>
47#include <media/s5p_fimc.h>
48#include <media/m5mols.h>
49
40/* Following are default values for UCON, ULCON and UFCON UART registers */ 50/* Following are default values for UCON, ULCON and UFCON UART registers */
41#define UNIVERSAL_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 51#define UNIVERSAL_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
42 S3C2410_UCON_RXILEVEL | \ 52 S3C2410_UCON_RXILEVEL | \
@@ -110,6 +120,9 @@ static struct regulator_consumer_supply lp3974_buck1_consumer =
110static struct regulator_consumer_supply lp3974_buck2_consumer = 120static struct regulator_consumer_supply lp3974_buck2_consumer =
111 REGULATOR_SUPPLY("vddg3d", NULL); 121 REGULATOR_SUPPLY("vddg3d", NULL);
112 122
123static struct regulator_consumer_supply lp3974_buck3_consumer =
124 REGULATOR_SUPPLY("vdet", "s5p-sdo");
125
113static struct regulator_init_data lp3974_buck1_data = { 126static struct regulator_init_data lp3974_buck1_data = {
114 .constraints = { 127 .constraints = {
115 .name = "VINT_1.1V", 128 .name = "VINT_1.1V",
@@ -153,6 +166,8 @@ static struct regulator_init_data lp3974_buck3_data = {
153 .enabled = 1, 166 .enabled = 1,
154 }, 167 },
155 }, 168 },
169 .num_consumer_supplies = 1,
170 .consumer_supplies = &lp3974_buck3_consumer,
156}; 171};
157 172
158static struct regulator_init_data lp3974_buck4_data = { 173static struct regulator_init_data lp3974_buck4_data = {
@@ -181,6 +196,12 @@ static struct regulator_init_data lp3974_ldo2_data = {
181 }, 196 },
182}; 197};
183 198
199static struct regulator_consumer_supply lp3974_ldo3_consumer[] = {
200 REGULATOR_SUPPLY("vdd", "exynos4-hdmi"),
201 REGULATOR_SUPPLY("vdd_pll", "exynos4-hdmi"),
202 REGULATOR_SUPPLY("vdd11", "s5p-mipi-csis.0"),
203};
204
184static struct regulator_init_data lp3974_ldo3_data = { 205static struct regulator_init_data lp3974_ldo3_data = {
185 .constraints = { 206 .constraints = {
186 .name = "VUSB+MIPI_1.1V", 207 .name = "VUSB+MIPI_1.1V",
@@ -192,6 +213,12 @@ static struct regulator_init_data lp3974_ldo3_data = {
192 .disabled = 1, 213 .disabled = 1,
193 }, 214 },
194 }, 215 },
216 .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo3_consumer),
217 .consumer_supplies = lp3974_ldo3_consumer,
218};
219
220static struct regulator_consumer_supply lp3974_ldo4_consumer[] = {
221 REGULATOR_SUPPLY("vdd_osc", "exynos4-hdmi"),
195}; 222};
196 223
197static struct regulator_init_data lp3974_ldo4_data = { 224static struct regulator_init_data lp3974_ldo4_data = {
@@ -205,6 +232,8 @@ static struct regulator_init_data lp3974_ldo4_data = {
205 .disabled = 1, 232 .disabled = 1,
206 }, 233 },
207 }, 234 },
235 .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo4_consumer),
236 .consumer_supplies = lp3974_ldo4_consumer,
208}; 237};
209 238
210static struct regulator_init_data lp3974_ldo5_data = { 239static struct regulator_init_data lp3974_ldo5_data = {
@@ -233,6 +262,10 @@ static struct regulator_init_data lp3974_ldo6_data = {
233 }, 262 },
234}; 263};
235 264
265static struct regulator_consumer_supply lp3974_ldo7_consumer[] = {
266 REGULATOR_SUPPLY("vdd18", "s5p-mipi-csis.0"),
267};
268
236static struct regulator_init_data lp3974_ldo7_data = { 269static struct regulator_init_data lp3974_ldo7_data = {
237 .constraints = { 270 .constraints = {
238 .name = "VLCD+VMIPI_1.8V", 271 .name = "VLCD+VMIPI_1.8V",
@@ -244,6 +277,12 @@ static struct regulator_init_data lp3974_ldo7_data = {
244 .disabled = 1, 277 .disabled = 1,
245 }, 278 },
246 }, 279 },
280 .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo7_consumer),
281 .consumer_supplies = lp3974_ldo7_consumer,
282};
283
284static struct regulator_consumer_supply lp3974_ldo8_consumer[] = {
285 REGULATOR_SUPPLY("vdd33a_dac", "s5p-sdo"),
247}; 286};
248 287
249static struct regulator_init_data lp3974_ldo8_data = { 288static struct regulator_init_data lp3974_ldo8_data = {
@@ -257,6 +296,8 @@ static struct regulator_init_data lp3974_ldo8_data = {
257 .disabled = 1, 296 .disabled = 1,
258 }, 297 },
259 }, 298 },
299 .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo8_consumer),
300 .consumer_supplies = lp3974_ldo8_consumer,
260}; 301};
261 302
262static struct regulator_init_data lp3974_ldo9_data = { 303static struct regulator_init_data lp3974_ldo9_data = {
@@ -286,6 +327,9 @@ static struct regulator_init_data lp3974_ldo10_data = {
286 }, 327 },
287}; 328};
288 329
330static struct regulator_consumer_supply lp3974_ldo11_consumer =
331 REGULATOR_SUPPLY("dig_28", "0-001f");
332
289static struct regulator_init_data lp3974_ldo11_data = { 333static struct regulator_init_data lp3974_ldo11_data = {
290 .constraints = { 334 .constraints = {
291 .name = "CAM_AF_3.3V", 335 .name = "CAM_AF_3.3V",
@@ -297,6 +341,8 @@ static struct regulator_init_data lp3974_ldo11_data = {
297 .disabled = 1, 341 .disabled = 1,
298 }, 342 },
299 }, 343 },
344 .num_consumer_supplies = 1,
345 .consumer_supplies = &lp3974_ldo11_consumer,
300}; 346};
301 347
302static struct regulator_init_data lp3974_ldo12_data = { 348static struct regulator_init_data lp3974_ldo12_data = {
@@ -325,6 +371,9 @@ static struct regulator_init_data lp3974_ldo13_data = {
325 }, 371 },
326}; 372};
327 373
374static struct regulator_consumer_supply lp3974_ldo14_consumer =
375 REGULATOR_SUPPLY("dig_18", "0-001f");
376
328static struct regulator_init_data lp3974_ldo14_data = { 377static struct regulator_init_data lp3974_ldo14_data = {
329 .constraints = { 378 .constraints = {
330 .name = "CAM_I_HOST_1.8V", 379 .name = "CAM_I_HOST_1.8V",
@@ -336,8 +385,14 @@ static struct regulator_init_data lp3974_ldo14_data = {
336 .disabled = 1, 385 .disabled = 1,
337 }, 386 },
338 }, 387 },
388 .num_consumer_supplies = 1,
389 .consumer_supplies = &lp3974_ldo14_consumer,
339}; 390};
340 391
392
393static struct regulator_consumer_supply lp3974_ldo15_consumer =
394 REGULATOR_SUPPLY("dig_12", "0-001f");
395
341static struct regulator_init_data lp3974_ldo15_data = { 396static struct regulator_init_data lp3974_ldo15_data = {
342 .constraints = { 397 .constraints = {
343 .name = "CAM_S_DIG+FM33_CORE_1.2V", 398 .name = "CAM_S_DIG+FM33_CORE_1.2V",
@@ -349,6 +404,12 @@ static struct regulator_init_data lp3974_ldo15_data = {
349 .disabled = 1, 404 .disabled = 1,
350 }, 405 },
351 }, 406 },
407 .num_consumer_supplies = 1,
408 .consumer_supplies = &lp3974_ldo15_consumer,
409};
410
411static struct regulator_consumer_supply lp3974_ldo16_consumer[] = {
412 REGULATOR_SUPPLY("a_sensor", "0-001f"),
352}; 413};
353 414
354static struct regulator_init_data lp3974_ldo16_data = { 415static struct regulator_init_data lp3974_ldo16_data = {
@@ -362,6 +423,8 @@ static struct regulator_init_data lp3974_ldo16_data = {
362 .disabled = 1, 423 .disabled = 1,
363 }, 424 },
364 }, 425 },
426 .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo16_consumer),
427 .consumer_supplies = lp3974_ldo16_consumer,
365}; 428};
366 429
367static struct regulator_init_data lp3974_ldo17_data = { 430static struct regulator_init_data lp3974_ldo17_data = {
@@ -472,6 +535,43 @@ static struct max8998_platform_data universal_lp3974_pdata = {
472 .wakeup = true, 535 .wakeup = true,
473}; 536};
474 537
538
539enum fixed_regulator_id {
540 FIXED_REG_ID_MMC0,
541 FIXED_REG_ID_HDMI_5V,
542 FIXED_REG_ID_CAM_S_IF,
543 FIXED_REG_ID_CAM_I_CORE,
544 FIXED_REG_ID_CAM_VT_DIO,
545};
546
547static struct regulator_consumer_supply hdmi_fixed_consumer =
548 REGULATOR_SUPPLY("hdmi-en", "exynos4-hdmi");
549
550static struct regulator_init_data hdmi_fixed_voltage_init_data = {
551 .constraints = {
552 .name = "HDMI_5V",
553 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
554 },
555 .num_consumer_supplies = 1,
556 .consumer_supplies = &hdmi_fixed_consumer,
557};
558
559static struct fixed_voltage_config hdmi_fixed_voltage_config = {
560 .supply_name = "HDMI_EN1",
561 .microvolts = 5000000,
562 .gpio = EXYNOS4_GPE0(1),
563 .enable_high = true,
564 .init_data = &hdmi_fixed_voltage_init_data,
565};
566
567static struct platform_device hdmi_fixed_voltage = {
568 .name = "reg-fixed-voltage",
569 .id = FIXED_REG_ID_HDMI_5V,
570 .dev = {
571 .platform_data = &hdmi_fixed_voltage_config,
572 },
573};
574
475/* GPIO I2C 5 (PMIC) */ 575/* GPIO I2C 5 (PMIC) */
476static struct i2c_board_info i2c5_devs[] __initdata = { 576static struct i2c_board_info i2c5_devs[] __initdata = {
477 { 577 {
@@ -573,6 +673,11 @@ static void __init universal_touchkey_init(void)
573 gpio_direction_output(gpio, 1); 673 gpio_direction_output(gpio, 1);
574} 674}
575 675
676static struct s3c2410_platform_i2c universal_i2c0_platdata __initdata = {
677 .frequency = 300 * 1000,
678 .sda_delay = 200,
679};
680
576/* GPIO KEYS */ 681/* GPIO KEYS */
577static struct gpio_keys_button universal_gpio_keys_tables[] = { 682static struct gpio_keys_button universal_gpio_keys_tables[] = {
578 { 683 {
@@ -658,7 +763,7 @@ static struct fixed_voltage_config mmc0_fixed_voltage_config = {
658 763
659static struct platform_device mmc0_fixed_voltage = { 764static struct platform_device mmc0_fixed_voltage = {
660 .name = "reg-fixed-voltage", 765 .name = "reg-fixed-voltage",
661 .id = 0, 766 .id = FIXED_REG_ID_MMC0,
662 .dev = { 767 .dev = {
663 .platform_data = &mmc0_fixed_voltage_config, 768 .platform_data = &mmc0_fixed_voltage_config,
664 }, 769 },
@@ -692,18 +797,170 @@ static void __init universal_sdhci_init(void)
692 s3c_sdhci3_set_platdata(&universal_hsmmc3_data); 797 s3c_sdhci3_set_platdata(&universal_hsmmc3_data);
693} 798}
694 799
695/* I2C0 */
696static struct i2c_board_info i2c0_devs[] __initdata = {
697 /* Camera, To be updated */
698};
699
700/* I2C1 */ 800/* I2C1 */
701static struct i2c_board_info i2c1_devs[] __initdata = { 801static struct i2c_board_info i2c1_devs[] __initdata = {
702 /* Gyro, To be updated */ 802 /* Gyro, To be updated */
703}; 803};
704 804
805/* Frame Buffer */
806static struct s3c_fb_pd_win universal_fb_win0 = {
807 .win_mode = {
808 .left_margin = 16,
809 .right_margin = 16,
810 .upper_margin = 2,
811 .lower_margin = 28,
812 .hsync_len = 2,
813 .vsync_len = 1,
814 .xres = 480,
815 .yres = 800,
816 .refresh = 55,
817 },
818 .max_bpp = 32,
819 .default_bpp = 16,
820};
821
822static struct s3c_fb_platdata universal_lcd_pdata __initdata = {
823 .win[0] = &universal_fb_win0,
824 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB |
825 VIDCON0_CLKSEL_LCD,
826 .vidcon1 = VIDCON1_INV_VCLK | VIDCON1_INV_VDEN
827 | VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
828 .setup_gpio = exynos4_fimd0_gpio_setup_24bpp,
829};
830
831static struct regulator_consumer_supply cam_i_core_supply =
832 REGULATOR_SUPPLY("core", "0-001f");
833
834static struct regulator_init_data cam_i_core_reg_init_data = {
835 .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS },
836 .num_consumer_supplies = 1,
837 .consumer_supplies = &cam_i_core_supply,
838};
839
840static struct fixed_voltage_config cam_i_core_fixed_voltage_cfg = {
841 .supply_name = "CAM_I_CORE_1.2V",
842 .microvolts = 1200000,
843 .gpio = EXYNOS4_GPE2(2), /* CAM_8M_CORE_EN */
844 .enable_high = 1,
845 .init_data = &cam_i_core_reg_init_data,
846};
847
848static struct platform_device cam_i_core_fixed_reg_dev = {
849 .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_I_CORE,
850 .dev = { .platform_data = &cam_i_core_fixed_voltage_cfg },
851};
852
853static struct regulator_consumer_supply cam_s_if_supply =
854 REGULATOR_SUPPLY("d_sensor", "0-001f");
855
856static struct regulator_init_data cam_s_if_reg_init_data = {
857 .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS },
858 .num_consumer_supplies = 1,
859 .consumer_supplies = &cam_s_if_supply,
860};
861
862static struct fixed_voltage_config cam_s_if_fixed_voltage_cfg = {
863 .supply_name = "CAM_S_IF_1.8V",
864 .microvolts = 1800000,
865 .gpio = EXYNOS4_GPE3(0), /* CAM_PWR_EN1 */
866 .enable_high = 1,
867 .init_data = &cam_s_if_reg_init_data,
868};
869
870static struct platform_device cam_s_if_fixed_reg_dev = {
871 .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_S_IF,
872 .dev = { .platform_data = &cam_s_if_fixed_voltage_cfg },
873};
874
875static struct s5p_platform_mipi_csis mipi_csis_platdata = {
876 .clk_rate = 166000000UL,
877 .lanes = 2,
878 .alignment = 32,
879 .hs_settle = 12,
880 .phy_enable = s5p_csis_phy_enable,
881};
882
883#define GPIO_CAM_LEVEL_EN(n) EXYNOS4_GPE4(n + 3)
884#define GPIO_CAM_8M_ISP_INT EXYNOS4_GPX1(5) /* XEINT_13 */
885#define GPIO_CAM_MEGA_nRST EXYNOS4_GPE2(5)
886
887static int m5mols_set_power(struct device *dev, int on)
888{
889 gpio_set_value(GPIO_CAM_LEVEL_EN(1), !on);
890 gpio_set_value(GPIO_CAM_LEVEL_EN(2), !!on);
891 return 0;
892}
893
894static struct m5mols_platform_data m5mols_platdata = {
895 .gpio_reset = GPIO_CAM_MEGA_nRST,
896 .reset_polarity = 0,
897 .set_power = m5mols_set_power,
898};
899
900static struct i2c_board_info m5mols_board_info = {
901 I2C_BOARD_INFO("M5MOLS", 0x1F),
902 .platform_data = &m5mols_platdata,
903};
904
905static struct s5p_fimc_isp_info universal_camera_sensors[] = {
906 {
907 .mux_id = 0,
908 .flags = V4L2_MBUS_PCLK_SAMPLE_FALLING |
909 V4L2_MBUS_VSYNC_ACTIVE_LOW,
910 .bus_type = FIMC_MIPI_CSI2,
911 .board_info = &m5mols_board_info,
912 .i2c_bus_num = 0,
913 .clk_frequency = 21600000UL,
914 .csi_data_align = 32,
915 },
916};
917
918static struct s5p_platform_fimc fimc_md_platdata = {
919 .isp_info = universal_camera_sensors,
920 .num_clients = ARRAY_SIZE(universal_camera_sensors),
921};
922
923struct platform_device s5p_device_fimc_md = {
924 .name = "s5p-fimc-md",
925 .id = -1,
926};
927
928static struct gpio universal_camera_gpios[] = {
929 { GPIO_CAM_LEVEL_EN(1), GPIOF_OUT_INIT_HIGH, "CAM_LVL_EN1" },
930 { GPIO_CAM_LEVEL_EN(2), GPIOF_OUT_INIT_LOW, "CAM_LVL_EN2" },
931 { GPIO_CAM_8M_ISP_INT, GPIOF_IN, "8M_ISP_INT" },
932 { GPIO_CAM_MEGA_nRST, GPIOF_OUT_INIT_LOW, "CAM_8M_NRST" },
933};
934
935static void universal_camera_init(void)
936{
937 s3c_set_platdata(&mipi_csis_platdata, sizeof(mipi_csis_platdata),
938 &s5p_device_mipi_csis0);
939 s3c_set_platdata(&fimc_md_platdata, sizeof(fimc_md_platdata),
940 &s5p_device_fimc_md);
941
942 if (gpio_request_array(universal_camera_gpios,
943 ARRAY_SIZE(universal_camera_gpios))) {
944 pr_err("%s: GPIO request failed\n", __func__);
945 return;
946 }
947
948 if (!s3c_gpio_cfgpin(GPIO_CAM_8M_ISP_INT, S3C_GPIO_SFN(0xf)))
949 m5mols_board_info.irq = gpio_to_irq(GPIO_CAM_8M_ISP_INT);
950 else
951 pr_err("Failed to configure 8M_ISP_INT GPIO\n");
952
953 /* Free GPIOs controlled directly by the sensor drivers. */
954 gpio_free(GPIO_CAM_MEGA_nRST);
955 gpio_free(GPIO_CAM_8M_ISP_INT);
956
957 if (exynos4_fimc_setup_gpio(S5P_CAMPORT_A))
958 pr_err("Camera port A setup failed\n");
959}
960
705static struct platform_device *universal_devices[] __initdata = { 961static struct platform_device *universal_devices[] __initdata = {
706 /* Samsung Platform Devices */ 962 /* Samsung Platform Devices */
963 &s5p_device_mipi_csis0,
707 &s5p_device_fimc0, 964 &s5p_device_fimc0,
708 &s5p_device_fimc1, 965 &s5p_device_fimc1,
709 &s5p_device_fimc2, 966 &s5p_device_fimc2,
@@ -712,17 +969,30 @@ static struct platform_device *universal_devices[] __initdata = {
712 &s3c_device_hsmmc0, 969 &s3c_device_hsmmc0,
713 &s3c_device_hsmmc2, 970 &s3c_device_hsmmc2,
714 &s3c_device_hsmmc3, 971 &s3c_device_hsmmc3,
972 &s3c_device_i2c0,
715 &s3c_device_i2c3, 973 &s3c_device_i2c3,
716 &s3c_device_i2c5, 974 &s3c_device_i2c5,
975 &s5p_device_i2c_hdmiphy,
976 &hdmi_fixed_voltage,
977 &exynos4_device_pd[PD_TV],
978 &s5p_device_hdmi,
979 &s5p_device_sdo,
980 &s5p_device_mixer,
717 981
718 /* Universal Devices */ 982 /* Universal Devices */
719 &i2c_gpio12, 983 &i2c_gpio12,
720 &universal_gpio_keys, 984 &universal_gpio_keys,
721 &s5p_device_onenand, 985 &s5p_device_onenand,
986 &s5p_device_fimd0,
722 &s5p_device_mfc, 987 &s5p_device_mfc,
723 &s5p_device_mfc_l, 988 &s5p_device_mfc_l,
724 &s5p_device_mfc_r, 989 &s5p_device_mfc_r,
725 &exynos4_device_pd[PD_MFC], 990 &exynos4_device_pd[PD_MFC],
991 &exynos4_device_pd[PD_LCD0],
992 &exynos4_device_pd[PD_CAM],
993 &cam_i_core_fixed_reg_dev,
994 &cam_s_if_fixed_reg_dev,
995 &s5p_device_fimc_md,
726}; 996};
727 997
728static void __init universal_map_io(void) 998static void __init universal_map_io(void)
@@ -732,6 +1002,20 @@ static void __init universal_map_io(void)
732 s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs)); 1002 s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
733} 1003}
734 1004
1005void s5p_tv_setup(void)
1006{
1007 /* direct HPD to HDMI chip */
1008 gpio_request(EXYNOS4_GPX3(7), "hpd-plug");
1009
1010 gpio_direction_input(EXYNOS4_GPX3(7));
1011 s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3));
1012 s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE);
1013
1014 /* setup dependencies between TV devices */
1015 s5p_device_hdmi.dev.parent = &exynos4_device_pd[PD_TV].dev;
1016 s5p_device_mixer.dev.parent = &exynos4_device_pd[PD_TV].dev;
1017}
1018
735static void __init universal_reserve(void) 1019static void __init universal_reserve(void)
736{ 1020{
737 s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20); 1021 s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
@@ -740,8 +1024,9 @@ static void __init universal_reserve(void)
740static void __init universal_machine_init(void) 1024static void __init universal_machine_init(void)
741{ 1025{
742 universal_sdhci_init(); 1026 universal_sdhci_init();
1027 s5p_tv_setup();
743 1028
744 i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs)); 1029 s3c_i2c0_set_platdata(&universal_i2c0_platdata);
745 i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs)); 1030 i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
746 1031
747 universal_tsp_init(); 1032 universal_tsp_init();
@@ -749,15 +1034,28 @@ static void __init universal_machine_init(void)
749 i2c_register_board_info(3, i2c3_devs, ARRAY_SIZE(i2c3_devs)); 1034 i2c_register_board_info(3, i2c3_devs, ARRAY_SIZE(i2c3_devs));
750 1035
751 s3c_i2c5_set_platdata(NULL); 1036 s3c_i2c5_set_platdata(NULL);
1037 s5p_i2c_hdmiphy_set_platdata(NULL);
752 i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs)); 1038 i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs));
753 1039
1040 s5p_fimd0_set_platdata(&universal_lcd_pdata);
1041
754 universal_touchkey_init(); 1042 universal_touchkey_init();
755 i2c_register_board_info(I2C_GPIO_BUS_12, i2c_gpio12_devs, 1043 i2c_register_board_info(I2C_GPIO_BUS_12, i2c_gpio12_devs,
756 ARRAY_SIZE(i2c_gpio12_devs)); 1044 ARRAY_SIZE(i2c_gpio12_devs));
757 1045
1046 universal_camera_init();
1047
758 /* Last */ 1048 /* Last */
759 platform_add_devices(universal_devices, ARRAY_SIZE(universal_devices)); 1049 platform_add_devices(universal_devices, ARRAY_SIZE(universal_devices));
1050
760 s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev; 1051 s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
1052 s5p_device_fimd0.dev.parent = &exynos4_device_pd[PD_LCD0].dev;
1053
1054 s5p_device_fimc0.dev.parent = &exynos4_device_pd[PD_CAM].dev;
1055 s5p_device_fimc1.dev.parent = &exynos4_device_pd[PD_CAM].dev;
1056 s5p_device_fimc2.dev.parent = &exynos4_device_pd[PD_CAM].dev;
1057 s5p_device_fimc3.dev.parent = &exynos4_device_pd[PD_CAM].dev;
1058 s5p_device_mipi_csis0.dev.parent = &exynos4_device_pd[PD_CAM].dev;
761} 1059}
762 1060
763MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210") 1061MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
diff --git a/arch/arm/mach-exynos4/pm.c b/arch/arm/mach-exynos4/pm.c
index 62e4f436300..509a435afd4 100644
--- a/arch/arm/mach-exynos4/pm.c
+++ b/arch/arm/mach-exynos4/pm.c
@@ -339,6 +339,13 @@ static int exynos4_pm_suspend(void)
339 tmp &= ~S5P_CENTRAL_LOWPWR_CFG; 339 tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
340 __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); 340 __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
341 341
342 if (soc_is_exynos4212()) {
343 tmp = __raw_readl(S5P_CENTRAL_SEQ_OPTION);
344 tmp &= ~(S5P_USE_STANDBYWFI_ISP_ARM |
345 S5P_USE_STANDBYWFE_ISP_ARM);
346 __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
347 }
348
342 /* Save Power control register */ 349 /* Save Power control register */
343 asm ("mrc p15, 0, %0, c15, c0, 0" 350 asm ("mrc p15, 0, %0, c15, c0, 0"
344 : "=r" (tmp) : : "cc"); 351 : "=r" (tmp) : : "cc");
diff --git a/arch/arm/mach-exynos4/pmu.c b/arch/arm/mach-exynos4/pmu.c
index 7ea9eb2a20d..bba48f5c3e8 100644
--- a/arch/arm/mach-exynos4/pmu.c
+++ b/arch/arm/mach-exynos4/pmu.c
@@ -16,160 +16,215 @@
16#include <mach/regs-clock.h> 16#include <mach/regs-clock.h>
17#include <mach/pmu.h> 17#include <mach/pmu.h>
18 18
19static void __iomem *sys_powerdown_reg[] = { 19static struct exynos4_pmu_conf *exynos4_pmu_config;
20 S5P_ARM_CORE0_LOWPWR, 20
21 S5P_DIS_IRQ_CORE0, 21static struct exynos4_pmu_conf exynos4210_pmu_config[] = {
22 S5P_DIS_IRQ_CENTRAL0, 22 /* { .reg = address, .val = { AFTR, LPA, SLEEP } */
23 S5P_ARM_CORE1_LOWPWR, 23 { S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } },
24 S5P_DIS_IRQ_CORE1, 24 { S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } },
25 S5P_DIS_IRQ_CENTRAL1, 25 { S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } },
26 S5P_ARM_COMMON_LOWPWR, 26 { S5P_ARM_CORE1_LOWPWR, { 0x0, 0x0, 0x2 } },
27 S5P_L2_0_LOWPWR, 27 { S5P_DIS_IRQ_CORE1, { 0x0, 0x0, 0x0 } },
28 S5P_L2_1_LOWPWR, 28 { S5P_DIS_IRQ_CENTRAL1, { 0x0, 0x0, 0x0 } },
29 S5P_CMU_ACLKSTOP_LOWPWR, 29 { S5P_ARM_COMMON_LOWPWR, { 0x0, 0x0, 0x2 } },
30 S5P_CMU_SCLKSTOP_LOWPWR, 30 { S5P_L2_0_LOWPWR, { 0x2, 0x2, 0x3 } },
31 S5P_CMU_RESET_LOWPWR, 31 { S5P_L2_1_LOWPWR, { 0x2, 0x2, 0x3 } },
32 S5P_APLL_SYSCLK_LOWPWR, 32 { S5P_CMU_ACLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } },
33 S5P_MPLL_SYSCLK_LOWPWR, 33 { S5P_CMU_SCLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } },
34 S5P_VPLL_SYSCLK_LOWPWR, 34 { S5P_CMU_RESET_LOWPWR, { 0x1, 0x1, 0x0 } },
35 S5P_EPLL_SYSCLK_LOWPWR, 35 { S5P_APLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
36 S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR, 36 { S5P_MPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
37 S5P_CMU_RESET_GPSALIVE_LOWPWR, 37 { S5P_VPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
38 S5P_CMU_CLKSTOP_CAM_LOWPWR, 38 { S5P_EPLL_SYSCLK_LOWPWR, { 0x1, 0x1, 0x0 } },
39 S5P_CMU_CLKSTOP_TV_LOWPWR, 39 { S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR, { 0x1, 0x1, 0x0 } },
40 S5P_CMU_CLKSTOP_MFC_LOWPWR, 40 { S5P_CMU_RESET_GPSALIVE_LOWPWR, { 0x1, 0x1, 0x0 } },
41 S5P_CMU_CLKSTOP_G3D_LOWPWR, 41 { S5P_CMU_CLKSTOP_CAM_LOWPWR, { 0x1, 0x1, 0x0 } },
42 S5P_CMU_CLKSTOP_LCD0_LOWPWR, 42 { S5P_CMU_CLKSTOP_TV_LOWPWR, { 0x1, 0x1, 0x0 } },
43 S5P_CMU_CLKSTOP_LCD1_LOWPWR, 43 { S5P_CMU_CLKSTOP_MFC_LOWPWR, { 0x1, 0x1, 0x0 } },
44 S5P_CMU_CLKSTOP_MAUDIO_LOWPWR, 44 { S5P_CMU_CLKSTOP_G3D_LOWPWR, { 0x1, 0x1, 0x0 } },
45 S5P_CMU_CLKSTOP_GPS_LOWPWR, 45 { S5P_CMU_CLKSTOP_LCD0_LOWPWR, { 0x1, 0x1, 0x0 } },
46 S5P_CMU_RESET_CAM_LOWPWR, 46 { S5P_CMU_CLKSTOP_LCD1_LOWPWR, { 0x1, 0x1, 0x0 } },
47 S5P_CMU_RESET_TV_LOWPWR, 47 { S5P_CMU_CLKSTOP_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
48 S5P_CMU_RESET_MFC_LOWPWR, 48 { S5P_CMU_CLKSTOP_GPS_LOWPWR, { 0x1, 0x1, 0x0 } },
49 S5P_CMU_RESET_G3D_LOWPWR, 49 { S5P_CMU_RESET_CAM_LOWPWR, { 0x1, 0x1, 0x0 } },
50 S5P_CMU_RESET_LCD0_LOWPWR, 50 { S5P_CMU_RESET_TV_LOWPWR, { 0x1, 0x1, 0x0 } },
51 S5P_CMU_RESET_LCD1_LOWPWR, 51 { S5P_CMU_RESET_MFC_LOWPWR, { 0x1, 0x1, 0x0 } },
52 S5P_CMU_RESET_MAUDIO_LOWPWR, 52 { S5P_CMU_RESET_G3D_LOWPWR, { 0x1, 0x1, 0x0 } },
53 S5P_CMU_RESET_GPS_LOWPWR, 53 { S5P_CMU_RESET_LCD0_LOWPWR, { 0x1, 0x1, 0x0 } },
54 S5P_TOP_BUS_LOWPWR, 54 { S5P_CMU_RESET_LCD1_LOWPWR, { 0x1, 0x1, 0x0 } },
55 S5P_TOP_RETENTION_LOWPWR, 55 { S5P_CMU_RESET_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
56 S5P_TOP_PWR_LOWPWR, 56 { S5P_CMU_RESET_GPS_LOWPWR, { 0x1, 0x1, 0x0 } },
57 S5P_LOGIC_RESET_LOWPWR, 57 { S5P_TOP_BUS_LOWPWR, { 0x3, 0x0, 0x0 } },
58 S5P_ONENAND_MEM_LOWPWR, 58 { S5P_TOP_RETENTION_LOWPWR, { 0x1, 0x0, 0x1 } },
59 S5P_MODIMIF_MEM_LOWPWR, 59 { S5P_TOP_PWR_LOWPWR, { 0x3, 0x0, 0x3 } },
60 S5P_G2D_ACP_MEM_LOWPWR, 60 { S5P_LOGIC_RESET_LOWPWR, { 0x1, 0x1, 0x0 } },
61 S5P_USBOTG_MEM_LOWPWR, 61 { S5P_ONENAND_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
62 S5P_HSMMC_MEM_LOWPWR, 62 { S5P_MODIMIF_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
63 S5P_CSSYS_MEM_LOWPWR, 63 { S5P_G2D_ACP_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
64 S5P_SECSS_MEM_LOWPWR, 64 { S5P_USBOTG_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
65 S5P_PCIE_MEM_LOWPWR, 65 { S5P_HSMMC_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
66 S5P_SATA_MEM_LOWPWR, 66 { S5P_CSSYS_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
67 S5P_PAD_RETENTION_DRAM_LOWPWR, 67 { S5P_SECSS_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
68 S5P_PAD_RETENTION_MAUDIO_LOWPWR, 68 { S5P_PCIE_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
69 S5P_PAD_RETENTION_GPIO_LOWPWR, 69 { S5P_SATA_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
70 S5P_PAD_RETENTION_UART_LOWPWR, 70 { S5P_PAD_RETENTION_DRAM_LOWPWR, { 0x1, 0x0, 0x0 } },
71 S5P_PAD_RETENTION_MMCA_LOWPWR, 71 { S5P_PAD_RETENTION_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
72 S5P_PAD_RETENTION_MMCB_LOWPWR, 72 { S5P_PAD_RETENTION_GPIO_LOWPWR, { 0x1, 0x0, 0x0 } },
73 S5P_PAD_RETENTION_EBIA_LOWPWR, 73 { S5P_PAD_RETENTION_UART_LOWPWR, { 0x1, 0x0, 0x0 } },
74 S5P_PAD_RETENTION_EBIB_LOWPWR, 74 { S5P_PAD_RETENTION_MMCA_LOWPWR, { 0x1, 0x0, 0x0 } },
75 S5P_PAD_RETENTION_ISOLATION_LOWPWR, 75 { S5P_PAD_RETENTION_MMCB_LOWPWR, { 0x1, 0x0, 0x0 } },
76 S5P_PAD_RETENTION_ALV_SEL_LOWPWR, 76 { S5P_PAD_RETENTION_EBIA_LOWPWR, { 0x1, 0x0, 0x0 } },
77 S5P_XUSBXTI_LOWPWR, 77 { S5P_PAD_RETENTION_EBIB_LOWPWR, { 0x1, 0x0, 0x0 } },
78 S5P_XXTI_LOWPWR, 78 { S5P_PAD_RETENTION_ISOLATION_LOWPWR, { 0x1, 0x0, 0x0 } },
79 S5P_EXT_REGULATOR_LOWPWR, 79 { S5P_PAD_RETENTION_ALV_SEL_LOWPWR, { 0x1, 0x0, 0x0 } },
80 S5P_GPIO_MODE_LOWPWR, 80 { S5P_XUSBXTI_LOWPWR, { 0x1, 0x1, 0x0 } },
81 S5P_GPIO_MODE_MAUDIO_LOWPWR, 81 { S5P_XXTI_LOWPWR, { 0x1, 0x1, 0x0 } },
82 S5P_CAM_LOWPWR, 82 { S5P_EXT_REGULATOR_LOWPWR, { 0x1, 0x1, 0x0 } },
83 S5P_TV_LOWPWR, 83 { S5P_GPIO_MODE_LOWPWR, { 0x1, 0x0, 0x0 } },
84 S5P_MFC_LOWPWR, 84 { S5P_GPIO_MODE_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
85 S5P_G3D_LOWPWR, 85 { S5P_CAM_LOWPWR, { 0x7, 0x0, 0x0 } },
86 S5P_LCD0_LOWPWR, 86 { S5P_TV_LOWPWR, { 0x7, 0x0, 0x0 } },
87 S5P_LCD1_LOWPWR, 87 { S5P_MFC_LOWPWR, { 0x7, 0x0, 0x0 } },
88 S5P_MAUDIO_LOWPWR, 88 { S5P_G3D_LOWPWR, { 0x7, 0x0, 0x0 } },
89 S5P_GPS_LOWPWR, 89 { S5P_LCD0_LOWPWR, { 0x7, 0x0, 0x0 } },
90 S5P_GPS_ALIVE_LOWPWR, 90 { S5P_LCD1_LOWPWR, { 0x7, 0x0, 0x0 } },
91 { S5P_MAUDIO_LOWPWR, { 0x7, 0x7, 0x0 } },
92 { S5P_GPS_LOWPWR, { 0x7, 0x0, 0x0 } },
93 { S5P_GPS_ALIVE_LOWPWR, { 0x7, 0x0, 0x0 } },
94 { PMU_TABLE_END,},
91}; 95};
92 96
93static const unsigned int sys_powerdown_val[][NUM_SYS_POWERDOWN] = { 97static struct exynos4_pmu_conf exynos4212_pmu_config[] = {
94 /* { AFTR, LPA, SLEEP }*/ 98 { S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } },
95 { 0, 0, 2 }, /* ARM_CORE0 */ 99 { S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } },
96 { 0, 0, 0 }, /* ARM_DIS_IRQ_CORE0 */ 100 { S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } },
97 { 0, 0, 0 }, /* ARM_DIS_IRQ_CENTRAL0 */ 101 { S5P_ARM_CORE1_LOWPWR, { 0x0, 0x0, 0x2 } },
98 { 0, 0, 2 }, /* ARM_CORE1 */ 102 { S5P_DIS_IRQ_CORE1, { 0x0, 0x0, 0x0 } },
99 { 0, 0, 0 }, /* ARM_DIS_IRQ_CORE1 */ 103 { S5P_DIS_IRQ_CENTRAL1, { 0x0, 0x0, 0x0 } },
100 { 0, 0, 0 }, /* ARM_DIS_IRQ_CENTRAL1 */ 104 { S5P_ISP_ARM_LOWPWR, { 0x1, 0x0, 0x0 } },
101 { 0, 0, 2 }, /* ARM_COMMON */ 105 { S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR, { 0x0, 0x0, 0x0 } },
102 { 2, 2, 3 }, /* ARM_CPU_L2_0 */ 106 { S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR, { 0x0, 0x0, 0x0 } },
103 { 2, 2, 3 }, /* ARM_CPU_L2_1 */ 107 { S5P_ARM_COMMON_LOWPWR, { 0x0, 0x0, 0x2 } },
104 { 1, 0, 0 }, /* CMU_ACLKSTOP */ 108 { S5P_L2_0_LOWPWR, { 0x0, 0x0, 0x3 } },
105 { 1, 0, 0 }, /* CMU_SCLKSTOP */ 109 /* XXX_OPTION register should be set other field */
106 { 1, 1, 0 }, /* CMU_RESET */ 110 { S5P_ARM_L2_0_OPTION, { 0x10, 0x10, 0x0 } },
107 { 1, 0, 0 }, /* APLL_SYSCLK */ 111 { S5P_L2_1_LOWPWR, { 0x0, 0x0, 0x3 } },
108 { 1, 0, 0 }, /* MPLL_SYSCLK */ 112 { S5P_ARM_L2_1_OPTION, { 0x10, 0x10, 0x0 } },
109 { 1, 0, 0 }, /* VPLL_SYSCLK */ 113 { S5P_CMU_ACLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } },
110 { 1, 1, 0 }, /* EPLL_SYSCLK */ 114 { S5P_CMU_SCLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } },
111 { 1, 1, 0 }, /* CMU_CLKSTOP_GPS_ALIVE */ 115 { S5P_CMU_RESET_LOWPWR, { 0x1, 0x1, 0x0 } },
112 { 1, 1, 0 }, /* CMU_RESET_GPS_ALIVE */ 116 { S5P_DRAM_FREQ_DOWN_LOWPWR, { 0x1, 0x1, 0x1 } },
113 { 1, 1, 0 }, /* CMU_CLKSTOP_CAM */ 117 { S5P_DDRPHY_DLLOFF_LOWPWR, { 0x1, 0x1, 0x1 } },
114 { 1, 1, 0 }, /* CMU_CLKSTOP_TV */ 118 { S5P_LPDDR_PHY_DLL_LOCK_LOWPWR, { 0x1, 0x1, 0x1 } },
115 { 1, 1, 0 }, /* CMU_CLKSTOP_MFC */ 119 { S5P_CMU_ACLKSTOP_COREBLK_LOWPWR, { 0x1, 0x0, 0x0 } },
116 { 1, 1, 0 }, /* CMU_CLKSTOP_G3D */ 120 { S5P_CMU_SCLKSTOP_COREBLK_LOWPWR, { 0x1, 0x0, 0x0 } },
117 { 1, 1, 0 }, /* CMU_CLKSTOP_LCD0 */ 121 { S5P_CMU_RESET_COREBLK_LOWPWR, { 0x1, 0x1, 0x0 } },
118 { 1, 1, 0 }, /* CMU_CLKSTOP_LCD1 */ 122 { S5P_APLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
119 { 1, 1, 0 }, /* CMU_CLKSTOP_MAUDIO */ 123 { S5P_MPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
120 { 1, 1, 0 }, /* CMU_CLKSTOP_GPS */ 124 { S5P_VPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
121 { 1, 1, 0 }, /* CMU_RESET_CAM */ 125 { S5P_EPLL_SYSCLK_LOWPWR, { 0x1, 0x1, 0x0 } },
122 { 1, 1, 0 }, /* CMU_RESET_TV */ 126 { S5P_MPLLUSER_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
123 { 1, 1, 0 }, /* CMU_RESET_MFC */ 127 { S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR, { 0x1, 0x0, 0x0 } },
124 { 1, 1, 0 }, /* CMU_RESET_G3D */ 128 { S5P_CMU_RESET_GPSALIVE_LOWPWR, { 0x1, 0x0, 0x0 } },
125 { 1, 1, 0 }, /* CMU_RESET_LCD0 */ 129 { S5P_CMU_CLKSTOP_CAM_LOWPWR, { 0x1, 0x0, 0x0 } },
126 { 1, 1, 0 }, /* CMU_RESET_LCD1 */ 130 { S5P_CMU_CLKSTOP_TV_LOWPWR, { 0x1, 0x0, 0x0 } },
127 { 1, 1, 0 }, /* CMU_RESET_MAUDIO */ 131 { S5P_CMU_CLKSTOP_MFC_LOWPWR, { 0x1, 0x0, 0x0 } },
128 { 1, 1, 0 }, /* CMU_RESET_GPS */ 132 { S5P_CMU_CLKSTOP_G3D_LOWPWR, { 0x1, 0x0, 0x0 } },
129 { 3, 0, 0 }, /* TOP_BUS */ 133 { S5P_CMU_CLKSTOP_LCD0_LOWPWR, { 0x1, 0x0, 0x0 } },
130 { 1, 0, 1 }, /* TOP_RETENTION */ 134 { S5P_CMU_CLKSTOP_ISP_LOWPWR, { 0x1, 0x0, 0x0 } },
131 { 3, 0, 3 }, /* TOP_PWR */ 135 { S5P_CMU_CLKSTOP_MAUDIO_LOWPWR, { 0x1, 0x0, 0x0 } },
132 { 1, 1, 0 }, /* LOGIC_RESET */ 136 { S5P_CMU_CLKSTOP_GPS_LOWPWR, { 0x1, 0x0, 0x0 } },
133 { 3, 0, 0 }, /* ONENAND_MEM */ 137 { S5P_CMU_RESET_CAM_LOWPWR, { 0x1, 0x0, 0x0 } },
134 { 3, 0, 0 }, /* MODIMIF_MEM */ 138 { S5P_CMU_RESET_TV_LOWPWR, { 0x1, 0x0, 0x0 } },
135 { 3, 0, 0 }, /* G2D_ACP_MEM */ 139 { S5P_CMU_RESET_MFC_LOWPWR, { 0x1, 0x0, 0x0 } },
136 { 3, 0, 0 }, /* USBOTG_MEM */ 140 { S5P_CMU_RESET_G3D_LOWPWR, { 0x1, 0x0, 0x0 } },
137 { 3, 0, 0 }, /* HSMMC_MEM */ 141 { S5P_CMU_RESET_LCD0_LOWPWR, { 0x1, 0x0, 0x0 } },
138 { 3, 0, 0 }, /* CSSYS_MEM */ 142 { S5P_CMU_RESET_ISP_LOWPWR, { 0x1, 0x0, 0x0 } },
139 { 3, 0, 0 }, /* SECSS_MEM */ 143 { S5P_CMU_RESET_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
140 { 3, 0, 0 }, /* PCIE_MEM */ 144 { S5P_CMU_RESET_GPS_LOWPWR, { 0x1, 0x0, 0x0 } },
141 { 3, 0, 0 }, /* SATA_MEM */ 145 { S5P_TOP_BUS_LOWPWR, { 0x3, 0x0, 0x0 } },
142 { 1, 0, 0 }, /* PAD_RETENTION_DRAM */ 146 { S5P_TOP_RETENTION_LOWPWR, { 0x1, 0x0, 0x1 } },
143 { 1, 1, 0 }, /* PAD_RETENTION_MAUDIO */ 147 { S5P_TOP_PWR_LOWPWR, { 0x3, 0x0, 0x3 } },
144 { 1, 0, 0 }, /* PAD_RETENTION_GPIO */ 148 { S5P_TOP_BUS_COREBLK_LOWPWR, { 0x3, 0x0, 0x0 } },
145 { 1, 0, 0 }, /* PAD_RETENTION_UART */ 149 { S5P_TOP_RETENTION_COREBLK_LOWPWR, { 0x1, 0x0, 0x1 } },
146 { 1, 0, 0 }, /* PAD_RETENTION_MMCA */ 150 { S5P_TOP_PWR_COREBLK_LOWPWR, { 0x3, 0x0, 0x3 } },
147 { 1, 0, 0 }, /* PAD_RETENTION_MMCB */ 151 { S5P_LOGIC_RESET_LOWPWR, { 0x1, 0x1, 0x0 } },
148 { 1, 0, 0 }, /* PAD_RETENTION_EBIA */ 152 { S5P_OSCCLK_GATE_LOWPWR, { 0x1, 0x0, 0x1 } },
149 { 1, 0, 0 }, /* PAD_RETENTION_EBIB */ 153 { S5P_LOGIC_RESET_COREBLK_LOWPWR, { 0x1, 0x1, 0x0 } },
150 { 1, 0, 0 }, /* PAD_RETENTION_ISOLATION */ 154 { S5P_OSCCLK_GATE_COREBLK_LOWPWR, { 0x1, 0x0, 0x1 } },
151 { 1, 0, 0 }, /* PAD_RETENTION_ALV_SEL */ 155 { S5P_ONENAND_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
152 { 1, 1, 0 }, /* XUSBXTI */ 156 { S5P_ONENAND_MEM_OPTION, { 0x10, 0x10, 0x0 } },
153 { 1, 1, 0 }, /* XXTI */ 157 { S5P_HSI_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
154 { 1, 1, 0 }, /* EXT_REGULATOR */ 158 { S5P_HSI_MEM_OPTION, { 0x10, 0x10, 0x0 } },
155 { 1, 0, 0 }, /* GPIO_MODE */ 159 { S5P_G2D_ACP_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
156 { 1, 1, 0 }, /* GPIO_MODE_MAUDIO */ 160 { S5P_G2D_ACP_MEM_OPTION, { 0x10, 0x10, 0x0 } },
157 { 7, 0, 0 }, /* CAM */ 161 { S5P_USBOTG_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
158 { 7, 0, 0 }, /* TV */ 162 { S5P_USBOTG_MEM_OPTION, { 0x10, 0x10, 0x0 } },
159 { 7, 0, 0 }, /* MFC */ 163 { S5P_HSMMC_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
160 { 7, 0, 0 }, /* G3D */ 164 { S5P_HSMMC_MEM_OPTION, { 0x10, 0x10, 0x0 } },
161 { 7, 0, 0 }, /* LCD0 */ 165 { S5P_CSSYS_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
162 { 7, 0, 0 }, /* LCD1 */ 166 { S5P_CSSYS_MEM_OPTION, { 0x10, 0x10, 0x0 } },
163 { 7, 7, 0 }, /* MAUDIO */ 167 { S5P_SECSS_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
164 { 7, 0, 0 }, /* GPS */ 168 { S5P_SECSS_MEM_OPTION, { 0x10, 0x10, 0x0 } },
165 { 7, 0, 0 }, /* GPS_ALIVE */ 169 { S5P_ROTATOR_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
170 { S5P_ROTATOR_MEM_OPTION, { 0x10, 0x10, 0x0 } },
171 { S5P_PAD_RETENTION_DRAM_LOWPWR, { 0x1, 0x0, 0x0 } },
172 { S5P_PAD_RETENTION_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
173 { S5P_PAD_RETENTION_GPIO_LOWPWR, { 0x1, 0x0, 0x0 } },
174 { S5P_PAD_RETENTION_UART_LOWPWR, { 0x1, 0x0, 0x0 } },
175 { S5P_PAD_RETENTION_MMCA_LOWPWR, { 0x1, 0x0, 0x0 } },
176 { S5P_PAD_RETENTION_MMCB_LOWPWR, { 0x1, 0x0, 0x0 } },
177 { S5P_PAD_RETENTION_EBIA_LOWPWR, { 0x1, 0x0, 0x0 } },
178 { S5P_PAD_RETENTION_EBIB_LOWPWR, { 0x1, 0x0, 0x0 } },
179 { S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR,{ 0x1, 0x0, 0x0 } },
180 { S5P_PAD_RETENTION_ISOLATION_LOWPWR, { 0x1, 0x0, 0x0 } },
181 { S5P_PAD_ISOLATION_COREBLK_LOWPWR, { 0x1, 0x0, 0x0 } },
182 { S5P_PAD_RETENTION_ALV_SEL_LOWPWR, { 0x1, 0x0, 0x0 } },
183 { S5P_XUSBXTI_LOWPWR, { 0x1, 0x1, 0x0 } },
184 { S5P_XXTI_LOWPWR, { 0x1, 0x1, 0x0 } },
185 { S5P_EXT_REGULATOR_LOWPWR, { 0x1, 0x1, 0x0 } },
186 { S5P_GPIO_MODE_LOWPWR, { 0x1, 0x0, 0x0 } },
187 { S5P_GPIO_MODE_COREBLK_LOWPWR, { 0x1, 0x0, 0x0 } },
188 { S5P_GPIO_MODE_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
189 { S5P_TOP_ASB_RESET_LOWPWR, { 0x1, 0x1, 0x1 } },
190 { S5P_TOP_ASB_ISOLATION_LOWPWR, { 0x1, 0x0, 0x1 } },
191 { S5P_CAM_LOWPWR, { 0x7, 0x0, 0x0 } },
192 { S5P_TV_LOWPWR, { 0x7, 0x0, 0x0 } },
193 { S5P_MFC_LOWPWR, { 0x7, 0x0, 0x0 } },
194 { S5P_G3D_LOWPWR, { 0x7, 0x0, 0x0 } },
195 { S5P_LCD0_LOWPWR, { 0x7, 0x0, 0x0 } },
196 { S5P_ISP_LOWPWR, { 0x7, 0x0, 0x0 } },
197 { S5P_MAUDIO_LOWPWR, { 0x7, 0x7, 0x0 } },
198 { S5P_GPS_LOWPWR, { 0x7, 0x0, 0x0 } },
199 { S5P_GPS_ALIVE_LOWPWR, { 0x7, 0x0, 0x0 } },
200 { S5P_CMU_SYSCLK_ISP_LOWPWR, { 0x1, 0x0, 0x0 } },
201 { S5P_CMU_SYSCLK_GPS_LOWPWR, { 0x1, 0x0, 0x0 } },
202 { PMU_TABLE_END,},
166}; 203};
167 204
168void exynos4_sys_powerdown_conf(enum sys_powerdown mode) 205void exynos4_sys_powerdown_conf(enum sys_powerdown mode)
169{ 206{
170 unsigned int count = ARRAY_SIZE(sys_powerdown_reg); 207 unsigned int i;
208
209 for (i = 0; (exynos4_pmu_config[i].reg != PMU_TABLE_END) ; i++)
210 __raw_writel(exynos4_pmu_config[i].val[mode],
211 exynos4_pmu_config[i].reg);
212}
213
214static int __init exynos4_pmu_init(void)
215{
216 exynos4_pmu_config = exynos4210_pmu_config;
217
218 if (soc_is_exynos4210()) {
219 exynos4_pmu_config = exynos4210_pmu_config;
220 pr_info("EXYNOS4210 PMU Initialize\n");
221 } else if (soc_is_exynos4212()) {
222 exynos4_pmu_config = exynos4212_pmu_config;
223 pr_info("EXYNOS4212 PMU Initialize\n");
224 } else {
225 pr_info("EXYNOS4: PMU not supported\n");
226 }
171 227
172 for (; count > 0; count--) 228 return 0;
173 __raw_writel(sys_powerdown_val[count - 1][mode],
174 sys_powerdown_reg[count - 1]);
175} 229}
230arch_initcall(exynos4_pmu_init);