diff options
Diffstat (limited to 'arch/arm/mach-exynos/include/mach/irqs.h')
-rw-r--r-- | arch/arm/mach-exynos/include/mach/irqs.h | 587 |
1 files changed, 432 insertions, 155 deletions
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h index f78070ee79f..9bee8535d9e 100644 --- a/arch/arm/mach-exynos/include/mach/irqs.h +++ b/arch/arm/mach-exynos/include/mach/irqs.h | |||
@@ -1,9 +1,8 @@ | |||
1 | /* linux/arch/arm/mach-exynos4/include/mach/irqs.h | 1 | /* |
2 | * | 2 | * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd. |
3 | * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. | ||
4 | * http://www.samsung.com | 3 | * http://www.samsung.com |
5 | * | 4 | * |
6 | * EXYNOS4 - IRQ definitions | 5 | * EXYNOS - IRQ definitions |
7 | * | 6 | * |
8 | * This program is free software; you can redistribute it and/or modify | 7 | * This program is free software; you can redistribute it and/or modify |
9 | * it under the terms of the GNU General Public License version 2 as | 8 | * it under the terms of the GNU General Public License version 2 as |
@@ -17,172 +16,450 @@ | |||
17 | 16 | ||
18 | /* PPI: Private Peripheral Interrupt */ | 17 | /* PPI: Private Peripheral Interrupt */ |
19 | 18 | ||
20 | #define IRQ_PPI(x) (x+16) | 19 | #define IRQ_PPI(x) (x + 16) |
21 | |||
22 | #define IRQ_MCT_LOCALTIMER IRQ_PPI(12) | ||
23 | 20 | ||
24 | /* SPI: Shared Peripheral Interrupt */ | 21 | /* SPI: Shared Peripheral Interrupt */ |
25 | 22 | ||
26 | #define IRQ_SPI(x) (x+32) | 23 | #define IRQ_SPI(x) (x + 32) |
27 | |||
28 | #define IRQ_EINT0 IRQ_SPI(16) | ||
29 | #define IRQ_EINT1 IRQ_SPI(17) | ||
30 | #define IRQ_EINT2 IRQ_SPI(18) | ||
31 | #define IRQ_EINT3 IRQ_SPI(19) | ||
32 | #define IRQ_EINT4 IRQ_SPI(20) | ||
33 | #define IRQ_EINT5 IRQ_SPI(21) | ||
34 | #define IRQ_EINT6 IRQ_SPI(22) | ||
35 | #define IRQ_EINT7 IRQ_SPI(23) | ||
36 | #define IRQ_EINT8 IRQ_SPI(24) | ||
37 | #define IRQ_EINT9 IRQ_SPI(25) | ||
38 | #define IRQ_EINT10 IRQ_SPI(26) | ||
39 | #define IRQ_EINT11 IRQ_SPI(27) | ||
40 | #define IRQ_EINT12 IRQ_SPI(28) | ||
41 | #define IRQ_EINT13 IRQ_SPI(29) | ||
42 | #define IRQ_EINT14 IRQ_SPI(30) | ||
43 | #define IRQ_EINT15 IRQ_SPI(31) | ||
44 | #define IRQ_EINT16_31 IRQ_SPI(32) | ||
45 | |||
46 | #define IRQ_MDMA0 IRQ_SPI(33) | ||
47 | #define IRQ_MDMA1 IRQ_SPI(34) | ||
48 | #define IRQ_PDMA0 IRQ_SPI(35) | ||
49 | #define IRQ_PDMA1 IRQ_SPI(36) | ||
50 | #define IRQ_TIMER0_VIC IRQ_SPI(37) | ||
51 | #define IRQ_TIMER1_VIC IRQ_SPI(38) | ||
52 | #define IRQ_TIMER2_VIC IRQ_SPI(39) | ||
53 | #define IRQ_TIMER3_VIC IRQ_SPI(40) | ||
54 | #define IRQ_TIMER4_VIC IRQ_SPI(41) | ||
55 | #define IRQ_MCT_L0 IRQ_SPI(42) | ||
56 | #define IRQ_WDT IRQ_SPI(43) | ||
57 | #define IRQ_RTC_ALARM IRQ_SPI(44) | ||
58 | #define IRQ_RTC_TIC IRQ_SPI(45) | ||
59 | #define IRQ_GPIO_XB IRQ_SPI(46) | ||
60 | #define IRQ_GPIO_XA IRQ_SPI(47) | ||
61 | #define IRQ_MCT_L1 IRQ_SPI(48) | ||
62 | |||
63 | #define IRQ_UART0 IRQ_SPI(52) | ||
64 | #define IRQ_UART1 IRQ_SPI(53) | ||
65 | #define IRQ_UART2 IRQ_SPI(54) | ||
66 | #define IRQ_UART3 IRQ_SPI(55) | ||
67 | #define IRQ_UART4 IRQ_SPI(56) | ||
68 | #define IRQ_MCT_G0 IRQ_SPI(57) | ||
69 | #define IRQ_IIC IRQ_SPI(58) | ||
70 | #define IRQ_IIC1 IRQ_SPI(59) | ||
71 | #define IRQ_IIC2 IRQ_SPI(60) | ||
72 | #define IRQ_IIC3 IRQ_SPI(61) | ||
73 | #define IRQ_IIC4 IRQ_SPI(62) | ||
74 | #define IRQ_IIC5 IRQ_SPI(63) | ||
75 | #define IRQ_IIC6 IRQ_SPI(64) | ||
76 | #define IRQ_IIC7 IRQ_SPI(65) | ||
77 | #define IRQ_SPI0 IRQ_SPI(66) | ||
78 | #define IRQ_SPI1 IRQ_SPI(67) | ||
79 | #define IRQ_SPI2 IRQ_SPI(68) | ||
80 | |||
81 | #define IRQ_USB_HOST IRQ_SPI(70) | ||
82 | #define IRQ_USB_HSOTG IRQ_SPI(71) | ||
83 | #define IRQ_MODEM_IF IRQ_SPI(72) | ||
84 | #define IRQ_HSMMC0 IRQ_SPI(73) | ||
85 | #define IRQ_HSMMC1 IRQ_SPI(74) | ||
86 | #define IRQ_HSMMC2 IRQ_SPI(75) | ||
87 | #define IRQ_HSMMC3 IRQ_SPI(76) | ||
88 | #define IRQ_DWMCI IRQ_SPI(77) | ||
89 | |||
90 | #define IRQ_MIPI_CSIS0 IRQ_SPI(78) | ||
91 | #define IRQ_MIPI_CSIS1 IRQ_SPI(80) | ||
92 | |||
93 | #define IRQ_ONENAND_AUDI IRQ_SPI(82) | ||
94 | #define IRQ_ROTATOR IRQ_SPI(83) | ||
95 | #define IRQ_FIMC0 IRQ_SPI(84) | ||
96 | #define IRQ_FIMC1 IRQ_SPI(85) | ||
97 | #define IRQ_FIMC2 IRQ_SPI(86) | ||
98 | #define IRQ_FIMC3 IRQ_SPI(87) | ||
99 | #define IRQ_JPEG IRQ_SPI(88) | ||
100 | #define IRQ_2D IRQ_SPI(89) | ||
101 | #define IRQ_PCIE IRQ_SPI(90) | ||
102 | |||
103 | #define IRQ_MIXER IRQ_SPI(91) | ||
104 | #define IRQ_HDMI IRQ_SPI(92) | ||
105 | #define IRQ_IIC_HDMIPHY IRQ_SPI(93) | ||
106 | #define IRQ_MFC IRQ_SPI(94) | ||
107 | #define IRQ_SDO IRQ_SPI(95) | ||
108 | |||
109 | #define IRQ_AUDIO_SS IRQ_SPI(96) | ||
110 | #define IRQ_I2S0 IRQ_SPI(97) | ||
111 | #define IRQ_I2S1 IRQ_SPI(98) | ||
112 | #define IRQ_I2S2 IRQ_SPI(99) | ||
113 | #define IRQ_AC97 IRQ_SPI(100) | ||
114 | |||
115 | #define IRQ_SPDIF IRQ_SPI(104) | ||
116 | #define IRQ_ADC0 IRQ_SPI(105) | ||
117 | #define IRQ_PEN0 IRQ_SPI(106) | ||
118 | #define IRQ_ADC1 IRQ_SPI(107) | ||
119 | #define IRQ_PEN1 IRQ_SPI(108) | ||
120 | #define IRQ_KEYPAD IRQ_SPI(109) | ||
121 | #define IRQ_PMU IRQ_SPI(110) | ||
122 | #define IRQ_GPS IRQ_SPI(111) | ||
123 | #define IRQ_INTFEEDCTRL_SSS IRQ_SPI(112) | ||
124 | #define IRQ_SLIMBUS IRQ_SPI(113) | ||
125 | |||
126 | #define IRQ_TSI IRQ_SPI(115) | ||
127 | #define IRQ_SATA IRQ_SPI(116) | ||
128 | |||
129 | #define MAX_IRQ_IN_COMBINER 8 | ||
130 | #define COMBINER_GROUP(x) ((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(128)) | ||
131 | #define COMBINER_IRQ(x, y) (COMBINER_GROUP(x) + y) | ||
132 | |||
133 | #define IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(4, 0) | ||
134 | #define IRQ_SYSMMU_SSS_0 COMBINER_IRQ(4, 1) | ||
135 | #define IRQ_SYSMMU_FIMC0_0 COMBINER_IRQ(4, 2) | ||
136 | #define IRQ_SYSMMU_FIMC1_0 COMBINER_IRQ(4, 3) | ||
137 | #define IRQ_SYSMMU_FIMC2_0 COMBINER_IRQ(4, 4) | ||
138 | #define IRQ_SYSMMU_FIMC3_0 COMBINER_IRQ(4, 5) | ||
139 | #define IRQ_SYSMMU_JPEG_0 COMBINER_IRQ(4, 6) | ||
140 | #define IRQ_SYSMMU_2D_0 COMBINER_IRQ(4, 7) | ||
141 | |||
142 | #define IRQ_SYSMMU_ROTATOR_0 COMBINER_IRQ(5, 0) | ||
143 | #define IRQ_SYSMMU_MDMA1_0 COMBINER_IRQ(5, 1) | ||
144 | #define IRQ_SYSMMU_LCD0_M0_0 COMBINER_IRQ(5, 2) | ||
145 | #define IRQ_SYSMMU_LCD1_M1_0 COMBINER_IRQ(5, 3) | ||
146 | #define IRQ_SYSMMU_TV_M0_0 COMBINER_IRQ(5, 4) | ||
147 | #define IRQ_SYSMMU_MFC_M0_0 COMBINER_IRQ(5, 5) | ||
148 | #define IRQ_SYSMMU_MFC_M1_0 COMBINER_IRQ(5, 6) | ||
149 | #define IRQ_SYSMMU_PCIE_0 COMBINER_IRQ(5, 7) | ||
150 | |||
151 | #define IRQ_FIMD0_FIFO COMBINER_IRQ(11, 0) | ||
152 | #define IRQ_FIMD0_VSYNC COMBINER_IRQ(11, 1) | ||
153 | #define IRQ_FIMD0_SYSTEM COMBINER_IRQ(11, 2) | ||
154 | |||
155 | #define MAX_COMBINER_NR 16 | ||
156 | |||
157 | #define IRQ_ADC IRQ_ADC0 | ||
158 | #define IRQ_TC IRQ_PEN0 | ||
159 | |||
160 | #define S5P_IRQ_EINT_BASE COMBINER_IRQ(MAX_COMBINER_NR, 0) | ||
161 | |||
162 | #define S5P_EINT_BASE1 (S5P_IRQ_EINT_BASE + 0) | ||
163 | #define S5P_EINT_BASE2 (S5P_IRQ_EINT_BASE + 16) | ||
164 | |||
165 | /* optional GPIO interrupts */ | ||
166 | #define S5P_GPIOINT_BASE (S5P_IRQ_EINT_BASE + 32) | ||
167 | #define IRQ_GPIO1_NR_GROUPS 16 | ||
168 | #define IRQ_GPIO2_NR_GROUPS 9 | ||
169 | #define IRQ_GPIO_END (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT) | ||
170 | |||
171 | #define IRQ_TIMER_BASE (IRQ_GPIO_END + 64) | ||
172 | 24 | ||
173 | /* Set the default NR_IRQS */ | 25 | /* COMBINER */ |
174 | #define NR_IRQS (IRQ_TIMER_BASE + IRQ_TIMER_COUNT) | 26 | |
27 | #define MAX_IRQ_IN_COMBINER 8 | ||
28 | #define COMBINER_GROUP(x) ((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(128)) | ||
29 | #define COMBINER_IRQ(x, y) (COMBINER_GROUP(x) + y) | ||
30 | |||
31 | /* For EXYNOS4 and EXYNOS5 */ | ||
32 | |||
33 | #define EXYNOS_IRQ_MCT_LOCALTIMER IRQ_PPI(12) | ||
34 | |||
35 | #define EXYNOS_IRQ_EINT16_31 IRQ_SPI(32) | ||
36 | |||
37 | /* For EXYNOS4 SoCs */ | ||
38 | |||
39 | #define EXYNOS4_IRQ_EINT0 IRQ_SPI(16) | ||
40 | #define EXYNOS4_IRQ_EINT1 IRQ_SPI(17) | ||
41 | #define EXYNOS4_IRQ_EINT2 IRQ_SPI(18) | ||
42 | #define EXYNOS4_IRQ_EINT3 IRQ_SPI(19) | ||
43 | #define EXYNOS4_IRQ_EINT4 IRQ_SPI(20) | ||
44 | #define EXYNOS4_IRQ_EINT5 IRQ_SPI(21) | ||
45 | #define EXYNOS4_IRQ_EINT6 IRQ_SPI(22) | ||
46 | #define EXYNOS4_IRQ_EINT7 IRQ_SPI(23) | ||
47 | #define EXYNOS4_IRQ_EINT8 IRQ_SPI(24) | ||
48 | #define EXYNOS4_IRQ_EINT9 IRQ_SPI(25) | ||
49 | #define EXYNOS4_IRQ_EINT10 IRQ_SPI(26) | ||
50 | #define EXYNOS4_IRQ_EINT11 IRQ_SPI(27) | ||
51 | #define EXYNOS4_IRQ_EINT12 IRQ_SPI(28) | ||
52 | #define EXYNOS4_IRQ_EINT13 IRQ_SPI(29) | ||
53 | #define EXYNOS4_IRQ_EINT14 IRQ_SPI(30) | ||
54 | #define EXYNOS4_IRQ_EINT15 IRQ_SPI(31) | ||
55 | |||
56 | #define EXYNOS4_IRQ_MDMA0 IRQ_SPI(33) | ||
57 | #define EXYNOS4_IRQ_MDMA1 IRQ_SPI(34) | ||
58 | #define EXYNOS4_IRQ_PDMA0 IRQ_SPI(35) | ||
59 | #define EXYNOS4_IRQ_PDMA1 IRQ_SPI(36) | ||
60 | #define EXYNOS4_IRQ_TIMER0_VIC IRQ_SPI(37) | ||
61 | #define EXYNOS4_IRQ_TIMER1_VIC IRQ_SPI(38) | ||
62 | #define EXYNOS4_IRQ_TIMER2_VIC IRQ_SPI(39) | ||
63 | #define EXYNOS4_IRQ_TIMER3_VIC IRQ_SPI(40) | ||
64 | #define EXYNOS4_IRQ_TIMER4_VIC IRQ_SPI(41) | ||
65 | #define EXYNOS4_IRQ_MCT_L0 IRQ_SPI(42) | ||
66 | #define EXYNOS4_IRQ_WDT IRQ_SPI(43) | ||
67 | #define EXYNOS4_IRQ_RTC_ALARM IRQ_SPI(44) | ||
68 | #define EXYNOS4_IRQ_RTC_TIC IRQ_SPI(45) | ||
69 | #define EXYNOS4_IRQ_GPIO_XB IRQ_SPI(46) | ||
70 | #define EXYNOS4_IRQ_GPIO_XA IRQ_SPI(47) | ||
71 | #define EXYNOS4_IRQ_MCT_L1 IRQ_SPI(48) | ||
175 | 72 | ||
176 | #define EXYNOS4_IRQ_UART0 IRQ_SPI(52) | 73 | #define EXYNOS4_IRQ_UART0 IRQ_SPI(52) |
177 | #define EXYNOS4_IRQ_UART1 IRQ_SPI(53) | 74 | #define EXYNOS4_IRQ_UART1 IRQ_SPI(53) |
178 | #define EXYNOS4_IRQ_UART2 IRQ_SPI(54) | 75 | #define EXYNOS4_IRQ_UART2 IRQ_SPI(54) |
179 | #define EXYNOS4_IRQ_UART3 IRQ_SPI(55) | 76 | #define EXYNOS4_IRQ_UART3 IRQ_SPI(55) |
180 | #define EXYNOS4_IRQ_UART4 IRQ_SPI(56) | 77 | #define EXYNOS4_IRQ_UART4 IRQ_SPI(56) |
78 | #define EXYNOS4_IRQ_MCT_G0 IRQ_SPI(57) | ||
79 | #define EXYNOS4_IRQ_IIC IRQ_SPI(58) | ||
80 | #define EXYNOS4_IRQ_IIC1 IRQ_SPI(59) | ||
81 | #define EXYNOS4_IRQ_IIC2 IRQ_SPI(60) | ||
82 | #define EXYNOS4_IRQ_IIC3 IRQ_SPI(61) | ||
83 | #define EXYNOS4_IRQ_IIC4 IRQ_SPI(62) | ||
84 | #define EXYNOS4_IRQ_IIC5 IRQ_SPI(63) | ||
85 | #define EXYNOS4_IRQ_IIC6 IRQ_SPI(64) | ||
86 | #define EXYNOS4_IRQ_IIC7 IRQ_SPI(65) | ||
87 | #define EXYNOS4_IRQ_SPI0 IRQ_SPI(66) | ||
88 | #define EXYNOS4_IRQ_SPI1 IRQ_SPI(67) | ||
89 | #define EXYNOS4_IRQ_SPI2 IRQ_SPI(68) | ||
90 | |||
91 | #define EXYNOS4_IRQ_USB_HOST IRQ_SPI(70) | ||
92 | #define EXYNOS4_IRQ_USB_HSOTG IRQ_SPI(71) | ||
93 | #define EXYNOS4_IRQ_MODEM_IF IRQ_SPI(72) | ||
94 | #define EXYNOS4_IRQ_HSMMC0 IRQ_SPI(73) | ||
95 | #define EXYNOS4_IRQ_HSMMC1 IRQ_SPI(74) | ||
96 | #define EXYNOS4_IRQ_HSMMC2 IRQ_SPI(75) | ||
97 | #define EXYNOS4_IRQ_HSMMC3 IRQ_SPI(76) | ||
98 | #define EXYNOS4_IRQ_DWMCI IRQ_SPI(77) | ||
99 | |||
100 | #define EXYNOS4_IRQ_MIPI_CSIS0 IRQ_SPI(78) | ||
101 | #define EXYNOS4_IRQ_MIPI_CSIS1 IRQ_SPI(80) | ||
102 | |||
103 | #define EXYNOS4_IRQ_ONENAND_AUDI IRQ_SPI(82) | ||
104 | #define EXYNOS4_IRQ_ROTATOR IRQ_SPI(83) | ||
105 | #define EXYNOS4_IRQ_FIMC0 IRQ_SPI(84) | ||
106 | #define EXYNOS4_IRQ_FIMC1 IRQ_SPI(85) | ||
107 | #define EXYNOS4_IRQ_FIMC2 IRQ_SPI(86) | ||
108 | #define EXYNOS4_IRQ_FIMC3 IRQ_SPI(87) | ||
109 | #define EXYNOS4_IRQ_JPEG IRQ_SPI(88) | ||
110 | #define EXYNOS4_IRQ_2D IRQ_SPI(89) | ||
111 | #define EXYNOS4_IRQ_PCIE IRQ_SPI(90) | ||
112 | |||
113 | #define EXYNOS4_IRQ_MIXER IRQ_SPI(91) | ||
114 | #define EXYNOS4_IRQ_HDMI IRQ_SPI(92) | ||
115 | #define EXYNOS4_IRQ_IIC_HDMIPHY IRQ_SPI(93) | ||
116 | #define EXYNOS4_IRQ_MFC IRQ_SPI(94) | ||
117 | #define EXYNOS4_IRQ_SDO IRQ_SPI(95) | ||
118 | |||
119 | #define EXYNOS4_IRQ_AUDIO_SS IRQ_SPI(96) | ||
120 | #define EXYNOS4_IRQ_I2S0 IRQ_SPI(97) | ||
121 | #define EXYNOS4_IRQ_I2S1 IRQ_SPI(98) | ||
122 | #define EXYNOS4_IRQ_I2S2 IRQ_SPI(99) | ||
123 | #define EXYNOS4_IRQ_AC97 IRQ_SPI(100) | ||
124 | |||
125 | #define EXYNOS4_IRQ_SPDIF IRQ_SPI(104) | ||
126 | #define EXYNOS4_IRQ_ADC0 IRQ_SPI(105) | ||
127 | #define EXYNOS4_IRQ_PEN0 IRQ_SPI(106) | ||
128 | #define EXYNOS4_IRQ_ADC1 IRQ_SPI(107) | ||
129 | #define EXYNOS4_IRQ_PEN1 IRQ_SPI(108) | ||
130 | #define EXYNOS4_IRQ_KEYPAD IRQ_SPI(109) | ||
131 | #define EXYNOS4_IRQ_PMU IRQ_SPI(110) | ||
132 | #define EXYNOS4_IRQ_GPS IRQ_SPI(111) | ||
133 | #define EXYNOS4_IRQ_INTFEEDCTRL_SSS IRQ_SPI(112) | ||
134 | #define EXYNOS4_IRQ_SLIMBUS IRQ_SPI(113) | ||
135 | |||
136 | #define EXYNOS4_IRQ_TSI IRQ_SPI(115) | ||
137 | #define EXYNOS4_IRQ_SATA IRQ_SPI(116) | ||
138 | |||
139 | #define EXYNOS4_IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(4, 0) | ||
140 | #define EXYNOS4_IRQ_SYSMMU_SSS_0 COMBINER_IRQ(4, 1) | ||
141 | #define EXYNOS4_IRQ_SYSMMU_FIMC0_0 COMBINER_IRQ(4, 2) | ||
142 | #define EXYNOS4_IRQ_SYSMMU_FIMC1_0 COMBINER_IRQ(4, 3) | ||
143 | #define EXYNOS4_IRQ_SYSMMU_FIMC2_0 COMBINER_IRQ(4, 4) | ||
144 | #define EXYNOS4_IRQ_SYSMMU_FIMC3_0 COMBINER_IRQ(4, 5) | ||
145 | #define EXYNOS4_IRQ_SYSMMU_JPEG_0 COMBINER_IRQ(4, 6) | ||
146 | #define EXYNOS4_IRQ_SYSMMU_2D_0 COMBINER_IRQ(4, 7) | ||
147 | |||
148 | #define EXYNOS4_IRQ_SYSMMU_ROTATOR_0 COMBINER_IRQ(5, 0) | ||
149 | #define EXYNOS4_IRQ_SYSMMU_MDMA1_0 COMBINER_IRQ(5, 1) | ||
150 | #define EXYNOS4_IRQ_SYSMMU_LCD0_M0_0 COMBINER_IRQ(5, 2) | ||
151 | #define EXYNOS4_IRQ_SYSMMU_LCD1_M1_0 COMBINER_IRQ(5, 3) | ||
152 | #define EXYNOS4_IRQ_SYSMMU_TV_M0_0 COMBINER_IRQ(5, 4) | ||
153 | #define EXYNOS4_IRQ_SYSMMU_MFC_M0_0 COMBINER_IRQ(5, 5) | ||
154 | #define EXYNOS4_IRQ_SYSMMU_MFC_M1_0 COMBINER_IRQ(5, 6) | ||
155 | #define EXYNOS4_IRQ_SYSMMU_PCIE_0 COMBINER_IRQ(5, 7) | ||
156 | |||
157 | #define EXYNOS4_IRQ_FIMD0_FIFO COMBINER_IRQ(11, 0) | ||
158 | #define EXYNOS4_IRQ_FIMD0_VSYNC COMBINER_IRQ(11, 1) | ||
159 | #define EXYNOS4_IRQ_FIMD0_SYSTEM COMBINER_IRQ(11, 2) | ||
160 | |||
161 | #define EXYNOS4_MAX_COMBINER_NR 16 | ||
162 | |||
163 | #define EXYNOS4_IRQ_GPIO1_NR_GROUPS 16 | ||
164 | #define EXYNOS4_IRQ_GPIO2_NR_GROUPS 9 | ||
165 | |||
166 | /* | ||
167 | * For Compatibility: | ||
168 | * the default is for EXYNOS4, and | ||
169 | * for exynos5, should be re-mapped at function | ||
170 | */ | ||
171 | |||
172 | #define IRQ_TIMER0_VIC EXYNOS4_IRQ_TIMER0_VIC | ||
173 | #define IRQ_TIMER1_VIC EXYNOS4_IRQ_TIMER1_VIC | ||
174 | #define IRQ_TIMER2_VIC EXYNOS4_IRQ_TIMER2_VIC | ||
175 | #define IRQ_TIMER3_VIC EXYNOS4_IRQ_TIMER3_VIC | ||
176 | #define IRQ_TIMER4_VIC EXYNOS4_IRQ_TIMER4_VIC | ||
177 | |||
178 | #define IRQ_WDT EXYNOS4_IRQ_WDT | ||
179 | #define IRQ_RTC_ALARM EXYNOS4_IRQ_RTC_ALARM | ||
180 | #define IRQ_RTC_TIC EXYNOS4_IRQ_RTC_TIC | ||
181 | #define IRQ_GPIO_XB EXYNOS4_IRQ_GPIO_XB | ||
182 | #define IRQ_GPIO_XA EXYNOS4_IRQ_GPIO_XA | ||
183 | |||
184 | #define IRQ_IIC EXYNOS4_IRQ_IIC | ||
185 | #define IRQ_IIC1 EXYNOS4_IRQ_IIC1 | ||
186 | #define IRQ_IIC3 EXYNOS4_IRQ_IIC3 | ||
187 | #define IRQ_IIC5 EXYNOS4_IRQ_IIC5 | ||
188 | #define IRQ_IIC6 EXYNOS4_IRQ_IIC6 | ||
189 | #define IRQ_IIC7 EXYNOS4_IRQ_IIC7 | ||
190 | |||
191 | #define IRQ_USB_HOST EXYNOS4_IRQ_USB_HOST | ||
192 | |||
193 | #define IRQ_HSMMC0 EXYNOS4_IRQ_HSMMC0 | ||
194 | #define IRQ_HSMMC1 EXYNOS4_IRQ_HSMMC1 | ||
195 | #define IRQ_HSMMC2 EXYNOS4_IRQ_HSMMC2 | ||
196 | #define IRQ_HSMMC3 EXYNOS4_IRQ_HSMMC3 | ||
197 | |||
198 | #define IRQ_MIPI_CSIS0 EXYNOS4_IRQ_MIPI_CSIS0 | ||
199 | |||
200 | #define IRQ_ONENAND_AUDI EXYNOS4_IRQ_ONENAND_AUDI | ||
201 | |||
202 | #define IRQ_FIMC0 EXYNOS4_IRQ_FIMC0 | ||
203 | #define IRQ_FIMC1 EXYNOS4_IRQ_FIMC1 | ||
204 | #define IRQ_FIMC2 EXYNOS4_IRQ_FIMC2 | ||
205 | #define IRQ_FIMC3 EXYNOS4_IRQ_FIMC3 | ||
206 | #define IRQ_JPEG EXYNOS4_IRQ_JPEG | ||
207 | #define IRQ_2D EXYNOS4_IRQ_2D | ||
208 | |||
209 | #define IRQ_MIXER EXYNOS4_IRQ_MIXER | ||
210 | #define IRQ_HDMI EXYNOS4_IRQ_HDMI | ||
211 | #define IRQ_IIC_HDMIPHY EXYNOS4_IRQ_IIC_HDMIPHY | ||
212 | #define IRQ_MFC EXYNOS4_IRQ_MFC | ||
213 | #define IRQ_SDO EXYNOS4_IRQ_SDO | ||
214 | |||
215 | #define IRQ_ADC EXYNOS4_IRQ_ADC0 | ||
216 | #define IRQ_TC EXYNOS4_IRQ_PEN0 | ||
217 | |||
218 | #define IRQ_KEYPAD EXYNOS4_IRQ_KEYPAD | ||
219 | #define IRQ_PMU EXYNOS4_IRQ_PMU | ||
220 | |||
221 | #define IRQ_SYSMMU_MDMA0_0 EXYNOS4_IRQ_SYSMMU_MDMA0_0 | ||
222 | #define IRQ_SYSMMU_SSS_0 EXYNOS4_IRQ_SYSMMU_SSS_0 | ||
223 | #define IRQ_SYSMMU_FIMC0_0 EXYNOS4_IRQ_SYSMMU_FIMC0_0 | ||
224 | #define IRQ_SYSMMU_FIMC1_0 EXYNOS4_IRQ_SYSMMU_FIMC1_0 | ||
225 | #define IRQ_SYSMMU_FIMC2_0 EXYNOS4_IRQ_SYSMMU_FIMC2_0 | ||
226 | #define IRQ_SYSMMU_FIMC3_0 EXYNOS4_IRQ_SYSMMU_FIMC3_0 | ||
227 | #define IRQ_SYSMMU_JPEG_0 EXYNOS4_IRQ_SYSMMU_JPEG_0 | ||
228 | #define IRQ_SYSMMU_2D_0 EXYNOS4_IRQ_SYSMMU_2D_0 | ||
181 | 229 | ||
230 | #define IRQ_SYSMMU_ROTATOR_0 EXYNOS4_IRQ_SYSMMU_ROTATOR_0 | ||
231 | #define IRQ_SYSMMU_MDMA1_0 EXYNOS4_IRQ_SYSMMU_MDMA1_0 | ||
232 | #define IRQ_SYSMMU_LCD0_M0_0 EXYNOS4_IRQ_SYSMMU_LCD0_M0_0 | ||
233 | #define IRQ_SYSMMU_LCD1_M1_0 EXYNOS4_IRQ_SYSMMU_LCD1_M1_0 | ||
234 | #define IRQ_SYSMMU_TV_M0_0 EXYNOS4_IRQ_SYSMMU_TV_M0_0 | ||
235 | #define IRQ_SYSMMU_MFC_M0_0 EXYNOS4_IRQ_SYSMMU_MFC_M0_0 | ||
236 | #define IRQ_SYSMMU_MFC_M1_0 EXYNOS4_IRQ_SYSMMU_MFC_M1_0 | ||
237 | #define IRQ_SYSMMU_PCIE_0 EXYNOS4_IRQ_SYSMMU_PCIE_0 | ||
238 | |||
239 | #define IRQ_FIMD0_FIFO EXYNOS4_IRQ_FIMD0_FIFO | ||
240 | #define IRQ_FIMD0_VSYNC EXYNOS4_IRQ_FIMD0_VSYNC | ||
241 | #define IRQ_FIMD0_SYSTEM EXYNOS4_IRQ_FIMD0_SYSTEM | ||
242 | |||
243 | #define IRQ_GPIO1_NR_GROUPS EXYNOS4_IRQ_GPIO1_NR_GROUPS | ||
244 | #define IRQ_GPIO2_NR_GROUPS EXYNOS4_IRQ_GPIO2_NR_GROUPS | ||
245 | |||
246 | /* For EXYNOS5 SoCs */ | ||
247 | |||
248 | #define EXYNOS5_IRQ_MDMA0 IRQ_SPI(33) | ||
249 | #define EXYNOS5_IRQ_PDMA0 IRQ_SPI(34) | ||
250 | #define EXYNOS5_IRQ_PDMA1 IRQ_SPI(35) | ||
251 | #define EXYNOS5_IRQ_TIMER0_VIC IRQ_SPI(36) | ||
252 | #define EXYNOS5_IRQ_TIMER1_VIC IRQ_SPI(37) | ||
253 | #define EXYNOS5_IRQ_TIMER2_VIC IRQ_SPI(38) | ||
254 | #define EXYNOS5_IRQ_TIMER3_VIC IRQ_SPI(39) | ||
255 | #define EXYNOS5_IRQ_TIMER4_VIC IRQ_SPI(40) | ||
256 | #define EXYNOS5_IRQ_RTIC IRQ_SPI(41) | ||
257 | #define EXYNOS5_IRQ_WDT IRQ_SPI(42) | ||
258 | #define EXYNOS5_IRQ_RTC_ALARM IRQ_SPI(43) | ||
259 | #define EXYNOS5_IRQ_RTC_TIC IRQ_SPI(44) | ||
260 | #define EXYNOS5_IRQ_GPIO_XB IRQ_SPI(45) | ||
261 | #define EXYNOS5_IRQ_GPIO_XA IRQ_SPI(46) | ||
262 | #define EXYNOS5_IRQ_GPIO IRQ_SPI(47) | ||
263 | #define EXYNOS5_IRQ_IEM_IEC IRQ_SPI(48) | ||
264 | #define EXYNOS5_IRQ_IEM_APC IRQ_SPI(49) | ||
265 | #define EXYNOS5_IRQ_GPIO_C2C IRQ_SPI(50) | ||
182 | #define EXYNOS5_IRQ_UART0 IRQ_SPI(51) | 266 | #define EXYNOS5_IRQ_UART0 IRQ_SPI(51) |
183 | #define EXYNOS5_IRQ_UART1 IRQ_SPI(52) | 267 | #define EXYNOS5_IRQ_UART1 IRQ_SPI(52) |
184 | #define EXYNOS5_IRQ_UART2 IRQ_SPI(53) | 268 | #define EXYNOS5_IRQ_UART2 IRQ_SPI(53) |
185 | #define EXYNOS5_IRQ_UART3 IRQ_SPI(54) | 269 | #define EXYNOS5_IRQ_UART3 IRQ_SPI(54) |
186 | #define EXYNOS5_IRQ_UART4 IRQ_SPI(55) | 270 | #define EXYNOS5_IRQ_UART4 IRQ_SPI(55) |
271 | #define EXYNOS5_IRQ_IIC IRQ_SPI(56) | ||
272 | #define EXYNOS5_IRQ_IIC1 IRQ_SPI(57) | ||
273 | #define EXYNOS5_IRQ_IIC2 IRQ_SPI(58) | ||
274 | #define EXYNOS5_IRQ_IIC3 IRQ_SPI(59) | ||
275 | #define EXYNOS5_IRQ_IIC4 IRQ_SPI(60) | ||
276 | #define EXYNOS5_IRQ_IIC5 IRQ_SPI(61) | ||
277 | #define EXYNOS5_IRQ_IIC6 IRQ_SPI(62) | ||
278 | #define EXYNOS5_IRQ_IIC7 IRQ_SPI(63) | ||
279 | #define EXYNOS5_IRQ_IIC_HDMIPHY IRQ_SPI(64) | ||
280 | #define EXYNOS5_IRQ_TMU IRQ_SPI(65) | ||
281 | #define EXYNOS5_IRQ_FIQ_0 IRQ_SPI(66) | ||
282 | #define EXYNOS5_IRQ_FIQ_1 IRQ_SPI(67) | ||
283 | #define EXYNOS5_IRQ_SPI0 IRQ_SPI(68) | ||
284 | #define EXYNOS5_IRQ_SPI1 IRQ_SPI(69) | ||
285 | #define EXYNOS5_IRQ_SPI2 IRQ_SPI(70) | ||
286 | #define EXYNOS5_IRQ_USB_HOST IRQ_SPI(71) | ||
287 | #define EXYNOS5_IRQ_USB3_DRD IRQ_SPI(72) | ||
288 | #define EXYNOS5_IRQ_MIPI_HSI IRQ_SPI(73) | ||
289 | #define EXYNOS5_IRQ_USB_HSOTG IRQ_SPI(74) | ||
290 | #define EXYNOS5_IRQ_HSMMC0 IRQ_SPI(75) | ||
291 | #define EXYNOS5_IRQ_HSMMC1 IRQ_SPI(76) | ||
292 | #define EXYNOS5_IRQ_HSMMC2 IRQ_SPI(77) | ||
293 | #define EXYNOS5_IRQ_HSMMC3 IRQ_SPI(78) | ||
294 | #define EXYNOS5_IRQ_MIPICSI0 IRQ_SPI(79) | ||
295 | #define EXYNOS5_IRQ_MIPICSI1 IRQ_SPI(80) | ||
296 | #define EXYNOS5_IRQ_EFNFCON_DMA_ABORT IRQ_SPI(81) | ||
297 | #define EXYNOS5_IRQ_MIPIDSI0 IRQ_SPI(82) | ||
298 | #define EXYNOS5_IRQ_ROTATOR IRQ_SPI(84) | ||
299 | #define EXYNOS5_IRQ_GSC0 IRQ_SPI(85) | ||
300 | #define EXYNOS5_IRQ_GSC1 IRQ_SPI(86) | ||
301 | #define EXYNOS5_IRQ_GSC2 IRQ_SPI(87) | ||
302 | #define EXYNOS5_IRQ_GSC3 IRQ_SPI(88) | ||
303 | #define EXYNOS5_IRQ_JPEG IRQ_SPI(89) | ||
304 | #define EXYNOS5_IRQ_EFNFCON_DMA IRQ_SPI(90) | ||
305 | #define EXYNOS5_IRQ_2D IRQ_SPI(91) | ||
306 | #define EXYNOS5_IRQ_SFMC0 IRQ_SPI(92) | ||
307 | #define EXYNOS5_IRQ_SFMC1 IRQ_SPI(93) | ||
308 | #define EXYNOS5_IRQ_MIXER IRQ_SPI(94) | ||
309 | #define EXYNOS5_IRQ_HDMI IRQ_SPI(95) | ||
310 | #define EXYNOS5_IRQ_MFC IRQ_SPI(96) | ||
311 | #define EXYNOS5_IRQ_AUDIO_SS IRQ_SPI(97) | ||
312 | #define EXYNOS5_IRQ_I2S0 IRQ_SPI(98) | ||
313 | #define EXYNOS5_IRQ_I2S1 IRQ_SPI(99) | ||
314 | #define EXYNOS5_IRQ_I2S2 IRQ_SPI(100) | ||
315 | #define EXYNOS5_IRQ_AC97 IRQ_SPI(101) | ||
316 | #define EXYNOS5_IRQ_PCM0 IRQ_SPI(102) | ||
317 | #define EXYNOS5_IRQ_PCM1 IRQ_SPI(103) | ||
318 | #define EXYNOS5_IRQ_PCM2 IRQ_SPI(104) | ||
319 | #define EXYNOS5_IRQ_SPDIF IRQ_SPI(105) | ||
320 | #define EXYNOS5_IRQ_ADC0 IRQ_SPI(106) | ||
321 | |||
322 | #define EXYNOS5_IRQ_SATA_PHY IRQ_SPI(108) | ||
323 | #define EXYNOS5_IRQ_SATA_PMEMREQ IRQ_SPI(109) | ||
324 | #define EXYNOS5_IRQ_CAM_C IRQ_SPI(110) | ||
325 | #define EXYNOS5_IRQ_EAGLE_PMU IRQ_SPI(111) | ||
326 | #define EXYNOS5_IRQ_INTFEEDCTRL_SSS IRQ_SPI(112) | ||
327 | #define EXYNOS5_IRQ_DP1_INTP1 IRQ_SPI(113) | ||
328 | #define EXYNOS5_IRQ_CEC IRQ_SPI(114) | ||
329 | #define EXYNOS5_IRQ_SATA IRQ_SPI(115) | ||
330 | #define EXYNOS5_IRQ_NFCON IRQ_SPI(116) | ||
331 | |||
332 | #define EXYNOS5_IRQ_MMC44 IRQ_SPI(123) | ||
333 | #define EXYNOS5_IRQ_MDMA1 IRQ_SPI(124) | ||
334 | #define EXYNOS5_IRQ_FIMC_LITE0 IRQ_SPI(125) | ||
335 | #define EXYNOS5_IRQ_FIMC_LITE1 IRQ_SPI(126) | ||
336 | #define EXYNOS5_IRQ_RP_TIMER IRQ_SPI(127) | ||
337 | |||
338 | #define EXYNOS5_IRQ_PMU COMBINER_IRQ(1, 2) | ||
339 | #define EXYNOS5_IRQ_PMU_CPU1 COMBINER_IRQ(1, 6) | ||
340 | |||
341 | #define EXYNOS5_IRQ_SYSMMU_GSC0_0 COMBINER_IRQ(2, 0) | ||
342 | #define EXYNOS5_IRQ_SYSMMU_GSC0_1 COMBINER_IRQ(2, 1) | ||
343 | #define EXYNOS5_IRQ_SYSMMU_GSC1_0 COMBINER_IRQ(2, 2) | ||
344 | #define EXYNOS5_IRQ_SYSMMU_GSC1_1 COMBINER_IRQ(2, 3) | ||
345 | #define EXYNOS5_IRQ_SYSMMU_GSC2_0 COMBINER_IRQ(2, 4) | ||
346 | #define EXYNOS5_IRQ_SYSMMU_GSC2_1 COMBINER_IRQ(2, 5) | ||
347 | #define EXYNOS5_IRQ_SYSMMU_GSC3_0 COMBINER_IRQ(2, 6) | ||
348 | #define EXYNOS5_IRQ_SYSMMU_GSC3_1 COMBINER_IRQ(2, 7) | ||
349 | |||
350 | #define EXYNOS5_IRQ_SYSMMU_FIMD1_0 COMBINER_IRQ(3, 2) | ||
351 | #define EXYNOS5_IRQ_SYSMMU_FIMD1_1 COMBINER_IRQ(3, 3) | ||
352 | #define EXYNOS5_IRQ_SYSMMU_LITE0_0 COMBINER_IRQ(3, 4) | ||
353 | #define EXYNOS5_IRQ_SYSMMU_LITE0_1 COMBINER_IRQ(3, 5) | ||
354 | #define EXYNOS5_IRQ_SYSMMU_SCALERPISP_0 COMBINER_IRQ(3, 6) | ||
355 | #define EXYNOS5_IRQ_SYSMMU_SCALERPISP_1 COMBINER_IRQ(3, 7) | ||
356 | |||
357 | #define EXYNOS5_IRQ_SYSMMU_ROTATOR_0 COMBINER_IRQ(4, 0) | ||
358 | #define EXYNOS5_IRQ_SYSMMU_ROTATOR_1 COMBINER_IRQ(4, 1) | ||
359 | #define EXYNOS5_IRQ_SYSMMU_JPEG_0 COMBINER_IRQ(4, 2) | ||
360 | #define EXYNOS5_IRQ_SYSMMU_JPEG_1 COMBINER_IRQ(4, 3) | ||
361 | |||
362 | #define EXYNOS5_IRQ_SYSMMU_FD_0 COMBINER_IRQ(5, 0) | ||
363 | #define EXYNOS5_IRQ_SYSMMU_FD_1 COMBINER_IRQ(5, 1) | ||
364 | #define EXYNOS5_IRQ_SYSMMU_SCALERCISP_0 COMBINER_IRQ(5, 2) | ||
365 | #define EXYNOS5_IRQ_SYSMMU_SCALERCISP_1 COMBINER_IRQ(5, 3) | ||
366 | #define EXYNOS5_IRQ_SYSMMU_MCUISP_0 COMBINER_IRQ(5, 4) | ||
367 | #define EXYNOS5_IRQ_SYSMMU_MCUISP_1 COMBINER_IRQ(5, 5) | ||
368 | #define EXYNOS5_IRQ_SYSMMU_3DNR_0 COMBINER_IRQ(5, 6) | ||
369 | #define EXYNOS5_IRQ_SYSMMU_3DNR_1 COMBINER_IRQ(5, 7) | ||
370 | |||
371 | #define EXYNOS5_IRQ_SYSMMU_ARM_0 COMBINER_IRQ(6, 0) | ||
372 | #define EXYNOS5_IRQ_SYSMMU_ARM_1 COMBINER_IRQ(6, 1) | ||
373 | #define EXYNOS5_IRQ_SYSMMU_MFC_L_0 COMBINER_IRQ(6, 2) | ||
374 | #define EXYNOS5_IRQ_SYSMMU_MFC_L_1 COMBINER_IRQ(6, 3) | ||
375 | #define EXYNOS5_IRQ_SYSMMU_RTIC_0 COMBINER_IRQ(6, 4) | ||
376 | #define EXYNOS5_IRQ_SYSMMU_RTIC_1 COMBINER_IRQ(6, 5) | ||
377 | #define EXYNOS5_IRQ_SYSMMU_SSS_0 COMBINER_IRQ(6, 6) | ||
378 | #define EXYNOS5_IRQ_SYSMMU_SSS_1 COMBINER_IRQ(6, 7) | ||
379 | |||
380 | #define EXYNOS5_IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(7, 0) | ||
381 | #define EXYNOS5_IRQ_SYSMMU_MDMA0_1 COMBINER_IRQ(7, 1) | ||
382 | #define EXYNOS5_IRQ_SYSMMU_MDMA1_0 COMBINER_IRQ(7, 2) | ||
383 | #define EXYNOS5_IRQ_SYSMMU_MDMA1_1 COMBINER_IRQ(7, 3) | ||
384 | #define EXYNOS5_IRQ_SYSMMU_TV_0 COMBINER_IRQ(7, 4) | ||
385 | #define EXYNOS5_IRQ_SYSMMU_TV_1 COMBINER_IRQ(7, 5) | ||
386 | #define EXYNOS5_IRQ_SYSMMU_GPSX_0 COMBINER_IRQ(7, 6) | ||
387 | #define EXYNOS5_IRQ_SYSMMU_GPSX_1 COMBINER_IRQ(7, 7) | ||
388 | |||
389 | #define EXYNOS5_IRQ_SYSMMU_MFC_R_0 COMBINER_IRQ(8, 5) | ||
390 | #define EXYNOS5_IRQ_SYSMMU_MFC_R_1 COMBINER_IRQ(8, 6) | ||
391 | |||
392 | #define EXYNOS5_IRQ_SYSMMU_DIS1_0 COMBINER_IRQ(9, 4) | ||
393 | #define EXYNOS5_IRQ_SYSMMU_DIS1_1 COMBINER_IRQ(9, 5) | ||
394 | |||
395 | #define EXYNOS5_IRQ_DP COMBINER_IRQ(10, 3) | ||
396 | #define EXYNOS5_IRQ_SYSMMU_DIS0_0 COMBINER_IRQ(10, 4) | ||
397 | #define EXYNOS5_IRQ_SYSMMU_DIS0_1 COMBINER_IRQ(10, 5) | ||
398 | #define EXYNOS5_IRQ_SYSMMU_ISP_0 COMBINER_IRQ(10, 6) | ||
399 | #define EXYNOS5_IRQ_SYSMMU_ISP_1 COMBINER_IRQ(10, 7) | ||
400 | |||
401 | #define EXYNOS5_IRQ_SYSMMU_ODC_0 COMBINER_IRQ(11, 0) | ||
402 | #define EXYNOS5_IRQ_SYSMMU_ODC_1 COMBINER_IRQ(11, 1) | ||
403 | #define EXYNOS5_IRQ_SYSMMU_DRC_0 COMBINER_IRQ(11, 6) | ||
404 | #define EXYNOS5_IRQ_SYSMMU_DRC_1 COMBINER_IRQ(11, 7) | ||
405 | |||
406 | #define EXYNOS5_IRQ_FIMD1_FIFO COMBINER_IRQ(18, 4) | ||
407 | #define EXYNOS5_IRQ_FIMD1_VSYNC COMBINER_IRQ(18, 5) | ||
408 | #define EXYNOS5_IRQ_FIMD1_SYSTEM COMBINER_IRQ(18, 6) | ||
409 | |||
410 | #define EXYNOS5_IRQ_EINT0 COMBINER_IRQ(23, 0) | ||
411 | #define EXYNOS5_IRQ_MCT_L0 COMBINER_IRQ(23, 1) | ||
412 | #define EXYNOS5_IRQ_MCT_L1 COMBINER_IRQ(23, 2) | ||
413 | #define EXYNOS5_IRQ_MCT_G0 COMBINER_IRQ(23, 3) | ||
414 | #define EXYNOS5_IRQ_MCT_G1 COMBINER_IRQ(23, 4) | ||
415 | #define EXYNOS5_IRQ_MCT_G2 COMBINER_IRQ(23, 5) | ||
416 | #define EXYNOS5_IRQ_MCT_G3 COMBINER_IRQ(23, 6) | ||
417 | |||
418 | #define EXYNOS5_IRQ_EINT1 COMBINER_IRQ(24, 0) | ||
419 | #define EXYNOS5_IRQ_SYSMMU_LITE1_0 COMBINER_IRQ(24, 1) | ||
420 | #define EXYNOS5_IRQ_SYSMMU_LITE1_1 COMBINER_IRQ(24, 2) | ||
421 | #define EXYNOS5_IRQ_SYSMMU_2D_0 COMBINER_IRQ(24, 5) | ||
422 | #define EXYNOS5_IRQ_SYSMMU_2D_1 COMBINER_IRQ(24, 6) | ||
423 | |||
424 | #define EXYNOS5_IRQ_EINT2 COMBINER_IRQ(25, 0) | ||
425 | #define EXYNOS5_IRQ_EINT3 COMBINER_IRQ(25, 1) | ||
426 | |||
427 | #define EXYNOS5_IRQ_EINT4 COMBINER_IRQ(26, 0) | ||
428 | #define EXYNOS5_IRQ_EINT5 COMBINER_IRQ(26, 1) | ||
429 | |||
430 | #define EXYNOS5_IRQ_EINT6 COMBINER_IRQ(27, 0) | ||
431 | #define EXYNOS5_IRQ_EINT7 COMBINER_IRQ(27, 1) | ||
432 | |||
433 | #define EXYNOS5_IRQ_EINT8 COMBINER_IRQ(28, 0) | ||
434 | #define EXYNOS5_IRQ_EINT9 COMBINER_IRQ(28, 1) | ||
435 | |||
436 | #define EXYNOS5_IRQ_EINT10 COMBINER_IRQ(29, 0) | ||
437 | #define EXYNOS5_IRQ_EINT11 COMBINER_IRQ(29, 1) | ||
438 | |||
439 | #define EXYNOS5_IRQ_EINT12 COMBINER_IRQ(30, 0) | ||
440 | #define EXYNOS5_IRQ_EINT13 COMBINER_IRQ(30, 1) | ||
441 | |||
442 | #define EXYNOS5_IRQ_EINT14 COMBINER_IRQ(31, 0) | ||
443 | #define EXYNOS5_IRQ_EINT15 COMBINER_IRQ(31, 1) | ||
444 | |||
445 | #define EXYNOS5_MAX_COMBINER_NR 32 | ||
446 | |||
447 | #define EXYNOS5_IRQ_GPIO1_NR_GROUPS 13 | ||
448 | #define EXYNOS5_IRQ_GPIO2_NR_GROUPS 9 | ||
449 | #define EXYNOS5_IRQ_GPIO3_NR_GROUPS 5 | ||
450 | #define EXYNOS5_IRQ_GPIO4_NR_GROUPS 1 | ||
451 | |||
452 | #define MAX_COMBINER_NR (EXYNOS4_MAX_COMBINER_NR > EXYNOS5_MAX_COMBINER_NR ? \ | ||
453 | EXYNOS4_MAX_COMBINER_NR : EXYNOS5_MAX_COMBINER_NR) | ||
454 | |||
455 | #define S5P_EINT_BASE1 COMBINER_IRQ(MAX_COMBINER_NR, 0) | ||
456 | #define S5P_EINT_BASE2 (S5P_EINT_BASE1 + 16) | ||
457 | #define S5P_GPIOINT_BASE (S5P_EINT_BASE1 + 32) | ||
458 | #define IRQ_GPIO_END (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT) | ||
459 | #define IRQ_TIMER_BASE (IRQ_GPIO_END + 64) | ||
460 | |||
461 | /* Set the default NR_IRQS */ | ||
462 | |||
463 | #define NR_IRQS (IRQ_TIMER_BASE + IRQ_TIMER_COUNT) | ||
187 | 464 | ||
188 | #endif /* __ASM_ARCH_IRQS_H */ | 465 | #endif /* __ASM_ARCH_IRQS_H */ |