diff options
Diffstat (limited to 'arch/arm/mach-exynos/common.c')
-rw-r--r-- | arch/arm/mach-exynos/common.c | 60 |
1 files changed, 47 insertions, 13 deletions
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index cbbaca54966..66742e91464 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c | |||
@@ -26,10 +26,12 @@ | |||
26 | #include <asm/hardware/gic.h> | 26 | #include <asm/hardware/gic.h> |
27 | #include <asm/mach/map.h> | 27 | #include <asm/mach/map.h> |
28 | #include <asm/mach/irq.h> | 28 | #include <asm/mach/irq.h> |
29 | #include <asm/cacheflush.h> | ||
29 | 30 | ||
30 | #include <mach/regs-irq.h> | 31 | #include <mach/regs-irq.h> |
31 | #include <mach/regs-pmu.h> | 32 | #include <mach/regs-pmu.h> |
32 | #include <mach/regs-gpio.h> | 33 | #include <mach/regs-gpio.h> |
34 | #include <mach/pmu.h> | ||
33 | 35 | ||
34 | #include <plat/cpu.h> | 36 | #include <plat/cpu.h> |
35 | #include <plat/clock.h> | 37 | #include <plat/clock.h> |
@@ -45,6 +47,8 @@ | |||
45 | #include <plat/regs-serial.h> | 47 | #include <plat/regs-serial.h> |
46 | 48 | ||
47 | #include "common.h" | 49 | #include "common.h" |
50 | #define L2_AUX_VAL 0x7C470001 | ||
51 | #define L2_AUX_MASK 0xC200ffff | ||
48 | 52 | ||
49 | static const char name_exynos4210[] = "EXYNOS4210"; | 53 | static const char name_exynos4210[] = "EXYNOS4210"; |
50 | static const char name_exynos4212[] = "EXYNOS4212"; | 54 | static const char name_exynos4212[] = "EXYNOS4212"; |
@@ -189,7 +193,12 @@ static struct map_desc exynos4_iodesc[] __initdata = { | |||
189 | }, { | 193 | }, { |
190 | .virtual = (unsigned long)S5P_VA_DMC0, | 194 | .virtual = (unsigned long)S5P_VA_DMC0, |
191 | .pfn = __phys_to_pfn(EXYNOS4_PA_DMC0), | 195 | .pfn = __phys_to_pfn(EXYNOS4_PA_DMC0), |
192 | .length = SZ_4K, | 196 | .length = SZ_64K, |
197 | .type = MT_DEVICE, | ||
198 | }, { | ||
199 | .virtual = (unsigned long)S5P_VA_DMC1, | ||
200 | .pfn = __phys_to_pfn(EXYNOS4_PA_DMC1), | ||
201 | .length = SZ_64K, | ||
193 | .type = MT_DEVICE, | 202 | .type = MT_DEVICE, |
194 | }, { | 203 | }, { |
195 | .virtual = (unsigned long)S3C_VA_USB_HSPHY, | 204 | .virtual = (unsigned long)S3C_VA_USB_HSPHY, |
@@ -592,23 +601,48 @@ static int __init exynos4_l2x0_cache_init(void) | |||
592 | if (soc_is_exynos5250()) | 601 | if (soc_is_exynos5250()) |
593 | return 0; | 602 | return 0; |
594 | 603 | ||
595 | /* TAG, Data Latency Control: 2cycle */ | 604 | int ret; |
596 | __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL); | 605 | ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK); |
606 | if (!ret) { | ||
607 | l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs); | ||
608 | clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long)); | ||
609 | return 0; | ||
610 | } | ||
611 | |||
612 | if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) { | ||
613 | l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC; | ||
614 | /* TAG, Data Latency Control: 2 cycles */ | ||
615 | l2x0_saved_regs.tag_latency = 0x110; | ||
597 | 616 | ||
598 | if (soc_is_exynos4210()) | 617 | if (soc_is_exynos4212() || soc_is_exynos4412()) |
599 | __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL); | 618 | l2x0_saved_regs.data_latency = 0x120; |
600 | else if (soc_is_exynos4212() || soc_is_exynos4412()) | 619 | else |
601 | __raw_writel(0x120, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL); | 620 | l2x0_saved_regs.data_latency = 0x110; |
621 | |||
622 | l2x0_saved_regs.prefetch_ctrl = 0x30000007; | ||
623 | l2x0_saved_regs.pwr_ctrl = | ||
624 | (L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN); | ||
602 | 625 | ||
603 | /* L2X0 Prefetch Control */ | 626 | l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs); |
604 | __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL); | ||
605 | 627 | ||
606 | /* L2X0 Power Control */ | 628 | __raw_writel(l2x0_saved_regs.tag_latency, |
607 | __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN, | 629 | S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL); |
608 | S5P_VA_L2CC + L2X0_POWER_CTRL); | 630 | __raw_writel(l2x0_saved_regs.data_latency, |
631 | S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL); | ||
609 | 632 | ||
610 | l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff); | 633 | /* L2X0 Prefetch Control */ |
634 | __raw_writel(l2x0_saved_regs.prefetch_ctrl, | ||
635 | S5P_VA_L2CC + L2X0_PREFETCH_CTRL); | ||
636 | |||
637 | /* L2X0 Power Control */ | ||
638 | __raw_writel(l2x0_saved_regs.pwr_ctrl, | ||
639 | S5P_VA_L2CC + L2X0_POWER_CTRL); | ||
640 | |||
641 | clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long)); | ||
642 | clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs)); | ||
643 | } | ||
611 | 644 | ||
645 | l2x0_init(S5P_VA_L2CC, L2_AUX_VAL, L2_AUX_MASK); | ||
612 | return 0; | 646 | return 0; |
613 | } | 647 | } |
614 | early_initcall(exynos4_l2x0_cache_init); | 648 | early_initcall(exynos4_l2x0_cache_init); |