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Diffstat (limited to 'arch/arm/mach-exynos/clock-exynos4.c')
-rw-r--r--arch/arm/mach-exynos/clock-exynos4.c24
1 files changed, 12 insertions, 12 deletions
diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c
index df54c2a9222..6efd1e5919f 100644
--- a/arch/arm/mach-exynos/clock-exynos4.c
+++ b/arch/arm/mach-exynos/clock-exynos4.c
@@ -497,25 +497,25 @@ static struct clk exynos4_init_clocks_off[] = {
497 .ctrlbit = (1 << 3), 497 .ctrlbit = (1 << 3),
498 }, { 498 }, {
499 .name = "hsmmc", 499 .name = "hsmmc",
500 .devname = "s3c-sdhci.0", 500 .devname = "exynos4-sdhci.0",
501 .parent = &exynos4_clk_aclk_133.clk, 501 .parent = &exynos4_clk_aclk_133.clk,
502 .enable = exynos4_clk_ip_fsys_ctrl, 502 .enable = exynos4_clk_ip_fsys_ctrl,
503 .ctrlbit = (1 << 5), 503 .ctrlbit = (1 << 5),
504 }, { 504 }, {
505 .name = "hsmmc", 505 .name = "hsmmc",
506 .devname = "s3c-sdhci.1", 506 .devname = "exynos4-sdhci.1",
507 .parent = &exynos4_clk_aclk_133.clk, 507 .parent = &exynos4_clk_aclk_133.clk,
508 .enable = exynos4_clk_ip_fsys_ctrl, 508 .enable = exynos4_clk_ip_fsys_ctrl,
509 .ctrlbit = (1 << 6), 509 .ctrlbit = (1 << 6),
510 }, { 510 }, {
511 .name = "hsmmc", 511 .name = "hsmmc",
512 .devname = "s3c-sdhci.2", 512 .devname = "exynos4-sdhci.2",
513 .parent = &exynos4_clk_aclk_133.clk, 513 .parent = &exynos4_clk_aclk_133.clk,
514 .enable = exynos4_clk_ip_fsys_ctrl, 514 .enable = exynos4_clk_ip_fsys_ctrl,
515 .ctrlbit = (1 << 7), 515 .ctrlbit = (1 << 7),
516 }, { 516 }, {
517 .name = "hsmmc", 517 .name = "hsmmc",
518 .devname = "s3c-sdhci.3", 518 .devname = "exynos4-sdhci.3",
519 .parent = &exynos4_clk_aclk_133.clk, 519 .parent = &exynos4_clk_aclk_133.clk,
520 .enable = exynos4_clk_ip_fsys_ctrl, 520 .enable = exynos4_clk_ip_fsys_ctrl,
521 .ctrlbit = (1 << 8), 521 .ctrlbit = (1 << 8),
@@ -1202,7 +1202,7 @@ static struct clksrc_clk exynos4_clk_sclk_uart3 = {
1202static struct clksrc_clk exynos4_clk_sclk_mmc0 = { 1202static struct clksrc_clk exynos4_clk_sclk_mmc0 = {
1203 .clk = { 1203 .clk = {
1204 .name = "sclk_mmc", 1204 .name = "sclk_mmc",
1205 .devname = "s3c-sdhci.0", 1205 .devname = "exynos4-sdhci.0",
1206 .parent = &exynos4_clk_dout_mmc0.clk, 1206 .parent = &exynos4_clk_dout_mmc0.clk,
1207 .enable = exynos4_clksrc_mask_fsys_ctrl, 1207 .enable = exynos4_clksrc_mask_fsys_ctrl,
1208 .ctrlbit = (1 << 0), 1208 .ctrlbit = (1 << 0),
@@ -1213,7 +1213,7 @@ static struct clksrc_clk exynos4_clk_sclk_mmc0 = {
1213static struct clksrc_clk exynos4_clk_sclk_mmc1 = { 1213static struct clksrc_clk exynos4_clk_sclk_mmc1 = {
1214 .clk = { 1214 .clk = {
1215 .name = "sclk_mmc", 1215 .name = "sclk_mmc",
1216 .devname = "s3c-sdhci.1", 1216 .devname = "exynos4-sdhci.1",
1217 .parent = &exynos4_clk_dout_mmc1.clk, 1217 .parent = &exynos4_clk_dout_mmc1.clk,
1218 .enable = exynos4_clksrc_mask_fsys_ctrl, 1218 .enable = exynos4_clksrc_mask_fsys_ctrl,
1219 .ctrlbit = (1 << 4), 1219 .ctrlbit = (1 << 4),
@@ -1224,7 +1224,7 @@ static struct clksrc_clk exynos4_clk_sclk_mmc1 = {
1224static struct clksrc_clk exynos4_clk_sclk_mmc2 = { 1224static struct clksrc_clk exynos4_clk_sclk_mmc2 = {
1225 .clk = { 1225 .clk = {
1226 .name = "sclk_mmc", 1226 .name = "sclk_mmc",
1227 .devname = "s3c-sdhci.2", 1227 .devname = "exynos4-sdhci.2",
1228 .parent = &exynos4_clk_dout_mmc2.clk, 1228 .parent = &exynos4_clk_dout_mmc2.clk,
1229 .enable = exynos4_clksrc_mask_fsys_ctrl, 1229 .enable = exynos4_clksrc_mask_fsys_ctrl,
1230 .ctrlbit = (1 << 8), 1230 .ctrlbit = (1 << 8),
@@ -1235,7 +1235,7 @@ static struct clksrc_clk exynos4_clk_sclk_mmc2 = {
1235static struct clksrc_clk exynos4_clk_sclk_mmc3 = { 1235static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
1236 .clk = { 1236 .clk = {
1237 .name = "sclk_mmc", 1237 .name = "sclk_mmc",
1238 .devname = "s3c-sdhci.3", 1238 .devname = "exynos4-sdhci.3",
1239 .parent = &exynos4_clk_dout_mmc3.clk, 1239 .parent = &exynos4_clk_dout_mmc3.clk,
1240 .enable = exynos4_clksrc_mask_fsys_ctrl, 1240 .enable = exynos4_clksrc_mask_fsys_ctrl,
1241 .ctrlbit = (1 << 12), 1241 .ctrlbit = (1 << 12),
@@ -1340,10 +1340,10 @@ static struct clk_lookup exynos4_clk_lookup[] = {
1340 CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos4_clk_sclk_uart1.clk), 1340 CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos4_clk_sclk_uart1.clk),
1341 CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos4_clk_sclk_uart2.clk), 1341 CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos4_clk_sclk_uart2.clk),
1342 CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos4_clk_sclk_uart3.clk), 1342 CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos4_clk_sclk_uart3.clk),
1343 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk), 1343 CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk),
1344 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk), 1344 CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk),
1345 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk), 1345 CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk),
1346 CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk), 1346 CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),
1347 CLKDEV_INIT("exynos4-fb.0", "lcd", &exynos4_clk_fimd0), 1347 CLKDEV_INIT("exynos4-fb.0", "lcd", &exynos4_clk_fimd0),
1348 CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0), 1348 CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0),
1349 CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1), 1349 CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1),