1 files changed, 169 insertions, 193 deletions
diff --git a/arch/arm/mach-dove/mpp.h b/arch/arm/mach-dove/mpp.h
index 2a43ce413b1..fbec7c52bfa 100644
--- a/arch/arm/mach-dove/mpp.h
+++ b/arch/arm/mach-dove/mpp.h
@@ -1,178 +1,150 @@
 #ifndef __ARCH_DOVE_MPP_CODED_H
 #define __ARCH_DOVE_MPP_CODED_H
-#define MPP(_num, _mode, _pmu, _grp, _au1, _nfc) (      \
+#define MPP(_num, _sel, _in, _out) ( \
-/* MPP/group number */          ((_num) & 0xff) |               \
+        /* MPP number */                ((_num) & 0xff) | \
-/* MPP select value */          (((_mode) & 0xf) << 8) |        \
+        /* MPP select value */          (((_sel) & 0xf) << 8) | \
-/* MPP PMU */                   ((!!(_pmu)) << 12) |            \
+        /* may be input signal */       ((!!(_in)) << 12) | \
-/* group flag */                ((!!(_grp)) << 13) |            \
+        /* may be output signal */      ((!!(_out)) << 13))
-/* AU1 flag */                  ((!!(_au1)) << 14) |            \
-/* NFCE flag */                 ((!!(_nfc)) << 15))
+#define MPP0_GPIO0              MPP(0, 0x0, 1, 1)
+#define MPP0_UA2_RTSn           MPP(0, 0x2, 0, 0)
-#define MPP_MAX 71
+#define MPP0_SDIO0_CD           MPP(0, 0x3, 0, 0)
+#define MPP0_LCD0_PWM           MPP(0, 0xf, 0, 0)
-#define MPP_NUM(x)    ((x) & 0xff)
-#define MPP_SEL(x)    (((x) >> 8) & 0xf)
+#define MPP1_GPIO1              MPP(1, 0x0, 1, 1)
+#define MPP1_UA2_CTSn           MPP(1, 0x2, 0, 0)
-#define MPP_PMU_MASK            MPP(0, 0x0, 1, 0, 0, 0)
+#define MPP1_SDIO0_WP           MPP(1, 0x3, 0, 0)
-#define MPP_GRP_MASK            MPP(0, 0x0, 0, 1, 0, 0)
+#define MPP1_LCD1_PWM           MPP(1, 0xf, 0, 0)
-#define MPP_AU1_MASK            MPP(0, 0x0, 0, 0, 1, 0)
-#define MPP_NFC_MASK            MPP(0, 0x0, 0, 0, 0, 1)
+#define MPP2_GPIO2              MPP(2, 0x0, 1, 1)
+#define MPP2_SATA_PRESENT       MPP(2, 0x1, 0, 0)
-#define MPP_END                 MPP(0xff, 0xf, 1, 1, 1, 1)
+#define MPP2_UA2_TXD            MPP(2, 0x2, 0, 0)
+#define MPP2_SDIO0_BUS_POWER    MPP(2, 0x3, 0, 0)
-#define MPP_PMU_DRIVE_0         0x1
+#define MPP2_UA_RTSn1           MPP(2, 0x4, 0, 0)
-#define MPP_PMU_DRIVE_1         0x2
-#define MPP_PMU_SDI             0x3
+#define MPP3_GPIO3              MPP(3, 0x0, 1, 1)
-#define MPP_PMU_CPU_PWRDWN      0x4
+#define MPP3_SATA_ACT           MPP(3, 0x1, 0, 0)
-#define MPP_PMU_STBY_PWRDWN     0x5
+#define MPP3_UA2_RXD            MPP(3, 0x2, 0, 0)
-#define MPP_PMU_CORE_PWR_GOOD   0x8
+#define MPP3_SDIO0_LED_CTRL     MPP(3, 0x3, 0, 0)
-#define MPP_PMU_BAT_FAULT       0xa
+#define MPP3_UA_CTSn1           MPP(3, 0x4, 0, 0)
-#define MPP_PMU_EXT0_WU         0xb
+#define MPP3_SPI_LCD_CS1        MPP(3, 0xf, 0, 0)
-#define MPP_PMU_EXT1_WU         0xc
-#define MPP_PMU_EXT2_WU         0xd
+#define MPP4_GPIO4              MPP(4, 0x0, 1, 1)
-#define MPP_PMU_BLINK           0xe
+#define MPP4_UA3_RTSn           MPP(4, 0x2, 0, 0)
-#define MPP_PMU(_num, _mode)    MPP((_num), MPP_PMU_##_mode, 1, 0, 0, 0)
+#define MPP4_SDIO1_CD           MPP(4, 0x3, 0, 0)
+#define MPP4_SPI_1_MISO         MPP(4, 0x4, 0, 0)
-#define MPP_PIN(_num, _mode)    MPP((_num), (_mode), 0, 0, 0, 0)
-#define MPP_GRP(_grp, _mode)    MPP((_grp), (_mode), 0, 1, 0, 0)
+#define MPP5_GPIO5              MPP(5, 0x0, 1, 1)
-#define MPP_GRP_AU1(_mode)      MPP(0, (_mode), 0, 0, 1, 0)
+#define MPP5_UA3_CTSn           MPP(5, 0x2, 0, 0)
-#define MPP_GRP_NFC(_mode)      MPP(0, (_mode), 0, 0, 0, 1)
+#define MPP5_SDIO1_WP           MPP(5, 0x3, 0, 0)
+#define MPP5_SPI_1_CS           MPP(5, 0x4, 0, 0)
-#define MPP0_GPIO0              MPP_PIN(0, 0x0)
-#define MPP0_UA2_RTSn           MPP_PIN(0, 0x2)
+#define MPP6_GPIO6              MPP(6, 0x0, 1, 1)
-#define MPP0_SDIO0_CD           MPP_PIN(0, 0x3)
+#define MPP6_UA3_TXD            MPP(6, 0x2, 0, 0)
-#define MPP0_LCD0_PWM           MPP_PIN(0, 0xf)
+#define MPP6_SDIO1_BUS_POWER    MPP(6, 0x3, 0, 0)
+#define MPP6_SPI_1_MOSI         MPP(6, 0x4, 0, 0)
-#define MPP1_GPIO1              MPP_PIN(1, 0x0)
-#define MPP1_UA2_CTSn           MPP_PIN(1, 0x2)
+#define MPP7_GPIO7              MPP(7, 0x0, 1, 1)
-#define MPP1_SDIO0_WP           MPP_PIN(1, 0x3)
+#define MPP7_UA3_RXD            MPP(7, 0x2, 0, 0)
-#define MPP1_LCD1_PWM           MPP_PIN(1, 0xf)
+#define MPP7_SDIO1_LED_CTRL     MPP(7, 0x3, 0, 0)
+#define MPP7_SPI_1_SCK          MPP(7, 0x4, 0, 0)
-#define MPP2_GPIO2              MPP_PIN(2, 0x0)
-#define MPP2_SATA_PRESENT       MPP_PIN(2, 0x1)
+#define MPP8_GPIO8              MPP(8, 0x0, 1, 1)
-#define MPP2_UA2_TXD            MPP_PIN(2, 0x2)
+#define MPP8_WD_RST_OUT         MPP(8, 0x1, 0, 0)
-#define MPP2_SDIO0_BUS_POWER    MPP_PIN(2, 0x3)
-#define MPP2_UA_RTSn1           MPP_PIN(2, 0x4)
+#define MPP9_GPIO9              MPP(9, 0x0, 1, 1)
+#define MPP9_PEX1_CLKREQn       MPP(9, 0x5, 0, 0)
-#define MPP3_GPIO3              MPP_PIN(3, 0x0)
-#define MPP3_SATA_ACT           MPP_PIN(3, 0x1)
+#define MPP10_GPIO10            MPP(10, 0x0, 1, 1)
-#define MPP3_UA2_RXD            MPP_PIN(3, 0x2)
+#define MPP10_SSP_SCLK          MPP(10, 0x5, 0, 0)
-#define MPP3_SDIO0_LED_CTRL     MPP_PIN(3, 0x3)
-#define MPP3_UA_CTSn1           MPP_PIN(3, 0x4)
+#define MPP11_GPIO11            MPP(11, 0x0, 1, 1)
-#define MPP3_SPI_LCD_CS1        MPP_PIN(3, 0xf)
+#define MPP11_SATA_PRESENT      MPP(11, 0x1, 0, 0)
+#define MPP11_SATA_ACT          MPP(11, 0x2, 0, 0)
-#define MPP4_GPIO4              MPP_PIN(4, 0x0)
+#define MPP11_SDIO0_LED_CTRL    MPP(11, 0x3, 0, 0)
-#define MPP4_UA3_RTSn           MPP_PIN(4, 0x2)
+#define MPP11_SDIO1_LED_CTRL    MPP(11, 0x4, 0, 0)
-#define MPP4_SDIO1_CD           MPP_PIN(4, 0x3)
+#define MPP11_PEX0_CLKREQn      MPP(11, 0x5, 0, 0)
-#define MPP4_SPI_1_MISO         MPP_PIN(4, 0x4)
+#define MPP12_GPIO12            MPP(12, 0x0, 1, 1)
-#define MPP5_GPIO5              MPP_PIN(5, 0x0)
+#define MPP12_SATA_ACT          MPP(12, 0x1, 0, 0)
-#define MPP5_UA3_CTSn           MPP_PIN(5, 0x2)
+#define MPP12_UA2_RTSn          MPP(12, 0x2, 0, 0)
-#define MPP5_SDIO1_WP           MPP_PIN(5, 0x3)
+#define MPP12_AD0_I2S_EXT_MCLK  MPP(12, 0x3, 0, 0)
-#define MPP5_SPI_1_CS           MPP_PIN(5, 0x4)
+#define MPP12_SDIO1_CD          MPP(12, 0x4, 0, 0)
-#define MPP6_GPIO6              MPP_PIN(6, 0x0)
+#define MPP13_GPIO13            MPP(13, 0x0, 1, 1)
-#define MPP6_UA3_TXD            MPP_PIN(6, 0x2)
+#define MPP13_UA2_CTSn          MPP(13, 0x2, 0, 0)
-#define MPP6_SDIO1_BUS_POWER    MPP_PIN(6, 0x3)
+#define MPP13_AD1_I2S_EXT_MCLK  MPP(13, 0x3, 0, 0)
-#define MPP6_SPI_1_MOSI         MPP_PIN(6, 0x4)
+#define MPP13_SDIO1WP           MPP(13, 0x4, 0, 0)
+#define MPP13_SSP_EXTCLK        MPP(13, 0x5, 0, 0)
-#define MPP7_GPIO7              MPP_PIN(7, 0x0)
-#define MPP7_UA3_RXD            MPP_PIN(7, 0x2)
+#define MPP14_GPIO14            MPP(14, 0x0, 1, 1)
-#define MPP7_SDIO1_LED_CTRL     MPP_PIN(7, 0x3)
+#define MPP14_UA2_TXD           MPP(14, 0x2, 0, 0)
-#define MPP7_SPI_1_SCK          MPP_PIN(7, 0x4)
+#define MPP14_SDIO1_BUS_POWER   MPP(14, 0x4, 0, 0)
+#define MPP14_SSP_RXD           MPP(14, 0x5, 0, 0)
-#define MPP8_GPIO8              MPP_PIN(8, 0x0)
-#define MPP8_WD_RST_OUT         MPP_PIN(8, 0x1)
+#define MPP15_GPIO15            MPP(15, 0x0, 1, 1)
+#define MPP15_UA2_RXD           MPP(15, 0x2, 0, 0)
-#define MPP9_GPIO9              MPP_PIN(9, 0x0)
+#define MPP15_SDIO1_LED_CTRL    MPP(15, 0x4, 0, 0)
-#define MPP9_PEX1_CLKREQn       MPP_PIN(9, 0x5)
+#define MPP15_SSP_SFRM          MPP(15, 0x5, 0, 0)
-#define MPP10_GPIO10            MPP_PIN(10, 0x0)
+#define MPP16_GPIO16            MPP(16, 0x0, 1, 1)
-#define MPP10_SSP_SCLK          MPP_PIN(10, 0x5)
+#define MPP16_UA3_RTSn          MPP(16, 0x2, 0, 0)
+#define MPP16_SDIO0_CD          MPP(16, 0x3, 0, 0)
-#define MPP11_GPIO11            MPP_PIN(11, 0x0)
+#define MPP16_SPI_LCD_CS1       MPP(16, 0x4, 0, 0)
-#define MPP11_SATA_PRESENT      MPP_PIN(11, 0x1)
+#define MPP16_AC97_SDATA_IN1    MPP(16, 0x5, 0, 0)
-#define MPP11_SATA_ACT          MPP_PIN(11, 0x2)
-#define MPP11_SDIO0_LED_CTRL    MPP_PIN(11, 0x3)
+#define MPP17_GPIO17            MPP(17, 0x0, 1, 1)
-#define MPP11_SDIO1_LED_CTRL    MPP_PIN(11, 0x4)
+#define MPP17_AC97_SYSCLK_OUT   MPP(17, 0x1, 0, 0)
-#define MPP11_PEX0_CLKREQn      MPP_PIN(11, 0x5)
+#define MPP17_UA3_CTSn          MPP(17, 0x2, 0, 0)
+#define MPP17_SDIO0_WP          MPP(17, 0x3, 0, 0)
-#define MPP12_GPIO12            MPP_PIN(12, 0x0)
+#define MPP17_TW_SDA2           MPP(17, 0x4, 0, 0)
-#define MPP12_SATA_ACT          MPP_PIN(12, 0x1)
+#define MPP17_AC97_SDATA_IN2    MPP(17, 0x5, 0, 0)
-#define MPP12_UA2_RTSn          MPP_PIN(12, 0x2)
-#define MPP12_AD0_I2S_EXT_MCLK  MPP_PIN(12, 0x3)
+#define MPP18_GPIO18            MPP(18, 0x0, 1, 1)
-#define MPP12_SDIO1_CD          MPP_PIN(12, 0x4)
+#define MPP18_UA3_TXD           MPP(18, 0x2, 0, 0)
+#define MPP18_SDIO0_BUS_POWER   MPP(18, 0x3, 0, 0)
-#define MPP13_GPIO13            MPP_PIN(13, 0x0)
+#define MPP18_LCD0_PWM          MPP(18, 0x4, 0, 0)
-#define MPP13_UA2_CTSn          MPP_PIN(13, 0x2)
+#define MPP18_AC_SDATA_IN3      MPP(18, 0x5, 0, 0)
-#define MPP13_AD1_I2S_EXT_MCLK  MPP_PIN(13, 0x3)
-#define MPP13_SDIO1WP           MPP_PIN(13, 0x4)
+#define MPP19_GPIO19            MPP(19, 0x0, 1, 1)
-#define MPP13_SSP_EXTCLK        MPP_PIN(13, 0x5)
+#define MPP19_UA3_RXD           MPP(19, 0x2, 0, 0)
+#define MPP19_SDIO0_LED_CTRL    MPP(19, 0x3, 0, 0)
-#define MPP14_GPIO14            MPP_PIN(14, 0x0)
+#define MPP19_TW_SCK2           MPP(19, 0x4, 0, 0)
-#define MPP14_UA2_TXD           MPP_PIN(14, 0x2)
-#define MPP14_SDIO1_BUS_POWER   MPP_PIN(14, 0x4)
+#define MPP20_GPIO20            MPP(20, 0x0, 1, 1)
-#define MPP14_SSP_RXD           MPP_PIN(14, 0x5)
+#define MPP20_AC97_SYSCLK_OUT   MPP(20, 0x1, 0, 0)
+#define MPP20_SPI_LCD_MISO      MPP(20, 0x2, 0, 0)
-#define MPP15_GPIO15            MPP_PIN(15, 0x0)
+#define MPP20_SDIO1_CD          MPP(20, 0x3, 0, 0)
-#define MPP15_UA2_RXD           MPP_PIN(15, 0x2)
+#define MPP20_SDIO0_CD          MPP(20, 0x5, 0, 0)
-#define MPP15_SDIO1_LED_CTRL    MPP_PIN(15, 0x4)
+#define MPP20_SPI_1_MISO        MPP(20, 0x6, 0, 0)
-#define MPP15_SSP_SFRM          MPP_PIN(15, 0x5)
+#define MPP21_GPIO21            MPP(21, 0x0, 1, 1)
-#define MPP16_GPIO16            MPP_PIN(16, 0x0)
+#define MPP21_UA1_RTSn          MPP(21, 0x1, 0, 0)
-#define MPP16_UA3_RTSn          MPP_PIN(16, 0x2)
+#define MPP21_SPI_LCD_CS0       MPP(21, 0x2, 0, 0)
-#define MPP16_SDIO0_CD          MPP_PIN(16, 0x3)
+#define MPP21_SDIO1_WP          MPP(21, 0x3, 0, 0)
-#define MPP16_SPI_LCD_CS1       MPP_PIN(16, 0x4)
+#define MPP21_SSP_SFRM          MPP(21, 0x4, 0, 0)
-#define MPP16_AC97_SDATA_IN1    MPP_PIN(16, 0x5)
+#define MPP21_SDIO0_WP          MPP(21, 0x5, 0, 0)
+#define MPP21_SPI_1_CS          MPP(21, 0x6, 0, 0)
-#define MPP17_GPIO17            MPP_PIN(17, 0x0)
-#define MPP17_AC97_SYSCLK_OUT   MPP_PIN(17, 0x1)
+#define MPP22_GPIO22            MPP(22, 0x0, 1, 1)
-#define MPP17_UA3_CTSn          MPP_PIN(17, 0x2)
+#define MPP22_UA1_CTSn          MPP(22, 0x1, 0, 0)
-#define MPP17_SDIO0_WP          MPP_PIN(17, 0x3)
+#define MPP22_SPI_LCD_MOSI      MPP(22, 0x2, 0, 0)
-#define MPP17_TW_SDA2           MPP_PIN(17, 0x4)
+#define MPP22_SDIO1_BUS_POWER   MPP(22, 0x3, 0, 0)
-#define MPP17_AC97_SDATA_IN2    MPP_PIN(17, 0x5)
+#define MPP22_SSP_TXD           MPP(22, 0x4, 0, 0)
+#define MPP22_SDIO0_BUS_POWER   MPP(22, 0x5, 0, 0)
-#define MPP18_GPIO18            MPP_PIN(18, 0x0)
+#define MPP22_SPI_1_MOSI        MPP(22, 0x6, 0, 0)
-#define MPP18_UA3_TXD           MPP_PIN(18, 0x2)
-#define MPP18_SDIO0_BUS_POWER   MPP_PIN(18, 0x3)
+#define MPP23_GPIO23            MPP(23, 0x0, 1, 1)
-#define MPP18_LCD0_PWM          MPP_PIN(18, 0x4)
+#define MPP23_SPI_LCD_SCK       MPP(23, 0x2, 0, 0)
-#define MPP18_AC_SDATA_IN3      MPP_PIN(18, 0x5)
+#define MPP23_SDIO1_LED_CTRL    MPP(23, 0x3, 0, 0)
+#define MPP23_SSP_SCLK          MPP(23, 0x4, 0, 0)
-#define MPP19_GPIO19            MPP_PIN(19, 0x0)
+#define MPP23_SDIO0_LED_CTRL    MPP(23, 0x5, 0, 0)
-#define MPP19_UA3_RXD           MPP_PIN(19, 0x2)
+#define MPP23_SPI_1_SCK         MPP(23, 0x6, 0, 0)
-#define MPP19_SDIO0_LED_CTRL    MPP_PIN(19, 0x3)
-#define MPP19_TW_SCK2           MPP_PIN(19, 0x4)
+#define MPP_MAX                 23
-#define MPP20_GPIO20            MPP_PIN(20, 0x0)
+#define MPP_GRP(_grp, _mode)    MPP((_grp), (_mode), 0, 0)
-#define MPP20_AC97_SYSCLK_OUT   MPP_PIN(20, 0x1)
-#define MPP20_SPI_LCD_MISO      MPP_PIN(20, 0x2)
-#define MPP20_SDIO1_CD          MPP_PIN(20, 0x3)
-#define MPP20_SDIO0_CD          MPP_PIN(20, 0x5)
-#define MPP20_SPI_1_MISO        MPP_PIN(20, 0x6)
-#define MPP21_GPIO21            MPP_PIN(21, 0x0)
-#define MPP21_UA1_RTSn          MPP_PIN(21, 0x1)
-#define MPP21_SPI_LCD_CS0       MPP_PIN(21, 0x2)
-#define MPP21_SDIO1_WP          MPP_PIN(21, 0x3)
-#define MPP21_SSP_SFRM          MPP_PIN(21, 0x4)
-#define MPP21_SDIO0_WP          MPP_PIN(21, 0x5)
-#define MPP21_SPI_1_CS          MPP_PIN(21, 0x6)
-#define MPP22_GPIO22            MPP_PIN(22, 0x0)
-#define MPP22_UA1_CTSn          MPP_PIN(22, 0x1)
-#define MPP22_SPI_LCD_MOSI      MPP_PIN(22, 0x2)
-#define MPP22_SDIO1_BUS_POWER   MPP_PIN(22, 0x3)
-#define MPP22_SSP_TXD           MPP_PIN(22, 0x4)
-#define MPP22_SDIO0_BUS_POWER   MPP_PIN(22, 0x5)
-#define MPP22_SPI_1_MOSI        MPP_PIN(22, 0x6)
-#define MPP23_GPIO23            MPP_PIN(23, 0x0)
-#define MPP23_SPI_LCD_SCK       MPP_PIN(23, 0x2)
-#define MPP23_SDIO1_LED_CTRL    MPP_PIN(23, 0x3)
-#define MPP23_SSP_SCLK          MPP_PIN(23, 0x4)
-#define MPP23_SDIO0_LED_CTRL    MPP_PIN(23, 0x5)
-#define MPP23_SPI_1_SCK         MPP_PIN(23, 0x6)
 /* for MPP groups _num is a group index */
 enum dove_mpp_grp_idx {
@@ -181,40 +153,44 @@ enum dove_mpp_grp_idx {
        MPP_46_51 = 1,
        MPP_58_61 = 5,
        MPP_62_63 = 4,
+        MPP_GRP_MAX = 5,
 };
-#define MPP24_39_GPIO           MPP_GRP(MPP_24_39, 0x1)
+#define MPP_GRP_24_39_GPIO              MPP_GRP(MPP_24_39, 0x1)
-#define MPP24_39_CAM            MPP_GRP(MPP_24_39, 0x0)
+#define MPP_GRP_24_39_CAM               MPP_GRP(MPP_24_39, 0x0)
-#define MPP40_45_GPIO           MPP_GRP(MPP_40_45, 0x1)
+#define MPP_GRP_40_45_GPIO              MPP_GRP(MPP_40_45, 0x1)
-#define MPP40_45_SD0            MPP_GRP(MPP_40_45, 0x0)
+#define MPP_GRP_40_45_SD0               MPP_GRP(MPP_40_45, 0x0)
-#define MPP46_51_GPIO           MPP_GRP(MPP_46_51, 0x1)
+#define MPP_GRP_46_51_GPIO              MPP_GRP(MPP_46_51, 0x1)
-#define MPP46_51_SD1            MPP_GRP(MPP_46_51, 0x0)
+#define MPP_GRP_46_51_SD1               MPP_GRP(MPP_46_51, 0x0)
-#define MPP58_61_GPIO           MPP_GRP(MPP_58_61, 0x1)
+#define MPP_GRP_58_61_GPIO              MPP_GRP(MPP_58_61, 0x1)
-#define MPP58_61_SPI            MPP_GRP(MPP_58_61, 0x0)
+#define MPP_GRP_58_61_SPI               MPP_GRP(MPP_58_61, 0x0)
-#define MPP62_63_GPIO           MPP_GRP(MPP_62_63, 0x1)
+#define MPP_GRP_62_63_GPIO              MPP_GRP(MPP_62_63, 0x1)
-#define MPP62_63_UA1            MPP_GRP(MPP_62_63, 0x0)
+#define MPP_GRP_62_63_UA1               MPP_GRP(MPP_62_63, 0x0)
 /* The MPP[64:71] control differs from other groups */
-#define MPP64_71_GPO            MPP_GRP_NFC(0x1)
+#define MPP_GRP_NFC_64_71_GPO           0x1
-#define MPP64_71_NFC            MPP_GRP_NFC(0x0)
+#define MPP_GRP_NFC_64_71_NFC           0x0
 /*
 * The MPP[52:57] functionality is encoded by 4 bits in different
 * registers. The _num field in this case encodes those bits in
 * correspodence with Table 135 of 88AP510 Functional specification
 */
-#define MPP52_57_AU1            MPP_GRP_AU1(0x0)
+#define MPP_GRP_AU1_52_57_AU1           0x0
-#define MPP52_57_AU1_GPIO57     MPP_GRP_AU1(0x2)
+#define MPP_GRP_AU1_52_57_AU1_GPIO57    0x2
-#define MPP52_57_GPIO           MPP_GRP_AU1(0xa)
+#define MPP_GRP_AU1_52_57_GPIO          0xa
-#define MPP52_57_TW_GPIO        MPP_GRP_AU1(0xb)
+#define MPP_GRP_AU1_52_57_TW_GPIO       0xb
-#define MPP52_57_AU1_SSP        MPP_GRP_AU1(0xc)
+#define MPP_GRP_AU1_52_57_AU1_SSP       0xc
-#define MPP52_57_SSP_GPIO       MPP_GRP_AU1(0xe)
+#define MPP_GRP_AU1_52_57_SSP_GPIO      0xe
-#define MPP52_57_SSP_TW         MPP_GRP_AU1(0xf)
+#define MPP_GRP_AU1_52_57_SSP_TW        0xf
-void dove_mpp_conf(unsigned int *mpp_list);
+void dove_mpp_conf(unsigned int *mpp_list,
+                   unsigned int *mpp_grp_list,
+                   unsigned int grp_au1_52_57,
+                   unsigned int grp_nfc_64_71);
 #endif  /* __ARCH_DOVE_MPP_CODED_H */

diff --git a/arch/arm/mach-dove/mpp.h b/arch/arm/mach-dove/mpp.h index 2a43ce413b1..fbec7c52bfa 100644 --- a/arch/arm/mach-dove/mpp.h +++ b/arch/arm/mach-dove/mpp.h
@@ -1,178 +1,150 @@
1	#ifndef __ARCH_DOVE_MPP_CODED_H	1	#ifndef __ARCH_DOVE_MPP_CODED_H
2	#define __ARCH_DOVE_MPP_CODED_H	2	#define __ARCH_DOVE_MPP_CODED_H
3		3
4	#define MPP(_num, _mode, _pmu, _grp, _au1, _nfc) ( \	4	#define MPP(_num, _sel, _in, _out) ( \
5	/* MPP/group number */ ((_num) & 0xff) \| \	5	/* MPP number */ ((_num) & 0xff) \| \
6	/* MPP select value */ (((_mode) & 0xf) << 8) \| \	6	/* MPP select value */ (((_sel) & 0xf) << 8) \| \
7	/* MPP PMU */ ((!!(_pmu)) << 12) \| \	7	/* may be input signal */ ((!!(_in)) << 12) \| \
8	/* group flag */ ((!!(_grp)) << 13) \| \	8	/* may be output signal */ ((!!(_out)) << 13))
9	/* AU1 flag */ ((!!(_au1)) << 14) \| \	9
10	/* NFCE flag */ ((!!(_nfc)) << 15))	10	#define MPP0_GPIO0 MPP(0, 0x0, 1, 1)
11		11	#define MPP0_UA2_RTSn MPP(0, 0x2, 0, 0)
12	#define MPP_MAX 71	12	#define MPP0_SDIO0_CD MPP(0, 0x3, 0, 0)
13		13	#define MPP0_LCD0_PWM MPP(0, 0xf, 0, 0)
14	#define MPP_NUM(x) ((x) & 0xff)	14
15	#define MPP_SEL(x) (((x) >> 8) & 0xf)	15	#define MPP1_GPIO1 MPP(1, 0x0, 1, 1)
16		16	#define MPP1_UA2_CTSn MPP(1, 0x2, 0, 0)
17	#define MPP_PMU_MASK MPP(0, 0x0, 1, 0, 0, 0)	17	#define MPP1_SDIO0_WP MPP(1, 0x3, 0, 0)
18	#define MPP_GRP_MASK MPP(0, 0x0, 0, 1, 0, 0)	18	#define MPP1_LCD1_PWM MPP(1, 0xf, 0, 0)
19	#define MPP_AU1_MASK MPP(0, 0x0, 0, 0, 1, 0)	19
20	#define MPP_NFC_MASK MPP(0, 0x0, 0, 0, 0, 1)	20	#define MPP2_GPIO2 MPP(2, 0x0, 1, 1)
21		21	#define MPP2_SATA_PRESENT MPP(2, 0x1, 0, 0)
22	#define MPP_END MPP(0xff, 0xf, 1, 1, 1, 1)	22	#define MPP2_UA2_TXD MPP(2, 0x2, 0, 0)
23		23	#define MPP2_SDIO0_BUS_POWER MPP(2, 0x3, 0, 0)
24	#define MPP_PMU_DRIVE_0 0x1	24	#define MPP2_UA_RTSn1 MPP(2, 0x4, 0, 0)
25	#define MPP_PMU_DRIVE_1 0x2	25
26	#define MPP_PMU_SDI 0x3	26	#define MPP3_GPIO3 MPP(3, 0x0, 1, 1)
27	#define MPP_PMU_CPU_PWRDWN 0x4	27	#define MPP3_SATA_ACT MPP(3, 0x1, 0, 0)
28	#define MPP_PMU_STBY_PWRDWN 0x5	28	#define MPP3_UA2_RXD MPP(3, 0x2, 0, 0)
29	#define MPP_PMU_CORE_PWR_GOOD 0x8	29	#define MPP3_SDIO0_LED_CTRL MPP(3, 0x3, 0, 0)
30	#define MPP_PMU_BAT_FAULT 0xa	30	#define MPP3_UA_CTSn1 MPP(3, 0x4, 0, 0)
31	#define MPP_PMU_EXT0_WU 0xb	31	#define MPP3_SPI_LCD_CS1 MPP(3, 0xf, 0, 0)
32	#define MPP_PMU_EXT1_WU 0xc	32
33	#define MPP_PMU_EXT2_WU 0xd	33	#define MPP4_GPIO4 MPP(4, 0x0, 1, 1)
34	#define MPP_PMU_BLINK 0xe	34	#define MPP4_UA3_RTSn MPP(4, 0x2, 0, 0)
35	#define MPP_PMU(_num, _mode) MPP((_num), MPP_PMU_##_mode, 1, 0, 0, 0)	35	#define MPP4_SDIO1_CD MPP(4, 0x3, 0, 0)
36		36	#define MPP4_SPI_1_MISO MPP(4, 0x4, 0, 0)
37	#define MPP_PIN(_num, _mode) MPP((_num), (_mode), 0, 0, 0, 0)	37
38	#define MPP_GRP(_grp, _mode) MPP((_grp), (_mode), 0, 1, 0, 0)	38	#define MPP5_GPIO5 MPP(5, 0x0, 1, 1)
39	#define MPP_GRP_AU1(_mode) MPP(0, (_mode), 0, 0, 1, 0)	39	#define MPP5_UA3_CTSn MPP(5, 0x2, 0, 0)
40	#define MPP_GRP_NFC(_mode) MPP(0, (_mode), 0, 0, 0, 1)	40	#define MPP5_SDIO1_WP MPP(5, 0x3, 0, 0)
41		41	#define MPP5_SPI_1_CS MPP(5, 0x4, 0, 0)
42	#define MPP0_GPIO0 MPP_PIN(0, 0x0)	42
43	#define MPP0_UA2_RTSn MPP_PIN(0, 0x2)	43	#define MPP6_GPIO6 MPP(6, 0x0, 1, 1)
44	#define MPP0_SDIO0_CD MPP_PIN(0, 0x3)	44	#define MPP6_UA3_TXD MPP(6, 0x2, 0, 0)
45	#define MPP0_LCD0_PWM MPP_PIN(0, 0xf)	45	#define MPP6_SDIO1_BUS_POWER MPP(6, 0x3, 0, 0)
46		46	#define MPP6_SPI_1_MOSI MPP(6, 0x4, 0, 0)
47	#define MPP1_GPIO1 MPP_PIN(1, 0x0)	47
48	#define MPP1_UA2_CTSn MPP_PIN(1, 0x2)	48	#define MPP7_GPIO7 MPP(7, 0x0, 1, 1)
49	#define MPP1_SDIO0_WP MPP_PIN(1, 0x3)	49	#define MPP7_UA3_RXD MPP(7, 0x2, 0, 0)
50	#define MPP1_LCD1_PWM MPP_PIN(1, 0xf)	50	#define MPP7_SDIO1_LED_CTRL MPP(7, 0x3, 0, 0)
51		51	#define MPP7_SPI_1_SCK MPP(7, 0x4, 0, 0)
52	#define MPP2_GPIO2 MPP_PIN(2, 0x0)	52
53	#define MPP2_SATA_PRESENT MPP_PIN(2, 0x1)	53	#define MPP8_GPIO8 MPP(8, 0x0, 1, 1)
54	#define MPP2_UA2_TXD MPP_PIN(2, 0x2)	54	#define MPP8_WD_RST_OUT MPP(8, 0x1, 0, 0)
55	#define MPP2_SDIO0_BUS_POWER MPP_PIN(2, 0x3)	55
56	#define MPP2_UA_RTSn1 MPP_PIN(2, 0x4)	56	#define MPP9_GPIO9 MPP(9, 0x0, 1, 1)
57		57	#define MPP9_PEX1_CLKREQn MPP(9, 0x5, 0, 0)
58	#define MPP3_GPIO3 MPP_PIN(3, 0x0)	58
59	#define MPP3_SATA_ACT MPP_PIN(3, 0x1)	59	#define MPP10_GPIO10 MPP(10, 0x0, 1, 1)
60	#define MPP3_UA2_RXD MPP_PIN(3, 0x2)	60	#define MPP10_SSP_SCLK MPP(10, 0x5, 0, 0)
61	#define MPP3_SDIO0_LED_CTRL MPP_PIN(3, 0x3)	61
62	#define MPP3_UA_CTSn1 MPP_PIN(3, 0x4)	62	#define MPP11_GPIO11 MPP(11, 0x0, 1, 1)
63	#define MPP3_SPI_LCD_CS1 MPP_PIN(3, 0xf)	63	#define MPP11_SATA_PRESENT MPP(11, 0x1, 0, 0)
64		64	#define MPP11_SATA_ACT MPP(11, 0x2, 0, 0)
65	#define MPP4_GPIO4 MPP_PIN(4, 0x0)	65	#define MPP11_SDIO0_LED_CTRL MPP(11, 0x3, 0, 0)
66	#define MPP4_UA3_RTSn MPP_PIN(4, 0x2)	66	#define MPP11_SDIO1_LED_CTRL MPP(11, 0x4, 0, 0)
67	#define MPP4_SDIO1_CD MPP_PIN(4, 0x3)	67	#define MPP11_PEX0_CLKREQn MPP(11, 0x5, 0, 0)
68	#define MPP4_SPI_1_MISO MPP_PIN(4, 0x4)	68
69		69	#define MPP12_GPIO12 MPP(12, 0x0, 1, 1)
70	#define MPP5_GPIO5 MPP_PIN(5, 0x0)	70	#define MPP12_SATA_ACT MPP(12, 0x1, 0, 0)
71	#define MPP5_UA3_CTSn MPP_PIN(5, 0x2)	71	#define MPP12_UA2_RTSn MPP(12, 0x2, 0, 0)
72	#define MPP5_SDIO1_WP MPP_PIN(5, 0x3)	72	#define MPP12_AD0_I2S_EXT_MCLK MPP(12, 0x3, 0, 0)
73	#define MPP5_SPI_1_CS MPP_PIN(5, 0x4)	73	#define MPP12_SDIO1_CD MPP(12, 0x4, 0, 0)
74		74
75	#define MPP6_GPIO6 MPP_PIN(6, 0x0)	75	#define MPP13_GPIO13 MPP(13, 0x0, 1, 1)
76	#define MPP6_UA3_TXD MPP_PIN(6, 0x2)	76	#define MPP13_UA2_CTSn MPP(13, 0x2, 0, 0)
77	#define MPP6_SDIO1_BUS_POWER MPP_PIN(6, 0x3)	77	#define MPP13_AD1_I2S_EXT_MCLK MPP(13, 0x3, 0, 0)
78	#define MPP6_SPI_1_MOSI MPP_PIN(6, 0x4)	78	#define MPP13_SDIO1WP MPP(13, 0x4, 0, 0)
79		79	#define MPP13_SSP_EXTCLK MPP(13, 0x5, 0, 0)
80	#define MPP7_GPIO7 MPP_PIN(7, 0x0)	80
81	#define MPP7_UA3_RXD MPP_PIN(7, 0x2)	81	#define MPP14_GPIO14 MPP(14, 0x0, 1, 1)
82	#define MPP7_SDIO1_LED_CTRL MPP_PIN(7, 0x3)	82	#define MPP14_UA2_TXD MPP(14, 0x2, 0, 0)
83	#define MPP7_SPI_1_SCK MPP_PIN(7, 0x4)	83	#define MPP14_SDIO1_BUS_POWER MPP(14, 0x4, 0, 0)
84		84	#define MPP14_SSP_RXD MPP(14, 0x5, 0, 0)
85	#define MPP8_GPIO8 MPP_PIN(8, 0x0)	85
86	#define MPP8_WD_RST_OUT MPP_PIN(8, 0x1)	86	#define MPP15_GPIO15 MPP(15, 0x0, 1, 1)
87		87	#define MPP15_UA2_RXD MPP(15, 0x2, 0, 0)
88	#define MPP9_GPIO9 MPP_PIN(9, 0x0)	88	#define MPP15_SDIO1_LED_CTRL MPP(15, 0x4, 0, 0)
89	#define MPP9_PEX1_CLKREQn MPP_PIN(9, 0x5)	89	#define MPP15_SSP_SFRM MPP(15, 0x5, 0, 0)
90		90
91	#define MPP10_GPIO10 MPP_PIN(10, 0x0)	91	#define MPP16_GPIO16 MPP(16, 0x0, 1, 1)
92	#define MPP10_SSP_SCLK MPP_PIN(10, 0x5)	92	#define MPP16_UA3_RTSn MPP(16, 0x2, 0, 0)
93		93	#define MPP16_SDIO0_CD MPP(16, 0x3, 0, 0)
94	#define MPP11_GPIO11 MPP_PIN(11, 0x0)	94	#define MPP16_SPI_LCD_CS1 MPP(16, 0x4, 0, 0)
95	#define MPP11_SATA_PRESENT MPP_PIN(11, 0x1)	95	#define MPP16_AC97_SDATA_IN1 MPP(16, 0x5, 0, 0)
96	#define MPP11_SATA_ACT MPP_PIN(11, 0x2)	96
97	#define MPP11_SDIO0_LED_CTRL MPP_PIN(11, 0x3)	97	#define MPP17_GPIO17 MPP(17, 0x0, 1, 1)
98	#define MPP11_SDIO1_LED_CTRL MPP_PIN(11, 0x4)	98	#define MPP17_AC97_SYSCLK_OUT MPP(17, 0x1, 0, 0)
99	#define MPP11_PEX0_CLKREQn MPP_PIN(11, 0x5)	99	#define MPP17_UA3_CTSn MPP(17, 0x2, 0, 0)
100		100	#define MPP17_SDIO0_WP MPP(17, 0x3, 0, 0)
101	#define MPP12_GPIO12 MPP_PIN(12, 0x0)	101	#define MPP17_TW_SDA2 MPP(17, 0x4, 0, 0)
102	#define MPP12_SATA_ACT MPP_PIN(12, 0x1)	102	#define MPP17_AC97_SDATA_IN2 MPP(17, 0x5, 0, 0)
103	#define MPP12_UA2_RTSn MPP_PIN(12, 0x2)	103
104	#define MPP12_AD0_I2S_EXT_MCLK MPP_PIN(12, 0x3)	104	#define MPP18_GPIO18 MPP(18, 0x0, 1, 1)
105	#define MPP12_SDIO1_CD MPP_PIN(12, 0x4)	105	#define MPP18_UA3_TXD MPP(18, 0x2, 0, 0)
106		106	#define MPP18_SDIO0_BUS_POWER MPP(18, 0x3, 0, 0)
107	#define MPP13_GPIO13 MPP_PIN(13, 0x0)	107	#define MPP18_LCD0_PWM MPP(18, 0x4, 0, 0)
108	#define MPP13_UA2_CTSn MPP_PIN(13, 0x2)	108	#define MPP18_AC_SDATA_IN3 MPP(18, 0x5, 0, 0)
109	#define MPP13_AD1_I2S_EXT_MCLK MPP_PIN(13, 0x3)	109
110	#define MPP13_SDIO1WP MPP_PIN(13, 0x4)	110	#define MPP19_GPIO19 MPP(19, 0x0, 1, 1)
111	#define MPP13_SSP_EXTCLK MPP_PIN(13, 0x5)	111	#define MPP19_UA3_RXD MPP(19, 0x2, 0, 0)
112		112	#define MPP19_SDIO0_LED_CTRL MPP(19, 0x3, 0, 0)
113	#define MPP14_GPIO14 MPP_PIN(14, 0x0)	113	#define MPP19_TW_SCK2 MPP(19, 0x4, 0, 0)
114	#define MPP14_UA2_TXD MPP_PIN(14, 0x2)	114
115	#define MPP14_SDIO1_BUS_POWER MPP_PIN(14, 0x4)	115	#define MPP20_GPIO20 MPP(20, 0x0, 1, 1)
116	#define MPP14_SSP_RXD MPP_PIN(14, 0x5)	116	#define MPP20_AC97_SYSCLK_OUT MPP(20, 0x1, 0, 0)
117		117	#define MPP20_SPI_LCD_MISO MPP(20, 0x2, 0, 0)
118	#define MPP15_GPIO15 MPP_PIN(15, 0x0)	118	#define MPP20_SDIO1_CD MPP(20, 0x3, 0, 0)
119	#define MPP15_UA2_RXD MPP_PIN(15, 0x2)	119	#define MPP20_SDIO0_CD MPP(20, 0x5, 0, 0)
120	#define MPP15_SDIO1_LED_CTRL MPP_PIN(15, 0x4)	120	#define MPP20_SPI_1_MISO MPP(20, 0x6, 0, 0)
121	#define MPP15_SSP_SFRM MPP_PIN(15, 0x5)	121
122		122	#define MPP21_GPIO21 MPP(21, 0x0, 1, 1)
123	#define MPP16_GPIO16 MPP_PIN(16, 0x0)	123	#define MPP21_UA1_RTSn MPP(21, 0x1, 0, 0)
124	#define MPP16_UA3_RTSn MPP_PIN(16, 0x2)	124	#define MPP21_SPI_LCD_CS0 MPP(21, 0x2, 0, 0)
125	#define MPP16_SDIO0_CD MPP_PIN(16, 0x3)	125	#define MPP21_SDIO1_WP MPP(21, 0x3, 0, 0)
126	#define MPP16_SPI_LCD_CS1 MPP_PIN(16, 0x4)	126	#define MPP21_SSP_SFRM MPP(21, 0x4, 0, 0)
127	#define MPP16_AC97_SDATA_IN1 MPP_PIN(16, 0x5)	127	#define MPP21_SDIO0_WP MPP(21, 0x5, 0, 0)
128		128	#define MPP21_SPI_1_CS MPP(21, 0x6, 0, 0)
129	#define MPP17_GPIO17 MPP_PIN(17, 0x0)	129
130	#define MPP17_AC97_SYSCLK_OUT MPP_PIN(17, 0x1)	130	#define MPP22_GPIO22 MPP(22, 0x0, 1, 1)
131	#define MPP17_UA3_CTSn MPP_PIN(17, 0x2)	131	#define MPP22_UA1_CTSn MPP(22, 0x1, 0, 0)
132	#define MPP17_SDIO0_WP MPP_PIN(17, 0x3)	132	#define MPP22_SPI_LCD_MOSI MPP(22, 0x2, 0, 0)
133	#define MPP17_TW_SDA2 MPP_PIN(17, 0x4)	133	#define MPP22_SDIO1_BUS_POWER MPP(22, 0x3, 0, 0)
134	#define MPP17_AC97_SDATA_IN2 MPP_PIN(17, 0x5)	134	#define MPP22_SSP_TXD MPP(22, 0x4, 0, 0)
135		135	#define MPP22_SDIO0_BUS_POWER MPP(22, 0x5, 0, 0)
136	#define MPP18_GPIO18 MPP_PIN(18, 0x0)	136	#define MPP22_SPI_1_MOSI MPP(22, 0x6, 0, 0)
137	#define MPP18_UA3_TXD MPP_PIN(18, 0x2)	137
138	#define MPP18_SDIO0_BUS_POWER MPP_PIN(18, 0x3)	138	#define MPP23_GPIO23 MPP(23, 0x0, 1, 1)
139	#define MPP18_LCD0_PWM MPP_PIN(18, 0x4)	139	#define MPP23_SPI_LCD_SCK MPP(23, 0x2, 0, 0)
140	#define MPP18_AC_SDATA_IN3 MPP_PIN(18, 0x5)	140	#define MPP23_SDIO1_LED_CTRL MPP(23, 0x3, 0, 0)
141		141	#define MPP23_SSP_SCLK MPP(23, 0x4, 0, 0)
142	#define MPP19_GPIO19 MPP_PIN(19, 0x0)	142	#define MPP23_SDIO0_LED_CTRL MPP(23, 0x5, 0, 0)
143	#define MPP19_UA3_RXD MPP_PIN(19, 0x2)	143	#define MPP23_SPI_1_SCK MPP(23, 0x6, 0, 0)
144	#define MPP19_SDIO0_LED_CTRL MPP_PIN(19, 0x3)	144
145	#define MPP19_TW_SCK2 MPP_PIN(19, 0x4)	145	#define MPP_MAX 23
146		146
147	#define MPP20_GPIO20 MPP_PIN(20, 0x0)	147	#define MPP_GRP(_grp, _mode) MPP((_grp), (_mode), 0, 0)
148	#define MPP20_AC97_SYSCLK_OUT MPP_PIN(20, 0x1)
149	#define MPP20_SPI_LCD_MISO MPP_PIN(20, 0x2)
150	#define MPP20_SDIO1_CD MPP_PIN(20, 0x3)
151	#define MPP20_SDIO0_CD MPP_PIN(20, 0x5)
152	#define MPP20_SPI_1_MISO MPP_PIN(20, 0x6)
153
154	#define MPP21_GPIO21 MPP_PIN(21, 0x0)
155	#define MPP21_UA1_RTSn MPP_PIN(21, 0x1)
156	#define MPP21_SPI_LCD_CS0 MPP_PIN(21, 0x2)
157	#define MPP21_SDIO1_WP MPP_PIN(21, 0x3)
158	#define MPP21_SSP_SFRM MPP_PIN(21, 0x4)
159	#define MPP21_SDIO0_WP MPP_PIN(21, 0x5)
160	#define MPP21_SPI_1_CS MPP_PIN(21, 0x6)
161
162	#define MPP22_GPIO22 MPP_PIN(22, 0x0)
163	#define MPP22_UA1_CTSn MPP_PIN(22, 0x1)
164	#define MPP22_SPI_LCD_MOSI MPP_PIN(22, 0x2)
165	#define MPP22_SDIO1_BUS_POWER MPP_PIN(22, 0x3)
166	#define MPP22_SSP_TXD MPP_PIN(22, 0x4)
167	#define MPP22_SDIO0_BUS_POWER MPP_PIN(22, 0x5)
168	#define MPP22_SPI_1_MOSI MPP_PIN(22, 0x6)
169
170	#define MPP23_GPIO23 MPP_PIN(23, 0x0)
171	#define MPP23_SPI_LCD_SCK MPP_PIN(23, 0x2)
172	#define MPP23_SDIO1_LED_CTRL MPP_PIN(23, 0x3)
173	#define MPP23_SSP_SCLK MPP_PIN(23, 0x4)
174	#define MPP23_SDIO0_LED_CTRL MPP_PIN(23, 0x5)
175	#define MPP23_SPI_1_SCK MPP_PIN(23, 0x6)
176		148
177	/* for MPP groups _num is a group index */	149	/* for MPP groups _num is a group index */
178	enum dove_mpp_grp_idx {	150	enum dove_mpp_grp_idx {
@@ -181,40 +153,44 @@ enum dove_mpp_grp_idx {
181	MPP_46_51 = 1,	153	MPP_46_51 = 1,
182	MPP_58_61 = 5,	154	MPP_58_61 = 5,
183	MPP_62_63 = 4,	155	MPP_62_63 = 4,
		156	MPP_GRP_MAX = 5,
184	};	157	};
185		158
186	#define MPP24_39_GPIO MPP_GRP(MPP_24_39, 0x1)	159	#define MPP_GRP_24_39_GPIO MPP_GRP(MPP_24_39, 0x1)
187	#define MPP24_39_CAM MPP_GRP(MPP_24_39, 0x0)	160	#define MPP_GRP_24_39_CAM MPP_GRP(MPP_24_39, 0x0)
188		161
189	#define MPP40_45_GPIO MPP_GRP(MPP_40_45, 0x1)	162	#define MPP_GRP_40_45_GPIO MPP_GRP(MPP_40_45, 0x1)
190	#define MPP40_45_SD0 MPP_GRP(MPP_40_45, 0x0)	163	#define MPP_GRP_40_45_SD0 MPP_GRP(MPP_40_45, 0x0)
191		164
192	#define MPP46_51_GPIO MPP_GRP(MPP_46_51, 0x1)	165	#define MPP_GRP_46_51_GPIO MPP_GRP(MPP_46_51, 0x1)
193	#define MPP46_51_SD1 MPP_GRP(MPP_46_51, 0x0)	166	#define MPP_GRP_46_51_SD1 MPP_GRP(MPP_46_51, 0x0)
194		167
195	#define MPP58_61_GPIO MPP_GRP(MPP_58_61, 0x1)	168	#define MPP_GRP_58_61_GPIO MPP_GRP(MPP_58_61, 0x1)
196	#define MPP58_61_SPI MPP_GRP(MPP_58_61, 0x0)	169	#define MPP_GRP_58_61_SPI MPP_GRP(MPP_58_61, 0x0)
197		170
198	#define MPP62_63_GPIO MPP_GRP(MPP_62_63, 0x1)	171	#define MPP_GRP_62_63_GPIO MPP_GRP(MPP_62_63, 0x1)
199	#define MPP62_63_UA1 MPP_GRP(MPP_62_63, 0x0)	172	#define MPP_GRP_62_63_UA1 MPP_GRP(MPP_62_63, 0x0)
200		173
201	/* The MPP[64:71] control differs from other groups */	174	/* The MPP[64:71] control differs from other groups */
202	#define MPP64_71_GPO MPP_GRP_NFC(0x1)	175	#define MPP_GRP_NFC_64_71_GPO 0x1
203	#define MPP64_71_NFC MPP_GRP_NFC(0x0)	176	#define MPP_GRP_NFC_64_71_NFC 0x0
204		177
205	/*	178	/*
206	* The MPP[52:57] functionality is encoded by 4 bits in different	179	* The MPP[52:57] functionality is encoded by 4 bits in different
207	* registers. The _num field in this case encodes those bits in	180	* registers. The _num field in this case encodes those bits in
208	* correspodence with Table 135 of 88AP510 Functional specification	181	* correspodence with Table 135 of 88AP510 Functional specification
209	*/	182	*/
210	#define MPP52_57_AU1 MPP_GRP_AU1(0x0)	183	#define MPP_GRP_AU1_52_57_AU1 0x0
211	#define MPP52_57_AU1_GPIO57 MPP_GRP_AU1(0x2)	184	#define MPP_GRP_AU1_52_57_AU1_GPIO57 0x2
212	#define MPP52_57_GPIO MPP_GRP_AU1(0xa)	185	#define MPP_GRP_AU1_52_57_GPIO 0xa
213	#define MPP52_57_TW_GPIO MPP_GRP_AU1(0xb)	186	#define MPP_GRP_AU1_52_57_TW_GPIO 0xb
214	#define MPP52_57_AU1_SSP MPP_GRP_AU1(0xc)	187	#define MPP_GRP_AU1_52_57_AU1_SSP 0xc
215	#define MPP52_57_SSP_GPIO MPP_GRP_AU1(0xe)	188	#define MPP_GRP_AU1_52_57_SSP_GPIO 0xe
216	#define MPP52_57_SSP_TW MPP_GRP_AU1(0xf)	189	#define MPP_GRP_AU1_52_57_SSP_TW 0xf
217		190
218	void dove_mpp_conf(unsigned int *mpp_list);	191	void dove_mpp_conf(unsigned int *mpp_list,
		192	unsigned int *mpp_grp_list,
		193	unsigned int grp_au1_52_57,
		194	unsigned int grp_nfc_64_71);
219		195
220	#endif /* __ARCH_DOVE_MPP_CODED_H */	196	#endif /* __ARCH_DOVE_MPP_CODED_H */