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-rw-r--r--arch/arm/mach-davinci/Kconfig43
-rw-r--r--arch/arm/mach-davinci/Makefile13
-rw-r--r--arch/arm/mach-davinci/board-dm355-evm.c298
-rw-r--r--arch/arm/mach-davinci/board-dm355-leopard.c296
-rw-r--r--arch/arm/mach-davinci/board-dm644x-evm.c68
-rw-r--r--arch/arm/mach-davinci/board-dm646x-evm.c262
-rw-r--r--arch/arm/mach-davinci/board-sffsdr.c189
-rw-r--r--arch/arm/mach-davinci/clock.c10
-rw-r--r--arch/arm/mach-davinci/clock.h4
-rw-r--r--arch/arm/mach-davinci/common.c108
-rw-r--r--arch/arm/mach-davinci/cp_intc.c161
-rw-r--r--arch/arm/mach-davinci/devices.c211
-rw-r--r--arch/arm/mach-davinci/dm355.c730
-rw-r--r--arch/arm/mach-davinci/dm644x.c204
-rw-r--r--arch/arm/mach-davinci/dm646x.c636
-rw-r--r--arch/arm/mach-davinci/gpio.c63
-rw-r--r--arch/arm/mach-davinci/id.c116
-rw-r--r--arch/arm/mach-davinci/include/mach/board-dm6446evm.h20
-rw-r--r--arch/arm/mach-davinci/include/mach/common.h55
-rw-r--r--arch/arm/mach-davinci/include/mach/cp_intc.h57
-rw-r--r--arch/arm/mach-davinci/include/mach/cputype.h29
-rw-r--r--arch/arm/mach-davinci/include/mach/debug-macro.S31
-rw-r--r--arch/arm/mach-davinci/include/mach/dm355.h22
-rw-r--r--arch/arm/mach-davinci/include/mach/dm644x.h1
-rw-r--r--arch/arm/mach-davinci/include/mach/dm646x.h26
-rw-r--r--arch/arm/mach-davinci/include/mach/edma.h4
-rw-r--r--arch/arm/mach-davinci/include/mach/emac.h36
-rw-r--r--arch/arm/mach-davinci/include/mach/entry-macro.S25
-rw-r--r--arch/arm/mach-davinci/include/mach/gpio.h14
-rw-r--r--arch/arm/mach-davinci/include/mach/irqs.h3
-rw-r--r--arch/arm/mach-davinci/include/mach/memory.h1
-rw-r--r--arch/arm/mach-davinci/include/mach/mmc.h33
-rw-r--r--arch/arm/mach-davinci/include/mach/mux.h16
-rw-r--r--arch/arm/mach-davinci/include/mach/psc.h8
-rw-r--r--arch/arm/mach-davinci/include/mach/serial.h4
-rw-r--r--arch/arm/mach-davinci/include/mach/sram.h27
-rw-r--r--arch/arm/mach-davinci/include/mach/time.h35
-rw-r--r--arch/arm/mach-davinci/include/mach/uncompress.h19
-rw-r--r--arch/arm/mach-davinci/io.c38
-rw-r--r--arch/arm/mach-davinci/irq.c217
-rw-r--r--arch/arm/mach-davinci/mux.c24
-rw-r--r--arch/arm/mach-davinci/psc.c32
-rw-r--r--arch/arm/mach-davinci/serial.c74
-rw-r--r--arch/arm/mach-davinci/sram.c74
-rw-r--r--arch/arm/mach-davinci/time.c247
45 files changed, 3886 insertions, 698 deletions
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index a9c78bc72b8..be747f5c6cd 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -1,11 +1,26 @@
1if ARCH_DAVINCI 1if ARCH_DAVINCI
2 2
3config AINTC
4 bool
5
6config CP_INTC
7 bool
8
3menu "TI DaVinci Implementations" 9menu "TI DaVinci Implementations"
4 10
5comment "DaVinci Core Type" 11comment "DaVinci Core Type"
6 12
7config ARCH_DAVINCI_DM644x 13config ARCH_DAVINCI_DM644x
8 bool "DaVinci 644x based system" 14 bool "DaVinci 644x based system"
15 select AINTC
16
17config ARCH_DAVINCI_DM355
18 bool "DaVinci 355 based system"
19 select AINTC
20
21config ARCH_DAVINCI_DM646x
22 bool "DaVinci 646x based system"
23 select AINTC
9 24
10comment "DaVinci Board Type" 25comment "DaVinci Board Type"
11 26
@@ -17,6 +32,34 @@ config MACH_DAVINCI_EVM
17 Configure this option to specify the whether the board used 32 Configure this option to specify the whether the board used
18 for development is a DM644x EVM 33 for development is a DM644x EVM
19 34
35config MACH_SFFSDR
36 bool "Lyrtech SFFSDR"
37 depends on ARCH_DAVINCI_DM644x
38 help
39 Say Y here to select the Lyrtech Small Form Factor
40 Software Defined Radio (SFFSDR) board.
41
42config MACH_DAVINCI_DM355_EVM
43 bool "TI DM355 EVM"
44 depends on ARCH_DAVINCI_DM355
45 help
46 Configure this option to specify the whether the board used
47 for development is a DM355 EVM
48
49config MACH_DM355_LEOPARD
50 bool "DM355 Leopard board"
51 depends on ARCH_DAVINCI_DM355
52 help
53 Configure this option to specify the whether the board used
54 for development is a DM355 Leopard board.
55
56config MACH_DAVINCI_DM6467_EVM
57 bool "TI DM6467 EVM"
58 depends on ARCH_DAVINCI_DM646x
59 help
60 Configure this option to specify the whether the board used
61 for development is a DM6467 EVM
62
20 63
21config DAVINCI_MUX 64config DAVINCI_MUX
22 bool "DAVINCI multiplexing support" 65 bool "DAVINCI multiplexing support"
diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
index 1674661942f..059ab78084b 100644
--- a/arch/arm/mach-davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
@@ -4,13 +4,22 @@
4# 4#
5 5
6# Common objects 6# Common objects
7obj-y := time.o irq.o clock.o serial.o io.o id.o psc.o \ 7obj-y := time.o clock.o serial.o io.o psc.o \
8 gpio.o devices.o dma.o usb.o 8 gpio.o devices.o dma.o usb.o common.o sram.o
9 9
10obj-$(CONFIG_DAVINCI_MUX) += mux.o 10obj-$(CONFIG_DAVINCI_MUX) += mux.o
11 11
12# Chip specific 12# Chip specific
13obj-$(CONFIG_ARCH_DAVINCI_DM644x) += dm644x.o 13obj-$(CONFIG_ARCH_DAVINCI_DM644x) += dm644x.o
14obj-$(CONFIG_ARCH_DAVINCI_DM355) += dm355.o
15obj-$(CONFIG_ARCH_DAVINCI_DM646x) += dm646x.o
16
17obj-$(CONFIG_AINTC) += irq.o
18obj-$(CONFIG_CP_INTC) += cp_intc.o
14 19
15# Board specific 20# Board specific
16obj-$(CONFIG_MACH_DAVINCI_EVM) += board-dm644x-evm.o 21obj-$(CONFIG_MACH_DAVINCI_EVM) += board-dm644x-evm.o
22obj-$(CONFIG_MACH_SFFSDR) += board-sffsdr.o
23obj-$(CONFIG_MACH_DAVINCI_DM355_EVM) += board-dm355-evm.o
24obj-$(CONFIG_MACH_DM355_LEOPARD) += board-dm355-leopard.o
25obj-$(CONFIG_MACH_DAVINCI_DM6467_EVM) += board-dm646x-evm.o
diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c
new file mode 100644
index 00000000000..5ac2f565d86
--- /dev/null
+++ b/arch/arm/mach-davinci/board-dm355-evm.c
@@ -0,0 +1,298 @@
1/*
2 * TI DaVinci EVM board support
3 *
4 * Author: Kevin Hilman, Deep Root Systems, LLC
5 *
6 * 2007 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/init.h>
14#include <linux/dma-mapping.h>
15#include <linux/platform_device.h>
16#include <linux/mtd/mtd.h>
17#include <linux/mtd/partitions.h>
18#include <linux/mtd/nand.h>
19#include <linux/i2c.h>
20#include <linux/io.h>
21#include <linux/gpio.h>
22#include <linux/clk.h>
23#include <linux/spi/spi.h>
24#include <linux/spi/eeprom.h>
25
26#include <asm/setup.h>
27#include <asm/mach-types.h>
28#include <asm/mach/arch.h>
29#include <asm/mach/map.h>
30#include <asm/mach/flash.h>
31
32#include <mach/hardware.h>
33#include <mach/dm355.h>
34#include <mach/psc.h>
35#include <mach/common.h>
36#include <mach/i2c.h>
37#include <mach/serial.h>
38#include <mach/nand.h>
39#include <mach/mmc.h>
40#include <mach/common.h>
41
42#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e10000
43#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
44
45/* NOTE: this is geared for the standard config, with a socketed
46 * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you
47 * swap chips, maybe with a different block size, partitioning may
48 * need to be changed.
49 */
50#define NAND_BLOCK_SIZE SZ_128K
51
52static struct mtd_partition davinci_nand_partitions[] = {
53 {
54 /* UBL (a few copies) plus U-Boot */
55 .name = "bootloader",
56 .offset = 0,
57 .size = 15 * NAND_BLOCK_SIZE,
58 .mask_flags = MTD_WRITEABLE, /* force read-only */
59 }, {
60 /* U-Boot environment */
61 .name = "params",
62 .offset = MTDPART_OFS_APPEND,
63 .size = 1 * NAND_BLOCK_SIZE,
64 .mask_flags = 0,
65 }, {
66 .name = "kernel",
67 .offset = MTDPART_OFS_APPEND,
68 .size = SZ_4M,
69 .mask_flags = 0,
70 }, {
71 .name = "filesystem1",
72 .offset = MTDPART_OFS_APPEND,
73 .size = SZ_512M,
74 .mask_flags = 0,
75 }, {
76 .name = "filesystem2",
77 .offset = MTDPART_OFS_APPEND,
78 .size = MTDPART_SIZ_FULL,
79 .mask_flags = 0,
80 }
81 /* two blocks with bad block table (and mirror) at the end */
82};
83
84static struct davinci_nand_pdata davinci_nand_data = {
85 .mask_chipsel = BIT(14),
86 .parts = davinci_nand_partitions,
87 .nr_parts = ARRAY_SIZE(davinci_nand_partitions),
88 .ecc_mode = NAND_ECC_HW_SYNDROME,
89 .options = NAND_USE_FLASH_BBT,
90};
91
92static struct resource davinci_nand_resources[] = {
93 {
94 .start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
95 .end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
96 .flags = IORESOURCE_MEM,
97 }, {
98 .start = DAVINCI_ASYNC_EMIF_CONTROL_BASE,
99 .end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
100 .flags = IORESOURCE_MEM,
101 },
102};
103
104static struct platform_device davinci_nand_device = {
105 .name = "davinci_nand",
106 .id = 0,
107
108 .num_resources = ARRAY_SIZE(davinci_nand_resources),
109 .resource = davinci_nand_resources,
110
111 .dev = {
112 .platform_data = &davinci_nand_data,
113 },
114};
115
116static struct davinci_i2c_platform_data i2c_pdata = {
117 .bus_freq = 400 /* kHz */,
118 .bus_delay = 0 /* usec */,
119};
120
121static int dm355evm_mmc_gpios = -EINVAL;
122
123static void dm355evm_mmcsd_gpios(unsigned gpio)
124{
125 gpio_request(gpio + 0, "mmc0_ro");
126 gpio_request(gpio + 1, "mmc0_cd");
127 gpio_request(gpio + 2, "mmc1_ro");
128 gpio_request(gpio + 3, "mmc1_cd");
129
130 /* we "know" these are input-only so we don't
131 * need to call gpio_direction_input()
132 */
133
134 dm355evm_mmc_gpios = gpio;
135}
136
137static struct i2c_board_info dm355evm_i2c_info[] = {
138 { I2C_BOARD_INFO("dm355evm_msp", 0x25),
139 .platform_data = dm355evm_mmcsd_gpios,
140 /* plus irq */ },
141 /* { I2C_BOARD_INFO("tlv320aic3x", 0x1b), }, */
142 /* { I2C_BOARD_INFO("tvp5146", 0x5d), }, */
143};
144
145static void __init evm_init_i2c(void)
146{
147 davinci_init_i2c(&i2c_pdata);
148
149 gpio_request(5, "dm355evm_msp");
150 gpio_direction_input(5);
151 dm355evm_i2c_info[0].irq = gpio_to_irq(5);
152
153 i2c_register_board_info(1, dm355evm_i2c_info,
154 ARRAY_SIZE(dm355evm_i2c_info));
155}
156
157static struct resource dm355evm_dm9000_rsrc[] = {
158 {
159 /* addr */
160 .start = 0x04014000,
161 .end = 0x04014001,
162 .flags = IORESOURCE_MEM,
163 }, {
164 /* data */
165 .start = 0x04014002,
166 .end = 0x04014003,
167 .flags = IORESOURCE_MEM,
168 }, {
169 .flags = IORESOURCE_IRQ
170 | IORESOURCE_IRQ_HIGHEDGE /* rising (active high) */,
171 },
172};
173
174static struct platform_device dm355evm_dm9000 = {
175 .name = "dm9000",
176 .id = -1,
177 .resource = dm355evm_dm9000_rsrc,
178 .num_resources = ARRAY_SIZE(dm355evm_dm9000_rsrc),
179};
180
181static struct platform_device *davinci_evm_devices[] __initdata = {
182 &dm355evm_dm9000,
183 &davinci_nand_device,
184};
185
186static struct davinci_uart_config uart_config __initdata = {
187 .enabled_uarts = (1 << 0),
188};
189
190static void __init dm355_evm_map_io(void)
191{
192 dm355_init();
193}
194
195static int dm355evm_mmc_get_cd(int module)
196{
197 if (!gpio_is_valid(dm355evm_mmc_gpios))
198 return -ENXIO;
199 /* low == card present */
200 return !gpio_get_value_cansleep(dm355evm_mmc_gpios + 2 * module + 1);
201}
202
203static int dm355evm_mmc_get_ro(int module)
204{
205 if (!gpio_is_valid(dm355evm_mmc_gpios))
206 return -ENXIO;
207 /* high == card's write protect switch active */
208 return gpio_get_value_cansleep(dm355evm_mmc_gpios + 2 * module + 0);
209}
210
211static struct davinci_mmc_config dm355evm_mmc_config = {
212 .get_cd = dm355evm_mmc_get_cd,
213 .get_ro = dm355evm_mmc_get_ro,
214 .wires = 4,
215 .max_freq = 50000000,
216 .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
217 .version = MMC_CTLR_VERSION_1,
218};
219
220/* Don't connect anything to J10 unless you're only using USB host
221 * mode *and* have to do so with some kind of gender-bender. If
222 * you have proper Mini-B or Mini-A cables (or Mini-A adapters)
223 * the ID pin won't need any help.
224 */
225#ifdef CONFIG_USB_MUSB_PERIPHERAL
226#define USB_ID_VALUE 0 /* ID pulled high; *should* float */
227#else
228#define USB_ID_VALUE 1 /* ID pulled low */
229#endif
230
231static struct spi_eeprom at25640a = {
232 .byte_len = SZ_64K / 8,
233 .name = "at25640a",
234 .page_size = 32,
235 .flags = EE_ADDR2,
236};
237
238static struct spi_board_info dm355_evm_spi_info[] __initconst = {
239 {
240 .modalias = "at25",
241 .platform_data = &at25640a,
242 .max_speed_hz = 10 * 1000 * 1000, /* at 3v3 */
243 .bus_num = 0,
244 .chip_select = 0,
245 .mode = SPI_MODE_0,
246 },
247};
248
249static __init void dm355_evm_init(void)
250{
251 struct clk *aemif;
252
253 gpio_request(1, "dm9000");
254 gpio_direction_input(1);
255 dm355evm_dm9000_rsrc[2].start = gpio_to_irq(1);
256
257 aemif = clk_get(&dm355evm_dm9000.dev, "aemif");
258 if (IS_ERR(aemif))
259 WARN("%s: unable to get AEMIF clock\n", __func__);
260 else
261 clk_enable(aemif);
262
263 platform_add_devices(davinci_evm_devices,
264 ARRAY_SIZE(davinci_evm_devices));
265 evm_init_i2c();
266 davinci_serial_init(&uart_config);
267
268 /* NOTE: NAND flash timings set by the UBL are slower than
269 * needed by MT29F16G08FAA chips ... EMIF.A1CR is 0x40400204
270 * but could be 0x0400008c for about 25% faster page reads.
271 */
272
273 gpio_request(2, "usb_id_toggle");
274 gpio_direction_output(2, USB_ID_VALUE);
275 /* irlml6401 switches over 1A in under 8 msec */
276 setup_usb(500, 8);
277
278 davinci_setup_mmc(0, &dm355evm_mmc_config);
279 davinci_setup_mmc(1, &dm355evm_mmc_config);
280
281 dm355_init_spi0(BIT(0), dm355_evm_spi_info,
282 ARRAY_SIZE(dm355_evm_spi_info));
283}
284
285static __init void dm355_evm_irq_init(void)
286{
287 davinci_irq_init();
288}
289
290MACHINE_START(DAVINCI_DM355_EVM, "DaVinci DM355 EVM")
291 .phys_io = IO_PHYS,
292 .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
293 .boot_params = (0x80000100),
294 .map_io = dm355_evm_map_io,
295 .init_irq = dm355_evm_irq_init,
296 .timer = &davinci_timer,
297 .init_machine = dm355_evm_init,
298MACHINE_END
diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c
new file mode 100644
index 00000000000..28c9008df4f
--- /dev/null
+++ b/arch/arm/mach-davinci/board-dm355-leopard.c
@@ -0,0 +1,296 @@
1/*
2 * DM355 leopard board support
3 *
4 * Based on board-dm355-evm.c
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10#include <linux/kernel.h>
11#include <linux/module.h>
12#include <linux/init.h>
13#include <linux/dma-mapping.h>
14#include <linux/platform_device.h>
15#include <linux/mtd/mtd.h>
16#include <linux/mtd/partitions.h>
17#include <linux/mtd/nand.h>
18#include <linux/i2c.h>
19#include <linux/io.h>
20#include <linux/gpio.h>
21#include <linux/clk.h>
22#include <linux/spi/spi.h>
23#include <linux/spi/eeprom.h>
24
25#include <asm/setup.h>
26#include <asm/mach-types.h>
27#include <asm/mach/arch.h>
28#include <asm/mach/map.h>
29#include <asm/mach/flash.h>
30
31#include <mach/hardware.h>
32#include <mach/dm355.h>
33#include <mach/psc.h>
34#include <mach/common.h>
35#include <mach/i2c.h>
36#include <mach/serial.h>
37#include <mach/nand.h>
38#include <mach/mmc.h>
39#include <mach/common.h>
40
41#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e10000
42#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
43
44/* NOTE: this is geared for the standard config, with a socketed
45 * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you
46 * swap chips, maybe with a different block size, partitioning may
47 * need to be changed.
48 */
49#define NAND_BLOCK_SIZE SZ_128K
50
51static struct mtd_partition davinci_nand_partitions[] = {
52 {
53 /* UBL (a few copies) plus U-Boot */
54 .name = "bootloader",
55 .offset = 0,
56 .size = 15 * NAND_BLOCK_SIZE,
57 .mask_flags = MTD_WRITEABLE, /* force read-only */
58 }, {
59 /* U-Boot environment */
60 .name = "params",
61 .offset = MTDPART_OFS_APPEND,
62 .size = 1 * NAND_BLOCK_SIZE,
63 .mask_flags = 0,
64 }, {
65 .name = "kernel",
66 .offset = MTDPART_OFS_APPEND,
67 .size = SZ_4M,
68 .mask_flags = 0,
69 }, {
70 .name = "filesystem1",
71 .offset = MTDPART_OFS_APPEND,
72 .size = SZ_512M,
73 .mask_flags = 0,
74 }, {
75 .name = "filesystem2",
76 .offset = MTDPART_OFS_APPEND,
77 .size = MTDPART_SIZ_FULL,
78 .mask_flags = 0,
79 }
80 /* two blocks with bad block table (and mirror) at the end */
81};
82
83static struct davinci_nand_pdata davinci_nand_data = {
84 .mask_chipsel = BIT(14),
85 .parts = davinci_nand_partitions,
86 .nr_parts = ARRAY_SIZE(davinci_nand_partitions),
87 .ecc_mode = NAND_ECC_HW_SYNDROME,
88 .options = NAND_USE_FLASH_BBT,
89};
90
91static struct resource davinci_nand_resources[] = {
92 {
93 .start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
94 .end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
95 .flags = IORESOURCE_MEM,
96 }, {
97 .start = DAVINCI_ASYNC_EMIF_CONTROL_BASE,
98 .end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
99 .flags = IORESOURCE_MEM,
100 },
101};
102
103static struct platform_device davinci_nand_device = {
104 .name = "davinci_nand",
105 .id = 0,
106
107 .num_resources = ARRAY_SIZE(davinci_nand_resources),
108 .resource = davinci_nand_resources,
109
110 .dev = {
111 .platform_data = &davinci_nand_data,
112 },
113};
114
115static struct davinci_i2c_platform_data i2c_pdata = {
116 .bus_freq = 400 /* kHz */,
117 .bus_delay = 0 /* usec */,
118};
119
120static int leopard_mmc_gpio = -EINVAL;
121
122static void dm355leopard_mmcsd_gpios(unsigned gpio)
123{
124 gpio_request(gpio + 0, "mmc0_ro");
125 gpio_request(gpio + 1, "mmc0_cd");
126 gpio_request(gpio + 2, "mmc1_ro");
127 gpio_request(gpio + 3, "mmc1_cd");
128
129 /* we "know" these are input-only so we don't
130 * need to call gpio_direction_input()
131 */
132
133 leopard_mmc_gpio = gpio;
134}
135
136static struct i2c_board_info dm355leopard_i2c_info[] = {
137 { I2C_BOARD_INFO("dm355leopard_msp", 0x25),
138 .platform_data = dm355leopard_mmcsd_gpios,
139 /* plus irq */ },
140 /* { I2C_BOARD_INFO("tlv320aic3x", 0x1b), }, */
141 /* { I2C_BOARD_INFO("tvp5146", 0x5d), }, */
142};
143
144static void __init leopard_init_i2c(void)
145{
146 davinci_init_i2c(&i2c_pdata);
147
148 gpio_request(5, "dm355leopard_msp");
149 gpio_direction_input(5);
150 dm355leopard_i2c_info[0].irq = gpio_to_irq(5);
151
152 i2c_register_board_info(1, dm355leopard_i2c_info,
153 ARRAY_SIZE(dm355leopard_i2c_info));
154}
155
156static struct resource dm355leopard_dm9000_rsrc[] = {
157 {
158 /* addr */
159 .start = 0x04000000,
160 .end = 0x04000001,
161 .flags = IORESOURCE_MEM,
162 }, {
163 /* data */
164 .start = 0x04000016,
165 .end = 0x04000017,
166 .flags = IORESOURCE_MEM,
167 }, {
168 .flags = IORESOURCE_IRQ
169 | IORESOURCE_IRQ_HIGHEDGE /* rising (active high) */,
170 },
171};
172
173static struct platform_device dm355leopard_dm9000 = {
174 .name = "dm9000",
175 .id = -1,
176 .resource = dm355leopard_dm9000_rsrc,
177 .num_resources = ARRAY_SIZE(dm355leopard_dm9000_rsrc),
178};
179
180static struct platform_device *davinci_leopard_devices[] __initdata = {
181 &dm355leopard_dm9000,
182 &davinci_nand_device,
183};
184
185static struct davinci_uart_config uart_config __initdata = {
186 .enabled_uarts = (1 << 0),
187};
188
189static void __init dm355_leopard_map_io(void)
190{
191 dm355_init();
192}
193
194static int dm355leopard_mmc_get_cd(int module)
195{
196 if (!gpio_is_valid(leopard_mmc_gpio))
197 return -ENXIO;
198 /* low == card present */
199 return !gpio_get_value_cansleep(leopard_mmc_gpio + 2 * module + 1);
200}
201
202static int dm355leopard_mmc_get_ro(int module)
203{
204 if (!gpio_is_valid(leopard_mmc_gpio))
205 return -ENXIO;
206 /* high == card's write protect switch active */
207 return gpio_get_value_cansleep(leopard_mmc_gpio + 2 * module + 0);
208}
209
210static struct davinci_mmc_config dm355leopard_mmc_config = {
211 .get_cd = dm355leopard_mmc_get_cd,
212 .get_ro = dm355leopard_mmc_get_ro,
213 .wires = 4,
214 .max_freq = 50000000,
215 .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
216};
217
218/* Don't connect anything to J10 unless you're only using USB host
219 * mode *and* have to do so with some kind of gender-bender. If
220 * you have proper Mini-B or Mini-A cables (or Mini-A adapters)
221 * the ID pin won't need any help.
222 */
223#ifdef CONFIG_USB_MUSB_PERIPHERAL
224#define USB_ID_VALUE 0 /* ID pulled high; *should* float */
225#else
226#define USB_ID_VALUE 1 /* ID pulled low */
227#endif
228
229static struct spi_eeprom at25640a = {
230 .byte_len = SZ_64K / 8,
231 .name = "at25640a",
232 .page_size = 32,
233 .flags = EE_ADDR2,
234};
235
236static struct spi_board_info dm355_leopard_spi_info[] __initconst = {
237 {
238 .modalias = "at25",
239 .platform_data = &at25640a,
240 .max_speed_hz = 10 * 1000 * 1000, /* at 3v3 */
241 .bus_num = 0,
242 .chip_select = 0,
243 .mode = SPI_MODE_0,
244 },
245};
246
247static __init void dm355_leopard_init(void)
248{
249 struct clk *aemif;
250
251 gpio_request(9, "dm9000");
252 gpio_direction_input(9);
253 dm355leopard_dm9000_rsrc[2].start = gpio_to_irq(9);
254
255 aemif = clk_get(&dm355leopard_dm9000.dev, "aemif");
256 if (IS_ERR(aemif))
257 WARN("%s: unable to get AEMIF clock\n", __func__);
258 else
259 clk_enable(aemif);
260
261 platform_add_devices(davinci_leopard_devices,
262 ARRAY_SIZE(davinci_leopard_devices));
263 leopard_init_i2c();
264 davinci_serial_init(&uart_config);
265
266 /* NOTE: NAND flash timings set by the UBL are slower than
267 * needed by MT29F16G08FAA chips ... EMIF.A1CR is 0x40400204
268 * but could be 0x0400008c for about 25% faster page reads.
269 */
270
271 gpio_request(2, "usb_id_toggle");
272 gpio_direction_output(2, USB_ID_VALUE);
273 /* irlml6401 switches over 1A in under 8 msec */
274 setup_usb(500, 8);
275
276 davinci_setup_mmc(0, &dm355leopard_mmc_config);
277 davinci_setup_mmc(1, &dm355leopard_mmc_config);
278
279 dm355_init_spi0(BIT(0), dm355_leopard_spi_info,
280 ARRAY_SIZE(dm355_leopard_spi_info));
281}
282
283static __init void dm355_leopard_irq_init(void)
284{
285 davinci_irq_init();
286}
287
288MACHINE_START(DM355_LEOPARD, "DaVinci DM355 leopard")
289 .phys_io = IO_PHYS,
290 .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
291 .boot_params = (0x80000100),
292 .map_io = dm355_leopard_map_io,
293 .init_irq = dm355_leopard_irq_init,
294 .timer = &davinci_timer,
295 .init_machine = dm355_leopard_init,
296MACHINE_END
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index b2e7f9c63bc..d9d40450bdc 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -16,12 +16,11 @@
16#include <linux/gpio.h> 16#include <linux/gpio.h>
17#include <linux/leds.h> 17#include <linux/leds.h>
18#include <linux/memory.h> 18#include <linux/memory.h>
19#include <linux/etherdevice.h>
20 19
21#include <linux/i2c.h> 20#include <linux/i2c.h>
22#include <linux/i2c/pcf857x.h> 21#include <linux/i2c/pcf857x.h>
23#include <linux/i2c/at24.h> 22#include <linux/i2c/at24.h>
24 23#include <linux/etherdevice.h>
25#include <linux/mtd/mtd.h> 24#include <linux/mtd/mtd.h>
26#include <linux/mtd/nand.h> 25#include <linux/mtd/nand.h>
27#include <linux/mtd/partitions.h> 26#include <linux/mtd/partitions.h>
@@ -44,6 +43,9 @@
44#include <mach/mux.h> 43#include <mach/mux.h>
45#include <mach/psc.h> 44#include <mach/psc.h>
46#include <mach/nand.h> 45#include <mach/nand.h>
46#include <mach/mmc.h>
47#include <mach/emac.h>
48#include <mach/common.h>
47 49
48#define DM644X_EVM_PHY_MASK (0x2) 50#define DM644X_EVM_PHY_MASK (0x2)
49#define DM644X_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */ 51#define DM644X_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */
@@ -436,45 +438,15 @@ static struct pcf857x_platform_data pcf_data_u35 = {
436 * - 0x0039, 1 byte NTSC vs PAL (bit 0x80 == PAL) 438 * - 0x0039, 1 byte NTSC vs PAL (bit 0x80 == PAL)
437 * - ... newer boards may have more 439 * - ... newer boards may have more
438 */ 440 */
439static struct memory_accessor *at24_mem_acc;
440
441static void at24_setup(struct memory_accessor *mem_acc, void *context)
442{
443 DECLARE_MAC_BUF(mac_str);
444 char mac_addr[6];
445
446 at24_mem_acc = mem_acc;
447
448 /* Read MAC addr from EEPROM */
449 if (at24_mem_acc->read(at24_mem_acc, mac_addr, 0x7f00, 6) == 6) {
450 printk(KERN_INFO "Read MAC addr from EEPROM: %s\n",
451 print_mac(mac_str, mac_addr));
452 }
453}
454 441
455static struct at24_platform_data eeprom_info = { 442static struct at24_platform_data eeprom_info = {
456 .byte_len = (256*1024) / 8, 443 .byte_len = (256*1024) / 8,
457 .page_size = 64, 444 .page_size = 64,
458 .flags = AT24_FLAG_ADDR16, 445 .flags = AT24_FLAG_ADDR16,
459 .setup = at24_setup, 446 .setup = davinci_get_mac_addr,
447 .context = (void *)0x7f00,
460}; 448};
461 449
462int dm6446evm_eeprom_read(void *buf, off_t off, size_t count)
463{
464 if (at24_mem_acc)
465 return at24_mem_acc->read(at24_mem_acc, buf, off, count);
466 return -ENODEV;
467}
468EXPORT_SYMBOL(dm6446evm_eeprom_read);
469
470int dm6446evm_eeprom_write(void *buf, off_t off, size_t count)
471{
472 if (at24_mem_acc)
473 return at24_mem_acc->write(at24_mem_acc, buf, off, count);
474 return -ENODEV;
475}
476EXPORT_SYMBOL(dm6446evm_eeprom_write);
477
478/* 450/*
479 * MSP430 supports RTC, card detection, input from IR remote, and 451 * MSP430 supports RTC, card detection, input from IR remote, and
480 * a bit more. It triggers interrupts on GPIO(7) from pressing 452 * a bit more. It triggers interrupts on GPIO(7) from pressing
@@ -545,6 +517,27 @@ static int dm6444evm_msp430_get_pins(void)
545 return (buf[3] << 8) | buf[2]; 517 return (buf[3] << 8) | buf[2];
546} 518}
547 519
520static int dm6444evm_mmc_get_cd(int module)
521{
522 int status = dm6444evm_msp430_get_pins();
523
524 return (status < 0) ? status : !(status & BIT(1));
525}
526
527static int dm6444evm_mmc_get_ro(int module)
528{
529 int status = dm6444evm_msp430_get_pins();
530
531 return (status < 0) ? status : status & BIT(6 + 8);
532}
533
534static struct davinci_mmc_config dm6446evm_mmc_config = {
535 .get_cd = dm6444evm_mmc_get_cd,
536 .get_ro = dm6444evm_mmc_get_ro,
537 .wires = 4,
538 .version = MMC_CTLR_VERSION_1
539};
540
548static struct i2c_board_info __initdata i2c_info[] = { 541static struct i2c_board_info __initdata i2c_info[] = {
549 { 542 {
550 I2C_BOARD_INFO("dm6446evm_msp", 0x23), 543 I2C_BOARD_INFO("dm6446evm_msp", 0x23),
@@ -598,7 +591,6 @@ static struct davinci_uart_config uart_config __initdata = {
598static void __init 591static void __init
599davinci_evm_map_io(void) 592davinci_evm_map_io(void)
600{ 593{
601 davinci_map_common_io();
602 dm644x_init(); 594 dm644x_init();
603} 595}
604 596
@@ -639,6 +631,7 @@ static int davinci_phy_fixup(struct phy_device *phydev)
639static __init void davinci_evm_init(void) 631static __init void davinci_evm_init(void)
640{ 632{
641 struct clk *aemif_clk; 633 struct clk *aemif_clk;
634 struct davinci_soc_info *soc_info = &davinci_soc_info;
642 635
643 aemif_clk = clk_get(NULL, "aemif"); 636 aemif_clk = clk_get(NULL, "aemif");
644 clk_enable(aemif_clk); 637 clk_enable(aemif_clk);
@@ -671,8 +664,13 @@ static __init void davinci_evm_init(void)
671 ARRAY_SIZE(davinci_evm_devices)); 664 ARRAY_SIZE(davinci_evm_devices));
672 evm_init_i2c(); 665 evm_init_i2c();
673 666
667 davinci_setup_mmc(0, &dm6446evm_mmc_config);
668
674 davinci_serial_init(&uart_config); 669 davinci_serial_init(&uart_config);
675 670
671 soc_info->emac_pdata->phy_mask = DM644X_EVM_PHY_MASK;
672 soc_info->emac_pdata->mdio_max_freq = DM644X_EVM_MDIO_FREQUENCY;
673
676 /* Register the fixup for PHY on DaVinci */ 674 /* Register the fixup for PHY on DaVinci */
677 phy_register_fixup_for_uid(LXT971_PHY_ID, LXT971_PHY_MASK, 675 phy_register_fixup_for_uid(LXT971_PHY_ID, LXT971_PHY_MASK,
678 davinci_phy_fixup); 676 davinci_phy_fixup);
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c
new file mode 100644
index 00000000000..e17de635262
--- /dev/null
+++ b/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -0,0 +1,262 @@
1/*
2 * TI DaVinci DM646X EVM board
3 *
4 * Derived from: arch/arm/mach-davinci/board-evm.c
5 * Copyright (C) 2006 Texas Instruments.
6 *
7 * (C) 2007-2008, MontaVista Software, Inc.
8 *
9 * This file is licensed under the terms of the GNU General Public License
10 * version 2. This program is licensed "as is" without any warranty of any
11 * kind, whether express or implied.
12 *
13 */
14
15/**************************************************************************
16 * Included Files
17 **************************************************************************/
18
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/init.h>
22#include <linux/fs.h>
23#include <linux/major.h>
24#include <linux/root_dev.h>
25#include <linux/dma-mapping.h>
26#include <linux/serial.h>
27#include <linux/serial_8250.h>
28#include <linux/leds.h>
29#include <linux/gpio.h>
30#include <linux/io.h>
31#include <linux/platform_device.h>
32#include <linux/i2c.h>
33#include <linux/i2c/at24.h>
34#include <linux/i2c/pcf857x.h>
35#include <linux/etherdevice.h>
36
37#include <asm/setup.h>
38#include <asm/mach-types.h>
39#include <asm/mach/arch.h>
40#include <asm/mach/map.h>
41#include <asm/mach/flash.h>
42
43#include <mach/dm646x.h>
44#include <mach/common.h>
45#include <mach/psc.h>
46#include <mach/serial.h>
47#include <mach/i2c.h>
48#include <mach/mmc.h>
49#include <mach/emac.h>
50#include <mach/common.h>
51
52#define DM646X_EVM_PHY_MASK (0x2)
53#define DM646X_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */
54
55static struct davinci_uart_config uart_config __initdata = {
56 .enabled_uarts = (1 << 0),
57};
58
59/* LEDS */
60
61static struct gpio_led evm_leds[] = {
62 { .name = "DS1", .active_low = 1, },
63 { .name = "DS2", .active_low = 1, },
64 { .name = "DS3", .active_low = 1, },
65 { .name = "DS4", .active_low = 1, },
66};
67
68static __initconst struct gpio_led_platform_data evm_led_data = {
69 .num_leds = ARRAY_SIZE(evm_leds),
70 .leds = evm_leds,
71};
72
73static struct platform_device *evm_led_dev;
74
75static int evm_led_setup(struct i2c_client *client, int gpio,
76 unsigned int ngpio, void *c)
77{
78 struct gpio_led *leds = evm_leds;
79 int status;
80
81 while (ngpio--) {
82 leds->gpio = gpio++;
83 leds++;
84 };
85
86 evm_led_dev = platform_device_alloc("leds-gpio", 0);
87 platform_device_add_data(evm_led_dev, &evm_led_data,
88 sizeof(evm_led_data));
89
90 evm_led_dev->dev.parent = &client->dev;
91 status = platform_device_add(evm_led_dev);
92 if (status < 0) {
93 platform_device_put(evm_led_dev);
94 evm_led_dev = NULL;
95 }
96 return status;
97}
98
99static int evm_led_teardown(struct i2c_client *client, int gpio,
100 unsigned ngpio, void *c)
101{
102 if (evm_led_dev) {
103 platform_device_unregister(evm_led_dev);
104 evm_led_dev = NULL;
105 }
106 return 0;
107}
108
109static int evm_sw_gpio[4] = { -EINVAL, -EINVAL, -EINVAL, -EINVAL };
110
111static int evm_sw_setup(struct i2c_client *client, int gpio,
112 unsigned ngpio, void *c)
113{
114 int status;
115 int i;
116 char label[10];
117
118 for (i = 0; i < 4; ++i) {
119 snprintf(label, 10, "user_sw%d", i);
120 status = gpio_request(gpio, label);
121 if (status)
122 goto out_free;
123 evm_sw_gpio[i] = gpio++;
124
125 status = gpio_direction_input(evm_sw_gpio[i]);
126 if (status) {
127 gpio_free(evm_sw_gpio[i]);
128 evm_sw_gpio[i] = -EINVAL;
129 goto out_free;
130 }
131
132 status = gpio_export(evm_sw_gpio[i], 0);
133 if (status) {
134 gpio_free(evm_sw_gpio[i]);
135 evm_sw_gpio[i] = -EINVAL;
136 goto out_free;
137 }
138 }
139 return status;
140out_free:
141 for (i = 0; i < 4; ++i) {
142 if (evm_sw_gpio[i] != -EINVAL) {
143 gpio_free(evm_sw_gpio[i]);
144 evm_sw_gpio[i] = -EINVAL;
145 }
146 }
147 return status;
148}
149
150static int evm_sw_teardown(struct i2c_client *client, int gpio,
151 unsigned ngpio, void *c)
152{
153 int i;
154
155 for (i = 0; i < 4; ++i) {
156 if (evm_sw_gpio[i] != -EINVAL) {
157 gpio_unexport(evm_sw_gpio[i]);
158 gpio_free(evm_sw_gpio[i]);
159 evm_sw_gpio[i] = -EINVAL;
160 }
161 }
162 return 0;
163}
164
165static int evm_pcf_setup(struct i2c_client *client, int gpio,
166 unsigned int ngpio, void *c)
167{
168 int status;
169
170 if (ngpio < 8)
171 return -EINVAL;
172
173 status = evm_sw_setup(client, gpio, 4, c);
174 if (status)
175 return status;
176
177 return evm_led_setup(client, gpio+4, 4, c);
178}
179
180static int evm_pcf_teardown(struct i2c_client *client, int gpio,
181 unsigned int ngpio, void *c)
182{
183 BUG_ON(ngpio < 8);
184
185 evm_sw_teardown(client, gpio, 4, c);
186 evm_led_teardown(client, gpio+4, 4, c);
187
188 return 0;
189}
190
191static struct pcf857x_platform_data pcf_data = {
192 .gpio_base = DAVINCI_N_GPIO+1,
193 .setup = evm_pcf_setup,
194 .teardown = evm_pcf_teardown,
195};
196
197/* Most of this EEPROM is unused, but U-Boot uses some data:
198 * - 0x7f00, 6 bytes Ethernet Address
199 * - ... newer boards may have more
200 */
201
202static struct at24_platform_data eeprom_info = {
203 .byte_len = (256*1024) / 8,
204 .page_size = 64,
205 .flags = AT24_FLAG_ADDR16,
206 .setup = davinci_get_mac_addr,
207 .context = (void *)0x7f00,
208};
209
210static struct i2c_board_info __initdata i2c_info[] = {
211 {
212 I2C_BOARD_INFO("24c256", 0x50),
213 .platform_data = &eeprom_info,
214 },
215 {
216 I2C_BOARD_INFO("pcf8574a", 0x38),
217 .platform_data = &pcf_data,
218 },
219};
220
221static struct davinci_i2c_platform_data i2c_pdata = {
222 .bus_freq = 100 /* kHz */,
223 .bus_delay = 0 /* usec */,
224};
225
226static void __init evm_init_i2c(void)
227{
228 davinci_init_i2c(&i2c_pdata);
229 i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
230}
231
232static void __init davinci_map_io(void)
233{
234 dm646x_init();
235}
236
237static __init void evm_init(void)
238{
239 struct davinci_soc_info *soc_info = &davinci_soc_info;
240
241 evm_init_i2c();
242 davinci_serial_init(&uart_config);
243
244 soc_info->emac_pdata->phy_mask = DM646X_EVM_PHY_MASK;
245 soc_info->emac_pdata->mdio_max_freq = DM646X_EVM_MDIO_FREQUENCY;
246}
247
248static __init void davinci_dm646x_evm_irq_init(void)
249{
250 davinci_irq_init();
251}
252
253MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM")
254 .phys_io = IO_PHYS,
255 .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
256 .boot_params = (0x80000100),
257 .map_io = davinci_map_io,
258 .init_irq = davinci_dm646x_evm_irq_init,
259 .timer = &davinci_timer,
260 .init_machine = evm_init,
261MACHINE_END
262
diff --git a/arch/arm/mach-davinci/board-sffsdr.c b/arch/arm/mach-davinci/board-sffsdr.c
new file mode 100644
index 00000000000..748a8e48541
--- /dev/null
+++ b/arch/arm/mach-davinci/board-sffsdr.c
@@ -0,0 +1,189 @@
1/*
2 * Lyrtech SFFSDR board support.
3 *
4 * Copyright (C) 2008 Philip Balister, OpenSDR <philip@opensdr.com>
5 * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
6 *
7 * Based on DV-EVM platform, original copyright follows:
8 *
9 * Copyright (C) 2007 MontaVista Software, Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26#include <linux/kernel.h>
27#include <linux/module.h>
28#include <linux/init.h>
29#include <linux/dma-mapping.h>
30#include <linux/platform_device.h>
31#include <linux/gpio.h>
32
33#include <linux/i2c.h>
34#include <linux/i2c/at24.h>
35#include <linux/etherdevice.h>
36#include <linux/mtd/mtd.h>
37#include <linux/mtd/nand.h>
38#include <linux/mtd/partitions.h>
39#include <linux/mtd/physmap.h>
40#include <linux/io.h>
41
42#include <asm/setup.h>
43#include <asm/mach-types.h>
44
45#include <asm/mach/arch.h>
46#include <asm/mach/map.h>
47#include <asm/mach/flash.h>
48
49#include <mach/dm644x.h>
50#include <mach/common.h>
51#include <mach/i2c.h>
52#include <mach/serial.h>
53#include <mach/psc.h>
54#include <mach/mux.h>
55#include <mach/common.h>
56
57#define SFFSDR_PHY_MASK (0x2)
58#define SFFSDR_MDIO_FREQUENCY (2200000) /* PHY bus frequency */
59
60#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e00000
61#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
62
63struct mtd_partition davinci_sffsdr_nandflash_partition[] = {
64 /* U-Boot Environment: Block 0
65 * UBL: Block 1
66 * U-Boot: Blocks 6-7 (256 kb)
67 * Integrity Kernel: Blocks 8-31 (3 Mb)
68 * Integrity Data: Blocks 100-END
69 */
70 {
71 .name = "Linux Kernel",
72 .offset = 32 * SZ_128K,
73 .size = 16 * SZ_128K, /* 2 Mb */
74 .mask_flags = MTD_WRITEABLE, /* Force read-only */
75 },
76 {
77 .name = "Linux ROOT",
78 .offset = MTDPART_OFS_APPEND,
79 .size = 256 * SZ_128K, /* 32 Mb */
80 .mask_flags = 0, /* R/W */
81 },
82};
83
84static struct flash_platform_data davinci_sffsdr_nandflash_data = {
85 .parts = davinci_sffsdr_nandflash_partition,
86 .nr_parts = ARRAY_SIZE(davinci_sffsdr_nandflash_partition),
87};
88
89static struct resource davinci_sffsdr_nandflash_resource[] = {
90 {
91 .start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
92 .end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
93 .flags = IORESOURCE_MEM,
94 }, {
95 .start = DAVINCI_ASYNC_EMIF_CONTROL_BASE,
96 .end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
97 .flags = IORESOURCE_MEM,
98 },
99};
100
101static struct platform_device davinci_sffsdr_nandflash_device = {
102 .name = "davinci_nand", /* Name of driver */
103 .id = 0,
104 .dev = {
105 .platform_data = &davinci_sffsdr_nandflash_data,
106 },
107 .num_resources = ARRAY_SIZE(davinci_sffsdr_nandflash_resource),
108 .resource = davinci_sffsdr_nandflash_resource,
109};
110
111static struct emac_platform_data sffsdr_emac_pdata = {
112 .phy_mask = SFFSDR_PHY_MASK,
113 .mdio_max_freq = SFFSDR_MDIO_FREQUENCY,
114};
115
116static struct at24_platform_data eeprom_info = {
117 .byte_len = (64*1024) / 8,
118 .page_size = 32,
119 .flags = AT24_FLAG_ADDR16,
120};
121
122static struct i2c_board_info __initdata i2c_info[] = {
123 {
124 I2C_BOARD_INFO("24lc64", 0x50),
125 .platform_data = &eeprom_info,
126 },
127 /* Other I2C devices:
128 * MSP430, addr 0x23 (not used)
129 * PCA9543, addr 0x70 (setup done by U-Boot)
130 * ADS7828, addr 0x48 (ADC for voltage monitoring.)
131 */
132};
133
134static struct davinci_i2c_platform_data i2c_pdata = {
135 .bus_freq = 20 /* kHz */,
136 .bus_delay = 100 /* usec */,
137};
138
139static void __init sffsdr_init_i2c(void)
140{
141 davinci_init_i2c(&i2c_pdata);
142 i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
143}
144
145static struct platform_device *davinci_sffsdr_devices[] __initdata = {
146 &davinci_sffsdr_nandflash_device,
147};
148
149static struct davinci_uart_config uart_config __initdata = {
150 .enabled_uarts = (1 << 0),
151};
152
153static void __init davinci_sffsdr_map_io(void)
154{
155 dm644x_init();
156}
157
158static __init void davinci_sffsdr_init(void)
159{
160 struct davinci_soc_info *soc_info = &davinci_soc_info;
161
162 platform_add_devices(davinci_sffsdr_devices,
163 ARRAY_SIZE(davinci_sffsdr_devices));
164 sffsdr_init_i2c();
165 davinci_serial_init(&uart_config);
166 soc_info->emac_pdata->phy_mask = SFFSDR_PHY_MASK;
167 soc_info->emac_pdata->mdio_max_freq = SFFSDR_MDIO_FREQUENCY;
168 setup_usb(0, 0); /* We support only peripheral mode. */
169
170 /* mux VLYNQ pins */
171 davinci_cfg_reg(DM644X_VLYNQEN);
172 davinci_cfg_reg(DM644X_VLYNQWD);
173}
174
175static __init void davinci_sffsdr_irq_init(void)
176{
177 davinci_irq_init();
178}
179
180MACHINE_START(SFFSDR, "Lyrtech SFFSDR")
181 /* Maintainer: Hugo Villeneuve hugo.villeneuve@lyrtech.com */
182 .phys_io = IO_PHYS,
183 .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
184 .boot_params = (DAVINCI_DDR_BASE + 0x100),
185 .map_io = davinci_sffsdr_map_io,
186 .init_irq = davinci_sffsdr_irq_init,
187 .timer = &davinci_timer,
188 .init_machine = davinci_sffsdr_init,
189MACHINE_END
diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
index f0baaa15a57..39bf321d70a 100644
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -42,7 +42,8 @@ static void __clk_enable(struct clk *clk)
42 if (clk->parent) 42 if (clk->parent)
43 __clk_enable(clk->parent); 43 __clk_enable(clk->parent);
44 if (clk->usecount++ == 0 && (clk->flags & CLK_PSC)) 44 if (clk->usecount++ == 0 && (clk->flags & CLK_PSC))
45 davinci_psc_config(psc_domain(clk), clk->lpsc, 1); 45 davinci_psc_config(psc_domain(clk), clk->psc_ctlr,
46 clk->lpsc, 1);
46} 47}
47 48
48static void __clk_disable(struct clk *clk) 49static void __clk_disable(struct clk *clk)
@@ -50,7 +51,8 @@ static void __clk_disable(struct clk *clk)
50 if (WARN_ON(clk->usecount == 0)) 51 if (WARN_ON(clk->usecount == 0))
51 return; 52 return;
52 if (--clk->usecount == 0 && !(clk->flags & CLK_PLL)) 53 if (--clk->usecount == 0 && !(clk->flags & CLK_PLL))
53 davinci_psc_config(psc_domain(clk), clk->lpsc, 0); 54 davinci_psc_config(psc_domain(clk), clk->psc_ctlr,
55 clk->lpsc, 0);
54 if (clk->parent) 56 if (clk->parent)
55 __clk_disable(clk->parent); 57 __clk_disable(clk->parent);
56} 58}
@@ -164,11 +166,11 @@ static int __init clk_disable_unused(void)
164 continue; 166 continue;
165 167
166 /* ignore if in Disabled or SwRstDisable states */ 168 /* ignore if in Disabled or SwRstDisable states */
167 if (!davinci_psc_is_clk_active(ck->lpsc)) 169 if (!davinci_psc_is_clk_active(ck->psc_ctlr, ck->lpsc))
168 continue; 170 continue;
169 171
170 pr_info("Clocks: disable unused %s\n", ck->name); 172 pr_info("Clocks: disable unused %s\n", ck->name);
171 davinci_psc_config(psc_domain(ck), ck->lpsc, 0); 173 davinci_psc_config(psc_domain(ck), ck->psc_ctlr, ck->lpsc, 0);
172 } 174 }
173 spin_unlock_irq(&clockfw_lock); 175 spin_unlock_irq(&clockfw_lock);
174 176
diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h
index 35736ec202f..27233cb4a2f 100644
--- a/arch/arm/mach-davinci/clock.h
+++ b/arch/arm/mach-davinci/clock.h
@@ -67,6 +67,7 @@ struct clk {
67 u8 usecount; 67 u8 usecount;
68 u8 flags; 68 u8 flags;
69 u8 lpsc; 69 u8 lpsc;
70 u8 psc_ctlr;
70 struct clk *parent; 71 struct clk *parent;
71 struct pll_data *pll_data; 72 struct pll_data *pll_data;
72 u32 div_reg; 73 u32 div_reg;
@@ -93,4 +94,7 @@ struct davinci_clk {
93 } 94 }
94 95
95int davinci_clk_init(struct davinci_clk *clocks); 96int davinci_clk_init(struct davinci_clk *clocks);
97
98extern struct platform_device davinci_wdt_device;
99
96#endif 100#endif
diff --git a/arch/arm/mach-davinci/common.c b/arch/arm/mach-davinci/common.c
new file mode 100644
index 00000000000..61ede19c6b5
--- /dev/null
+++ b/arch/arm/mach-davinci/common.c
@@ -0,0 +1,108 @@
1/*
2 * Code commons to all DaVinci SoCs.
3 *
4 * Author: Mark A. Greer <mgreer@mvista.com>
5 *
6 * 2009 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11#include <linux/module.h>
12#include <linux/io.h>
13#include <linux/etherdevice.h>
14
15#include <asm/tlb.h>
16#include <asm/mach/map.h>
17
18#include <mach/common.h>
19#include <mach/cputype.h>
20#include <mach/emac.h>
21
22#include "clock.h"
23
24struct davinci_soc_info davinci_soc_info;
25EXPORT_SYMBOL(davinci_soc_info);
26
27void __iomem *davinci_intc_base;
28int davinci_intc_type;
29
30void davinci_get_mac_addr(struct memory_accessor *mem_acc, void *context)
31{
32 char *mac_addr = davinci_soc_info.emac_pdata->mac_addr;
33 off_t offset = (off_t)context;
34
35 /* Read MAC addr from EEPROM */
36 if (mem_acc->read(mem_acc, mac_addr, offset, ETH_ALEN) == ETH_ALEN)
37 pr_info("Read MAC addr from EEPROM: %pM\n", mac_addr);
38}
39
40static struct davinci_id * __init davinci_get_id(u32 jtag_id)
41{
42 int i;
43 struct davinci_id *dip;
44 u8 variant = (jtag_id & 0xf0000000) >> 28;
45 u16 part_no = (jtag_id & 0x0ffff000) >> 12;
46
47 for (i = 0, dip = davinci_soc_info.ids; i < davinci_soc_info.ids_num;
48 i++, dip++)
49 /* Don't care about the manufacturer right now */
50 if ((dip->part_no == part_no) && (dip->variant == variant))
51 return dip;
52
53 return NULL;
54}
55
56void __init davinci_common_init(struct davinci_soc_info *soc_info)
57{
58 int ret;
59 struct davinci_id *dip;
60
61 if (!soc_info) {
62 ret = -EINVAL;
63 goto err;
64 }
65
66 memcpy(&davinci_soc_info, soc_info, sizeof(struct davinci_soc_info));
67
68 if (davinci_soc_info.io_desc && (davinci_soc_info.io_desc_num > 0))
69 iotable_init(davinci_soc_info.io_desc,
70 davinci_soc_info.io_desc_num);
71
72 /*
73 * Normally devicemaps_init() would flush caches and tlb after
74 * mdesc->map_io(), but we must also do it here because of the CPU
75 * revision check below.
76 */
77 local_flush_tlb_all();
78 flush_cache_all();
79
80 /*
81 * We want to check CPU revision early for cpu_is_xxxx() macros.
82 * IO space mapping must be initialized before we can do that.
83 */
84 davinci_soc_info.jtag_id = __raw_readl(davinci_soc_info.jtag_id_base);
85
86 dip = davinci_get_id(davinci_soc_info.jtag_id);
87 if (!dip) {
88 ret = -EINVAL;
89 goto err;
90 }
91
92 davinci_soc_info.cpu_id = dip->cpu_id;
93 pr_info("DaVinci %s variant 0x%x\n", dip->name, dip->variant);
94
95 if (davinci_soc_info.cpu_clks) {
96 ret = davinci_clk_init(davinci_soc_info.cpu_clks);
97
98 if (ret != 0)
99 goto err;
100 }
101
102 davinci_intc_base = davinci_soc_info.intc_base;
103 davinci_intc_type = davinci_soc_info.intc_type;
104 return;
105
106err:
107 pr_err("davinci_common_init: SoC Initialization failed\n");
108}
diff --git a/arch/arm/mach-davinci/cp_intc.c b/arch/arm/mach-davinci/cp_intc.c
new file mode 100644
index 00000000000..96c8e97a7de
--- /dev/null
+++ b/arch/arm/mach-davinci/cp_intc.c
@@ -0,0 +1,161 @@
1/*
2 * TI Common Platform Interrupt Controller (cp_intc) driver
3 *
4 * Author: Steve Chen <schen@mvista.com>
5 * Copyright (C) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11
12#include <linux/init.h>
13#include <linux/sched.h>
14#include <linux/interrupt.h>
15#include <linux/kernel.h>
16#include <linux/irq.h>
17#include <linux/io.h>
18
19#include <mach/cp_intc.h>
20
21static void __iomem *cp_intc_base;
22
23static inline unsigned int cp_intc_read(unsigned offset)
24{
25 return __raw_readl(cp_intc_base + offset);
26}
27
28static inline void cp_intc_write(unsigned long value, unsigned offset)
29{
30 __raw_writel(value, cp_intc_base + offset);
31}
32
33static void cp_intc_ack_irq(unsigned int irq)
34{
35 cp_intc_write(irq, CP_INTC_SYS_STAT_IDX_CLR);
36}
37
38/* Disable interrupt */
39static void cp_intc_mask_irq(unsigned int irq)
40{
41 /* XXX don't know why we need to disable nIRQ here... */
42 cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_CLR);
43 cp_intc_write(irq, CP_INTC_SYS_ENABLE_IDX_CLR);
44 cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_SET);
45}
46
47/* Enable interrupt */
48static void cp_intc_unmask_irq(unsigned int irq)
49{
50 cp_intc_write(irq, CP_INTC_SYS_ENABLE_IDX_SET);
51}
52
53static int cp_intc_set_irq_type(unsigned int irq, unsigned int flow_type)
54{
55 unsigned reg = BIT_WORD(irq);
56 unsigned mask = BIT_MASK(irq);
57 unsigned polarity = cp_intc_read(CP_INTC_SYS_POLARITY(reg));
58 unsigned type = cp_intc_read(CP_INTC_SYS_TYPE(reg));
59
60 switch (flow_type) {
61 case IRQ_TYPE_EDGE_RISING:
62 polarity |= mask;
63 type |= mask;
64 break;
65 case IRQ_TYPE_EDGE_FALLING:
66 polarity &= ~mask;
67 type |= mask;
68 break;
69 case IRQ_TYPE_LEVEL_HIGH:
70 polarity |= mask;
71 type &= ~mask;
72 break;
73 case IRQ_TYPE_LEVEL_LOW:
74 polarity &= ~mask;
75 type &= ~mask;
76 break;
77 default:
78 return -EINVAL;
79 }
80
81 cp_intc_write(polarity, CP_INTC_SYS_POLARITY(reg));
82 cp_intc_write(type, CP_INTC_SYS_TYPE(reg));
83
84 return 0;
85}
86
87static struct irq_chip cp_intc_irq_chip = {
88 .name = "cp_intc",
89 .ack = cp_intc_ack_irq,
90 .mask = cp_intc_mask_irq,
91 .unmask = cp_intc_unmask_irq,
92 .set_type = cp_intc_set_irq_type,
93};
94
95void __init cp_intc_init(void __iomem *base, unsigned short num_irq,
96 u8 *irq_prio)
97{
98 unsigned num_reg = BITS_TO_LONGS(num_irq);
99 int i;
100
101 cp_intc_base = base;
102
103 cp_intc_write(0, CP_INTC_GLOBAL_ENABLE);
104
105 /* Disable all host interrupts */
106 cp_intc_write(0, CP_INTC_HOST_ENABLE(0));
107
108 /* Disable system interrupts */
109 for (i = 0; i < num_reg; i++)
110 cp_intc_write(~0, CP_INTC_SYS_ENABLE_CLR(i));
111
112 /* Set to normal mode, no nesting, no priority hold */
113 cp_intc_write(0, CP_INTC_CTRL);
114 cp_intc_write(0, CP_INTC_HOST_CTRL);
115
116 /* Clear system interrupt status */
117 for (i = 0; i < num_reg; i++)
118 cp_intc_write(~0, CP_INTC_SYS_STAT_CLR(i));
119
120 /* Enable nIRQ (what about nFIQ?) */
121 cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_SET);
122
123 /*
124 * Priority is determined by host channel: lower channel number has
125 * higher priority i.e. channel 0 has highest priority and channel 31
126 * had the lowest priority.
127 */
128 num_reg = (num_irq + 3) >> 2; /* 4 channels per register */
129 if (irq_prio) {
130 unsigned j, k;
131 u32 val;
132
133 for (k = i = 0; i < num_reg; i++) {
134 for (val = j = 0; j < 4; j++, k++) {
135 val >>= 8;
136 if (k < num_irq)
137 val |= irq_prio[k] << 24;
138 }
139
140 cp_intc_write(val, CP_INTC_CHAN_MAP(i));
141 }
142 } else {
143 /*
144 * Default everything to channel 15 if priority not specified.
145 * Note that channel 0-1 are mapped to nFIQ and channels 2-31
146 * are mapped to nIRQ.
147 */
148 for (i = 0; i < num_reg; i++)
149 cp_intc_write(0x0f0f0f0f, CP_INTC_CHAN_MAP(i));
150 }
151
152 /* Set up genirq dispatching for cp_intc */
153 for (i = 0; i < num_irq; i++) {
154 set_irq_chip(i, &cp_intc_irq_chip);
155 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
156 set_irq_handler(i, handle_edge_irq);
157 }
158
159 /* Enable global interrupt */
160 cp_intc_write(1, CP_INTC_GLOBAL_ENABLE);
161}
diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
index a31370b93dd..de16f347566 100644
--- a/arch/arm/mach-davinci/devices.c
+++ b/arch/arm/mach-davinci/devices.c
@@ -23,8 +23,14 @@
23#include <mach/irqs.h> 23#include <mach/irqs.h>
24#include <mach/cputype.h> 24#include <mach/cputype.h>
25#include <mach/mux.h> 25#include <mach/mux.h>
26#include <mach/edma.h>
27#include <mach/mmc.h>
28#include <mach/time.h>
26 29
27#define DAVINCI_I2C_BASE 0x01C21000 30#define DAVINCI_I2C_BASE 0x01C21000
31#define DAVINCI_MMCSD0_BASE 0x01E10000
32#define DM355_MMCSD0_BASE 0x01E11000
33#define DM355_MMCSD1_BASE 0x01E00000
28 34
29static struct resource i2c_resources[] = { 35static struct resource i2c_resources[] = {
30 { 36 {
@@ -54,3 +60,208 @@ void __init davinci_init_i2c(struct davinci_i2c_platform_data *pdata)
54 (void) platform_device_register(&davinci_i2c_device); 60 (void) platform_device_register(&davinci_i2c_device);
55} 61}
56 62
63#if defined(CONFIG_MMC_DAVINCI) || defined(CONFIG_MMC_DAVINCI_MODULE)
64
65static u64 mmcsd0_dma_mask = DMA_BIT_MASK(32);
66
67static struct resource mmcsd0_resources[] = {
68 {
69 /* different on dm355 */
70 .start = DAVINCI_MMCSD0_BASE,
71 .end = DAVINCI_MMCSD0_BASE + SZ_4K - 1,
72 .flags = IORESOURCE_MEM,
73 },
74 /* IRQs: MMC/SD, then SDIO */
75 {
76 .start = IRQ_MMCINT,
77 .flags = IORESOURCE_IRQ,
78 }, {
79 /* different on dm355 */
80 .start = IRQ_SDIOINT,
81 .flags = IORESOURCE_IRQ,
82 },
83 /* DMA channels: RX, then TX */
84 {
85 .start = DAVINCI_DMA_MMCRXEVT,
86 .flags = IORESOURCE_DMA,
87 }, {
88 .start = DAVINCI_DMA_MMCTXEVT,
89 .flags = IORESOURCE_DMA,
90 },
91};
92
93static struct platform_device davinci_mmcsd0_device = {
94 .name = "davinci_mmc",
95 .id = 0,
96 .dev = {
97 .dma_mask = &mmcsd0_dma_mask,
98 .coherent_dma_mask = DMA_BIT_MASK(32),
99 },
100 .num_resources = ARRAY_SIZE(mmcsd0_resources),
101 .resource = mmcsd0_resources,
102};
103
104static u64 mmcsd1_dma_mask = DMA_BIT_MASK(32);
105
106static struct resource mmcsd1_resources[] = {
107 {
108 .start = DM355_MMCSD1_BASE,
109 .end = DM355_MMCSD1_BASE + SZ_4K - 1,
110 .flags = IORESOURCE_MEM,
111 },
112 /* IRQs: MMC/SD, then SDIO */
113 {
114 .start = IRQ_DM355_MMCINT1,
115 .flags = IORESOURCE_IRQ,
116 }, {
117 .start = IRQ_DM355_SDIOINT1,
118 .flags = IORESOURCE_IRQ,
119 },
120 /* DMA channels: RX, then TX */
121 {
122 .start = 30, /* rx */
123 .flags = IORESOURCE_DMA,
124 }, {
125 .start = 31, /* tx */
126 .flags = IORESOURCE_DMA,
127 },
128};
129
130static struct platform_device davinci_mmcsd1_device = {
131 .name = "davinci_mmc",
132 .id = 1,
133 .dev = {
134 .dma_mask = &mmcsd1_dma_mask,
135 .coherent_dma_mask = DMA_BIT_MASK(32),
136 },
137 .num_resources = ARRAY_SIZE(mmcsd1_resources),
138 .resource = mmcsd1_resources,
139};
140
141
142void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config)
143{
144 struct platform_device *pdev = NULL;
145
146 if (WARN_ON(cpu_is_davinci_dm646x()))
147 return;
148
149 /* REVISIT: update PINMUX, ARM_IRQMUX, and EDMA_EVTMUX here too;
150 * for example if MMCSD1 is used for SDIO, maybe DAT2 is unused.
151 *
152 * FIXME dm6441 (no MMC/SD), dm357 (one), and dm335 (two) are
153 * not handled right here ...
154 */
155 switch (module) {
156 case 1:
157 if (!cpu_is_davinci_dm355())
158 break;
159
160 /* REVISIT we may not need all these pins if e.g. this
161 * is a hard-wired SDIO device...
162 */
163 davinci_cfg_reg(DM355_SD1_CMD);
164 davinci_cfg_reg(DM355_SD1_CLK);
165 davinci_cfg_reg(DM355_SD1_DATA0);
166 davinci_cfg_reg(DM355_SD1_DATA1);
167 davinci_cfg_reg(DM355_SD1_DATA2);
168 davinci_cfg_reg(DM355_SD1_DATA3);
169
170 pdev = &davinci_mmcsd1_device;
171 break;
172 case 0:
173 if (cpu_is_davinci_dm355()) {
174 mmcsd0_resources[0].start = DM355_MMCSD0_BASE;
175 mmcsd0_resources[0].end = DM355_MMCSD0_BASE + SZ_4K - 1;
176 mmcsd0_resources[2].start = IRQ_DM355_SDIOINT0;
177
178 /* expose all 6 MMC0 signals: CLK, CMD, DATA[0..3] */
179 davinci_cfg_reg(DM355_MMCSD0);
180
181 /* enable RX EDMA */
182 davinci_cfg_reg(DM355_EVT26_MMC0_RX);
183 }
184
185 else if (cpu_is_davinci_dm644x()) {
186 /* REVISIT: should this be in board-init code? */
187 void __iomem *base =
188 IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE);
189
190 /* Power-on 3.3V IO cells */
191 __raw_writel(0, base + DM64XX_VDD3P3V_PWDN);
192 /*Set up the pull regiter for MMC */
193 davinci_cfg_reg(DM644X_MSTK);
194 }
195
196 pdev = &davinci_mmcsd0_device;
197 break;
198 }
199
200 if (WARN_ON(!pdev))
201 return;
202
203 pdev->dev.platform_data = config;
204 platform_device_register(pdev);
205}
206
207#else
208
209void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config)
210{
211}
212
213#endif
214
215/*-------------------------------------------------------------------------*/
216
217static struct resource wdt_resources[] = {
218 {
219 .flags = IORESOURCE_MEM,
220 },
221};
222
223struct platform_device davinci_wdt_device = {
224 .name = "watchdog",
225 .id = -1,
226 .num_resources = ARRAY_SIZE(wdt_resources),
227 .resource = wdt_resources,
228};
229
230static void davinci_init_wdt(void)
231{
232 struct davinci_soc_info *soc_info = &davinci_soc_info;
233
234 wdt_resources[0].start = (resource_size_t)soc_info->wdt_base;
235 wdt_resources[0].end = (resource_size_t)soc_info->wdt_base + SZ_1K - 1;
236
237 platform_device_register(&davinci_wdt_device);
238}
239
240/*-------------------------------------------------------------------------*/
241
242struct davinci_timer_instance davinci_timer_instance[2] = {
243 {
244 .base = IO_ADDRESS(DAVINCI_TIMER0_BASE),
245 .bottom_irq = IRQ_TINT0_TINT12,
246 .top_irq = IRQ_TINT0_TINT34,
247 },
248 {
249 .base = IO_ADDRESS(DAVINCI_TIMER1_BASE),
250 .bottom_irq = IRQ_TINT1_TINT12,
251 .top_irq = IRQ_TINT1_TINT34,
252 },
253};
254
255/*-------------------------------------------------------------------------*/
256
257static int __init davinci_init_devices(void)
258{
259 /* please keep these calls, and their implementations above,
260 * in alphabetical order so they're easier to sort through.
261 */
262 davinci_init_wdt();
263
264 return 0;
265}
266arch_initcall(davinci_init_devices);
267
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
new file mode 100644
index 00000000000..baaaf328de2
--- /dev/null
+++ b/arch/arm/mach-davinci/dm355.c
@@ -0,0 +1,730 @@
1/*
2 * TI DaVinci DM355 chip specific setup
3 *
4 * Author: Kevin Hilman, Deep Root Systems, LLC
5 *
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/clk.h>
14#include <linux/serial_8250.h>
15#include <linux/platform_device.h>
16#include <linux/dma-mapping.h>
17#include <linux/gpio.h>
18
19#include <linux/spi/spi.h>
20
21#include <asm/mach/map.h>
22
23#include <mach/dm355.h>
24#include <mach/clock.h>
25#include <mach/cputype.h>
26#include <mach/edma.h>
27#include <mach/psc.h>
28#include <mach/mux.h>
29#include <mach/irqs.h>
30#include <mach/time.h>
31#include <mach/serial.h>
32#include <mach/common.h>
33
34#include "clock.h"
35#include "mux.h"
36
37#define DM355_UART2_BASE (IO_PHYS + 0x206000)
38
39/*
40 * Device specific clocks
41 */
42#define DM355_REF_FREQ 24000000 /* 24 or 36 MHz */
43
44static struct pll_data pll1_data = {
45 .num = 1,
46 .phys_base = DAVINCI_PLL1_BASE,
47 .flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
48};
49
50static struct pll_data pll2_data = {
51 .num = 2,
52 .phys_base = DAVINCI_PLL2_BASE,
53 .flags = PLL_HAS_PREDIV,
54};
55
56static struct clk ref_clk = {
57 .name = "ref_clk",
58 /* FIXME -- crystal rate is board-specific */
59 .rate = DM355_REF_FREQ,
60};
61
62static struct clk pll1_clk = {
63 .name = "pll1",
64 .parent = &ref_clk,
65 .flags = CLK_PLL,
66 .pll_data = &pll1_data,
67};
68
69static struct clk pll1_aux_clk = {
70 .name = "pll1_aux_clk",
71 .parent = &pll1_clk,
72 .flags = CLK_PLL | PRE_PLL,
73};
74
75static struct clk pll1_sysclk1 = {
76 .name = "pll1_sysclk1",
77 .parent = &pll1_clk,
78 .flags = CLK_PLL,
79 .div_reg = PLLDIV1,
80};
81
82static struct clk pll1_sysclk2 = {
83 .name = "pll1_sysclk2",
84 .parent = &pll1_clk,
85 .flags = CLK_PLL,
86 .div_reg = PLLDIV2,
87};
88
89static struct clk pll1_sysclk3 = {
90 .name = "pll1_sysclk3",
91 .parent = &pll1_clk,
92 .flags = CLK_PLL,
93 .div_reg = PLLDIV3,
94};
95
96static struct clk pll1_sysclk4 = {
97 .name = "pll1_sysclk4",
98 .parent = &pll1_clk,
99 .flags = CLK_PLL,
100 .div_reg = PLLDIV4,
101};
102
103static struct clk pll1_sysclkbp = {
104 .name = "pll1_sysclkbp",
105 .parent = &pll1_clk,
106 .flags = CLK_PLL | PRE_PLL,
107 .div_reg = BPDIV
108};
109
110static struct clk vpss_dac_clk = {
111 .name = "vpss_dac",
112 .parent = &pll1_sysclk3,
113 .lpsc = DM355_LPSC_VPSS_DAC,
114};
115
116static struct clk vpss_master_clk = {
117 .name = "vpss_master",
118 .parent = &pll1_sysclk4,
119 .lpsc = DAVINCI_LPSC_VPSSMSTR,
120 .flags = CLK_PSC,
121};
122
123static struct clk vpss_slave_clk = {
124 .name = "vpss_slave",
125 .parent = &pll1_sysclk4,
126 .lpsc = DAVINCI_LPSC_VPSSSLV,
127};
128
129
130static struct clk clkout1_clk = {
131 .name = "clkout1",
132 .parent = &pll1_aux_clk,
133 /* NOTE: clkout1 can be externally gated by muxing GPIO-18 */
134};
135
136static struct clk clkout2_clk = {
137 .name = "clkout2",
138 .parent = &pll1_sysclkbp,
139};
140
141static struct clk pll2_clk = {
142 .name = "pll2",
143 .parent = &ref_clk,
144 .flags = CLK_PLL,
145 .pll_data = &pll2_data,
146};
147
148static struct clk pll2_sysclk1 = {
149 .name = "pll2_sysclk1",
150 .parent = &pll2_clk,
151 .flags = CLK_PLL,
152 .div_reg = PLLDIV1,
153};
154
155static struct clk pll2_sysclkbp = {
156 .name = "pll2_sysclkbp",
157 .parent = &pll2_clk,
158 .flags = CLK_PLL | PRE_PLL,
159 .div_reg = BPDIV
160};
161
162static struct clk clkout3_clk = {
163 .name = "clkout3",
164 .parent = &pll2_sysclkbp,
165 /* NOTE: clkout3 can be externally gated by muxing GPIO-16 */
166};
167
168static struct clk arm_clk = {
169 .name = "arm_clk",
170 .parent = &pll1_sysclk1,
171 .lpsc = DAVINCI_LPSC_ARM,
172 .flags = ALWAYS_ENABLED,
173};
174
175/*
176 * NOT LISTED below, and not touched by Linux
177 * - in SyncReset state by default
178 * .lpsc = DAVINCI_LPSC_TPCC,
179 * .lpsc = DAVINCI_LPSC_TPTC0,
180 * .lpsc = DAVINCI_LPSC_TPTC1,
181 * .lpsc = DAVINCI_LPSC_DDR_EMIF, .parent = &sysclk2_clk,
182 * .lpsc = DAVINCI_LPSC_MEMSTICK,
183 * - in Enabled state by default
184 * .lpsc = DAVINCI_LPSC_SYSTEM_SUBSYS,
185 * .lpsc = DAVINCI_LPSC_SCR2, // "bus"
186 * .lpsc = DAVINCI_LPSC_SCR3, // "bus"
187 * .lpsc = DAVINCI_LPSC_SCR4, // "bus"
188 * .lpsc = DAVINCI_LPSC_CROSSBAR, // "emulation"
189 * .lpsc = DAVINCI_LPSC_CFG27, // "test"
190 * .lpsc = DAVINCI_LPSC_CFG3, // "test"
191 * .lpsc = DAVINCI_LPSC_CFG5, // "test"
192 */
193
194static struct clk mjcp_clk = {
195 .name = "mjcp",
196 .parent = &pll1_sysclk1,
197 .lpsc = DAVINCI_LPSC_IMCOP,
198};
199
200static struct clk uart0_clk = {
201 .name = "uart0",
202 .parent = &pll1_aux_clk,
203 .lpsc = DAVINCI_LPSC_UART0,
204};
205
206static struct clk uart1_clk = {
207 .name = "uart1",
208 .parent = &pll1_aux_clk,
209 .lpsc = DAVINCI_LPSC_UART1,
210};
211
212static struct clk uart2_clk = {
213 .name = "uart2",
214 .parent = &pll1_sysclk2,
215 .lpsc = DAVINCI_LPSC_UART2,
216};
217
218static struct clk i2c_clk = {
219 .name = "i2c",
220 .parent = &pll1_aux_clk,
221 .lpsc = DAVINCI_LPSC_I2C,
222};
223
224static struct clk asp0_clk = {
225 .name = "asp0",
226 .parent = &pll1_sysclk2,
227 .lpsc = DAVINCI_LPSC_McBSP,
228};
229
230static struct clk asp1_clk = {
231 .name = "asp1",
232 .parent = &pll1_sysclk2,
233 .lpsc = DM355_LPSC_McBSP1,
234};
235
236static struct clk mmcsd0_clk = {
237 .name = "mmcsd0",
238 .parent = &pll1_sysclk2,
239 .lpsc = DAVINCI_LPSC_MMC_SD,
240};
241
242static struct clk mmcsd1_clk = {
243 .name = "mmcsd1",
244 .parent = &pll1_sysclk2,
245 .lpsc = DM355_LPSC_MMC_SD1,
246};
247
248static struct clk spi0_clk = {
249 .name = "spi0",
250 .parent = &pll1_sysclk2,
251 .lpsc = DAVINCI_LPSC_SPI,
252};
253
254static struct clk spi1_clk = {
255 .name = "spi1",
256 .parent = &pll1_sysclk2,
257 .lpsc = DM355_LPSC_SPI1,
258};
259
260static struct clk spi2_clk = {
261 .name = "spi2",
262 .parent = &pll1_sysclk2,
263 .lpsc = DM355_LPSC_SPI2,
264};
265
266static struct clk gpio_clk = {
267 .name = "gpio",
268 .parent = &pll1_sysclk2,
269 .lpsc = DAVINCI_LPSC_GPIO,
270};
271
272static struct clk aemif_clk = {
273 .name = "aemif",
274 .parent = &pll1_sysclk2,
275 .lpsc = DAVINCI_LPSC_AEMIF,
276};
277
278static struct clk pwm0_clk = {
279 .name = "pwm0",
280 .parent = &pll1_aux_clk,
281 .lpsc = DAVINCI_LPSC_PWM0,
282};
283
284static struct clk pwm1_clk = {
285 .name = "pwm1",
286 .parent = &pll1_aux_clk,
287 .lpsc = DAVINCI_LPSC_PWM1,
288};
289
290static struct clk pwm2_clk = {
291 .name = "pwm2",
292 .parent = &pll1_aux_clk,
293 .lpsc = DAVINCI_LPSC_PWM2,
294};
295
296static struct clk pwm3_clk = {
297 .name = "pwm3",
298 .parent = &pll1_aux_clk,
299 .lpsc = DM355_LPSC_PWM3,
300};
301
302static struct clk timer0_clk = {
303 .name = "timer0",
304 .parent = &pll1_aux_clk,
305 .lpsc = DAVINCI_LPSC_TIMER0,
306};
307
308static struct clk timer1_clk = {
309 .name = "timer1",
310 .parent = &pll1_aux_clk,
311 .lpsc = DAVINCI_LPSC_TIMER1,
312};
313
314static struct clk timer2_clk = {
315 .name = "timer2",
316 .parent = &pll1_aux_clk,
317 .lpsc = DAVINCI_LPSC_TIMER2,
318 .usecount = 1, /* REVISIT: why cant' this be disabled? */
319};
320
321static struct clk timer3_clk = {
322 .name = "timer3",
323 .parent = &pll1_aux_clk,
324 .lpsc = DM355_LPSC_TIMER3,
325};
326
327static struct clk rto_clk = {
328 .name = "rto",
329 .parent = &pll1_aux_clk,
330 .lpsc = DM355_LPSC_RTO,
331};
332
333static struct clk usb_clk = {
334 .name = "usb",
335 .parent = &pll1_sysclk2,
336 .lpsc = DAVINCI_LPSC_USB,
337};
338
339static struct davinci_clk dm355_clks[] = {
340 CLK(NULL, "ref", &ref_clk),
341 CLK(NULL, "pll1", &pll1_clk),
342 CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
343 CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
344 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
345 CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
346 CLK(NULL, "pll1_aux", &pll1_aux_clk),
347 CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
348 CLK(NULL, "vpss_dac", &vpss_dac_clk),
349 CLK(NULL, "vpss_master", &vpss_master_clk),
350 CLK(NULL, "vpss_slave", &vpss_slave_clk),
351 CLK(NULL, "clkout1", &clkout1_clk),
352 CLK(NULL, "clkout2", &clkout2_clk),
353 CLK(NULL, "pll2", &pll2_clk),
354 CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
355 CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp),
356 CLK(NULL, "clkout3", &clkout3_clk),
357 CLK(NULL, "arm", &arm_clk),
358 CLK(NULL, "mjcp", &mjcp_clk),
359 CLK(NULL, "uart0", &uart0_clk),
360 CLK(NULL, "uart1", &uart1_clk),
361 CLK(NULL, "uart2", &uart2_clk),
362 CLK("i2c_davinci.1", NULL, &i2c_clk),
363 CLK("soc-audio.0", NULL, &asp0_clk),
364 CLK("soc-audio.1", NULL, &asp1_clk),
365 CLK("davinci_mmc.0", NULL, &mmcsd0_clk),
366 CLK("davinci_mmc.1", NULL, &mmcsd1_clk),
367 CLK(NULL, "spi0", &spi0_clk),
368 CLK(NULL, "spi1", &spi1_clk),
369 CLK(NULL, "spi2", &spi2_clk),
370 CLK(NULL, "gpio", &gpio_clk),
371 CLK(NULL, "aemif", &aemif_clk),
372 CLK(NULL, "pwm0", &pwm0_clk),
373 CLK(NULL, "pwm1", &pwm1_clk),
374 CLK(NULL, "pwm2", &pwm2_clk),
375 CLK(NULL, "pwm3", &pwm3_clk),
376 CLK(NULL, "timer0", &timer0_clk),
377 CLK(NULL, "timer1", &timer1_clk),
378 CLK("watchdog", NULL, &timer2_clk),
379 CLK(NULL, "timer3", &timer3_clk),
380 CLK(NULL, "rto", &rto_clk),
381 CLK(NULL, "usb", &usb_clk),
382 CLK(NULL, NULL, NULL),
383};
384
385/*----------------------------------------------------------------------*/
386
387static u64 dm355_spi0_dma_mask = DMA_BIT_MASK(32);
388
389static struct resource dm355_spi0_resources[] = {
390 {
391 .start = 0x01c66000,
392 .end = 0x01c667ff,
393 .flags = IORESOURCE_MEM,
394 },
395 {
396 .start = IRQ_DM355_SPINT0_1,
397 .flags = IORESOURCE_IRQ,
398 },
399 /* Not yet used, so not included:
400 * IORESOURCE_IRQ:
401 * - IRQ_DM355_SPINT0_0
402 * IORESOURCE_DMA:
403 * - DAVINCI_DMA_SPI_SPIX
404 * - DAVINCI_DMA_SPI_SPIR
405 */
406};
407
408static struct platform_device dm355_spi0_device = {
409 .name = "spi_davinci",
410 .id = 0,
411 .dev = {
412 .dma_mask = &dm355_spi0_dma_mask,
413 .coherent_dma_mask = DMA_BIT_MASK(32),
414 },
415 .num_resources = ARRAY_SIZE(dm355_spi0_resources),
416 .resource = dm355_spi0_resources,
417};
418
419void __init dm355_init_spi0(unsigned chipselect_mask,
420 struct spi_board_info *info, unsigned len)
421{
422 /* for now, assume we need MISO */
423 davinci_cfg_reg(DM355_SPI0_SDI);
424
425 /* not all slaves will be wired up */
426 if (chipselect_mask & BIT(0))
427 davinci_cfg_reg(DM355_SPI0_SDENA0);
428 if (chipselect_mask & BIT(1))
429 davinci_cfg_reg(DM355_SPI0_SDENA1);
430
431 spi_register_board_info(info, len);
432
433 platform_device_register(&dm355_spi0_device);
434}
435
436/*----------------------------------------------------------------------*/
437
438#define PINMUX0 0x00
439#define PINMUX1 0x04
440#define PINMUX2 0x08
441#define PINMUX3 0x0c
442#define PINMUX4 0x10
443#define INTMUX 0x18
444#define EVTMUX 0x1c
445
446/*
447 * Device specific mux setup
448 *
449 * soc description mux mode mode mux dbg
450 * reg offset mask mode
451 */
452static const struct mux_config dm355_pins[] = {
453#ifdef CONFIG_DAVINCI_MUX
454MUX_CFG(DM355, MMCSD0, 4, 2, 1, 0, false)
455
456MUX_CFG(DM355, SD1_CLK, 3, 6, 1, 1, false)
457MUX_CFG(DM355, SD1_CMD, 3, 7, 1, 1, false)
458MUX_CFG(DM355, SD1_DATA3, 3, 8, 3, 1, false)
459MUX_CFG(DM355, SD1_DATA2, 3, 10, 3, 1, false)
460MUX_CFG(DM355, SD1_DATA1, 3, 12, 3, 1, false)
461MUX_CFG(DM355, SD1_DATA0, 3, 14, 3, 1, false)
462
463MUX_CFG(DM355, I2C_SDA, 3, 19, 1, 1, false)
464MUX_CFG(DM355, I2C_SCL, 3, 20, 1, 1, false)
465
466MUX_CFG(DM355, MCBSP0_BDX, 3, 0, 1, 1, false)
467MUX_CFG(DM355, MCBSP0_X, 3, 1, 1, 1, false)
468MUX_CFG(DM355, MCBSP0_BFSX, 3, 2, 1, 1, false)
469MUX_CFG(DM355, MCBSP0_BDR, 3, 3, 1, 1, false)
470MUX_CFG(DM355, MCBSP0_R, 3, 4, 1, 1, false)
471MUX_CFG(DM355, MCBSP0_BFSR, 3, 5, 1, 1, false)
472
473MUX_CFG(DM355, SPI0_SDI, 4, 1, 1, 0, false)
474MUX_CFG(DM355, SPI0_SDENA0, 4, 0, 1, 0, false)
475MUX_CFG(DM355, SPI0_SDENA1, 3, 28, 1, 1, false)
476
477INT_CFG(DM355, INT_EDMA_CC, 2, 1, 1, false)
478INT_CFG(DM355, INT_EDMA_TC0_ERR, 3, 1, 1, false)
479INT_CFG(DM355, INT_EDMA_TC1_ERR, 4, 1, 1, false)
480
481EVT_CFG(DM355, EVT8_ASP1_TX, 0, 1, 0, false)
482EVT_CFG(DM355, EVT9_ASP1_RX, 1, 1, 0, false)
483EVT_CFG(DM355, EVT26_MMC0_RX, 2, 1, 0, false)
484#endif
485};
486
487static u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = {
488 [IRQ_DM355_CCDC_VDINT0] = 2,
489 [IRQ_DM355_CCDC_VDINT1] = 6,
490 [IRQ_DM355_CCDC_VDINT2] = 6,
491 [IRQ_DM355_IPIPE_HST] = 6,
492 [IRQ_DM355_H3AINT] = 6,
493 [IRQ_DM355_IPIPE_SDR] = 6,
494 [IRQ_DM355_IPIPEIFINT] = 6,
495 [IRQ_DM355_OSDINT] = 7,
496 [IRQ_DM355_VENCINT] = 6,
497 [IRQ_ASQINT] = 6,
498 [IRQ_IMXINT] = 6,
499 [IRQ_USBINT] = 4,
500 [IRQ_DM355_RTOINT] = 4,
501 [IRQ_DM355_UARTINT2] = 7,
502 [IRQ_DM355_TINT6] = 7,
503 [IRQ_CCINT0] = 5, /* dma */
504 [IRQ_CCERRINT] = 5, /* dma */
505 [IRQ_TCERRINT0] = 5, /* dma */
506 [IRQ_TCERRINT] = 5, /* dma */
507 [IRQ_DM355_SPINT2_1] = 7,
508 [IRQ_DM355_TINT7] = 4,
509 [IRQ_DM355_SDIOINT0] = 7,
510 [IRQ_MBXINT] = 7,
511 [IRQ_MBRINT] = 7,
512 [IRQ_MMCINT] = 7,
513 [IRQ_DM355_MMCINT1] = 7,
514 [IRQ_DM355_PWMINT3] = 7,
515 [IRQ_DDRINT] = 7,
516 [IRQ_AEMIFINT] = 7,
517 [IRQ_DM355_SDIOINT1] = 4,
518 [IRQ_TINT0_TINT12] = 2, /* clockevent */
519 [IRQ_TINT0_TINT34] = 2, /* clocksource */
520 [IRQ_TINT1_TINT12] = 7, /* DSP timer */
521 [IRQ_TINT1_TINT34] = 7, /* system tick */
522 [IRQ_PWMINT0] = 7,
523 [IRQ_PWMINT1] = 7,
524 [IRQ_PWMINT2] = 7,
525 [IRQ_I2C] = 3,
526 [IRQ_UARTINT0] = 3,
527 [IRQ_UARTINT1] = 3,
528 [IRQ_DM355_SPINT0_0] = 3,
529 [IRQ_DM355_SPINT0_1] = 3,
530 [IRQ_DM355_GPIO0] = 3,
531 [IRQ_DM355_GPIO1] = 7,
532 [IRQ_DM355_GPIO2] = 4,
533 [IRQ_DM355_GPIO3] = 4,
534 [IRQ_DM355_GPIO4] = 7,
535 [IRQ_DM355_GPIO5] = 7,
536 [IRQ_DM355_GPIO6] = 7,
537 [IRQ_DM355_GPIO7] = 7,
538 [IRQ_DM355_GPIO8] = 7,
539 [IRQ_DM355_GPIO9] = 7,
540 [IRQ_DM355_GPIOBNK0] = 7,
541 [IRQ_DM355_GPIOBNK1] = 7,
542 [IRQ_DM355_GPIOBNK2] = 7,
543 [IRQ_DM355_GPIOBNK3] = 7,
544 [IRQ_DM355_GPIOBNK4] = 7,
545 [IRQ_DM355_GPIOBNK5] = 7,
546 [IRQ_DM355_GPIOBNK6] = 7,
547 [IRQ_COMMTX] = 7,
548 [IRQ_COMMRX] = 7,
549 [IRQ_EMUINT] = 7,
550};
551
552/*----------------------------------------------------------------------*/
553
554static const s8 dma_chan_dm355_no_event[] = {
555 12, 13, 24, 56, 57,
556 58, 59, 60, 61, 62,
557 63,
558 -1
559};
560
561static struct edma_soc_info dm355_edma_info = {
562 .n_channel = 64,
563 .n_region = 4,
564 .n_slot = 128,
565 .n_tc = 2,
566 .noevent = dma_chan_dm355_no_event,
567};
568
569static struct resource edma_resources[] = {
570 {
571 .name = "edma_cc",
572 .start = 0x01c00000,
573 .end = 0x01c00000 + SZ_64K - 1,
574 .flags = IORESOURCE_MEM,
575 },
576 {
577 .name = "edma_tc0",
578 .start = 0x01c10000,
579 .end = 0x01c10000 + SZ_1K - 1,
580 .flags = IORESOURCE_MEM,
581 },
582 {
583 .name = "edma_tc1",
584 .start = 0x01c10400,
585 .end = 0x01c10400 + SZ_1K - 1,
586 .flags = IORESOURCE_MEM,
587 },
588 {
589 .start = IRQ_CCINT0,
590 .flags = IORESOURCE_IRQ,
591 },
592 {
593 .start = IRQ_CCERRINT,
594 .flags = IORESOURCE_IRQ,
595 },
596 /* not using (or muxing) TC*_ERR */
597};
598
599static struct platform_device dm355_edma_device = {
600 .name = "edma",
601 .id = -1,
602 .dev.platform_data = &dm355_edma_info,
603 .num_resources = ARRAY_SIZE(edma_resources),
604 .resource = edma_resources,
605};
606
607/*----------------------------------------------------------------------*/
608
609static struct map_desc dm355_io_desc[] = {
610 {
611 .virtual = IO_VIRT,
612 .pfn = __phys_to_pfn(IO_PHYS),
613 .length = IO_SIZE,
614 .type = MT_DEVICE
615 },
616 {
617 .virtual = SRAM_VIRT,
618 .pfn = __phys_to_pfn(0x00010000),
619 .length = SZ_32K,
620 /* MT_MEMORY_NONCACHED requires supersection alignment */
621 .type = MT_DEVICE,
622 },
623};
624
625/* Contents of JTAG ID register used to identify exact cpu type */
626static struct davinci_id dm355_ids[] = {
627 {
628 .variant = 0x0,
629 .part_no = 0xb73b,
630 .manufacturer = 0x00f,
631 .cpu_id = DAVINCI_CPU_ID_DM355,
632 .name = "dm355",
633 },
634};
635
636static void __iomem *dm355_psc_bases[] = {
637 IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
638};
639
640/*
641 * T0_BOT: Timer 0, bottom: clockevent source for hrtimers
642 * T0_TOP: Timer 0, top : clocksource for generic timekeeping
643 * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
644 * T1_TOP: Timer 1, top : <unused>
645 */
646struct davinci_timer_info dm355_timer_info = {
647 .timers = davinci_timer_instance,
648 .clockevent_id = T0_BOT,
649 .clocksource_id = T0_TOP,
650};
651
652static struct plat_serial8250_port dm355_serial_platform_data[] = {
653 {
654 .mapbase = DAVINCI_UART0_BASE,
655 .irq = IRQ_UARTINT0,
656 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
657 UPF_IOREMAP,
658 .iotype = UPIO_MEM,
659 .regshift = 2,
660 },
661 {
662 .mapbase = DAVINCI_UART1_BASE,
663 .irq = IRQ_UARTINT1,
664 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
665 UPF_IOREMAP,
666 .iotype = UPIO_MEM,
667 .regshift = 2,
668 },
669 {
670 .mapbase = DM355_UART2_BASE,
671 .irq = IRQ_DM355_UARTINT2,
672 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
673 UPF_IOREMAP,
674 .iotype = UPIO_MEM,
675 .regshift = 2,
676 },
677 {
678 .flags = 0
679 },
680};
681
682static struct platform_device dm355_serial_device = {
683 .name = "serial8250",
684 .id = PLAT8250_DEV_PLATFORM,
685 .dev = {
686 .platform_data = dm355_serial_platform_data,
687 },
688};
689
690static struct davinci_soc_info davinci_soc_info_dm355 = {
691 .io_desc = dm355_io_desc,
692 .io_desc_num = ARRAY_SIZE(dm355_io_desc),
693 .jtag_id_base = IO_ADDRESS(0x01c40028),
694 .ids = dm355_ids,
695 .ids_num = ARRAY_SIZE(dm355_ids),
696 .cpu_clks = dm355_clks,
697 .psc_bases = dm355_psc_bases,
698 .psc_bases_num = ARRAY_SIZE(dm355_psc_bases),
699 .pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
700 .pinmux_pins = dm355_pins,
701 .pinmux_pins_num = ARRAY_SIZE(dm355_pins),
702 .intc_base = IO_ADDRESS(DAVINCI_ARM_INTC_BASE),
703 .intc_type = DAVINCI_INTC_TYPE_AINTC,
704 .intc_irq_prios = dm355_default_priorities,
705 .intc_irq_num = DAVINCI_N_AINTC_IRQ,
706 .timer_info = &dm355_timer_info,
707 .wdt_base = IO_ADDRESS(DAVINCI_WDOG_BASE),
708 .gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE),
709 .gpio_num = 104,
710 .gpio_irq = IRQ_DM355_GPIOBNK0,
711 .serial_dev = &dm355_serial_device,
712 .sram_dma = 0x00010000,
713 .sram_len = SZ_32K,
714};
715
716void __init dm355_init(void)
717{
718 davinci_common_init(&davinci_soc_info_dm355);
719}
720
721static int __init dm355_init_devices(void)
722{
723 if (!cpu_is_davinci_dm355())
724 return 0;
725
726 davinci_cfg_reg(DM355_INT_EDMA_CC);
727 platform_device_register(&dm355_edma_device);
728 return 0;
729}
730postcore_initcall(dm355_init_devices);
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index d428ef192ea..fb5449b3c97 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -11,7 +11,11 @@
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/clk.h> 13#include <linux/clk.h>
14#include <linux/serial_8250.h>
14#include <linux/platform_device.h> 15#include <linux/platform_device.h>
16#include <linux/gpio.h>
17
18#include <asm/mach/map.h>
15 19
16#include <mach/dm644x.h> 20#include <mach/dm644x.h>
17#include <mach/clock.h> 21#include <mach/clock.h>
@@ -20,6 +24,9 @@
20#include <mach/irqs.h> 24#include <mach/irqs.h>
21#include <mach/psc.h> 25#include <mach/psc.h>
22#include <mach/mux.h> 26#include <mach/mux.h>
27#include <mach/time.h>
28#include <mach/serial.h>
29#include <mach/common.h>
23 30
24#include "clock.h" 31#include "clock.h"
25#include "mux.h" 32#include "mux.h"
@@ -312,7 +319,14 @@ struct davinci_clk dm644x_clks[] = {
312 CLK(NULL, NULL, NULL), 319 CLK(NULL, NULL, NULL),
313}; 320};
314 321
315#if defined(CONFIG_TI_DAVINCI_EMAC) || defined(CONFIG_TI_DAVINCI_EMAC_MODULE) 322static struct emac_platform_data dm644x_emac_pdata = {
323 .ctrl_reg_offset = DM644X_EMAC_CNTRL_OFFSET,
324 .ctrl_mod_reg_offset = DM644X_EMAC_CNTRL_MOD_OFFSET,
325 .ctrl_ram_offset = DM644X_EMAC_CNTRL_RAM_OFFSET,
326 .mdio_reg_offset = DM644X_EMAC_MDIO_OFFSET,
327 .ctrl_ram_size = DM644X_EMAC_CNTRL_RAM_SIZE,
328 .version = EMAC_VERSION_1,
329};
316 330
317static struct resource dm644x_emac_resources[] = { 331static struct resource dm644x_emac_resources[] = {
318 { 332 {
@@ -330,11 +344,15 @@ static struct resource dm644x_emac_resources[] = {
330static struct platform_device dm644x_emac_device = { 344static struct platform_device dm644x_emac_device = {
331 .name = "davinci_emac", 345 .name = "davinci_emac",
332 .id = 1, 346 .id = 1,
347 .dev = {
348 .platform_data = &dm644x_emac_pdata,
349 },
333 .num_resources = ARRAY_SIZE(dm644x_emac_resources), 350 .num_resources = ARRAY_SIZE(dm644x_emac_resources),
334 .resource = dm644x_emac_resources, 351 .resource = dm644x_emac_resources,
335}; 352};
336 353
337#endif 354#define PINMUX0 0x00
355#define PINMUX1 0x04
338 356
339/* 357/*
340 * Device specific mux setup 358 * Device specific mux setup
@@ -343,6 +361,7 @@ static struct platform_device dm644x_emac_device = {
343 * reg offset mask mode 361 * reg offset mask mode
344 */ 362 */
345static const struct mux_config dm644x_pins[] = { 363static const struct mux_config dm644x_pins[] = {
364#ifdef CONFIG_DAVINCI_MUX
346MUX_CFG(DM644X, HDIREN, 0, 16, 1, 1, true) 365MUX_CFG(DM644X, HDIREN, 0, 16, 1, 1, true)
347MUX_CFG(DM644X, ATAEN, 0, 17, 1, 1, true) 366MUX_CFG(DM644X, ATAEN, 0, 17, 1, 1, true)
348MUX_CFG(DM644X, ATAEN_DISABLE, 0, 17, 1, 0, true) 367MUX_CFG(DM644X, ATAEN_DISABLE, 0, 17, 1, 0, true)
@@ -383,8 +402,76 @@ MUX_CFG(DM644X, RGB666, 0, 22, 1, 1, true)
383 402
384MUX_CFG(DM644X, LOEEN, 0, 24, 1, 1, true) 403MUX_CFG(DM644X, LOEEN, 0, 24, 1, 1, true)
385MUX_CFG(DM644X, LFLDEN, 0, 25, 1, 1, false) 404MUX_CFG(DM644X, LFLDEN, 0, 25, 1, 1, false)
405#endif
386}; 406};
387 407
408/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
409static u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
410 [IRQ_VDINT0] = 2,
411 [IRQ_VDINT1] = 6,
412 [IRQ_VDINT2] = 6,
413 [IRQ_HISTINT] = 6,
414 [IRQ_H3AINT] = 6,
415 [IRQ_PRVUINT] = 6,
416 [IRQ_RSZINT] = 6,
417 [7] = 7,
418 [IRQ_VENCINT] = 6,
419 [IRQ_ASQINT] = 6,
420 [IRQ_IMXINT] = 6,
421 [IRQ_VLCDINT] = 6,
422 [IRQ_USBINT] = 4,
423 [IRQ_EMACINT] = 4,
424 [14] = 7,
425 [15] = 7,
426 [IRQ_CCINT0] = 5, /* dma */
427 [IRQ_CCERRINT] = 5, /* dma */
428 [IRQ_TCERRINT0] = 5, /* dma */
429 [IRQ_TCERRINT] = 5, /* dma */
430 [IRQ_PSCIN] = 7,
431 [21] = 7,
432 [IRQ_IDE] = 4,
433 [23] = 7,
434 [IRQ_MBXINT] = 7,
435 [IRQ_MBRINT] = 7,
436 [IRQ_MMCINT] = 7,
437 [IRQ_SDIOINT] = 7,
438 [28] = 7,
439 [IRQ_DDRINT] = 7,
440 [IRQ_AEMIFINT] = 7,
441 [IRQ_VLQINT] = 4,
442 [IRQ_TINT0_TINT12] = 2, /* clockevent */
443 [IRQ_TINT0_TINT34] = 2, /* clocksource */
444 [IRQ_TINT1_TINT12] = 7, /* DSP timer */
445 [IRQ_TINT1_TINT34] = 7, /* system tick */
446 [IRQ_PWMINT0] = 7,
447 [IRQ_PWMINT1] = 7,
448 [IRQ_PWMINT2] = 7,
449 [IRQ_I2C] = 3,
450 [IRQ_UARTINT0] = 3,
451 [IRQ_UARTINT1] = 3,
452 [IRQ_UARTINT2] = 3,
453 [IRQ_SPINT0] = 3,
454 [IRQ_SPINT1] = 3,
455 [45] = 7,
456 [IRQ_DSP2ARM0] = 4,
457 [IRQ_DSP2ARM1] = 4,
458 [IRQ_GPIO0] = 7,
459 [IRQ_GPIO1] = 7,
460 [IRQ_GPIO2] = 7,
461 [IRQ_GPIO3] = 7,
462 [IRQ_GPIO4] = 7,
463 [IRQ_GPIO5] = 7,
464 [IRQ_GPIO6] = 7,
465 [IRQ_GPIO7] = 7,
466 [IRQ_GPIOBNK0] = 7,
467 [IRQ_GPIOBNK1] = 7,
468 [IRQ_GPIOBNK2] = 7,
469 [IRQ_GPIOBNK3] = 7,
470 [IRQ_GPIOBNK4] = 7,
471 [IRQ_COMMTX] = 7,
472 [IRQ_COMMRX] = 7,
473 [IRQ_EMUINT] = 7,
474};
388 475
389/*----------------------------------------------------------------------*/ 476/*----------------------------------------------------------------------*/
390 477
@@ -444,10 +531,118 @@ static struct platform_device dm644x_edma_device = {
444}; 531};
445 532
446/*----------------------------------------------------------------------*/ 533/*----------------------------------------------------------------------*/
534
535static struct map_desc dm644x_io_desc[] = {
536 {
537 .virtual = IO_VIRT,
538 .pfn = __phys_to_pfn(IO_PHYS),
539 .length = IO_SIZE,
540 .type = MT_DEVICE
541 },
542 {
543 .virtual = SRAM_VIRT,
544 .pfn = __phys_to_pfn(0x00008000),
545 .length = SZ_16K,
546 /* MT_MEMORY_NONCACHED requires supersection alignment */
547 .type = MT_DEVICE,
548 },
549};
550
551/* Contents of JTAG ID register used to identify exact cpu type */
552static struct davinci_id dm644x_ids[] = {
553 {
554 .variant = 0x0,
555 .part_no = 0xb700,
556 .manufacturer = 0x017,
557 .cpu_id = DAVINCI_CPU_ID_DM6446,
558 .name = "dm6446",
559 },
560};
561
562static void __iomem *dm644x_psc_bases[] = {
563 IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
564};
565
566/*
567 * T0_BOT: Timer 0, bottom: clockevent source for hrtimers
568 * T0_TOP: Timer 0, top : clocksource for generic timekeeping
569 * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
570 * T1_TOP: Timer 1, top : <unused>
571 */
572struct davinci_timer_info dm644x_timer_info = {
573 .timers = davinci_timer_instance,
574 .clockevent_id = T0_BOT,
575 .clocksource_id = T0_TOP,
576};
577
578static struct plat_serial8250_port dm644x_serial_platform_data[] = {
579 {
580 .mapbase = DAVINCI_UART0_BASE,
581 .irq = IRQ_UARTINT0,
582 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
583 UPF_IOREMAP,
584 .iotype = UPIO_MEM,
585 .regshift = 2,
586 },
587 {
588 .mapbase = DAVINCI_UART1_BASE,
589 .irq = IRQ_UARTINT1,
590 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
591 UPF_IOREMAP,
592 .iotype = UPIO_MEM,
593 .regshift = 2,
594 },
595 {
596 .mapbase = DAVINCI_UART2_BASE,
597 .irq = IRQ_UARTINT2,
598 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
599 UPF_IOREMAP,
600 .iotype = UPIO_MEM,
601 .regshift = 2,
602 },
603 {
604 .flags = 0
605 },
606};
607
608static struct platform_device dm644x_serial_device = {
609 .name = "serial8250",
610 .id = PLAT8250_DEV_PLATFORM,
611 .dev = {
612 .platform_data = dm644x_serial_platform_data,
613 },
614};
615
616static struct davinci_soc_info davinci_soc_info_dm644x = {
617 .io_desc = dm644x_io_desc,
618 .io_desc_num = ARRAY_SIZE(dm644x_io_desc),
619 .jtag_id_base = IO_ADDRESS(0x01c40028),
620 .ids = dm644x_ids,
621 .ids_num = ARRAY_SIZE(dm644x_ids),
622 .cpu_clks = dm644x_clks,
623 .psc_bases = dm644x_psc_bases,
624 .psc_bases_num = ARRAY_SIZE(dm644x_psc_bases),
625 .pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
626 .pinmux_pins = dm644x_pins,
627 .pinmux_pins_num = ARRAY_SIZE(dm644x_pins),
628 .intc_base = IO_ADDRESS(DAVINCI_ARM_INTC_BASE),
629 .intc_type = DAVINCI_INTC_TYPE_AINTC,
630 .intc_irq_prios = dm644x_default_priorities,
631 .intc_irq_num = DAVINCI_N_AINTC_IRQ,
632 .timer_info = &dm644x_timer_info,
633 .wdt_base = IO_ADDRESS(DAVINCI_WDOG_BASE),
634 .gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE),
635 .gpio_num = 71,
636 .gpio_irq = IRQ_GPIOBNK0,
637 .serial_dev = &dm644x_serial_device,
638 .emac_pdata = &dm644x_emac_pdata,
639 .sram_dma = 0x00008000,
640 .sram_len = SZ_16K,
641};
642
447void __init dm644x_init(void) 643void __init dm644x_init(void)
448{ 644{
449 davinci_clk_init(dm644x_clks); 645 davinci_common_init(&davinci_soc_info_dm644x);
450 davinci_mux_register(dm644x_pins, ARRAY_SIZE(dm644x_pins));
451} 646}
452 647
453static int __init dm644x_init_devices(void) 648static int __init dm644x_init_devices(void)
@@ -456,6 +651,7 @@ static int __init dm644x_init_devices(void)
456 return 0; 651 return 0;
457 652
458 platform_device_register(&dm644x_edma_device); 653 platform_device_register(&dm644x_edma_device);
654 platform_device_register(&dm644x_emac_device);
459 return 0; 655 return 0;
460} 656}
461postcore_initcall(dm644x_init_devices); 657postcore_initcall(dm644x_init_devices);
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
new file mode 100644
index 00000000000..334f0711e0f
--- /dev/null
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -0,0 +1,636 @@
1/*
2 * TI DaVinci DM644x chip specific setup
3 *
4 * Author: Kevin Hilman, Deep Root Systems, LLC
5 *
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/clk.h>
14#include <linux/serial_8250.h>
15#include <linux/platform_device.h>
16#include <linux/gpio.h>
17
18#include <asm/mach/map.h>
19
20#include <mach/dm646x.h>
21#include <mach/clock.h>
22#include <mach/cputype.h>
23#include <mach/edma.h>
24#include <mach/irqs.h>
25#include <mach/psc.h>
26#include <mach/mux.h>
27#include <mach/time.h>
28#include <mach/serial.h>
29#include <mach/common.h>
30
31#include "clock.h"
32#include "mux.h"
33
34/*
35 * Device specific clocks
36 */
37#define DM646X_REF_FREQ 27000000
38#define DM646X_AUX_FREQ 24000000
39
40static struct pll_data pll1_data = {
41 .num = 1,
42 .phys_base = DAVINCI_PLL1_BASE,
43};
44
45static struct pll_data pll2_data = {
46 .num = 2,
47 .phys_base = DAVINCI_PLL2_BASE,
48};
49
50static struct clk ref_clk = {
51 .name = "ref_clk",
52 .rate = DM646X_REF_FREQ,
53};
54
55static struct clk aux_clkin = {
56 .name = "aux_clkin",
57 .rate = DM646X_AUX_FREQ,
58};
59
60static struct clk pll1_clk = {
61 .name = "pll1",
62 .parent = &ref_clk,
63 .pll_data = &pll1_data,
64 .flags = CLK_PLL,
65};
66
67static struct clk pll1_sysclk1 = {
68 .name = "pll1_sysclk1",
69 .parent = &pll1_clk,
70 .flags = CLK_PLL,
71 .div_reg = PLLDIV1,
72};
73
74static struct clk pll1_sysclk2 = {
75 .name = "pll1_sysclk2",
76 .parent = &pll1_clk,
77 .flags = CLK_PLL,
78 .div_reg = PLLDIV2,
79};
80
81static struct clk pll1_sysclk3 = {
82 .name = "pll1_sysclk3",
83 .parent = &pll1_clk,
84 .flags = CLK_PLL,
85 .div_reg = PLLDIV3,
86};
87
88static struct clk pll1_sysclk4 = {
89 .name = "pll1_sysclk4",
90 .parent = &pll1_clk,
91 .flags = CLK_PLL,
92 .div_reg = PLLDIV4,
93};
94
95static struct clk pll1_sysclk5 = {
96 .name = "pll1_sysclk5",
97 .parent = &pll1_clk,
98 .flags = CLK_PLL,
99 .div_reg = PLLDIV5,
100};
101
102static struct clk pll1_sysclk6 = {
103 .name = "pll1_sysclk6",
104 .parent = &pll1_clk,
105 .flags = CLK_PLL,
106 .div_reg = PLLDIV6,
107};
108
109static struct clk pll1_sysclk8 = {
110 .name = "pll1_sysclk8",
111 .parent = &pll1_clk,
112 .flags = CLK_PLL,
113 .div_reg = PLLDIV8,
114};
115
116static struct clk pll1_sysclk9 = {
117 .name = "pll1_sysclk9",
118 .parent = &pll1_clk,
119 .flags = CLK_PLL,
120 .div_reg = PLLDIV9,
121};
122
123static struct clk pll1_sysclkbp = {
124 .name = "pll1_sysclkbp",
125 .parent = &pll1_clk,
126 .flags = CLK_PLL | PRE_PLL,
127 .div_reg = BPDIV,
128};
129
130static struct clk pll1_aux_clk = {
131 .name = "pll1_aux_clk",
132 .parent = &pll1_clk,
133 .flags = CLK_PLL | PRE_PLL,
134};
135
136static struct clk pll2_clk = {
137 .name = "pll2_clk",
138 .parent = &ref_clk,
139 .pll_data = &pll2_data,
140 .flags = CLK_PLL,
141};
142
143static struct clk pll2_sysclk1 = {
144 .name = "pll2_sysclk1",
145 .parent = &pll2_clk,
146 .flags = CLK_PLL,
147 .div_reg = PLLDIV1,
148};
149
150static struct clk dsp_clk = {
151 .name = "dsp",
152 .parent = &pll1_sysclk1,
153 .lpsc = DM646X_LPSC_C64X_CPU,
154 .flags = PSC_DSP,
155 .usecount = 1, /* REVISIT how to disable? */
156};
157
158static struct clk arm_clk = {
159 .name = "arm",
160 .parent = &pll1_sysclk2,
161 .lpsc = DM646X_LPSC_ARM,
162 .flags = ALWAYS_ENABLED,
163};
164
165static struct clk uart0_clk = {
166 .name = "uart0",
167 .parent = &aux_clkin,
168 .lpsc = DM646X_LPSC_UART0,
169};
170
171static struct clk uart1_clk = {
172 .name = "uart1",
173 .parent = &aux_clkin,
174 .lpsc = DM646X_LPSC_UART1,
175};
176
177static struct clk uart2_clk = {
178 .name = "uart2",
179 .parent = &aux_clkin,
180 .lpsc = DM646X_LPSC_UART2,
181};
182
183static struct clk i2c_clk = {
184 .name = "I2CCLK",
185 .parent = &pll1_sysclk3,
186 .lpsc = DM646X_LPSC_I2C,
187};
188
189static struct clk gpio_clk = {
190 .name = "gpio",
191 .parent = &pll1_sysclk3,
192 .lpsc = DM646X_LPSC_GPIO,
193};
194
195static struct clk aemif_clk = {
196 .name = "aemif",
197 .parent = &pll1_sysclk3,
198 .lpsc = DM646X_LPSC_AEMIF,
199 .flags = ALWAYS_ENABLED,
200};
201
202static struct clk emac_clk = {
203 .name = "emac",
204 .parent = &pll1_sysclk3,
205 .lpsc = DM646X_LPSC_EMAC,
206};
207
208static struct clk pwm0_clk = {
209 .name = "pwm0",
210 .parent = &pll1_sysclk3,
211 .lpsc = DM646X_LPSC_PWM0,
212 .usecount = 1, /* REVIST: disabling hangs system */
213};
214
215static struct clk pwm1_clk = {
216 .name = "pwm1",
217 .parent = &pll1_sysclk3,
218 .lpsc = DM646X_LPSC_PWM1,
219 .usecount = 1, /* REVIST: disabling hangs system */
220};
221
222static struct clk timer0_clk = {
223 .name = "timer0",
224 .parent = &pll1_sysclk3,
225 .lpsc = DM646X_LPSC_TIMER0,
226};
227
228static struct clk timer1_clk = {
229 .name = "timer1",
230 .parent = &pll1_sysclk3,
231 .lpsc = DM646X_LPSC_TIMER1,
232};
233
234static struct clk timer2_clk = {
235 .name = "timer2",
236 .parent = &pll1_sysclk3,
237 .flags = ALWAYS_ENABLED, /* no LPSC, always enabled; c.f. spruep9a */
238};
239
240static struct clk vpif0_clk = {
241 .name = "vpif0",
242 .parent = &ref_clk,
243 .lpsc = DM646X_LPSC_VPSSMSTR,
244 .flags = ALWAYS_ENABLED,
245};
246
247static struct clk vpif1_clk = {
248 .name = "vpif1",
249 .parent = &ref_clk,
250 .lpsc = DM646X_LPSC_VPSSSLV,
251 .flags = ALWAYS_ENABLED,
252};
253
254struct davinci_clk dm646x_clks[] = {
255 CLK(NULL, "ref", &ref_clk),
256 CLK(NULL, "aux", &aux_clkin),
257 CLK(NULL, "pll1", &pll1_clk),
258 CLK(NULL, "pll1_sysclk", &pll1_sysclk1),
259 CLK(NULL, "pll1_sysclk", &pll1_sysclk2),
260 CLK(NULL, "pll1_sysclk", &pll1_sysclk3),
261 CLK(NULL, "pll1_sysclk", &pll1_sysclk4),
262 CLK(NULL, "pll1_sysclk", &pll1_sysclk5),
263 CLK(NULL, "pll1_sysclk", &pll1_sysclk6),
264 CLK(NULL, "pll1_sysclk", &pll1_sysclk8),
265 CLK(NULL, "pll1_sysclk", &pll1_sysclk9),
266 CLK(NULL, "pll1_sysclk", &pll1_sysclkbp),
267 CLK(NULL, "pll1_aux", &pll1_aux_clk),
268 CLK(NULL, "pll2", &pll2_clk),
269 CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
270 CLK(NULL, "dsp", &dsp_clk),
271 CLK(NULL, "arm", &arm_clk),
272 CLK(NULL, "uart0", &uart0_clk),
273 CLK(NULL, "uart1", &uart1_clk),
274 CLK(NULL, "uart2", &uart2_clk),
275 CLK("i2c_davinci.1", NULL, &i2c_clk),
276 CLK(NULL, "gpio", &gpio_clk),
277 CLK(NULL, "aemif", &aemif_clk),
278 CLK("davinci_emac.1", NULL, &emac_clk),
279 CLK(NULL, "pwm0", &pwm0_clk),
280 CLK(NULL, "pwm1", &pwm1_clk),
281 CLK(NULL, "timer0", &timer0_clk),
282 CLK(NULL, "timer1", &timer1_clk),
283 CLK("watchdog", NULL, &timer2_clk),
284 CLK(NULL, "vpif0", &vpif0_clk),
285 CLK(NULL, "vpif1", &vpif1_clk),
286 CLK(NULL, NULL, NULL),
287};
288
289static struct emac_platform_data dm646x_emac_pdata = {
290 .ctrl_reg_offset = DM646X_EMAC_CNTRL_OFFSET,
291 .ctrl_mod_reg_offset = DM646X_EMAC_CNTRL_MOD_OFFSET,
292 .ctrl_ram_offset = DM646X_EMAC_CNTRL_RAM_OFFSET,
293 .mdio_reg_offset = DM646X_EMAC_MDIO_OFFSET,
294 .ctrl_ram_size = DM646X_EMAC_CNTRL_RAM_SIZE,
295 .version = EMAC_VERSION_2,
296};
297
298static struct resource dm646x_emac_resources[] = {
299 {
300 .start = DM646X_EMAC_BASE,
301 .end = DM646X_EMAC_BASE + 0x47ff,
302 .flags = IORESOURCE_MEM,
303 },
304 {
305 .start = IRQ_DM646X_EMACRXTHINT,
306 .end = IRQ_DM646X_EMACRXTHINT,
307 .flags = IORESOURCE_IRQ,
308 },
309 {
310 .start = IRQ_DM646X_EMACRXINT,
311 .end = IRQ_DM646X_EMACRXINT,
312 .flags = IORESOURCE_IRQ,
313 },
314 {
315 .start = IRQ_DM646X_EMACTXINT,
316 .end = IRQ_DM646X_EMACTXINT,
317 .flags = IORESOURCE_IRQ,
318 },
319 {
320 .start = IRQ_DM646X_EMACMISCINT,
321 .end = IRQ_DM646X_EMACMISCINT,
322 .flags = IORESOURCE_IRQ,
323 },
324};
325
326static struct platform_device dm646x_emac_device = {
327 .name = "davinci_emac",
328 .id = 1,
329 .dev = {
330 .platform_data = &dm646x_emac_pdata,
331 },
332 .num_resources = ARRAY_SIZE(dm646x_emac_resources),
333 .resource = dm646x_emac_resources,
334};
335
336#define PINMUX0 0x00
337#define PINMUX1 0x04
338
339/*
340 * Device specific mux setup
341 *
342 * soc description mux mode mode mux dbg
343 * reg offset mask mode
344 */
345static const struct mux_config dm646x_pins[] = {
346#ifdef CONFIG_DAVINCI_MUX
347MUX_CFG(DM646X, ATAEN, 0, 0, 1, 1, true)
348
349MUX_CFG(DM646X, AUDCK1, 0, 29, 1, 0, false)
350
351MUX_CFG(DM646X, AUDCK0, 0, 28, 1, 0, false)
352
353MUX_CFG(DM646X, CRGMUX, 0, 24, 7, 5, true)
354
355MUX_CFG(DM646X, STSOMUX_DISABLE, 0, 22, 3, 0, true)
356
357MUX_CFG(DM646X, STSIMUX_DISABLE, 0, 20, 3, 0, true)
358
359MUX_CFG(DM646X, PTSOMUX_DISABLE, 0, 18, 3, 0, true)
360
361MUX_CFG(DM646X, PTSIMUX_DISABLE, 0, 16, 3, 0, true)
362
363MUX_CFG(DM646X, STSOMUX, 0, 22, 3, 2, true)
364
365MUX_CFG(DM646X, STSIMUX, 0, 20, 3, 2, true)
366
367MUX_CFG(DM646X, PTSOMUX_PARALLEL, 0, 18, 3, 2, true)
368
369MUX_CFG(DM646X, PTSIMUX_PARALLEL, 0, 16, 3, 2, true)
370
371MUX_CFG(DM646X, PTSOMUX_SERIAL, 0, 18, 3, 3, true)
372
373MUX_CFG(DM646X, PTSIMUX_SERIAL, 0, 16, 3, 3, true)
374#endif
375};
376
377static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
378 [IRQ_DM646X_VP_VERTINT0] = 7,
379 [IRQ_DM646X_VP_VERTINT1] = 7,
380 [IRQ_DM646X_VP_VERTINT2] = 7,
381 [IRQ_DM646X_VP_VERTINT3] = 7,
382 [IRQ_DM646X_VP_ERRINT] = 7,
383 [IRQ_DM646X_RESERVED_1] = 7,
384 [IRQ_DM646X_RESERVED_2] = 7,
385 [IRQ_DM646X_WDINT] = 7,
386 [IRQ_DM646X_CRGENINT0] = 7,
387 [IRQ_DM646X_CRGENINT1] = 7,
388 [IRQ_DM646X_TSIFINT0] = 7,
389 [IRQ_DM646X_TSIFINT1] = 7,
390 [IRQ_DM646X_VDCEINT] = 7,
391 [IRQ_DM646X_USBINT] = 7,
392 [IRQ_DM646X_USBDMAINT] = 7,
393 [IRQ_DM646X_PCIINT] = 7,
394 [IRQ_CCINT0] = 7, /* dma */
395 [IRQ_CCERRINT] = 7, /* dma */
396 [IRQ_TCERRINT0] = 7, /* dma */
397 [IRQ_TCERRINT] = 7, /* dma */
398 [IRQ_DM646X_TCERRINT2] = 7,
399 [IRQ_DM646X_TCERRINT3] = 7,
400 [IRQ_DM646X_IDE] = 7,
401 [IRQ_DM646X_HPIINT] = 7,
402 [IRQ_DM646X_EMACRXTHINT] = 7,
403 [IRQ_DM646X_EMACRXINT] = 7,
404 [IRQ_DM646X_EMACTXINT] = 7,
405 [IRQ_DM646X_EMACMISCINT] = 7,
406 [IRQ_DM646X_MCASP0TXINT] = 7,
407 [IRQ_DM646X_MCASP0RXINT] = 7,
408 [IRQ_AEMIFINT] = 7,
409 [IRQ_DM646X_RESERVED_3] = 7,
410 [IRQ_DM646X_MCASP1TXINT] = 7, /* clockevent */
411 [IRQ_TINT0_TINT34] = 7, /* clocksource */
412 [IRQ_TINT1_TINT12] = 7, /* DSP timer */
413 [IRQ_TINT1_TINT34] = 7, /* system tick */
414 [IRQ_PWMINT0] = 7,
415 [IRQ_PWMINT1] = 7,
416 [IRQ_DM646X_VLQINT] = 7,
417 [IRQ_I2C] = 7,
418 [IRQ_UARTINT0] = 7,
419 [IRQ_UARTINT1] = 7,
420 [IRQ_DM646X_UARTINT2] = 7,
421 [IRQ_DM646X_SPINT0] = 7,
422 [IRQ_DM646X_SPINT1] = 7,
423 [IRQ_DM646X_DSP2ARMINT] = 7,
424 [IRQ_DM646X_RESERVED_4] = 7,
425 [IRQ_DM646X_PSCINT] = 7,
426 [IRQ_DM646X_GPIO0] = 7,
427 [IRQ_DM646X_GPIO1] = 7,
428 [IRQ_DM646X_GPIO2] = 7,
429 [IRQ_DM646X_GPIO3] = 7,
430 [IRQ_DM646X_GPIO4] = 7,
431 [IRQ_DM646X_GPIO5] = 7,
432 [IRQ_DM646X_GPIO6] = 7,
433 [IRQ_DM646X_GPIO7] = 7,
434 [IRQ_DM646X_GPIOBNK0] = 7,
435 [IRQ_DM646X_GPIOBNK1] = 7,
436 [IRQ_DM646X_GPIOBNK2] = 7,
437 [IRQ_DM646X_DDRINT] = 7,
438 [IRQ_DM646X_AEMIFINT] = 7,
439 [IRQ_COMMTX] = 7,
440 [IRQ_COMMRX] = 7,
441 [IRQ_EMUINT] = 7,
442};
443
444/*----------------------------------------------------------------------*/
445
446static const s8 dma_chan_dm646x_no_event[] = {
447 0, 1, 2, 3, 13,
448 14, 15, 24, 25, 26,
449 27, 30, 31, 54, 55,
450 56,
451 -1
452};
453
454static struct edma_soc_info dm646x_edma_info = {
455 .n_channel = 64,
456 .n_region = 6, /* 0-1, 4-7 */
457 .n_slot = 512,
458 .n_tc = 4,
459 .noevent = dma_chan_dm646x_no_event,
460};
461
462static struct resource edma_resources[] = {
463 {
464 .name = "edma_cc",
465 .start = 0x01c00000,
466 .end = 0x01c00000 + SZ_64K - 1,
467 .flags = IORESOURCE_MEM,
468 },
469 {
470 .name = "edma_tc0",
471 .start = 0x01c10000,
472 .end = 0x01c10000 + SZ_1K - 1,
473 .flags = IORESOURCE_MEM,
474 },
475 {
476 .name = "edma_tc1",
477 .start = 0x01c10400,
478 .end = 0x01c10400 + SZ_1K - 1,
479 .flags = IORESOURCE_MEM,
480 },
481 {
482 .name = "edma_tc2",
483 .start = 0x01c10800,
484 .end = 0x01c10800 + SZ_1K - 1,
485 .flags = IORESOURCE_MEM,
486 },
487 {
488 .name = "edma_tc3",
489 .start = 0x01c10c00,
490 .end = 0x01c10c00 + SZ_1K - 1,
491 .flags = IORESOURCE_MEM,
492 },
493 {
494 .start = IRQ_CCINT0,
495 .flags = IORESOURCE_IRQ,
496 },
497 {
498 .start = IRQ_CCERRINT,
499 .flags = IORESOURCE_IRQ,
500 },
501 /* not using TC*_ERR */
502};
503
504static struct platform_device dm646x_edma_device = {
505 .name = "edma",
506 .id = -1,
507 .dev.platform_data = &dm646x_edma_info,
508 .num_resources = ARRAY_SIZE(edma_resources),
509 .resource = edma_resources,
510};
511
512/*----------------------------------------------------------------------*/
513
514static struct map_desc dm646x_io_desc[] = {
515 {
516 .virtual = IO_VIRT,
517 .pfn = __phys_to_pfn(IO_PHYS),
518 .length = IO_SIZE,
519 .type = MT_DEVICE
520 },
521 {
522 .virtual = SRAM_VIRT,
523 .pfn = __phys_to_pfn(0x00010000),
524 .length = SZ_32K,
525 /* MT_MEMORY_NONCACHED requires supersection alignment */
526 .type = MT_DEVICE,
527 },
528};
529
530/* Contents of JTAG ID register used to identify exact cpu type */
531static struct davinci_id dm646x_ids[] = {
532 {
533 .variant = 0x0,
534 .part_no = 0xb770,
535 .manufacturer = 0x017,
536 .cpu_id = DAVINCI_CPU_ID_DM6467,
537 .name = "dm6467",
538 },
539};
540
541static void __iomem *dm646x_psc_bases[] = {
542 IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
543};
544
545/*
546 * T0_BOT: Timer 0, bottom: clockevent source for hrtimers
547 * T0_TOP: Timer 0, top : clocksource for generic timekeeping
548 * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
549 * T1_TOP: Timer 1, top : <unused>
550 */
551struct davinci_timer_info dm646x_timer_info = {
552 .timers = davinci_timer_instance,
553 .clockevent_id = T0_BOT,
554 .clocksource_id = T0_TOP,
555};
556
557static struct plat_serial8250_port dm646x_serial_platform_data[] = {
558 {
559 .mapbase = DAVINCI_UART0_BASE,
560 .irq = IRQ_UARTINT0,
561 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
562 UPF_IOREMAP,
563 .iotype = UPIO_MEM32,
564 .regshift = 2,
565 },
566 {
567 .mapbase = DAVINCI_UART1_BASE,
568 .irq = IRQ_UARTINT1,
569 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
570 UPF_IOREMAP,
571 .iotype = UPIO_MEM32,
572 .regshift = 2,
573 },
574 {
575 .mapbase = DAVINCI_UART2_BASE,
576 .irq = IRQ_DM646X_UARTINT2,
577 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
578 UPF_IOREMAP,
579 .iotype = UPIO_MEM32,
580 .regshift = 2,
581 },
582 {
583 .flags = 0
584 },
585};
586
587static struct platform_device dm646x_serial_device = {
588 .name = "serial8250",
589 .id = PLAT8250_DEV_PLATFORM,
590 .dev = {
591 .platform_data = dm646x_serial_platform_data,
592 },
593};
594
595static struct davinci_soc_info davinci_soc_info_dm646x = {
596 .io_desc = dm646x_io_desc,
597 .io_desc_num = ARRAY_SIZE(dm646x_io_desc),
598 .jtag_id_base = IO_ADDRESS(0x01c40028),
599 .ids = dm646x_ids,
600 .ids_num = ARRAY_SIZE(dm646x_ids),
601 .cpu_clks = dm646x_clks,
602 .psc_bases = dm646x_psc_bases,
603 .psc_bases_num = ARRAY_SIZE(dm646x_psc_bases),
604 .pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
605 .pinmux_pins = dm646x_pins,
606 .pinmux_pins_num = ARRAY_SIZE(dm646x_pins),
607 .intc_base = IO_ADDRESS(DAVINCI_ARM_INTC_BASE),
608 .intc_type = DAVINCI_INTC_TYPE_AINTC,
609 .intc_irq_prios = dm646x_default_priorities,
610 .intc_irq_num = DAVINCI_N_AINTC_IRQ,
611 .timer_info = &dm646x_timer_info,
612 .wdt_base = IO_ADDRESS(DAVINCI_WDOG_BASE),
613 .gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE),
614 .gpio_num = 43, /* Only 33 usable */
615 .gpio_irq = IRQ_DM646X_GPIOBNK0,
616 .serial_dev = &dm646x_serial_device,
617 .emac_pdata = &dm646x_emac_pdata,
618 .sram_dma = 0x10010000,
619 .sram_len = SZ_32K,
620};
621
622void __init dm646x_init(void)
623{
624 davinci_common_init(&davinci_soc_info_dm646x);
625}
626
627static int __init dm646x_init_devices(void)
628{
629 if (!cpu_is_davinci_dm646x())
630 return 0;
631
632 platform_device_register(&dm646x_edma_device);
633 platform_device_register(&dm646x_emac_device);
634 return 0;
635}
636postcore_initcall(dm646x_init_devices);
diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c
index 1aba41c6351..1b6532159c5 100644
--- a/arch/arm/mach-davinci/gpio.c
+++ b/arch/arm/mach-davinci/gpio.c
@@ -23,6 +23,7 @@
23#include <mach/cputype.h> 23#include <mach/cputype.h>
24#include <mach/irqs.h> 24#include <mach/irqs.h>
25#include <mach/hardware.h> 25#include <mach/hardware.h>
26#include <mach/common.h>
26#include <mach/gpio.h> 27#include <mach/gpio.h>
27 28
28#include <asm/mach/irq.h> 29#include <asm/mach/irq.h>
@@ -37,14 +38,13 @@ struct davinci_gpio {
37 38
38static struct davinci_gpio chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)]; 39static struct davinci_gpio chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];
39 40
40static unsigned __initdata ngpio;
41
42/* create a non-inlined version */ 41/* create a non-inlined version */
43static struct gpio_controller __iomem * __init gpio2controller(unsigned gpio) 42static struct gpio_controller __iomem * __init gpio2controller(unsigned gpio)
44{ 43{
45 return __gpio_to_controller(gpio); 44 return __gpio_to_controller(gpio);
46} 45}
47 46
47static int __init davinci_gpio_irq_setup(void);
48 48
49/*--------------------------------------------------------------------------*/ 49/*--------------------------------------------------------------------------*/
50 50
@@ -115,23 +115,16 @@ davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
115static int __init davinci_gpio_setup(void) 115static int __init davinci_gpio_setup(void)
116{ 116{
117 int i, base; 117 int i, base;
118 unsigned ngpio;
119 struct davinci_soc_info *soc_info = &davinci_soc_info;
118 120
119 /* The gpio banks conceptually expose a segmented bitmap, 121 /*
122 * The gpio banks conceptually expose a segmented bitmap,
120 * and "ngpio" is one more than the largest zero-based 123 * and "ngpio" is one more than the largest zero-based
121 * bit index that's valid. 124 * bit index that's valid.
122 */ 125 */
123 if (cpu_is_davinci_dm355()) { /* or dm335() */ 126 ngpio = soc_info->gpio_num;
124 ngpio = 104; 127 if (ngpio == 0) {
125 } else if (cpu_is_davinci_dm644x()) { /* or dm337() */
126 ngpio = 71;
127 } else if (cpu_is_davinci_dm646x()) {
128 /* NOTE: each bank has several "reserved" bits,
129 * unusable as GPIOs. Only 33 of the GPIO numbers
130 * are usable, and we're not rejecting the others.
131 */
132 ngpio = 43;
133 } else {
134 /* if cpu_is_davinci_dm643x() ngpio = 111 */
135 pr_err("GPIO setup: how many GPIOs?\n"); 128 pr_err("GPIO setup: how many GPIOs?\n");
136 return -EINVAL; 129 return -EINVAL;
137 } 130 }
@@ -157,6 +150,7 @@ static int __init davinci_gpio_setup(void)
157 gpiochip_add(&chips[i].chip); 150 gpiochip_add(&chips[i].chip);
158 } 151 }
159 152
153 davinci_gpio_irq_setup();
160 return 0; 154 return 0;
161} 155}
162pure_initcall(davinci_gpio_setup); 156pure_initcall(davinci_gpio_setup);
@@ -187,10 +181,15 @@ static void gpio_irq_enable(unsigned irq)
187{ 181{
188 struct gpio_controller *__iomem g = get_irq_chip_data(irq); 182 struct gpio_controller *__iomem g = get_irq_chip_data(irq);
189 u32 mask = __gpio_mask(irq_to_gpio(irq)); 183 u32 mask = __gpio_mask(irq_to_gpio(irq));
184 unsigned status = irq_desc[irq].status;
185
186 status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
187 if (!status)
188 status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
190 189
191 if (irq_desc[irq].status & IRQ_TYPE_EDGE_FALLING) 190 if (status & IRQ_TYPE_EDGE_FALLING)
192 __raw_writel(mask, &g->set_falling); 191 __raw_writel(mask, &g->set_falling);
193 if (irq_desc[irq].status & IRQ_TYPE_EDGE_RISING) 192 if (status & IRQ_TYPE_EDGE_RISING)
194 __raw_writel(mask, &g->set_rising); 193 __raw_writel(mask, &g->set_rising);
195} 194}
196 195
@@ -205,10 +204,13 @@ static int gpio_irq_type(unsigned irq, unsigned trigger)
205 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK; 204 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
206 irq_desc[irq].status |= trigger; 205 irq_desc[irq].status |= trigger;
207 206
208 __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING) 207 /* don't enable the IRQ if it's currently disabled */
209 ? &g->set_falling : &g->clr_falling); 208 if (irq_desc[irq].depth == 0) {
210 __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING) 209 __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
211 ? &g->set_rising : &g->clr_rising); 210 ? &g->set_falling : &g->clr_falling);
211 __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING)
212 ? &g->set_rising : &g->clr_rising);
213 }
212 return 0; 214 return 0;
213} 215}
214 216
@@ -230,6 +232,7 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc)
230 mask <<= 16; 232 mask <<= 16;
231 233
232 /* temporarily mask (level sensitive) parent IRQ */ 234 /* temporarily mask (level sensitive) parent IRQ */
235 desc->chip->mask(irq);
233 desc->chip->ack(irq); 236 desc->chip->ack(irq);
234 while (1) { 237 while (1) {
235 u32 status; 238 u32 status;
@@ -268,17 +271,15 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc)
268static int __init davinci_gpio_irq_setup(void) 271static int __init davinci_gpio_irq_setup(void)
269{ 272{
270 unsigned gpio, irq, bank; 273 unsigned gpio, irq, bank;
271 unsigned bank_irq;
272 struct clk *clk; 274 struct clk *clk;
273 u32 binten = 0; 275 u32 binten = 0;
276 unsigned ngpio, bank_irq;
277 struct davinci_soc_info *soc_info = &davinci_soc_info;
278
279 ngpio = soc_info->gpio_num;
274 280
275 if (cpu_is_davinci_dm355()) { /* or dm335() */ 281 bank_irq = soc_info->gpio_irq;
276 bank_irq = IRQ_DM355_GPIOBNK0; 282 if (bank_irq == 0) {
277 } else if (cpu_is_davinci_dm644x()) {
278 bank_irq = IRQ_GPIOBNK0;
279 } else if (cpu_is_davinci_dm646x()) {
280 bank_irq = IRQ_DM646X_GPIOBNK0;
281 } else {
282 printk(KERN_ERR "Don't know first GPIO bank IRQ.\n"); 283 printk(KERN_ERR "Don't know first GPIO bank IRQ.\n");
283 return -EINVAL; 284 return -EINVAL;
284 } 285 }
@@ -318,11 +319,9 @@ static int __init davinci_gpio_irq_setup(void)
318 /* BINTEN -- per-bank interrupt enable. genirq would also let these 319 /* BINTEN -- per-bank interrupt enable. genirq would also let these
319 * bits be set/cleared dynamically. 320 * bits be set/cleared dynamically.
320 */ 321 */
321 __raw_writel(binten, (void *__iomem) 322 __raw_writel(binten, soc_info->gpio_base + 0x08);
322 IO_ADDRESS(DAVINCI_GPIO_BASE + 0x08));
323 323
324 printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0)); 324 printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0));
325 325
326 return 0; 326 return 0;
327} 327}
328arch_initcall(davinci_gpio_irq_setup);
diff --git a/arch/arm/mach-davinci/id.c b/arch/arm/mach-davinci/id.c
deleted file mode 100644
index 018b994cd79..00000000000
--- a/arch/arm/mach-davinci/id.c
+++ /dev/null
@@ -1,116 +0,0 @@
1/*
2 * Davinci CPU identification code
3 *
4 * Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com>
5 *
6 * Derived from OMAP1 CPU identification code.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/io.h>
17
18#define JTAG_ID_BASE IO_ADDRESS(0x01c40028)
19
20static unsigned int davinci_revision;
21
22struct davinci_id {
23 u8 variant; /* JTAG ID bits 31:28 */
24 u16 part_no; /* JTAG ID bits 27:12 */
25 u32 manufacturer; /* JTAG ID bits 11:1 */
26 u32 type; /* Cpu id bits [31:8], cpu class bits [7:0] */
27};
28
29/* Register values to detect the DaVinci version */
30static struct davinci_id davinci_ids[] __initdata = {
31 {
32 /* DM6446 */
33 .part_no = 0xb700,
34 .variant = 0x0,
35 .manufacturer = 0x017,
36 .type = 0x64460000,
37 },
38 {
39 /* DM646X */
40 .part_no = 0xb770,
41 .variant = 0x0,
42 .manufacturer = 0x017,
43 .type = 0x64670000,
44 },
45 {
46 /* DM355 */
47 .part_no = 0xb73b,
48 .variant = 0x0,
49 .manufacturer = 0x00f,
50 .type = 0x03550000,
51 },
52};
53
54/*
55 * Get Device Part No. from JTAG ID register
56 */
57static u16 __init davinci_get_part_no(void)
58{
59 u32 dev_id, part_no;
60
61 dev_id = __raw_readl(JTAG_ID_BASE);
62
63 part_no = ((dev_id >> 12) & 0xffff);
64
65 return part_no;
66}
67
68/*
69 * Get Device Revision from JTAG ID register
70 */
71static u8 __init davinci_get_variant(void)
72{
73 u32 variant;
74
75 variant = __raw_readl(JTAG_ID_BASE);
76
77 variant = (variant >> 28) & 0xf;
78
79 return variant;
80}
81
82unsigned int davinci_rev(void)
83{
84 return davinci_revision >> 16;
85}
86EXPORT_SYMBOL(davinci_rev);
87
88void __init davinci_check_revision(void)
89{
90 int i;
91 u16 part_no;
92 u8 variant;
93
94 part_no = davinci_get_part_no();
95 variant = davinci_get_variant();
96
97 /* First check only the major version in a safe way */
98 for (i = 0; i < ARRAY_SIZE(davinci_ids); i++) {
99 if (part_no == (davinci_ids[i].part_no)) {
100 davinci_revision = davinci_ids[i].type;
101 break;
102 }
103 }
104
105 /* Check if we can find the dev revision */
106 for (i = 0; i < ARRAY_SIZE(davinci_ids); i++) {
107 if (part_no == davinci_ids[i].part_no &&
108 variant == davinci_ids[i].variant) {
109 davinci_revision = davinci_ids[i].type;
110 break;
111 }
112 }
113
114 printk(KERN_INFO "DaVinci DM%04x variant 0x%x\n",
115 davinci_rev(), variant);
116}
diff --git a/arch/arm/mach-davinci/include/mach/board-dm6446evm.h b/arch/arm/mach-davinci/include/mach/board-dm6446evm.h
deleted file mode 100644
index 3216f21c123..00000000000
--- a/arch/arm/mach-davinci/include/mach/board-dm6446evm.h
+++ /dev/null
@@ -1,20 +0,0 @@
1/*
2 * DaVinci DM6446 EVM board specific headers
3 *
4 * Author: Kevin Hilman, Deep Root Systems, LLC
5 *
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or ifndef.
10 */
11
12#ifndef _MACH_DAVINCI_DM6446EVM_H
13#define _MACH_DAVINCI_DM6446EVM_H
14
15#include <linux/types.h>
16
17int dm6446evm_eeprom_read(char *buf, off_t off, size_t count);
18int dm6446evm_eeprom_write(char *buf, off_t off, size_t count);
19
20#endif
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index 19177097625..a1f03b606d8 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -17,7 +17,8 @@ struct sys_timer;
17extern struct sys_timer davinci_timer; 17extern struct sys_timer davinci_timer;
18 18
19extern void davinci_irq_init(void); 19extern void davinci_irq_init(void);
20extern void davinci_map_common_io(void); 20extern void __iomem *davinci_intc_base;
21extern int davinci_intc_type;
21 22
22/* parameters describe VBUS sourcing for host mode */ 23/* parameters describe VBUS sourcing for host mode */
23extern void setup_usb(unsigned mA, unsigned potpgt_msec); 24extern void setup_usb(unsigned mA, unsigned potpgt_msec);
@@ -25,4 +26,56 @@ extern void setup_usb(unsigned mA, unsigned potpgt_msec);
25/* parameters describe VBUS sourcing for host mode */ 26/* parameters describe VBUS sourcing for host mode */
26extern void setup_usb(unsigned mA, unsigned potpgt_msec); 27extern void setup_usb(unsigned mA, unsigned potpgt_msec);
27 28
29struct davinci_timer_instance {
30 void __iomem *base;
31 u32 bottom_irq;
32 u32 top_irq;
33 unsigned long cmp_off;
34 unsigned int cmp_irq;
35};
36
37struct davinci_timer_info {
38 struct davinci_timer_instance *timers;
39 unsigned int clockevent_id;
40 unsigned int clocksource_id;
41};
42
43/* SoC specific init support */
44struct davinci_soc_info {
45 struct map_desc *io_desc;
46 unsigned long io_desc_num;
47 u32 cpu_id;
48 u32 jtag_id;
49 void __iomem *jtag_id_base;
50 struct davinci_id *ids;
51 unsigned long ids_num;
52 struct davinci_clk *cpu_clks;
53 void __iomem **psc_bases;
54 unsigned long psc_bases_num;
55 void __iomem *pinmux_base;
56 const struct mux_config *pinmux_pins;
57 unsigned long pinmux_pins_num;
58 void __iomem *intc_base;
59 int intc_type;
60 u8 *intc_irq_prios;
61 unsigned long intc_irq_num;
62 struct davinci_timer_info *timer_info;
63 void __iomem *wdt_base;
64 void __iomem *gpio_base;
65 unsigned gpio_num;
66 unsigned gpio_irq;
67 struct platform_device *serial_dev;
68 struct emac_platform_data *emac_pdata;
69 dma_addr_t sram_dma;
70 unsigned sram_len;
71};
72
73extern struct davinci_soc_info davinci_soc_info;
74
75extern void davinci_common_init(struct davinci_soc_info *soc_info);
76
77/* standard place to map on-chip SRAMs; they *may* support DMA */
78#define SRAM_VIRT 0xfffe0000
79#define SRAM_SIZE SZ_128K
80
28#endif /* __ARCH_ARM_MACH_DAVINCI_COMMON_H */ 81#endif /* __ARCH_ARM_MACH_DAVINCI_COMMON_H */
diff --git a/arch/arm/mach-davinci/include/mach/cp_intc.h b/arch/arm/mach-davinci/include/mach/cp_intc.h
new file mode 100644
index 00000000000..c4d27eec806
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/cp_intc.h
@@ -0,0 +1,57 @@
1/*
2 * TI Common Platform Interrupt Controller (cp_intc) definitions
3 *
4 * Author: Steve Chen <schen@mvista.com>
5 * Copyright (C) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11#ifndef __ASM_HARDWARE_CP_INTC_H
12#define __ASM_HARDWARE_CP_INTC_H
13
14#define CP_INTC_REV 0x00
15#define CP_INTC_CTRL 0x04
16#define CP_INTC_HOST_CTRL 0x0C
17#define CP_INTC_GLOBAL_ENABLE 0x10
18#define CP_INTC_GLOBAL_NESTING_LEVEL 0x1C
19#define CP_INTC_SYS_STAT_IDX_SET 0x20
20#define CP_INTC_SYS_STAT_IDX_CLR 0x24
21#define CP_INTC_SYS_ENABLE_IDX_SET 0x28
22#define CP_INTC_SYS_ENABLE_IDX_CLR 0x2C
23#define CP_INTC_GLOBAL_WAKEUP_ENABLE 0x30
24#define CP_INTC_HOST_ENABLE_IDX_SET 0x34
25#define CP_INTC_HOST_ENABLE_IDX_CLR 0x38
26#define CP_INTC_PACING_PRESCALE 0x40
27#define CP_INTC_VECTOR_BASE 0x50
28#define CP_INTC_VECTOR_SIZE 0x54
29#define CP_INTC_VECTOR_NULL 0x58
30#define CP_INTC_PRIO_IDX 0x80
31#define CP_INTC_PRIO_VECTOR 0x84
32#define CP_INTC_SECURE_ENABLE 0x90
33#define CP_INTC_SECURE_PRIO_IDX 0x94
34#define CP_INTC_PACING_PARAM(n) (0x0100 + (n << 4))
35#define CP_INTC_PACING_DEC(n) (0x0104 + (n << 4))
36#define CP_INTC_PACING_MAP(n) (0x0108 + (n << 4))
37#define CP_INTC_SYS_RAW_STAT(n) (0x0200 + (n << 2))
38#define CP_INTC_SYS_STAT_CLR(n) (0x0280 + (n << 2))
39#define CP_INTC_SYS_ENABLE_SET(n) (0x0300 + (n << 2))
40#define CP_INTC_SYS_ENABLE_CLR(n) (0x0380 + (n << 2))
41#define CP_INTC_CHAN_MAP(n) (0x0400 + (n << 2))
42#define CP_INTC_HOST_MAP(n) (0x0800 + (n << 2))
43#define CP_INTC_HOST_PRIO_IDX(n) (0x0900 + (n << 2))
44#define CP_INTC_SYS_POLARITY(n) (0x0D00 + (n << 2))
45#define CP_INTC_SYS_TYPE(n) (0x0D80 + (n << 2))
46#define CP_INTC_WAKEUP_ENABLE(n) (0x0E00 + (n << 2))
47#define CP_INTC_DEBUG_SELECT(n) (0x0F00 + (n << 2))
48#define CP_INTC_SYS_SECURE_ENABLE(n) (0x1000 + (n << 2))
49#define CP_INTC_HOST_NESTING_LEVEL(n) (0x1100 + (n << 2))
50#define CP_INTC_HOST_ENABLE(n) (0x1500 + (n << 2))
51#define CP_INTC_HOST_PRIO_VECTOR(n) (0x1600 + (n << 2))
52#define CP_INTC_VECTOR_ADDR(n) (0x2000 + (n << 2))
53
54void __init cp_intc_init(void __iomem *base, unsigned short num_irq,
55 u8 *irq_prio);
56
57#endif /* __ASM_HARDWARE_CP_INTC_H */
diff --git a/arch/arm/mach-davinci/include/mach/cputype.h b/arch/arm/mach-davinci/include/mach/cputype.h
index 27cfb1b3a66..d12a5ed2959 100644
--- a/arch/arm/mach-davinci/include/mach/cputype.h
+++ b/arch/arm/mach-davinci/include/mach/cputype.h
@@ -16,17 +16,30 @@
16#ifndef _ASM_ARCH_CPU_H 16#ifndef _ASM_ARCH_CPU_H
17#define _ASM_ARCH_CPU_H 17#define _ASM_ARCH_CPU_H
18 18
19extern unsigned int davinci_rev(void); 19#include <mach/common.h>
20 20
21#define IS_DAVINCI_CPU(type, id) \ 21struct davinci_id {
22static inline int is_davinci_dm ##type(void) \ 22 u8 variant; /* JTAG ID bits 31:28 */
23{ \ 23 u16 part_no; /* JTAG ID bits 27:12 */
24 return (davinci_rev() == (id)) ? 1 : 0; \ 24 u16 manufacturer; /* JTAG ID bits 11:1 */
25 u32 cpu_id;
26 char *name;
27};
28
29/* Can use lower 16 bits of cpu id for a variant when required */
30#define DAVINCI_CPU_ID_DM6446 0x64460000
31#define DAVINCI_CPU_ID_DM6467 0x64670000
32#define DAVINCI_CPU_ID_DM355 0x03550000
33
34#define IS_DAVINCI_CPU(type, id) \
35static inline int is_davinci_ ##type(void) \
36{ \
37 return (davinci_soc_info.cpu_id == (id)); \
25} 38}
26 39
27IS_DAVINCI_CPU(644x, 0x6446) 40IS_DAVINCI_CPU(dm644x, DAVINCI_CPU_ID_DM6446)
28IS_DAVINCI_CPU(646x, 0x6467) 41IS_DAVINCI_CPU(dm646x, DAVINCI_CPU_ID_DM6467)
29IS_DAVINCI_CPU(355, 0x355) 42IS_DAVINCI_CPU(dm355, DAVINCI_CPU_ID_DM355)
30 43
31#ifdef CONFIG_ARCH_DAVINCI_DM644x 44#ifdef CONFIG_ARCH_DAVINCI_DM644x
32#define cpu_is_davinci_dm644x() is_davinci_dm644x() 45#define cpu_is_davinci_dm644x() is_davinci_dm644x()
diff --git a/arch/arm/mach-davinci/include/mach/debug-macro.S b/arch/arm/mach-davinci/include/mach/debug-macro.S
index e6c0f0d5d06..de3fc2182b4 100644
--- a/arch/arm/mach-davinci/include/mach/debug-macro.S
+++ b/arch/arm/mach-davinci/include/mach/debug-macro.S
@@ -9,6 +9,16 @@
9 * or implied. 9 * or implied.
10 */ 10 */
11 11
12/* Modifications
13 * Jan 2009 Chaithrika U S Added senduart, busyuart, waituart
14 * macros, based on debug-8250.S file
15 * but using 32-bit accesses required for
16 * some davinci devices.
17 */
18
19#include <linux/serial_reg.h>
20#define UART_SHIFT 2
21
12 .macro addruart, rx 22 .macro addruart, rx
13 mrc p15, 0, \rx, c1, c0 23 mrc p15, 0, \rx, c1, c0
14 tst \rx, #1 @ MMU enabled? 24 tst \rx, #1 @ MMU enabled?
@@ -17,5 +27,22 @@
17 orr \rx, \rx, #0x00c20000 @ UART 0 27 orr \rx, \rx, #0x00c20000 @ UART 0
18 .endm 28 .endm
19 29
20#define UART_SHIFT 2 30 .macro senduart,rd,rx
21#include <asm/hardware/debug-8250.S> 31 str \rd, [\rx, #UART_TX << UART_SHIFT]
32 .endm
33
34 .macro busyuart,rd,rx
351002: ldr \rd, [\rx, #UART_LSR << UART_SHIFT]
36 and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE
37 teq \rd, #UART_LSR_TEMT | UART_LSR_THRE
38 bne 1002b
39 .endm
40
41 .macro waituart,rd,rx
42#ifdef FLOW_CONTROL
431001: ldr \rd, [\rx, #UART_MSR << UART_SHIFT]
44 tst \rd, #UART_MSR_CTS
45 beq 1001b
46#endif
47 .endm
48
diff --git a/arch/arm/mach-davinci/include/mach/dm355.h b/arch/arm/mach-davinci/include/mach/dm355.h
new file mode 100644
index 00000000000..54903b72438
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/dm355.h
@@ -0,0 +1,22 @@
1/*
2 * Chip specific defines for DM355 SoC
3 *
4 * Author: Kevin Hilman, Deep Root Systems, LLC
5 *
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11#ifndef __ASM_ARCH_DM355_H
12#define __ASM_ARCH_DM355_H
13
14#include <mach/hardware.h>
15
16struct spi_board_info;
17
18void __init dm355_init(void);
19void dm355_init_spi0(unsigned chipselect_mask,
20 struct spi_board_info *info, unsigned len);
21
22#endif /* __ASM_ARCH_DM355_H */
diff --git a/arch/arm/mach-davinci/include/mach/dm644x.h b/arch/arm/mach-davinci/include/mach/dm644x.h
index 3dcb9f4e58b..15d42b92a8c 100644
--- a/arch/arm/mach-davinci/include/mach/dm644x.h
+++ b/arch/arm/mach-davinci/include/mach/dm644x.h
@@ -24,6 +24,7 @@
24 24
25#include <linux/platform_device.h> 25#include <linux/platform_device.h>
26#include <mach/hardware.h> 26#include <mach/hardware.h>
27#include <mach/emac.h>
27 28
28#define DM644X_EMAC_BASE (0x01C80000) 29#define DM644X_EMAC_BASE (0x01C80000)
29#define DM644X_EMAC_CNTRL_OFFSET (0x0000) 30#define DM644X_EMAC_CNTRL_OFFSET (0x0000)
diff --git a/arch/arm/mach-davinci/include/mach/dm646x.h b/arch/arm/mach-davinci/include/mach/dm646x.h
new file mode 100644
index 00000000000..1fc764c8646
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/dm646x.h
@@ -0,0 +1,26 @@
1/*
2 * Chip specific defines for DM646x SoC
3 *
4 * Author: Kevin Hilman, Deep Root Systems, LLC
5 *
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11#ifndef __ASM_ARCH_DM646X_H
12#define __ASM_ARCH_DM646X_H
13
14#include <mach/hardware.h>
15#include <mach/emac.h>
16
17#define DM646X_EMAC_BASE (0x01C80000)
18#define DM646X_EMAC_CNTRL_OFFSET (0x0000)
19#define DM646X_EMAC_CNTRL_MOD_OFFSET (0x1000)
20#define DM646X_EMAC_CNTRL_RAM_OFFSET (0x2000)
21#define DM646X_EMAC_MDIO_OFFSET (0x4000)
22#define DM646X_EMAC_CNTRL_RAM_SIZE (0x2000)
23
24void __init dm646x_init(void);
25
26#endif /* __ASM_ARCH_DM646X_H */
diff --git a/arch/arm/mach-davinci/include/mach/edma.h b/arch/arm/mach-davinci/include/mach/edma.h
index f6fc5396daf..24a379239d7 100644
--- a/arch/arm/mach-davinci/include/mach/edma.h
+++ b/arch/arm/mach-davinci/include/mach/edma.h
@@ -208,10 +208,6 @@ void edma_clear_event(unsigned channel);
208void edma_pause(unsigned channel); 208void edma_pause(unsigned channel);
209void edma_resume(unsigned channel); 209void edma_resume(unsigned channel);
210 210
211/* UNRELATED TO DMA */
212int davinci_alloc_iram(unsigned size);
213void davinci_free_iram(unsigned addr, unsigned size);
214
215/* platform_data for EDMA driver */ 211/* platform_data for EDMA driver */
216struct edma_soc_info { 212struct edma_soc_info {
217 213
diff --git a/arch/arm/mach-davinci/include/mach/emac.h b/arch/arm/mach-davinci/include/mach/emac.h
new file mode 100644
index 00000000000..beff4fb7c84
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/emac.h
@@ -0,0 +1,36 @@
1/*
2 * TI DaVinci EMAC platform support
3 *
4 * Author: Kevin Hilman, Deep Root Systems, LLC
5 *
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11#ifndef _MACH_DAVINCI_EMAC_H
12#define _MACH_DAVINCI_EMAC_H
13
14#include <linux/if_ether.h>
15#include <linux/memory.h>
16
17struct emac_platform_data {
18 char mac_addr[ETH_ALEN];
19 u32 ctrl_reg_offset;
20 u32 ctrl_mod_reg_offset;
21 u32 ctrl_ram_offset;
22 u32 mdio_reg_offset;
23 u32 ctrl_ram_size;
24 u32 phy_mask;
25 u32 mdio_max_freq;
26 u8 rmii_en;
27 u8 version;
28};
29
30enum {
31 EMAC_VERSION_1, /* DM644x */
32 EMAC_VERSION_2, /* DM646x */
33};
34
35void davinci_get_mac_addr(struct memory_accessor *mem_acc, void *context);
36#endif
diff --git a/arch/arm/mach-davinci/include/mach/entry-macro.S b/arch/arm/mach-davinci/include/mach/entry-macro.S
index 039b84f933b..fbdebc7cb40 100644
--- a/arch/arm/mach-davinci/include/mach/entry-macro.S
+++ b/arch/arm/mach-davinci/include/mach/entry-macro.S
@@ -15,17 +15,36 @@
15 .endm 15 .endm
16 16
17 .macro get_irqnr_preamble, base, tmp 17 .macro get_irqnr_preamble, base, tmp
18 ldr \base, =IO_ADDRESS(DAVINCI_ARM_INTC_BASE) 18 ldr \base, =davinci_intc_base
19 ldr \base, [\base]
19 .endm 20 .endm
20 21
21 .macro arch_ret_to_user, tmp1, tmp2 22 .macro arch_ret_to_user, tmp1, tmp2
22 .endm 23 .endm
23 24
24 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 25 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
26#if defined(CONFIG_AINTC) && defined(CONFIG_CP_INTC)
27 ldr \tmp, =davinci_intc_type
28 ldr \tmp, [\tmp]
29 cmp \tmp, #DAVINCI_INTC_TYPE_CP_INTC
30 beq 1001f
31#endif
32#if defined(CONFIG_AINTC)
25 ldr \tmp, [\base, #0x14] 33 ldr \tmp, [\base, #0x14]
26 mov \tmp, \tmp, lsr #2 34 movs \tmp, \tmp, lsr #2
27 sub \irqnr, \tmp, #1 35 sub \irqnr, \tmp, #1
28 cmp \tmp, #0 36 b 1002f
37#endif
38#if defined(CONFIG_CP_INTC)
391001: ldr \irqnr, [\base, #0x80] /* get irq number */
40 and \irqnr, \irqnr, #0xff /* irq is in bits 0-9 */
41 mov \tmp, \irqnr, lsr #3
42 and \tmp, \tmp, #0xfc
43 add \tmp, \tmp, #0x280 /* get the register offset */
44 ldr \irqstat, [\base, \tmp] /* get the intc status */
45 cmp \irqstat, #0x0
46#endif
471002:
29 .endm 48 .endm
30 49
31 .macro irq_prio_table 50 .macro irq_prio_table
diff --git a/arch/arm/mach-davinci/include/mach/gpio.h b/arch/arm/mach-davinci/include/mach/gpio.h
index efe3281364e..ae074556831 100644
--- a/arch/arm/mach-davinci/include/mach/gpio.h
+++ b/arch/arm/mach-davinci/include/mach/gpio.h
@@ -17,6 +17,7 @@
17#include <asm-generic/gpio.h> 17#include <asm-generic/gpio.h>
18 18
19#include <mach/irqs.h> 19#include <mach/irqs.h>
20#include <mach/common.h>
20 21
21#define DAVINCI_GPIO_BASE 0x01C67000 22#define DAVINCI_GPIO_BASE 0x01C67000
22 23
@@ -67,15 +68,16 @@ static inline struct gpio_controller *__iomem
67__gpio_to_controller(unsigned gpio) 68__gpio_to_controller(unsigned gpio)
68{ 69{
69 void *__iomem ptr; 70 void *__iomem ptr;
71 void __iomem *base = davinci_soc_info.gpio_base;
70 72
71 if (gpio < 32 * 1) 73 if (gpio < 32 * 1)
72 ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x10); 74 ptr = base + 0x10;
73 else if (gpio < 32 * 2) 75 else if (gpio < 32 * 2)
74 ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x38); 76 ptr = base + 0x38;
75 else if (gpio < 32 * 3) 77 else if (gpio < 32 * 3)
76 ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x60); 78 ptr = base + 0x60;
77 else if (gpio < 32 * 4) 79 else if (gpio < 32 * 4)
78 ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x88); 80 ptr = base + 0x88;
79 else 81 else
80 ptr = NULL; 82 ptr = NULL;
81 return ptr; 83 return ptr;
@@ -142,13 +144,13 @@ static inline int gpio_to_irq(unsigned gpio)
142{ 144{
143 if (gpio >= DAVINCI_N_GPIO) 145 if (gpio >= DAVINCI_N_GPIO)
144 return -EINVAL; 146 return -EINVAL;
145 return DAVINCI_N_AINTC_IRQ + gpio; 147 return davinci_soc_info.intc_irq_num + gpio;
146} 148}
147 149
148static inline int irq_to_gpio(unsigned irq) 150static inline int irq_to_gpio(unsigned irq)
149{ 151{
150 /* caller guarantees gpio_to_irq() succeeded */ 152 /* caller guarantees gpio_to_irq() succeeded */
151 return irq - DAVINCI_N_AINTC_IRQ; 153 return irq - davinci_soc_info.intc_irq_num;
152} 154}
153 155
154#endif /* __DAVINCI_GPIO_H */ 156#endif /* __DAVINCI_GPIO_H */
diff --git a/arch/arm/mach-davinci/include/mach/irqs.h b/arch/arm/mach-davinci/include/mach/irqs.h
index 18066074c99..bc5d6aaa69a 100644
--- a/arch/arm/mach-davinci/include/mach/irqs.h
+++ b/arch/arm/mach-davinci/include/mach/irqs.h
@@ -30,6 +30,9 @@
30/* Base address */ 30/* Base address */
31#define DAVINCI_ARM_INTC_BASE 0x01C48000 31#define DAVINCI_ARM_INTC_BASE 0x01C48000
32 32
33#define DAVINCI_INTC_TYPE_AINTC 0
34#define DAVINCI_INTC_TYPE_CP_INTC 1
35
33/* Interrupt lines */ 36/* Interrupt lines */
34#define IRQ_VDINT0 0 37#define IRQ_VDINT0 0
35#define IRQ_VDINT1 1 38#define IRQ_VDINT1 1
diff --git a/arch/arm/mach-davinci/include/mach/memory.h b/arch/arm/mach-davinci/include/mach/memory.h
index 86c25c7f3ce..c712c7cdf38 100644
--- a/arch/arm/mach-davinci/include/mach/memory.h
+++ b/arch/arm/mach-davinci/include/mach/memory.h
@@ -21,7 +21,6 @@
21 * Definitions 21 * Definitions
22 **************************************************************************/ 22 **************************************************************************/
23#define DAVINCI_DDR_BASE 0x80000000 23#define DAVINCI_DDR_BASE 0x80000000
24#define DAVINCI_IRAM_BASE 0x00008000 /* ARM Internal RAM */
25 24
26#define PHYS_OFFSET DAVINCI_DDR_BASE 25#define PHYS_OFFSET DAVINCI_DDR_BASE
27 26
diff --git a/arch/arm/mach-davinci/include/mach/mmc.h b/arch/arm/mach-davinci/include/mach/mmc.h
new file mode 100644
index 00000000000..5a85e24f367
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/mmc.h
@@ -0,0 +1,33 @@
1/*
2 * Board-specific MMC configuration
3 */
4
5#ifndef _DAVINCI_MMC_H
6#define _DAVINCI_MMC_H
7
8#include <linux/types.h>
9#include <linux/mmc/host.h>
10
11struct davinci_mmc_config {
12 /* get_cd()/get_wp() may sleep */
13 int (*get_cd)(int module);
14 int (*get_ro)(int module);
15 /* wires == 0 is equivalent to wires == 4 (4-bit parallel) */
16 u8 wires;
17
18 u32 max_freq;
19
20 /* any additional host capabilities: OR'd in to mmc->f_caps */
21 u32 caps;
22
23 /* Version of the MMC/SD controller */
24 u8 version;
25};
26void davinci_setup_mmc(int module, struct davinci_mmc_config *config);
27
28enum {
29 MMC_CTLR_VERSION_1 = 0, /* DM644x and DM355 */
30 MMC_CTLR_VERSION_2, /* DA830 */
31};
32
33#endif
diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h
index bae22cb3e27..27378458542 100644
--- a/arch/arm/mach-davinci/include/mach/mux.h
+++ b/arch/arm/mach-davinci/include/mach/mux.h
@@ -19,16 +19,6 @@
19#ifndef __INC_MACH_MUX_H 19#ifndef __INC_MACH_MUX_H
20#define __INC_MACH_MUX_H 20#define __INC_MACH_MUX_H
21 21
22/* System module registers */
23#define PINMUX0 0x00
24#define PINMUX1 0x04
25/* dm355 only */
26#define PINMUX2 0x08
27#define PINMUX3 0x0c
28#define PINMUX4 0x10
29#define INTMUX 0x18
30#define EVTMUX 0x1c
31
32struct mux_config { 22struct mux_config {
33 const char *name; 23 const char *name;
34 const char *mux_reg_name; 24 const char *mux_reg_name;
@@ -168,15 +158,9 @@ enum davinci_dm355_index {
168 158
169#ifdef CONFIG_DAVINCI_MUX 159#ifdef CONFIG_DAVINCI_MUX
170/* setup pin muxing */ 160/* setup pin muxing */
171extern void davinci_mux_init(void);
172extern int davinci_mux_register(const struct mux_config *pins,
173 unsigned long size);
174extern int davinci_cfg_reg(unsigned long reg_cfg); 161extern int davinci_cfg_reg(unsigned long reg_cfg);
175#else 162#else
176/* boot loader does it all (no warnings from CONFIG_DAVINCI_MUX_WARNINGS) */ 163/* boot loader does it all (no warnings from CONFIG_DAVINCI_MUX_WARNINGS) */
177static inline void davinci_mux_init(void) {}
178static inline int davinci_mux_register(const struct mux_config *pins,
179 unsigned long size) { return 0; }
180static inline int davinci_cfg_reg(unsigned long reg_cfg) { return 0; } 164static inline int davinci_cfg_reg(unsigned long reg_cfg) { return 0; }
181#endif 165#endif
182 166
diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h
index 55a90d419fa..ab8a2586d1c 100644
--- a/arch/arm/mach-davinci/include/mach/psc.h
+++ b/arch/arm/mach-davinci/include/mach/psc.h
@@ -27,6 +27,8 @@
27#ifndef __ASM_ARCH_PSC_H 27#ifndef __ASM_ARCH_PSC_H
28#define __ASM_ARCH_PSC_H 28#define __ASM_ARCH_PSC_H
29 29
30#define DAVINCI_PWR_SLEEP_CNTRL_BASE 0x01C41000
31
30/* Power and Sleep Controller (PSC) Domains */ 32/* Power and Sleep Controller (PSC) Domains */
31#define DAVINCI_GPSC_ARMDOMAIN 0 33#define DAVINCI_GPSC_ARMDOMAIN 0
32#define DAVINCI_GPSC_DSPDOMAIN 1 34#define DAVINCI_GPSC_DSPDOMAIN 1
@@ -116,8 +118,8 @@
116#define DM646X_LPSC_TIMER1 35 118#define DM646X_LPSC_TIMER1 35
117#define DM646X_LPSC_ARM_INTC 45 119#define DM646X_LPSC_ARM_INTC 45
118 120
119extern int davinci_psc_is_clk_active(unsigned int id); 121extern int davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id);
120extern void davinci_psc_config(unsigned int domain, unsigned int id, 122extern void davinci_psc_config(unsigned int domain, unsigned int ctlr,
121 char enable); 123 unsigned int id, char enable);
122 124
123#endif /* __ASM_ARCH_PSC_H */ 125#endif /* __ASM_ARCH_PSC_H */
diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h
index 632847d74a1..794fa5cf93c 100644
--- a/arch/arm/mach-davinci/include/mach/serial.h
+++ b/arch/arm/mach-davinci/include/mach/serial.h
@@ -18,8 +18,6 @@
18#define DAVINCI_UART1_BASE (IO_PHYS + 0x20400) 18#define DAVINCI_UART1_BASE (IO_PHYS + 0x20400)
19#define DAVINCI_UART2_BASE (IO_PHYS + 0x20800) 19#define DAVINCI_UART2_BASE (IO_PHYS + 0x20800)
20 20
21#define DM355_UART2_BASE (IO_PHYS + 0x206000)
22
23/* DaVinci UART register offsets */ 21/* DaVinci UART register offsets */
24#define UART_DAVINCI_PWREMU 0x0c 22#define UART_DAVINCI_PWREMU 0x0c
25#define UART_DM646X_SCR 0x10 23#define UART_DM646X_SCR 0x10
@@ -30,6 +28,6 @@ struct davinci_uart_config {
30 unsigned int enabled_uarts; 28 unsigned int enabled_uarts;
31}; 29};
32 30
33extern void davinci_serial_init(struct davinci_uart_config *); 31extern int davinci_serial_init(struct davinci_uart_config *);
34 32
35#endif /* __ASM_ARCH_SERIAL_H */ 33#endif /* __ASM_ARCH_SERIAL_H */
diff --git a/arch/arm/mach-davinci/include/mach/sram.h b/arch/arm/mach-davinci/include/mach/sram.h
new file mode 100644
index 00000000000..111f7cc71e0
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/sram.h
@@ -0,0 +1,27 @@
1/*
2 * mach/sram.h - DaVinci simple SRAM allocator
3 *
4 * Copyright (C) 2009 David Brownell
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#ifndef __MACH_SRAM_H
11#define __MACH_SRAM_H
12
13/* ARBITRARY: SRAM allocations are multiples of this 2^N size */
14#define SRAM_GRANULARITY 512
15
16/*
17 * SRAM allocations return a CPU virtual address, or NULL on error.
18 * If a DMA address is requested and the SRAM supports DMA, its
19 * mapped address is also returned.
20 *
21 * Errors include SRAM memory not being available, and requesting
22 * DMA mapped SRAM on systems which don't allow that.
23 */
24extern void *sram_alloc(size_t len, dma_addr_t *dma);
25extern void sram_free(void *addr, size_t len);
26
27#endif /* __MACH_SRAM_H */
diff --git a/arch/arm/mach-davinci/include/mach/time.h b/arch/arm/mach-davinci/include/mach/time.h
new file mode 100644
index 00000000000..1c971d8d8ba
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/time.h
@@ -0,0 +1,35 @@
1/*
2 * Local header file for DaVinci time code.
3 *
4 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
5 *
6 * 2007 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11#ifndef __ARCH_ARM_MACH_DAVINCI_TIME_H
12#define __ARCH_ARM_MACH_DAVINCI_TIME_H
13
14#define DAVINCI_TIMER0_BASE (IO_PHYS + 0x21400)
15#define DAVINCI_TIMER1_BASE (IO_PHYS + 0x21800)
16#define DAVINCI_WDOG_BASE (IO_PHYS + 0x21C00)
17
18enum {
19 T0_BOT,
20 T0_TOP,
21 T1_BOT,
22 T1_TOP,
23 NUM_TIMERS
24};
25
26#define IS_TIMER1(id) (id & 0x2)
27#define IS_TIMER0(id) (!IS_TIMER1(id))
28#define IS_TIMER_TOP(id) ((id & 0x1))
29#define IS_TIMER_BOT(id) (!IS_TIMER_TOP(id))
30
31#define ID_TO_TIMER(id) (IS_TIMER1(id) != 0)
32
33extern struct davinci_timer_instance davinci_timer_instance[];
34
35#endif /* __ARCH_ARM_MACH_DAVINCI_TIME_H */
diff --git a/arch/arm/mach-davinci/include/mach/uncompress.h b/arch/arm/mach-davinci/include/mach/uncompress.h
index 8c165def37b..1e27475f9a2 100644
--- a/arch/arm/mach-davinci/include/mach/uncompress.h
+++ b/arch/arm/mach-davinci/include/mach/uncompress.h
@@ -13,11 +13,24 @@
13#include <linux/serial_reg.h> 13#include <linux/serial_reg.h>
14#include <mach/serial.h> 14#include <mach/serial.h>
15 15
16#include <asm/mach-types.h>
17
18extern unsigned int __machine_arch_type;
19
20static u32 *uart;
21
22static u32 *get_uart_base(void)
23{
24 /* Add logic here for new platforms, using __macine_arch_type */
25 return (u32 *)DAVINCI_UART0_BASE;
26}
27
16/* PORT_16C550A, in polled non-fifo mode */ 28/* PORT_16C550A, in polled non-fifo mode */
17 29
18static void putc(char c) 30static void putc(char c)
19{ 31{
20 volatile u32 *uart = (volatile void *) DAVINCI_UART0_BASE; 32 if (!uart)
33 uart = get_uart_base();
21 34
22 while (!(uart[UART_LSR] & UART_LSR_THRE)) 35 while (!(uart[UART_LSR] & UART_LSR_THRE))
23 barrier(); 36 barrier();
@@ -26,7 +39,9 @@ static void putc(char c)
26 39
27static inline void flush(void) 40static inline void flush(void)
28{ 41{
29 volatile u32 *uart = (volatile void *) DAVINCI_UART0_BASE; 42 if (!uart)
43 uart = get_uart_base();
44
30 while (!(uart[UART_LSR] & UART_LSR_THRE)) 45 while (!(uart[UART_LSR] & UART_LSR_THRE))
31 barrier(); 46 barrier();
32} 47}
diff --git a/arch/arm/mach-davinci/io.c b/arch/arm/mach-davinci/io.c
index a548abb513e..49912b48b1b 100644
--- a/arch/arm/mach-davinci/io.c
+++ b/arch/arm/mach-davinci/io.c
@@ -9,47 +9,9 @@
9 */ 9 */
10 10
11#include <linux/module.h> 11#include <linux/module.h>
12#include <linux/kernel.h>
13#include <linux/init.h>
14#include <linux/io.h> 12#include <linux/io.h>
15 13
16#include <asm/tlb.h> 14#include <asm/tlb.h>
17#include <asm/memory.h>
18
19#include <asm/mach/map.h>
20#include <mach/clock.h>
21
22extern void davinci_check_revision(void);
23
24/*
25 * The machine specific code may provide the extra mapping besides the
26 * default mapping provided here.
27 */
28static struct map_desc davinci_io_desc[] __initdata = {
29 {
30 .virtual = IO_VIRT,
31 .pfn = __phys_to_pfn(IO_PHYS),
32 .length = IO_SIZE,
33 .type = MT_DEVICE
34 },
35};
36
37void __init davinci_map_common_io(void)
38{
39 iotable_init(davinci_io_desc, ARRAY_SIZE(davinci_io_desc));
40
41 /* Normally devicemaps_init() would flush caches and tlb after
42 * mdesc->map_io(), but we must also do it here because of the CPU
43 * revision check below.
44 */
45 local_flush_tlb_all();
46 flush_cache_all();
47
48 /* We want to check CPU revision early for cpu_is_xxxx() macros.
49 * IO space mapping must be initialized before we can do that.
50 */
51 davinci_check_revision();
52}
53 15
54#define BETWEEN(p, st, sz) ((p) >= (st) && (p) < ((st) + (sz))) 16#define BETWEEN(p, st, sz) ((p) >= (st) && (p) < ((st) + (sz)))
55#define XLATE(p, pst, vst) ((void __iomem *)((p) - (pst) + (vst))) 17#define XLATE(p, pst, vst) ((void __iomem *)((p) - (pst) + (vst)))
diff --git a/arch/arm/mach-davinci/irq.c b/arch/arm/mach-davinci/irq.c
index 5a324c90e29..af92ffee847 100644
--- a/arch/arm/mach-davinci/irq.c
+++ b/arch/arm/mach-davinci/irq.c
@@ -26,6 +26,7 @@
26 26
27#include <mach/hardware.h> 27#include <mach/hardware.h>
28#include <mach/cputype.h> 28#include <mach/cputype.h>
29#include <mach/common.h>
29#include <asm/mach/irq.h> 30#include <asm/mach/irq.h>
30 31
31#define IRQ_BIT(irq) ((irq) & 0x1f) 32#define IRQ_BIT(irq) ((irq) & 0x1f)
@@ -41,18 +42,14 @@
41#define IRQ_INTPRI0_REG_OFFSET 0x0030 42#define IRQ_INTPRI0_REG_OFFSET 0x0030
42#define IRQ_INTPRI7_REG_OFFSET 0x004C 43#define IRQ_INTPRI7_REG_OFFSET 0x004C
43 44
44const u8 *davinci_def_priorities;
45
46#define INTC_BASE IO_ADDRESS(DAVINCI_ARM_INTC_BASE)
47
48static inline unsigned int davinci_irq_readl(int offset) 45static inline unsigned int davinci_irq_readl(int offset)
49{ 46{
50 return __raw_readl(INTC_BASE + offset); 47 return __raw_readl(davinci_intc_base + offset);
51} 48}
52 49
53static inline void davinci_irq_writel(unsigned long value, int offset) 50static inline void davinci_irq_writel(unsigned long value, int offset)
54{ 51{
55 __raw_writel(value, INTC_BASE + offset); 52 __raw_writel(value, davinci_intc_base + offset);
56} 53}
57 54
58/* Disable interrupt */ 55/* Disable interrupt */
@@ -113,217 +110,11 @@ static struct irq_chip davinci_irq_chip_0 = {
113 .unmask = davinci_unmask_irq, 110 .unmask = davinci_unmask_irq,
114}; 111};
115 112
116/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
117static const u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] __initdata = {
118 [IRQ_VDINT0] = 2,
119 [IRQ_VDINT1] = 6,
120 [IRQ_VDINT2] = 6,
121 [IRQ_HISTINT] = 6,
122 [IRQ_H3AINT] = 6,
123 [IRQ_PRVUINT] = 6,
124 [IRQ_RSZINT] = 6,
125 [7] = 7,
126 [IRQ_VENCINT] = 6,
127 [IRQ_ASQINT] = 6,
128 [IRQ_IMXINT] = 6,
129 [IRQ_VLCDINT] = 6,
130 [IRQ_USBINT] = 4,
131 [IRQ_EMACINT] = 4,
132 [14] = 7,
133 [15] = 7,
134 [IRQ_CCINT0] = 5, /* dma */
135 [IRQ_CCERRINT] = 5, /* dma */
136 [IRQ_TCERRINT0] = 5, /* dma */
137 [IRQ_TCERRINT] = 5, /* dma */
138 [IRQ_PSCIN] = 7,
139 [21] = 7,
140 [IRQ_IDE] = 4,
141 [23] = 7,
142 [IRQ_MBXINT] = 7,
143 [IRQ_MBRINT] = 7,
144 [IRQ_MMCINT] = 7,
145 [IRQ_SDIOINT] = 7,
146 [28] = 7,
147 [IRQ_DDRINT] = 7,
148 [IRQ_AEMIFINT] = 7,
149 [IRQ_VLQINT] = 4,
150 [IRQ_TINT0_TINT12] = 2, /* clockevent */
151 [IRQ_TINT0_TINT34] = 2, /* clocksource */
152 [IRQ_TINT1_TINT12] = 7, /* DSP timer */
153 [IRQ_TINT1_TINT34] = 7, /* system tick */
154 [IRQ_PWMINT0] = 7,
155 [IRQ_PWMINT1] = 7,
156 [IRQ_PWMINT2] = 7,
157 [IRQ_I2C] = 3,
158 [IRQ_UARTINT0] = 3,
159 [IRQ_UARTINT1] = 3,
160 [IRQ_UARTINT2] = 3,
161 [IRQ_SPINT0] = 3,
162 [IRQ_SPINT1] = 3,
163 [45] = 7,
164 [IRQ_DSP2ARM0] = 4,
165 [IRQ_DSP2ARM1] = 4,
166 [IRQ_GPIO0] = 7,
167 [IRQ_GPIO1] = 7,
168 [IRQ_GPIO2] = 7,
169 [IRQ_GPIO3] = 7,
170 [IRQ_GPIO4] = 7,
171 [IRQ_GPIO5] = 7,
172 [IRQ_GPIO6] = 7,
173 [IRQ_GPIO7] = 7,
174 [IRQ_GPIOBNK0] = 7,
175 [IRQ_GPIOBNK1] = 7,
176 [IRQ_GPIOBNK2] = 7,
177 [IRQ_GPIOBNK3] = 7,
178 [IRQ_GPIOBNK4] = 7,
179 [IRQ_COMMTX] = 7,
180 [IRQ_COMMRX] = 7,
181 [IRQ_EMUINT] = 7,
182};
183
184static const u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
185 [IRQ_DM646X_VP_VERTINT0] = 7,
186 [IRQ_DM646X_VP_VERTINT1] = 7,
187 [IRQ_DM646X_VP_VERTINT2] = 7,
188 [IRQ_DM646X_VP_VERTINT3] = 7,
189 [IRQ_DM646X_VP_ERRINT] = 7,
190 [IRQ_DM646X_RESERVED_1] = 7,
191 [IRQ_DM646X_RESERVED_2] = 7,
192 [IRQ_DM646X_WDINT] = 7,
193 [IRQ_DM646X_CRGENINT0] = 7,
194 [IRQ_DM646X_CRGENINT1] = 7,
195 [IRQ_DM646X_TSIFINT0] = 7,
196 [IRQ_DM646X_TSIFINT1] = 7,
197 [IRQ_DM646X_VDCEINT] = 7,
198 [IRQ_DM646X_USBINT] = 7,
199 [IRQ_DM646X_USBDMAINT] = 7,
200 [IRQ_DM646X_PCIINT] = 7,
201 [IRQ_CCINT0] = 7, /* dma */
202 [IRQ_CCERRINT] = 7, /* dma */
203 [IRQ_TCERRINT0] = 7, /* dma */
204 [IRQ_TCERRINT] = 7, /* dma */
205 [IRQ_DM646X_TCERRINT2] = 7,
206 [IRQ_DM646X_TCERRINT3] = 7,
207 [IRQ_DM646X_IDE] = 7,
208 [IRQ_DM646X_HPIINT] = 7,
209 [IRQ_DM646X_EMACRXTHINT] = 7,
210 [IRQ_DM646X_EMACRXINT] = 7,
211 [IRQ_DM646X_EMACTXINT] = 7,
212 [IRQ_DM646X_EMACMISCINT] = 7,
213 [IRQ_DM646X_MCASP0TXINT] = 7,
214 [IRQ_DM646X_MCASP0RXINT] = 7,
215 [IRQ_AEMIFINT] = 7,
216 [IRQ_DM646X_RESERVED_3] = 7,
217 [IRQ_DM646X_MCASP1TXINT] = 7, /* clockevent */
218 [IRQ_TINT0_TINT34] = 7, /* clocksource */
219 [IRQ_TINT1_TINT12] = 7, /* DSP timer */
220 [IRQ_TINT1_TINT34] = 7, /* system tick */
221 [IRQ_PWMINT0] = 7,
222 [IRQ_PWMINT1] = 7,
223 [IRQ_DM646X_VLQINT] = 7,
224 [IRQ_I2C] = 7,
225 [IRQ_UARTINT0] = 7,
226 [IRQ_UARTINT1] = 7,
227 [IRQ_DM646X_UARTINT2] = 7,
228 [IRQ_DM646X_SPINT0] = 7,
229 [IRQ_DM646X_SPINT1] = 7,
230 [IRQ_DM646X_DSP2ARMINT] = 7,
231 [IRQ_DM646X_RESERVED_4] = 7,
232 [IRQ_DM646X_PSCINT] = 7,
233 [IRQ_DM646X_GPIO0] = 7,
234 [IRQ_DM646X_GPIO1] = 7,
235 [IRQ_DM646X_GPIO2] = 7,
236 [IRQ_DM646X_GPIO3] = 7,
237 [IRQ_DM646X_GPIO4] = 7,
238 [IRQ_DM646X_GPIO5] = 7,
239 [IRQ_DM646X_GPIO6] = 7,
240 [IRQ_DM646X_GPIO7] = 7,
241 [IRQ_DM646X_GPIOBNK0] = 7,
242 [IRQ_DM646X_GPIOBNK1] = 7,
243 [IRQ_DM646X_GPIOBNK2] = 7,
244 [IRQ_DM646X_DDRINT] = 7,
245 [IRQ_DM646X_AEMIFINT] = 7,
246 [IRQ_COMMTX] = 7,
247 [IRQ_COMMRX] = 7,
248 [IRQ_EMUINT] = 7,
249};
250
251static const u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = {
252 [IRQ_DM355_CCDC_VDINT0] = 2,
253 [IRQ_DM355_CCDC_VDINT1] = 6,
254 [IRQ_DM355_CCDC_VDINT2] = 6,
255 [IRQ_DM355_IPIPE_HST] = 6,
256 [IRQ_DM355_H3AINT] = 6,
257 [IRQ_DM355_IPIPE_SDR] = 6,
258 [IRQ_DM355_IPIPEIFINT] = 6,
259 [IRQ_DM355_OSDINT] = 7,
260 [IRQ_DM355_VENCINT] = 6,
261 [IRQ_ASQINT] = 6,
262 [IRQ_IMXINT] = 6,
263 [IRQ_USBINT] = 4,
264 [IRQ_DM355_RTOINT] = 4,
265 [IRQ_DM355_UARTINT2] = 7,
266 [IRQ_DM355_TINT6] = 7,
267 [IRQ_CCINT0] = 5, /* dma */
268 [IRQ_CCERRINT] = 5, /* dma */
269 [IRQ_TCERRINT0] = 5, /* dma */
270 [IRQ_TCERRINT] = 5, /* dma */
271 [IRQ_DM355_SPINT2_1] = 7,
272 [IRQ_DM355_TINT7] = 4,
273 [IRQ_DM355_SDIOINT0] = 7,
274 [IRQ_MBXINT] = 7,
275 [IRQ_MBRINT] = 7,
276 [IRQ_MMCINT] = 7,
277 [IRQ_DM355_MMCINT1] = 7,
278 [IRQ_DM355_PWMINT3] = 7,
279 [IRQ_DDRINT] = 7,
280 [IRQ_AEMIFINT] = 7,
281 [IRQ_DM355_SDIOINT1] = 4,
282 [IRQ_TINT0_TINT12] = 2, /* clockevent */
283 [IRQ_TINT0_TINT34] = 2, /* clocksource */
284 [IRQ_TINT1_TINT12] = 7, /* DSP timer */
285 [IRQ_TINT1_TINT34] = 7, /* system tick */
286 [IRQ_PWMINT0] = 7,
287 [IRQ_PWMINT1] = 7,
288 [IRQ_PWMINT2] = 7,
289 [IRQ_I2C] = 3,
290 [IRQ_UARTINT0] = 3,
291 [IRQ_UARTINT1] = 3,
292 [IRQ_DM355_SPINT0_0] = 3,
293 [IRQ_DM355_SPINT0_1] = 3,
294 [IRQ_DM355_GPIO0] = 3,
295 [IRQ_DM355_GPIO1] = 7,
296 [IRQ_DM355_GPIO2] = 4,
297 [IRQ_DM355_GPIO3] = 4,
298 [IRQ_DM355_GPIO4] = 7,
299 [IRQ_DM355_GPIO5] = 7,
300 [IRQ_DM355_GPIO6] = 7,
301 [IRQ_DM355_GPIO7] = 7,
302 [IRQ_DM355_GPIO8] = 7,
303 [IRQ_DM355_GPIO9] = 7,
304 [IRQ_DM355_GPIOBNK0] = 7,
305 [IRQ_DM355_GPIOBNK1] = 7,
306 [IRQ_DM355_GPIOBNK2] = 7,
307 [IRQ_DM355_GPIOBNK3] = 7,
308 [IRQ_DM355_GPIOBNK4] = 7,
309 [IRQ_DM355_GPIOBNK5] = 7,
310 [IRQ_DM355_GPIOBNK6] = 7,
311 [IRQ_COMMTX] = 7,
312 [IRQ_COMMRX] = 7,
313 [IRQ_EMUINT] = 7,
314};
315
316/* ARM Interrupt Controller Initialization */ 113/* ARM Interrupt Controller Initialization */
317void __init davinci_irq_init(void) 114void __init davinci_irq_init(void)
318{ 115{
319 unsigned i; 116 unsigned i;
320 117 const u8 *davinci_def_priorities = davinci_soc_info.intc_irq_prios;
321 if (cpu_is_davinci_dm644x())
322 davinci_def_priorities = dm644x_default_priorities;
323 else if (cpu_is_davinci_dm646x())
324 davinci_def_priorities = dm646x_default_priorities;
325 else if (cpu_is_davinci_dm355())
326 davinci_def_priorities = dm355_default_priorities;
327 118
328 /* Clear all interrupt requests */ 119 /* Clear all interrupt requests */
329 davinci_irq_writel(~0x0, FIQ_REG0_OFFSET); 120 davinci_irq_writel(~0x0, FIQ_REG0_OFFSET);
diff --git a/arch/arm/mach-davinci/mux.c b/arch/arm/mach-davinci/mux.c
index bbba0b247a4..d310f579aa8 100644
--- a/arch/arm/mach-davinci/mux.c
+++ b/arch/arm/mach-davinci/mux.c
@@ -21,18 +21,7 @@
21 21
22#include <mach/hardware.h> 22#include <mach/hardware.h>
23#include <mach/mux.h> 23#include <mach/mux.h>
24 24#include <mach/common.h>
25static const struct mux_config *mux_table;
26static unsigned long pin_table_sz;
27
28int __init davinci_mux_register(const struct mux_config *pins,
29 unsigned long size)
30{
31 mux_table = pins;
32 pin_table_sz = size;
33
34 return 0;
35}
36 25
37/* 26/*
38 * Sets the DAVINCI MUX register based on the table 27 * Sets the DAVINCI MUX register based on the table
@@ -40,23 +29,24 @@ int __init davinci_mux_register(const struct mux_config *pins,
40int __init_or_module davinci_cfg_reg(const unsigned long index) 29int __init_or_module davinci_cfg_reg(const unsigned long index)
41{ 30{
42 static DEFINE_SPINLOCK(mux_spin_lock); 31 static DEFINE_SPINLOCK(mux_spin_lock);
43 void __iomem *base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE); 32 struct davinci_soc_info *soc_info = &davinci_soc_info;
33 void __iomem *base = soc_info->pinmux_base;
44 unsigned long flags; 34 unsigned long flags;
45 const struct mux_config *cfg; 35 const struct mux_config *cfg;
46 unsigned int reg_orig = 0, reg = 0; 36 unsigned int reg_orig = 0, reg = 0;
47 unsigned int mask, warn = 0; 37 unsigned int mask, warn = 0;
48 38
49 if (!mux_table) 39 if (!soc_info->pinmux_pins)
50 BUG(); 40 BUG();
51 41
52 if (index >= pin_table_sz) { 42 if (index >= soc_info->pinmux_pins_num) {
53 printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n", 43 printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n",
54 index, pin_table_sz); 44 index, soc_info->pinmux_pins_num);
55 dump_stack(); 45 dump_stack();
56 return -ENODEV; 46 return -ENODEV;
57 } 47 }
58 48
59 cfg = &mux_table[index]; 49 cfg = &soc_info->pinmux_pins[index];
60 50
61 if (cfg->name == NULL) { 51 if (cfg->name == NULL) {
62 printk(KERN_ERR "No entry for the specified index\n"); 52 printk(KERN_ERR "No entry for the specified index\n");
diff --git a/arch/arm/mach-davinci/psc.c b/arch/arm/mach-davinci/psc.c
index 84171abf5f7..a78b657e916 100644
--- a/arch/arm/mach-davinci/psc.c
+++ b/arch/arm/mach-davinci/psc.c
@@ -28,8 +28,6 @@
28#include <mach/psc.h> 28#include <mach/psc.h>
29#include <mach/mux.h> 29#include <mach/mux.h>
30 30
31#define DAVINCI_PWR_SLEEP_CNTRL_BASE 0x01C41000
32
33/* PSC register offsets */ 31/* PSC register offsets */
34#define EPCPR 0x070 32#define EPCPR 0x070
35#define PTCMD 0x120 33#define PTCMD 0x120
@@ -42,22 +40,42 @@
42#define MDSTAT_STATE_MASK 0x1f 40#define MDSTAT_STATE_MASK 0x1f
43 41
44/* Return nonzero iff the domain's clock is active */ 42/* Return nonzero iff the domain's clock is active */
45int __init davinci_psc_is_clk_active(unsigned int id) 43int __init davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id)
46{ 44{
47 void __iomem *psc_base = IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE); 45 void __iomem *psc_base;
48 u32 mdstat = __raw_readl(psc_base + MDSTAT + 4 * id); 46 u32 mdstat;
47 struct davinci_soc_info *soc_info = &davinci_soc_info;
48
49 if (!soc_info->psc_bases || (ctlr >= soc_info->psc_bases_num)) {
50 pr_warning("PSC: Bad psc data: 0x%x[%d]\n",
51 (int)soc_info->psc_bases, ctlr);
52 return 0;
53 }
54
55 psc_base = soc_info->psc_bases[ctlr];
56 mdstat = __raw_readl(psc_base + MDSTAT + 4 * id);
49 57
50 /* if clocked, state can be "Enable" or "SyncReset" */ 58 /* if clocked, state can be "Enable" or "SyncReset" */
51 return mdstat & BIT(12); 59 return mdstat & BIT(12);
52} 60}
53 61
54/* Enable or disable a PSC domain */ 62/* Enable or disable a PSC domain */
55void davinci_psc_config(unsigned int domain, unsigned int id, char enable) 63void davinci_psc_config(unsigned int domain, unsigned int ctlr,
64 unsigned int id, char enable)
56{ 65{
57 u32 epcpr, ptcmd, ptstat, pdstat, pdctl1, mdstat, mdctl; 66 u32 epcpr, ptcmd, ptstat, pdstat, pdctl1, mdstat, mdctl;
58 void __iomem *psc_base = IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE); 67 void __iomem *psc_base;
68 struct davinci_soc_info *soc_info = &davinci_soc_info;
59 u32 next_state = enable ? 0x3 : 0x2; /* 0x3 enables, 0x2 disables */ 69 u32 next_state = enable ? 0x3 : 0x2; /* 0x3 enables, 0x2 disables */
60 70
71 if (!soc_info->psc_bases || (ctlr >= soc_info->psc_bases_num)) {
72 pr_warning("PSC: Bad psc data: 0x%x[%d]\n",
73 (int)soc_info->psc_bases, ctlr);
74 return;
75 }
76
77 psc_base = soc_info->psc_bases[ctlr];
78
61 mdctl = __raw_readl(psc_base + MDCTL + 4 * id); 79 mdctl = __raw_readl(psc_base + MDCTL + 4 * id);
62 mdctl &= ~MDSTAT_STATE_MASK; 80 mdctl &= ~MDSTAT_STATE_MASK;
63 mdctl |= next_state; 81 mdctl |= next_state;
diff --git a/arch/arm/mach-davinci/serial.c b/arch/arm/mach-davinci/serial.c
index 69507579652..c530c7333d0 100644
--- a/arch/arm/mach-davinci/serial.c
+++ b/arch/arm/mach-davinci/serial.c
@@ -33,6 +33,8 @@
33#include <mach/serial.h> 33#include <mach/serial.h>
34#include <mach/irqs.h> 34#include <mach/irqs.h>
35#include <mach/cputype.h> 35#include <mach/cputype.h>
36#include <mach/common.h>
37
36#include "clock.h" 38#include "clock.h"
37 39
38static inline unsigned int serial_read_reg(struct plat_serial8250_port *up, 40static inline unsigned int serial_read_reg(struct plat_serial8250_port *up,
@@ -49,44 +51,6 @@ static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
49 __raw_writel(value, IO_ADDRESS(p->mapbase) + offset); 51 __raw_writel(value, IO_ADDRESS(p->mapbase) + offset);
50} 52}
51 53
52static struct plat_serial8250_port serial_platform_data[] = {
53 {
54 .mapbase = DAVINCI_UART0_BASE,
55 .irq = IRQ_UARTINT0,
56 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
57 UPF_IOREMAP,
58 .iotype = UPIO_MEM,
59 .regshift = 2,
60 },
61 {
62 .mapbase = DAVINCI_UART1_BASE,
63 .irq = IRQ_UARTINT1,
64 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
65 UPF_IOREMAP,
66 .iotype = UPIO_MEM,
67 .regshift = 2,
68 },
69 {
70 .mapbase = DAVINCI_UART2_BASE,
71 .irq = IRQ_UARTINT2,
72 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
73 UPF_IOREMAP,
74 .iotype = UPIO_MEM,
75 .regshift = 2,
76 },
77 {
78 .flags = 0
79 },
80};
81
82static struct platform_device serial_device = {
83 .name = "serial8250",
84 .id = PLAT8250_DEV_PLATFORM,
85 .dev = {
86 .platform_data = serial_platform_data,
87 },
88};
89
90static void __init davinci_serial_reset(struct plat_serial8250_port *p) 54static void __init davinci_serial_reset(struct plat_serial8250_port *p)
91{ 55{
92 unsigned int pwremu = 0; 56 unsigned int pwremu = 0;
@@ -106,35 +70,22 @@ static void __init davinci_serial_reset(struct plat_serial8250_port *p)
106 UART_DM646X_SCR_TX_WATERMARK); 70 UART_DM646X_SCR_TX_WATERMARK);
107} 71}
108 72
109void __init davinci_serial_init(struct davinci_uart_config *info) 73int __init davinci_serial_init(struct davinci_uart_config *info)
110{ 74{
111 int i; 75 int i;
112 char name[16]; 76 char name[16];
113 struct clk *uart_clk; 77 struct clk *uart_clk;
114 struct device *dev = &serial_device.dev; 78 struct davinci_soc_info *soc_info = &davinci_soc_info;
79 struct device *dev = &soc_info->serial_dev->dev;
80 struct plat_serial8250_port *p = dev->platform_data;
115 81
116 /* 82 /*
117 * Make sure the serial ports are muxed on at this point. 83 * Make sure the serial ports are muxed on at this point.
118 * You have to mux them off in device drivers later on 84 * You have to mux them off in device drivers later on if not needed.
119 * if not needed.
120 */ 85 */
121 for (i = 0; i < DAVINCI_MAX_NR_UARTS; i++) { 86 for (i = 0; i < DAVINCI_MAX_NR_UARTS; i++, p++) {
122 struct plat_serial8250_port *p = serial_platform_data + i; 87 if (!(info->enabled_uarts & (1 << i)))
123
124 if (!(info->enabled_uarts & (1 << i))) {
125 p->flags = 0;
126 continue; 88 continue;
127 }
128
129 if (cpu_is_davinci_dm646x())
130 p->iotype = UPIO_MEM32;
131
132 if (cpu_is_davinci_dm355()) {
133 if (i == 2) {
134 p->mapbase = (unsigned long)DM355_UART2_BASE;
135 p->irq = IRQ_DM355_UARTINT2;
136 }
137 }
138 89
139 sprintf(name, "uart%d", i); 90 sprintf(name, "uart%d", i);
140 uart_clk = clk_get(dev, name); 91 uart_clk = clk_get(dev, name);
@@ -147,11 +98,6 @@ void __init davinci_serial_init(struct davinci_uart_config *info)
147 davinci_serial_reset(p); 98 davinci_serial_reset(p);
148 } 99 }
149 } 100 }
150}
151 101
152static int __init davinci_init(void) 102 return platform_device_register(soc_info->serial_dev);
153{
154 return platform_device_register(&serial_device);
155} 103}
156
157arch_initcall(davinci_init);
diff --git a/arch/arm/mach-davinci/sram.c b/arch/arm/mach-davinci/sram.c
new file mode 100644
index 00000000000..db54b2a66b4
--- /dev/null
+++ b/arch/arm/mach-davinci/sram.c
@@ -0,0 +1,74 @@
1/*
2 * mach-davinci/sram.c - DaVinci simple SRAM allocator
3 *
4 * Copyright (C) 2009 David Brownell
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11#include <linux/module.h>
12#include <linux/kernel.h>
13#include <linux/init.h>
14#include <linux/genalloc.h>
15
16#include <mach/common.h>
17#include <mach/memory.h>
18#include <mach/sram.h>
19
20
21static struct gen_pool *sram_pool;
22
23void *sram_alloc(size_t len, dma_addr_t *dma)
24{
25 unsigned long vaddr;
26 dma_addr_t dma_base = davinci_soc_info.sram_dma;
27
28 if (dma)
29 *dma = 0;
30 if (!sram_pool || (dma && !dma_base))
31 return NULL;
32
33 vaddr = gen_pool_alloc(sram_pool, len);
34 if (!vaddr)
35 return NULL;
36
37 if (dma)
38 *dma = dma_base + (vaddr - SRAM_VIRT);
39 return (void *)vaddr;
40
41}
42EXPORT_SYMBOL(sram_alloc);
43
44void sram_free(void *addr, size_t len)
45{
46 gen_pool_free(sram_pool, (unsigned long) addr, len);
47}
48EXPORT_SYMBOL(sram_free);
49
50
51/*
52 * REVISIT This supports CPU and DMA access to/from SRAM, but it
53 * doesn't (yet?) support some other notable uses of SRAM: as TCM
54 * for data and/or instructions; and holding code needed to enter
55 * and exit suspend states (while DRAM can't be used).
56 */
57static int __init sram_init(void)
58{
59 unsigned len = davinci_soc_info.sram_len;
60 int status = 0;
61
62 if (len) {
63 len = min(len, SRAM_SIZE);
64 sram_pool = gen_pool_create(ilog2(SRAM_GRANULARITY), -1);
65 if (!sram_pool)
66 status = -ENOMEM;
67 }
68 if (sram_pool)
69 status = gen_pool_add(sram_pool, SRAM_VIRT, len, -1);
70 WARN_ON(status < 0);
71 return status;
72}
73core_initcall(sram_init);
74
diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c
index 494e01bff5c..0884ca57bfb 100644
--- a/arch/arm/mach-davinci/time.c
+++ b/arch/arm/mach-davinci/time.c
@@ -19,6 +19,7 @@
19#include <linux/clk.h> 19#include <linux/clk.h>
20#include <linux/err.h> 20#include <linux/err.h>
21#include <linux/device.h> 21#include <linux/device.h>
22#include <linux/platform_device.h>
22 23
23#include <mach/hardware.h> 24#include <mach/hardware.h>
24#include <asm/system.h> 25#include <asm/system.h>
@@ -28,52 +29,41 @@
28#include <asm/errno.h> 29#include <asm/errno.h>
29#include <mach/io.h> 30#include <mach/io.h>
30#include <mach/cputype.h> 31#include <mach/cputype.h>
32#include <mach/time.h>
31#include "clock.h" 33#include "clock.h"
32 34
33static struct clock_event_device clockevent_davinci; 35static struct clock_event_device clockevent_davinci;
34static unsigned int davinci_clock_tick_rate; 36static unsigned int davinci_clock_tick_rate;
35 37
36#define DAVINCI_TIMER0_BASE (IO_PHYS + 0x21400)
37#define DAVINCI_TIMER1_BASE (IO_PHYS + 0x21800)
38#define DAVINCI_WDOG_BASE (IO_PHYS + 0x21C00)
39
40enum {
41 T0_BOT = 0, T0_TOP, T1_BOT, T1_TOP, NUM_TIMERS,
42};
43
44#define IS_TIMER1(id) (id & 0x2)
45#define IS_TIMER0(id) (!IS_TIMER1(id))
46#define IS_TIMER_TOP(id) ((id & 0x1))
47#define IS_TIMER_BOT(id) (!IS_TIMER_TOP(id))
48
49static int timer_irqs[NUM_TIMERS] = {
50 IRQ_TINT0_TINT12,
51 IRQ_TINT0_TINT34,
52 IRQ_TINT1_TINT12,
53 IRQ_TINT1_TINT34,
54};
55
56/* 38/*
57 * This driver configures the 2 64-bit count-up timers as 4 independent 39 * This driver configures the 2 64-bit count-up timers as 4 independent
58 * 32-bit count-up timers used as follows: 40 * 32-bit count-up timers used as follows:
59 *
60 * T0_BOT: Timer 0, bottom: clockevent source for hrtimers
61 * T0_TOP: Timer 0, top : clocksource for generic timekeeping
62 * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
63 * T1_TOP: Timer 1, top : <unused>
64 */ 41 */
65#define TID_CLOCKEVENT T0_BOT 42
66#define TID_CLOCKSOURCE T0_TOP 43enum {
44 TID_CLOCKEVENT,
45 TID_CLOCKSOURCE,
46};
67 47
68/* Timer register offsets */ 48/* Timer register offsets */
69#define PID12 0x0 49#define PID12 0x0
70#define TIM12 0x10 50#define TIM12 0x10
71#define TIM34 0x14 51#define TIM34 0x14
72#define PRD12 0x18 52#define PRD12 0x18
73#define PRD34 0x1c 53#define PRD34 0x1c
74#define TCR 0x20 54#define TCR 0x20
75#define TGCR 0x24 55#define TGCR 0x24
76#define WDTCR 0x28 56#define WDTCR 0x28
57
58/* Offsets of the 8 compare registers */
59#define CMP12_0 0x60
60#define CMP12_1 0x64
61#define CMP12_2 0x68
62#define CMP12_3 0x6c
63#define CMP12_4 0x70
64#define CMP12_5 0x74
65#define CMP12_6 0x78
66#define CMP12_7 0x7c
77 67
78/* Timer register bitfields */ 68/* Timer register bitfields */
79#define TCR_ENAMODE_DISABLE 0x0 69#define TCR_ENAMODE_DISABLE 0x0
@@ -105,6 +95,7 @@ struct timer_s {
105 unsigned int id; 95 unsigned int id;
106 unsigned long period; 96 unsigned long period;
107 unsigned long opts; 97 unsigned long opts;
98 unsigned long flags;
108 void __iomem *base; 99 void __iomem *base;
109 unsigned long tim_off; 100 unsigned long tim_off;
110 unsigned long prd_off; 101 unsigned long prd_off;
@@ -114,30 +105,58 @@ struct timer_s {
114static struct timer_s timers[]; 105static struct timer_s timers[];
115 106
116/* values for 'opts' field of struct timer_s */ 107/* values for 'opts' field of struct timer_s */
117#define TIMER_OPTS_DISABLED 0x00 108#define TIMER_OPTS_DISABLED 0x01
118#define TIMER_OPTS_ONESHOT 0x01 109#define TIMER_OPTS_ONESHOT 0x02
119#define TIMER_OPTS_PERIODIC 0x02 110#define TIMER_OPTS_PERIODIC 0x04
111#define TIMER_OPTS_STATE_MASK 0x07
112
113#define TIMER_OPTS_USE_COMPARE 0x80000000
114#define USING_COMPARE(t) ((t)->opts & TIMER_OPTS_USE_COMPARE)
115
116static char *id_to_name[] = {
117 [T0_BOT] = "timer0_0",
118 [T0_TOP] = "timer0_1",
119 [T1_BOT] = "timer1_0",
120 [T1_TOP] = "timer1_1",
121};
120 122
121static int timer32_config(struct timer_s *t) 123static int timer32_config(struct timer_s *t)
122{ 124{
123 u32 tcr = __raw_readl(t->base + TCR); 125 u32 tcr;
124 126 struct davinci_soc_info *soc_info = &davinci_soc_info;
125 /* disable timer */ 127
126 tcr &= ~(TCR_ENAMODE_MASK << t->enamode_shift); 128 if (USING_COMPARE(t)) {
127 __raw_writel(tcr, t->base + TCR); 129 struct davinci_timer_instance *dtip =
128 130 soc_info->timer_info->timers;
129 /* reset counter to zero, set new period */ 131 int event_timer = ID_TO_TIMER(timers[TID_CLOCKEVENT].id);
130 __raw_writel(0, t->base + t->tim_off); 132
131 __raw_writel(t->period, t->base + t->prd_off); 133 /*
132 134 * Next interrupt should be the current time reg value plus
133 /* Set enable mode */ 135 * the new period (using 32-bit unsigned addition/wrapping
134 if (t->opts & TIMER_OPTS_ONESHOT) { 136 * to 0 on overflow). This assumes that the clocksource
135 tcr |= TCR_ENAMODE_ONESHOT << t->enamode_shift; 137 * is setup to count to 2^32-1 before wrapping around to 0.
136 } else if (t->opts & TIMER_OPTS_PERIODIC) { 138 */
137 tcr |= TCR_ENAMODE_PERIODIC << t->enamode_shift; 139 __raw_writel(__raw_readl(t->base + t->tim_off) + t->period,
140 t->base + dtip[event_timer].cmp_off);
141 } else {
142 tcr = __raw_readl(t->base + TCR);
143
144 /* disable timer */
145 tcr &= ~(TCR_ENAMODE_MASK << t->enamode_shift);
146 __raw_writel(tcr, t->base + TCR);
147
148 /* reset counter to zero, set new period */
149 __raw_writel(0, t->base + t->tim_off);
150 __raw_writel(t->period, t->base + t->prd_off);
151
152 /* Set enable mode */
153 if (t->opts & TIMER_OPTS_ONESHOT)
154 tcr |= TCR_ENAMODE_ONESHOT << t->enamode_shift;
155 else if (t->opts & TIMER_OPTS_PERIODIC)
156 tcr |= TCR_ENAMODE_PERIODIC << t->enamode_shift;
157
158 __raw_writel(tcr, t->base + TCR);
138 } 159 }
139
140 __raw_writel(tcr, t->base + TCR);
141 return 0; 160 return 0;
142} 161}
143 162
@@ -182,13 +201,14 @@ static struct timer_s timers[] = {
182 201
183static void __init timer_init(void) 202static void __init timer_init(void)
184{ 203{
185 u32 phys_bases[] = {DAVINCI_TIMER0_BASE, DAVINCI_TIMER1_BASE}; 204 struct davinci_soc_info *soc_info = &davinci_soc_info;
205 struct davinci_timer_instance *dtip = soc_info->timer_info->timers;
186 int i; 206 int i;
187 207
188 /* Global init of each 64-bit timer as a whole */ 208 /* Global init of each 64-bit timer as a whole */
189 for(i=0; i<2; i++) { 209 for(i=0; i<2; i++) {
190 u32 tgcr; 210 u32 tgcr;
191 void __iomem *base = IO_ADDRESS(phys_bases[i]); 211 void __iomem *base = dtip[i].base;
192 212
193 /* Disabled, Internal clock source */ 213 /* Disabled, Internal clock source */
194 __raw_writel(0, base + TCR); 214 __raw_writel(0, base + TCR);
@@ -214,33 +234,33 @@ static void __init timer_init(void)
214 /* Init of each timer as a 32-bit timer */ 234 /* Init of each timer as a 32-bit timer */
215 for (i=0; i< ARRAY_SIZE(timers); i++) { 235 for (i=0; i< ARRAY_SIZE(timers); i++) {
216 struct timer_s *t = &timers[i]; 236 struct timer_s *t = &timers[i];
217 u32 phys_base; 237 int timer = ID_TO_TIMER(t->id);
218 238 u32 irq;
219 if (t->name) { 239
220 t->id = i; 240 t->base = dtip[timer].base;
221 phys_base = (IS_TIMER1(t->id) ? 241
222 DAVINCI_TIMER1_BASE : DAVINCI_TIMER0_BASE); 242 if (IS_TIMER_BOT(t->id)) {
223 t->base = IO_ADDRESS(phys_base); 243 t->enamode_shift = 6;
224 244 t->tim_off = TIM12;
225 if (IS_TIMER_BOT(t->id)) { 245 t->prd_off = PRD12;
226 t->enamode_shift = 6; 246 irq = dtip[timer].bottom_irq;
227 t->tim_off = TIM12; 247 } else {
228 t->prd_off = PRD12; 248 t->enamode_shift = 22;
229 } else { 249 t->tim_off = TIM34;
230 t->enamode_shift = 22; 250 t->prd_off = PRD34;
231 t->tim_off = TIM34; 251 irq = dtip[timer].top_irq;
232 t->prd_off = PRD34; 252 }
233 } 253
234 254 /* Register interrupt */
235 /* Register interrupt */ 255 t->irqaction.name = t->name;
236 t->irqaction.name = t->name; 256 t->irqaction.dev_id = (void *)t;
237 t->irqaction.dev_id = (void *)t; 257
238 if (t->irqaction.handler != NULL) { 258 if (t->irqaction.handler != NULL) {
239 setup_irq(timer_irqs[t->id], &t->irqaction); 259 irq = USING_COMPARE(t) ? dtip[i].cmp_irq : irq;
240 } 260 setup_irq(irq, &t->irqaction);
241
242 timer32_config(&timers[i]);
243 } 261 }
262
263 timer32_config(&timers[i]);
244 } 264 }
245} 265}
246 266
@@ -255,7 +275,6 @@ static cycle_t read_cycles(struct clocksource *cs)
255} 275}
256 276
257static struct clocksource clocksource_davinci = { 277static struct clocksource clocksource_davinci = {
258 .name = "timer0_1",
259 .rating = 300, 278 .rating = 300,
260 .read = read_cycles, 279 .read = read_cycles,
261 .mask = CLOCKSOURCE_MASK(32), 280 .mask = CLOCKSOURCE_MASK(32),
@@ -284,15 +303,18 @@ static void davinci_set_mode(enum clock_event_mode mode,
284 switch (mode) { 303 switch (mode) {
285 case CLOCK_EVT_MODE_PERIODIC: 304 case CLOCK_EVT_MODE_PERIODIC:
286 t->period = davinci_clock_tick_rate / (HZ); 305 t->period = davinci_clock_tick_rate / (HZ);
287 t->opts = TIMER_OPTS_PERIODIC; 306 t->opts &= ~TIMER_OPTS_STATE_MASK;
307 t->opts |= TIMER_OPTS_PERIODIC;
288 timer32_config(t); 308 timer32_config(t);
289 break; 309 break;
290 case CLOCK_EVT_MODE_ONESHOT: 310 case CLOCK_EVT_MODE_ONESHOT:
291 t->opts = TIMER_OPTS_ONESHOT; 311 t->opts &= ~TIMER_OPTS_STATE_MASK;
312 t->opts |= TIMER_OPTS_ONESHOT;
292 break; 313 break;
293 case CLOCK_EVT_MODE_UNUSED: 314 case CLOCK_EVT_MODE_UNUSED:
294 case CLOCK_EVT_MODE_SHUTDOWN: 315 case CLOCK_EVT_MODE_SHUTDOWN:
295 t->opts = TIMER_OPTS_DISABLED; 316 t->opts &= ~TIMER_OPTS_STATE_MASK;
317 t->opts |= TIMER_OPTS_DISABLED;
296 break; 318 break;
297 case CLOCK_EVT_MODE_RESUME: 319 case CLOCK_EVT_MODE_RESUME:
298 break; 320 break;
@@ -300,7 +322,6 @@ static void davinci_set_mode(enum clock_event_mode mode,
300} 322}
301 323
302static struct clock_event_device clockevent_davinci = { 324static struct clock_event_device clockevent_davinci = {
303 .name = "timer0_0",
304 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, 325 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
305 .shift = 32, 326 .shift = 32,
306 .set_next_event = davinci_set_next_event, 327 .set_next_event = davinci_set_next_event,
@@ -311,10 +332,42 @@ static struct clock_event_device clockevent_davinci = {
311static void __init davinci_timer_init(void) 332static void __init davinci_timer_init(void)
312{ 333{
313 struct clk *timer_clk; 334 struct clk *timer_clk;
314 335 struct davinci_soc_info *soc_info = &davinci_soc_info;
336 unsigned int clockevent_id;
337 unsigned int clocksource_id;
315 static char err[] __initdata = KERN_ERR 338 static char err[] __initdata = KERN_ERR
316 "%s: can't register clocksource!\n"; 339 "%s: can't register clocksource!\n";
317 340
341 clockevent_id = soc_info->timer_info->clockevent_id;
342 clocksource_id = soc_info->timer_info->clocksource_id;
343
344 timers[TID_CLOCKEVENT].id = clockevent_id;
345 timers[TID_CLOCKSOURCE].id = clocksource_id;
346
347 /*
348 * If using same timer for both clock events & clocksource,
349 * a compare register must be used to generate an event interrupt.
350 * This is equivalent to a oneshot timer only (not periodic).
351 */
352 if (clockevent_id == clocksource_id) {
353 struct davinci_timer_instance *dtip =
354 soc_info->timer_info->timers;
355 int event_timer = ID_TO_TIMER(clockevent_id);
356
357 /* Only bottom timers can use compare regs */
358 if (IS_TIMER_TOP(clockevent_id))
359 pr_warning("davinci_timer_init: Invalid use"
360 " of system timers. Results unpredictable.\n");
361 else if ((dtip[event_timer].cmp_off == 0)
362 || (dtip[event_timer].cmp_irq == 0))
363 pr_warning("davinci_timer_init: Invalid timer instance"
364 " setup. Results unpredictable.\n");
365 else {
366 timers[TID_CLOCKEVENT].opts |= TIMER_OPTS_USE_COMPARE;
367 clockevent_davinci.features = CLOCK_EVT_FEAT_ONESHOT;
368 }
369 }
370
318 /* init timer hw */ 371 /* init timer hw */
319 timer_init(); 372 timer_init();
320 373
@@ -325,6 +378,7 @@ static void __init davinci_timer_init(void)
325 davinci_clock_tick_rate = clk_get_rate(timer_clk); 378 davinci_clock_tick_rate = clk_get_rate(timer_clk);
326 379
327 /* setup clocksource */ 380 /* setup clocksource */
381 clocksource_davinci.name = id_to_name[clocksource_id];
328 clocksource_davinci.mult = 382 clocksource_davinci.mult =
329 clocksource_khz2mult(davinci_clock_tick_rate/1000, 383 clocksource_khz2mult(davinci_clock_tick_rate/1000,
330 clocksource_davinci.shift); 384 clocksource_davinci.shift);
@@ -332,12 +386,12 @@ static void __init davinci_timer_init(void)
332 printk(err, clocksource_davinci.name); 386 printk(err, clocksource_davinci.name);
333 387
334 /* setup clockevent */ 388 /* setup clockevent */
389 clockevent_davinci.name = id_to_name[timers[TID_CLOCKEVENT].id];
335 clockevent_davinci.mult = div_sc(davinci_clock_tick_rate, NSEC_PER_SEC, 390 clockevent_davinci.mult = div_sc(davinci_clock_tick_rate, NSEC_PER_SEC,
336 clockevent_davinci.shift); 391 clockevent_davinci.shift);
337 clockevent_davinci.max_delta_ns = 392 clockevent_davinci.max_delta_ns =
338 clockevent_delta2ns(0xfffffffe, &clockevent_davinci); 393 clockevent_delta2ns(0xfffffffe, &clockevent_davinci);
339 clockevent_davinci.min_delta_ns = 394 clockevent_davinci.min_delta_ns = 50000; /* 50 usec */
340 clockevent_delta2ns(1, &clockevent_davinci);
341 395
342 clockevent_davinci.cpumask = cpumask_of(0); 396 clockevent_davinci.cpumask = cpumask_of(0);
343 clockevents_register_device(&clockevent_davinci); 397 clockevents_register_device(&clockevent_davinci);
@@ -349,15 +403,14 @@ struct sys_timer davinci_timer = {
349 403
350 404
351/* reset board using watchdog timer */ 405/* reset board using watchdog timer */
352void davinci_watchdog_reset(void) { 406void davinci_watchdog_reset(void)
407{
353 u32 tgcr, wdtcr; 408 u32 tgcr, wdtcr;
354 void __iomem *base = IO_ADDRESS(DAVINCI_WDOG_BASE); 409 struct davinci_soc_info *soc_info = &davinci_soc_info;
355 struct device dev; 410 void __iomem *base = soc_info->wdt_base;
356 struct clk *wd_clk; 411 struct clk *wd_clk;
357 char *name = "watchdog";
358 412
359 dev_set_name(&dev, name); 413 wd_clk = clk_get(&davinci_wdt_device.dev, NULL);
360 wd_clk = clk_get(&dev, NULL);
361 if (WARN_ON(IS_ERR(wd_clk))) 414 if (WARN_ON(IS_ERR(wd_clk)))
362 return; 415 return;
363 clk_enable(wd_clk); 416 clk_enable(wd_clk);
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-20 04:18:45 -0400