diff options
Diffstat (limited to 'arch/arm/mach-davinci')
19 files changed, 1566 insertions, 0 deletions
diff --git a/arch/arm/mach-davinci/gpio-tnetv107x.c b/arch/arm/mach-davinci/gpio-tnetv107x.c new file mode 100644 index 00000000000..3fa3e2867e1 --- /dev/null +++ b/arch/arm/mach-davinci/gpio-tnetv107x.c | |||
@@ -0,0 +1,205 @@ | |||
1 | /* | ||
2 | * Texas Instruments TNETV107X GPIO Controller | ||
3 | * | ||
4 | * Copyright (C) 2010 Texas Instruments | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or | ||
7 | * modify it under the terms of the GNU General Public License as | ||
8 | * published by the Free Software Foundation version 2. | ||
9 | * | ||
10 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | ||
11 | * kind, whether express or implied; without even the implied warranty | ||
12 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
13 | * GNU General Public License for more details. | ||
14 | */ | ||
15 | #include <linux/kernel.h> | ||
16 | #include <linux/init.h> | ||
17 | #include <linux/gpio.h> | ||
18 | |||
19 | #include <mach/common.h> | ||
20 | #include <mach/tnetv107x.h> | ||
21 | |||
22 | struct tnetv107x_gpio_regs { | ||
23 | u32 idver; | ||
24 | u32 data_in[3]; | ||
25 | u32 data_out[3]; | ||
26 | u32 direction[3]; | ||
27 | u32 enable[3]; | ||
28 | }; | ||
29 | |||
30 | #define gpio_reg_index(gpio) ((gpio) >> 5) | ||
31 | #define gpio_reg_bit(gpio) BIT((gpio) & 0x1f) | ||
32 | |||
33 | #define gpio_reg_rmw(reg, mask, val) \ | ||
34 | __raw_writel((__raw_readl(reg) & ~(mask)) | (val), (reg)) | ||
35 | |||
36 | #define gpio_reg_set_bit(reg, gpio) \ | ||
37 | gpio_reg_rmw((reg) + gpio_reg_index(gpio), 0, gpio_reg_bit(gpio)) | ||
38 | |||
39 | #define gpio_reg_clear_bit(reg, gpio) \ | ||
40 | gpio_reg_rmw((reg) + gpio_reg_index(gpio), gpio_reg_bit(gpio), 0) | ||
41 | |||
42 | #define gpio_reg_get_bit(reg, gpio) \ | ||
43 | (__raw_readl((reg) + gpio_reg_index(gpio)) & gpio_reg_bit(gpio)) | ||
44 | |||
45 | #define chip2controller(chip) \ | ||
46 | container_of(chip, struct davinci_gpio_controller, chip) | ||
47 | |||
48 | #define TNETV107X_GPIO_CTLRS DIV_ROUND_UP(TNETV107X_N_GPIO, 32) | ||
49 | |||
50 | static struct davinci_gpio_controller chips[TNETV107X_GPIO_CTLRS]; | ||
51 | |||
52 | static int tnetv107x_gpio_request(struct gpio_chip *chip, unsigned offset) | ||
53 | { | ||
54 | struct davinci_gpio_controller *ctlr = chip2controller(chip); | ||
55 | struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs; | ||
56 | unsigned gpio = chip->base + offset; | ||
57 | unsigned long flags; | ||
58 | |||
59 | spin_lock_irqsave(&ctlr->lock, flags); | ||
60 | |||
61 | gpio_reg_set_bit(regs->enable, gpio); | ||
62 | |||
63 | spin_unlock_irqrestore(&ctlr->lock, flags); | ||
64 | |||
65 | return 0; | ||
66 | } | ||
67 | |||
68 | static void tnetv107x_gpio_free(struct gpio_chip *chip, unsigned offset) | ||
69 | { | ||
70 | struct davinci_gpio_controller *ctlr = chip2controller(chip); | ||
71 | struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs; | ||
72 | unsigned gpio = chip->base + offset; | ||
73 | unsigned long flags; | ||
74 | |||
75 | spin_lock_irqsave(&ctlr->lock, flags); | ||
76 | |||
77 | gpio_reg_clear_bit(regs->enable, gpio); | ||
78 | |||
79 | spin_unlock_irqrestore(&ctlr->lock, flags); | ||
80 | } | ||
81 | |||
82 | static int tnetv107x_gpio_dir_in(struct gpio_chip *chip, unsigned offset) | ||
83 | { | ||
84 | struct davinci_gpio_controller *ctlr = chip2controller(chip); | ||
85 | struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs; | ||
86 | unsigned gpio = chip->base + offset; | ||
87 | unsigned long flags; | ||
88 | |||
89 | spin_lock_irqsave(&ctlr->lock, flags); | ||
90 | |||
91 | gpio_reg_set_bit(regs->direction, gpio); | ||
92 | |||
93 | spin_unlock_irqrestore(&ctlr->lock, flags); | ||
94 | |||
95 | return 0; | ||
96 | } | ||
97 | |||
98 | static int tnetv107x_gpio_dir_out(struct gpio_chip *chip, | ||
99 | unsigned offset, int value) | ||
100 | { | ||
101 | struct davinci_gpio_controller *ctlr = chip2controller(chip); | ||
102 | struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs; | ||
103 | unsigned gpio = chip->base + offset; | ||
104 | unsigned long flags; | ||
105 | |||
106 | spin_lock_irqsave(&ctlr->lock, flags); | ||
107 | |||
108 | if (value) | ||
109 | gpio_reg_set_bit(regs->data_out, gpio); | ||
110 | else | ||
111 | gpio_reg_clear_bit(regs->data_out, gpio); | ||
112 | |||
113 | gpio_reg_clear_bit(regs->direction, gpio); | ||
114 | |||
115 | spin_unlock_irqrestore(&ctlr->lock, flags); | ||
116 | |||
117 | return 0; | ||
118 | } | ||
119 | |||
120 | static int tnetv107x_gpio_get(struct gpio_chip *chip, unsigned offset) | ||
121 | { | ||
122 | struct davinci_gpio_controller *ctlr = chip2controller(chip); | ||
123 | struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs; | ||
124 | unsigned gpio = chip->base + offset; | ||
125 | int ret; | ||
126 | |||
127 | ret = gpio_reg_get_bit(regs->data_in, gpio); | ||
128 | |||
129 | return ret ? 1 : 0; | ||
130 | } | ||
131 | |||
132 | static void tnetv107x_gpio_set(struct gpio_chip *chip, | ||
133 | unsigned offset, int value) | ||
134 | { | ||
135 | struct davinci_gpio_controller *ctlr = chip2controller(chip); | ||
136 | struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs; | ||
137 | unsigned gpio = chip->base + offset; | ||
138 | unsigned long flags; | ||
139 | |||
140 | spin_lock_irqsave(&ctlr->lock, flags); | ||
141 | |||
142 | if (value) | ||
143 | gpio_reg_set_bit(regs->data_out, gpio); | ||
144 | else | ||
145 | gpio_reg_clear_bit(regs->data_out, gpio); | ||
146 | |||
147 | spin_unlock_irqrestore(&ctlr->lock, flags); | ||
148 | } | ||
149 | |||
150 | static int __init tnetv107x_gpio_setup(void) | ||
151 | { | ||
152 | int i, base; | ||
153 | unsigned ngpio; | ||
154 | struct davinci_soc_info *soc_info = &davinci_soc_info; | ||
155 | struct tnetv107x_gpio_regs *regs; | ||
156 | struct davinci_gpio_controller *ctlr; | ||
157 | |||
158 | if (soc_info->gpio_type != GPIO_TYPE_TNETV107X) | ||
159 | return 0; | ||
160 | |||
161 | ngpio = soc_info->gpio_num; | ||
162 | if (ngpio == 0) { | ||
163 | pr_err("GPIO setup: how many GPIOs?\n"); | ||
164 | return -EINVAL; | ||
165 | } | ||
166 | |||
167 | if (WARN_ON(TNETV107X_N_GPIO < ngpio)) | ||
168 | ngpio = TNETV107X_N_GPIO; | ||
169 | |||
170 | regs = ioremap(soc_info->gpio_base, SZ_4K); | ||
171 | if (WARN_ON(!regs)) | ||
172 | return -EINVAL; | ||
173 | |||
174 | for (i = 0, base = 0; base < ngpio; i++, base += 32) { | ||
175 | ctlr = &chips[i]; | ||
176 | |||
177 | ctlr->chip.label = "tnetv107x"; | ||
178 | ctlr->chip.can_sleep = 0; | ||
179 | ctlr->chip.base = base; | ||
180 | ctlr->chip.ngpio = ngpio - base; | ||
181 | if (ctlr->chip.ngpio > 32) | ||
182 | ctlr->chip.ngpio = 32; | ||
183 | |||
184 | ctlr->chip.request = tnetv107x_gpio_request; | ||
185 | ctlr->chip.free = tnetv107x_gpio_free; | ||
186 | ctlr->chip.direction_input = tnetv107x_gpio_dir_in; | ||
187 | ctlr->chip.get = tnetv107x_gpio_get; | ||
188 | ctlr->chip.direction_output = tnetv107x_gpio_dir_out; | ||
189 | ctlr->chip.set = tnetv107x_gpio_set; | ||
190 | |||
191 | spin_lock_init(&ctlr->lock); | ||
192 | |||
193 | ctlr->regs = regs; | ||
194 | ctlr->set_data = ®s->data_out[i]; | ||
195 | ctlr->clr_data = ®s->data_out[i]; | ||
196 | ctlr->in_data = ®s->data_in[i]; | ||
197 | |||
198 | gpiochip_add(&ctlr->chip); | ||
199 | } | ||
200 | |||
201 | soc_info->gpio_ctlrs = chips; | ||
202 | soc_info->gpio_ctlrs_num = DIV_ROUND_UP(ngpio, 32); | ||
203 | return 0; | ||
204 | } | ||
205 | pure_initcall(tnetv107x_gpio_setup); | ||
diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c new file mode 100644 index 00000000000..cafbe13a82a --- /dev/null +++ b/arch/arm/mach-davinci/gpio.c | |||
@@ -0,0 +1,460 @@ | |||
1 | /* | ||
2 | * TI DaVinci GPIO Support | ||
3 | * | ||
4 | * Copyright (c) 2006-2007 David Brownell | ||
5 | * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com> | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License as published by | ||
9 | * the Free Software Foundation; either version 2 of the License, or | ||
10 | * (at your option) any later version. | ||
11 | */ | ||
12 | |||
13 | #include <linux/errno.h> | ||
14 | #include <linux/kernel.h> | ||
15 | #include <linux/clk.h> | ||
16 | #include <linux/err.h> | ||
17 | #include <linux/io.h> | ||
18 | |||
19 | #include <mach/gpio.h> | ||
20 | |||
21 | #include <asm/mach/irq.h> | ||
22 | |||
23 | struct davinci_gpio_regs { | ||
24 | u32 dir; | ||
25 | u32 out_data; | ||
26 | u32 set_data; | ||
27 | u32 clr_data; | ||
28 | u32 in_data; | ||
29 | u32 set_rising; | ||
30 | u32 clr_rising; | ||
31 | u32 set_falling; | ||
32 | u32 clr_falling; | ||
33 | u32 intstat; | ||
34 | }; | ||
35 | |||
36 | #define chip2controller(chip) \ | ||
37 | container_of(chip, struct davinci_gpio_controller, chip) | ||
38 | |||
39 | static struct davinci_gpio_controller chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)]; | ||
40 | static void __iomem *gpio_base; | ||
41 | |||
42 | static struct davinci_gpio_regs __iomem __init *gpio2regs(unsigned gpio) | ||
43 | { | ||
44 | void __iomem *ptr; | ||
45 | |||
46 | if (gpio < 32 * 1) | ||
47 | ptr = gpio_base + 0x10; | ||
48 | else if (gpio < 32 * 2) | ||
49 | ptr = gpio_base + 0x38; | ||
50 | else if (gpio < 32 * 3) | ||
51 | ptr = gpio_base + 0x60; | ||
52 | else if (gpio < 32 * 4) | ||
53 | ptr = gpio_base + 0x88; | ||
54 | else if (gpio < 32 * 5) | ||
55 | ptr = gpio_base + 0xb0; | ||
56 | else | ||
57 | ptr = NULL; | ||
58 | return ptr; | ||
59 | } | ||
60 | |||
61 | static inline struct davinci_gpio_regs __iomem *irq2regs(int irq) | ||
62 | { | ||
63 | struct davinci_gpio_regs __iomem *g; | ||
64 | |||
65 | g = (__force struct davinci_gpio_regs __iomem *)irq_get_chip_data(irq); | ||
66 | |||
67 | return g; | ||
68 | } | ||
69 | |||
70 | static int __init davinci_gpio_irq_setup(void); | ||
71 | |||
72 | /*--------------------------------------------------------------------------*/ | ||
73 | |||
74 | /* board setup code *MUST* setup pinmux and enable the GPIO clock. */ | ||
75 | static inline int __davinci_direction(struct gpio_chip *chip, | ||
76 | unsigned offset, bool out, int value) | ||
77 | { | ||
78 | struct davinci_gpio_controller *d = chip2controller(chip); | ||
79 | struct davinci_gpio_regs __iomem *g = d->regs; | ||
80 | unsigned long flags; | ||
81 | u32 temp; | ||
82 | u32 mask = 1 << offset; | ||
83 | |||
84 | spin_lock_irqsave(&d->lock, flags); | ||
85 | temp = __raw_readl(&g->dir); | ||
86 | if (out) { | ||
87 | temp &= ~mask; | ||
88 | __raw_writel(mask, value ? &g->set_data : &g->clr_data); | ||
89 | } else { | ||
90 | temp |= mask; | ||
91 | } | ||
92 | __raw_writel(temp, &g->dir); | ||
93 | spin_unlock_irqrestore(&d->lock, flags); | ||
94 | |||
95 | return 0; | ||
96 | } | ||
97 | |||
98 | static int davinci_direction_in(struct gpio_chip *chip, unsigned offset) | ||
99 | { | ||
100 | return __davinci_direction(chip, offset, false, 0); | ||
101 | } | ||
102 | |||
103 | static int | ||
104 | davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value) | ||
105 | { | ||
106 | return __davinci_direction(chip, offset, true, value); | ||
107 | } | ||
108 | |||
109 | /* | ||
110 | * Read the pin's value (works even if it's set up as output); | ||
111 | * returns zero/nonzero. | ||
112 | * | ||
113 | * Note that changes are synched to the GPIO clock, so reading values back | ||
114 | * right after you've set them may give old values. | ||
115 | */ | ||
116 | static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset) | ||
117 | { | ||
118 | struct davinci_gpio_controller *d = chip2controller(chip); | ||
119 | struct davinci_gpio_regs __iomem *g = d->regs; | ||
120 | |||
121 | return (1 << offset) & __raw_readl(&g->in_data); | ||
122 | } | ||
123 | |||
124 | /* | ||
125 | * Assuming the pin is muxed as a gpio output, set its output value. | ||
126 | */ | ||
127 | static void | ||
128 | davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | ||
129 | { | ||
130 | struct davinci_gpio_controller *d = chip2controller(chip); | ||
131 | struct davinci_gpio_regs __iomem *g = d->regs; | ||
132 | |||
133 | __raw_writel((1 << offset), value ? &g->set_data : &g->clr_data); | ||
134 | } | ||
135 | |||
136 | static int __init davinci_gpio_setup(void) | ||
137 | { | ||
138 | int i, base; | ||
139 | unsigned ngpio; | ||
140 | struct davinci_soc_info *soc_info = &davinci_soc_info; | ||
141 | struct davinci_gpio_regs *regs; | ||
142 | |||
143 | if (soc_info->gpio_type != GPIO_TYPE_DAVINCI) | ||
144 | return 0; | ||
145 | |||
146 | /* | ||
147 | * The gpio banks conceptually expose a segmented bitmap, | ||
148 | * and "ngpio" is one more than the largest zero-based | ||
149 | * bit index that's valid. | ||
150 | */ | ||
151 | ngpio = soc_info->gpio_num; | ||
152 | if (ngpio == 0) { | ||
153 | pr_err("GPIO setup: how many GPIOs?\n"); | ||
154 | return -EINVAL; | ||
155 | } | ||
156 | |||
157 | if (WARN_ON(DAVINCI_N_GPIO < ngpio)) | ||
158 | ngpio = DAVINCI_N_GPIO; | ||
159 | |||
160 | gpio_base = ioremap(soc_info->gpio_base, SZ_4K); | ||
161 | if (WARN_ON(!gpio_base)) | ||
162 | return -ENOMEM; | ||
163 | |||
164 | for (i = 0, base = 0; base < ngpio; i++, base += 32) { | ||
165 | chips[i].chip.label = "DaVinci"; | ||
166 | |||
167 | chips[i].chip.direction_input = davinci_direction_in; | ||
168 | chips[i].chip.get = davinci_gpio_get; | ||
169 | chips[i].chip.direction_output = davinci_direction_out; | ||
170 | chips[i].chip.set = davinci_gpio_set; | ||
171 | |||
172 | chips[i].chip.base = base; | ||
173 | chips[i].chip.ngpio = ngpio - base; | ||
174 | if (chips[i].chip.ngpio > 32) | ||
175 | chips[i].chip.ngpio = 32; | ||
176 | |||
177 | spin_lock_init(&chips[i].lock); | ||
178 | |||
179 | regs = gpio2regs(base); | ||
180 | chips[i].regs = regs; | ||
181 | chips[i].set_data = ®s->set_data; | ||
182 | chips[i].clr_data = ®s->clr_data; | ||
183 | chips[i].in_data = ®s->in_data; | ||
184 | |||
185 | gpiochip_add(&chips[i].chip); | ||
186 | } | ||
187 | |||
188 | soc_info->gpio_ctlrs = chips; | ||
189 | soc_info->gpio_ctlrs_num = DIV_ROUND_UP(ngpio, 32); | ||
190 | |||
191 | davinci_gpio_irq_setup(); | ||
192 | return 0; | ||
193 | } | ||
194 | pure_initcall(davinci_gpio_setup); | ||
195 | |||
196 | /*--------------------------------------------------------------------------*/ | ||
197 | /* | ||
198 | * We expect irqs will normally be set up as input pins, but they can also be | ||
199 | * used as output pins ... which is convenient for testing. | ||
200 | * | ||
201 | * NOTE: The first few GPIOs also have direct INTC hookups in addition | ||
202 | * to their GPIOBNK0 irq, with a bit less overhead. | ||
203 | * | ||
204 | * All those INTC hookups (direct, plus several IRQ banks) can also | ||
205 | * serve as EDMA event triggers. | ||
206 | */ | ||
207 | |||
208 | static void gpio_irq_disable(struct irq_data *d) | ||
209 | { | ||
210 | struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); | ||
211 | u32 mask = (u32) irq_data_get_irq_handler_data(d); | ||
212 | |||
213 | __raw_writel(mask, &g->clr_falling); | ||
214 | __raw_writel(mask, &g->clr_rising); | ||
215 | } | ||
216 | |||
217 | static void gpio_irq_enable(struct irq_data *d) | ||
218 | { | ||
219 | struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); | ||
220 | u32 mask = (u32) irq_data_get_irq_handler_data(d); | ||
221 | unsigned status = irqd_get_trigger_type(d); | ||
222 | |||
223 | status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; | ||
224 | if (!status) | ||
225 | status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; | ||
226 | |||
227 | if (status & IRQ_TYPE_EDGE_FALLING) | ||
228 | __raw_writel(mask, &g->set_falling); | ||
229 | if (status & IRQ_TYPE_EDGE_RISING) | ||
230 | __raw_writel(mask, &g->set_rising); | ||
231 | } | ||
232 | |||
233 | static int gpio_irq_type(struct irq_data *d, unsigned trigger) | ||
234 | { | ||
235 | struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); | ||
236 | u32 mask = (u32) irq_data_get_irq_handler_data(d); | ||
237 | |||
238 | if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) | ||
239 | return -EINVAL; | ||
240 | |||
241 | return 0; | ||
242 | } | ||
243 | |||
244 | static struct irq_chip gpio_irqchip = { | ||
245 | .name = "GPIO", | ||
246 | .irq_enable = gpio_irq_enable, | ||
247 | .irq_disable = gpio_irq_disable, | ||
248 | .irq_set_type = gpio_irq_type, | ||
249 | .flags = IRQCHIP_SET_TYPE_MASKED, | ||
250 | }; | ||
251 | |||
252 | static void | ||
253 | gpio_irq_handler(unsigned irq, struct irq_desc *desc) | ||
254 | { | ||
255 | struct davinci_gpio_regs __iomem *g; | ||
256 | u32 mask = 0xffff; | ||
257 | struct davinci_gpio_controller *d; | ||
258 | |||
259 | d = (struct davinci_gpio_controller *)irq_desc_get_handler_data(desc); | ||
260 | g = (struct davinci_gpio_regs __iomem *)d->regs; | ||
261 | |||
262 | /* we only care about one bank */ | ||
263 | if (irq & 1) | ||
264 | mask <<= 16; | ||
265 | |||
266 | /* temporarily mask (level sensitive) parent IRQ */ | ||
267 | desc->irq_data.chip->irq_mask(&desc->irq_data); | ||
268 | desc->irq_data.chip->irq_ack(&desc->irq_data); | ||
269 | while (1) { | ||
270 | u32 status; | ||
271 | int n; | ||
272 | int res; | ||
273 | |||
274 | /* ack any irqs */ | ||
275 | status = __raw_readl(&g->intstat) & mask; | ||
276 | if (!status) | ||
277 | break; | ||
278 | __raw_writel(status, &g->intstat); | ||
279 | |||
280 | /* now demux them to the right lowlevel handler */ | ||
281 | n = d->irq_base; | ||
282 | if (irq & 1) { | ||
283 | n += 16; | ||
284 | status >>= 16; | ||
285 | } | ||
286 | |||
287 | while (status) { | ||
288 | res = ffs(status); | ||
289 | n += res; | ||
290 | generic_handle_irq(n - 1); | ||
291 | status >>= res; | ||
292 | } | ||
293 | } | ||
294 | desc->irq_data.chip->irq_unmask(&desc->irq_data); | ||
295 | /* now it may re-trigger */ | ||
296 | } | ||
297 | |||
298 | static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset) | ||
299 | { | ||
300 | struct davinci_gpio_controller *d = chip2controller(chip); | ||
301 | |||
302 | if (d->irq_base >= 0) | ||
303 | return d->irq_base + offset; | ||
304 | else | ||
305 | return -ENODEV; | ||
306 | } | ||
307 | |||
308 | static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset) | ||
309 | { | ||
310 | struct davinci_soc_info *soc_info = &davinci_soc_info; | ||
311 | |||
312 | /* NOTE: we assume for now that only irqs in the first gpio_chip | ||
313 | * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs). | ||
314 | */ | ||
315 | if (offset < soc_info->gpio_unbanked) | ||
316 | return soc_info->gpio_irq + offset; | ||
317 | else | ||
318 | return -ENODEV; | ||
319 | } | ||
320 | |||
321 | static int gpio_irq_type_unbanked(struct irq_data *d, unsigned trigger) | ||
322 | { | ||
323 | struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); | ||
324 | u32 mask = (u32) irq_data_get_irq_handler_data(d); | ||
325 | |||
326 | if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) | ||
327 | return -EINVAL; | ||
328 | |||
329 | __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING) | ||
330 | ? &g->set_falling : &g->clr_falling); | ||
331 | __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING) | ||
332 | ? &g->set_rising : &g->clr_rising); | ||
333 | |||
334 | return 0; | ||
335 | } | ||
336 | |||
337 | /* | ||
338 | * NOTE: for suspend/resume, probably best to make a platform_device with | ||
339 | * suspend_late/resume_resume calls hooking into results of the set_wake() | ||
340 | * calls ... so if no gpios are wakeup events the clock can be disabled, | ||
341 | * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0 | ||
342 | * (dm6446) can be set appropriately for GPIOV33 pins. | ||
343 | */ | ||
344 | |||
345 | static int __init davinci_gpio_irq_setup(void) | ||
346 | { | ||
347 | unsigned gpio, irq, bank; | ||
348 | struct clk *clk; | ||
349 | u32 binten = 0; | ||
350 | unsigned ngpio, bank_irq; | ||
351 | struct davinci_soc_info *soc_info = &davinci_soc_info; | ||
352 | struct davinci_gpio_regs __iomem *g; | ||
353 | |||
354 | ngpio = soc_info->gpio_num; | ||
355 | |||
356 | bank_irq = soc_info->gpio_irq; | ||
357 | if (bank_irq == 0) { | ||
358 | printk(KERN_ERR "Don't know first GPIO bank IRQ.\n"); | ||
359 | return -EINVAL; | ||
360 | } | ||
361 | |||
362 | clk = clk_get(NULL, "gpio"); | ||
363 | if (IS_ERR(clk)) { | ||
364 | printk(KERN_ERR "Error %ld getting gpio clock?\n", | ||
365 | PTR_ERR(clk)); | ||
366 | return PTR_ERR(clk); | ||
367 | } | ||
368 | clk_enable(clk); | ||
369 | |||
370 | /* Arrange gpio_to_irq() support, handling either direct IRQs or | ||
371 | * banked IRQs. Having GPIOs in the first GPIO bank use direct | ||
372 | * IRQs, while the others use banked IRQs, would need some setup | ||
373 | * tweaks to recognize hardware which can do that. | ||
374 | */ | ||
375 | for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) { | ||
376 | chips[bank].chip.to_irq = gpio_to_irq_banked; | ||
377 | chips[bank].irq_base = soc_info->gpio_unbanked | ||
378 | ? -EINVAL | ||
379 | : (soc_info->intc_irq_num + gpio); | ||
380 | } | ||
381 | |||
382 | /* | ||
383 | * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO | ||
384 | * controller only handling trigger modes. We currently assume no | ||
385 | * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs. | ||
386 | */ | ||
387 | if (soc_info->gpio_unbanked) { | ||
388 | static struct irq_chip gpio_irqchip_unbanked; | ||
389 | |||
390 | /* pass "bank 0" GPIO IRQs to AINTC */ | ||
391 | chips[0].chip.to_irq = gpio_to_irq_unbanked; | ||
392 | binten = BIT(0); | ||
393 | |||
394 | /* AINTC handles mask/unmask; GPIO handles triggering */ | ||
395 | irq = bank_irq; | ||
396 | gpio_irqchip_unbanked = *irq_get_chip(irq); | ||
397 | gpio_irqchip_unbanked.name = "GPIO-AINTC"; | ||
398 | gpio_irqchip_unbanked.irq_set_type = gpio_irq_type_unbanked; | ||
399 | |||
400 | /* default trigger: both edges */ | ||
401 | g = gpio2regs(0); | ||
402 | __raw_writel(~0, &g->set_falling); | ||
403 | __raw_writel(~0, &g->set_rising); | ||
404 | |||
405 | /* set the direct IRQs up to use that irqchip */ | ||
406 | for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) { | ||
407 | irq_set_chip(irq, &gpio_irqchip_unbanked); | ||
408 | irq_set_handler_data(irq, (void *)__gpio_mask(gpio)); | ||
409 | irq_set_chip_data(irq, (__force void *)g); | ||
410 | irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH); | ||
411 | } | ||
412 | |||
413 | goto done; | ||
414 | } | ||
415 | |||
416 | /* | ||
417 | * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we | ||
418 | * then chain through our own handler. | ||
419 | */ | ||
420 | for (gpio = 0, irq = gpio_to_irq(0), bank = 0; | ||
421 | gpio < ngpio; | ||
422 | bank++, bank_irq++) { | ||
423 | unsigned i; | ||
424 | |||
425 | /* disabled by default, enabled only as needed */ | ||
426 | g = gpio2regs(gpio); | ||
427 | __raw_writel(~0, &g->clr_falling); | ||
428 | __raw_writel(~0, &g->clr_rising); | ||
429 | |||
430 | /* set up all irqs in this bank */ | ||
431 | irq_set_chained_handler(bank_irq, gpio_irq_handler); | ||
432 | |||
433 | /* | ||
434 | * Each chip handles 32 gpios, and each irq bank consists of 16 | ||
435 | * gpio irqs. Pass the irq bank's corresponding controller to | ||
436 | * the chained irq handler. | ||
437 | */ | ||
438 | irq_set_handler_data(bank_irq, &chips[gpio / 32]); | ||
439 | |||
440 | for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) { | ||
441 | irq_set_chip(irq, &gpio_irqchip); | ||
442 | irq_set_chip_data(irq, (__force void *)g); | ||
443 | irq_set_handler_data(irq, (void *)__gpio_mask(gpio)); | ||
444 | irq_set_handler(irq, handle_simple_irq); | ||
445 | set_irq_flags(irq, IRQF_VALID); | ||
446 | } | ||
447 | |||
448 | binten |= BIT(bank); | ||
449 | } | ||
450 | |||
451 | done: | ||
452 | /* BINTEN -- per-bank interrupt enable. genirq would also let these | ||
453 | * bits be set/cleared dynamically. | ||
454 | */ | ||
455 | __raw_writel(binten, gpio_base + 0x08); | ||
456 | |||
457 | printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0)); | ||
458 | |||
459 | return 0; | ||
460 | } | ||
diff --git a/arch/arm/mach-davinci/include/mach/aemif.h b/arch/arm/mach-davinci/include/mach/aemif.h new file mode 100644 index 00000000000..05b29344309 --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/aemif.h | |||
@@ -0,0 +1,36 @@ | |||
1 | /* | ||
2 | * TI DaVinci AEMIF support | ||
3 | * | ||
4 | * Copyright 2010 (C) Texas Instruments, Inc. http://www.ti.com/ | ||
5 | * | ||
6 | * This file is licensed under the terms of the GNU General Public License | ||
7 | * version 2. This program is licensed "as is" without any warranty of any | ||
8 | * kind, whether express or implied. | ||
9 | */ | ||
10 | #ifndef _MACH_DAVINCI_AEMIF_H | ||
11 | #define _MACH_DAVINCI_AEMIF_H | ||
12 | |||
13 | #define NRCSR_OFFSET 0x00 | ||
14 | #define AWCCR_OFFSET 0x04 | ||
15 | #define A1CR_OFFSET 0x10 | ||
16 | |||
17 | #define ACR_ASIZE_MASK 0x3 | ||
18 | #define ACR_EW_MASK BIT(30) | ||
19 | #define ACR_SS_MASK BIT(31) | ||
20 | |||
21 | /* All timings in nanoseconds */ | ||
22 | struct davinci_aemif_timing { | ||
23 | u8 wsetup; | ||
24 | u8 wstrobe; | ||
25 | u8 whold; | ||
26 | |||
27 | u8 rsetup; | ||
28 | u8 rstrobe; | ||
29 | u8 rhold; | ||
30 | |||
31 | u8 ta; | ||
32 | }; | ||
33 | |||
34 | int davinci_aemif_setup_timing(struct davinci_aemif_timing *t, | ||
35 | void __iomem *base, unsigned cs); | ||
36 | #endif | ||
diff --git a/arch/arm/mach-davinci/include/mach/asp.h b/arch/arm/mach-davinci/include/mach/asp.h new file mode 100644 index 00000000000..9aa240909a2 --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/asp.h | |||
@@ -0,0 +1,137 @@ | |||
1 | /* | ||
2 | * <mach/asp.h> - DaVinci Audio Serial Port support | ||
3 | */ | ||
4 | #ifndef __ASM_ARCH_DAVINCI_ASP_H | ||
5 | #define __ASM_ARCH_DAVINCI_ASP_H | ||
6 | |||
7 | #include <mach/irqs.h> | ||
8 | #include <mach/edma.h> | ||
9 | |||
10 | /* Bases of dm644x and dm355 register banks */ | ||
11 | #define DAVINCI_ASP0_BASE 0x01E02000 | ||
12 | #define DAVINCI_ASP1_BASE 0x01E04000 | ||
13 | |||
14 | /* Bases of dm365 register banks */ | ||
15 | #define DAVINCI_DM365_ASP0_BASE 0x01D02000 | ||
16 | |||
17 | /* Bases of dm646x register banks */ | ||
18 | #define DAVINCI_DM646X_MCASP0_REG_BASE 0x01D01000 | ||
19 | #define DAVINCI_DM646X_MCASP1_REG_BASE 0x01D01800 | ||
20 | |||
21 | /* Bases of da850/da830 McASP0 register banks */ | ||
22 | #define DAVINCI_DA8XX_MCASP0_REG_BASE 0x01D00000 | ||
23 | |||
24 | /* Bases of da830 McASP1 register banks */ | ||
25 | #define DAVINCI_DA830_MCASP1_REG_BASE 0x01D04000 | ||
26 | |||
27 | /* EDMA channels of dm644x and dm355 */ | ||
28 | #define DAVINCI_DMA_ASP0_TX 2 | ||
29 | #define DAVINCI_DMA_ASP0_RX 3 | ||
30 | #define DAVINCI_DMA_ASP1_TX 8 | ||
31 | #define DAVINCI_DMA_ASP1_RX 9 | ||
32 | |||
33 | /* EDMA channels of dm646x */ | ||
34 | #define DAVINCI_DM646X_DMA_MCASP0_AXEVT0 6 | ||
35 | #define DAVINCI_DM646X_DMA_MCASP0_AREVT0 9 | ||
36 | #define DAVINCI_DM646X_DMA_MCASP1_AXEVT1 12 | ||
37 | |||
38 | /* EDMA channels of da850/da830 McASP0 */ | ||
39 | #define DAVINCI_DA8XX_DMA_MCASP0_AREVT 0 | ||
40 | #define DAVINCI_DA8XX_DMA_MCASP0_AXEVT 1 | ||
41 | |||
42 | /* EDMA channels of da830 McASP1 */ | ||
43 | #define DAVINCI_DA830_DMA_MCASP1_AREVT 2 | ||
44 | #define DAVINCI_DA830_DMA_MCASP1_AXEVT 3 | ||
45 | |||
46 | /* Interrupts */ | ||
47 | #define DAVINCI_ASP0_RX_INT IRQ_MBRINT | ||
48 | #define DAVINCI_ASP0_TX_INT IRQ_MBXINT | ||
49 | #define DAVINCI_ASP1_RX_INT IRQ_MBRINT | ||
50 | #define DAVINCI_ASP1_TX_INT IRQ_MBXINT | ||
51 | |||
52 | struct snd_platform_data { | ||
53 | u32 tx_dma_offset; | ||
54 | u32 rx_dma_offset; | ||
55 | enum dma_event_q asp_chan_q; /* event queue number for ASP channel */ | ||
56 | enum dma_event_q ram_chan_q; /* event queue number for RAM channel */ | ||
57 | unsigned int codec_fmt; | ||
58 | /* | ||
59 | * Allowing this is more efficient and eliminates left and right swaps | ||
60 | * caused by underruns, but will swap the left and right channels | ||
61 | * when compared to previous behavior. | ||
62 | */ | ||
63 | unsigned enable_channel_combine:1; | ||
64 | unsigned sram_size_playback; | ||
65 | unsigned sram_size_capture; | ||
66 | |||
67 | /* | ||
68 | * If McBSP peripheral gets the clock from an external pin, | ||
69 | * there are three chooses, that are MCBSP_CLKX, MCBSP_CLKR | ||
70 | * and MCBSP_CLKS. | ||
71 | * Depending on different hardware connections it is possible | ||
72 | * to use this setting to change the behaviour of McBSP | ||
73 | * driver. The dm365_clk_input_pin enum is available for dm365 | ||
74 | */ | ||
75 | int clk_input_pin; | ||
76 | |||
77 | /* | ||
78 | * This flag works when both clock and FS are outputs for the cpu | ||
79 | * and makes clock more accurate (FS is not symmetrical and the | ||
80 | * clock is very fast. | ||
81 | * The clock becoming faster is named | ||
82 | * i2s continuous serial clock (I2S_SCK) and it is an externally | ||
83 | * visible bit clock. | ||
84 | * | ||
85 | * first line : WordSelect | ||
86 | * second line : ContinuousSerialClock | ||
87 | * third line: SerialData | ||
88 | * | ||
89 | * SYMMETRICAL APPROACH: | ||
90 | * _______________________ LEFT | ||
91 | * _| RIGHT |______________________| | ||
92 | * _ _ _ _ _ _ _ _ | ||
93 | * _| |_| |_ x16 _| |_| |_| |_| |_ x16 _| |_| |_ | ||
94 | * _ _ _ _ _ _ _ _ | ||
95 | * _/ \_/ \_ ... _/ \_/ \_/ \_/ \_ ... _/ \_/ \_ | ||
96 | * \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ | ||
97 | * | ||
98 | * ACCURATE CLOCK APPROACH: | ||
99 | * ______________ LEFT | ||
100 | * _| RIGHT |_______________________________| | ||
101 | * _ _ _ _ _ _ _ _ _ | ||
102 | * _| |_ x16 _| |_| |_ x16 _| |_| |_| |_| |_| |_| | | ||
103 | * _ _ _ _ dummy cycles | ||
104 | * _/ \_ ... _/ \_/ \_ ... _/ \__________________ | ||
105 | * \_/ \_/ \_/ \_/ | ||
106 | * | ||
107 | */ | ||
108 | bool i2s_accurate_sck; | ||
109 | |||
110 | /* McASP specific fields */ | ||
111 | int tdm_slots; | ||
112 | u8 op_mode; | ||
113 | u8 num_serializer; | ||
114 | u8 *serial_dir; | ||
115 | u8 version; | ||
116 | u8 txnumevt; | ||
117 | u8 rxnumevt; | ||
118 | }; | ||
119 | |||
120 | enum { | ||
121 | MCASP_VERSION_1 = 0, /* DM646x */ | ||
122 | MCASP_VERSION_2, /* DA8xx/OMAPL1x */ | ||
123 | }; | ||
124 | |||
125 | enum dm365_clk_input_pin { | ||
126 | MCBSP_CLKR = 0, /* DM365 */ | ||
127 | MCBSP_CLKS, | ||
128 | }; | ||
129 | |||
130 | #define INACTIVE_MODE 0 | ||
131 | #define TX_MODE 1 | ||
132 | #define RX_MODE 2 | ||
133 | |||
134 | #define DAVINCI_MCASP_IIS_MODE 0 | ||
135 | #define DAVINCI_MCASP_DIT_MODE 1 | ||
136 | |||
137 | #endif /* __ASM_ARCH_DAVINCI_ASP_H */ | ||
diff --git a/arch/arm/mach-davinci/include/mach/dm355.h b/arch/arm/mach-davinci/include/mach/dm355.h new file mode 100644 index 00000000000..36dff4a0ce3 --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/dm355.h | |||
@@ -0,0 +1,32 @@ | |||
1 | /* | ||
2 | * Chip specific defines for DM355 SoC | ||
3 | * | ||
4 | * Author: Kevin Hilman, Deep Root Systems, LLC | ||
5 | * | ||
6 | * 2007 (c) Deep Root Systems, LLC. This file is licensed under | ||
7 | * the terms of the GNU General Public License version 2. This program | ||
8 | * is licensed "as is" without any warranty of any kind, whether express | ||
9 | * or implied. | ||
10 | */ | ||
11 | #ifndef __ASM_ARCH_DM355_H | ||
12 | #define __ASM_ARCH_DM355_H | ||
13 | |||
14 | #include <mach/hardware.h> | ||
15 | #include <mach/asp.h> | ||
16 | #include <media/davinci/vpfe_capture.h> | ||
17 | |||
18 | #define DM355_ASYNC_EMIF_CONTROL_BASE 0x01E10000 | ||
19 | #define DM355_ASYNC_EMIF_DATA_CE0_BASE 0x02000000 | ||
20 | |||
21 | #define ASP1_TX_EVT_EN 1 | ||
22 | #define ASP1_RX_EVT_EN 2 | ||
23 | |||
24 | struct spi_board_info; | ||
25 | |||
26 | void __init dm355_init(void); | ||
27 | void dm355_init_spi0(unsigned chipselect_mask, | ||
28 | struct spi_board_info *info, unsigned len); | ||
29 | void __init dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata); | ||
30 | void dm355_set_vpfe_config(struct vpfe_config *cfg); | ||
31 | |||
32 | #endif /* __ASM_ARCH_DM355_H */ | ||
diff --git a/arch/arm/mach-davinci/include/mach/dm365.h b/arch/arm/mach-davinci/include/mach/dm365.h new file mode 100644 index 00000000000..2563bf4e93a --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/dm365.h | |||
@@ -0,0 +1,52 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2009 Texas Instruments Incorporated | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or | ||
5 | * modify it under the terms of the GNU General Public License as | ||
6 | * published by the Free Software Foundation version 2. | ||
7 | * | ||
8 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | ||
9 | * kind, whether express or implied; without even the implied warranty | ||
10 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
11 | * GNU General Public License for more details. | ||
12 | */ | ||
13 | #ifndef __ASM_ARCH_DM365_H | ||
14 | #define __ASM_ARCH_DM665_H | ||
15 | |||
16 | #include <linux/platform_device.h> | ||
17 | #include <linux/davinci_emac.h> | ||
18 | #include <mach/hardware.h> | ||
19 | #include <mach/asp.h> | ||
20 | #include <mach/keyscan.h> | ||
21 | #include <media/davinci/vpfe_capture.h> | ||
22 | |||
23 | #define DM365_EMAC_BASE (0x01D07000) | ||
24 | #define DM365_EMAC_MDIO_BASE (DM365_EMAC_BASE + 0x4000) | ||
25 | #define DM365_EMAC_CNTRL_OFFSET (0x0000) | ||
26 | #define DM365_EMAC_CNTRL_MOD_OFFSET (0x3000) | ||
27 | #define DM365_EMAC_CNTRL_RAM_OFFSET (0x1000) | ||
28 | #define DM365_EMAC_CNTRL_RAM_SIZE (0x2000) | ||
29 | |||
30 | /* Base of key scan register bank */ | ||
31 | #define DM365_KEYSCAN_BASE (0x01C69400) | ||
32 | |||
33 | #define DM365_RTC_BASE (0x01C69000) | ||
34 | |||
35 | #define DAVINCI_DM365_VC_BASE (0x01D0C000) | ||
36 | #define DAVINCI_DMA_VC_TX 2 | ||
37 | #define DAVINCI_DMA_VC_RX 3 | ||
38 | |||
39 | #define DM365_ASYNC_EMIF_CONTROL_BASE 0x01D10000 | ||
40 | #define DM365_ASYNC_EMIF_DATA_CE0_BASE 0x02000000 | ||
41 | #define DM365_ASYNC_EMIF_DATA_CE1_BASE 0x04000000 | ||
42 | |||
43 | void __init dm365_init(void); | ||
44 | void __init dm365_init_asp(struct snd_platform_data *pdata); | ||
45 | void __init dm365_init_vc(struct snd_platform_data *pdata); | ||
46 | void __init dm365_init_ks(struct davinci_ks_platform_data *pdata); | ||
47 | void __init dm365_init_rtc(void); | ||
48 | void dm365_init_spi0(unsigned chipselect_mask, | ||
49 | struct spi_board_info *info, unsigned len); | ||
50 | |||
51 | void dm365_set_vpfe_config(struct vpfe_config *cfg); | ||
52 | #endif /* __ASM_ARCH_DM365_H */ | ||
diff --git a/arch/arm/mach-davinci/include/mach/dm644x.h b/arch/arm/mach-davinci/include/mach/dm644x.h new file mode 100644 index 00000000000..5a1b26d4e68 --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/dm644x.h | |||
@@ -0,0 +1,47 @@ | |||
1 | /* | ||
2 | * This file contains the processor specific definitions | ||
3 | * of the TI DM644x. | ||
4 | * | ||
5 | * Copyright (C) 2008 Texas Instruments. | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License as published by | ||
9 | * the Free Software Foundation; either version 2 of the License, or | ||
10 | * (at your option) any later version. | ||
11 | * | ||
12 | * This program is distributed in the hope that it will be useful, | ||
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
15 | * GNU General Public License for more details. | ||
16 | * | ||
17 | * You should have received a copy of the GNU General Public License | ||
18 | * along with this program; if not, write to the Free Software | ||
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
20 | * | ||
21 | */ | ||
22 | #ifndef __ASM_ARCH_DM644X_H | ||
23 | #define __ASM_ARCH_DM644X_H | ||
24 | |||
25 | #include <linux/davinci_emac.h> | ||
26 | #include <mach/hardware.h> | ||
27 | #include <mach/asp.h> | ||
28 | #include <media/davinci/vpfe_capture.h> | ||
29 | |||
30 | #define DM644X_EMAC_BASE (0x01C80000) | ||
31 | #define DM644X_EMAC_MDIO_BASE (DM644X_EMAC_BASE + 0x4000) | ||
32 | #define DM644X_EMAC_CNTRL_OFFSET (0x0000) | ||
33 | #define DM644X_EMAC_CNTRL_MOD_OFFSET (0x1000) | ||
34 | #define DM644X_EMAC_CNTRL_RAM_OFFSET (0x2000) | ||
35 | #define DM644X_EMAC_CNTRL_RAM_SIZE (0x2000) | ||
36 | |||
37 | #define DM644X_ASYNC_EMIF_CONTROL_BASE 0x01E00000 | ||
38 | #define DM644X_ASYNC_EMIF_DATA_CE0_BASE 0x02000000 | ||
39 | #define DM644X_ASYNC_EMIF_DATA_CE1_BASE 0x04000000 | ||
40 | #define DM644X_ASYNC_EMIF_DATA_CE2_BASE 0x06000000 | ||
41 | #define DM644X_ASYNC_EMIF_DATA_CE3_BASE 0x08000000 | ||
42 | |||
43 | void __init dm644x_init(void); | ||
44 | void __init dm644x_init_asp(struct snd_platform_data *pdata); | ||
45 | void dm644x_set_vpfe_config(struct vpfe_config *cfg); | ||
46 | |||
47 | #endif /* __ASM_ARCH_DM644X_H */ | ||
diff --git a/arch/arm/mach-davinci/include/mach/dm646x.h b/arch/arm/mach-davinci/include/mach/dm646x.h new file mode 100644 index 00000000000..2a00fe5ac25 --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/dm646x.h | |||
@@ -0,0 +1,92 @@ | |||
1 | /* | ||
2 | * Chip specific defines for DM646x SoC | ||
3 | * | ||
4 | * Author: Kevin Hilman, Deep Root Systems, LLC | ||
5 | * | ||
6 | * 2007 (c) Deep Root Systems, LLC. This file is licensed under | ||
7 | * the terms of the GNU General Public License version 2. This program | ||
8 | * is licensed "as is" without any warranty of any kind, whether express | ||
9 | * or implied. | ||
10 | */ | ||
11 | #ifndef __ASM_ARCH_DM646X_H | ||
12 | #define __ASM_ARCH_DM646X_H | ||
13 | |||
14 | #include <mach/hardware.h> | ||
15 | #include <mach/asp.h> | ||
16 | #include <linux/i2c.h> | ||
17 | #include <linux/videodev2.h> | ||
18 | #include <linux/davinci_emac.h> | ||
19 | |||
20 | #define DM646X_EMAC_BASE (0x01C80000) | ||
21 | #define DM646X_EMAC_MDIO_BASE (DM646X_EMAC_BASE + 0x4000) | ||
22 | #define DM646X_EMAC_CNTRL_OFFSET (0x0000) | ||
23 | #define DM646X_EMAC_CNTRL_MOD_OFFSET (0x1000) | ||
24 | #define DM646X_EMAC_CNTRL_RAM_OFFSET (0x2000) | ||
25 | #define DM646X_EMAC_CNTRL_RAM_SIZE (0x2000) | ||
26 | |||
27 | #define DM646X_ASYNC_EMIF_CONTROL_BASE 0x20008000 | ||
28 | #define DM646X_ASYNC_EMIF_CS2_SPACE_BASE 0x42000000 | ||
29 | |||
30 | void __init dm646x_init(void); | ||
31 | void __init dm646x_init_mcasp0(struct snd_platform_data *pdata); | ||
32 | void __init dm646x_init_mcasp1(struct snd_platform_data *pdata); | ||
33 | int __init dm646x_init_edma(struct edma_rsv_info *rsv); | ||
34 | |||
35 | void dm646x_video_init(void); | ||
36 | |||
37 | enum vpif_if_type { | ||
38 | VPIF_IF_BT656, | ||
39 | VPIF_IF_BT1120, | ||
40 | VPIF_IF_RAW_BAYER | ||
41 | }; | ||
42 | |||
43 | struct vpif_interface { | ||
44 | enum vpif_if_type if_type; | ||
45 | unsigned hd_pol:1; | ||
46 | unsigned vd_pol:1; | ||
47 | unsigned fid_pol:1; | ||
48 | }; | ||
49 | |||
50 | struct vpif_subdev_info { | ||
51 | const char *name; | ||
52 | struct i2c_board_info board_info; | ||
53 | u32 input; | ||
54 | u32 output; | ||
55 | unsigned can_route:1; | ||
56 | struct vpif_interface vpif_if; | ||
57 | }; | ||
58 | |||
59 | struct vpif_display_config { | ||
60 | int (*set_clock)(int, int); | ||
61 | struct vpif_subdev_info *subdevinfo; | ||
62 | int subdev_count; | ||
63 | const char **output; | ||
64 | int output_count; | ||
65 | const char *card_name; | ||
66 | }; | ||
67 | |||
68 | struct vpif_input { | ||
69 | struct v4l2_input input; | ||
70 | const char *subdev_name; | ||
71 | }; | ||
72 | |||
73 | #define VPIF_CAPTURE_MAX_CHANNELS 2 | ||
74 | |||
75 | struct vpif_capture_chan_config { | ||
76 | const struct vpif_input *inputs; | ||
77 | int input_count; | ||
78 | }; | ||
79 | |||
80 | struct vpif_capture_config { | ||
81 | int (*setup_input_channel_mode)(int); | ||
82 | int (*setup_input_path)(int, const char *); | ||
83 | struct vpif_capture_chan_config chan_config[VPIF_CAPTURE_MAX_CHANNELS]; | ||
84 | struct vpif_subdev_info *subdev_info; | ||
85 | int subdev_count; | ||
86 | const char *card_name; | ||
87 | }; | ||
88 | |||
89 | void dm646x_setup_vpif(struct vpif_display_config *, | ||
90 | struct vpif_capture_config *); | ||
91 | |||
92 | #endif /* __ASM_ARCH_DM646X_H */ | ||
diff --git a/arch/arm/mach-davinci/include/mach/i2c.h b/arch/arm/mach-davinci/include/mach/i2c.h new file mode 100644 index 00000000000..2312d197dfb --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/i2c.h | |||
@@ -0,0 +1,26 @@ | |||
1 | /* | ||
2 | * DaVinci I2C controller platform_device info | ||
3 | * | ||
4 | * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com> | ||
5 | * | ||
6 | * 2007 (c) MontaVista Software, Inc. This file is licensed under | ||
7 | * the terms of the GNU General Public License version 2. This program | ||
8 | * is licensed "as is" without any warranty of any kind, whether express | ||
9 | * or implied. | ||
10 | */ | ||
11 | |||
12 | #ifndef __ASM_ARCH_I2C_H | ||
13 | #define __ASM_ARCH_I2C_H | ||
14 | |||
15 | /* All frequencies are expressed in kHz */ | ||
16 | struct davinci_i2c_platform_data { | ||
17 | unsigned int bus_freq; /* standard bus frequency (kHz) */ | ||
18 | unsigned int bus_delay; /* post-transaction delay (usec) */ | ||
19 | unsigned int sda_pin; /* GPIO pin ID to use for SDA */ | ||
20 | unsigned int scl_pin; /* GPIO pin ID to use for SCL */ | ||
21 | }; | ||
22 | |||
23 | /* for board setup code */ | ||
24 | void davinci_init_i2c(struct davinci_i2c_platform_data *); | ||
25 | |||
26 | #endif /* __ASM_ARCH_I2C_H */ | ||
diff --git a/arch/arm/mach-davinci/include/mach/io.h b/arch/arm/mach-davinci/include/mach/io.h new file mode 100644 index 00000000000..d1b954955c1 --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/io.h | |||
@@ -0,0 +1,32 @@ | |||
1 | /* | ||
2 | * DaVinci IO address definitions | ||
3 | * | ||
4 | * Copied from include/asm/arm/arch-omap/io.h | ||
5 | * | ||
6 | * 2007 (c) MontaVista Software, Inc. This file is licensed under | ||
7 | * the terms of the GNU General Public License version 2. This program | ||
8 | * is licensed "as is" without any warranty of any kind, whether express | ||
9 | * or implied. | ||
10 | */ | ||
11 | #ifndef __ASM_ARCH_IO_H | ||
12 | #define __ASM_ARCH_IO_H | ||
13 | |||
14 | #define IO_SPACE_LIMIT 0xffffffff | ||
15 | |||
16 | /* | ||
17 | * We don't actually have real ISA nor PCI buses, but there is so many | ||
18 | * drivers out there that might just work if we fake them... | ||
19 | */ | ||
20 | #define __io(a) __typesafe_io(a) | ||
21 | #define __mem_pci(a) (a) | ||
22 | #define __mem_isa(a) (a) | ||
23 | |||
24 | #ifndef __ASSEMBLER__ | ||
25 | #define __arch_ioremap davinci_ioremap | ||
26 | #define __arch_iounmap davinci_iounmap | ||
27 | |||
28 | void __iomem *davinci_ioremap(unsigned long phys, size_t size, | ||
29 | unsigned int type); | ||
30 | void davinci_iounmap(volatile void __iomem *addr); | ||
31 | #endif | ||
32 | #endif /* __ASM_ARCH_IO_H */ | ||
diff --git a/arch/arm/mach-davinci/include/mach/keyscan.h b/arch/arm/mach-davinci/include/mach/keyscan.h new file mode 100644 index 00000000000..7a560e05bda --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/keyscan.h | |||
@@ -0,0 +1,42 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2009 Texas Instruments, Inc | ||
3 | * | ||
4 | * Author: Miguel Aguilar <miguel.aguilar@ridgerun.com> | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License as published by | ||
8 | * the Free Software Foundation; either version 2 of the License, or | ||
9 | * (at your option) any later version. | ||
10 | * | ||
11 | * This program is distributed in the hope that it will be useful, | ||
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
14 | * GNU General Public License for more details. | ||
15 | * | ||
16 | * You should have received a copy of the GNU General Public License | ||
17 | * along with this program; if not, write to the Free Software | ||
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
19 | */ | ||
20 | |||
21 | #ifndef DAVINCI_KEYSCAN_H | ||
22 | #define DAVINCI_KEYSCAN_H | ||
23 | |||
24 | #include <linux/io.h> | ||
25 | |||
26 | enum davinci_matrix_types { | ||
27 | DAVINCI_KEYSCAN_MATRIX_4X4, | ||
28 | DAVINCI_KEYSCAN_MATRIX_5X3, | ||
29 | }; | ||
30 | |||
31 | struct davinci_ks_platform_data { | ||
32 | int (*device_enable)(struct device *dev); | ||
33 | unsigned short *keymap; | ||
34 | u32 keymapsize; | ||
35 | u8 rep:1; | ||
36 | u8 strobe; | ||
37 | u8 interval; | ||
38 | u8 matrix_type; | ||
39 | }; | ||
40 | |||
41 | #endif | ||
42 | |||
diff --git a/arch/arm/mach-davinci/include/mach/memory.h b/arch/arm/mach-davinci/include/mach/memory.h new file mode 100644 index 00000000000..78731944a70 --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/memory.h | |||
@@ -0,0 +1,44 @@ | |||
1 | /* | ||
2 | * DaVinci memory space definitions | ||
3 | * | ||
4 | * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> | ||
5 | * | ||
6 | * 2007 (c) MontaVista Software, Inc. This file is licensed under | ||
7 | * the terms of the GNU General Public License version 2. This program | ||
8 | * is licensed "as is" without any warranty of any kind, whether express | ||
9 | * or implied. | ||
10 | */ | ||
11 | #ifndef __ASM_ARCH_MEMORY_H | ||
12 | #define __ASM_ARCH_MEMORY_H | ||
13 | |||
14 | /************************************************************************** | ||
15 | * Included Files | ||
16 | **************************************************************************/ | ||
17 | #include <asm/page.h> | ||
18 | #include <asm/sizes.h> | ||
19 | |||
20 | /************************************************************************** | ||
21 | * Definitions | ||
22 | **************************************************************************/ | ||
23 | #define DAVINCI_DDR_BASE 0x80000000 | ||
24 | #define DA8XX_DDR_BASE 0xc0000000 | ||
25 | |||
26 | #if defined(CONFIG_ARCH_DAVINCI_DA8XX) && defined(CONFIG_ARCH_DAVINCI_DMx) | ||
27 | #error Cannot enable DaVinci and DA8XX platforms concurrently | ||
28 | #elif defined(CONFIG_ARCH_DAVINCI_DA8XX) | ||
29 | #define PLAT_PHYS_OFFSET DA8XX_DDR_BASE | ||
30 | #else | ||
31 | #define PLAT_PHYS_OFFSET DAVINCI_DDR_BASE | ||
32 | #endif | ||
33 | |||
34 | #define DDR2_SDRCR_OFFSET 0xc | ||
35 | #define DDR2_SRPD_BIT BIT(23) | ||
36 | #define DDR2_MCLKSTOPEN_BIT BIT(30) | ||
37 | #define DDR2_LPMODEN_BIT BIT(31) | ||
38 | |||
39 | /* | ||
40 | * Increase size of DMA-consistent memory region | ||
41 | */ | ||
42 | #define CONSISTENT_DMA_SIZE (14<<20) | ||
43 | |||
44 | #endif /* __ASM_ARCH_MEMORY_H */ | ||
diff --git a/arch/arm/mach-davinci/include/mach/mmc.h b/arch/arm/mach-davinci/include/mach/mmc.h new file mode 100644 index 00000000000..d4f1e967506 --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/mmc.h | |||
@@ -0,0 +1,36 @@ | |||
1 | /* | ||
2 | * Board-specific MMC configuration | ||
3 | */ | ||
4 | |||
5 | #ifndef _DAVINCI_MMC_H | ||
6 | #define _DAVINCI_MMC_H | ||
7 | |||
8 | #include <linux/types.h> | ||
9 | #include <linux/mmc/host.h> | ||
10 | |||
11 | struct davinci_mmc_config { | ||
12 | /* get_cd()/get_wp() may sleep */ | ||
13 | int (*get_cd)(int module); | ||
14 | int (*get_ro)(int module); | ||
15 | /* wires == 0 is equivalent to wires == 4 (4-bit parallel) */ | ||
16 | u8 wires; | ||
17 | |||
18 | u32 max_freq; | ||
19 | |||
20 | /* any additional host capabilities: OR'd in to mmc->f_caps */ | ||
21 | u32 caps; | ||
22 | |||
23 | /* Version of the MMC/SD controller */ | ||
24 | u8 version; | ||
25 | |||
26 | /* Number of sg segments */ | ||
27 | u8 nr_sg; | ||
28 | }; | ||
29 | void davinci_setup_mmc(int module, struct davinci_mmc_config *config); | ||
30 | |||
31 | enum { | ||
32 | MMC_CTLR_VERSION_1 = 0, /* DM644x and DM355 */ | ||
33 | MMC_CTLR_VERSION_2, /* DA830 */ | ||
34 | }; | ||
35 | |||
36 | #endif | ||
diff --git a/arch/arm/mach-davinci/include/mach/nand.h b/arch/arm/mach-davinci/include/mach/nand.h new file mode 100644 index 00000000000..025151049f0 --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/nand.h | |||
@@ -0,0 +1,88 @@ | |||
1 | /* | ||
2 | * mach-davinci/nand.h | ||
3 | * | ||
4 | * Copyright © 2006 Texas Instruments. | ||
5 | * | ||
6 | * Ported to 2.6.23 Copyright © 2008 by | ||
7 | * Sander Huijsen <Shuijsen@optelecom-nkf.com> | ||
8 | * Troy Kisky <troy.kisky@boundarydevices.com> | ||
9 | * Dirk Behme <Dirk.Behme@gmail.com> | ||
10 | * | ||
11 | * -------------------------------------------------------------------------- | ||
12 | * | ||
13 | * This program is free software; you can redistribute it and/or modify | ||
14 | * it under the terms of the GNU General Public License as published by | ||
15 | * the Free Software Foundation; either version 2 of the License, or | ||
16 | * (at your option) any later version. | ||
17 | * | ||
18 | * This program is distributed in the hope that it will be useful, | ||
19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
21 | * GNU General Public License for more details. | ||
22 | * | ||
23 | * You should have received a copy of the GNU General Public License | ||
24 | * along with this program; if not, write to the Free Software | ||
25 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | ||
26 | */ | ||
27 | |||
28 | #ifndef __ARCH_ARM_DAVINCI_NAND_H | ||
29 | #define __ARCH_ARM_DAVINCI_NAND_H | ||
30 | |||
31 | #include <linux/mtd/nand.h> | ||
32 | |||
33 | #define NANDFCR_OFFSET 0x60 | ||
34 | #define NANDFSR_OFFSET 0x64 | ||
35 | #define NANDF1ECC_OFFSET 0x70 | ||
36 | |||
37 | /* 4-bit ECC syndrome registers */ | ||
38 | #define NAND_4BIT_ECC_LOAD_OFFSET 0xbc | ||
39 | #define NAND_4BIT_ECC1_OFFSET 0xc0 | ||
40 | #define NAND_4BIT_ECC2_OFFSET 0xc4 | ||
41 | #define NAND_4BIT_ECC3_OFFSET 0xc8 | ||
42 | #define NAND_4BIT_ECC4_OFFSET 0xcc | ||
43 | #define NAND_ERR_ADD1_OFFSET 0xd0 | ||
44 | #define NAND_ERR_ADD2_OFFSET 0xd4 | ||
45 | #define NAND_ERR_ERRVAL1_OFFSET 0xd8 | ||
46 | #define NAND_ERR_ERRVAL2_OFFSET 0xdc | ||
47 | |||
48 | /* NOTE: boards don't need to use these address bits | ||
49 | * for ALE/CLE unless they support booting from NAND. | ||
50 | * They're used unless platform data overrides them. | ||
51 | */ | ||
52 | #define MASK_ALE 0x08 | ||
53 | #define MASK_CLE 0x10 | ||
54 | |||
55 | struct davinci_nand_pdata { /* platform_data */ | ||
56 | uint32_t mask_ale; | ||
57 | uint32_t mask_cle; | ||
58 | |||
59 | /* for packages using two chipselects */ | ||
60 | uint32_t mask_chipsel; | ||
61 | |||
62 | /* board's default static partition info */ | ||
63 | struct mtd_partition *parts; | ||
64 | unsigned nr_parts; | ||
65 | |||
66 | /* none == NAND_ECC_NONE (strongly *not* advised!!) | ||
67 | * soft == NAND_ECC_SOFT | ||
68 | * else == NAND_ECC_HW, according to ecc_bits | ||
69 | * | ||
70 | * All DaVinci-family chips support 1-bit hardware ECC. | ||
71 | * Newer ones also support 4-bit ECC, but are awkward | ||
72 | * using it with large page chips. | ||
73 | */ | ||
74 | nand_ecc_modes_t ecc_mode; | ||
75 | u8 ecc_bits; | ||
76 | |||
77 | /* e.g. NAND_BUSWIDTH_16 or NAND_USE_FLASH_BBT */ | ||
78 | unsigned options; | ||
79 | |||
80 | /* Main and mirror bbt descriptor overrides */ | ||
81 | struct nand_bbt_descr *bbt_td; | ||
82 | struct nand_bbt_descr *bbt_md; | ||
83 | |||
84 | /* Access timings */ | ||
85 | struct davinci_aemif_timing *timing; | ||
86 | }; | ||
87 | |||
88 | #endif /* __ARCH_ARM_DAVINCI_NAND_H */ | ||
diff --git a/arch/arm/mach-davinci/include/mach/spi.h b/arch/arm/mach-davinci/include/mach/spi.h new file mode 100644 index 00000000000..7af305b3786 --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/spi.h | |||
@@ -0,0 +1,89 @@ | |||
1 | /* | ||
2 | * Copyright 2009 Texas Instruments. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify | ||
5 | * it under the terms of the GNU General Public License as published by | ||
6 | * the Free Software Foundation; either version 2 of the License, or | ||
7 | * (at your option) any later version. | ||
8 | * | ||
9 | * This program is distributed in the hope that it will be useful, | ||
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
12 | * GNU General Public License for more details. | ||
13 | * | ||
14 | * You should have received a copy of the GNU General Public License | ||
15 | * along with this program; if not, write to the Free Software | ||
16 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | ||
17 | */ | ||
18 | |||
19 | #ifndef __ARCH_ARM_DAVINCI_SPI_H | ||
20 | #define __ARCH_ARM_DAVINCI_SPI_H | ||
21 | |||
22 | #include <mach/edma.h> | ||
23 | |||
24 | #define SPI_INTERN_CS 0xFF | ||
25 | |||
26 | enum { | ||
27 | SPI_VERSION_1, /* For DM355/DM365/DM6467 */ | ||
28 | SPI_VERSION_2, /* For DA8xx */ | ||
29 | }; | ||
30 | |||
31 | /** | ||
32 | * davinci_spi_platform_data - Platform data for SPI master device on DaVinci | ||
33 | * | ||
34 | * @version: version of the SPI IP. Different DaVinci devices have slightly | ||
35 | * varying versions of the same IP. | ||
36 | * @num_chipselect: number of chipselects supported by this SPI master | ||
37 | * @intr_line: interrupt line used to connect the SPI IP to the ARM interrupt | ||
38 | * controller withn the SoC. Possible values are 0 and 1. | ||
39 | * @chip_sel: list of GPIOs which can act as chip-selects for the SPI. | ||
40 | * SPI_INTERN_CS denotes internal SPI chip-select. Not necessary | ||
41 | * to populate if all chip-selects are internal. | ||
42 | * @cshold_bug: set this to true if the SPI controller on your chip requires | ||
43 | * a write to CSHOLD bit in between transfers (like in DM355). | ||
44 | * @dma_event_q: DMA event queue to use if SPI_IO_TYPE_DMA is used for any | ||
45 | * device on the bus. | ||
46 | */ | ||
47 | struct davinci_spi_platform_data { | ||
48 | u8 version; | ||
49 | u8 num_chipselect; | ||
50 | u8 intr_line; | ||
51 | u8 *chip_sel; | ||
52 | bool cshold_bug; | ||
53 | enum dma_event_q dma_event_q; | ||
54 | }; | ||
55 | |||
56 | /** | ||
57 | * davinci_spi_config - Per-chip-select configuration for SPI slave devices | ||
58 | * | ||
59 | * @wdelay: amount of delay between transmissions. Measured in number of | ||
60 | * SPI module clocks. | ||
61 | * @odd_parity: polarity of parity flag at the end of transmit data stream. | ||
62 | * 0 - odd parity, 1 - even parity. | ||
63 | * @parity_enable: enable transmission of parity at end of each transmit | ||
64 | * data stream. | ||
65 | * @io_type: type of IO transfer. Choose between polled, interrupt and DMA. | ||
66 | * @timer_disable: disable chip-select timers (setup and hold) | ||
67 | * @c2tdelay: chip-select setup time. Measured in number of SPI module clocks. | ||
68 | * @t2cdelay: chip-select hold time. Measured in number of SPI module clocks. | ||
69 | * @t2edelay: transmit data finished to SPI ENAn pin inactive time. Measured | ||
70 | * in number of SPI clocks. | ||
71 | * @c2edelay: chip-select active to SPI ENAn signal active time. Measured in | ||
72 | * number of SPI clocks. | ||
73 | */ | ||
74 | struct davinci_spi_config { | ||
75 | u8 wdelay; | ||
76 | u8 odd_parity; | ||
77 | u8 parity_enable; | ||
78 | #define SPI_IO_TYPE_INTR 0 | ||
79 | #define SPI_IO_TYPE_POLL 1 | ||
80 | #define SPI_IO_TYPE_DMA 2 | ||
81 | u8 io_type; | ||
82 | u8 timer_disable; | ||
83 | u8 c2tdelay; | ||
84 | u8 t2cdelay; | ||
85 | u8 t2edelay; | ||
86 | u8 c2edelay; | ||
87 | }; | ||
88 | |||
89 | #endif /* __ARCH_ARM_DAVINCI_SPI_H */ | ||
diff --git a/arch/arm/mach-davinci/include/mach/system.h b/arch/arm/mach-davinci/include/mach/system.h new file mode 100644 index 00000000000..e65629c2076 --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/system.h | |||
@@ -0,0 +1,27 @@ | |||
1 | /* | ||
2 | * DaVinci system defines | ||
3 | * | ||
4 | * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> | ||
5 | * | ||
6 | * 2007 (c) MontaVista Software, Inc. This file is licensed under | ||
7 | * the terms of the GNU General Public License version 2. This program | ||
8 | * is licensed "as is" without any warranty of any kind, whether express | ||
9 | * or implied. | ||
10 | */ | ||
11 | #ifndef __ASM_ARCH_SYSTEM_H | ||
12 | #define __ASM_ARCH_SYSTEM_H | ||
13 | |||
14 | #include <mach/common.h> | ||
15 | |||
16 | static inline void arch_idle(void) | ||
17 | { | ||
18 | cpu_do_idle(); | ||
19 | } | ||
20 | |||
21 | static inline void arch_reset(char mode, const char *cmd) | ||
22 | { | ||
23 | if (davinci_soc_info.reset) | ||
24 | davinci_soc_info.reset(davinci_soc_info.reset_device); | ||
25 | } | ||
26 | |||
27 | #endif /* __ASM_ARCH_SYSTEM_H */ | ||
diff --git a/arch/arm/mach-davinci/include/mach/usb.h b/arch/arm/mach-davinci/include/mach/usb.h new file mode 100644 index 00000000000..e0bc4abe69c --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/usb.h | |||
@@ -0,0 +1,59 @@ | |||
1 | /* | ||
2 | * USB related definitions | ||
3 | * | ||
4 | * Copyright (C) 2009 MontaVista Software, Inc. <source@mvista.com> | ||
5 | * | ||
6 | * This file is licensed under the terms of the GNU General Public License | ||
7 | * version 2. This program is licensed "as is" without any warranty of any | ||
8 | * kind, whether express or implied. | ||
9 | */ | ||
10 | |||
11 | #ifndef __ASM_ARCH_USB_H | ||
12 | #define __ASM_ARCH_USB_H | ||
13 | |||
14 | /* DA8xx CFGCHIP2 (USB 2.0 PHY Control) register bits */ | ||
15 | #define CFGCHIP2_PHYCLKGD (1 << 17) | ||
16 | #define CFGCHIP2_VBUSSENSE (1 << 16) | ||
17 | #define CFGCHIP2_RESET (1 << 15) | ||
18 | #define CFGCHIP2_OTGMODE (3 << 13) | ||
19 | #define CFGCHIP2_NO_OVERRIDE (0 << 13) | ||
20 | #define CFGCHIP2_FORCE_HOST (1 << 13) | ||
21 | #define CFGCHIP2_FORCE_DEVICE (2 << 13) | ||
22 | #define CFGCHIP2_FORCE_HOST_VBUS_LOW (3 << 13) | ||
23 | #define CFGCHIP2_USB1PHYCLKMUX (1 << 12) | ||
24 | #define CFGCHIP2_USB2PHYCLKMUX (1 << 11) | ||
25 | #define CFGCHIP2_PHYPWRDN (1 << 10) | ||
26 | #define CFGCHIP2_OTGPWRDN (1 << 9) | ||
27 | #define CFGCHIP2_DATPOL (1 << 8) | ||
28 | #define CFGCHIP2_USB1SUSPENDM (1 << 7) | ||
29 | #define CFGCHIP2_PHY_PLLON (1 << 6) /* override PLL suspend */ | ||
30 | #define CFGCHIP2_SESENDEN (1 << 5) /* Vsess_end comparator */ | ||
31 | #define CFGCHIP2_VBDTCTEN (1 << 4) /* Vbus comparator */ | ||
32 | #define CFGCHIP2_REFFREQ (0xf << 0) | ||
33 | #define CFGCHIP2_REFFREQ_12MHZ (1 << 0) | ||
34 | #define CFGCHIP2_REFFREQ_24MHZ (2 << 0) | ||
35 | #define CFGCHIP2_REFFREQ_48MHZ (3 << 0) | ||
36 | |||
37 | struct da8xx_ohci_root_hub; | ||
38 | |||
39 | typedef void (*da8xx_ocic_handler_t)(struct da8xx_ohci_root_hub *hub, | ||
40 | unsigned port); | ||
41 | |||
42 | /* Passed as the platform data to the OHCI driver */ | ||
43 | struct da8xx_ohci_root_hub { | ||
44 | /* Switch the port power on/off */ | ||
45 | int (*set_power)(unsigned port, int on); | ||
46 | /* Read the port power status */ | ||
47 | int (*get_power)(unsigned port); | ||
48 | /* Read the port over-current indicator */ | ||
49 | int (*get_oci)(unsigned port); | ||
50 | /* Over-current indicator change notification (pass NULL to disable) */ | ||
51 | int (*ocic_notify)(da8xx_ocic_handler_t handler); | ||
52 | |||
53 | /* Time from power on to power good (in 2 ms units) */ | ||
54 | u8 potpgt; | ||
55 | }; | ||
56 | |||
57 | void davinci_setup_usb(unsigned mA, unsigned potpgt_ms); | ||
58 | |||
59 | #endif /* ifndef __ASM_ARCH_USB_H */ | ||
diff --git a/arch/arm/mach-davinci/include/mach/vmalloc.h b/arch/arm/mach-davinci/include/mach/vmalloc.h new file mode 100644 index 00000000000..d49646a8e20 --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/vmalloc.h | |||
@@ -0,0 +1,14 @@ | |||
1 | /* | ||
2 | * DaVinci vmalloc definitions | ||
3 | * | ||
4 | * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> | ||
5 | * | ||
6 | * 2007 (c) MontaVista Software, Inc. This file is licensed under | ||
7 | * the terms of the GNU General Public License version 2. This program | ||
8 | * is licensed "as is" without any warranty of any kind, whether express | ||
9 | * or implied. | ||
10 | */ | ||
11 | #include <mach/hardware.h> | ||
12 | |||
13 | /* Allow vmalloc range until the IO virtual range minus a 2M "hole" */ | ||
14 | #define VMALLOC_END (IO_VIRT - (2<<20)) | ||
diff --git a/arch/arm/mach-davinci/io.c b/arch/arm/mach-davinci/io.c new file mode 100644 index 00000000000..8ea60a8b249 --- /dev/null +++ b/arch/arm/mach-davinci/io.c | |||
@@ -0,0 +1,48 @@ | |||
1 | /* | ||
2 | * DaVinci I/O mapping code | ||
3 | * | ||
4 | * Copyright (C) 2005-2006 Texas Instruments | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | |||
11 | #include <linux/module.h> | ||
12 | #include <linux/io.h> | ||
13 | |||
14 | #include <asm/tlb.h> | ||
15 | #include <asm/mach/map.h> | ||
16 | |||
17 | #include <mach/common.h> | ||
18 | |||
19 | /* | ||
20 | * Intercept ioremap() requests for addresses in our fixed mapping regions. | ||
21 | */ | ||
22 | void __iomem *davinci_ioremap(unsigned long p, size_t size, unsigned int type) | ||
23 | { | ||
24 | struct map_desc *desc = davinci_soc_info.io_desc; | ||
25 | int desc_num = davinci_soc_info.io_desc_num; | ||
26 | int i; | ||
27 | |||
28 | for (i = 0; i < desc_num; i++, desc++) { | ||
29 | unsigned long iophys = __pfn_to_phys(desc->pfn); | ||
30 | unsigned long iosize = desc->length; | ||
31 | |||
32 | if (p >= iophys && (p + size) <= (iophys + iosize)) | ||
33 | return __io(desc->virtual + p - iophys); | ||
34 | } | ||
35 | |||
36 | return __arm_ioremap_caller(p, size, type, | ||
37 | __builtin_return_address(0)); | ||
38 | } | ||
39 | EXPORT_SYMBOL(davinci_ioremap); | ||
40 | |||
41 | void davinci_iounmap(volatile void __iomem *addr) | ||
42 | { | ||
43 | unsigned long virt = (unsigned long)addr; | ||
44 | |||
45 | if (virt >= VMALLOC_START && virt < VMALLOC_END) | ||
46 | __iounmap(addr); | ||
47 | } | ||
48 | EXPORT_SYMBOL(davinci_iounmap); | ||