diff options
Diffstat (limited to 'arch/arm/mach-cns3xxx/include/mach/entry-macro.S')
| -rw-r--r-- | arch/arm/mach-cns3xxx/include/mach/entry-macro.S | 66 |
1 files changed, 1 insertions, 65 deletions
diff --git a/arch/arm/mach-cns3xxx/include/mach/entry-macro.S b/arch/arm/mach-cns3xxx/include/mach/entry-macro.S index 5e1c5545680..6bd83ed90af 100644 --- a/arch/arm/mach-cns3xxx/include/mach/entry-macro.S +++ b/arch/arm/mach-cns3xxx/include/mach/entry-macro.S | |||
| @@ -9,74 +9,10 @@ | |||
| 9 | */ | 9 | */ |
| 10 | 10 | ||
| 11 | #include <mach/hardware.h> | 11 | #include <mach/hardware.h> |
| 12 | #include <asm/hardware/gic.h> | 12 | #include <asm/hardware/entry-macro-gic.S> |
| 13 | 13 | ||
| 14 | .macro disable_fiq | 14 | .macro disable_fiq |
| 15 | .endm | 15 | .endm |
| 16 | 16 | ||
| 17 | .macro get_irqnr_preamble, base, tmp | ||
| 18 | ldr \base, =gic_cpu_base_addr | ||
| 19 | ldr \base, [\base] | ||
| 20 | .endm | ||
| 21 | |||
| 22 | .macro arch_ret_to_user, tmp1, tmp2 | 17 | .macro arch_ret_to_user, tmp1, tmp2 |
| 23 | .endm | 18 | .endm |
| 24 | |||
| 25 | /* | ||
| 26 | * The interrupt numbering scheme is defined in the | ||
| 27 | * interrupt controller spec. To wit: | ||
| 28 | * | ||
| 29 | * Interrupts 0-15 are IPI | ||
| 30 | * 16-28 are reserved | ||
| 31 | * 29-31 are local. We allow 30 to be used for the watchdog. | ||
| 32 | * 32-1020 are global | ||
| 33 | * 1021-1022 are reserved | ||
| 34 | * 1023 is "spurious" (no interrupt) | ||
| 35 | * | ||
| 36 | * For now, we ignore all local interrupts so only return an interrupt if it's | ||
| 37 | * between 30 and 1020. The test_for_ipi routine below will pick up on IPIs. | ||
| 38 | * | ||
| 39 | * A simple read from the controller will tell us the number of the highest | ||
| 40 | * priority enabled interrupt. We then just need to check whether it is in the | ||
| 41 | * valid range for an IRQ (30-1020 inclusive). | ||
| 42 | */ | ||
| 43 | |||
| 44 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
| 45 | |||
| 46 | ldr \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */ | ||
| 47 | |||
| 48 | ldr \tmp, =1021 | ||
| 49 | |||
| 50 | bic \irqnr, \irqstat, #0x1c00 | ||
| 51 | |||
| 52 | cmp \irqnr, #29 | ||
| 53 | cmpcc \irqnr, \irqnr | ||
| 54 | cmpne \irqnr, \tmp | ||
| 55 | cmpcs \irqnr, \irqnr | ||
| 56 | |||
| 57 | .endm | ||
| 58 | |||
| 59 | /* We assume that irqstat (the raw value of the IRQ acknowledge | ||
| 60 | * register) is preserved from the macro above. | ||
| 61 | * If there is an IPI, we immediately signal end of interrupt on the | ||
| 62 | * controller, since this requires the original irqstat value which | ||
| 63 | * we won't easily be able to recreate later. | ||
| 64 | */ | ||
| 65 | |||
| 66 | .macro test_for_ipi, irqnr, irqstat, base, tmp | ||
| 67 | bic \irqnr, \irqstat, #0x1c00 | ||
| 68 | cmp \irqnr, #16 | ||
| 69 | strcc \irqstat, [\base, #GIC_CPU_EOI] | ||
| 70 | cmpcs \irqnr, \irqnr | ||
| 71 | .endm | ||
| 72 | |||
| 73 | /* As above, this assumes that irqstat and base are preserved.. */ | ||
| 74 | |||
| 75 | .macro test_for_ltirq, irqnr, irqstat, base, tmp | ||
| 76 | bic \irqnr, \irqstat, #0x1c00 | ||
| 77 | mov \tmp, #0 | ||
| 78 | cmp \irqnr, #29 | ||
| 79 | moveq \tmp, #1 | ||
| 80 | streq \irqstat, [\base, #GIC_CPU_EOI] | ||
| 81 | cmp \tmp, #0 | ||
| 82 | .endm | ||