diff options
Diffstat (limited to 'arch/arm/mach-clps711x/Kconfig')
-rw-r--r-- | arch/arm/mach-clps711x/Kconfig | 21 |
1 files changed, 4 insertions, 17 deletions
diff --git a/arch/arm/mach-clps711x/Kconfig b/arch/arm/mach-clps711x/Kconfig index eb34bd1251d..ea036d62158 100644 --- a/arch/arm/mach-clps711x/Kconfig +++ b/arch/arm/mach-clps711x/Kconfig | |||
@@ -1,6 +1,6 @@ | |||
1 | if ARCH_CLPS711X | 1 | if ARCH_CLPS711X |
2 | 2 | ||
3 | menu "CLPS711X/EP721X Implementations" | 3 | menu "CLPS711X/EP721X/EP731X Implementations" |
4 | 4 | ||
5 | config ARCH_AUTCPU12 | 5 | config ARCH_AUTCPU12 |
6 | bool "AUTCPU12" | 6 | bool "AUTCPU12" |
@@ -45,26 +45,13 @@ config ARCH_P720T | |||
45 | config ARCH_FORTUNET | 45 | config ARCH_FORTUNET |
46 | bool "FORTUNET" | 46 | bool "FORTUNET" |
47 | 47 | ||
48 | # XXX Maybe these should indicate register compatibility | ||
49 | # instead of being mutually exclusive. | ||
50 | config ARCH_EP7211 | ||
51 | bool | ||
52 | depends on ARCH_EDB7211 | ||
53 | default y | ||
54 | |||
55 | config ARCH_EP7212 | ||
56 | bool | ||
57 | depends on ARCH_P720T || ARCH_CEIVA | ||
58 | default y | ||
59 | |||
60 | config EP72XX_ROM_BOOT | 48 | config EP72XX_ROM_BOOT |
61 | bool "EP72xx ROM boot" | 49 | bool "EP721x/EP731x ROM boot" |
62 | depends on ARCH_EP7211 || ARCH_EP7212 | 50 | help |
63 | ---help--- | ||
64 | If you say Y here, your CLPS711x-based kernel will use the bootstrap | 51 | If you say Y here, your CLPS711x-based kernel will use the bootstrap |
65 | mode memory map instead of the normal memory map. | 52 | mode memory map instead of the normal memory map. |
66 | 53 | ||
67 | Processors derived from the Cirrus CLPS-711X core support two boot | 54 | Processors derived from the Cirrus CLPS711X core support two boot |
68 | modes. Normal mode boots from the external memory device at CS0. | 55 | modes. Normal mode boots from the external memory device at CS0. |
69 | Bootstrap mode rearranges parts of the memory map, placing an | 56 | Bootstrap mode rearranges parts of the memory map, placing an |
70 | internal 128 byte bootstrap ROM at CS0. This option performs the | 57 | internal 128 byte bootstrap ROM at CS0. This option performs the |