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-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/mm_addr.h101
-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/mm_io.h147
-rw-r--r--arch/arm/mach-bcmring/include/mach/memory.h33
-rw-r--r--arch/arm/mach-bcmring/include/mach/memory_settings.h67
-rw-r--r--arch/arm/mach-bcmring/include/mach/vmalloc.h25
-rw-r--r--arch/arm/mach-bcmring/mm.c56
6 files changed, 429 insertions, 0 deletions
diff --git a/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h b/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h
new file mode 100644
index 00000000000..86bb58d4f58
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h
@@ -0,0 +1,101 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/****************************************************************************/
16/**
17* @file mm_addr.h
18*
19* @brief Memory Map address defintions
20*
21* @note
22* None
23*/
24/****************************************************************************/
25
26#ifndef _MM_ADDR_H
27#define _MM_ADDR_H
28
29/* ---- Include Files ---------------------------------------------------- */
30
31#if !defined(CSP_SIMULATION)
32#include <cfg_global.h>
33#endif
34
35/* ---- Public Constants and Types --------------------------------------- */
36
37/* Memory Map address definitions */
38
39#define MM_ADDR_DDR 0x00000000
40
41#define MM_ADDR_IO_VPM_EXTMEM_RSVD 0x0F000000 /* 16 MB - Reserved external memory for VPM use */
42
43#define MM_ADDR_IO_FLASHC 0x20000000
44#define MM_ADDR_IO_BROM 0x30000000
45#define MM_ADDR_IO_ARAM 0x30100000 /* 64 KB - extra cycle latency - WS switch */
46#define MM_ADDR_IO_DMA0 0x30200000
47#define MM_ADDR_IO_DMA1 0x30300000
48#define MM_ADDR_IO_ESW 0x30400000
49#define MM_ADDR_IO_CLCD 0x30500000
50#define MM_ADDR_IO_PIF 0x30580000
51#define MM_ADDR_IO_APM 0x30600000
52#define MM_ADDR_IO_SPUM 0x30700000
53#define MM_ADDR_IO_VPM_PROG 0x30800000
54#define MM_ADDR_IO_VPM_DATA 0x30A00000
55#define MM_ADDR_IO_VRAM 0x40000000 /* 64 KB - security block in front of it */
56#define MM_ADDR_IO_CHIPC 0x80000000
57#define MM_ADDR_IO_UMI 0x80001000
58#define MM_ADDR_IO_NAND 0x80001800
59#define MM_ADDR_IO_LEDM 0x80002000
60#define MM_ADDR_IO_PWM 0x80002040
61#define MM_ADDR_IO_VINTC 0x80003000
62#define MM_ADDR_IO_GPIO0 0x80004000
63#define MM_ADDR_IO_GPIO1 0x80004800
64#define MM_ADDR_IO_I2CS 0x80005000
65#define MM_ADDR_IO_SPIS 0x80006000
66#define MM_ADDR_IO_HPM 0x80007400
67#define MM_ADDR_IO_HPM_REMAP 0x80007800
68#define MM_ADDR_IO_TZPC 0x80008000
69#define MM_ADDR_IO_MPU 0x80009000
70#define MM_ADDR_IO_SPUMP 0x8000a000
71#define MM_ADDR_IO_PKA 0x8000b000
72#define MM_ADDR_IO_RNG 0x8000c000
73#define MM_ADDR_IO_KEYC 0x8000d000
74#define MM_ADDR_IO_BBL 0x8000e000
75#define MM_ADDR_IO_OTP 0x8000f000
76#define MM_ADDR_IO_I2S0 0x80010000
77#define MM_ADDR_IO_I2S1 0x80011000
78#define MM_ADDR_IO_UARTA 0x80012000
79#define MM_ADDR_IO_UARTB 0x80013000
80#define MM_ADDR_IO_I2CH 0x80014020
81#define MM_ADDR_IO_SPIH 0x80015000
82#define MM_ADDR_IO_TSC 0x80016000
83#define MM_ADDR_IO_TMR 0x80017000
84#define MM_ADDR_IO_WATCHDOG 0x80017800
85#define MM_ADDR_IO_ETM 0x80018000
86#define MM_ADDR_IO_DDRC 0x80019000
87#define MM_ADDR_IO_SINTC 0x80100000
88#define MM_ADDR_IO_INTC0 0x80200000
89#define MM_ADDR_IO_INTC1 0x80201000
90#define MM_ADDR_IO_GE 0x80300000
91#define MM_ADDR_IO_USB_CTLR0 0x80400000
92#define MM_ADDR_IO_USB_CTLR1 0x80410000
93#define MM_ADDR_IO_USB_PHY 0x80420000
94#define MM_ADDR_IO_SDIOH0 0x80500000
95#define MM_ADDR_IO_SDIOH1 0x80600000
96#define MM_ADDR_IO_VDEC 0x80700000
97
98/* ---- Public Variable Externs ------------------------------------------ */
99/* ---- Public Function Prototypes --------------------------------------- */
100
101#endif /* _MM_ADDR_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/mm_io.h b/arch/arm/mach-bcmring/include/mach/csp/mm_io.h
new file mode 100644
index 00000000000..de92ec6a01a
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/mm_io.h
@@ -0,0 +1,147 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/****************************************************************************/
16/**
17* @file mm_io.h
18*
19* @brief Memory Map I/O definitions
20*
21* @note
22* None
23*/
24/****************************************************************************/
25
26#ifndef _MM_IO_H
27#define _MM_IO_H
28
29/* ---- Include Files ---------------------------------------------------- */
30#include <mach/csp/mm_addr.h>
31
32#if !defined(CSP_SIMULATION)
33#include <cfg_global.h>
34#endif
35
36/* ---- Public Constants and Types --------------------------------------- */
37
38#if defined(CONFIG_MMU)
39
40/* This macro is referenced in <mach/io.h>
41 * Phys to Virtual 0xNyxxxxxx => 0xFNxxxxxx
42 * This macro is referenced in <asm/arch/io.h>
43 *
44 * Assume VPM address is the last x MB of memory. For VPM, map to
45 * 0xf0000000 and up.
46 */
47
48#ifndef MM_IO_PHYS_TO_VIRT
49#ifdef __ASSEMBLY__
50#define MM_IO_PHYS_TO_VIRT(phys) (0xF0000000 | (((phys) >> 4) & 0x0F000000) | ((phys) & 0xFFFFFF))
51#else
52#define MM_IO_PHYS_TO_VIRT(phys) (((phys) == MM_ADDR_IO_VPM_EXTMEM_RSVD) ? 0xF0000000 : \
53 (0xF0000000 | (((phys) >> 4) & 0x0F000000) | ((phys) & 0xFFFFFF)))
54#endif
55#endif
56
57/* Virtual to Physical 0xFNxxxxxx => 0xN0xxxxxx */
58
59#ifndef MM_IO_VIRT_TO_PHYS
60#ifdef __ASSEMBLY__
61#define MM_IO_VIRT_TO_PHYS(virt) ((((virt) & 0x0F000000) << 4) | ((virt) & 0xFFFFFF))
62#else
63#define MM_IO_VIRT_TO_PHYS(virt) (((virt) == 0xF0000000) ? MM_ADDR_IO_VPM_EXTMEM_RSVD : \
64 ((((virt) & 0x0F000000) << 4) | ((virt) & 0xFFFFFF)))
65#endif
66#endif
67
68#else
69
70#ifndef MM_IO_PHYS_TO_VIRT
71#define MM_IO_PHYS_TO_VIRT(phys) (phys)
72#endif
73
74#ifndef MM_IO_VIRT_TO_PHYS
75#define MM_IO_VIRT_TO_PHYS(virt) (virt)
76#endif
77
78#endif
79
80/* Registers in 0xExxxxxxx that should be moved to 0xFxxxxxxx */
81#define MM_IO_BASE_FLASHC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_FLASHC)
82#define MM_IO_BASE_NAND MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_NAND)
83#define MM_IO_BASE_UMI MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_UMI)
84
85#define MM_IO_START MM_ADDR_IO_FLASHC /* Physical beginning of IO mapped memory */
86#define MM_IO_BASE MM_IO_BASE_FLASHC /* Virtual beginning of IO mapped memory */
87
88#define MM_IO_BASE_BROM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_BROM)
89#define MM_IO_BASE_ARAM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_ARAM)
90#define MM_IO_BASE_DMA0 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_DMA0)
91#define MM_IO_BASE_DMA1 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_DMA1)
92#define MM_IO_BASE_ESW MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_ESW)
93#define MM_IO_BASE_CLCD MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_CLCD)
94#define MM_IO_BASE_PIF MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_PIF)
95#define MM_IO_BASE_APM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_APM)
96#define MM_IO_BASE_SPUM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SPUM)
97#define MM_IO_BASE_VPM_PROG MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VPM_PROG)
98#define MM_IO_BASE_VPM_DATA MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VPM_DATA)
99
100#define MM_IO_BASE_VRAM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VRAM)
101
102#define MM_IO_BASE_CHIPC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_CHIPC)
103#define MM_IO_BASE_DDRC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_DDRC)
104#define MM_IO_BASE_LEDM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_LEDM)
105#define MM_IO_BASE_PWM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_PWM)
106#define MM_IO_BASE_VINTC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VINTC)
107#define MM_IO_BASE_GPIO0 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_GPIO0)
108#define MM_IO_BASE_GPIO1 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_GPIO1)
109#define MM_IO_BASE_TMR MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_TMR)
110#define MM_IO_BASE_WATCHDOG MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_WATCHDOG)
111#define MM_IO_BASE_ETM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_ETM)
112#define MM_IO_BASE_HPM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_HPM)
113#define MM_IO_BASE_HPM_REMAP MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_HPM_REMAP)
114#define MM_IO_BASE_TZPC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_TZPC)
115#define MM_IO_BASE_MPU MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_MPU)
116#define MM_IO_BASE_SPUMP MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SPUMP)
117#define MM_IO_BASE_PKA MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_PKA)
118#define MM_IO_BASE_RNG MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_RNG)
119#define MM_IO_BASE_KEYC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_KEYC)
120#define MM_IO_BASE_BBL MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_BBL)
121#define MM_IO_BASE_OTP MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_OTP)
122#define MM_IO_BASE_I2S0 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_I2S0)
123#define MM_IO_BASE_I2S1 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_I2S1)
124#define MM_IO_BASE_UARTA MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_UARTA)
125#define MM_IO_BASE_UARTB MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_UARTB)
126#define MM_IO_BASE_I2CH MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_I2CH)
127#define MM_IO_BASE_SPIH MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SPIH)
128#define MM_IO_BASE_TSC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_TSC)
129#define MM_IO_BASE_I2CS MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_I2CS)
130#define MM_IO_BASE_SPIS MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SPIS)
131#define MM_IO_BASE_SINTC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SINTC)
132#define MM_IO_BASE_INTC0 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_INTC0)
133#define MM_IO_BASE_INTC1 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_INTC1)
134#define MM_IO_BASE_GE MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_GE)
135#define MM_IO_BASE_USB_CTLR0 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_USB_CTLR0)
136#define MM_IO_BASE_USB_CTLR1 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_USB_CTLR1)
137#define MM_IO_BASE_USB_PHY MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_USB_PHY)
138#define MM_IO_BASE_SDIOH0 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SDIOH0)
139#define MM_IO_BASE_SDIOH1 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SDIOH1)
140#define MM_IO_BASE_VDEC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VDEC)
141
142#define MM_IO_BASE_VPM_EXTMEM_RSVD MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VPM_EXTMEM_RSVD)
143
144/* ---- Public Variable Externs ------------------------------------------ */
145/* ---- Public Function Prototypes --------------------------------------- */
146
147#endif /* _MM_IO_H */
diff --git a/arch/arm/mach-bcmring/include/mach/memory.h b/arch/arm/mach-bcmring/include/mach/memory.h
new file mode 100644
index 00000000000..114f942bb4f
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/memory.h
@@ -0,0 +1,33 @@
1/*****************************************************************************
2* Copyright 2005 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15#ifndef __ASM_ARCH_MEMORY_H
16#define __ASM_ARCH_MEMORY_H
17
18#include <cfg_global.h>
19
20/*
21 * Physical vs virtual RAM address space conversion. These are
22 * private definitions which should NOT be used outside memory.h
23 * files. Use virt_to_phys/phys_to_virt/__pa/__va instead.
24 */
25
26#define PHYS_OFFSET CFG_GLOBAL_RAM_BASE
27
28/*
29 * Maximum DMA memory allowed is 14M
30 */
31#define CONSISTENT_DMA_SIZE (SZ_16M - SZ_2M)
32
33#endif
diff --git a/arch/arm/mach-bcmring/include/mach/memory_settings.h b/arch/arm/mach-bcmring/include/mach/memory_settings.h
new file mode 100644
index 00000000000..ce5cd16f2ac
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/memory_settings.h
@@ -0,0 +1,67 @@
1/*****************************************************************************
2* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15#ifndef MEMORY_SETTINGS_H
16#define MEMORY_SETTINGS_H
17
18/* ---- Include Files ---------------------------------------- */
19/* ---- Constants and Types ---------------------------------- */
20
21/* Memory devices */
22/* NAND Flash timing for 166 MHz setting */
23#define HW_CFG_NAND_tBTA (5 << 16) /* Bus turnaround cycle (n) 0-7 (30 ns) */
24#define HW_CFG_NAND_tWP (4 << 11) /* Write pulse width cycle (n+1) 0-31 (25 ns) */
25#define HW_CFG_NAND_tWR (1 << 9) /* Write recovery cycle (n+1) 0-3 (10 ns) */
26#define HW_CFG_NAND_tAS (0 << 7) /* Write address setup cycle (n+1) 0-3 ( 0 ns) */
27#define HW_CFG_NAND_tOE (3 << 5) /* Output enable delay cycle (n) 0-3 (15 ns) */
28#define HW_CFG_NAND_tRC (7 << 0) /* Read access cycle (n+2) 0-31 (50 ns) */
29
30#define HW_CFG_NAND_TCR (HW_CFG_NAND_tBTA \
31 | HW_CFG_NAND_tWP \
32 | HW_CFG_NAND_tWR \
33 | HW_CFG_NAND_tAS \
34 | HW_CFG_NAND_tOE \
35 | HW_CFG_NAND_tRC)
36
37/* NOR Flash timing for 166 MHz setting */
38#define HW_CFG_NOR_TPRC_TWLC (0 << 19) /* Page read access cycle / Burst write latency (n+2 / n+1) (max 25ns) */
39#define HW_CFG_NOR_TBTA (0 << 16) /* Bus turnaround cycle (n) (DNA) */
40#define HW_CFG_NOR_TWP (6 << 11) /* Write pulse width cycle (n+1) (35ns) */
41#define HW_CFG_NOR_TWR (0 << 9) /* Write recovery cycle (n+1) (0ns) */
42#define HW_CFG_NOR_TAS (0 << 7) /* Write address setup cycle (n+1) (0ns) */
43#define HW_CFG_NOR_TOE (0 << 5) /* Output enable delay cycle (n) (max 25ns) */
44#define HW_CFG_NOR_TRC_TLC (0x10 << 0) /* Read access cycle / Burst read latency (n+2 / n+1) (100ns) */
45
46#define HW_CFG_FLASH0_TCR (HW_CFG_NOR_TPRC_TWLC \
47 | HW_CFG_NOR_TBTA \
48 | HW_CFG_NOR_TWP \
49 | HW_CFG_NOR_TWR \
50 | HW_CFG_NOR_TAS \
51 | HW_CFG_NOR_TOE \
52 | HW_CFG_NOR_TRC_TLC)
53
54#define HW_CFG_FLASH1_TCR HW_CFG_FLASH0_TCR
55#define HW_CFG_FLASH2_TCR HW_CFG_FLASH0_TCR
56
57/* SDRAM Settings */
58/* #define HW_CFG_SDRAM_CAS_LATENCY 5 Default 5, Values [3..6] */
59/* #define HW_CFG_SDRAM_CHIP_SELECT_CNT 1 Default 1, Vaules [1..2] */
60/* #define HW_CFG_SDRAM_SPEED_GRADE 667 Default 667, Values [400,533,667,800] */
61/* #define HW_CFG_SDRAM_WIDTH_BITS 16 Default 16, Vaules [8,16] */
62#define HW_CFG_SDRAM_SIZE_BYTES 0x10000000 /* Total memory, not per device size */
63
64/* ---- Variable Externs ------------------------------------- */
65/* ---- Function Prototypes ---------------------------------- */
66
67#endif /* MEMORY_SETTINGS_H */
diff --git a/arch/arm/mach-bcmring/include/mach/vmalloc.h b/arch/arm/mach-bcmring/include/mach/vmalloc.h
new file mode 100644
index 00000000000..35e2ead8395
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/vmalloc.h
@@ -0,0 +1,25 @@
1/*
2 *
3 * Copyright (C) 2000 Russell King.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20/*
21 * Move VMALLOC_END to 0xf0000000 so that the vm space can range from
22 * 0xe0000000 to 0xefffffff. This gives us 256 MB of vm space and handles
23 * larger physical memory designs better.
24 */
25#define VMALLOC_END (PAGE_OFFSET + 0x30000000)
diff --git a/arch/arm/mach-bcmring/mm.c b/arch/arm/mach-bcmring/mm.c
new file mode 100644
index 00000000000..0f1c37e4523
--- /dev/null
+++ b/arch/arm/mach-bcmring/mm.c
@@ -0,0 +1,56 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15#include <linux/platform_device.h>
16#include <asm/mach/map.h>
17
18#include <mach/hardware.h>
19#include <mach/csp/mm_io.h>
20
21#define IO_DESC(va, sz) { .virtual = va, \
22 .pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \
23 .length = sz, \
24 .type = MT_DEVICE }
25
26#define MEM_DESC(va, sz) { .virtual = va, \
27 .pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \
28 .length = sz, \
29 .type = MT_MEMORY }
30
31static struct map_desc bcmring_io_desc[] __initdata = {
32 IO_DESC(MM_IO_BASE_NAND, SZ_64K), /* phys:0x28000000-0x28000FFF virt:0xE8000000-0xE8000FFF size:0x00010000 */
33 IO_DESC(MM_IO_BASE_UMI, SZ_64K), /* phys:0x2C000000-0x2C000FFF virt:0xEC000000-0xEC000FFF size:0x00010000 */
34
35 IO_DESC(MM_IO_BASE_BROM, SZ_64K), /* phys:0x30000000-0x3000FFFF virt:0xF3000000-0xF300FFFF size:0x00010000 */
36 MEM_DESC(MM_IO_BASE_ARAM, SZ_1M), /* phys:0x31000000-0x31FFFFFF virt:0xF3100000-0xF31FFFFF size:0x01000000 */
37 IO_DESC(MM_IO_BASE_DMA0, SZ_1M), /* phys:0x32000000-0x32FFFFFF virt:0xF3200000-0xF32FFFFF size:0x01000000 */
38 IO_DESC(MM_IO_BASE_DMA1, SZ_1M), /* phys:0x33000000-0x33FFFFFF virt:0xF3300000-0xF33FFFFF size:0x01000000 */
39 IO_DESC(MM_IO_BASE_ESW, SZ_1M), /* phys:0x34000000-0x34FFFFFF virt:0xF3400000-0xF34FFFFF size:0x01000000 */
40 IO_DESC(MM_IO_BASE_CLCD, SZ_1M), /* phys:0x35000000-0x35FFFFFF virt:0xF3500000-0xF35FFFFF size:0x01000000 */
41 IO_DESC(MM_IO_BASE_APM, SZ_1M), /* phys:0x36000000-0x36FFFFFF virt:0xF3600000-0xF36FFFFF size:0x01000000 */
42 IO_DESC(MM_IO_BASE_SPUM, SZ_1M), /* phys:0x37000000-0x37FFFFFF virt:0xF3700000-0xF37FFFFF size:0x01000000 */
43 IO_DESC(MM_IO_BASE_VPM_PROG, SZ_1M), /* phys:0x38000000-0x38FFFFFF virt:0xF3800000-0xF38FFFFF size:0x01000000 */
44 IO_DESC(MM_IO_BASE_VPM_DATA, SZ_1M), /* phys:0x3A000000-0x3AFFFFFF virt:0xF3A00000-0xF3AFFFFF size:0x01000000 */
45
46 IO_DESC(MM_IO_BASE_VRAM, SZ_64K), /* phys:0x40000000-0x4000FFFF virt:0xF4000000-0xF400FFFF size:0x00010000 */
47 IO_DESC(MM_IO_BASE_CHIPC, SZ_16M), /* phys:0x80000000-0x80FFFFFF virt:0xF8000000-0xF8FFFFFF size:0x01000000 */
48 IO_DESC(MM_IO_BASE_VPM_EXTMEM_RSVD,
49 SZ_16M), /* phys:0x0F000000-0x0FFFFFFF virt:0xF0000000-0xF0FFFFFF size:0x01000000 */
50};
51
52void __init bcmring_map_io(void)
53{
54
55 iotable_init(bcmring_io_desc, ARRAY_SIZE(bcmring_io_desc));
56}
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-21 04:03:39 -0400