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-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/cap.h63
-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/cap_inline.h409
-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h1123
-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h1673
-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h530
-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h872
-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h145
-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h406
-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h73
-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h246
-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/mm_addr.h101
-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/mm_io.h147
-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/secHw_def.h100
-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h79
-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/tmrHw_reg.h82
15 files changed, 6049 insertions, 0 deletions
diff --git a/arch/arm/mach-bcmring/include/mach/csp/cap.h b/arch/arm/mach-bcmring/include/mach/csp/cap.h
new file mode 100644
index 00000000000..30fa2d54063
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/cap.h
@@ -0,0 +1,63 @@
1/*****************************************************************************
2* Copyright 2009 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15#ifndef CAP_H
16#define CAP_H
17
18/* ---- Include Files ---------------------------------------------------- */
19/* ---- Public Constants and Types --------------------------------------- */
20typedef enum {
21 CAP_NOT_PRESENT = 0,
22 CAP_PRESENT
23} CAP_RC_T;
24
25typedef enum {
26 CAP_VPM,
27 CAP_ETH_PHY,
28 CAP_ETH_GMII,
29 CAP_ETH_SGMII,
30 CAP_USB,
31 CAP_TSC,
32 CAP_EHSS,
33 CAP_SDIO,
34 CAP_UARTB,
35 CAP_KEYPAD,
36 CAP_CLCD,
37 CAP_GE,
38 CAP_LEDM,
39 CAP_BBL,
40 CAP_VDEC,
41 CAP_PIF,
42 CAP_APM,
43 CAP_SPU,
44 CAP_PKA,
45 CAP_RNG,
46} CAP_CAPABILITY_T;
47
48typedef enum {
49 CAP_LCD_WVGA = 0,
50 CAP_LCD_VGA = 0x1,
51 CAP_LCD_WQVGA = 0x2,
52 CAP_LCD_QVGA = 0x3
53} CAP_LCD_RES_T;
54
55/* ---- Public Variable Externs ------------------------------------------ */
56/* ---- Public Function Prototypes --------------------------------------- */
57
58static inline CAP_RC_T cap_isPresent(CAP_CAPABILITY_T capability, int index);
59static inline uint32_t cap_getMaxArmSpeedHz(void);
60static inline uint32_t cap_getMaxVpmSpeedHz(void);
61static inline CAP_LCD_RES_T cap_getMaxLcdRes(void);
62
63#endif
diff --git a/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h b/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h
new file mode 100644
index 00000000000..933ce68ed90
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h
@@ -0,0 +1,409 @@
1/*****************************************************************************
2* Copyright 2009 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15#ifndef CAP_INLINE_H
16#define CAP_INLINE_H
17
18/* ---- Include Files ---------------------------------------------------- */
19#include <mach/csp/cap.h>
20#include <cfg_global.h>
21
22/* ---- Public Constants and Types --------------------------------------- */
23#define CAP_CONFIG0_VPM_DIS 0x00000001
24#define CAP_CONFIG0_ETH_PHY0_DIS 0x00000002
25#define CAP_CONFIG0_ETH_PHY1_DIS 0x00000004
26#define CAP_CONFIG0_ETH_GMII0_DIS 0x00000008
27#define CAP_CONFIG0_ETH_GMII1_DIS 0x00000010
28#define CAP_CONFIG0_ETH_SGMII0_DIS 0x00000020
29#define CAP_CONFIG0_ETH_SGMII1_DIS 0x00000040
30#define CAP_CONFIG0_USB0_DIS 0x00000080
31#define CAP_CONFIG0_USB1_DIS 0x00000100
32#define CAP_CONFIG0_TSC_DIS 0x00000200
33#define CAP_CONFIG0_EHSS0_DIS 0x00000400
34#define CAP_CONFIG0_EHSS1_DIS 0x00000800
35#define CAP_CONFIG0_SDIO0_DIS 0x00001000
36#define CAP_CONFIG0_SDIO1_DIS 0x00002000
37#define CAP_CONFIG0_UARTB_DIS 0x00004000
38#define CAP_CONFIG0_KEYPAD_DIS 0x00008000
39#define CAP_CONFIG0_CLCD_DIS 0x00010000
40#define CAP_CONFIG0_GE_DIS 0x00020000
41#define CAP_CONFIG0_LEDM_DIS 0x00040000
42#define CAP_CONFIG0_BBL_DIS 0x00080000
43#define CAP_CONFIG0_VDEC_DIS 0x00100000
44#define CAP_CONFIG0_PIF_DIS 0x00200000
45#define CAP_CONFIG0_RESERVED1_DIS 0x00400000
46#define CAP_CONFIG0_RESERVED2_DIS 0x00800000
47
48#define CAP_CONFIG1_APMA_DIS 0x00000001
49#define CAP_CONFIG1_APMB_DIS 0x00000002
50#define CAP_CONFIG1_APMC_DIS 0x00000004
51#define CAP_CONFIG1_CLCD_RES_MASK 0x00000600
52#define CAP_CONFIG1_CLCD_RES_SHIFT 9
53#define CAP_CONFIG1_CLCD_RES_WVGA (CAP_LCD_WVGA << CAP_CONFIG1_CLCD_RES_SHIFT)
54#define CAP_CONFIG1_CLCD_RES_VGA (CAP_LCD_VGA << CAP_CONFIG1_CLCD_RES_SHIFT)
55#define CAP_CONFIG1_CLCD_RES_WQVGA (CAP_LCD_WQVGA << CAP_CONFIG1_CLCD_RES_SHIFT)
56#define CAP_CONFIG1_CLCD_RES_QVGA (CAP_LCD_QVGA << CAP_CONFIG1_CLCD_RES_SHIFT)
57
58#define CAP_CONFIG2_SPU_DIS 0x00000010
59#define CAP_CONFIG2_PKA_DIS 0x00000020
60#define CAP_CONFIG2_RNG_DIS 0x00000080
61
62#if (CFG_GLOBAL_CHIP == BCM11107)
63#define capConfig0 0
64#define capConfig1 CAP_CONFIG1_CLCD_RES_WVGA
65#define capConfig2 0
66#define CAP_APM_MAX_NUM_CHANS 3
67#elif (CFG_GLOBAL_CHIP == FPGA11107)
68#define capConfig0 0
69#define capConfig1 CAP_CONFIG1_CLCD_RES_WVGA
70#define capConfig2 0
71#define CAP_APM_MAX_NUM_CHANS 3
72#elif (CFG_GLOBAL_CHIP == BCM11109)
73#define capConfig0 (CAP_CONFIG0_USB1_DIS | CAP_CONFIG0_EHSS1_DIS | CAP_CONFIG0_SDIO1_DIS | CAP_CONFIG0_GE_DIS | CAP_CONFIG0_BBL_DIS | CAP_CONFIG0_VDEC_DIS)
74#define capConfig1 (CAP_CONFIG1_APMC_DIS | CAP_CONFIG1_CLCD_RES_WQVGA)
75#define capConfig2 (CAP_CONFIG2_SPU_DIS | CAP_CONFIG2_PKA_DIS)
76#define CAP_APM_MAX_NUM_CHANS 2
77#elif (CFG_GLOBAL_CHIP == BCM11170)
78#define capConfig0 (CAP_CONFIG0_ETH_GMII0_DIS | CAP_CONFIG0_ETH_GMII1_DIS | CAP_CONFIG0_USB0_DIS | CAP_CONFIG0_USB1_DIS | CAP_CONFIG0_TSC_DIS | CAP_CONFIG0_EHSS1_DIS | CAP_CONFIG0_SDIO0_DIS | CAP_CONFIG0_SDIO1_DIS | CAP_CONFIG0_UARTB_DIS | CAP_CONFIG0_CLCD_DIS | CAP_CONFIG0_GE_DIS | CAP_CONFIG0_BBL_DIS | CAP_CONFIG0_VDEC_DIS)
79#define capConfig1 (CAP_CONFIG1_APMC_DIS | CAP_CONFIG1_CLCD_RES_WQVGA)
80#define capConfig2 (CAP_CONFIG2_SPU_DIS | CAP_CONFIG2_PKA_DIS)
81#define CAP_APM_MAX_NUM_CHANS 2
82#elif (CFG_GLOBAL_CHIP == BCM11110)
83#define capConfig0 (CAP_CONFIG0_USB1_DIS | CAP_CONFIG0_TSC_DIS | CAP_CONFIG0_EHSS1_DIS | CAP_CONFIG0_SDIO0_DIS | CAP_CONFIG0_SDIO1_DIS | CAP_CONFIG0_UARTB_DIS | CAP_CONFIG0_GE_DIS | CAP_CONFIG0_BBL_DIS | CAP_CONFIG0_VDEC_DIS)
84#define capConfig1 CAP_CONFIG1_APMC_DIS
85#define capConfig2 (CAP_CONFIG2_SPU_DIS | CAP_CONFIG2_PKA_DIS)
86#define CAP_APM_MAX_NUM_CHANS 2
87#elif (CFG_GLOBAL_CHIP == BCM11211)
88#define capConfig0 (CAP_CONFIG0_ETH_PHY0_DIS | CAP_CONFIG0_ETH_GMII0_DIS | CAP_CONFIG0_ETH_GMII1_DIS | CAP_CONFIG0_ETH_SGMII0_DIS | CAP_CONFIG0_ETH_SGMII1_DIS | CAP_CONFIG0_CLCD_DIS)
89#define capConfig1 CAP_CONFIG1_APMC_DIS
90#define capConfig2 0
91#define CAP_APM_MAX_NUM_CHANS 2
92#else
93#error CFG_GLOBAL_CHIP type capabilities not defined
94#endif
95
96#if ((CFG_GLOBAL_CHIP == BCM11107) || (CFG_GLOBAL_CHIP == FPGA11107))
97#define CAP_HW_CFG_ARM_CLK_HZ 500000000
98#elif ((CFG_GLOBAL_CHIP == BCM11109) || (CFG_GLOBAL_CHIP == BCM11170) || (CFG_GLOBAL_CHIP == BCM11110))
99#define CAP_HW_CFG_ARM_CLK_HZ 300000000
100#elif (CFG_GLOBAL_CHIP == BCM11211)
101#define CAP_HW_CFG_ARM_CLK_HZ 666666666
102#else
103#error CFG_GLOBAL_CHIP type capabilities not defined
104#endif
105
106#if ((CFG_GLOBAL_CHIP == BCM11107) || (CFG_GLOBAL_CHIP == BCM11211) || (CFG_GLOBAL_CHIP == FPGA11107))
107#define CAP_HW_CFG_VPM_CLK_HZ 333333333
108#elif ((CFG_GLOBAL_CHIP == BCM11109) || (CFG_GLOBAL_CHIP == BCM11170) || (CFG_GLOBAL_CHIP == BCM11110))
109#define CAP_HW_CFG_VPM_CLK_HZ 200000000
110#else
111#error CFG_GLOBAL_CHIP type capabilities not defined
112#endif
113
114/* ---- Public Variable Externs ------------------------------------------ */
115/* ---- Public Function Prototypes --------------------------------------- */
116
117/****************************************************************************
118* cap_isPresent -
119*
120* PURPOSE:
121* Determines if the chip has a certain capability present
122*
123* PARAMETERS:
124* capability - type of capability to determine if present
125*
126* RETURNS:
127* CAP_PRESENT or CAP_NOT_PRESENT
128****************************************************************************/
129static inline CAP_RC_T cap_isPresent(CAP_CAPABILITY_T capability, int index)
130{
131 CAP_RC_T returnVal = CAP_NOT_PRESENT;
132
133 switch (capability) {
134 case CAP_VPM:
135 {
136 if (!(capConfig0 & CAP_CONFIG0_VPM_DIS)) {
137 returnVal = CAP_PRESENT;
138 }
139 }
140 break;
141
142 case CAP_ETH_PHY:
143 {
144 if ((index == 0)
145 && (!(capConfig0 & CAP_CONFIG0_ETH_PHY0_DIS))) {
146 returnVal = CAP_PRESENT;
147 }
148 if ((index == 1)
149 && (!(capConfig0 & CAP_CONFIG0_ETH_PHY1_DIS))) {
150 returnVal = CAP_PRESENT;
151 }
152 }
153 break;
154
155 case CAP_ETH_GMII:
156 {
157 if ((index == 0)
158 && (!(capConfig0 & CAP_CONFIG0_ETH_GMII0_DIS))) {
159 returnVal = CAP_PRESENT;
160 }
161 if ((index == 1)
162 && (!(capConfig0 & CAP_CONFIG0_ETH_GMII1_DIS))) {
163 returnVal = CAP_PRESENT;
164 }
165 }
166 break;
167
168 case CAP_ETH_SGMII:
169 {
170 if ((index == 0)
171 && (!(capConfig0 & CAP_CONFIG0_ETH_SGMII0_DIS))) {
172 returnVal = CAP_PRESENT;
173 }
174 if ((index == 1)
175 && (!(capConfig0 & CAP_CONFIG0_ETH_SGMII1_DIS))) {
176 returnVal = CAP_PRESENT;
177 }
178 }
179 break;
180
181 case CAP_USB:
182 {
183 if ((index == 0)
184 && (!(capConfig0 & CAP_CONFIG0_USB0_DIS))) {
185 returnVal = CAP_PRESENT;
186 }
187 if ((index == 1)
188 && (!(capConfig0 & CAP_CONFIG0_USB1_DIS))) {
189 returnVal = CAP_PRESENT;
190 }
191 }
192 break;
193
194 case CAP_TSC:
195 {
196 if (!(capConfig0 & CAP_CONFIG0_TSC_DIS)) {
197 returnVal = CAP_PRESENT;
198 }
199 }
200 break;
201
202 case CAP_EHSS:
203 {
204 if ((index == 0)
205 && (!(capConfig0 & CAP_CONFIG0_EHSS0_DIS))) {
206 returnVal = CAP_PRESENT;
207 }
208 if ((index == 1)
209 && (!(capConfig0 & CAP_CONFIG0_EHSS1_DIS))) {
210 returnVal = CAP_PRESENT;
211 }
212 }
213 break;
214
215 case CAP_SDIO:
216 {
217 if ((index == 0)
218 && (!(capConfig0 & CAP_CONFIG0_SDIO0_DIS))) {
219 returnVal = CAP_PRESENT;
220 }
221 if ((index == 1)
222 && (!(capConfig0 & CAP_CONFIG0_SDIO1_DIS))) {
223 returnVal = CAP_PRESENT;
224 }
225 }
226 break;
227
228 case CAP_UARTB:
229 {
230 if (!(capConfig0 & CAP_CONFIG0_UARTB_DIS)) {
231 returnVal = CAP_PRESENT;
232 }
233 }
234 break;
235
236 case CAP_KEYPAD:
237 {
238 if (!(capConfig0 & CAP_CONFIG0_KEYPAD_DIS)) {
239 returnVal = CAP_PRESENT;
240 }
241 }
242 break;
243
244 case CAP_CLCD:
245 {
246 if (!(capConfig0 & CAP_CONFIG0_CLCD_DIS)) {
247 returnVal = CAP_PRESENT;
248 }
249 }
250 break;
251
252 case CAP_GE:
253 {
254 if (!(capConfig0 & CAP_CONFIG0_GE_DIS)) {
255 returnVal = CAP_PRESENT;
256 }
257 }
258 break;
259
260 case CAP_LEDM:
261 {
262 if (!(capConfig0 & CAP_CONFIG0_LEDM_DIS)) {
263 returnVal = CAP_PRESENT;
264 }
265 }
266 break;
267
268 case CAP_BBL:
269 {
270 if (!(capConfig0 & CAP_CONFIG0_BBL_DIS)) {
271 returnVal = CAP_PRESENT;
272 }
273 }
274 break;
275
276 case CAP_VDEC:
277 {
278 if (!(capConfig0 & CAP_CONFIG0_VDEC_DIS)) {
279 returnVal = CAP_PRESENT;
280 }
281 }
282 break;
283
284 case CAP_PIF:
285 {
286 if (!(capConfig0 & CAP_CONFIG0_PIF_DIS)) {
287 returnVal = CAP_PRESENT;
288 }
289 }
290 break;
291
292 case CAP_APM:
293 {
294 if ((index == 0)
295 && (!(capConfig1 & CAP_CONFIG1_APMA_DIS))) {
296 returnVal = CAP_PRESENT;
297 }
298 if ((index == 1)
299 && (!(capConfig1 & CAP_CONFIG1_APMB_DIS))) {
300 returnVal = CAP_PRESENT;
301 }
302 if ((index == 2)
303 && (!(capConfig1 & CAP_CONFIG1_APMC_DIS))) {
304 returnVal = CAP_PRESENT;
305 }
306 }
307 break;
308
309 case CAP_SPU:
310 {
311 if (!(capConfig2 & CAP_CONFIG2_SPU_DIS)) {
312 returnVal = CAP_PRESENT;
313 }
314 }
315 break;
316
317 case CAP_PKA:
318 {
319 if (!(capConfig2 & CAP_CONFIG2_PKA_DIS)) {
320 returnVal = CAP_PRESENT;
321 }
322 }
323 break;
324
325 case CAP_RNG:
326 {
327 if (!(capConfig2 & CAP_CONFIG2_RNG_DIS)) {
328 returnVal = CAP_PRESENT;
329 }
330 }
331 break;
332
333 default:
334 {
335 }
336 break;
337 }
338 return returnVal;
339}
340
341/****************************************************************************
342* cap_getMaxArmSpeedHz -
343*
344* PURPOSE:
345* Determines the maximum speed of the ARM CPU
346*
347* PARAMETERS:
348* none
349*
350* RETURNS:
351* clock speed in Hz that the ARM processor is able to run at
352****************************************************************************/
353static inline uint32_t cap_getMaxArmSpeedHz(void)
354{
355#if ((CFG_GLOBAL_CHIP == BCM11107) || (CFG_GLOBAL_CHIP == FPGA11107))
356 return 500000000;
357#elif ((CFG_GLOBAL_CHIP == BCM11109) || (CFG_GLOBAL_CHIP == BCM11170) || (CFG_GLOBAL_CHIP == BCM11110))
358 return 300000000;
359#elif (CFG_GLOBAL_CHIP == BCM11211)
360 return 666666666;
361#else
362#error CFG_GLOBAL_CHIP type capabilities not defined
363#endif
364}
365
366/****************************************************************************
367* cap_getMaxVpmSpeedHz -
368*
369* PURPOSE:
370* Determines the maximum speed of the VPM
371*
372* PARAMETERS:
373* none
374*
375* RETURNS:
376* clock speed in Hz that the VPM is able to run at
377****************************************************************************/
378static inline uint32_t cap_getMaxVpmSpeedHz(void)
379{
380#if ((CFG_GLOBAL_CHIP == BCM11107) || (CFG_GLOBAL_CHIP == BCM11211) || (CFG_GLOBAL_CHIP == FPGA11107))
381 return 333333333;
382#elif ((CFG_GLOBAL_CHIP == BCM11109) || (CFG_GLOBAL_CHIP == BCM11170) || (CFG_GLOBAL_CHIP == BCM11110))
383 return 200000000;
384#else
385#error CFG_GLOBAL_CHIP type capabilities not defined
386#endif
387}
388
389/****************************************************************************
390* cap_getMaxLcdRes -
391*
392* PURPOSE:
393* Determines the maximum LCD resolution capabilities
394*
395* PARAMETERS:
396* none
397*
398* RETURNS:
399* CAP_LCD_WVGA, CAP_LCD_VGA, CAP_LCD_WQVGA or CAP_LCD_QVGA
400*
401****************************************************************************/
402static inline CAP_LCD_RES_T cap_getMaxLcdRes(void)
403{
404 return (CAP_LCD_RES_T)
405 ((capConfig1 & CAP_CONFIG1_CLCD_RES_MASK) >>
406 CAP_CONFIG1_CLCD_RES_SHIFT);
407}
408
409#endif
diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h
new file mode 100644
index 00000000000..161973385fa
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h
@@ -0,0 +1,1123 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15#ifndef CHIPC_DEF_H
16#define CHIPC_DEF_H
17
18/* ---- Include Files ----------------------------------------------------- */
19
20#include <csp/stdint.h>
21#include <csp/errno.h>
22#include <csp/reg.h>
23#include <mach/csp/chipcHw_reg.h>
24
25/* ---- Public Constants and Types ---------------------------------------- */
26
27/* Set 1 to configure DDR/VPM phase alignment by HW */
28#define chipcHw_DDR_HW_PHASE_ALIGN 0
29#define chipcHw_VPM_HW_PHASE_ALIGN 0
30
31typedef uint32_t chipcHw_freq;
32
33/* Configurable miscellaneous clocks */
34typedef enum {
35 chipcHw_CLOCK_DDR, /* DDR PHY Clock */
36 chipcHw_CLOCK_ARM, /* ARM Clock */
37 chipcHw_CLOCK_ESW, /* Ethernet Switch Clock */
38 chipcHw_CLOCK_VPM, /* VPM Clock */
39 chipcHw_CLOCK_ESW125, /* Ethernet MII Clock */
40 chipcHw_CLOCK_UART, /* UART Clock */
41 chipcHw_CLOCK_SDIO0, /* SDIO 0 Clock */
42 chipcHw_CLOCK_SDIO1, /* SDIO 1 Clock */
43 chipcHw_CLOCK_SPI, /* SPI Clock */
44 chipcHw_CLOCK_ETM, /* ARM ETM Clock */
45
46 chipcHw_CLOCK_BUS, /* BUS Clock */
47 chipcHw_CLOCK_OTP, /* OTP Clock */
48 chipcHw_CLOCK_I2C, /* I2C Host Clock */
49 chipcHw_CLOCK_I2S0, /* I2S 0 Host Clock */
50 chipcHw_CLOCK_RTBUS, /* DDR PHY Configuration Clock */
51 chipcHw_CLOCK_APM100, /* APM100 Clock */
52 chipcHw_CLOCK_TSC, /* Touch screen Clock */
53 chipcHw_CLOCK_LED, /* LED Clock */
54
55 chipcHw_CLOCK_USB, /* USB Clock */
56 chipcHw_CLOCK_LCD, /* LCD CLock */
57 chipcHw_CLOCK_APM, /* APM Clock */
58
59 chipcHw_CLOCK_I2S1, /* I2S 1 Host Clock */
60} chipcHw_CLOCK_e;
61
62/* System booting strap options */
63typedef enum {
64 chipcHw_BOOT_DEVICE_UART = chipcHw_STRAPS_BOOT_DEVICE_UART,
65 chipcHw_BOOT_DEVICE_SERIAL_FLASH =
66 chipcHw_STRAPS_BOOT_DEVICE_SERIAL_FLASH,
67 chipcHw_BOOT_DEVICE_NOR_FLASH_16 =
68 chipcHw_STRAPS_BOOT_DEVICE_NOR_FLASH_16,
69 chipcHw_BOOT_DEVICE_NAND_FLASH_8 =
70 chipcHw_STRAPS_BOOT_DEVICE_NAND_FLASH_8,
71 chipcHw_BOOT_DEVICE_NAND_FLASH_16 =
72 chipcHw_STRAPS_BOOT_DEVICE_NAND_FLASH_16
73} chipcHw_BOOT_DEVICE_e;
74
75/* System booting modes */
76typedef enum {
77 chipcHw_BOOT_MODE_NORMAL = chipcHw_STRAPS_BOOT_MODE_NORMAL,
78 chipcHw_BOOT_MODE_DBG_SW = chipcHw_STRAPS_BOOT_MODE_DBG_SW,
79 chipcHw_BOOT_MODE_DBG_BOOT = chipcHw_STRAPS_BOOT_MODE_DBG_BOOT,
80 chipcHw_BOOT_MODE_NORMAL_QUIET = chipcHw_STRAPS_BOOT_MODE_NORMAL_QUIET
81} chipcHw_BOOT_MODE_e;
82
83/* NAND Flash page size strap options */
84typedef enum {
85 chipcHw_NAND_PAGESIZE_512 = chipcHw_STRAPS_NAND_PAGESIZE_512,
86 chipcHw_NAND_PAGESIZE_2048 = chipcHw_STRAPS_NAND_PAGESIZE_2048,
87 chipcHw_NAND_PAGESIZE_4096 = chipcHw_STRAPS_NAND_PAGESIZE_4096,
88 chipcHw_NAND_PAGESIZE_EXT = chipcHw_STRAPS_NAND_PAGESIZE_EXT
89} chipcHw_NAND_PAGESIZE_e;
90
91/* GPIO Pin function */
92typedef enum {
93 chipcHw_GPIO_FUNCTION_KEYPAD = chipcHw_REG_GPIO_MUX_KEYPAD,
94 chipcHw_GPIO_FUNCTION_I2CH = chipcHw_REG_GPIO_MUX_I2CH,
95 chipcHw_GPIO_FUNCTION_SPI = chipcHw_REG_GPIO_MUX_SPI,
96 chipcHw_GPIO_FUNCTION_UART = chipcHw_REG_GPIO_MUX_UART,
97 chipcHw_GPIO_FUNCTION_LEDMTXP = chipcHw_REG_GPIO_MUX_LEDMTXP,
98 chipcHw_GPIO_FUNCTION_LEDMTXS = chipcHw_REG_GPIO_MUX_LEDMTXS,
99 chipcHw_GPIO_FUNCTION_SDIO0 = chipcHw_REG_GPIO_MUX_SDIO0,
100 chipcHw_GPIO_FUNCTION_SDIO1 = chipcHw_REG_GPIO_MUX_SDIO1,
101 chipcHw_GPIO_FUNCTION_PCM = chipcHw_REG_GPIO_MUX_PCM,
102 chipcHw_GPIO_FUNCTION_I2S = chipcHw_REG_GPIO_MUX_I2S,
103 chipcHw_GPIO_FUNCTION_ETM = chipcHw_REG_GPIO_MUX_ETM,
104 chipcHw_GPIO_FUNCTION_DEBUG = chipcHw_REG_GPIO_MUX_DEBUG,
105 chipcHw_GPIO_FUNCTION_MISC = chipcHw_REG_GPIO_MUX_MISC,
106 chipcHw_GPIO_FUNCTION_GPIO = chipcHw_REG_GPIO_MUX_GPIO
107} chipcHw_GPIO_FUNCTION_e;
108
109/* PIN Output slew rate */
110typedef enum {
111 chipcHw_PIN_SLEW_RATE_HIGH = chipcHw_REG_SLEW_RATE_HIGH,
112 chipcHw_PIN_SLEW_RATE_NORMAL = chipcHw_REG_SLEW_RATE_NORMAL
113} chipcHw_PIN_SLEW_RATE_e;
114
115/* PIN Current drive strength */
116typedef enum {
117 chipcHw_PIN_CURRENT_STRENGTH_2mA = chipcHw_REG_CURRENT_STRENGTH_2mA,
118 chipcHw_PIN_CURRENT_STRENGTH_4mA = chipcHw_REG_CURRENT_STRENGTH_4mA,
119 chipcHw_PIN_CURRENT_STRENGTH_6mA = chipcHw_REG_CURRENT_STRENGTH_6mA,
120 chipcHw_PIN_CURRENT_STRENGTH_8mA = chipcHw_REG_CURRENT_STRENGTH_8mA,
121 chipcHw_PIN_CURRENT_STRENGTH_10mA = chipcHw_REG_CURRENT_STRENGTH_10mA,
122 chipcHw_PIN_CURRENT_STRENGTH_12mA = chipcHw_REG_CURRENT_STRENGTH_12mA
123} chipcHw_PIN_CURRENT_STRENGTH_e;
124
125/* PIN Pull up register settings */
126typedef enum {
127 chipcHw_PIN_PULL_NONE = chipcHw_REG_PULL_NONE,
128 chipcHw_PIN_PULL_UP = chipcHw_REG_PULL_UP,
129 chipcHw_PIN_PULL_DOWN = chipcHw_REG_PULL_DOWN
130} chipcHw_PIN_PULL_e;
131
132/* PIN input type settings */
133typedef enum {
134 chipcHw_PIN_INPUTTYPE_CMOS = chipcHw_REG_INPUTTYPE_CMOS,
135 chipcHw_PIN_INPUTTYPE_ST = chipcHw_REG_INPUTTYPE_ST
136} chipcHw_PIN_INPUTTYPE_e;
137
138/* Allow/Disalow the support of spread spectrum */
139typedef enum {
140 chipcHw_SPREAD_SPECTRUM_DISALLOW, /* Spread spectrum support is not allowed */
141 chipcHw_SPREAD_SPECTRUM_ALLOW /* Spread spectrum support is allowed */
142} chipcHw_SPREAD_SPECTRUM_e;
143
144typedef struct {
145 chipcHw_SPREAD_SPECTRUM_e ssSupport; /* Allow/Disalow to support spread spectrum.
146 If supported, call chipcHw_enableSpreadSpectrum ()
147 to activate the spread spectrum with desired spread. */
148 uint32_t pllVcoFreqHz; /* PLL VCO frequency in Hz */
149 uint32_t pll2VcoFreqHz; /* PLL2 VCO frequency in Hz */
150 uint32_t busClockFreqHz; /* Bus clock frequency in Hz */
151 uint32_t armBusRatio; /* ARM clock : Bus clock */
152 uint32_t vpmBusRatio; /* VPM clock : Bus clock */
153 uint32_t ddrBusRatio; /* DDR clock : Bus clock */
154} chipcHw_INIT_PARAM_t;
155
156/* CHIP revision number */
157typedef enum {
158 chipcHw_REV_NUMBER_A0 = chipcHw_REG_REV_A0,
159 chipcHw_REV_NUMBER_B0 = chipcHw_REG_REV_B0
160} chipcHw_REV_NUMBER_e;
161
162typedef enum {
163 chipcHw_VPM_HW_PHASE_INTR_DISABLE = chipcHw_REG_VPM_INTR_DISABLE,
164 chipcHw_VPM_HW_PHASE_INTR_FAST = chipcHw_REG_VPM_INTR_FAST,
165 chipcHw_VPM_HW_PHASE_INTR_MEDIUM = chipcHw_REG_VPM_INTR_MEDIUM,
166 chipcHw_VPM_HW_PHASE_INTR_SLOW = chipcHw_REG_VPM_INTR_SLOW
167} chipcHw_VPM_HW_PHASE_INTR_e;
168
169typedef enum {
170 chipcHw_DDR_HW_PHASE_MARGIN_STRICT, /* Strict margin for DDR phase align condition */
171 chipcHw_DDR_HW_PHASE_MARGIN_MEDIUM, /* Medium margin for DDR phase align condition */
172 chipcHw_DDR_HW_PHASE_MARGIN_WIDE /* Wider margin for DDR phase align condition */
173} chipcHw_DDR_HW_PHASE_MARGIN_e;
174
175typedef enum {
176 chipcHw_VPM_HW_PHASE_MARGIN_STRICT, /* Strict margin for VPM phase align condition */
177 chipcHw_VPM_HW_PHASE_MARGIN_MEDIUM, /* Medium margin for VPM phase align condition */
178 chipcHw_VPM_HW_PHASE_MARGIN_WIDE /* Wider margin for VPM phase align condition */
179} chipcHw_VPM_HW_PHASE_MARGIN_e;
180
181#define chipcHw_XTAL_FREQ_Hz 25000000 /* Reference clock frequency in Hz */
182
183/* Programmable pin defines */
184#define chipcHw_PIN_GPIO(n) ((((n) >= 0) && ((n) < (chipcHw_GPIO_COUNT))) ? (n) : 0xFFFFFFFF)
185 /* GPIO pin 0 - 60 */
186#define chipcHw_PIN_UARTTXD (chipcHw_GPIO_COUNT + 0) /* UART Transmit */
187#define chipcHw_PIN_NVI_A (chipcHw_GPIO_COUNT + 1) /* NVI Interface */
188#define chipcHw_PIN_NVI_D (chipcHw_GPIO_COUNT + 2) /* NVI Interface */
189#define chipcHw_PIN_NVI_OEB (chipcHw_GPIO_COUNT + 3) /* NVI Interface */
190#define chipcHw_PIN_NVI_WEB (chipcHw_GPIO_COUNT + 4) /* NVI Interface */
191#define chipcHw_PIN_NVI_CS (chipcHw_GPIO_COUNT + 5) /* NVI Interface */
192#define chipcHw_PIN_NVI_NAND_CSB (chipcHw_GPIO_COUNT + 6) /* NVI Interface */
193#define chipcHw_PIN_NVI_FLASHWP (chipcHw_GPIO_COUNT + 7) /* NVI Interface */
194#define chipcHw_PIN_NVI_NAND_RDYB (chipcHw_GPIO_COUNT + 8) /* NVI Interface */
195#define chipcHw_PIN_CL_DATA_0_17 (chipcHw_GPIO_COUNT + 9) /* LCD Data 0 - 17 */
196#define chipcHw_PIN_CL_DATA_18_20 (chipcHw_GPIO_COUNT + 10) /* LCD Data 18 - 20 */
197#define chipcHw_PIN_CL_DATA_21_23 (chipcHw_GPIO_COUNT + 11) /* LCD Data 21 - 23 */
198#define chipcHw_PIN_CL_POWER (chipcHw_GPIO_COUNT + 12) /* LCD Power */
199#define chipcHw_PIN_CL_ACK (chipcHw_GPIO_COUNT + 13) /* LCD Ack */
200#define chipcHw_PIN_CL_FP (chipcHw_GPIO_COUNT + 14) /* LCD FP */
201#define chipcHw_PIN_CL_LP (chipcHw_GPIO_COUNT + 15) /* LCD LP */
202#define chipcHw_PIN_UARTRXD (chipcHw_GPIO_COUNT + 16) /* UART Receive */
203
204/* ---- Public Variable Externs ------------------------------------------ */
205/* ---- Public Function Prototypes --------------------------------------- */
206
207/****************************************************************************/
208/**
209* @brief Initializes the clock module
210*
211*/
212/****************************************************************************/
213void chipcHw_Init(chipcHw_INIT_PARAM_t *initParam /* [ IN ] Misc chip initialization parameter */
214 ) __attribute__ ((section(".aramtext")));
215
216/****************************************************************************/
217/**
218* @brief Enables the PLL1
219*
220* This function enables the PLL1
221*
222*/
223/****************************************************************************/
224void chipcHw_pll1Enable(uint32_t vcoFreqHz, /* [ IN ] VCO frequency in Hz */
225 chipcHw_SPREAD_SPECTRUM_e ssSupport /* [ IN ] SS status */
226 ) __attribute__ ((section(".aramtext")));
227
228/****************************************************************************/
229/**
230* @brief Enables the PLL2
231*
232* This function enables the PLL2
233*
234*/
235/****************************************************************************/
236void chipcHw_pll2Enable(uint32_t vcoFreqHz /* [ IN ] VCO frequency in Hz */
237 ) __attribute__ ((section(".aramtext")));
238
239/****************************************************************************/
240/**
241* @brief Disable the PLL1
242*
243*/
244/****************************************************************************/
245static inline void chipcHw_pll1Disable(void);
246
247/****************************************************************************/
248/**
249* @brief Disable the PLL2
250*
251*/
252/****************************************************************************/
253static inline void chipcHw_pll2Disable(void);
254
255/****************************************************************************/
256/**
257* @brief Set clock fequency for miscellaneous configurable clocks
258*
259* This function sets clock frequency
260*
261* @return Configured clock frequency in KHz
262*
263*/
264/****************************************************************************/
265chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock /* [ IN ] Configurable clock */
266 ) __attribute__ ((section(".aramtext")));
267
268/****************************************************************************/
269/**
270* @brief Set clock fequency for miscellaneous configurable clocks
271*
272* This function sets clock frequency
273*
274* @return Configured clock frequency in Hz
275*
276*/
277/****************************************************************************/
278chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configurable clock */
279 uint32_t freq /* [ IN ] Clock frequency in Hz */
280 ) __attribute__ ((section(".aramtext")));
281
282/****************************************************************************/
283/**
284* @brief Set VPM clock in sync with BUS clock
285*
286* This function does the phase adjustment between VPM and BUS clock
287*
288* @return >= 0 : On success ( # of adjustment required )
289* -1 : On failure
290*/
291/****************************************************************************/
292int chipcHw_vpmPhaseAlign(void);
293
294/****************************************************************************/
295/**
296* @brief Enables core a clock of a certain device
297*
298* This function enables a core clock
299*
300* @return void
301*
302* @note Doesnot affect the bus interface clock
303*/
304/****************************************************************************/
305static inline void chipcHw_setClockEnable(chipcHw_CLOCK_e clock /* [ IN ] Configurable clock */
306 );
307
308/****************************************************************************/
309/**
310* @brief Disabled a core clock of a certain device
311*
312* This function disables a core clock
313*
314* @return void
315*
316* @note Doesnot affect the bus interface clock
317*/
318/****************************************************************************/
319static inline void chipcHw_setClockDisable(chipcHw_CLOCK_e clock /* [ IN ] Configurable clock */
320 );
321
322/****************************************************************************/
323/**
324* @brief Enables bypass clock of a certain device
325*
326* This function enables bypass clock
327*
328* @note Doesnot affect the bus interface clock
329*/
330/****************************************************************************/
331static inline void chipcHw_bypassClockEnable(chipcHw_CLOCK_e clock /* [ IN ] Configurable clock */
332 );
333
334/****************************************************************************/
335/**
336* @brief Disabled bypass clock of a certain device
337*
338* This function disables bypass clock
339*
340* @note Doesnot affect the bus interface clock
341*/
342/****************************************************************************/
343static inline void chipcHw_bypassClockDisable(chipcHw_CLOCK_e clock /* [ IN ] Configurable clock */
344 );
345
346/****************************************************************************/
347/**
348* @brief Get Numeric Chip ID
349*
350* This function returns Chip ID that includes the revison number
351*
352* @return Complete numeric Chip ID
353*
354*/
355/****************************************************************************/
356static inline uint32_t chipcHw_getChipId(void);
357
358/****************************************************************************/
359/**
360* @brief Get Chip Product ID
361*
362* This function returns Chip Product ID
363*
364* @return Chip Product ID
365*/
366/****************************************************************************/
367static inline uint32_t chipcHw_getChipProductId(void);
368
369/****************************************************************************/
370/**
371* @brief Get revision number
372*
373* This function returns revision number of the chip
374*
375* @return Revision number
376*/
377/****************************************************************************/
378static inline chipcHw_REV_NUMBER_e chipcHw_getChipRevisionNumber(void);
379
380/****************************************************************************/
381/**
382* @brief Enables bus interface clock
383*
384* Enables bus interface clock of various device
385*
386* @return void
387*
388* @note use chipcHw_REG_BUS_CLOCK_XXXX
389*/
390/****************************************************************************/
391static inline void chipcHw_busInterfaceClockEnable(uint32_t mask /* [ IN ] Bit map of type chipcHw_REG_BUS_CLOCK_XXXXX */
392 );
393
394/****************************************************************************/
395/**
396* @brief Disables bus interface clock
397*
398* Disables bus interface clock of various device
399*
400* @return void
401*
402* @note use chipcHw_REG_BUS_CLOCK_XXXX
403*/
404/****************************************************************************/
405static inline void chipcHw_busInterfaceClockDisable(uint32_t mask /* [ IN ] Bit map of type chipcHw_REG_BUS_CLOCK_XXXXX */
406 );
407
408/****************************************************************************/
409/**
410* @brief Enables various audio channels
411*
412* Enables audio channel
413*
414* @return void
415*
416* @note use chipcHw_REG_AUDIO_CHANNEL_XXXXXX
417*/
418/****************************************************************************/
419static inline void chipcHw_audioChannelEnable(uint32_t mask /* [ IN ] Bit map of type chipcHw_REG_AUDIO_CHANNEL_XXXXXX */
420 );
421
422/****************************************************************************/
423/**
424* @brief Disables various audio channels
425*
426* Disables audio channel
427*
428* @return void
429*
430* @note use chipcHw_REG_AUDIO_CHANNEL_XXXXXX
431*/
432/****************************************************************************/
433static inline void chipcHw_audioChannelDisable(uint32_t mask /* [ IN ] Bit map of type chipcHw_REG_AUDIO_CHANNEL_XXXXXX */
434 );
435
436/****************************************************************************/
437/**
438* @brief Soft resets devices
439*
440* Soft resets various devices
441*
442* @return void
443*
444* @note use chipcHw_REG_SOFT_RESET_XXXXXX defines
445*/
446/****************************************************************************/
447static inline void chipcHw_softReset(uint64_t mask /* [ IN ] Bit map of type chipcHw_REG_SOFT_RESET_XXXXXX */
448 );
449
450static inline void chipcHw_softResetDisable(uint64_t mask /* [ IN ] Bit map of type chipcHw_REG_SOFT_RESET_XXXXXX */
451 );
452
453static inline void chipcHw_softResetEnable(uint64_t mask /* [ IN ] Bit map of type chipcHw_REG_SOFT_RESET_XXXXXX */
454 );
455
456/****************************************************************************/
457/**
458* @brief Configures misc CHIP functionality
459*
460* Configures CHIP functionality
461*
462* @return void
463*
464* @note use chipcHw_REG_MISC_CTRL_XXXXXX
465*/
466/****************************************************************************/
467static inline void chipcHw_miscControl(uint32_t mask /* [ IN ] Bit map of type chipcHw_REG_MISC_CTRL_XXXXXX */
468 );
469
470static inline void chipcHw_miscControlDisable(uint32_t mask /* [ IN ] Bit map of type chipcHw_REG_MISC_CTRL_XXXXXX */
471 );
472
473static inline void chipcHw_miscControlEnable(uint32_t mask /* [ IN ] Bit map of type chipcHw_REG_MISC_CTRL_XXXXXX */
474 );
475
476/****************************************************************************/
477/**
478* @brief Set OTP options
479*
480* Set OTP options
481*
482* @return void
483*
484* @note use chipcHw_REG_OTP_XXXXXX
485*/
486/****************************************************************************/
487static inline void chipcHw_setOTPOption(uint64_t mask /* [ IN ] Bit map of type chipcHw_REG_OTP_XXXXXX */
488 );
489
490/****************************************************************************/
491/**
492* @brief Get sticky bits
493*
494* @return Sticky bit options of type chipcHw_REG_STICKY_XXXXXX
495*
496*/
497/****************************************************************************/
498static inline uint32_t chipcHw_getStickyBits(void);
499
500/****************************************************************************/
501/**
502* @brief Set sticky bits
503*
504* @return void
505*
506* @note use chipcHw_REG_STICKY_XXXXXX
507*/
508/****************************************************************************/
509static inline void chipcHw_setStickyBits(uint32_t mask /* [ IN ] Bit map of type chipcHw_REG_STICKY_XXXXXX */
510 );
511
512/****************************************************************************/
513/**
514* @brief Clear sticky bits
515*
516* @return void
517*
518* @note use chipcHw_REG_STICKY_XXXXXX
519*/
520/****************************************************************************/
521static inline void chipcHw_clearStickyBits(uint32_t mask /* [ IN ] Bit map of type chipcHw_REG_STICKY_XXXXXX */
522 );
523
524/****************************************************************************/
525/**
526* @brief Get software override strap options
527*
528* Retrieves software override strap options
529*
530* @return Software override strap value
531*
532*/
533/****************************************************************************/
534static inline uint32_t chipcHw_getSoftStraps(void);
535
536/****************************************************************************/
537/**
538* @brief Set software override strap options
539*
540* set software override strap options
541*
542* @return nothing
543*
544*/
545/****************************************************************************/
546static inline void chipcHw_setSoftStraps(uint32_t strapOptions);
547
548/****************************************************************************/
549/**
550* @brief Get pin strap options
551*
552* Retrieves pin strap options
553*
554* @return Pin strap value
555*
556*/
557/****************************************************************************/
558static inline uint32_t chipcHw_getPinStraps(void);
559
560/****************************************************************************/
561/**
562* @brief Get valid pin strap options
563*
564* Retrieves valid pin strap options
565*
566* @return valid Pin strap value
567*
568*/
569/****************************************************************************/
570static inline uint32_t chipcHw_getValidStraps(void);
571
572/****************************************************************************/
573/**
574* @brief Initialize valid pin strap options
575*
576* Retrieves valid pin strap options by copying HW strap options to soft register
577* (if chipcHw_STRAPS_SOFT_OVERRIDE not set)
578*
579* @return nothing
580*
581*/
582/****************************************************************************/
583static inline void chipcHw_initValidStraps(void);
584
585/****************************************************************************/
586/**
587* @brief Get status (enabled/disabled) of bus interface clock
588*
589* This function returns the status of devices' bus interface clock
590*
591* @return Bus interface clock
592*
593*/
594/****************************************************************************/
595static inline uint32_t chipcHw_getBusInterfaceClockStatus(void);
596
597/****************************************************************************/
598/**
599* @brief Get boot device
600*
601* This function returns the device type used in booting the system
602*
603* @return Boot device of type chipcHw_BOOT_DEVICE_e
604*
605*/
606/****************************************************************************/
607static inline chipcHw_BOOT_DEVICE_e chipcHw_getBootDevice(void);
608
609/****************************************************************************/
610/**
611* @brief Get boot mode
612*
613* This function returns the way the system was booted
614*
615* @return Boot mode of type chipcHw_BOOT_MODE_e
616*
617*/
618/****************************************************************************/
619static inline chipcHw_BOOT_MODE_e chipcHw_getBootMode(void);
620
621/****************************************************************************/
622/**
623* @brief Get NAND flash page size
624*
625* This function returns the NAND device page size
626*
627* @return Boot NAND device page size
628*
629*/
630/****************************************************************************/
631static inline chipcHw_NAND_PAGESIZE_e chipcHw_getNandPageSize(void);
632
633/****************************************************************************/
634/**
635* @brief Get NAND flash address cycle configuration
636*
637* This function returns the NAND flash address cycle configuration
638*
639* @return 0 = Do not extra address cycle, 1 = Add extra cycle
640*
641*/
642/****************************************************************************/
643static inline int chipcHw_getNandExtraCycle(void);
644
645/****************************************************************************/
646/**
647* @brief Activates PIF interface
648*
649* This function activates PIF interface by taking control of LCD pins
650*
651* @note
652* When activated, LCD pins will be defined as follows for PIF operation
653*
654* CLD[17:0] = pif_data[17:0]
655* CLD[23:18] = pif_address[5:0]
656* CLPOWER = pif_wr_str
657* CLCP = pif_rd_str
658* CLAC = pif_hat1
659* CLFP = pif_hrdy1
660* CLLP = pif_hat2
661* GPIO[42] = pif_hrdy2
662*
663* In PIF mode, "pif_hrdy2" overrides other shared function for GPIO[42] pin
664*
665*/
666/****************************************************************************/
667static inline void chipcHw_activatePifInterface(void);
668
669/****************************************************************************/
670/**
671* @brief Activates LCD interface
672*
673* This function activates LCD interface
674*
675* @note
676* When activated, LCD pins will be defined as follows
677*
678* CLD[17:0] = LCD data
679* CLD[23:18] = LCD data
680* CLPOWER = LCD power
681* CLCP =
682* CLAC = LCD ack
683* CLFP =
684* CLLP =
685*/
686/****************************************************************************/
687static inline void chipcHw_activateLcdInterface(void);
688
689/****************************************************************************/
690/**
691* @brief Deactivates PIF/LCD interface
692*
693* This function deactivates PIF/LCD interface
694*
695* @note
696* When deactivated LCD pins will be in rti-stated
697*
698*/
699/****************************************************************************/
700static inline void chipcHw_deactivatePifLcdInterface(void);
701
702/****************************************************************************/
703/**
704* @brief Get to know the configuration of GPIO pin
705*
706*/
707/****************************************************************************/
708static inline chipcHw_GPIO_FUNCTION_e chipcHw_getGpioPinFunction(int pin /* GPIO Pin number */
709 );
710
711/****************************************************************************/
712/**
713* @brief Configure GPIO pin function
714*
715*/
716/****************************************************************************/
717static inline void chipcHw_setGpioPinFunction(int pin, /* GPIO Pin number */
718 chipcHw_GPIO_FUNCTION_e func /* Configuration function */
719 );
720
721/****************************************************************************/
722/**
723* @brief Set Pin slew rate
724*
725* This function sets the slew of individual pin
726*
727*/
728/****************************************************************************/
729static inline void chipcHw_setPinSlewRate(uint32_t pin, /* Pin of type chipcHw_PIN_XXXXX */
730 chipcHw_PIN_SLEW_RATE_e slewRate /* Pin slew rate */
731 );
732
733/****************************************************************************/
734/**
735* @brief Set Pin output drive current
736*
737* This function sets output drive current of individual pin
738*
739* Note: Avoid the use of the word 'current' since linux headers define this
740* to be the current task.
741*/
742/****************************************************************************/
743static inline void chipcHw_setPinOutputCurrent(uint32_t pin, /* Pin of type chipcHw_PIN_XXXXX */
744 chipcHw_PIN_CURRENT_STRENGTH_e curr /* Pin current rating */
745 );
746
747/****************************************************************************/
748/**
749* @brief Set Pin pullup register
750*
751* This function sets pullup register of individual pin
752*
753*/
754/****************************************************************************/
755static inline void chipcHw_setPinPullup(uint32_t pin, /* Pin of type chipcHw_PIN_XXXXX */
756 chipcHw_PIN_PULL_e pullup /* Pullup register settings */
757 );
758
759/****************************************************************************/
760/**
761* @brief Set Pin input type
762*
763* This function sets input type of individual Pin
764*
765*/
766/****************************************************************************/
767static inline void chipcHw_setPinInputType(uint32_t pin, /* Pin of type chipcHw_PIN_XXXXX */
768 chipcHw_PIN_INPUTTYPE_e inputType /* Pin input type */
769 );
770
771/****************************************************************************/
772/**
773* @brief Retrieves a string representation of the mux setting for a pin.
774*
775* @return Pointer to a character string.
776*/
777/****************************************************************************/
778
779const char *chipcHw_getGpioPinFunctionStr(int pin);
780
781/****************************************************************************/
782/** @brief issue warmReset
783 */
784/****************************************************************************/
785void chipcHw_reset(uint32_t mask);
786
787/****************************************************************************/
788/** @brief clock reconfigure
789 */
790/****************************************************************************/
791void chipcHw_clockReconfig(uint32_t busHz, uint32_t armRatio, uint32_t vpmRatio,
792 uint32_t ddrRatio);
793
794/****************************************************************************/
795/**
796* @brief Enable Spread Spectrum
797*
798* @note chipcHw_Init() must be called earlier
799*/
800/****************************************************************************/
801static inline void chipcHw_enableSpreadSpectrum(void);
802
803/****************************************************************************/
804/**
805* @brief Disable Spread Spectrum
806*
807*/
808/****************************************************************************/
809static inline void chipcHw_disableSpreadSpectrum(void);
810
811/****************************************************************************/
812/** @brief Checks if software strap is enabled
813 *
814 * @return 1 : When enable
815 * 0 : When disable
816 */
817/****************************************************************************/
818static inline int chipcHw_isSoftwareStrapsEnable(void);
819
820/****************************************************************************/
821/** @brief Enable software strap
822 */
823/****************************************************************************/
824static inline void chipcHw_softwareStrapsEnable(void);
825
826/****************************************************************************/
827/** @brief Disable software strap
828 */
829/****************************************************************************/
830static inline void chipcHw_softwareStrapsDisable(void);
831
832/****************************************************************************/
833/** @brief PLL test enable
834 */
835/****************************************************************************/
836static inline void chipcHw_pllTestEnable(void);
837
838/****************************************************************************/
839/** @brief PLL2 test enable
840 */
841/****************************************************************************/
842static inline void chipcHw_pll2TestEnable(void);
843
844/****************************************************************************/
845/** @brief PLL test disable
846 */
847/****************************************************************************/
848static inline void chipcHw_pllTestDisable(void);
849
850/****************************************************************************/
851/** @brief PLL2 test disable
852 */
853/****************************************************************************/
854static inline void chipcHw_pll2TestDisable(void);
855
856/****************************************************************************/
857/** @brief Get PLL test status
858 */
859/****************************************************************************/
860static inline int chipcHw_isPllTestEnable(void);
861
862/****************************************************************************/
863/** @brief Get PLL2 test status
864 */
865/****************************************************************************/
866static inline int chipcHw_isPll2TestEnable(void);
867
868/****************************************************************************/
869/** @brief PLL test select
870 */
871/****************************************************************************/
872static inline void chipcHw_pllTestSelect(uint32_t val);
873
874/****************************************************************************/
875/** @brief PLL2 test select
876 */
877/****************************************************************************/
878static inline void chipcHw_pll2TestSelect(uint32_t val);
879
880/****************************************************************************/
881/** @brief Get PLL test selected option
882 */
883/****************************************************************************/
884static inline uint8_t chipcHw_getPllTestSelected(void);
885
886/****************************************************************************/
887/** @brief Get PLL2 test selected option
888 */
889/****************************************************************************/
890static inline uint8_t chipcHw_getPll2TestSelected(void);
891
892/****************************************************************************/
893/**
894* @brief Enables DDR SW phase alignment interrupt
895*/
896/****************************************************************************/
897static inline void chipcHw_ddrPhaseAlignInterruptEnable(void);
898
899/****************************************************************************/
900/**
901* @brief Disables DDR SW phase alignment interrupt
902*/
903/****************************************************************************/
904static inline void chipcHw_ddrPhaseAlignInterruptDisable(void);
905
906/****************************************************************************/
907/**
908* @brief Set VPM SW phase alignment interrupt mode
909*
910* This function sets VPM phase alignment interrupt
911*
912*/
913/****************************************************************************/
914static inline void
915chipcHw_vpmPhaseAlignInterruptMode(chipcHw_VPM_HW_PHASE_INTR_e mode);
916
917/****************************************************************************/
918/**
919* @brief Enable DDR phase alignment in software
920*
921*/
922/****************************************************************************/
923static inline void chipcHw_ddrSwPhaseAlignEnable(void);
924
925/****************************************************************************/
926/**
927* @brief Disable DDR phase alignment in software
928*
929*/
930/****************************************************************************/
931static inline void chipcHw_ddrSwPhaseAlignDisable(void);
932
933/****************************************************************************/
934/**
935* @brief Enable DDR phase alignment in hardware
936*
937*/
938/****************************************************************************/
939static inline void chipcHw_ddrHwPhaseAlignEnable(void);
940
941/****************************************************************************/
942/**
943* @brief Disable DDR phase alignment in hardware
944*
945*/
946/****************************************************************************/
947static inline void chipcHw_ddrHwPhaseAlignDisable(void);
948
949/****************************************************************************/
950/**
951* @brief Enable VPM phase alignment in software
952*
953*/
954/****************************************************************************/
955static inline void chipcHw_vpmSwPhaseAlignEnable(void);
956
957/****************************************************************************/
958/**
959* @brief Disable VPM phase alignment in software
960*
961*/
962/****************************************************************************/
963static inline void chipcHw_vpmSwPhaseAlignDisable(void);
964
965/****************************************************************************/
966/**
967* @brief Enable VPM phase alignment in hardware
968*
969*/
970/****************************************************************************/
971static inline void chipcHw_vpmHwPhaseAlignEnable(void);
972
973/****************************************************************************/
974/**
975* @brief Disable VPM phase alignment in hardware
976*
977*/
978/****************************************************************************/
979static inline void chipcHw_vpmHwPhaseAlignDisable(void);
980
981/****************************************************************************/
982/**
983* @brief Set DDR phase alignment margin in hardware
984*
985*/
986/****************************************************************************/
987static inline void chipcHw_setDdrHwPhaseAlignMargin(chipcHw_DDR_HW_PHASE_MARGIN_e margin /* Margin alinging DDR phase */
988 );
989
990/****************************************************************************/
991/**
992* @brief Set VPM phase alignment margin in hardware
993*
994*/
995/****************************************************************************/
996static inline void chipcHw_setVpmHwPhaseAlignMargin(chipcHw_VPM_HW_PHASE_MARGIN_e margin /* Margin alinging VPM phase */
997 );
998
999/****************************************************************************/
1000/**
1001* @brief Checks DDR phase aligned status done by HW
1002*
1003* @return 1: When aligned
1004* 0: When not aligned
1005*/
1006/****************************************************************************/
1007static inline uint32_t chipcHw_isDdrHwPhaseAligned(void);
1008
1009/****************************************************************************/
1010/**
1011* @brief Checks VPM phase aligned status done by HW
1012*
1013* @return 1: When aligned
1014* 0: When not aligned
1015*/
1016/****************************************************************************/
1017static inline uint32_t chipcHw_isVpmHwPhaseAligned(void);
1018
1019/****************************************************************************/
1020/**
1021* @brief Get DDR phase aligned status done by HW
1022*
1023*/
1024/****************************************************************************/
1025static inline uint32_t chipcHw_getDdrHwPhaseAlignStatus(void);
1026
1027/****************************************************************************/
1028/**
1029* @brief Get VPM phase aligned status done by HW
1030*
1031*/
1032/****************************************************************************/
1033static inline uint32_t chipcHw_getVpmHwPhaseAlignStatus(void);
1034
1035/****************************************************************************/
1036/**
1037* @brief Get DDR phase control value
1038*
1039*/
1040/****************************************************************************/
1041static inline uint32_t chipcHw_getDdrPhaseControl(void);
1042
1043/****************************************************************************/
1044/**
1045* @brief Get VPM phase control value
1046*
1047*/
1048/****************************************************************************/
1049static inline uint32_t chipcHw_getVpmPhaseControl(void);
1050
1051/****************************************************************************/
1052/**
1053* @brief DDR phase alignment timeout count
1054*
1055* @note If HW fails to perform the phase alignment, it will trigger
1056* a DDR phase alignment timeout interrupt.
1057*/
1058/****************************************************************************/
1059static inline void chipcHw_ddrHwPhaseAlignTimeout(uint32_t busCycle /* Timeout in bus cycle */
1060 );
1061
1062/****************************************************************************/
1063/**
1064* @brief VPM phase alignment timeout count
1065*
1066* @note If HW fails to perform the phase alignment, it will trigger
1067* a VPM phase alignment timeout interrupt.
1068*/
1069/****************************************************************************/
1070static inline void chipcHw_vpmHwPhaseAlignTimeout(uint32_t busCycle /* Timeout in bus cycle */
1071 );
1072
1073/****************************************************************************/
1074/**
1075* @brief DDR phase alignment timeout interrupt enable
1076*
1077*/
1078/****************************************************************************/
1079static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptEnable(void);
1080
1081/****************************************************************************/
1082/**
1083* @brief VPM phase alignment timeout interrupt enable
1084*
1085*/
1086/****************************************************************************/
1087static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptEnable(void);
1088
1089/****************************************************************************/
1090/**
1091* @brief DDR phase alignment timeout interrupt disable
1092*
1093*/
1094/****************************************************************************/
1095static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptDisable(void);
1096
1097/****************************************************************************/
1098/**
1099* @brief VPM phase alignment timeout interrupt disable
1100*
1101*/
1102/****************************************************************************/
1103static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptDisable(void);
1104
1105/****************************************************************************/
1106/**
1107* @brief Clear DDR phase alignment timeout interrupt
1108*
1109*/
1110/****************************************************************************/
1111static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptClear(void);
1112
1113/****************************************************************************/
1114/**
1115* @brief Clear VPM phase alignment timeout interrupt
1116*
1117*/
1118/****************************************************************************/
1119static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptClear(void);
1120
1121/* ---- Private Constants and Types -------------------------------------- */
1122
1123#endif /* CHIPC_DEF_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h
new file mode 100644
index 00000000000..03238c29900
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h
@@ -0,0 +1,1673 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15#ifndef CHIPC_INLINE_H
16#define CHIPC_INLINE_H
17
18/* ---- Include Files ----------------------------------------------------- */
19
20#include <csp/errno.h>
21#include <csp/reg.h>
22#include <mach/csp/chipcHw_reg.h>
23#include <mach/csp/chipcHw_def.h>
24
25/* ---- Private Constants and Types --------------------------------------- */
26typedef enum {
27 chipcHw_OPTYPE_BYPASS, /* Bypass operation */
28 chipcHw_OPTYPE_OUTPUT /* Output operation */
29} chipcHw_OPTYPE_e;
30
31/* ---- Public Constants and Types ---------------------------------------- */
32/* ---- Public Variable Externs ------------------------------------------- */
33/* ---- Public Function Prototypes ---------------------------------------- */
34/* ---- Private Function Prototypes --------------------------------------- */
35static inline void chipcHw_setClock(chipcHw_CLOCK_e clock,
36 chipcHw_OPTYPE_e type, int mode);
37
38/****************************************************************************/
39/**
40* @brief Get Numeric Chip ID
41*
42* This function returns Chip ID that includes the revison number
43*
44* @return Complete numeric Chip ID
45*
46*/
47/****************************************************************************/
48static inline uint32_t chipcHw_getChipId(void)
49{
50 return pChipcHw->ChipId;
51}
52
53/****************************************************************************/
54/**
55* @brief Enable Spread Spectrum
56*
57* @note chipcHw_Init() must be called earlier
58*/
59/****************************************************************************/
60static inline void chipcHw_enableSpreadSpectrum(void)
61{
62 if ((pChipcHw->
63 PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) !=
64 chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
65 ddrcReg_PHY_ADDR_CTL_REGP->ssCfg =
66 (0xFFFF << ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_SHIFT) |
67 (ddrcReg_PHY_ADDR_SS_CFG_MIN_CYCLE_PER_TICK <<
68 ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_SHIFT);
69 ddrcReg_PHY_ADDR_CTL_REGP->ssCtl |=
70 ddrcReg_PHY_ADDR_SS_CTRL_ENABLE;
71 }
72}
73
74/****************************************************************************/
75/**
76* @brief Disable Spread Spectrum
77*
78*/
79/****************************************************************************/
80static inline void chipcHw_disableSpreadSpectrum(void)
81{
82 ddrcReg_PHY_ADDR_CTL_REGP->ssCtl &= ~ddrcReg_PHY_ADDR_SS_CTRL_ENABLE;
83}
84
85/****************************************************************************/
86/**
87* @brief Get Chip Product ID
88*
89* This function returns Chip Product ID
90*
91* @return Chip Product ID
92*/
93/****************************************************************************/
94static inline uint32_t chipcHw_getChipProductId(void)
95{
96 return (pChipcHw->
97 ChipId & chipcHw_REG_CHIPID_BASE_MASK) >>
98 chipcHw_REG_CHIPID_BASE_SHIFT;
99}
100
101/****************************************************************************/
102/**
103* @brief Get revision number
104*
105* This function returns revision number of the chip
106*
107* @return Revision number
108*/
109/****************************************************************************/
110static inline chipcHw_REV_NUMBER_e chipcHw_getChipRevisionNumber(void)
111{
112 return pChipcHw->ChipId & chipcHw_REG_CHIPID_REV_MASK;
113}
114
115/****************************************************************************/
116/**
117* @brief Enables bus interface clock
118*
119* Enables bus interface clock of various device
120*
121* @return void
122*
123* @note use chipcHw_REG_BUS_CLOCK_XXXX for mask
124*/
125/****************************************************************************/
126static inline void chipcHw_busInterfaceClockEnable(uint32_t mask)
127{
128 reg32_modify_or(&pChipcHw->BusIntfClock, mask);
129}
130
131/****************************************************************************/
132/**
133* @brief Disables bus interface clock
134*
135* Disables bus interface clock of various device
136*
137* @return void
138*
139* @note use chipcHw_REG_BUS_CLOCK_XXXX
140*/
141/****************************************************************************/
142static inline void chipcHw_busInterfaceClockDisable(uint32_t mask)
143{
144 reg32_modify_and(&pChipcHw->BusIntfClock, ~mask);
145}
146
147/****************************************************************************/
148/**
149* @brief Get status (enabled/disabled) of bus interface clock
150*
151* This function returns the status of devices' bus interface clock
152*
153* @return Bus interface clock
154*
155*/
156/****************************************************************************/
157static inline uint32_t chipcHw_getBusInterfaceClockStatus(void)
158{
159 return pChipcHw->BusIntfClock;
160}
161
162/****************************************************************************/
163/**
164* @brief Enables various audio channels
165*
166* Enables audio channel
167*
168* @return void
169*
170* @note use chipcHw_REG_AUDIO_CHANNEL_XXXXXX
171*/
172/****************************************************************************/
173static inline void chipcHw_audioChannelEnable(uint32_t mask)
174{
175 reg32_modify_or(&pChipcHw->AudioEnable, mask);
176}
177
178/****************************************************************************/
179/**
180* @brief Disables various audio channels
181*
182* Disables audio channel
183*
184* @return void
185*
186* @note use chipcHw_REG_AUDIO_CHANNEL_XXXXXX
187*/
188/****************************************************************************/
189static inline void chipcHw_audioChannelDisable(uint32_t mask)
190{
191 reg32_modify_and(&pChipcHw->AudioEnable, ~mask);
192}
193
194/****************************************************************************/
195/**
196* @brief Soft resets devices
197*
198* Soft resets various devices
199*
200* @return void
201*
202* @note use chipcHw_REG_SOFT_RESET_XXXXXX defines
203*/
204/****************************************************************************/
205static inline void chipcHw_softReset(uint64_t mask)
206{
207 chipcHw_softResetEnable(mask);
208 chipcHw_softResetDisable(mask);
209}
210
211static inline void chipcHw_softResetDisable(uint64_t mask)
212{
213 uint32_t ctrl1 = (uint32_t) mask;
214 uint32_t ctrl2 = (uint32_t) (mask >> 32);
215
216 /* Deassert module soft reset */
217 REG_LOCAL_IRQ_SAVE;
218 pChipcHw->SoftReset1 ^= ctrl1;
219 pChipcHw->SoftReset2 ^= (ctrl2 & (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK));
220 REG_LOCAL_IRQ_RESTORE;
221}
222
223static inline void chipcHw_softResetEnable(uint64_t mask)
224{
225 uint32_t ctrl1 = (uint32_t) mask;
226 uint32_t ctrl2 = (uint32_t) (mask >> 32);
227 uint32_t unhold = 0;
228
229 REG_LOCAL_IRQ_SAVE;
230 pChipcHw->SoftReset1 |= ctrl1;
231 /* Mask out unhold request bits */
232 pChipcHw->SoftReset2 |= (ctrl2 & (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK));
233
234 /* Process unhold requests */
235 if (ctrl2 & chipcHw_REG_SOFT_RESET_VPM_GLOBAL_UNHOLD) {
236 unhold = chipcHw_REG_SOFT_RESET_VPM_GLOBAL_HOLD;
237 }
238
239 if (ctrl2 & chipcHw_REG_SOFT_RESET_VPM_UNHOLD) {
240 unhold |= chipcHw_REG_SOFT_RESET_VPM_HOLD;
241 }
242
243 if (ctrl2 & chipcHw_REG_SOFT_RESET_ARM_UNHOLD) {
244 unhold |= chipcHw_REG_SOFT_RESET_ARM_HOLD;
245 }
246
247 if (unhold) {
248 /* Make sure unhold request is effective */
249 pChipcHw->SoftReset1 &= ~unhold;
250 }
251 REG_LOCAL_IRQ_RESTORE;
252}
253
254/****************************************************************************/
255/**
256* @brief Configures misc CHIP functionality
257*
258* Configures CHIP functionality
259*
260* @return void
261*
262* @note use chipcHw_REG_MISC_CTRL_XXXXXX
263*/
264/****************************************************************************/
265static inline void chipcHw_miscControl(uint32_t mask)
266{
267 reg32_write(&pChipcHw->MiscCtrl, mask);
268}
269
270static inline void chipcHw_miscControlDisable(uint32_t mask)
271{
272 reg32_modify_and(&pChipcHw->MiscCtrl, ~mask);
273}
274
275static inline void chipcHw_miscControlEnable(uint32_t mask)
276{
277 reg32_modify_or(&pChipcHw->MiscCtrl, mask);
278}
279
280/****************************************************************************/
281/**
282* @brief Set OTP options
283*
284* Set OTP options
285*
286* @return void
287*
288* @note use chipcHw_REG_OTP_XXXXXX
289*/
290/****************************************************************************/
291static inline void chipcHw_setOTPOption(uint64_t mask)
292{
293 uint32_t ctrl1 = (uint32_t) mask;
294 uint32_t ctrl2 = (uint32_t) (mask >> 32);
295
296 reg32_modify_or(&pChipcHw->SoftOTP1, ctrl1);
297 reg32_modify_or(&pChipcHw->SoftOTP2, ctrl2);
298}
299
300/****************************************************************************/
301/**
302* @brief Get sticky bits
303*
304* @return Sticky bit options of type chipcHw_REG_STICKY_XXXXXX
305*
306*/
307/****************************************************************************/
308static inline uint32_t chipcHw_getStickyBits(void)
309{
310 return pChipcHw->Sticky;
311}
312
313/****************************************************************************/
314/**
315* @brief Set sticky bits
316*
317* @return void
318*
319* @note use chipcHw_REG_STICKY_XXXXXX
320*/
321/****************************************************************************/
322static inline void chipcHw_setStickyBits(uint32_t mask)
323{
324 uint32_t bits = 0;
325
326 REG_LOCAL_IRQ_SAVE;
327 if (mask & chipcHw_REG_STICKY_POR_BROM) {
328 bits |= chipcHw_REG_STICKY_POR_BROM;
329 } else {
330 uint32_t sticky;
331 sticky = pChipcHw->Sticky;
332
333 if ((mask & chipcHw_REG_STICKY_BOOT_DONE)
334 && (sticky & chipcHw_REG_STICKY_BOOT_DONE) == 0) {
335 bits |= chipcHw_REG_STICKY_BOOT_DONE;
336 }
337 if ((mask & chipcHw_REG_STICKY_GENERAL_1)
338 && (sticky & chipcHw_REG_STICKY_GENERAL_1) == 0) {
339 bits |= chipcHw_REG_STICKY_GENERAL_1;
340 }
341 if ((mask & chipcHw_REG_STICKY_GENERAL_2)
342 && (sticky & chipcHw_REG_STICKY_GENERAL_2) == 0) {
343 bits |= chipcHw_REG_STICKY_GENERAL_2;
344 }
345 if ((mask & chipcHw_REG_STICKY_GENERAL_3)
346 && (sticky & chipcHw_REG_STICKY_GENERAL_3) == 0) {
347 bits |= chipcHw_REG_STICKY_GENERAL_3;
348 }
349 if ((mask & chipcHw_REG_STICKY_GENERAL_4)
350 && (sticky & chipcHw_REG_STICKY_GENERAL_4) == 0) {
351 bits |= chipcHw_REG_STICKY_GENERAL_4;
352 }
353 if ((mask & chipcHw_REG_STICKY_GENERAL_5)
354 && (sticky & chipcHw_REG_STICKY_GENERAL_5) == 0) {
355 bits |= chipcHw_REG_STICKY_GENERAL_5;
356 }
357 }
358 pChipcHw->Sticky = bits;
359 REG_LOCAL_IRQ_RESTORE;
360}
361
362/****************************************************************************/
363/**
364* @brief Clear sticky bits
365*
366* @return void
367*
368* @note use chipcHw_REG_STICKY_XXXXXX
369*/
370/****************************************************************************/
371static inline void chipcHw_clearStickyBits(uint32_t mask)
372{
373 uint32_t bits = 0;
374
375 REG_LOCAL_IRQ_SAVE;
376 if (mask &
377 (chipcHw_REG_STICKY_BOOT_DONE | chipcHw_REG_STICKY_GENERAL_1 |
378 chipcHw_REG_STICKY_GENERAL_2 | chipcHw_REG_STICKY_GENERAL_3 |
379 chipcHw_REG_STICKY_GENERAL_4 | chipcHw_REG_STICKY_GENERAL_5)) {
380 uint32_t sticky = pChipcHw->Sticky;
381
382 if ((mask & chipcHw_REG_STICKY_BOOT_DONE)
383 && (sticky & chipcHw_REG_STICKY_BOOT_DONE)) {
384 bits = chipcHw_REG_STICKY_BOOT_DONE;
385 mask &= ~chipcHw_REG_STICKY_BOOT_DONE;
386 }
387 if ((mask & chipcHw_REG_STICKY_GENERAL_1)
388 && (sticky & chipcHw_REG_STICKY_GENERAL_1)) {
389 bits |= chipcHw_REG_STICKY_GENERAL_1;
390 mask &= ~chipcHw_REG_STICKY_GENERAL_1;
391 }
392 if ((mask & chipcHw_REG_STICKY_GENERAL_2)
393 && (sticky & chipcHw_REG_STICKY_GENERAL_2)) {
394 bits |= chipcHw_REG_STICKY_GENERAL_2;
395 mask &= ~chipcHw_REG_STICKY_GENERAL_2;
396 }
397 if ((mask & chipcHw_REG_STICKY_GENERAL_3)
398 && (sticky & chipcHw_REG_STICKY_GENERAL_3)) {
399 bits |= chipcHw_REG_STICKY_GENERAL_3;
400 mask &= ~chipcHw_REG_STICKY_GENERAL_3;
401 }
402 if ((mask & chipcHw_REG_STICKY_GENERAL_4)
403 && (sticky & chipcHw_REG_STICKY_GENERAL_4)) {
404 bits |= chipcHw_REG_STICKY_GENERAL_4;
405 mask &= ~chipcHw_REG_STICKY_GENERAL_4;
406 }
407 if ((mask & chipcHw_REG_STICKY_GENERAL_5)
408 && (sticky & chipcHw_REG_STICKY_GENERAL_5)) {
409 bits |= chipcHw_REG_STICKY_GENERAL_5;
410 mask &= ~chipcHw_REG_STICKY_GENERAL_5;
411 }
412 }
413 pChipcHw->Sticky = bits | mask;
414 REG_LOCAL_IRQ_RESTORE;
415}
416
417/****************************************************************************/
418/**
419* @brief Get software strap value
420*
421* Retrieves software strap value
422*
423* @return Software strap value
424*
425*/
426/****************************************************************************/
427static inline uint32_t chipcHw_getSoftStraps(void)
428{
429 return pChipcHw->SoftStraps;
430}
431
432/****************************************************************************/
433/**
434* @brief Set software override strap options
435*
436* set software override strap options
437*
438* @return nothing
439*
440*/
441/****************************************************************************/
442static inline void chipcHw_setSoftStraps(uint32_t strapOptions)
443{
444 reg32_write(&pChipcHw->SoftStraps, strapOptions);
445}
446
447/****************************************************************************/
448/**
449* @brief Get Pin Strap Options
450*
451* This function returns the raw boot strap options
452*
453* @return strap options
454*
455*/
456/****************************************************************************/
457static inline uint32_t chipcHw_getPinStraps(void)
458{
459 return pChipcHw->PinStraps;
460}
461
462/****************************************************************************/
463/**
464* @brief Get Valid Strap Options
465*
466* This function returns the valid raw boot strap options
467*
468* @return strap options
469*
470*/
471/****************************************************************************/
472static inline uint32_t chipcHw_getValidStraps(void)
473{
474 uint32_t softStraps;
475
476 /*
477 ** Always return the SoftStraps - bootROM calls chipcHw_initValidStraps
478 ** which copies HW straps to soft straps if there is no override
479 */
480 softStraps = chipcHw_getSoftStraps();
481
482 return softStraps;
483}
484
485/****************************************************************************/
486/**
487* @brief Initialize valid pin strap options
488*
489* Retrieves valid pin strap options by copying HW strap options to soft register
490* (if chipcHw_STRAPS_SOFT_OVERRIDE not set)
491*
492* @return nothing
493*
494*/
495/****************************************************************************/
496static inline void chipcHw_initValidStraps(void)
497{
498 uint32_t softStraps;
499
500 REG_LOCAL_IRQ_SAVE;
501 softStraps = chipcHw_getSoftStraps();
502
503 if ((softStraps & chipcHw_STRAPS_SOFT_OVERRIDE) == 0) {
504 /* Copy HW straps to software straps */
505 chipcHw_setSoftStraps(chipcHw_getPinStraps());
506 }
507 REG_LOCAL_IRQ_RESTORE;
508}
509
510/****************************************************************************/
511/**
512* @brief Get boot device
513*
514* This function returns the device type used in booting the system
515*
516* @return Boot device of type chipcHw_BOOT_DEVICE
517*
518*/
519/****************************************************************************/
520static inline chipcHw_BOOT_DEVICE_e chipcHw_getBootDevice(void)
521{
522 return chipcHw_getValidStraps() & chipcHw_STRAPS_BOOT_DEVICE_MASK;
523}
524
525/****************************************************************************/
526/**
527* @brief Get boot mode
528*
529* This function returns the way the system was booted
530*
531* @return Boot mode of type chipcHw_BOOT_MODE
532*
533*/
534/****************************************************************************/
535static inline chipcHw_BOOT_MODE_e chipcHw_getBootMode(void)
536{
537 return chipcHw_getValidStraps() & chipcHw_STRAPS_BOOT_MODE_MASK;
538}
539
540/****************************************************************************/
541/**
542* @brief Get NAND flash page size
543*
544* This function returns the NAND device page size
545*
546* @return Boot NAND device page size
547*
548*/
549/****************************************************************************/
550static inline chipcHw_NAND_PAGESIZE_e chipcHw_getNandPageSize(void)
551{
552 return chipcHw_getValidStraps() & chipcHw_STRAPS_NAND_PAGESIZE_MASK;
553}
554
555/****************************************************************************/
556/**
557* @brief Get NAND flash address cycle configuration
558*
559* This function returns the NAND flash address cycle configuration
560*
561* @return 0 = Do not extra address cycle, 1 = Add extra cycle
562*
563*/
564/****************************************************************************/
565static inline int chipcHw_getNandExtraCycle(void)
566{
567 if (chipcHw_getValidStraps() & chipcHw_STRAPS_NAND_EXTRA_CYCLE) {
568 return 1;
569 } else {
570 return 0;
571 }
572}
573
574/****************************************************************************/
575/**
576* @brief Activates PIF interface
577*
578* This function activates PIF interface by taking control of LCD pins
579*
580* @note
581* When activated, LCD pins will be defined as follows for PIF operation
582*
583* CLD[17:0] = pif_data[17:0]
584* CLD[23:18] = pif_address[5:0]
585* CLPOWER = pif_wr_str
586* CLCP = pif_rd_str
587* CLAC = pif_hat1
588* CLFP = pif_hrdy1
589* CLLP = pif_hat2
590* GPIO[42] = pif_hrdy2
591*
592* In PIF mode, "pif_hrdy2" overrides other shared function for GPIO[42] pin
593*
594*/
595/****************************************************************************/
596static inline void chipcHw_activatePifInterface(void)
597{
598 reg32_write(&pChipcHw->LcdPifMode, chipcHw_REG_PIF_PIN_ENABLE);
599}
600
601/****************************************************************************/
602/**
603* @brief Activates LCD interface
604*
605* This function activates LCD interface
606*
607* @note
608* When activated, LCD pins will be defined as follows
609*
610* CLD[17:0] = LCD data
611* CLD[23:18] = LCD data
612* CLPOWER = LCD power
613* CLCP =
614* CLAC = LCD ack
615* CLFP =
616* CLLP =
617*/
618/****************************************************************************/
619static inline void chipcHw_activateLcdInterface(void)
620{
621 reg32_write(&pChipcHw->LcdPifMode, chipcHw_REG_LCD_PIN_ENABLE);
622}
623
624/****************************************************************************/
625/**
626* @brief Deactivates PIF/LCD interface
627*
628* This function deactivates PIF/LCD interface
629*
630* @note
631* When deactivated LCD pins will be in rti-stated
632*
633*/
634/****************************************************************************/
635static inline void chipcHw_deactivatePifLcdInterface(void)
636{
637 reg32_write(&pChipcHw->LcdPifMode, 0);
638}
639
640/****************************************************************************/
641/**
642* @brief Select GE2
643*
644* This function select GE2 as the graphic engine
645*
646*/
647/****************************************************************************/
648static inline void chipcHw_selectGE2(void)
649{
650 reg32_modify_and(&pChipcHw->MiscCtrl, ~chipcHw_REG_MISC_CTRL_GE_SEL);
651}
652
653/****************************************************************************/
654/**
655* @brief Select GE3
656*
657* This function select GE3 as the graphic engine
658*
659*/
660/****************************************************************************/
661static inline void chipcHw_selectGE3(void)
662{
663 reg32_modify_or(&pChipcHw->MiscCtrl, chipcHw_REG_MISC_CTRL_GE_SEL);
664}
665
666/****************************************************************************/
667/**
668* @brief Get to know the configuration of GPIO pin
669*
670*/
671/****************************************************************************/
672static inline chipcHw_GPIO_FUNCTION_e chipcHw_getGpioPinFunction(int pin)
673{
674 return (*((uint32_t *) chipcHw_REG_GPIO_MUX(pin)) &
675 (chipcHw_REG_GPIO_MUX_MASK <<
676 chipcHw_REG_GPIO_MUX_POSITION(pin))) >>
677 chipcHw_REG_GPIO_MUX_POSITION(pin);
678}
679
680/****************************************************************************/
681/**
682* @brief Configure GPIO pin function
683*
684*/
685/****************************************************************************/
686static inline void chipcHw_setGpioPinFunction(int pin,
687 chipcHw_GPIO_FUNCTION_e func)
688{
689 REG_LOCAL_IRQ_SAVE;
690 *((uint32_t *) chipcHw_REG_GPIO_MUX(pin)) &=
691 ~(chipcHw_REG_GPIO_MUX_MASK << chipcHw_REG_GPIO_MUX_POSITION(pin));
692 *((uint32_t *) chipcHw_REG_GPIO_MUX(pin)) |=
693 func << chipcHw_REG_GPIO_MUX_POSITION(pin);
694 REG_LOCAL_IRQ_RESTORE;
695}
696
697/****************************************************************************/
698/**
699* @brief Set Pin slew rate
700*
701* This function sets the slew of individual pin
702*
703*/
704/****************************************************************************/
705static inline void chipcHw_setPinSlewRate(uint32_t pin,
706 chipcHw_PIN_SLEW_RATE_e slewRate)
707{
708 REG_LOCAL_IRQ_SAVE;
709 *((uint32_t *) chipcHw_REG_SLEW_RATE(pin)) &=
710 ~(chipcHw_REG_SLEW_RATE_MASK <<
711 chipcHw_REG_SLEW_RATE_POSITION(pin));
712 *((uint32_t *) chipcHw_REG_SLEW_RATE(pin)) |=
713 (uint32_t) slewRate << chipcHw_REG_SLEW_RATE_POSITION(pin);
714 REG_LOCAL_IRQ_RESTORE;
715}
716
717/****************************************************************************/
718/**
719* @brief Set Pin output drive current
720*
721* This function sets output drive current of individual pin
722*
723* Note: Avoid the use of the word 'current' since linux headers define this
724* to be the current task.
725*/
726/****************************************************************************/
727static inline void chipcHw_setPinOutputCurrent(uint32_t pin,
728 chipcHw_PIN_CURRENT_STRENGTH_e
729 curr)
730{
731 REG_LOCAL_IRQ_SAVE;
732 *((uint32_t *) chipcHw_REG_CURRENT(pin)) &=
733 ~(chipcHw_REG_CURRENT_MASK << chipcHw_REG_CURRENT_POSITION(pin));
734 *((uint32_t *) chipcHw_REG_CURRENT(pin)) |=
735 (uint32_t) curr << chipcHw_REG_CURRENT_POSITION(pin);
736 REG_LOCAL_IRQ_RESTORE;
737}
738
739/****************************************************************************/
740/**
741* @brief Set Pin pullup register
742*
743* This function sets pullup register of individual pin
744*
745*/
746/****************************************************************************/
747static inline void chipcHw_setPinPullup(uint32_t pin, chipcHw_PIN_PULL_e pullup)
748{
749 REG_LOCAL_IRQ_SAVE;
750 *((uint32_t *) chipcHw_REG_PULLUP(pin)) &=
751 ~(chipcHw_REG_PULLUP_MASK << chipcHw_REG_PULLUP_POSITION(pin));
752 *((uint32_t *) chipcHw_REG_PULLUP(pin)) |=
753 (uint32_t) pullup << chipcHw_REG_PULLUP_POSITION(pin);
754 REG_LOCAL_IRQ_RESTORE;
755}
756
757/****************************************************************************/
758/**
759* @brief Set Pin input type
760*
761* This function sets input type of individual pin
762*
763*/
764/****************************************************************************/
765static inline void chipcHw_setPinInputType(uint32_t pin,
766 chipcHw_PIN_INPUTTYPE_e inputType)
767{
768 REG_LOCAL_IRQ_SAVE;
769 *((uint32_t *) chipcHw_REG_INPUTTYPE(pin)) &=
770 ~(chipcHw_REG_INPUTTYPE_MASK <<
771 chipcHw_REG_INPUTTYPE_POSITION(pin));
772 *((uint32_t *) chipcHw_REG_INPUTTYPE(pin)) |=
773 (uint32_t) inputType << chipcHw_REG_INPUTTYPE_POSITION(pin);
774 REG_LOCAL_IRQ_RESTORE;
775}
776
777/****************************************************************************/
778/**
779* @brief Power up the USB PHY
780*
781* This function powers up the USB PHY
782*
783*/
784/****************************************************************************/
785static inline void chipcHw_powerUpUsbPhy(void)
786{
787 reg32_modify_and(&pChipcHw->MiscCtrl,
788 chipcHw_REG_MISC_CTRL_USB_POWERON);
789}
790
791/****************************************************************************/
792/**
793* @brief Power down the USB PHY
794*
795* This function powers down the USB PHY
796*
797*/
798/****************************************************************************/
799static inline void chipcHw_powerDownUsbPhy(void)
800{
801 reg32_modify_or(&pChipcHw->MiscCtrl,
802 chipcHw_REG_MISC_CTRL_USB_POWEROFF);
803}
804
805/****************************************************************************/
806/**
807* @brief Set the 2nd USB as host
808*
809* This function sets the 2nd USB as host
810*
811*/
812/****************************************************************************/
813static inline void chipcHw_setUsbHost(void)
814{
815 reg32_modify_or(&pChipcHw->MiscCtrl,
816 chipcHw_REG_MISC_CTRL_USB_MODE_HOST);
817}
818
819/****************************************************************************/
820/**
821* @brief Set the 2nd USB as device
822*
823* This function sets the 2nd USB as device
824*
825*/
826/****************************************************************************/
827static inline void chipcHw_setUsbDevice(void)
828{
829 reg32_modify_and(&pChipcHw->MiscCtrl,
830 chipcHw_REG_MISC_CTRL_USB_MODE_DEVICE);
831}
832
833/****************************************************************************/
834/**
835* @brief Lower layer function to enable/disable a clock of a certain device
836*
837* This function enables/disables a core clock
838*
839*/
840/****************************************************************************/
841static inline void chipcHw_setClock(chipcHw_CLOCK_e clock,
842 chipcHw_OPTYPE_e type, int mode)
843{
844 volatile uint32_t *pPLLReg = (uint32_t *) 0x0;
845 volatile uint32_t *pClockCtrl = (uint32_t *) 0x0;
846
847 switch (clock) {
848 case chipcHw_CLOCK_DDR:
849 pPLLReg = &pChipcHw->DDRClock;
850 break;
851 case chipcHw_CLOCK_ARM:
852 pPLLReg = &pChipcHw->ARMClock;
853 break;
854 case chipcHw_CLOCK_ESW:
855 pPLLReg = &pChipcHw->ESWClock;
856 break;
857 case chipcHw_CLOCK_VPM:
858 pPLLReg = &pChipcHw->VPMClock;
859 break;
860 case chipcHw_CLOCK_ESW125:
861 pPLLReg = &pChipcHw->ESW125Clock;
862 break;
863 case chipcHw_CLOCK_UART:
864 pPLLReg = &pChipcHw->UARTClock;
865 break;
866 case chipcHw_CLOCK_SDIO0:
867 pPLLReg = &pChipcHw->SDIO0Clock;
868 break;
869 case chipcHw_CLOCK_SDIO1:
870 pPLLReg = &pChipcHw->SDIO1Clock;
871 break;
872 case chipcHw_CLOCK_SPI:
873 pPLLReg = &pChipcHw->SPIClock;
874 break;
875 case chipcHw_CLOCK_ETM:
876 pPLLReg = &pChipcHw->ETMClock;
877 break;
878 case chipcHw_CLOCK_USB:
879 pPLLReg = &pChipcHw->USBClock;
880 if (type == chipcHw_OPTYPE_OUTPUT) {
881 if (mode) {
882 reg32_modify_and(pPLLReg,
883 ~chipcHw_REG_PLL_CLOCK_POWER_DOWN);
884 } else {
885 reg32_modify_or(pPLLReg,
886 chipcHw_REG_PLL_CLOCK_POWER_DOWN);
887 }
888 }
889 break;
890 case chipcHw_CLOCK_LCD:
891 pPLLReg = &pChipcHw->LCDClock;
892 if (type == chipcHw_OPTYPE_OUTPUT) {
893 if (mode) {
894 reg32_modify_and(pPLLReg,
895 ~chipcHw_REG_PLL_CLOCK_POWER_DOWN);
896 } else {
897 reg32_modify_or(pPLLReg,
898 chipcHw_REG_PLL_CLOCK_POWER_DOWN);
899 }
900 }
901 break;
902 case chipcHw_CLOCK_APM:
903 pPLLReg = &pChipcHw->APMClock;
904 if (type == chipcHw_OPTYPE_OUTPUT) {
905 if (mode) {
906 reg32_modify_and(pPLLReg,
907 ~chipcHw_REG_PLL_CLOCK_POWER_DOWN);
908 } else {
909 reg32_modify_or(pPLLReg,
910 chipcHw_REG_PLL_CLOCK_POWER_DOWN);
911 }
912 }
913 break;
914 case chipcHw_CLOCK_BUS:
915 pClockCtrl = &pChipcHw->ACLKClock;
916 break;
917 case chipcHw_CLOCK_OTP:
918 pClockCtrl = &pChipcHw->OTPClock;
919 break;
920 case chipcHw_CLOCK_I2C:
921 pClockCtrl = &pChipcHw->I2CClock;
922 break;
923 case chipcHw_CLOCK_I2S0:
924 pClockCtrl = &pChipcHw->I2S0Clock;
925 break;
926 case chipcHw_CLOCK_RTBUS:
927 pClockCtrl = &pChipcHw->RTBUSClock;
928 break;
929 case chipcHw_CLOCK_APM100:
930 pClockCtrl = &pChipcHw->APM100Clock;
931 break;
932 case chipcHw_CLOCK_TSC:
933 pClockCtrl = &pChipcHw->TSCClock;
934 break;
935 case chipcHw_CLOCK_LED:
936 pClockCtrl = &pChipcHw->LEDClock;
937 break;
938 case chipcHw_CLOCK_I2S1:
939 pClockCtrl = &pChipcHw->I2S1Clock;
940 break;
941 }
942
943 if (pPLLReg) {
944 switch (type) {
945 case chipcHw_OPTYPE_OUTPUT:
946 /* PLL clock output enable/disable */
947 if (mode) {
948 if (clock == chipcHw_CLOCK_DDR) {
949 /* DDR clock enable is inverted */
950 reg32_modify_and(pPLLReg,
951 ~chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE);
952 } else {
953 reg32_modify_or(pPLLReg,
954 chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE);
955 }
956 } else {
957 if (clock == chipcHw_CLOCK_DDR) {
958 /* DDR clock disable is inverted */
959 reg32_modify_or(pPLLReg,
960 chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE);
961 } else {
962 reg32_modify_and(pPLLReg,
963 ~chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE);
964 }
965 }
966 break;
967 case chipcHw_OPTYPE_BYPASS:
968 /* PLL clock bypass enable/disable */
969 if (mode) {
970 reg32_modify_or(pPLLReg,
971 chipcHw_REG_PLL_CLOCK_BYPASS_SELECT);
972 } else {
973 reg32_modify_and(pPLLReg,
974 ~chipcHw_REG_PLL_CLOCK_BYPASS_SELECT);
975 }
976 break;
977 }
978 } else if (pClockCtrl) {
979 switch (type) {
980 case chipcHw_OPTYPE_OUTPUT:
981 if (mode) {
982 reg32_modify_or(pClockCtrl,
983 chipcHw_REG_DIV_CLOCK_OUTPUT_ENABLE);
984 } else {
985 reg32_modify_and(pClockCtrl,
986 ~chipcHw_REG_DIV_CLOCK_OUTPUT_ENABLE);
987 }
988 break;
989 case chipcHw_OPTYPE_BYPASS:
990 if (mode) {
991 reg32_modify_or(pClockCtrl,
992 chipcHw_REG_DIV_CLOCK_BYPASS_SELECT);
993 } else {
994 reg32_modify_and(pClockCtrl,
995 ~chipcHw_REG_DIV_CLOCK_BYPASS_SELECT);
996 }
997 break;
998 }
999 }
1000}
1001
1002/****************************************************************************/
1003/**
1004* @brief Disables a core clock of a certain device
1005*
1006* This function disables a core clock
1007*
1008* @note no change in power consumption
1009*/
1010/****************************************************************************/
1011static inline void chipcHw_setClockDisable(chipcHw_CLOCK_e clock)
1012{
1013
1014 /* Disable output of the clock */
1015 chipcHw_setClock(clock, chipcHw_OPTYPE_OUTPUT, 0);
1016}
1017
1018/****************************************************************************/
1019/**
1020* @brief Enable a core clock of a certain device
1021*
1022* This function enables a core clock
1023*
1024* @note no change in power consumption
1025*/
1026/****************************************************************************/
1027static inline void chipcHw_setClockEnable(chipcHw_CLOCK_e clock)
1028{
1029
1030 /* Enable output of the clock */
1031 chipcHw_setClock(clock, chipcHw_OPTYPE_OUTPUT, 1);
1032}
1033
1034/****************************************************************************/
1035/**
1036* @brief Enables bypass clock of a certain device
1037*
1038* This function enables bypass clock
1039*
1040* @note Doesnot affect the bus interface clock
1041*/
1042/****************************************************************************/
1043static inline void chipcHw_bypassClockEnable(chipcHw_CLOCK_e clock)
1044{
1045 /* Enable bypass clock */
1046 chipcHw_setClock(clock, chipcHw_OPTYPE_BYPASS, 1);
1047}
1048
1049/****************************************************************************/
1050/**
1051* @brief Disabled bypass clock of a certain device
1052*
1053* This function disables bypass clock
1054*
1055* @note Doesnot affect the bus interface clock
1056*/
1057/****************************************************************************/
1058static inline void chipcHw_bypassClockDisable(chipcHw_CLOCK_e clock)
1059{
1060 /* Disable bypass clock */
1061 chipcHw_setClock(clock, chipcHw_OPTYPE_BYPASS, 0);
1062
1063}
1064
1065/****************************************************************************/
1066/** @brief Checks if software strap is enabled
1067 *
1068 * @return 1 : When enable
1069 * 0 : When disable
1070 */
1071/****************************************************************************/
1072static inline int chipcHw_isSoftwareStrapsEnable(void)
1073{
1074 return pChipcHw->SoftStraps & 0x00000001;
1075}
1076
1077/****************************************************************************/
1078/** @brief Enable software strap
1079 */
1080/****************************************************************************/
1081static inline void chipcHw_softwareStrapsEnable(void)
1082{
1083 reg32_modify_or(&pChipcHw->SoftStraps, 0x00000001);
1084}
1085
1086/****************************************************************************/
1087/** @brief Disable software strap
1088 */
1089/****************************************************************************/
1090static inline void chipcHw_softwareStrapsDisable(void)
1091{
1092 reg32_modify_and(&pChipcHw->SoftStraps, (~0x00000001));
1093}
1094
1095/****************************************************************************/
1096/** @brief PLL test enable
1097 */
1098/****************************************************************************/
1099static inline void chipcHw_pllTestEnable(void)
1100{
1101 reg32_modify_or(&pChipcHw->PLLConfig,
1102 chipcHw_REG_PLL_CONFIG_TEST_ENABLE);
1103}
1104
1105/****************************************************************************/
1106/** @brief PLL2 test enable
1107 */
1108/****************************************************************************/
1109static inline void chipcHw_pll2TestEnable(void)
1110{
1111 reg32_modify_or(&pChipcHw->PLLConfig2,
1112 chipcHw_REG_PLL_CONFIG_TEST_ENABLE);
1113}
1114
1115/****************************************************************************/
1116/** @brief PLL test disable
1117 */
1118/****************************************************************************/
1119static inline void chipcHw_pllTestDisable(void)
1120{
1121 reg32_modify_and(&pChipcHw->PLLConfig,
1122 ~chipcHw_REG_PLL_CONFIG_TEST_ENABLE);
1123}
1124
1125/****************************************************************************/
1126/** @brief PLL2 test disable
1127 */
1128/****************************************************************************/
1129static inline void chipcHw_pll2TestDisable(void)
1130{
1131 reg32_modify_and(&pChipcHw->PLLConfig2,
1132 ~chipcHw_REG_PLL_CONFIG_TEST_ENABLE);
1133}
1134
1135/****************************************************************************/
1136/** @brief Get PLL test status
1137 */
1138/****************************************************************************/
1139static inline int chipcHw_isPllTestEnable(void)
1140{
1141 return pChipcHw->PLLConfig & chipcHw_REG_PLL_CONFIG_TEST_ENABLE;
1142}
1143
1144/****************************************************************************/
1145/** @brief Get PLL2 test status
1146 */
1147/****************************************************************************/
1148static inline int chipcHw_isPll2TestEnable(void)
1149{
1150 return pChipcHw->PLLConfig2 & chipcHw_REG_PLL_CONFIG_TEST_ENABLE;
1151}
1152
1153/****************************************************************************/
1154/** @brief PLL test select
1155 */
1156/****************************************************************************/
1157static inline void chipcHw_pllTestSelect(uint32_t val)
1158{
1159 REG_LOCAL_IRQ_SAVE;
1160 pChipcHw->PLLConfig &= ~chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK;
1161 pChipcHw->PLLConfig |=
1162 (val) << chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT;
1163 REG_LOCAL_IRQ_RESTORE;
1164}
1165
1166/****************************************************************************/
1167/** @brief PLL2 test select
1168 */
1169/****************************************************************************/
1170static inline void chipcHw_pll2TestSelect(uint32_t val)
1171{
1172
1173 REG_LOCAL_IRQ_SAVE;
1174 pChipcHw->PLLConfig2 &= ~chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK;
1175 pChipcHw->PLLConfig2 |=
1176 (val) << chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT;
1177 REG_LOCAL_IRQ_RESTORE;
1178}
1179
1180/****************************************************************************/
1181/** @brief Get PLL test selected option
1182 */
1183/****************************************************************************/
1184static inline uint8_t chipcHw_getPllTestSelected(void)
1185{
1186 return (uint8_t) ((pChipcHw->
1187 PLLConfig & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK)
1188 >> chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT);
1189}
1190
1191/****************************************************************************/
1192/** @brief Get PLL2 test selected option
1193 */
1194/****************************************************************************/
1195static inline uint8_t chipcHw_getPll2TestSelected(void)
1196{
1197 return (uint8_t) ((pChipcHw->
1198 PLLConfig2 & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK)
1199 >> chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT);
1200}
1201
1202/****************************************************************************/
1203/**
1204* @brief Disable the PLL1
1205*
1206*/
1207/****************************************************************************/
1208static inline void chipcHw_pll1Disable(void)
1209{
1210 REG_LOCAL_IRQ_SAVE;
1211 pChipcHw->PLLConfig |= chipcHw_REG_PLL_CONFIG_POWER_DOWN;
1212 REG_LOCAL_IRQ_RESTORE;
1213}
1214
1215/****************************************************************************/
1216/**
1217* @brief Disable the PLL2
1218*
1219*/
1220/****************************************************************************/
1221static inline void chipcHw_pll2Disable(void)
1222{
1223 REG_LOCAL_IRQ_SAVE;
1224 pChipcHw->PLLConfig2 |= chipcHw_REG_PLL_CONFIG_POWER_DOWN;
1225 REG_LOCAL_IRQ_RESTORE;
1226}
1227
1228/****************************************************************************/
1229/**
1230* @brief Enables DDR SW phase alignment interrupt
1231*/
1232/****************************************************************************/
1233static inline void chipcHw_ddrPhaseAlignInterruptEnable(void)
1234{
1235 REG_LOCAL_IRQ_SAVE;
1236 pChipcHw->Spare1 |= chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE;
1237 REG_LOCAL_IRQ_RESTORE;
1238}
1239
1240/****************************************************************************/
1241/**
1242* @brief Disables DDR SW phase alignment interrupt
1243*/
1244/****************************************************************************/
1245static inline void chipcHw_ddrPhaseAlignInterruptDisable(void)
1246{
1247 REG_LOCAL_IRQ_SAVE;
1248 pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE;
1249 REG_LOCAL_IRQ_RESTORE;
1250}
1251
1252/****************************************************************************/
1253/**
1254* @brief Set VPM SW phase alignment interrupt mode
1255*
1256* This function sets VPM phase alignment interrupt
1257*/
1258/****************************************************************************/
1259static inline void
1260chipcHw_vpmPhaseAlignInterruptMode(chipcHw_VPM_HW_PHASE_INTR_e mode)
1261{
1262 REG_LOCAL_IRQ_SAVE;
1263 if (mode == chipcHw_VPM_HW_PHASE_INTR_DISABLE) {
1264 pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_PHASE_INTR_ENABLE;
1265 } else {
1266 pChipcHw->Spare1 |= chipcHw_REG_SPARE1_VPM_PHASE_INTR_ENABLE;
1267 }
1268 pChipcHw->VPMPhaseCtrl2 =
1269 (pChipcHw->
1270 VPMPhaseCtrl2 & ~(chipcHw_REG_VPM_INTR_SELECT_MASK <<
1271 chipcHw_REG_VPM_INTR_SELECT_SHIFT)) | mode;
1272 REG_LOCAL_IRQ_RESTORE;
1273}
1274
1275/****************************************************************************/
1276/**
1277* @brief Enable DDR phase alignment in software
1278*
1279*/
1280/****************************************************************************/
1281static inline void chipcHw_ddrSwPhaseAlignEnable(void)
1282{
1283 REG_LOCAL_IRQ_SAVE;
1284 pChipcHw->DDRPhaseCtrl1 |= chipcHw_REG_DDR_SW_PHASE_CTRL_ENABLE;
1285 REG_LOCAL_IRQ_RESTORE;
1286}
1287
1288/****************************************************************************/
1289/**
1290* @brief Disable DDR phase alignment in software
1291*
1292*/
1293/****************************************************************************/
1294static inline void chipcHw_ddrSwPhaseAlignDisable(void)
1295{
1296 REG_LOCAL_IRQ_SAVE;
1297 pChipcHw->DDRPhaseCtrl1 &= ~chipcHw_REG_DDR_SW_PHASE_CTRL_ENABLE;
1298 REG_LOCAL_IRQ_RESTORE;
1299}
1300
1301/****************************************************************************/
1302/**
1303* @brief Enable DDR phase alignment in hardware
1304*
1305*/
1306/****************************************************************************/
1307static inline void chipcHw_ddrHwPhaseAlignEnable(void)
1308{
1309 REG_LOCAL_IRQ_SAVE;
1310 pChipcHw->DDRPhaseCtrl1 |= chipcHw_REG_DDR_HW_PHASE_CTRL_ENABLE;
1311 REG_LOCAL_IRQ_RESTORE;
1312}
1313
1314/****************************************************************************/
1315/**
1316* @brief Disable DDR phase alignment in hardware
1317*
1318*/
1319/****************************************************************************/
1320static inline void chipcHw_ddrHwPhaseAlignDisable(void)
1321{
1322 REG_LOCAL_IRQ_SAVE;
1323 pChipcHw->DDRPhaseCtrl1 &= ~chipcHw_REG_DDR_HW_PHASE_CTRL_ENABLE;
1324 REG_LOCAL_IRQ_RESTORE;
1325}
1326
1327/****************************************************************************/
1328/**
1329* @brief Enable VPM phase alignment in software
1330*
1331*/
1332/****************************************************************************/
1333static inline void chipcHw_vpmSwPhaseAlignEnable(void)
1334{
1335 REG_LOCAL_IRQ_SAVE;
1336 pChipcHw->VPMPhaseCtrl1 |= chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE;
1337 REG_LOCAL_IRQ_RESTORE;
1338}
1339
1340/****************************************************************************/
1341/**
1342* @brief Disable VPM phase alignment in software
1343*
1344*/
1345/****************************************************************************/
1346static inline void chipcHw_vpmSwPhaseAlignDisable(void)
1347{
1348 REG_LOCAL_IRQ_SAVE;
1349 pChipcHw->VPMPhaseCtrl1 &= ~chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE;
1350 REG_LOCAL_IRQ_RESTORE;
1351}
1352
1353/****************************************************************************/
1354/**
1355* @brief Enable VPM phase alignment in hardware
1356*
1357*/
1358/****************************************************************************/
1359static inline void chipcHw_vpmHwPhaseAlignEnable(void)
1360{
1361 REG_LOCAL_IRQ_SAVE;
1362 pChipcHw->VPMPhaseCtrl1 |= chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE;
1363 REG_LOCAL_IRQ_RESTORE;
1364}
1365
1366/****************************************************************************/
1367/**
1368* @brief Disable VPM phase alignment in hardware
1369*
1370*/
1371/****************************************************************************/
1372static inline void chipcHw_vpmHwPhaseAlignDisable(void)
1373{
1374 REG_LOCAL_IRQ_SAVE;
1375 pChipcHw->VPMPhaseCtrl1 &= ~chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE;
1376 REG_LOCAL_IRQ_RESTORE;
1377}
1378
1379/****************************************************************************/
1380/**
1381* @brief Set DDR phase alignment margin in hardware
1382*
1383*/
1384/****************************************************************************/
1385static inline void
1386chipcHw_setDdrHwPhaseAlignMargin(chipcHw_DDR_HW_PHASE_MARGIN_e margin)
1387{
1388 uint32_t ge = 0;
1389 uint32_t le = 0;
1390
1391 switch (margin) {
1392 case chipcHw_DDR_HW_PHASE_MARGIN_STRICT:
1393 ge = 0x0F;
1394 le = 0x0F;
1395 break;
1396 case chipcHw_DDR_HW_PHASE_MARGIN_MEDIUM:
1397 ge = 0x03;
1398 le = 0x3F;
1399 break;
1400 case chipcHw_DDR_HW_PHASE_MARGIN_WIDE:
1401 ge = 0x01;
1402 le = 0x7F;
1403 break;
1404 }
1405
1406 {
1407 REG_LOCAL_IRQ_SAVE;
1408
1409 pChipcHw->DDRPhaseCtrl1 &=
1410 ~((chipcHw_REG_DDR_PHASE_VALUE_GE_MASK <<
1411 chipcHw_REG_DDR_PHASE_VALUE_GE_SHIFT)
1412 || (chipcHw_REG_DDR_PHASE_VALUE_LE_MASK <<
1413 chipcHw_REG_DDR_PHASE_VALUE_LE_SHIFT));
1414
1415 pChipcHw->DDRPhaseCtrl1 |=
1416 ((ge << chipcHw_REG_DDR_PHASE_VALUE_GE_SHIFT)
1417 || (le << chipcHw_REG_DDR_PHASE_VALUE_LE_SHIFT));
1418
1419 REG_LOCAL_IRQ_RESTORE;
1420 }
1421}
1422
1423/****************************************************************************/
1424/**
1425* @brief Set VPM phase alignment margin in hardware
1426*
1427*/
1428/****************************************************************************/
1429static inline void
1430chipcHw_setVpmHwPhaseAlignMargin(chipcHw_VPM_HW_PHASE_MARGIN_e margin)
1431{
1432 uint32_t ge = 0;
1433 uint32_t le = 0;
1434
1435 switch (margin) {
1436 case chipcHw_VPM_HW_PHASE_MARGIN_STRICT:
1437 ge = 0x0F;
1438 le = 0x0F;
1439 break;
1440 case chipcHw_VPM_HW_PHASE_MARGIN_MEDIUM:
1441 ge = 0x03;
1442 le = 0x3F;
1443 break;
1444 case chipcHw_VPM_HW_PHASE_MARGIN_WIDE:
1445 ge = 0x01;
1446 le = 0x7F;
1447 break;
1448 }
1449
1450 {
1451 REG_LOCAL_IRQ_SAVE;
1452
1453 pChipcHw->VPMPhaseCtrl1 &=
1454 ~((chipcHw_REG_VPM_PHASE_VALUE_GE_MASK <<
1455 chipcHw_REG_VPM_PHASE_VALUE_GE_SHIFT)
1456 || (chipcHw_REG_VPM_PHASE_VALUE_LE_MASK <<
1457 chipcHw_REG_VPM_PHASE_VALUE_LE_SHIFT));
1458
1459 pChipcHw->VPMPhaseCtrl1 |=
1460 ((ge << chipcHw_REG_VPM_PHASE_VALUE_GE_SHIFT)
1461 || (le << chipcHw_REG_VPM_PHASE_VALUE_LE_SHIFT));
1462
1463 REG_LOCAL_IRQ_RESTORE;
1464 }
1465}
1466
1467/****************************************************************************/
1468/**
1469* @brief Checks DDR phase aligned status done by HW
1470*
1471* @return 1: When aligned
1472* 0: When not aligned
1473*/
1474/****************************************************************************/
1475static inline uint32_t chipcHw_isDdrHwPhaseAligned(void)
1476{
1477 return (pChipcHw->
1478 PhaseAlignStatus & chipcHw_REG_DDR_PHASE_ALIGNED) ? 1 : 0;
1479}
1480
1481/****************************************************************************/
1482/**
1483* @brief Checks VPM phase aligned status done by HW
1484*
1485* @return 1: When aligned
1486* 0: When not aligned
1487*/
1488/****************************************************************************/
1489static inline uint32_t chipcHw_isVpmHwPhaseAligned(void)
1490{
1491 return (pChipcHw->
1492 PhaseAlignStatus & chipcHw_REG_VPM_PHASE_ALIGNED) ? 1 : 0;
1493}
1494
1495/****************************************************************************/
1496/**
1497* @brief Get DDR phase aligned status done by HW
1498*
1499*/
1500/****************************************************************************/
1501static inline uint32_t chipcHw_getDdrHwPhaseAlignStatus(void)
1502{
1503 return (pChipcHw->
1504 PhaseAlignStatus & chipcHw_REG_DDR_PHASE_STATUS_MASK) >>
1505 chipcHw_REG_DDR_PHASE_STATUS_SHIFT;
1506}
1507
1508/****************************************************************************/
1509/**
1510* @brief Get VPM phase aligned status done by HW
1511*
1512*/
1513/****************************************************************************/
1514static inline uint32_t chipcHw_getVpmHwPhaseAlignStatus(void)
1515{
1516 return (pChipcHw->
1517 PhaseAlignStatus & chipcHw_REG_VPM_PHASE_STATUS_MASK) >>
1518 chipcHw_REG_VPM_PHASE_STATUS_SHIFT;
1519}
1520
1521/****************************************************************************/
1522/**
1523* @brief Get DDR phase control value
1524*
1525*/
1526/****************************************************************************/
1527static inline uint32_t chipcHw_getDdrPhaseControl(void)
1528{
1529 return (pChipcHw->
1530 PhaseAlignStatus & chipcHw_REG_DDR_PHASE_CTRL_MASK) >>
1531 chipcHw_REG_DDR_PHASE_CTRL_SHIFT;
1532}
1533
1534/****************************************************************************/
1535/**
1536* @brief Get VPM phase control value
1537*
1538*/
1539/****************************************************************************/
1540static inline uint32_t chipcHw_getVpmPhaseControl(void)
1541{
1542 return (pChipcHw->
1543 PhaseAlignStatus & chipcHw_REG_VPM_PHASE_CTRL_MASK) >>
1544 chipcHw_REG_VPM_PHASE_CTRL_SHIFT;
1545}
1546
1547/****************************************************************************/
1548/**
1549* @brief DDR phase alignment timeout count
1550*
1551* @note If HW fails to perform the phase alignment, it will trigger
1552* a DDR phase alignment timeout interrupt.
1553*/
1554/****************************************************************************/
1555static inline void chipcHw_ddrHwPhaseAlignTimeout(uint32_t busCycle)
1556{
1557 REG_LOCAL_IRQ_SAVE;
1558 pChipcHw->DDRPhaseCtrl2 &=
1559 ~(chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_MASK <<
1560 chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_SHIFT);
1561 pChipcHw->DDRPhaseCtrl2 |=
1562 (busCycle & chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_MASK) <<
1563 chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_SHIFT;
1564 REG_LOCAL_IRQ_RESTORE;
1565}
1566
1567/****************************************************************************/
1568/**
1569* @brief VPM phase alignment timeout count
1570*
1571* @note If HW fails to perform the phase alignment, it will trigger
1572* a VPM phase alignment timeout interrupt.
1573*/
1574/****************************************************************************/
1575static inline void chipcHw_vpmHwPhaseAlignTimeout(uint32_t busCycle)
1576{
1577 REG_LOCAL_IRQ_SAVE;
1578 pChipcHw->VPMPhaseCtrl2 &=
1579 ~(chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_MASK <<
1580 chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_SHIFT);
1581 pChipcHw->VPMPhaseCtrl2 |=
1582 (busCycle & chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_MASK) <<
1583 chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_SHIFT;
1584 REG_LOCAL_IRQ_RESTORE;
1585}
1586
1587/****************************************************************************/
1588/**
1589* @brief Clear DDR phase alignment timeout interrupt
1590*
1591*/
1592/****************************************************************************/
1593static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptClear(void)
1594{
1595 REG_LOCAL_IRQ_SAVE;
1596 /* Clear timeout interrupt service bit */
1597 pChipcHw->DDRPhaseCtrl2 |= chipcHw_REG_DDR_INTR_SERVICED;
1598 pChipcHw->DDRPhaseCtrl2 &= ~chipcHw_REG_DDR_INTR_SERVICED;
1599 REG_LOCAL_IRQ_RESTORE;
1600}
1601
1602/****************************************************************************/
1603/**
1604* @brief Clear VPM phase alignment timeout interrupt
1605*
1606*/
1607/****************************************************************************/
1608static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptClear(void)
1609{
1610 REG_LOCAL_IRQ_SAVE;
1611 /* Clear timeout interrupt service bit */
1612 pChipcHw->VPMPhaseCtrl2 |= chipcHw_REG_VPM_INTR_SERVICED;
1613 pChipcHw->VPMPhaseCtrl2 &= ~chipcHw_REG_VPM_INTR_SERVICED;
1614 REG_LOCAL_IRQ_RESTORE;
1615}
1616
1617/****************************************************************************/
1618/**
1619* @brief DDR phase alignment timeout interrupt enable
1620*
1621*/
1622/****************************************************************************/
1623static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptEnable(void)
1624{
1625 REG_LOCAL_IRQ_SAVE;
1626 chipcHw_ddrHwPhaseAlignTimeoutInterruptClear(); /* Recommended */
1627 /* Enable timeout interrupt */
1628 pChipcHw->DDRPhaseCtrl2 |= chipcHw_REG_DDR_TIMEOUT_INTR_ENABLE;
1629 REG_LOCAL_IRQ_RESTORE;
1630}
1631
1632/****************************************************************************/
1633/**
1634* @brief VPM phase alignment timeout interrupt enable
1635*
1636*/
1637/****************************************************************************/
1638static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptEnable(void)
1639{
1640 REG_LOCAL_IRQ_SAVE;
1641 chipcHw_vpmHwPhaseAlignTimeoutInterruptClear(); /* Recommended */
1642 /* Enable timeout interrupt */
1643 pChipcHw->VPMPhaseCtrl2 |= chipcHw_REG_VPM_TIMEOUT_INTR_ENABLE;
1644 REG_LOCAL_IRQ_RESTORE;
1645}
1646
1647/****************************************************************************/
1648/**
1649* @brief DDR phase alignment timeout interrupt disable
1650*
1651*/
1652/****************************************************************************/
1653static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptDisable(void)
1654{
1655 REG_LOCAL_IRQ_SAVE;
1656 pChipcHw->DDRPhaseCtrl2 &= ~chipcHw_REG_DDR_TIMEOUT_INTR_ENABLE;
1657 REG_LOCAL_IRQ_RESTORE;
1658}
1659
1660/****************************************************************************/
1661/**
1662* @brief VPM phase alignment timeout interrupt disable
1663*
1664*/
1665/****************************************************************************/
1666static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptDisable(void)
1667{
1668 REG_LOCAL_IRQ_SAVE;
1669 pChipcHw->VPMPhaseCtrl2 &= ~chipcHw_REG_VPM_TIMEOUT_INTR_ENABLE;
1670 REG_LOCAL_IRQ_RESTORE;
1671}
1672
1673#endif /* CHIPC_INLINE_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h
new file mode 100644
index 00000000000..b162448f613
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h
@@ -0,0 +1,530 @@
1/*****************************************************************************
2* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/****************************************************************************/
16/**
17* @file chipcHw_reg.h
18*
19* @brief Definitions for low level chip control registers
20*
21*/
22/****************************************************************************/
23#ifndef CHIPCHW_REG_H
24#define CHIPCHW_REG_H
25
26#include <mach/csp/mm_io.h>
27#include <csp/reg.h>
28#include <mach/csp/ddrcReg.h>
29
30#define chipcHw_BASE_ADDRESS MM_IO_BASE_CHIPC
31
32typedef struct {
33 uint32_t ChipId; /* Chip ID */
34 uint32_t DDRClock; /* PLL1 Channel 1 for DDR clock */
35 uint32_t ARMClock; /* PLL1 Channel 2 for ARM clock */
36 uint32_t ESWClock; /* PLL1 Channel 3 for ESW system clock */
37 uint32_t VPMClock; /* PLL1 Channel 4 for VPM clock */
38 uint32_t ESW125Clock; /* PLL1 Channel 5 for ESW 125MHz clock */
39 uint32_t UARTClock; /* PLL1 Channel 6 for UART clock */
40 uint32_t SDIO0Clock; /* PLL1 Channel 7 for SDIO 0 clock */
41 uint32_t SDIO1Clock; /* PLL1 Channel 8 for SDIO 1 clock */
42 uint32_t SPIClock; /* PLL1 Channel 9 for SPI master Clock */
43 uint32_t ETMClock; /* PLL1 Channel 10 for ARM ETM Clock */
44
45 uint32_t ACLKClock; /* ACLK Clock (Divider) */
46 uint32_t OTPClock; /* OTP Clock (Divider) */
47 uint32_t I2CClock; /* I2C Clock (CK_13m) (Divider) */
48 uint32_t I2S0Clock; /* I2S0 Clock (Divider) */
49 uint32_t RTBUSClock; /* RTBUS (DDR PHY Config.) Clock (Divider) */
50 uint32_t pad1;
51 uint32_t APM100Clock; /* APM 100MHz CLK Clock (Divider) */
52 uint32_t TSCClock; /* TSC Clock (Divider) */
53 uint32_t LEDClock; /* LED Clock (Divider) */
54
55 uint32_t USBClock; /* PLL2 Channel 1 for USB clock */
56 uint32_t LCDClock; /* PLL2 Channel 2 for LCD clock */
57 uint32_t APMClock; /* PLL2 Channel 3 for APM 200 MHz clock */
58
59 uint32_t BusIntfClock; /* Bus interface clock */
60
61 uint32_t PLLStatus; /* PLL status register (PLL1) */
62 uint32_t PLLConfig; /* PLL configuration register (PLL1) */
63 uint32_t PLLPreDivider; /* PLL pre-divider control register (PLL1) */
64 uint32_t PLLDivider; /* PLL divider control register (PLL1) */
65 uint32_t PLLControl1; /* PLL analog control register #1 (PLL1) */
66 uint32_t PLLControl2; /* PLL analog control register #2 (PLL1) */
67
68 uint32_t I2S1Clock; /* I2S1 Clock */
69 uint32_t AudioEnable; /* Enable/ disable audio channel */
70 uint32_t SoftReset1; /* Reset blocks */
71 uint32_t SoftReset2; /* Reset blocks */
72 uint32_t Spare1; /* Phase align interrupts */
73 uint32_t Sticky; /* Sticky bits */
74 uint32_t MiscCtrl; /* Misc. control */
75 uint32_t pad3[3];
76
77 uint32_t PLLStatus2; /* PLL status register (PLL2) */
78 uint32_t PLLConfig2; /* PLL configuration register (PLL2) */
79 uint32_t PLLPreDivider2; /* PLL pre-divider control register (PLL2) */
80 uint32_t PLLDivider2; /* PLL divider control register (PLL2) */
81 uint32_t PLLControl12; /* PLL analog control register #1 (PLL2) */
82 uint32_t PLLControl22; /* PLL analog control register #2 (PLL2) */
83
84 uint32_t DDRPhaseCtrl1; /* DDR Clock Phase Alignment control1 */
85 uint32_t VPMPhaseCtrl1; /* VPM Clock Phase Alignment control1 */
86 uint32_t PhaseAlignStatus; /* DDR/VPM Clock Phase Alignment Status */
87 uint32_t PhaseCtrlStatus; /* DDR/VPM Clock HW DDR/VPM ph_ctrl and load_ch Status */
88 uint32_t DDRPhaseCtrl2; /* DDR Clock Phase Alignment control2 */
89 uint32_t VPMPhaseCtrl2; /* VPM Clock Phase Alignment control2 */
90 uint32_t pad4[9];
91
92 uint32_t SoftOTP1; /* Software OTP control */
93 uint32_t SoftOTP2; /* Software OTP control */
94 uint32_t SoftStraps; /* Software strap */
95 uint32_t PinStraps; /* Pin Straps */
96 uint32_t DiffOscCtrl; /* Diff oscillator control */
97 uint32_t DiagsCtrl; /* Diagnostic control */
98 uint32_t DiagsOutputCtrl; /* Diagnostic output enable */
99 uint32_t DiagsReadBackCtrl; /* Diagnostic read back control */
100
101 uint32_t LcdPifMode; /* LCD/PIF Pin Sharing MUX Mode */
102
103 uint32_t GpioMux_0_7; /* Pin Sharing MUX0 Control */
104 uint32_t GpioMux_8_15; /* Pin Sharing MUX1 Control */
105 uint32_t GpioMux_16_23; /* Pin Sharing MUX2 Control */
106 uint32_t GpioMux_24_31; /* Pin Sharing MUX3 Control */
107 uint32_t GpioMux_32_39; /* Pin Sharing MUX4 Control */
108 uint32_t GpioMux_40_47; /* Pin Sharing MUX5 Control */
109 uint32_t GpioMux_48_55; /* Pin Sharing MUX6 Control */
110 uint32_t GpioMux_56_63; /* Pin Sharing MUX7 Control */
111
112 uint32_t GpioSR_0_7; /* Slew rate for GPIO 0 - 7 */
113 uint32_t GpioSR_8_15; /* Slew rate for GPIO 8 - 15 */
114 uint32_t GpioSR_16_23; /* Slew rate for GPIO 16 - 23 */
115 uint32_t GpioSR_24_31; /* Slew rate for GPIO 24 - 31 */
116 uint32_t GpioSR_32_39; /* Slew rate for GPIO 32 - 39 */
117 uint32_t GpioSR_40_47; /* Slew rate for GPIO 40 - 47 */
118 uint32_t GpioSR_48_55; /* Slew rate for GPIO 48 - 55 */
119 uint32_t GpioSR_56_63; /* Slew rate for GPIO 56 - 63 */
120 uint32_t MiscSR_0_7; /* Slew rate for MISC 0 - 7 */
121 uint32_t MiscSR_8_15; /* Slew rate for MISC 8 - 15 */
122
123 uint32_t GpioPull_0_15; /* Pull up registers for GPIO 0 - 15 */
124 uint32_t GpioPull_16_31; /* Pull up registers for GPIO 16 - 31 */
125 uint32_t GpioPull_32_47; /* Pull up registers for GPIO 32 - 47 */
126 uint32_t GpioPull_48_63; /* Pull up registers for GPIO 48 - 63 */
127 uint32_t MiscPull_0_15; /* Pull up registers for MISC 0 - 15 */
128
129 uint32_t GpioInput_0_31; /* Input type for GPIO 0 - 31 */
130 uint32_t GpioInput_32_63; /* Input type for GPIO 32 - 63 */
131 uint32_t MiscInput_0_15; /* Input type for MISC 0 - 16 */
132} chipcHw_REG_t;
133
134#define pChipcHw ((volatile chipcHw_REG_t *) chipcHw_BASE_ADDRESS)
135#define pChipcPhysical ((volatile chipcHw_REG_t *) MM_ADDR_IO_CHIPC)
136
137#define chipcHw_REG_CHIPID_BASE_MASK 0xFFFFF000
138#define chipcHw_REG_CHIPID_BASE_SHIFT 12
139#define chipcHw_REG_CHIPID_REV_MASK 0x00000FFF
140#define chipcHw_REG_REV_A0 0xA00
141#define chipcHw_REG_REV_B0 0x0B0
142
143#define chipcHw_REG_PLL_STATUS_CONTROL_ENABLE 0x80000000 /* Allow controlling PLL registers */
144#define chipcHw_REG_PLL_STATUS_LOCKED 0x00000001 /* PLL is settled */
145#define chipcHw_REG_PLL_CONFIG_D_RESET 0x00000008 /* Digital reset */
146#define chipcHw_REG_PLL_CONFIG_A_RESET 0x00000004 /* Analog reset */
147#define chipcHw_REG_PLL_CONFIG_BYPASS_ENABLE 0x00000020 /* Bypass enable */
148#define chipcHw_REG_PLL_CONFIG_OUTPUT_ENABLE 0x00000010 /* Output enable */
149#define chipcHw_REG_PLL_CONFIG_POWER_DOWN 0x00000001 /* Power down */
150#define chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ 1600000000 /* 1.6GHz VCO split frequency */
151#define chipcHw_REG_PLL_CONFIG_VCO_800_1600 0x00000000 /* VCO range 800-1600 MHz */
152#define chipcHw_REG_PLL_CONFIG_VCO_1601_3200 0x00000080 /* VCO range 1601-3200 MHz */
153#define chipcHw_REG_PLL_CONFIG_TEST_ENABLE 0x00010000 /* PLL test output enable */
154#define chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK 0x003E0000 /* Mask to set test values */
155#define chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT 17
156
157#define chipcHw_REG_PLL_CLOCK_PHASE_COMP 0x00800000 /* Phase comparator output */
158#define chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK 0x00300000 /* Clock to bus ratio mask */
159#define chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT 20 /* Number of bits to be shifted */
160#define chipcHw_REG_PLL_CLOCK_POWER_DOWN 0x00080000 /* PLL channel power down */
161#define chipcHw_REG_PLL_CLOCK_SOURCE_GPIO 0x00040000 /* Use GPIO as source */
162#define chipcHw_REG_PLL_CLOCK_BYPASS_SELECT 0x00020000 /* Select bypass clock */
163#define chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE 0x00010000 /* Clock gated ON */
164#define chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE 0x00008000 /* Clock phase update enable */
165#define chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT 8 /* Number of bits to be shifted */
166#define chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK 0x00003F00 /* Phase control mask */
167#define chipcHw_REG_PLL_CLOCK_MDIV_MASK 0x000000FF /* Clock post divider mask
168
169 00000000 = divide-by-256
170 00000001 = divide-by-1
171 00000010 = divide-by-2
172 00000011 = divide-by-3
173 00000100 = divide-by-4
174 00000101 = divide-by-5
175 00000110 = divide-by-6
176 .
177 .
178 11111011 = divide-by-251
179 11111100 = divide-by-252
180 11111101 = divide-by-253
181 11111110 = divide-by-254
182 */
183
184#define chipcHw_REG_DIV_CLOCK_SOURCE_OTHER 0x00040000 /* NON-PLL clock source select */
185#define chipcHw_REG_DIV_CLOCK_BYPASS_SELECT 0x00020000 /* NON-PLL clock bypass enable */
186#define chipcHw_REG_DIV_CLOCK_OUTPUT_ENABLE 0x00010000 /* NON-PLL clock output enable */
187#define chipcHw_REG_DIV_CLOCK_DIV_MASK 0x000000FF /* NON-PLL clock post-divide mask */
188#define chipcHw_REG_DIV_CLOCK_DIV_256 0x00000000 /* NON-PLL clock post-divide by 256 */
189
190#define chipcHw_REG_PLL_PREDIVIDER_P1_SHIFT 0
191#define chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT 4
192#define chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT 8
193#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK 0x0001FF00
194#define chipcHw_REG_PLL_PREDIVIDER_POWER_DOWN 0x02000000
195#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK 0x00700000 /* Divider mask */
196#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER 0x00000000 /* Integer-N Mode */
197#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASH_UNIT 0x00100000 /* MASH Sigma-Delta Modulator Unit Mode */
198#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MFB_UNIT 0x00200000 /* MFB Sigma-Delta Modulator Unit Mode */
199#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASH_1_8 0x00300000 /* MASH Sigma-Delta Modulator 1/8 Mode */
200#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MFB_1_8 0x00400000 /* MFB Sigma-Delta Modulator 1/8 Mode */
201
202#define chipcHw_REG_PLL_PREDIVIDER_NDIV_i(vco) ((vco) / chipcHw_XTAL_FREQ_Hz)
203#define chipcHw_REG_PLL_PREDIVIDER_P1 1
204#define chipcHw_REG_PLL_PREDIVIDER_P2 1
205
206#define chipcHw_REG_PLL_DIVIDER_M1DIV 0x03000000
207#define chipcHw_REG_PLL_DIVIDER_FRAC 0x00FFFFFF /* Fractional divider */
208
209#define chipcHw_REG_PLL_DIVIDER_NDIV_f_SS (0x00FFFFFF) /* To attain spread with max frequency */
210
211#define chipcHw_REG_PLL_DIVIDER_NDIV_f 0 /* ndiv_frac = chipcHw_REG_PLL_DIVIDER_NDIV_f /
212 chipcHw_REG_PLL_DIVIDER_FRAC
213 = 0, when SS is disable
214 */
215
216#define chipcHw_REG_PLL_DIVIDER_MDIV(vco, Hz) ((chipcHw_divide((vco), (Hz)) > 255) ? 0 : chipcHw_divide((vco), (Hz)))
217
218#define chipcHw_REG_ACLKClock_CLK_DIV_MASK 0x3
219
220/* System booting strap options */
221#define chipcHw_STRAPS_SOFT_OVERRIDE 0x00000001 /* Software Strap Override */
222
223#define chipcHw_STRAPS_BOOT_DEVICE_NAND_FLASH_8 0x00000000 /* 8 bit NAND FLASH Boot */
224#define chipcHw_STRAPS_BOOT_DEVICE_NOR_FLASH_16 0x00000002 /* 16 bit NOR FLASH Boot */
225#define chipcHw_STRAPS_BOOT_DEVICE_SERIAL_FLASH 0x00000004 /* Serial FLASH Boot */
226#define chipcHw_STRAPS_BOOT_DEVICE_NAND_FLASH_16 0x00000006 /* 16 bit NAND FLASH Boot */
227#define chipcHw_STRAPS_BOOT_DEVICE_UART 0x00000008 /* UART Boot */
228#define chipcHw_STRAPS_BOOT_DEVICE_MASK 0x0000000E /* Mask */
229
230/* System boot option */
231#define chipcHw_STRAPS_BOOT_OPTION_BROM 0x00000000 /* Boot from Boot ROM */
232#define chipcHw_STRAPS_BOOT_OPTION_ARAM 0x00000020 /* Boot from ARAM */
233#define chipcHw_STRAPS_BOOT_OPTION_NOR 0x00000030 /* Boot from NOR flash */
234
235/* NAND Flash page size strap options */
236#define chipcHw_STRAPS_NAND_PAGESIZE_512 0x00000000 /* NAND FLASH page size of 512 bytes */
237#define chipcHw_STRAPS_NAND_PAGESIZE_2048 0x00000040 /* NAND FLASH page size of 2048 bytes */
238#define chipcHw_STRAPS_NAND_PAGESIZE_4096 0x00000080 /* NAND FLASH page size of 4096 bytes */
239#define chipcHw_STRAPS_NAND_PAGESIZE_EXT 0x000000C0 /* NAND FLASH page of extened size */
240#define chipcHw_STRAPS_NAND_PAGESIZE_MASK 0x000000C0 /* Mask */
241
242#define chipcHw_STRAPS_NAND_EXTRA_CYCLE 0x00000400 /* NAND FLASH address cycle configuration */
243#define chipcHw_STRAPS_REBOOT_TO_UART 0x00000800 /* Reboot to UART on error */
244
245/* Secure boot mode strap options */
246#define chipcHw_STRAPS_BOOT_MODE_NORMAL 0x00000000 /* Normal Boot */
247#define chipcHw_STRAPS_BOOT_MODE_DBG_SW 0x00000100 /* Software debugging Boot */
248#define chipcHw_STRAPS_BOOT_MODE_DBG_BOOT 0x00000200 /* Boot rom debugging Boot */
249#define chipcHw_STRAPS_BOOT_MODE_NORMAL_QUIET 0x00000300 /* Normal Boot (Quiet BootRom) */
250#define chipcHw_STRAPS_BOOT_MODE_MASK 0x00000300 /* Mask */
251
252/* Slave Mode straps */
253#define chipcHw_STRAPS_I2CS 0x02000000 /* I2C Slave */
254#define chipcHw_STRAPS_SPIS 0x01000000 /* SPI Slave */
255
256/* Strap pin options */
257#define chipcHw_REG_SW_STRAPS ((pChipcHw->PinStraps & 0x0000FC00) >> 10)
258
259/* PIF/LCD pin sharing defines */
260#define chipcHw_REG_LCD_PIN_ENABLE 0x00000001 /* LCD Controller is used and the pins have LCD functions */
261#define chipcHw_REG_PIF_PIN_ENABLE 0x00000002 /* LCD pins are used to perform PIF functions */
262
263#define chipcHw_GPIO_COUNT 61 /* Number of GPIO pin accessible thorugh CHIPC */
264
265/* NOTE: Any changes to these constants will require a corresponding change to chipcHw_str.c */
266#define chipcHw_REG_GPIO_MUX_KEYPAD 0x00000001 /* GPIO mux for Keypad */
267#define chipcHw_REG_GPIO_MUX_I2CH 0x00000002 /* GPIO mux for I2CH */
268#define chipcHw_REG_GPIO_MUX_SPI 0x00000003 /* GPIO mux for SPI */
269#define chipcHw_REG_GPIO_MUX_UART 0x00000004 /* GPIO mux for UART */
270#define chipcHw_REG_GPIO_MUX_LEDMTXP 0x00000005 /* GPIO mux for LEDMTXP */
271#define chipcHw_REG_GPIO_MUX_LEDMTXS 0x00000006 /* GPIO mux for LEDMTXS */
272#define chipcHw_REG_GPIO_MUX_SDIO0 0x00000007 /* GPIO mux for SDIO0 */
273#define chipcHw_REG_GPIO_MUX_SDIO1 0x00000008 /* GPIO mux for SDIO1 */
274#define chipcHw_REG_GPIO_MUX_PCM 0x00000009 /* GPIO mux for PCM */
275#define chipcHw_REG_GPIO_MUX_I2S 0x0000000A /* GPIO mux for I2S */
276#define chipcHw_REG_GPIO_MUX_ETM 0x0000000B /* GPIO mux for ETM */
277#define chipcHw_REG_GPIO_MUX_DEBUG 0x0000000C /* GPIO mux for DEBUG */
278#define chipcHw_REG_GPIO_MUX_MISC 0x0000000D /* GPIO mux for MISC */
279#define chipcHw_REG_GPIO_MUX_GPIO 0x00000000 /* GPIO mux for GPIO */
280#define chipcHw_REG_GPIO_MUX(pin) (&pChipcHw->GpioMux_0_7 + ((pin) >> 3))
281#define chipcHw_REG_GPIO_MUX_POSITION(pin) (((pin) & 0x00000007) << 2)
282#define chipcHw_REG_GPIO_MUX_MASK 0x0000000F /* Mask */
283
284#define chipcHw_REG_SLEW_RATE_HIGH 0x00000000 /* High speed slew rate */
285#define chipcHw_REG_SLEW_RATE_NORMAL 0x00000008 /* Normal slew rate */
286 /* Pins beyond 42 are defined by skipping 8 bits within the register */
287#define chipcHw_REG_SLEW_RATE(pin) (((pin) > 42) ? (&pChipcHw->GpioSR_0_7 + (((pin) + 2) >> 3)) : (&pChipcHw->GpioSR_0_7 + ((pin) >> 3)))
288#define chipcHw_REG_SLEW_RATE_POSITION(pin) (((pin) > 42) ? ((((pin) + 2) & 0x00000007) << 2) : (((pin) & 0x00000007) << 2))
289#define chipcHw_REG_SLEW_RATE_MASK 0x00000008 /* Mask */
290
291#define chipcHw_REG_CURRENT_STRENGTH_2mA 0x00000001 /* Current driving strength 2 milli ampere */
292#define chipcHw_REG_CURRENT_STRENGTH_4mA 0x00000002 /* Current driving strength 4 milli ampere */
293#define chipcHw_REG_CURRENT_STRENGTH_6mA 0x00000004 /* Current driving strength 6 milli ampere */
294#define chipcHw_REG_CURRENT_STRENGTH_8mA 0x00000005 /* Current driving strength 8 milli ampere */
295#define chipcHw_REG_CURRENT_STRENGTH_10mA 0x00000006 /* Current driving strength 10 milli ampere */
296#define chipcHw_REG_CURRENT_STRENGTH_12mA 0x00000007 /* Current driving strength 12 milli ampere */
297#define chipcHw_REG_CURRENT_MASK 0x00000007 /* Mask */
298 /* Pins beyond 42 are defined by skipping 8 bits */
299#define chipcHw_REG_CURRENT(pin) (((pin) > 42) ? (&pChipcHw->GpioSR_0_7 + (((pin) + 2) >> 3)) : (&pChipcHw->GpioSR_0_7 + ((pin) >> 3)))
300#define chipcHw_REG_CURRENT_POSITION(pin) (((pin) > 42) ? ((((pin) + 2) & 0x00000007) << 2) : (((pin) & 0x00000007) << 2))
301
302#define chipcHw_REG_PULL_NONE 0x00000000 /* No pull up register */
303#define chipcHw_REG_PULL_UP 0x00000001 /* Pull up register enable */
304#define chipcHw_REG_PULL_DOWN 0x00000002 /* Pull down register enable */
305#define chipcHw_REG_PULLUP_MASK 0x00000003 /* Mask */
306 /* Pins beyond 42 are defined by skipping 4 bits */
307#define chipcHw_REG_PULLUP(pin) (((pin) > 42) ? (&pChipcHw->GpioPull_0_15 + (((pin) + 2) >> 4)) : (&pChipcHw->GpioPull_0_15 + ((pin) >> 4)))
308#define chipcHw_REG_PULLUP_POSITION(pin) (((pin) > 42) ? ((((pin) + 2) & 0x0000000F) << 1) : (((pin) & 0x0000000F) << 1))
309
310#define chipcHw_REG_INPUTTYPE_CMOS 0x00000000 /* Normal CMOS logic */
311#define chipcHw_REG_INPUTTYPE_ST 0x00000001 /* High speed Schmitt Trigger */
312#define chipcHw_REG_INPUTTYPE_MASK 0x00000001 /* Mask */
313 /* Pins beyond 42 are defined by skipping 2 bits */
314#define chipcHw_REG_INPUTTYPE(pin) (((pin) > 42) ? (&pChipcHw->GpioInput_0_31 + (((pin) + 2) >> 5)) : (&pChipcHw->GpioInput_0_31 + ((pin) >> 5)))
315#define chipcHw_REG_INPUTTYPE_POSITION(pin) (((pin) > 42) ? ((((pin) + 2) & 0x0000001F)) : (((pin) & 0x0000001F)))
316
317/* Device connected to the bus clock */
318#define chipcHw_REG_BUS_CLOCK_ARM 0x00000001 /* Bus interface clock for ARM */
319#define chipcHw_REG_BUS_CLOCK_VDEC 0x00000002 /* Bus interface clock for VDEC */
320#define chipcHw_REG_BUS_CLOCK_ARAM 0x00000004 /* Bus interface clock for ARAM */
321#define chipcHw_REG_BUS_CLOCK_HPM 0x00000008 /* Bus interface clock for HPM */
322#define chipcHw_REG_BUS_CLOCK_DDRC 0x00000010 /* Bus interface clock for DDRC */
323#define chipcHw_REG_BUS_CLOCK_DMAC0 0x00000020 /* Bus interface clock for DMAC0 */
324#define chipcHw_REG_BUS_CLOCK_DMAC1 0x00000040 /* Bus interface clock for DMAC1 */
325#define chipcHw_REG_BUS_CLOCK_NVI 0x00000080 /* Bus interface clock for NVI */
326#define chipcHw_REG_BUS_CLOCK_ESW 0x00000100 /* Bus interface clock for ESW */
327#define chipcHw_REG_BUS_CLOCK_GE 0x00000200 /* Bus interface clock for GE */
328#define chipcHw_REG_BUS_CLOCK_I2CH 0x00000400 /* Bus interface clock for I2CH */
329#define chipcHw_REG_BUS_CLOCK_I2S0 0x00000800 /* Bus interface clock for I2S0 */
330#define chipcHw_REG_BUS_CLOCK_I2S1 0x00001000 /* Bus interface clock for I2S1 */
331#define chipcHw_REG_BUS_CLOCK_VRAM 0x00002000 /* Bus interface clock for VRAM */
332#define chipcHw_REG_BUS_CLOCK_CLCD 0x00004000 /* Bus interface clock for CLCD */
333#define chipcHw_REG_BUS_CLOCK_LDK 0x00008000 /* Bus interface clock for LDK */
334#define chipcHw_REG_BUS_CLOCK_LED 0x00010000 /* Bus interface clock for LED */
335#define chipcHw_REG_BUS_CLOCK_OTP 0x00020000 /* Bus interface clock for OTP */
336#define chipcHw_REG_BUS_CLOCK_PIF 0x00040000 /* Bus interface clock for PIF */
337#define chipcHw_REG_BUS_CLOCK_SPU 0x00080000 /* Bus interface clock for SPU */
338#define chipcHw_REG_BUS_CLOCK_SDIO0 0x00100000 /* Bus interface clock for SDIO0 */
339#define chipcHw_REG_BUS_CLOCK_SDIO1 0x00200000 /* Bus interface clock for SDIO1 */
340#define chipcHw_REG_BUS_CLOCK_SPIH 0x00400000 /* Bus interface clock for SPIH */
341#define chipcHw_REG_BUS_CLOCK_SPIS 0x00800000 /* Bus interface clock for SPIS */
342#define chipcHw_REG_BUS_CLOCK_UART0 0x01000000 /* Bus interface clock for UART0 */
343#define chipcHw_REG_BUS_CLOCK_UART1 0x02000000 /* Bus interface clock for UART1 */
344#define chipcHw_REG_BUS_CLOCK_BBL 0x04000000 /* Bus interface clock for BBL */
345#define chipcHw_REG_BUS_CLOCK_I2CS 0x08000000 /* Bus interface clock for I2CS */
346#define chipcHw_REG_BUS_CLOCK_USBH 0x10000000 /* Bus interface clock for USB Host */
347#define chipcHw_REG_BUS_CLOCK_USBD 0x20000000 /* Bus interface clock for USB Device */
348#define chipcHw_REG_BUS_CLOCK_BROM 0x40000000 /* Bus interface clock for Boot ROM */
349#define chipcHw_REG_BUS_CLOCK_TSC 0x80000000 /* Bus interface clock for Touch screen */
350
351/* Software resets defines */
352#define chipcHw_REG_SOFT_RESET_VPM_GLOBAL_HOLD 0x0000000080000000ULL /* Reset Global VPM and hold */
353#define chipcHw_REG_SOFT_RESET_VPM_HOLD 0x0000000040000000ULL /* Reset VPM and hold */
354#define chipcHw_REG_SOFT_RESET_VPM_GLOBAL 0x0000000020000000ULL /* Reset Global VPM */
355#define chipcHw_REG_SOFT_RESET_VPM 0x0000000010000000ULL /* Reset VPM */
356#define chipcHw_REG_SOFT_RESET_KEYPAD 0x0000000008000000ULL /* Reset Key pad */
357#define chipcHw_REG_SOFT_RESET_LED 0x0000000004000000ULL /* Reset LED */
358#define chipcHw_REG_SOFT_RESET_SPU 0x0000000002000000ULL /* Reset SPU */
359#define chipcHw_REG_SOFT_RESET_RNG 0x0000000001000000ULL /* Reset RNG */
360#define chipcHw_REG_SOFT_RESET_PKA 0x0000000000800000ULL /* Reset PKA */
361#define chipcHw_REG_SOFT_RESET_LCD 0x0000000000400000ULL /* Reset LCD */
362#define chipcHw_REG_SOFT_RESET_PIF 0x0000000000200000ULL /* Reset PIF */
363#define chipcHw_REG_SOFT_RESET_I2CS 0x0000000000100000ULL /* Reset I2C Slave */
364#define chipcHw_REG_SOFT_RESET_I2CH 0x0000000000080000ULL /* Reset I2C Host */
365#define chipcHw_REG_SOFT_RESET_SDIO1 0x0000000000040000ULL /* Reset SDIO 1 */
366#define chipcHw_REG_SOFT_RESET_SDIO0 0x0000000000020000ULL /* Reset SDIO 0 */
367#define chipcHw_REG_SOFT_RESET_BBL 0x0000000000010000ULL /* Reset BBL */
368#define chipcHw_REG_SOFT_RESET_I2S1 0x0000000000008000ULL /* Reset I2S1 */
369#define chipcHw_REG_SOFT_RESET_I2S0 0x0000000000004000ULL /* Reset I2S0 */
370#define chipcHw_REG_SOFT_RESET_SPIS 0x0000000000002000ULL /* Reset SPI Slave */
371#define chipcHw_REG_SOFT_RESET_SPIH 0x0000000000001000ULL /* Reset SPI Host */
372#define chipcHw_REG_SOFT_RESET_GPIO1 0x0000000000000800ULL /* Reset GPIO block 1 */
373#define chipcHw_REG_SOFT_RESET_GPIO0 0x0000000000000400ULL /* Reset GPIO block 0 */
374#define chipcHw_REG_SOFT_RESET_UART1 0x0000000000000200ULL /* Reset UART 1 */
375#define chipcHw_REG_SOFT_RESET_UART0 0x0000000000000100ULL /* Reset UART 0 */
376#define chipcHw_REG_SOFT_RESET_NVI 0x0000000000000080ULL /* Reset NVI */
377#define chipcHw_REG_SOFT_RESET_WDOG 0x0000000000000040ULL /* Reset Watch dog */
378#define chipcHw_REG_SOFT_RESET_TMR 0x0000000000000020ULL /* Reset Timer */
379#define chipcHw_REG_SOFT_RESET_ETM 0x0000000000000010ULL /* Reset ETM */
380#define chipcHw_REG_SOFT_RESET_ARM_HOLD 0x0000000000000008ULL /* Reset ARM and HOLD */
381#define chipcHw_REG_SOFT_RESET_ARM 0x0000000000000004ULL /* Reset ARM */
382#define chipcHw_REG_SOFT_RESET_CHIP_WARM 0x0000000000000002ULL /* Chip warm reset */
383#define chipcHw_REG_SOFT_RESET_CHIP_SOFT 0x0000000000000001ULL /* Chip soft reset */
384#define chipcHw_REG_SOFT_RESET_VDEC 0x0000100000000000ULL /* Video decoder */
385#define chipcHw_REG_SOFT_RESET_GE 0x0000080000000000ULL /* Graphics engine */
386#define chipcHw_REG_SOFT_RESET_OTP 0x0000040000000000ULL /* Reset OTP */
387#define chipcHw_REG_SOFT_RESET_USB2 0x0000020000000000ULL /* Reset USB2 */
388#define chipcHw_REG_SOFT_RESET_USB1 0x0000010000000000ULL /* Reset USB 1 */
389#define chipcHw_REG_SOFT_RESET_USB 0x0000008000000000ULL /* Reset USB 1 and USB2 soft reset */
390#define chipcHw_REG_SOFT_RESET_ESW 0x0000004000000000ULL /* Reset Ethernet switch */
391#define chipcHw_REG_SOFT_RESET_ESWCLK 0x0000002000000000ULL /* Reset Ethernet switch clock */
392#define chipcHw_REG_SOFT_RESET_DDRPHY 0x0000001000000000ULL /* Reset DDR Physical */
393#define chipcHw_REG_SOFT_RESET_DDR 0x0000000800000000ULL /* Reset DDR Controller */
394#define chipcHw_REG_SOFT_RESET_TSC 0x0000000400000000ULL /* Reset Touch screen */
395#define chipcHw_REG_SOFT_RESET_PCM 0x0000000200000000ULL /* Reset PCM device */
396#define chipcHw_REG_SOFT_RESET_APM 0x0000200100000000ULL /* Reset APM device */
397
398#define chipcHw_REG_SOFT_RESET_VPM_GLOBAL_UNHOLD 0x8000000000000000ULL /* Unhold Global VPM */
399#define chipcHw_REG_SOFT_RESET_VPM_UNHOLD 0x4000000000000000ULL /* Unhold VPM */
400#define chipcHw_REG_SOFT_RESET_ARM_UNHOLD 0x2000000000000000ULL /* Unhold ARM reset */
401#define chipcHw_REG_SOFT_RESET_UNHOLD_MASK 0xF000000000000000ULL /* Mask to handle unhold request */
402
403/* Audio channel control defines */
404#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_ALL 0x00000001 /* Enable all audio channel */
405#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_A 0x00000002 /* Enable channel A */
406#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_B 0x00000004 /* Enable channel B */
407#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_C 0x00000008 /* Enable channel C */
408#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_NTP_CLOCK 0x00000010 /* Enable NTP clock */
409#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_PCM0_CLOCK 0x00000020 /* Enable PCM0 clock */
410#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_PCM1_CLOCK 0x00000040 /* Enable PCM1 clock */
411#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_APM_CLOCK 0x00000080 /* Enable APM clock */
412
413/* Misc. chip control defines */
414#define chipcHw_REG_MISC_CTRL_GE_SEL 0x00040000 /* Select GE2/GE3 */
415#define chipcHw_REG_MISC_CTRL_I2S1_CLOCK_ONCHIP 0x00000000 /* Use on chip clock for I2S1 */
416#define chipcHw_REG_MISC_CTRL_I2S1_CLOCK_GPIO 0x00020000 /* Use external clock via GPIO pin 26 for I2S1 */
417#define chipcHw_REG_MISC_CTRL_I2S0_CLOCK_ONCHIP 0x00000000 /* Use on chip clock for I2S0 */
418#define chipcHw_REG_MISC_CTRL_I2S0_CLOCK_GPIO 0x00010000 /* Use external clock via GPIO pin 45 for I2S0 */
419#define chipcHw_REG_MISC_CTRL_ARM_CP15_DISABLE 0x00008000 /* Disable ARM CP15 bit */
420#define chipcHw_REG_MISC_CTRL_RTC_DISABLE 0x00000008 /* Disable RTC registers */
421#define chipcHw_REG_MISC_CTRL_BBRAM_DISABLE 0x00000004 /* Disable Battery Backed RAM */
422#define chipcHw_REG_MISC_CTRL_USB_MODE_HOST 0x00000002 /* Set USB as host */
423#define chipcHw_REG_MISC_CTRL_USB_MODE_DEVICE 0xFFFFFFFD /* Set USB as device */
424#define chipcHw_REG_MISC_CTRL_USB_POWERON 0xFFFFFFFE /* Power up USB */
425#define chipcHw_REG_MISC_CTRL_USB_POWEROFF 0x00000001 /* Power down USB */
426
427/* OTP configuration defines */
428#define chipcHw_REG_OTP_SECURITY_OFF 0x0000020000000000ULL /* Security support is OFF */
429#define chipcHw_REG_OTP_SPU_SLOW 0x0000010000000000ULL /* Limited SPU throughput */
430#define chipcHw_REG_OTP_LCD_SPEED 0x0000000600000000ULL /* Set VPM speed one */
431#define chipcHw_REG_OTP_VPM_SPEED_1 0x0000000100000000ULL /* Set VPM speed one */
432#define chipcHw_REG_OTP_VPM_SPEED_0 0x0000000080000000ULL /* Set VPM speed zero */
433#define chipcHw_REG_OTP_AXI_SPEED 0x0000000060000000ULL /* Set maximum AXI bus speed */
434#define chipcHw_REG_OTP_APM_DISABLE 0x000000001F000000ULL /* Disable APM */
435#define chipcHw_REG_OTP_PIF_DISABLE 0x0000000000200000ULL /* Disable PIF */
436#define chipcHw_REG_OTP_VDEC_DISABLE 0x0000000000100000ULL /* Disable Video decoder */
437#define chipcHw_REG_OTP_BBL_DISABLE 0x0000000000080000ULL /* Disable RTC and BBRAM */
438#define chipcHw_REG_OTP_LED_DISABLE 0x0000000000040000ULL /* Disable LED */
439#define chipcHw_REG_OTP_GE_DISABLE 0x0000000000020000ULL /* Disable Graphics Engine */
440#define chipcHw_REG_OTP_LCD_DISABLE 0x0000000000010000ULL /* Disable LCD */
441#define chipcHw_REG_OTP_KEYPAD_DISABLE 0x0000000000008000ULL /* Disable keypad */
442#define chipcHw_REG_OTP_UART_DISABLE 0x0000000000004000ULL /* Disable UART */
443#define chipcHw_REG_OTP_SDIOH_DISABLE 0x0000000000003000ULL /* Disable SDIO host */
444#define chipcHw_REG_OTP_HSS_DISABLE 0x0000000000000C00ULL /* Disable HSS */
445#define chipcHw_REG_OTP_TSC_DISABLE 0x0000000000000200ULL /* Disable touch screen */
446#define chipcHw_REG_OTP_USB_DISABLE 0x0000000000000180ULL /* Disable USB */
447#define chipcHw_REG_OTP_SGMII_DISABLE 0x0000000000000060ULL /* Disable SGMII */
448#define chipcHw_REG_OTP_ETH_DISABLE 0x0000000000000018ULL /* Disable gigabit ethernet */
449#define chipcHw_REG_OTP_ETH_PHY_DISABLE 0x0000000000000006ULL /* Disable ethernet PHY */
450#define chipcHw_REG_OTP_VPM_DISABLE 0x0000000000000001ULL /* Disable VPM */
451
452/* Sticky bit defines */
453#define chipcHw_REG_STICKY_BOOT_DONE 0x00000001 /* Boot done */
454#define chipcHw_REG_STICKY_SOFT_RESET 0x00000002 /* ARM soft reset */
455#define chipcHw_REG_STICKY_GENERAL_1 0x00000004 /* General purpose bit 1 */
456#define chipcHw_REG_STICKY_GENERAL_2 0x00000008 /* General purpose bit 2 */
457#define chipcHw_REG_STICKY_GENERAL_3 0x00000010 /* General purpose bit 3 */
458#define chipcHw_REG_STICKY_GENERAL_4 0x00000020 /* General purpose bit 4 */
459#define chipcHw_REG_STICKY_GENERAL_5 0x00000040 /* General purpose bit 5 */
460#define chipcHw_REG_STICKY_POR_BROM 0x00000080 /* Special sticky bit for security - set in BROM to avoid other modes being entered */
461#define chipcHw_REG_STICKY_ARM_RESET 0x00000100 /* ARM reset */
462#define chipcHw_REG_STICKY_CHIP_SOFT_RESET 0x00000200 /* Chip soft reset */
463#define chipcHw_REG_STICKY_CHIP_WARM_RESET 0x00000400 /* Chip warm reset */
464#define chipcHw_REG_STICKY_WDOG_RESET 0x00000800 /* Watchdog reset */
465#define chipcHw_REG_STICKY_OTP_RESET 0x00001000 /* OTP reset */
466
467 /* HW phase alignment defines *//* Spare1 register definitions */
468#define chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE 0x80000000 /* Enable DDR phase align panic interrupt */
469#define chipcHw_REG_SPARE1_VPM_PHASE_INTR_ENABLE 0x40000000 /* Enable VPM phase align panic interrupt */
470#define chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE 0x00000002 /* Enable access to VPM using system BUS */
471#define chipcHw_REG_SPARE1_DDR_BUS_ACCESS_ENABLE 0x00000001 /* Enable access to DDR using system BUS */
472 /* DDRPhaseCtrl1 register definitions */
473#define chipcHw_REG_DDR_SW_PHASE_CTRL_ENABLE 0x80000000 /* Enable DDR SW phase alignment */
474#define chipcHw_REG_DDR_HW_PHASE_CTRL_ENABLE 0x40000000 /* Enable DDR HW phase alignment */
475#define chipcHw_REG_DDR_PHASE_VALUE_GE_MASK 0x0000007F /* DDR lower threshold for phase alignment */
476#define chipcHw_REG_DDR_PHASE_VALUE_GE_SHIFT 23
477#define chipcHw_REG_DDR_PHASE_VALUE_LE_MASK 0x0000007F /* DDR upper threshold for phase alignment */
478#define chipcHw_REG_DDR_PHASE_VALUE_LE_SHIFT 16
479#define chipcHw_REG_DDR_PHASE_ALIGN_WAIT_CYCLE_MASK 0x0000FFFF /* BUS Cycle to wait to run next DDR phase alignment */
480#define chipcHw_REG_DDR_PHASE_ALIGN_WAIT_CYCLE_SHIFT 0
481 /* VPMPhaseCtrl1 register definitions */
482#define chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE 0x80000000 /* Enable VPM SW phase alignment */
483#define chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE 0x40000000 /* Enable VPM HW phase alignment */
484#define chipcHw_REG_VPM_PHASE_VALUE_GE_MASK 0x0000007F /* VPM lower threshold for phase alignment */
485#define chipcHw_REG_VPM_PHASE_VALUE_GE_SHIFT 23
486#define chipcHw_REG_VPM_PHASE_VALUE_LE_MASK 0x0000007F /* VPM upper threshold for phase alignment */
487#define chipcHw_REG_VPM_PHASE_VALUE_LE_SHIFT 16
488#define chipcHw_REG_VPM_PHASE_ALIGN_WAIT_CYCLE_MASK 0x0000FFFF /* BUS Cycle to wait to complete the VPM phase alignment */
489#define chipcHw_REG_VPM_PHASE_ALIGN_WAIT_CYCLE_SHIFT 0
490 /* PhaseAlignStatus register definitions */
491#define chipcHw_REG_DDR_TIMEOUT_INTR_STATUS 0x80000000 /* DDR time out interrupt status */
492#define chipcHw_REG_DDR_PHASE_STATUS_MASK 0x0000007F /* DDR phase status value */
493#define chipcHw_REG_DDR_PHASE_STATUS_SHIFT 24
494#define chipcHw_REG_DDR_PHASE_ALIGNED 0x00800000 /* DDR Phase aligned status */
495#define chipcHw_REG_DDR_LOAD 0x00400000 /* Load DDR phase status */
496#define chipcHw_REG_DDR_PHASE_CTRL_MASK 0x0000003F /* DDR phase control value */
497#define chipcHw_REG_DDR_PHASE_CTRL_SHIFT 16
498#define chipcHw_REG_VPM_TIMEOUT_INTR_STATUS 0x80000000 /* VPM time out interrupt status */
499#define chipcHw_REG_VPM_PHASE_STATUS_MASK 0x0000007F /* VPM phase status value */
500#define chipcHw_REG_VPM_PHASE_STATUS_SHIFT 8
501#define chipcHw_REG_VPM_PHASE_ALIGNED 0x00000080 /* VPM Phase aligned status */
502#define chipcHw_REG_VPM_LOAD 0x00000040 /* Load VPM phase status */
503#define chipcHw_REG_VPM_PHASE_CTRL_MASK 0x0000003F /* VPM phase control value */
504#define chipcHw_REG_VPM_PHASE_CTRL_SHIFT 0
505 /* DDRPhaseCtrl2 register definitions */
506#define chipcHw_REG_DDR_INTR_SERVICED 0x02000000 /* Acknowledge that interrupt was serviced */
507#define chipcHw_REG_DDR_TIMEOUT_INTR_ENABLE 0x01000000 /* Enable time out interrupt */
508#define chipcHw_REG_DDR_LOAD_COUNT_PHASE_CTRL_MASK 0x0000000F /* Wait before toggling load_ch */
509#define chipcHw_REG_DDR_LOAD_COUNT_PHASE_CTRL_SHIFT 20
510#define chipcHw_REG_DDR_TOTAL_LOAD_COUNT_CTRL_MASK 0x0000000F /* Total wait to settle ph_ctrl and load_ch */
511#define chipcHw_REG_DDR_TOTAL_LOAD_COUNT_CTRL_SHIFT 16
512#define chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_MASK 0x0000FFFF /* Time out value for DDR HW phase alignment */
513#define chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_SHIFT 0
514 /* VPMPhaseCtrl2 register definitions */
515#define chipcHw_REG_VPM_INTR_SELECT_MASK 0x00000003 /* Interrupt select */
516#define chipcHw_REG_VPM_INTR_SELECT_SHIFT 26
517#define chipcHw_REG_VPM_INTR_DISABLE 0x00000000
518#define chipcHw_REG_VPM_INTR_FAST (0x1 << chipcHw_REG_VPM_INTR_SELECT_SHIFT)
519#define chipcHw_REG_VPM_INTR_MEDIUM (0x2 << chipcHw_REG_VPM_INTR_SELECT_SHIFT)
520#define chipcHw_REG_VPM_INTR_SLOW (0x3 << chipcHw_REG_VPM_INTR_SELECT_SHIFT)
521#define chipcHw_REG_VPM_INTR_SERVICED 0x02000000 /* Acknowledge that interrupt was serviced */
522#define chipcHw_REG_VPM_TIMEOUT_INTR_ENABLE 0x01000000 /* Enable time out interrupt */
523#define chipcHw_REG_VPM_LOAD_COUNT_PHASE_CTRL_MASK 0x0000000F /* Wait before toggling load_ch */
524#define chipcHw_REG_VPM_LOAD_COUNT_PHASE_CTRL_SHIFT 20
525#define chipcHw_REG_VPM_TOTAL_LOAD_COUNT_CTRL_MASK 0x0000000F /* Total wait cycle to settle ph_ctrl and load_ch */
526#define chipcHw_REG_VPM_TOTAL_LOAD_COUNT_CTRL_SHIFT 16
527#define chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_MASK 0x0000FFFF /* Time out value for VPM HW phase alignment */
528#define chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_SHIFT 0
529
530#endif /* CHIPCHW_REG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h b/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h
new file mode 100644
index 00000000000..f1b68e26fa6
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h
@@ -0,0 +1,872 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/****************************************************************************/
16/**
17* @file ddrcReg.h
18*
19* @brief Register definitions for BCMRING DDR2 Controller and PHY
20*
21*/
22/****************************************************************************/
23
24#ifndef DDRC_REG_H
25#define DDRC_REG_H
26
27#ifdef __cplusplus
28extern "C" {
29#endif
30
31/* ---- Include Files ---------------------------------------------------- */
32
33#include <csp/reg.h>
34#include <csp/stdint.h>
35
36#include <mach/csp/mm_io.h>
37
38/* ---- Public Constants and Types --------------------------------------- */
39
40/*********************************************************************/
41/* DDR2 Controller (ARM PL341) register definitions */
42/*********************************************************************/
43
44/* -------------------------------------------------------------------- */
45/* -------------------------------------------------------------------- */
46/* ARM PL341 DDR2 configuration registers, offset 0x000 */
47/* -------------------------------------------------------------------- */
48/* -------------------------------------------------------------------- */
49
50 typedef struct {
51 uint32_t memcStatus;
52 uint32_t memcCmd;
53 uint32_t directCmd;
54 uint32_t memoryCfg;
55 uint32_t refreshPrd;
56 uint32_t casLatency;
57 uint32_t writeLatency;
58 uint32_t tMrd;
59 uint32_t tRas;
60 uint32_t tRc;
61 uint32_t tRcd;
62 uint32_t tRfc;
63 uint32_t tRp;
64 uint32_t tRrd;
65 uint32_t tWr;
66 uint32_t tWtr;
67 uint32_t tXp;
68 uint32_t tXsr;
69 uint32_t tEsr;
70 uint32_t memoryCfg2;
71 uint32_t memoryCfg3;
72 uint32_t tFaw;
73 } ddrcReg_CTLR_MEMC_REG_t;
74
75#define ddrcReg_CTLR_MEMC_REG_OFFSET 0x0000
76#define ddrcReg_CTLR_MEMC_REGP ((volatile ddrcReg_CTLR_MEMC_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_CTLR_MEMC_REG_OFFSET))
77
78/* ----------------------------------------------------- */
79
80#define ddrcReg_CTLR_MEMC_STATUS_BANKS_MASK (0x3 << 12)
81#define ddrcReg_CTLR_MEMC_STATUS_BANKS_4 (0x0 << 12)
82#define ddrcReg_CTLR_MEMC_STATUS_BANKS_8 (0x3 << 12)
83
84#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_MASK (0x3 << 10)
85#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_0 (0x0 << 10)
86#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_1 (0x1 << 10)
87#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_2 (0x2 << 10)
88#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_4 (0x3 << 10)
89
90#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_MASK (0x3 << 7)
91#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_1 (0x0 << 7)
92#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_2 (0x1 << 7)
93#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_3 (0x2 << 7)
94#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_4 (0x3 << 7)
95
96#define ddrcReg_CTLR_MEMC_STATUS_TYPE_MASK (0x7 << 4)
97#define ddrcReg_CTLR_MEMC_STATUS_TYPE_DDR2 (0x5 << 4)
98
99#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_MASK (0x3 << 2)
100#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_16 (0x0 << 2)
101#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_32 (0x1 << 2)
102#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_64 (0x2 << 2)
103#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_128 (0x3 << 2)
104
105#define ddrcReg_CTLR_MEMC_STATUS_STATE_MASK (0x3 << 0)
106#define ddrcReg_CTLR_MEMC_STATUS_STATE_CONFIG (0x0 << 0)
107#define ddrcReg_CTLR_MEMC_STATUS_STATE_READY (0x1 << 0)
108#define ddrcReg_CTLR_MEMC_STATUS_STATE_PAUSED (0x2 << 0)
109#define ddrcReg_CTLR_MEMC_STATUS_STATE_LOWPWR (0x3 << 0)
110
111/* ----------------------------------------------------- */
112
113#define ddrcReg_CTLR_MEMC_CMD_MASK (0x7 << 0)
114#define ddrcReg_CTLR_MEMC_CMD_GO (0x0 << 0)
115#define ddrcReg_CTLR_MEMC_CMD_SLEEP (0x1 << 0)
116#define ddrcReg_CTLR_MEMC_CMD_WAKEUP (0x2 << 0)
117#define ddrcReg_CTLR_MEMC_CMD_PAUSE (0x3 << 0)
118#define ddrcReg_CTLR_MEMC_CMD_CONFIGURE (0x4 << 0)
119#define ddrcReg_CTLR_MEMC_CMD_ACTIVE_PAUSE (0x7 << 0)
120
121/* ----------------------------------------------------- */
122
123#define ddrcReg_CTLR_DIRECT_CMD_CHIP_SHIFT 20
124#define ddrcReg_CTLR_DIRECT_CMD_CHIP_MASK (0x3 << ddrcReg_CTLR_DIRECT_CMD_CHIP_SHIFT)
125
126#define ddrcReg_CTLR_DIRECT_CMD_TYPE_PRECHARGEALL (0x0 << 18)
127#define ddrcReg_CTLR_DIRECT_CMD_TYPE_AUTOREFRESH (0x1 << 18)
128#define ddrcReg_CTLR_DIRECT_CMD_TYPE_MODEREG (0x2 << 18)
129#define ddrcReg_CTLR_DIRECT_CMD_TYPE_NOP (0x3 << 18)
130
131#define ddrcReg_CTLR_DIRECT_CMD_BANK_SHIFT 16
132#define ddrcReg_CTLR_DIRECT_CMD_BANK_MASK (0x3 << ddrcReg_CTLR_DIRECT_CMD_BANK_SHIFT)
133
134#define ddrcReg_CTLR_DIRECT_CMD_ADDR_SHIFT 0
135#define ddrcReg_CTLR_DIRECT_CMD_ADDR_MASK (0x1ffff << ddrcReg_CTLR_DIRECT_CMD_ADDR_SHIFT)
136
137/* ----------------------------------------------------- */
138
139#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_MASK (0x3 << 21)
140#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_1 (0x0 << 21)
141#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_2 (0x1 << 21)
142#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_3 (0x2 << 21)
143#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_4 (0x3 << 21)
144
145#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_MASK (0x7 << 18)
146#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_3_0 (0x0 << 18)
147#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_4_1 (0x1 << 18)
148#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_5_2 (0x2 << 18)
149#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_6_3 (0x3 << 18)
150#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_7_4 (0x4 << 18)
151#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_8_5 (0x5 << 18)
152#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_9_6 (0x6 << 18)
153#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_10_7 (0x7 << 18)
154
155#define ddrcReg_CTLR_MEMORY_CFG_BURST_LEN_MASK (0x7 << 15)
156#define ddrcReg_CTLR_MEMORY_CFG_BURST_LEN_4 (0x2 << 15)
157#define ddrcReg_CTLR_MEMORY_CFG_BURST_LEN_8 (0x3 << 15) /* @note Not supported in PL341 */
158
159#define ddrcReg_CTLR_MEMORY_CFG_PWRDOWN_ENABLE (0x1 << 13)
160
161#define ddrcReg_CTLR_MEMORY_CFG_PWRDOWN_CYCLES_SHIFT 7
162#define ddrcReg_CTLR_MEMORY_CFG_PWRDOWN_CYCLES_MASK (0x3f << ddrcReg_CTLR_MEMORY_CFG_PWRDOWN_CYCLES_SHIFT)
163
164#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_MASK (0x7 << 3)
165#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_11 (0x0 << 3)
166#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_12 (0x1 << 3)
167#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_13 (0x2 << 3)
168#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_14 (0x3 << 3)
169#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_15 (0x4 << 3)
170#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_16 (0x5 << 3)
171
172#define ddrcReg_CTLR_MEMORY_CFG_AXI_COL_BITS_MASK (0x7 << 0)
173#define ddrcReg_CTLR_MEMORY_CFG_AXI_COL_BITS_9 (0x1 << 0)
174#define ddrcReg_CTLR_MEMORY_CFG_AXI_COL_BITS_10 (0x2 << 0)
175#define ddrcReg_CTLR_MEMORY_CFG_AXI_COL_BITS_11 (0x3 << 0)
176
177/* ----------------------------------------------------- */
178
179#define ddrcReg_CTLR_REFRESH_PRD_SHIFT 0
180#define ddrcReg_CTLR_REFRESH_PRD_MASK (0x7fff << ddrcReg_CTLR_REFRESH_PRD_SHIFT)
181
182/* ----------------------------------------------------- */
183
184#define ddrcReg_CTLR_CAS_LATENCY_SHIFT 1
185#define ddrcReg_CTLR_CAS_LATENCY_MASK (0x7 << ddrcReg_CTLR_CAS_LATENCY_SHIFT)
186
187/* ----------------------------------------------------- */
188
189#define ddrcReg_CTLR_WRITE_LATENCY_SHIFT 0
190#define ddrcReg_CTLR_WRITE_LATENCY_MASK (0x7 << ddrcReg_CTLR_WRITE_LATENCY_SHIFT)
191
192/* ----------------------------------------------------- */
193
194#define ddrcReg_CTLR_T_MRD_SHIFT 0
195#define ddrcReg_CTLR_T_MRD_MASK (0x7f << ddrcReg_CTLR_T_MRD_SHIFT)
196
197/* ----------------------------------------------------- */
198
199#define ddrcReg_CTLR_T_RAS_SHIFT 0
200#define ddrcReg_CTLR_T_RAS_MASK (0x1f << ddrcReg_CTLR_T_RAS_SHIFT)
201
202/* ----------------------------------------------------- */
203
204#define ddrcReg_CTLR_T_RC_SHIFT 0
205#define ddrcReg_CTLR_T_RC_MASK (0x1f << ddrcReg_CTLR_T_RC_SHIFT)
206
207/* ----------------------------------------------------- */
208
209#define ddrcReg_CTLR_T_RCD_SCHEDULE_DELAY_SHIFT 8
210#define ddrcReg_CTLR_T_RCD_SCHEDULE_DELAY_MASK (0x7 << ddrcReg_CTLR_T_RCD_SCHEDULE_DELAY_SHIFT)
211
212#define ddrcReg_CTLR_T_RCD_SHIFT 0
213#define ddrcReg_CTLR_T_RCD_MASK (0x7 << ddrcReg_CTLR_T_RCD_SHIFT)
214
215/* ----------------------------------------------------- */
216
217#define ddrcReg_CTLR_T_RFC_SCHEDULE_DELAY_SHIFT 8
218#define ddrcReg_CTLR_T_RFC_SCHEDULE_DELAY_MASK (0x7f << ddrcReg_CTLR_T_RFC_SCHEDULE_DELAY_SHIFT)
219
220#define ddrcReg_CTLR_T_RFC_SHIFT 0
221#define ddrcReg_CTLR_T_RFC_MASK (0x7f << ddrcReg_CTLR_T_RFC_SHIFT)
222
223/* ----------------------------------------------------- */
224
225#define ddrcReg_CTLR_T_RP_SCHEDULE_DELAY_SHIFT 8
226#define ddrcReg_CTLR_T_RP_SCHEDULE_DELAY_MASK (0x7 << ddrcReg_CTLR_T_RP_SCHEDULE_DELAY_SHIFT)
227
228#define ddrcReg_CTLR_T_RP_SHIFT 0
229#define ddrcReg_CTLR_T_RP_MASK (0xf << ddrcReg_CTLR_T_RP_SHIFT)
230
231/* ----------------------------------------------------- */
232
233#define ddrcReg_CTLR_T_RRD_SHIFT 0
234#define ddrcReg_CTLR_T_RRD_MASK (0xf << ddrcReg_CTLR_T_RRD_SHIFT)
235
236/* ----------------------------------------------------- */
237
238#define ddrcReg_CTLR_T_WR_SHIFT 0
239#define ddrcReg_CTLR_T_WR_MASK (0x7 << ddrcReg_CTLR_T_WR_SHIFT)
240
241/* ----------------------------------------------------- */
242
243#define ddrcReg_CTLR_T_WTR_SHIFT 0
244#define ddrcReg_CTLR_T_WTR_MASK (0x7 << ddrcReg_CTLR_T_WTR_SHIFT)
245
246/* ----------------------------------------------------- */
247
248#define ddrcReg_CTLR_T_XP_SHIFT 0
249#define ddrcReg_CTLR_T_XP_MASK (0xff << ddrcReg_CTLR_T_XP_SHIFT)
250
251/* ----------------------------------------------------- */
252
253#define ddrcReg_CTLR_T_XSR_SHIFT 0
254#define ddrcReg_CTLR_T_XSR_MASK (0xff << ddrcReg_CTLR_T_XSR_SHIFT)
255
256/* ----------------------------------------------------- */
257
258#define ddrcReg_CTLR_T_ESR_SHIFT 0
259#define ddrcReg_CTLR_T_ESR_MASK (0xff << ddrcReg_CTLR_T_ESR_SHIFT)
260
261/* ----------------------------------------------------- */
262
263#define ddrcReg_CTLR_MEMORY_CFG2_WIDTH_MASK (0x3 << 6)
264#define ddrcReg_CTLR_MEMORY_CFG2_WIDTH_16BITS (0 << 6)
265#define ddrcReg_CTLR_MEMORY_CFG2_WIDTH_32BITS (1 << 6)
266#define ddrcReg_CTLR_MEMORY_CFG2_WIDTH_64BITS (2 << 6)
267
268#define ddrcReg_CTLR_MEMORY_CFG2_AXI_BANK_BITS_MASK (0x3 << 4)
269#define ddrcReg_CTLR_MEMORY_CFG2_AXI_BANK_BITS_2 (0 << 4)
270#define ddrcReg_CTLR_MEMORY_CFG2_AXI_BANK_BITS_3 (3 << 4)
271
272#define ddrcReg_CTLR_MEMORY_CFG2_CKE_INIT_STATE_LOW (0 << 3)
273#define ddrcReg_CTLR_MEMORY_CFG2_CKE_INIT_STATE_HIGH (1 << 3)
274
275#define ddrcReg_CTLR_MEMORY_CFG2_DQM_INIT_STATE_LOW (0 << 2)
276#define ddrcReg_CTLR_MEMORY_CFG2_DQM_INIT_STATE_HIGH (1 << 2)
277
278#define ddrcReg_CTLR_MEMORY_CFG2_CLK_MASK (0x3 << 0)
279#define ddrcReg_CTLR_MEMORY_CFG2_CLK_ASYNC (0 << 0)
280#define ddrcReg_CTLR_MEMORY_CFG2_CLK_SYNC_A_LE_M (1 << 0)
281#define ddrcReg_CTLR_MEMORY_CFG2_CLK_SYNC_A_GT_M (3 << 0)
282
283/* ----------------------------------------------------- */
284
285#define ddrcReg_CTLR_MEMORY_CFG3_REFRESH_TO_SHIFT 0
286#define ddrcReg_CTLR_MEMORY_CFG3_REFRESH_TO_MASK (0x7 << ddrcReg_CTLR_MEMORY_CFG3_REFRESH_TO_SHIFT)
287
288/* ----------------------------------------------------- */
289
290#define ddrcReg_CTLR_T_FAW_SCHEDULE_DELAY_SHIFT 8
291#define ddrcReg_CTLR_T_FAW_SCHEDULE_DELAY_MASK (0x1f << ddrcReg_CTLR_T_FAW_SCHEDULE_DELAY_SHIFT)
292
293#define ddrcReg_CTLR_T_FAW_PERIOD_SHIFT 0
294#define ddrcReg_CTLR_T_FAW_PERIOD_MASK (0x1f << ddrcReg_CTLR_T_FAW_PERIOD_SHIFT)
295
296/* -------------------------------------------------------------------- */
297/* -------------------------------------------------------------------- */
298/* ARM PL341 AXI ID QOS configuration registers, offset 0x100 */
299/* -------------------------------------------------------------------- */
300/* -------------------------------------------------------------------- */
301
302#define ddrcReg_CTLR_QOS_CNT 16
303#define ddrcReg_CTLR_QOS_MAX (ddrcReg_CTLR_QOS_CNT - 1)
304
305 typedef struct {
306 uint32_t cfg[ddrcReg_CTLR_QOS_CNT];
307 } ddrcReg_CTLR_QOS_REG_t;
308
309#define ddrcReg_CTLR_QOS_REG_OFFSET 0x100
310#define ddrcReg_CTLR_QOS_REGP ((volatile ddrcReg_CTLR_QOS_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_CTLR_QOS_REG_OFFSET))
311
312/* ----------------------------------------------------- */
313
314#define ddrcReg_CTLR_QOS_CFG_MAX_SHIFT 2
315#define ddrcReg_CTLR_QOS_CFG_MAX_MASK (0xff << ddrcReg_CTLR_QOS_CFG_MAX_SHIFT)
316
317#define ddrcReg_CTLR_QOS_CFG_MIN_SHIFT 1
318#define ddrcReg_CTLR_QOS_CFG_MIN_MASK (1 << ddrcReg_CTLR_QOS_CFG_MIN_SHIFT)
319
320#define ddrcReg_CTLR_QOS_CFG_ENABLE (1 << 0)
321
322/* -------------------------------------------------------------------- */
323/* -------------------------------------------------------------------- */
324/* ARM PL341 Memory chip configuration registers, offset 0x200 */
325/* -------------------------------------------------------------------- */
326/* -------------------------------------------------------------------- */
327
328#define ddrcReg_CTLR_CHIP_CNT 4
329#define ddrcReg_CTLR_CHIP_MAX (ddrcReg_CTLR_CHIP_CNT - 1)
330
331 typedef struct {
332 uint32_t cfg[ddrcReg_CTLR_CHIP_CNT];
333 } ddrcReg_CTLR_CHIP_REG_t;
334
335#define ddrcReg_CTLR_CHIP_REG_OFFSET 0x200
336#define ddrcReg_CTLR_CHIP_REGP ((volatile ddrcReg_CTLR_CHIP_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_CTLR_CHIP_REG_OFFSET))
337
338/* ----------------------------------------------------- */
339
340#define ddrcReg_CTLR_CHIP_CFG_MEM_ORG_MASK (1 << 16)
341#define ddrcReg_CTLR_CHIP_CFG_MEM_ORG_ROW_BANK_COL (0 << 16)
342#define ddrcReg_CTLR_CHIP_CFG_MEM_ORG_BANK_ROW_COL (1 << 16)
343
344#define ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MATCH_SHIFT 8
345#define ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MATCH_MASK (0xff << ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MATCH_SHIFT)
346
347#define ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MASK_SHIFT 0
348#define ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MASK_MASK (0xff << ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MASK_SHIFT)
349
350/* -------------------------------------------------------------------- */
351/* -------------------------------------------------------------------- */
352/* ARM PL341 User configuration registers, offset 0x300 */
353/* -------------------------------------------------------------------- */
354/* -------------------------------------------------------------------- */
355
356#define ddrcReg_CTLR_USER_OUTPUT_CNT 2
357
358 typedef struct {
359 uint32_t input;
360 uint32_t output[ddrcReg_CTLR_USER_OUTPUT_CNT];
361 uint32_t feature;
362 } ddrcReg_CTLR_USER_REG_t;
363
364#define ddrcReg_CTLR_USER_REG_OFFSET 0x300
365#define ddrcReg_CTLR_USER_REGP ((volatile ddrcReg_CTLR_USER_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_CTLR_USER_REG_OFFSET))
366
367/* ----------------------------------------------------- */
368
369#define ddrcReg_CTLR_USER_INPUT_STATUS_SHIFT 0
370#define ddrcReg_CTLR_USER_INPUT_STATUS_MASK (0xff << ddrcReg_CTLR_USER_INPUT_STATUS_SHIFT)
371
372/* ----------------------------------------------------- */
373
374#define ddrcReg_CTLR_USER_OUTPUT_CFG_SHIFT 0
375#define ddrcReg_CTLR_USER_OUTPUT_CFG_MASK (0xff << ddrcReg_CTLR_USER_OUTPUT_CFG_SHIFT)
376
377#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_SHIFT 1
378#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_MASK (1 << ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_SHIFT)
379#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_BP134 (0 << ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_SHIFT)
380#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_PL301 (1 << ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_SHIFT)
381#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_REGISTERED ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_PL301
382
383/* ----------------------------------------------------- */
384
385#define ddrcReg_CTLR_FEATURE_WRITE_BLOCK_DISABLE (1 << 2)
386#define ddrcReg_CTLR_FEATURE_EARLY_BURST_RSP_DISABLE (1 << 0)
387
388/*********************************************************************/
389/* Broadcom DDR23 PHY register definitions */
390/*********************************************************************/
391
392/* -------------------------------------------------------------------- */
393/* -------------------------------------------------------------------- */
394/* Broadcom DDR23 PHY Address and Control register definitions */
395/* -------------------------------------------------------------------- */
396/* -------------------------------------------------------------------- */
397
398 typedef struct {
399 uint32_t revision;
400 uint32_t pmCtl;
401 REG32_RSVD(0x0008, 0x0010);
402 uint32_t pllStatus;
403 uint32_t pllCfg;
404 uint32_t pllPreDiv;
405 uint32_t pllDiv;
406 uint32_t pllCtl1;
407 uint32_t pllCtl2;
408 uint32_t ssCtl;
409 uint32_t ssCfg;
410 uint32_t vdlStatic;
411 uint32_t vdlDynamic;
412 uint32_t padIdle;
413 uint32_t pvtComp;
414 uint32_t padDrive;
415 uint32_t clkRgltrCtl;
416 } ddrcReg_PHY_ADDR_CTL_REG_t;
417
418#define ddrcReg_PHY_ADDR_CTL_REG_OFFSET 0x0400
419#define ddrcReg_PHY_ADDR_CTL_REGP ((volatile ddrcReg_PHY_ADDR_CTL_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_PHY_ADDR_CTL_REG_OFFSET))
420
421/* @todo These SS definitions are duplicates of ones below */
422
423#define ddrcReg_PHY_ADDR_SS_CTRL_ENABLE 0x00000001
424#define ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_MASK 0xFFFF0000
425#define ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_SHIFT 16
426#define ddrcReg_PHY_ADDR_SS_CFG_MIN_CYCLE_PER_TICK 10 /* Higher the value, lower the SS modulation frequency */
427#define ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_MASK 0x0000FFFF
428#define ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_SHIFT 0
429
430/* ----------------------------------------------------- */
431
432#define ddrcReg_PHY_ADDR_CTL_REVISION_MAJOR_SHIFT 8
433#define ddrcReg_PHY_ADDR_CTL_REVISION_MAJOR_MASK (0xff << ddrcReg_PHY_ADDR_CTL_REVISION_MAJOR_SHIFT)
434
435#define ddrcReg_PHY_ADDR_CTL_REVISION_MINOR_SHIFT 0
436#define ddrcReg_PHY_ADDR_CTL_REVISION_MINOR_MASK (0xff << ddrcReg_PHY_ADDR_CTL_REVISION_MINOR_SHIFT)
437
438/* ----------------------------------------------------- */
439
440#define ddrcReg_PHY_ADDR_CTL_CLK_PM_CTL_DDR_CLK_DISABLE (1 << 0)
441
442/* ----------------------------------------------------- */
443
444#define ddrcReg_PHY_ADDR_CTL_PLL_STATUS_LOCKED (1 << 0)
445
446/* ----------------------------------------------------- */
447
448#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_DIV2_CLK_RESET (1 << 31)
449
450#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_TEST_SEL_SHIFT 17
451#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_TEST_SEL_MASK (0x1f << ddrcReg_PHY_ADDR_CTL_PLL_CFG_TEST_SEL_SHIFT)
452
453#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_TEST_ENABLE (1 << 16)
454
455#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_BGAP_ADJ_SHIFT 12
456#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_BGAP_ADJ_MASK (0xf << ddrcReg_PHY_ADDR_CTL_PLL_CFG_BGAP_ADJ_SHIFT)
457
458#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_VCO_RNG (1 << 7)
459#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_CH1_PWRDWN (1 << 6)
460#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_BYPASS_ENABLE (1 << 5)
461#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_CLKOUT_ENABLE (1 << 4)
462#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_D_RESET (1 << 3)
463#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_A_RESET (1 << 2)
464#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_PWRDWN (1 << 0)
465
466/* ----------------------------------------------------- */
467
468#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_DITHER_MFB (1 << 26)
469#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_PWRDWN (1 << 25)
470
471#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_MODE_SHIFT 20
472#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_MODE_MASK (0x7 << ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_MODE_SHIFT)
473
474#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_INT_SHIFT 8
475#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_INT_MASK (0x1ff << ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_INT_SHIFT)
476
477#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P2_SHIFT 4
478#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P2_MASK (0xf << ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P2_SHIFT)
479
480#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P1_SHIFT 0
481#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P1_MASK (0xf << ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P1_SHIFT)
482
483/* ----------------------------------------------------- */
484
485#define ddrcReg_PHY_ADDR_CTL_PLL_DIV_M1_SHIFT 24
486#define ddrcReg_PHY_ADDR_CTL_PLL_DIV_M1_MASK (0xff << ddrcReg_PHY_ADDR_CTL_PLL_DIV_M1_SHIFT)
487
488#define ddrcReg_PHY_ADDR_CTL_PLL_DIV_FRAC_SHIFT 0
489#define ddrcReg_PHY_ADDR_CTL_PLL_DIV_FRAC_MASK (0xffffff << ddrcReg_PHY_ADDR_CTL_PLL_DIV_FRAC_SHIFT)
490
491/* ----------------------------------------------------- */
492
493#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_TESTA_SHIFT 30
494#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_TESTA_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_TESTA_SHIFT)
495
496#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XS_SHIFT 27
497#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XS_MASK (0x7 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XS_SHIFT)
498
499#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XF_SHIFT 24
500#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XF_MASK (0x7 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XF_SHIFT)
501
502#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_LPF_BW_SHIFT 22
503#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_LPF_BW_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_LPF_BW_SHIFT)
504
505#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_LF_ORDER (0x1 << 21)
506
507#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CN_SHIFT 19
508#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CN_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CN_SHIFT)
509
510#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RN_SHIFT 17
511#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RN_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RN_SHIFT)
512
513#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CP_SHIFT 15
514#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CP_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CP_SHIFT)
515
516#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CZ_SHIFT 13
517#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CZ_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CZ_SHIFT)
518
519#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RZ_SHIFT 10
520#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RZ_MASK (0x7 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RZ_SHIFT)
521
522#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICPX_SHIFT 5
523#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICPX_MASK (0x1f << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICPX_SHIFT)
524
525#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICP_OFF_SHIFT 0
526#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICP_OFF_MASK (0x1f << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICP_OFF_SHIFT)
527
528/* ----------------------------------------------------- */
529#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_PTAP_ADJ_SHIFT 4
530#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_PTAP_ADJ_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL2_PTAP_ADJ_SHIFT)
531
532#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_CTAP_ADJ_SHIFT 2
533#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_CTAP_ADJ_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL2_CTAP_ADJ_SHIFT)
534
535#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_LOWCUR_ENABLE (0x1 << 1)
536#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_BIASIN_ENABLE (0x1 << 0)
537
538/* ----------------------------------------------------- */
539
540#define ddrcReg_PHY_ADDR_CTL_PLL_SS_EN_ENABLE (0x1 << 0)
541
542/* ----------------------------------------------------- */
543
544#define ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_CYC_PER_TICK_SHIFT 16
545#define ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_CYC_PER_TICK_MASK (0xffff << ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_CYC_PER_TICK_SHIFT)
546
547#define ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_NDIV_AMP_SHIFT 0
548#define ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_NDIV_AMP_MASK (0xffff << ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_NDIV_AMP_SHIFT)
549
550/* ----------------------------------------------------- */
551
552#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_FORCE (1 << 20)
553#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_ENABLE (1 << 16)
554
555#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_FALL_SHIFT 12
556#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_FALL_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_FALL_SHIFT)
557
558#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_RISE_SHIFT 8
559#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_RISE_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_RISE_SHIFT)
560
561#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_STEP_SHIFT 0
562#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_STEP_MASK (0x3f << ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_STEP_SHIFT)
563
564/* ----------------------------------------------------- */
565
566#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_ENABLE (1 << 16)
567
568#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_FALL_SHIFT 12
569#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_FALL_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_FALL_SHIFT)
570
571#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_RISE_SHIFT 8
572#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_RISE_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_RISE_SHIFT)
573
574#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_STEP_SHIFT 0
575#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_STEP_MASK (0x3f << ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_STEP_SHIFT)
576
577/* ----------------------------------------------------- */
578
579#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_ENABLE (1u << 31)
580#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_RXENB_DISABLE (1 << 8)
581#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CTL_IDDQ_DISABLE (1 << 6)
582#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CTL_REB_DISABLE (1 << 5)
583#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CTL_OEB_DISABLE (1 << 4)
584#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CKE_IDDQ_DISABLE (1 << 2)
585#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CKE_REB_DISABLE (1 << 1)
586#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CKE_OEB_DISABLE (1 << 0)
587
588/* ----------------------------------------------------- */
589
590#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_PD_DONE (1 << 30)
591#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ND_DONE (1 << 29)
592#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_SAMPLE_DONE (1 << 28)
593#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_SAMPLE_AUTO_ENABLE (1 << 27)
594#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_SAMPLE_ENABLE (1 << 26)
595#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_OVR_ENABLE (1 << 25)
596#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_OVR_ENABLE (1 << 24)
597
598#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_PD_SHIFT 20
599#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_PD_MASK (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_PD_SHIFT)
600
601#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ND_SHIFT 16
602#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ND_MASK (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_ND_SHIFT)
603
604#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_PD_SHIFT 12
605#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_PD_MASK (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_PD_SHIFT)
606
607#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_ND_SHIFT 8
608#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_ND_MASK (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_ND_SHIFT)
609
610#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_PD_SHIFT 4
611#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_PD_MASK (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_PD_SHIFT)
612
613#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_ND_SHIFT 0
614#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_ND_MASK (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_ND_SHIFT)
615
616/* ----------------------------------------------------- */
617
618#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_RT60B (1 << 4)
619#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_SEL_SSTL18 (1 << 3)
620#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_SELTXDRV_CI (1 << 2)
621#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_SELRXDRV (1 << 1)
622#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_SLEW (1 << 0)
623
624/* ----------------------------------------------------- */
625
626#define ddrcReg_PHY_ADDR_CTL_CLK_RGLTR_CTL_PWR_HALF (1 << 1)
627#define ddrcReg_PHY_ADDR_CTL_CLK_RGLTR_CTL_PWR_OFF (1 << 0)
628
629/* -------------------------------------------------------------------- */
630/* -------------------------------------------------------------------- */
631/* Broadcom DDR23 PHY Byte Lane register definitions */
632/* -------------------------------------------------------------------- */
633/* -------------------------------------------------------------------- */
634
635#define ddrcReg_PHY_BYTE_LANE_CNT 2
636#define ddrcReg_PHY_BYTE_LANE_MAX (ddrcReg_CTLR_BYTE_LANE_CNT - 1)
637
638#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_CNT 8
639
640 typedef struct {
641 uint32_t revision;
642 uint32_t vdlCalibrate;
643 uint32_t vdlStatus;
644 REG32_RSVD(0x000c, 0x0010);
645 uint32_t vdlOverride[ddrcReg_PHY_BYTE_LANE_VDL_OVR_CNT];
646 uint32_t readCtl;
647 uint32_t readStatus;
648 uint32_t readClear;
649 uint32_t padIdleCtl;
650 uint32_t padDriveCtl;
651 uint32_t padClkCtl;
652 uint32_t writeCtl;
653 uint32_t clkRegCtl;
654 } ddrcReg_PHY_BYTE_LANE_REG_t;
655
656/* There are 2 instances of the byte Lane registers, one for each byte lane. */
657#define ddrcReg_PHY_BYTE_LANE_1_REG_OFFSET 0x0500
658#define ddrcReg_PHY_BYTE_LANE_2_REG_OFFSET 0x0600
659
660#define ddrcReg_PHY_BYTE_LANE_1_REGP ((volatile ddrcReg_PHY_BYTE_LANE_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_PHY_BYTE_LANE_1_REG_OFFSET))
661#define ddrcReg_PHY_BYTE_LANE_2_REGP ((volatile ddrcReg_PHY_BYTE_LANE_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_PHY_BYTE_LANE_2_REG_OFFSET))
662
663/* ----------------------------------------------------- */
664
665#define ddrcReg_PHY_BYTE_LANE_REVISION_MAJOR_SHIFT 8
666#define ddrcReg_PHY_BYTE_LANE_REVISION_MAJOR_MASK (0xff << ddrcReg_PHY_BYTE_LANE_REVISION_MAJOR_SHIFT)
667
668#define ddrcReg_PHY_BYTE_LANE_REVISION_MINOR_SHIFT 0
669#define ddrcReg_PHY_BYTE_LANE_REVISION_MINOR_MASK (0xff << ddrcReg_PHY_BYTE_LANE_REVISION_MINOR_SHIFT)
670
671/* ----------------------------------------------------- */
672
673#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_CLK_2CYCLE (1 << 4)
674#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_CLK_1CYCLE (0 << 4)
675
676#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_TEST (1 << 3)
677#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_ALWAYS (1 << 2)
678#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_ONCE (1 << 1)
679#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_FAST (1 << 0)
680
681/* ----------------------------------------------------- */
682
683/* The byte lane VDL status calibTotal[9:0] is comprised of [9:4] step value, [3:2] fine fall */
684/* and [1:0] fine rise. Note that calibTotal[9:0] is located at bit 4 in the VDL status */
685/* register. The fine rise and fall are no longer used, so add some definitions for just */
686/* the step setting to simplify things. */
687
688#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_STEP_SHIFT 8
689#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_STEP_MASK (0x3f << ddrcReg_PHY_BYTE_LANE_VDL_STATUS_STEP_SHIFT)
690
691#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_TOTAL_SHIFT 4
692#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_TOTAL_MASK (0x3ff << ddrcReg_PHY_BYTE_LANE_VDL_STATUS_TOTAL_SHIFT)
693
694#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_LOCK (1 << 1)
695#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_IDLE (1 << 0)
696
697/* ----------------------------------------------------- */
698
699#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_ENABLE (1 << 16)
700
701#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_FALL_SHIFT 12
702#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_FALL_MASK (0x3 << ddrcReg_PHY_BYTE_LANE_VDL_OVR_FALL_SHIFT)
703
704#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_RISE_SHIFT 8
705#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_RISE_MASK (0x3 << ddrcReg_PHY_BYTE_LANE_VDL_OVR_RISE_SHIFT)
706
707#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_STEP_SHIFT 0
708#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_STEP_MASK (0x3f << ddrcReg_PHY_BYTE_LANE_VDL_OVR_STEP_SHIFT)
709
710#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_STATIC_READ_DQS_P 0
711#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_STATIC_READ_DQS_N 1
712#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_STATIC_READ_EN 2
713#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_STATIC_WRITE_DQ_DQM 3
714#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_DYNAMIC_READ_DQS_P 4
715#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_DYNAMIC_READ_DQS_N 5
716#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_DYNAMIC_READ_EN 6
717#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_DYNAMIC_WRITE_DQ_DQM 7
718
719/* ----------------------------------------------------- */
720
721#define ddrcReg_PHY_BYTE_LANE_READ_CTL_DELAY_SHIFT 8
722#define ddrcReg_PHY_BYTE_LANE_READ_CTL_DELAY_MASK (0x3 << ddrcReg_PHY_BYTE_LANE_READ_CTL_DELAY_SHIFT)
723
724#define ddrcReg_PHY_BYTE_LANE_READ_CTL_DQ_ODT_ENABLE (1 << 3)
725#define ddrcReg_PHY_BYTE_LANE_READ_CTL_DQ_ODT_ADJUST (1 << 2)
726#define ddrcReg_PHY_BYTE_LANE_READ_CTL_RD_ODT_ENABLE (1 << 1)
727#define ddrcReg_PHY_BYTE_LANE_READ_CTL_RD_ODT_ADJUST (1 << 0)
728
729/* ----------------------------------------------------- */
730
731#define ddrcReg_PHY_BYTE_LANE_READ_STATUS_ERROR_SHIFT 0
732#define ddrcReg_PHY_BYTE_LANE_READ_STATUS_ERROR_MASK (0xf << ddrcReg_PHY_BYTE_LANE_READ_STATUS_ERROR_SHIFT)
733
734/* ----------------------------------------------------- */
735
736#define ddrcReg_PHY_BYTE_LANE_READ_CLEAR_STATUS (1 << 0)
737
738/* ----------------------------------------------------- */
739
740#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_ENABLE (1u << 31)
741#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DM_RXENB_DISABLE (1 << 19)
742#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DM_IDDQ_DISABLE (1 << 18)
743#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DM_REB_DISABLE (1 << 17)
744#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DM_OEB_DISABLE (1 << 16)
745#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQ_RXENB_DISABLE (1 << 15)
746#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQ_IDDQ_DISABLE (1 << 14)
747#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQ_REB_DISABLE (1 << 13)
748#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQ_OEB_DISABLE (1 << 12)
749#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_READ_ENB_RXENB_DISABLE (1 << 11)
750#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_READ_ENB_IDDQ_DISABLE (1 << 10)
751#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_READ_ENB_REB_DISABLE (1 << 9)
752#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_READ_ENB_OEB_DISABLE (1 << 8)
753#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQS_RXENB_DISABLE (1 << 7)
754#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQS_IDDQ_DISABLE (1 << 6)
755#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQS_REB_DISABLE (1 << 5)
756#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQS_OEB_DISABLE (1 << 4)
757#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_CLK_RXENB_DISABLE (1 << 3)
758#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_CLK_IDDQ_DISABLE (1 << 2)
759#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_CLK_REB_DISABLE (1 << 1)
760#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_CLK_OEB_DISABLE (1 << 0)
761
762/* ----------------------------------------------------- */
763
764#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_RT60B_DDR_READ_ENB (1 << 5)
765#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_RT60B (1 << 4)
766#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_SEL_SSTL18 (1 << 3)
767#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_SELTXDRV_CI (1 << 2)
768#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_SELRXDRV (1 << 1)
769#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_SLEW (1 << 0)
770
771/* ----------------------------------------------------- */
772
773#define ddrcReg_PHY_BYTE_LANE_PAD_CLK_CTL_DISABLE (1 << 0)
774
775/* ----------------------------------------------------- */
776
777#define ddrcReg_PHY_BYTE_LANE_WRITE_CTL_PREAMBLE_DDR3 (1 << 0)
778
779/* ----------------------------------------------------- */
780
781#define ddrcReg_PHY_BYTE_LANE_CLK_REG_CTL_PWR_HALF (1 << 1)
782#define ddrcReg_PHY_BYTE_LANE_CLK_REG_CTL_PWR_OFF (1 << 0)
783
784/*********************************************************************/
785/* ARM PL341 DDRC to Broadcom DDR23 PHY glue register definitions */
786/*********************************************************************/
787
788 typedef struct {
789 uint32_t cfg;
790 uint32_t actMonCnt;
791 uint32_t ctl;
792 uint32_t lbistCtl;
793 uint32_t lbistSeed;
794 uint32_t lbistStatus;
795 uint32_t tieOff;
796 uint32_t actMonClear;
797 uint32_t status;
798 uint32_t user;
799 } ddrcReg_CTLR_PHY_GLUE_REG_t;
800
801#define ddrcReg_CTLR_PHY_GLUE_OFFSET 0x0700
802#define ddrcReg_CTLR_PHY_GLUE_REGP ((volatile ddrcReg_CTLR_PHY_GLUE_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_CTLR_PHY_GLUE_OFFSET))
803
804/* ----------------------------------------------------- */
805
806/* DDR2 / AXI block phase alignment interrupt control */
807#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT 18
808#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_MASK (0x3 << ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT)
809#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_OFF (0 << ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT)
810#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_ON_TIGHT (1 << ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT)
811#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_ON_MEDIUM (2 << ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT)
812#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_ON_LOOSE (3 << ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT)
813
814#define ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_SHIFT 17
815#define ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_MASK (1 << ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_SHIFT)
816#define ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_DIFFERENTIAL (0 << ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_SHIFT)
817#define ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_CMOS (1 << ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_SHIFT)
818
819#define ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHIFT 16
820#define ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_MASK (1 << ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHIFT)
821#define ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_DEEP (0 << ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHIFT)
822#define ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHALLOW (1 << ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHIFT)
823#define ddrcReg_CTLR_PHY_GLUE_CFG_HW_FIXED_ALIGNMENT_DISABLED ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHALLOW
824
825#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_SHIFT 15
826#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_MASK (1 << ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_SHIFT)
827#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_BP134 (0 << ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_SHIFT)
828#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_PL301 (1 << ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_SHIFT)
829#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_REGISTERED ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_PL301
830
831/* Software control of PHY VDL updates from control register settings. Bit 13 enables the use of Bit 14. */
832/* If software control is not enabled, then updates occur when a refresh command is issued by the hardware */
833/* controller. If 2 chips selects are being used, then software control must be enabled. */
834#define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_VDL_UPDATE_SW_CTL_LOAD (1 << 14)
835#define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_VDL_UPDATE_SW_CTL_ENABLE (1 << 13)
836
837/* Use these to bypass a pipeline stage. By default the ADDR is off but the BYTE LANE in / out are on. */
838#define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_ADDR_CTL_IN_BYPASS_PIPELINE_STAGE (1 << 12)
839#define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_BYTE_LANE_IN_BYPASS_PIPELINE_STAGE (1 << 11)
840#define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_BYTE_LANE_OUT_BYPASS_PIPELINE_STAGE (1 << 10)
841
842/* Chip select count */
843#define ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_SHIFT 9
844#define ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_MASK (1 << ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_SHIFT)
845#define ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_1 (0 << ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_SHIFT)
846#define ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_2 (1 << ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_SHIFT)
847
848#define ddrcReg_CTLR_PHY_GLUE_CFG_CLK_SHIFT 8
849#define ddrcReg_CTLR_PHY_GLUE_CFG_CLK_ASYNC (0 << ddrcReg_CTLR_PHY_GLUE_CFG_CLK_SHIFT)
850#define ddrcReg_CTLR_PHY_GLUE_CFG_CLK_SYNC (1 << ddrcReg_CTLR_PHY_GLUE_CFG_CLK_SHIFT)
851
852#define ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_SHIFT 7
853#define ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_LOW (0 << ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_SHIFT)
854#define ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_HIGH (1 << ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_SHIFT)
855
856#define ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_SHIFT 6
857#define ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_LOW (0 << ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_SHIFT)
858#define ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_HIGH (1 << ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_SHIFT)
859
860#define ddrcReg_CTLR_PHY_GLUE_CFG_CAS_LATENCY_SHIFT 0
861#define ddrcReg_CTLR_PHY_GLUE_CFG_CAS_LATENCY_MASK (0x7 << ddrcReg_CTLR_PHY_GLUE_CFG_CAS_LATENCY_SHIFT)
862
863/* ----------------------------------------------------- */
864#define ddrcReg_CTLR_PHY_GLUE_STATUS_PHASE_SHIFT 0
865#define ddrcReg_CTLR_PHY_GLUE_STATUS_PHASE_MASK (0x7f << ddrcReg_CTLR_PHY_GLUE_STATUS_PHASE_SHIFT)
866
867/* ---- Public Function Prototypes --------------------------------------- */
868
869#ifdef __cplusplus
870} /* end extern "C" */
871#endif
872#endif /* DDRC_REG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h b/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h
new file mode 100644
index 00000000000..d67e2f8c22d
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h
@@ -0,0 +1,145 @@
1/*****************************************************************************
2* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/****************************************************************************/
16/**
17* @file dmacHw_priv.h
18*
19* @brief Private Definitions for low level DMA driver
20*
21*/
22/****************************************************************************/
23
24#ifndef _DMACHW_PRIV_H
25#define _DMACHW_PRIV_H
26
27#include <csp/stdint.h>
28
29/* Data type for DMA Link List Item */
30typedef struct {
31 uint32_t sar; /* Source Address Register.
32 Address must be aligned to CTLx.SRC_TR_WIDTH. */
33 uint32_t dar; /* Destination Address Register.
34 Address must be aligned to CTLx.DST_TR_WIDTH. */
35 uint32_t llpPhy; /* LLP contains the physical address of the next descriptor for block chaining using linked lists.
36 Address MUST be aligned to a 32-bit boundary. */
37 dmacHw_REG64_t ctl; /* Control Register. 64 bits */
38 uint32_t sstat; /* Source Status Register */
39 uint32_t dstat; /* Destination Status Register */
40 uint32_t devCtl; /* Device specific control information */
41 uint32_t llp; /* LLP contains the virtual address of the next descriptor for block chaining using linked lists. */
42} dmacHw_DESC_t;
43
44/*
45 * Descriptor ring pointers
46 */
47typedef struct {
48 int num; /* Number of link items */
49 dmacHw_DESC_t *pHead; /* Head of descriptor ring (for writing) */
50 dmacHw_DESC_t *pTail; /* Tail of descriptor ring (for reading) */
51 dmacHw_DESC_t *pProg; /* Descriptor to program the channel (for programming the channel register) */
52 dmacHw_DESC_t *pEnd; /* End of current descriptor chain */
53 dmacHw_DESC_t *pFree; /* Descriptor to free memory (freeing dynamic memory) */
54 uint32_t virt2PhyOffset; /* Virtual to physical address offset for the descriptor ring */
55} dmacHw_DESC_RING_t;
56
57/*
58 * DMA channel control block
59 */
60typedef struct {
61 uint32_t module; /* DMA controller module (0-1) */
62 uint32_t channel; /* DMA channel (0-7) */
63 volatile uint32_t varDataStarted; /* Flag indicating variable data channel is enabled */
64 volatile uint32_t descUpdated; /* Flag to indicate descriptor update is complete */
65 void *userData; /* Channel specifc user data */
66} dmacHw_CBLK_t;
67
68#define dmacHw_ASSERT(a) if (!(a)) while (1)
69#define dmacHw_MAX_CHANNEL_COUNT 16
70#define dmacHw_FREE_USER_MEMORY 0xFFFFFFFF
71#define dmacHw_DESC_FREE dmacHw_REG_CTL_DONE
72#define dmacHw_DESC_INIT ((dmacHw_DESC_t *) 0xFFFFFFFF)
73#define dmacHw_MAX_BLOCKSIZE 4064
74#define dmacHw_GET_DESC_RING(addr) (dmacHw_DESC_RING_t *)(addr)
75#define dmacHw_ADDRESS_MASK(byte) ((byte) - 1)
76#define dmacHw_NEXT_DESC(rp, dp) ((rp)->dp = (dmacHw_DESC_t *)(rp)->dp->llp)
77#define dmacHw_HANDLE_TO_CBLK(handle) ((dmacHw_CBLK_t *) (handle))
78#define dmacHw_CBLK_TO_HANDLE(cblkp) ((dmacHw_HANDLE_t) (cblkp))
79#define dmacHw_DST_IS_MEMORY(tt) (((tt) == dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM) || ((tt) == dmacHw_TRANSFER_TYPE_MEM_TO_MEM)) ? 1 : 0
80
81/****************************************************************************/
82/**
83* @brief Get next available transaction width
84*
85*
86* @return On success : Next available transaction width
87* On failure : dmacHw_TRANSACTION_WIDTH_8
88*
89* @note
90* None
91*/
92/****************************************************************************/
93static inline dmacHw_TRANSACTION_WIDTH_e dmacHw_GetNextTrWidth(dmacHw_TRANSACTION_WIDTH_e tw /* [ IN ] Current transaction width */
94 ) {
95 if (tw & dmacHw_REG_CTL_SRC_TR_WIDTH_MASK) {
96 return ((tw >> dmacHw_REG_CTL_SRC_TR_WIDTH_SHIFT) -
97 1) << dmacHw_REG_CTL_SRC_TR_WIDTH_SHIFT;
98 } else if (tw & dmacHw_REG_CTL_DST_TR_WIDTH_MASK) {
99 return ((tw >> dmacHw_REG_CTL_DST_TR_WIDTH_SHIFT) -
100 1) << dmacHw_REG_CTL_DST_TR_WIDTH_SHIFT;
101 }
102
103 /* Default return */
104 return dmacHw_SRC_TRANSACTION_WIDTH_8;
105}
106
107/****************************************************************************/
108/**
109* @brief Get number of bytes per transaction
110*
111* @return Number of bytes per transaction
112*
113*
114* @note
115* None
116*/
117/****************************************************************************/
118static inline int dmacHw_GetTrWidthInBytes(dmacHw_TRANSACTION_WIDTH_e tw /* [ IN ] Transaction width */
119 ) {
120 int width = 1;
121 switch (tw) {
122 case dmacHw_SRC_TRANSACTION_WIDTH_8:
123 width = 1;
124 break;
125 case dmacHw_SRC_TRANSACTION_WIDTH_16:
126 case dmacHw_DST_TRANSACTION_WIDTH_16:
127 width = 2;
128 break;
129 case dmacHw_SRC_TRANSACTION_WIDTH_32:
130 case dmacHw_DST_TRANSACTION_WIDTH_32:
131 width = 4;
132 break;
133 case dmacHw_SRC_TRANSACTION_WIDTH_64:
134 case dmacHw_DST_TRANSACTION_WIDTH_64:
135 width = 8;
136 break;
137 default:
138 dmacHw_ASSERT(0);
139 }
140
141 /* Default transaction width */
142 return width;
143}
144
145#endif /* _DMACHW_PRIV_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h
new file mode 100644
index 00000000000..f1ecf96f2da
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h
@@ -0,0 +1,406 @@
1/*****************************************************************************
2* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/****************************************************************************/
16/**
17* @file dmacHw_reg.h
18*
19* @brief Definitions for low level DMA registers
20*
21*/
22/****************************************************************************/
23
24#ifndef _DMACHW_REG_H
25#define _DMACHW_REG_H
26
27#include <csp/stdint.h>
28#include <mach/csp/mm_io.h>
29
30/* Data type for 64 bit little endian register */
31typedef struct {
32 volatile uint32_t lo; /* Lower 32 bit in little endian mode */
33 volatile uint32_t hi; /* Upper 32 bit in little endian mode */
34} dmacHw_REG64_t;
35
36/* Data type representing DMA channel registers */
37typedef struct {
38 dmacHw_REG64_t ChannelSar; /* Source Address Register. 64 bits (upper 32 bits are reserved)
39 Address must be aligned to CTLx.SRC_TR_WIDTH.
40 */
41 dmacHw_REG64_t ChannelDar; /* Destination Address Register.64 bits (upper 32 bits are reserved)
42 Address must be aligned to CTLx.DST_TR_WIDTH.
43 */
44 dmacHw_REG64_t ChannelLlp; /* Link List Pointer.64 bits (upper 32 bits are reserved)
45 LLP contains the pointer to the next LLI for block chaining using linked lists.
46 If LLPis set to 0x0, then transfers using linked lists are not enabled.
47 Address MUST be aligned to a 32-bit boundary.
48 */
49 dmacHw_REG64_t ChannelCtl; /* Control Register. 64 bits */
50 dmacHw_REG64_t ChannelSstat; /* Source Status Register */
51 dmacHw_REG64_t ChannelDstat; /* Destination Status Register */
52 dmacHw_REG64_t ChannelSstatAddr; /* Source Status Address Register */
53 dmacHw_REG64_t ChannelDstatAddr; /* Destination Status Address Register */
54 dmacHw_REG64_t ChannelConfig; /* Channel Configuration Register */
55 dmacHw_REG64_t SrcGather; /* Source gather register */
56 dmacHw_REG64_t DstScatter; /* Destination scatter register */
57} dmacHw_CH_REG_t;
58
59/* Data type for RAW interrupt status registers */
60typedef struct {
61 dmacHw_REG64_t RawTfr; /* Raw Status for IntTfr Interrupt */
62 dmacHw_REG64_t RawBlock; /* Raw Status for IntBlock Interrupt */
63 dmacHw_REG64_t RawSrcTran; /* Raw Status for IntSrcTran Interrupt */
64 dmacHw_REG64_t RawDstTran; /* Raw Status for IntDstTran Interrupt */
65 dmacHw_REG64_t RawErr; /* Raw Status for IntErr Interrupt */
66} dmacHw_INT_RAW_t;
67
68/* Data type for interrupt status registers */
69typedef struct {
70 dmacHw_REG64_t StatusTfr; /* Status for IntTfr Interrupt */
71 dmacHw_REG64_t StatusBlock; /* Status for IntBlock Interrupt */
72 dmacHw_REG64_t StatusSrcTran; /* Status for IntSrcTran Interrupt */
73 dmacHw_REG64_t StatusDstTran; /* Status for IntDstTran Interrupt */
74 dmacHw_REG64_t StatusErr; /* Status for IntErr Interrupt */
75} dmacHw_INT_STATUS_t;
76
77/* Data type for interrupt mask registers*/
78typedef struct {
79 dmacHw_REG64_t MaskTfr; /* Mask for IntTfr Interrupt */
80 dmacHw_REG64_t MaskBlock; /* Mask for IntBlock Interrupt */
81 dmacHw_REG64_t MaskSrcTran; /* Mask for IntSrcTran Interrupt */
82 dmacHw_REG64_t MaskDstTran; /* Mask for IntDstTran Interrupt */
83 dmacHw_REG64_t MaskErr; /* Mask for IntErr Interrupt */
84} dmacHw_INT_MASK_t;
85
86/* Data type for interrupt clear registers */
87typedef struct {
88 dmacHw_REG64_t ClearTfr; /* Clear for IntTfr Interrupt */
89 dmacHw_REG64_t ClearBlock; /* Clear for IntBlock Interrupt */
90 dmacHw_REG64_t ClearSrcTran; /* Clear for IntSrcTran Interrupt */
91 dmacHw_REG64_t ClearDstTran; /* Clear for IntDstTran Interrupt */
92 dmacHw_REG64_t ClearErr; /* Clear for IntErr Interrupt */
93 dmacHw_REG64_t StatusInt; /* Status for each interrupt type */
94} dmacHw_INT_CLEAR_t;
95
96/* Data type for software handshaking registers */
97typedef struct {
98 dmacHw_REG64_t ReqSrcReg; /* Source Software Transaction Request Register */
99 dmacHw_REG64_t ReqDstReg; /* Destination Software Transaction Request Register */
100 dmacHw_REG64_t SglReqSrcReg; /* Single Source Transaction Request Register */
101 dmacHw_REG64_t SglReqDstReg; /* Single Destination Transaction Request Register */
102 dmacHw_REG64_t LstSrcReg; /* Last Source Transaction Request Register */
103 dmacHw_REG64_t LstDstReg; /* Last Destination Transaction Request Register */
104} dmacHw_SW_HANDSHAKE_t;
105
106/* Data type for misc. registers */
107typedef struct {
108 dmacHw_REG64_t DmaCfgReg; /* DMA Configuration Register */
109 dmacHw_REG64_t ChEnReg; /* DMA Channel Enable Register */
110 dmacHw_REG64_t DmaIdReg; /* DMA ID Register */
111 dmacHw_REG64_t DmaTestReg; /* DMA Test Register */
112 dmacHw_REG64_t Reserved0; /* Reserved */
113 dmacHw_REG64_t Reserved1; /* Reserved */
114 dmacHw_REG64_t CompParm6; /* Component Parameter 6 */
115 dmacHw_REG64_t CompParm5; /* Component Parameter 5 */
116 dmacHw_REG64_t CompParm4; /* Component Parameter 4 */
117 dmacHw_REG64_t CompParm3; /* Component Parameter 3 */
118 dmacHw_REG64_t CompParm2; /* Component Parameter 2 */
119 dmacHw_REG64_t CompParm1; /* Component Parameter 1 */
120 dmacHw_REG64_t CompId; /* Compoent ID */
121} dmacHw_MISC_t;
122
123/* Base registers */
124#define dmacHw_0_MODULE_BASE_ADDR (char *) MM_IO_BASE_DMA0 /* DMAC 0 module's base address */
125#define dmacHw_1_MODULE_BASE_ADDR (char *) MM_IO_BASE_DMA1 /* DMAC 1 module's base address */
126
127extern uint32_t dmaChannelCount_0;
128extern uint32_t dmaChannelCount_1;
129
130/* Define channel specific registers */
131#define dmacHw_CHAN_BASE(module, chan) ((dmacHw_CH_REG_t *) ((char *)((module) ? dmacHw_1_MODULE_BASE_ADDR : dmacHw_0_MODULE_BASE_ADDR) + ((chan) * sizeof(dmacHw_CH_REG_t))))
132
133/* Raw interrupt status registers */
134#define dmacHw_REG_INT_RAW_BASE(module) ((char *)dmacHw_CHAN_BASE((module), ((module) ? dmaChannelCount_1 : dmaChannelCount_0)))
135#define dmacHw_REG_INT_RAW_TRAN(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawTfr.lo)
136#define dmacHw_REG_INT_RAW_BLOCK(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawBlock.lo)
137#define dmacHw_REG_INT_RAW_STRAN(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawSrcTran.lo)
138#define dmacHw_REG_INT_RAW_DTRAN(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawDstTran.lo)
139#define dmacHw_REG_INT_RAW_ERROR(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawErr.lo)
140
141/* Interrupt status registers */
142#define dmacHw_REG_INT_STAT_BASE(module) ((char *)(dmacHw_REG_INT_RAW_BASE((module)) + sizeof(dmacHw_INT_RAW_t)))
143#define dmacHw_REG_INT_STAT_TRAN(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusTfr.lo)
144#define dmacHw_REG_INT_STAT_BLOCK(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusBlock.lo)
145#define dmacHw_REG_INT_STAT_STRAN(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusSrcTran.lo)
146#define dmacHw_REG_INT_STAT_DTRAN(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusDstTran.lo)
147#define dmacHw_REG_INT_STAT_ERROR(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusErr.lo)
148
149/* Interrupt status registers */
150#define dmacHw_REG_INT_MASK_BASE(module) ((char *)(dmacHw_REG_INT_STAT_BASE((module)) + sizeof(dmacHw_INT_STATUS_t)))
151#define dmacHw_REG_INT_MASK_TRAN(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskTfr.lo)
152#define dmacHw_REG_INT_MASK_BLOCK(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskBlock.lo)
153#define dmacHw_REG_INT_MASK_STRAN(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskSrcTran.lo)
154#define dmacHw_REG_INT_MASK_DTRAN(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskDstTran.lo)
155#define dmacHw_REG_INT_MASK_ERROR(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskErr.lo)
156
157/* Interrupt clear registers */
158#define dmacHw_REG_INT_CLEAR_BASE(module) ((char *)(dmacHw_REG_INT_MASK_BASE((module)) + sizeof(dmacHw_INT_MASK_t)))
159#define dmacHw_REG_INT_CLEAR_TRAN(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearTfr.lo)
160#define dmacHw_REG_INT_CLEAR_BLOCK(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearBlock.lo)
161#define dmacHw_REG_INT_CLEAR_STRAN(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearSrcTran.lo)
162#define dmacHw_REG_INT_CLEAR_DTRAN(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearDstTran.lo)
163#define dmacHw_REG_INT_CLEAR_ERROR(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearErr.lo)
164#define dmacHw_REG_INT_STATUS(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->StatusInt.lo)
165
166/* Software handshaking registers */
167#define dmacHw_REG_SW_HS_BASE(module) ((char *)(dmacHw_REG_INT_CLEAR_BASE((module)) + sizeof(dmacHw_INT_CLEAR_t)))
168#define dmacHw_REG_SW_HS_SRC_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->ReqSrcReg.lo)
169#define dmacHw_REG_SW_HS_DST_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->ReqDstReg.lo)
170#define dmacHw_REG_SW_HS_SRC_SGL_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->SglReqSrcReg.lo)
171#define dmacHw_REG_SW_HS_DST_SGL_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->SglReqDstReg.lo)
172#define dmacHw_REG_SW_HS_SRC_LST_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->LstSrcReg.lo)
173#define dmacHw_REG_SW_HS_DST_LST_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->LstDstReg.lo)
174
175/* Miscellaneous registers */
176#define dmacHw_REG_MISC_BASE(module) ((char *)(dmacHw_REG_SW_HS_BASE((module)) + sizeof(dmacHw_SW_HANDSHAKE_t)))
177#define dmacHw_REG_MISC_CFG(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaCfgReg.lo)
178#define dmacHw_REG_MISC_CH_ENABLE(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->ChEnReg.lo)
179#define dmacHw_REG_MISC_ID(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaIdReg.lo)
180#define dmacHw_REG_MISC_TEST(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaTestReg.lo)
181#define dmacHw_REG_MISC_COMP_PARAM1_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm1.lo)
182#define dmacHw_REG_MISC_COMP_PARAM1_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm1.hi)
183#define dmacHw_REG_MISC_COMP_PARAM2_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm2.lo)
184#define dmacHw_REG_MISC_COMP_PARAM2_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm2.hi)
185#define dmacHw_REG_MISC_COMP_PARAM3_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm3.lo)
186#define dmacHw_REG_MISC_COMP_PARAM3_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm3.hi)
187#define dmacHw_REG_MISC_COMP_PARAM4_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm4.lo)
188#define dmacHw_REG_MISC_COMP_PARAM4_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm4.hi)
189#define dmacHw_REG_MISC_COMP_PARAM5_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm5.lo)
190#define dmacHw_REG_MISC_COMP_PARAM5_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm5.hi)
191#define dmacHw_REG_MISC_COMP_PARAM6_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm6.lo)
192#define dmacHw_REG_MISC_COMP_PARAM6_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm6.hi)
193
194/* Channel control registers */
195#define dmacHw_REG_SAR(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelSar.lo)
196#define dmacHw_REG_DAR(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelDar.lo)
197#define dmacHw_REG_LLP(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelLlp.lo)
198
199#define dmacHw_REG_CTL_LO(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelCtl.lo)
200#define dmacHw_REG_CTL_HI(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelCtl.hi)
201
202#define dmacHw_REG_SSTAT(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelSstat.lo)
203#define dmacHw_REG_DSTAT(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelDstat.lo)
204#define dmacHw_REG_SSTATAR(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelSstatAddr.lo)
205#define dmacHw_REG_DSTATAR(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelDstatAddr.lo)
206
207#define dmacHw_REG_CFG_LO(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelConfig.lo)
208#define dmacHw_REG_CFG_HI(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelConfig.hi)
209
210#define dmacHw_REG_SGR_LO(module, chan) (dmacHw_CHAN_BASE((module), (chan))->SrcGather.lo)
211#define dmacHw_REG_SGR_HI(module, chan) (dmacHw_CHAN_BASE((module), (chan))->SrcGather.hi)
212
213#define dmacHw_REG_DSR_LO(module, chan) (dmacHw_CHAN_BASE((module), (chan))->DstScatter.lo)
214#define dmacHw_REG_DSR_HI(module, chan) (dmacHw_CHAN_BASE((module), (chan))->DstScatter.hi)
215
216#define INT_STATUS_MASK(channel) (0x00000001 << (channel))
217#define CHANNEL_BUSY(mod, channel) (dmacHw_REG_MISC_CH_ENABLE((mod)) & (0x00000001 << (channel)))
218
219/* Bit mask for REG_DMACx_CTL_LO */
220
221#define dmacHw_REG_CTL_INT_EN 0x00000001 /* Channel interrupt enable */
222
223#define dmacHw_REG_CTL_DST_TR_WIDTH_MASK 0x0000000E /* Destination transaction width mask */
224#define dmacHw_REG_CTL_DST_TR_WIDTH_SHIFT 1
225#define dmacHw_REG_CTL_DST_TR_WIDTH_8 0x00000000 /* Destination transaction width 8 bit */
226#define dmacHw_REG_CTL_DST_TR_WIDTH_16 0x00000002 /* Destination transaction width 16 bit */
227#define dmacHw_REG_CTL_DST_TR_WIDTH_32 0x00000004 /* Destination transaction width 32 bit */
228#define dmacHw_REG_CTL_DST_TR_WIDTH_64 0x00000006 /* Destination transaction width 64 bit */
229
230#define dmacHw_REG_CTL_SRC_TR_WIDTH_MASK 0x00000070 /* Source transaction width mask */
231#define dmacHw_REG_CTL_SRC_TR_WIDTH_SHIFT 4
232#define dmacHw_REG_CTL_SRC_TR_WIDTH_8 0x00000000 /* Source transaction width 8 bit */
233#define dmacHw_REG_CTL_SRC_TR_WIDTH_16 0x00000010 /* Source transaction width 16 bit */
234#define dmacHw_REG_CTL_SRC_TR_WIDTH_32 0x00000020 /* Source transaction width 32 bit */
235#define dmacHw_REG_CTL_SRC_TR_WIDTH_64 0x00000030 /* Source transaction width 64 bit */
236
237#define dmacHw_REG_CTL_DS_ENABLE 0x00040000 /* Destination scatter enable */
238#define dmacHw_REG_CTL_SG_ENABLE 0x00020000 /* Source gather enable */
239
240#define dmacHw_REG_CTL_DINC_MASK 0x00000180 /* Destination address inc/dec mask */
241#define dmacHw_REG_CTL_DINC_INC 0x00000000 /* Destination address increment */
242#define dmacHw_REG_CTL_DINC_DEC 0x00000080 /* Destination address decrement */
243#define dmacHw_REG_CTL_DINC_NC 0x00000100 /* Destination address no change */
244
245#define dmacHw_REG_CTL_SINC_MASK 0x00000600 /* Source address inc/dec mask */
246#define dmacHw_REG_CTL_SINC_INC 0x00000000 /* Source address increment */
247#define dmacHw_REG_CTL_SINC_DEC 0x00000200 /* Source address decrement */
248#define dmacHw_REG_CTL_SINC_NC 0x00000400 /* Source address no change */
249
250#define dmacHw_REG_CTL_DST_MSIZE_MASK 0x00003800 /* Destination burst transaction length */
251#define dmacHw_REG_CTL_DST_MSIZE_0 0x00000000 /* No Destination burst */
252#define dmacHw_REG_CTL_DST_MSIZE_4 0x00000800 /* Destination burst transaction length 4 */
253#define dmacHw_REG_CTL_DST_MSIZE_8 0x00001000 /* Destination burst transaction length 8 */
254#define dmacHw_REG_CTL_DST_MSIZE_16 0x00001800 /* Destination burst transaction length 16 */
255
256#define dmacHw_REG_CTL_SRC_MSIZE_MASK 0x0001C000 /* Source burst transaction length */
257#define dmacHw_REG_CTL_SRC_MSIZE_0 0x00000000 /* No Source burst */
258#define dmacHw_REG_CTL_SRC_MSIZE_4 0x00004000 /* Source burst transaction length 4 */
259#define dmacHw_REG_CTL_SRC_MSIZE_8 0x00008000 /* Source burst transaction length 8 */
260#define dmacHw_REG_CTL_SRC_MSIZE_16 0x0000C000 /* Source burst transaction length 16 */
261
262#define dmacHw_REG_CTL_TTFC_MASK 0x00700000 /* Transfer type and flow controller */
263#define dmacHw_REG_CTL_TTFC_MM_DMAC 0x00000000 /* Memory to Memory with DMAC as flow controller */
264#define dmacHw_REG_CTL_TTFC_MP_DMAC 0x00100000 /* Memory to Peripheral with DMAC as flow controller */
265#define dmacHw_REG_CTL_TTFC_PM_DMAC 0x00200000 /* Peripheral to Memory with DMAC as flow controller */
266#define dmacHw_REG_CTL_TTFC_PP_DMAC 0x00300000 /* Peripheral to Peripheral with DMAC as flow controller */
267#define dmacHw_REG_CTL_TTFC_PM_PERI 0x00400000 /* Peripheral to Memory with Peripheral as flow controller */
268#define dmacHw_REG_CTL_TTFC_PP_SPERI 0x00500000 /* Peripheral to Peripheral with Source Peripheral as flow controller */
269#define dmacHw_REG_CTL_TTFC_MP_PERI 0x00600000 /* Memory to Peripheral with Peripheral as flow controller */
270#define dmacHw_REG_CTL_TTFC_PP_DPERI 0x00700000 /* Peripheral to Peripheral with Destination Peripheral as flow controller */
271
272#define dmacHw_REG_CTL_DMS_MASK 0x01800000 /* Destination AHB master interface */
273#define dmacHw_REG_CTL_DMS_1 0x00000000 /* Destination AHB master interface 1 */
274#define dmacHw_REG_CTL_DMS_2 0x00800000 /* Destination AHB master interface 2 */
275
276#define dmacHw_REG_CTL_SMS_MASK 0x06000000 /* Source AHB master interface */
277#define dmacHw_REG_CTL_SMS_1 0x00000000 /* Source AHB master interface 1 */
278#define dmacHw_REG_CTL_SMS_2 0x02000000 /* Source AHB master interface 2 */
279
280#define dmacHw_REG_CTL_LLP_DST_EN 0x08000000 /* Block chaining enable for destination side */
281#define dmacHw_REG_CTL_LLP_SRC_EN 0x10000000 /* Block chaining enable for source side */
282
283/* Bit mask for REG_DMACx_CTL_HI */
284#define dmacHw_REG_CTL_BLOCK_TS_MASK 0x00000FFF /* Block transfer size */
285#define dmacHw_REG_CTL_DONE 0x00001000 /* Block trasnfer done */
286
287/* Bit mask for REG_DMACx_CFG_LO */
288#define dmacHw_REG_CFG_LO_CH_PRIORITY_SHIFT 5 /* Channel priority shift */
289#define dmacHw_REG_CFG_LO_CH_PRIORITY_MASK 0x000000E0 /* Channel priority mask */
290#define dmacHw_REG_CFG_LO_CH_PRIORITY_0 0x00000000 /* Channel priority 0 */
291#define dmacHw_REG_CFG_LO_CH_PRIORITY_1 0x00000020 /* Channel priority 1 */
292#define dmacHw_REG_CFG_LO_CH_PRIORITY_2 0x00000040 /* Channel priority 2 */
293#define dmacHw_REG_CFG_LO_CH_PRIORITY_3 0x00000060 /* Channel priority 3 */
294#define dmacHw_REG_CFG_LO_CH_PRIORITY_4 0x00000080 /* Channel priority 4 */
295#define dmacHw_REG_CFG_LO_CH_PRIORITY_5 0x000000A0 /* Channel priority 5 */
296#define dmacHw_REG_CFG_LO_CH_PRIORITY_6 0x000000C0 /* Channel priority 6 */
297#define dmacHw_REG_CFG_LO_CH_PRIORITY_7 0x000000E0 /* Channel priority 7 */
298
299#define dmacHw_REG_CFG_LO_CH_SUSPEND 0x00000100 /* Channel suspend */
300#define dmacHw_REG_CFG_LO_CH_FIFO_EMPTY 0x00000200 /* Channel FIFO empty */
301#define dmacHw_REG_CFG_LO_DST_CH_SW_HS 0x00000400 /* Destination channel SW handshaking */
302#define dmacHw_REG_CFG_LO_SRC_CH_SW_HS 0x00000800 /* Source channel SW handshaking */
303
304#define dmacHw_REG_CFG_LO_CH_LOCK_MASK 0x00003000 /* Channel locking mask */
305#define dmacHw_REG_CFG_LO_CH_LOCK_DMA 0x00000000 /* Channel lock over the entire DMA transfer operation */
306#define dmacHw_REG_CFG_LO_CH_LOCK_BLOCK 0x00001000 /* Channel lock over the block transfer operation */
307#define dmacHw_REG_CFG_LO_CH_LOCK_TRANS 0x00002000 /* Channel lock over the transaction */
308#define dmacHw_REG_CFG_LO_CH_LOCK_ENABLE 0x00010000 /* Channel lock enable */
309
310#define dmacHw_REG_CFG_LO_BUS_LOCK_MASK 0x0000C000 /* Bus locking mask */
311#define dmacHw_REG_CFG_LO_BUS_LOCK_DMA 0x00000000 /* Bus lock over the entire DMA transfer operation */
312#define dmacHw_REG_CFG_LO_BUS_LOCK_BLOCK 0x00004000 /* Bus lock over the block transfer operation */
313#define dmacHw_REG_CFG_LO_BUS_LOCK_TRANS 0x00008000 /* Bus lock over the transaction */
314#define dmacHw_REG_CFG_LO_BUS_LOCK_ENABLE 0x00020000 /* Bus lock enable */
315
316#define dmacHw_REG_CFG_LO_DST_HS_POLARITY_LOW 0x00040000 /* Destination channel handshaking signal polarity low */
317#define dmacHw_REG_CFG_LO_SRC_HS_POLARITY_LOW 0x00080000 /* Source channel handshaking signal polarity low */
318
319#define dmacHw_REG_CFG_LO_MAX_AMBA_BURST_LEN_MASK 0x3FF00000 /* Maximum AMBA burst length */
320
321#define dmacHw_REG_CFG_LO_AUTO_RELOAD_SRC 0x40000000 /* Source address auto reload */
322#define dmacHw_REG_CFG_LO_AUTO_RELOAD_DST 0x80000000 /* Destination address auto reload */
323
324/* Bit mask for REG_DMACx_CFG_HI */
325#define dmacHw_REG_CFG_HI_FC_DST_READY 0x00000001 /* Source transaction request is serviced when destination is ready */
326#define dmacHw_REG_CFG_HI_FIFO_ENOUGH 0x00000002 /* Initiate burst transaction when enough data in available in FIFO */
327
328#define dmacHw_REG_CFG_HI_AHB_HPROT_MASK 0x0000001C /* AHB protection mask */
329#define dmacHw_REG_CFG_HI_AHB_HPROT_1 0x00000004 /* AHB protection 1 */
330#define dmacHw_REG_CFG_HI_AHB_HPROT_2 0x00000008 /* AHB protection 2 */
331#define dmacHw_REG_CFG_HI_AHB_HPROT_3 0x00000010 /* AHB protection 3 */
332
333#define dmacHw_REG_CFG_HI_UPDATE_DST_STAT 0x00000020 /* Destination status update enable */
334#define dmacHw_REG_CFG_HI_UPDATE_SRC_STAT 0x00000040 /* Source status update enable */
335
336#define dmacHw_REG_CFG_HI_SRC_PERI_INTF_MASK 0x00000780 /* Source peripheral hardware interface mask */
337#define dmacHw_REG_CFG_HI_DST_PERI_INTF_MASK 0x00007800 /* Destination peripheral hardware interface mask */
338
339/* DMA Configuration Parameters */
340#define dmacHw_REG_COMP_PARAM_NUM_CHANNELS 0x00000700 /* Number of channels */
341#define dmacHw_REG_COMP_PARAM_NUM_INTERFACE 0x00001800 /* Number of master interface */
342#define dmacHw_REG_COMP_PARAM_MAX_BLK_SIZE 0x0000000f /* Maximum brust size */
343#define dmacHw_REG_COMP_PARAM_DATA_WIDTH 0x00006000 /* Data transfer width */
344
345/* Define GET/SET macros to program the registers */
346#define dmacHw_SET_SAR(module, channel, addr) (dmacHw_REG_SAR((module), (channel)) = (uint32_t) (addr))
347#define dmacHw_SET_DAR(module, channel, addr) (dmacHw_REG_DAR((module), (channel)) = (uint32_t) (addr))
348#define dmacHw_SET_LLP(module, channel, ptr) (dmacHw_REG_LLP((module), (channel)) = (uint32_t) (ptr))
349
350#define dmacHw_GET_SSTAT(module, channel) (dmacHw_REG_SSTAT((module), (channel)))
351#define dmacHw_GET_DSTAT(module, channel) (dmacHw_REG_DSTAT((module), (channel)))
352
353#define dmacHw_SET_SSTATAR(module, channel, addr) (dmacHw_REG_SSTATAR((module), (channel)) = (uint32_t) (addr))
354#define dmacHw_SET_DSTATAR(module, channel, addr) (dmacHw_REG_DSTATAR((module), (channel)) = (uint32_t) (addr))
355
356#define dmacHw_SET_CONTROL_LO(module, channel, ctl) (dmacHw_REG_CTL_LO((module), (channel)) |= (ctl))
357#define dmacHw_RESET_CONTROL_LO(module, channel) (dmacHw_REG_CTL_LO((module), (channel)) = 0)
358#define dmacHw_GET_CONTROL_LO(module, channel) (dmacHw_REG_CTL_LO((module), (channel)))
359
360#define dmacHw_SET_CONTROL_HI(module, channel, ctl) (dmacHw_REG_CTL_HI((module), (channel)) |= (ctl))
361#define dmacHw_RESET_CONTROL_HI(module, channel) (dmacHw_REG_CTL_HI((module), (channel)) = 0)
362#define dmacHw_GET_CONTROL_HI(module, channel) (dmacHw_REG_CTL_HI((module), (channel)))
363
364#define dmacHw_GET_BLOCK_SIZE(module, channel) (dmacHw_REG_CTL_HI((module), (channel)) & dmacHw_REG_CTL_BLOCK_TS_MASK)
365#define dmacHw_DMA_COMPLETE(module, channel) (dmacHw_REG_CTL_HI((module), (channel)) & dmacHw_REG_CTL_DONE)
366
367#define dmacHw_SET_CONFIG_LO(module, channel, cfg) (dmacHw_REG_CFG_LO((module), (channel)) |= (cfg))
368#define dmacHw_RESET_CONFIG_LO(module, channel) (dmacHw_REG_CFG_LO((module), (channel)) = 0)
369#define dmacHw_GET_CONFIG_LO(module, channel) (dmacHw_REG_CFG_LO((module), (channel)))
370#define dmacHw_SET_AMBA_BUSRT_LEN(module, channel, len) (dmacHw_REG_CFG_LO((module), (channel)) = (dmacHw_REG_CFG_LO((module), (channel)) & ~(dmacHw_REG_CFG_LO_MAX_AMBA_BURST_LEN_MASK)) | (((len) << 20) & dmacHw_REG_CFG_LO_MAX_AMBA_BURST_LEN_MASK))
371#define dmacHw_SET_CHANNEL_PRIORITY(module, channel, prio) (dmacHw_REG_CFG_LO((module), (channel)) = (dmacHw_REG_CFG_LO((module), (channel)) & ~(dmacHw_REG_CFG_LO_CH_PRIORITY_MASK)) | (prio))
372#define dmacHw_SET_AHB_HPROT(module, channel, protect) (dmacHw_REG_CFG_HI(module, channel) = (dmacHw_REG_CFG_HI((module), (channel)) & ~(dmacHw_REG_CFG_HI_AHB_HPROT_MASK)) | (protect))
373
374#define dmacHw_SET_CONFIG_HI(module, channel, cfg) (dmacHw_REG_CFG_HI((module), (channel)) |= (cfg))
375#define dmacHw_RESET_CONFIG_HI(module, channel) (dmacHw_REG_CFG_HI((module), (channel)) = 0)
376#define dmacHw_GET_CONFIG_HI(module, channel) (dmacHw_REG_CFG_HI((module), (channel)))
377#define dmacHw_SET_SRC_PERI_INTF(module, channel, intf) (dmacHw_REG_CFG_HI((module), (channel)) = (dmacHw_REG_CFG_HI((module), (channel)) & ~(dmacHw_REG_CFG_HI_SRC_PERI_INTF_MASK)) | (((intf) << 7) & dmacHw_REG_CFG_HI_SRC_PERI_INTF_MASK))
378#define dmacHw_SRC_PERI_INTF(intf) (((intf) << 7) & dmacHw_REG_CFG_HI_SRC_PERI_INTF_MASK)
379#define dmacHw_SET_DST_PERI_INTF(module, channel, intf) (dmacHw_REG_CFG_HI((module), (channel)) = (dmacHw_REG_CFG_HI((module), (channel)) & ~(dmacHw_REG_CFG_HI_DST_PERI_INTF_MASK)) | (((intf) << 11) & dmacHw_REG_CFG_HI_DST_PERI_INTF_MASK))
380#define dmacHw_DST_PERI_INTF(intf) (((intf) << 11) & dmacHw_REG_CFG_HI_DST_PERI_INTF_MASK)
381
382#define dmacHw_DMA_START(module, channel) (dmacHw_REG_MISC_CH_ENABLE((module)) = (0x00000001 << ((channel) + 8)) | (0x00000001 << (channel)))
383#define dmacHw_DMA_STOP(module, channel) (dmacHw_REG_MISC_CH_ENABLE((module)) = (0x00000001 << ((channel) + 8)))
384#define dmacHw_DMA_ENABLE(module) (dmacHw_REG_MISC_CFG((module)) = 1)
385#define dmacHw_DMA_DISABLE(module) (dmacHw_REG_MISC_CFG((module)) = 0)
386
387#define dmacHw_TRAN_INT_ENABLE(module, channel) (dmacHw_REG_INT_MASK_TRAN((module)) = (0x00000001 << ((channel) + 8)) | (0x00000001 << (channel)))
388#define dmacHw_BLOCK_INT_ENABLE(module, channel) (dmacHw_REG_INT_MASK_BLOCK((module)) = (0x00000001 << ((channel) + 8)) | (0x00000001 << (channel)))
389#define dmacHw_ERROR_INT_ENABLE(module, channel) (dmacHw_REG_INT_MASK_ERROR((module)) = (0x00000001 << ((channel) + 8)) | (0x00000001 << (channel)))
390
391#define dmacHw_TRAN_INT_DISABLE(module, channel) (dmacHw_REG_INT_MASK_TRAN((module)) = (0x00000001 << ((channel) + 8)))
392#define dmacHw_BLOCK_INT_DISABLE(module, channel) (dmacHw_REG_INT_MASK_BLOCK((module)) = (0x00000001 << ((channel) + 8)))
393#define dmacHw_ERROR_INT_DISABLE(module, channel) (dmacHw_REG_INT_MASK_ERROR((module)) = (0x00000001 << ((channel) + 8)))
394#define dmacHw_STRAN_INT_DISABLE(module, channel) (dmacHw_REG_INT_MASK_STRAN((module)) = (0x00000001 << ((channel) + 8)))
395#define dmacHw_DTRAN_INT_DISABLE(module, channel) (dmacHw_REG_INT_MASK_DTRAN((module)) = (0x00000001 << ((channel) + 8)))
396
397#define dmacHw_TRAN_INT_CLEAR(module, channel) (dmacHw_REG_INT_CLEAR_TRAN((module)) = (0x00000001 << (channel)))
398#define dmacHw_BLOCK_INT_CLEAR(module, channel) (dmacHw_REG_INT_CLEAR_BLOCK((module)) = (0x00000001 << (channel)))
399#define dmacHw_ERROR_INT_CLEAR(module, channel) (dmacHw_REG_INT_CLEAR_ERROR((module)) = (0x00000001 << (channel)))
400
401#define dmacHw_GET_NUM_CHANNEL(module) (((dmacHw_REG_MISC_COMP_PARAM1_HI((module)) & dmacHw_REG_COMP_PARAM_NUM_CHANNELS) >> 8) + 1)
402#define dmacHw_GET_NUM_INTERFACE(module) (((dmacHw_REG_MISC_COMP_PARAM1_HI((module)) & dmacHw_REG_COMP_PARAM_NUM_INTERFACE) >> 11) + 1)
403#define dmacHw_GET_MAX_BLOCK_SIZE(module, channel) ((dmacHw_REG_MISC_COMP_PARAM1_LO((module)) >> (4 * (channel))) & dmacHw_REG_COMP_PARAM_MAX_BLK_SIZE)
404#define dmacHw_GET_CHANNEL_DATA_WIDTH(module, channel) ((dmacHw_REG_MISC_COMP_PARAM1_HI((module)) & dmacHw_REG_COMP_PARAM_DATA_WIDTH) >> 13)
405
406#endif /* _DMACHW_REG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h b/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h
new file mode 100644
index 00000000000..cfa91bed9d3
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h
@@ -0,0 +1,73 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15
16#ifndef CSP_HW_CFG_H
17#define CSP_HW_CFG_H
18
19/* ---- Include Files ---------------------------------------------------- */
20
21#include <cfg_global.h>
22#include <mach/csp/cap_inline.h>
23
24#if defined(__KERNEL__)
25#include <mach/memory_settings.h>
26#else
27#include <hw_cfg.h>
28#endif
29
30/* Some items that can be defined externally, but will be set to default values */
31/* if they are not defined. */
32/* HW_CFG_PLL_SPREAD_SPECTRUM_DISABLE Default undefined and SS is enabled. */
33/* HW_CFG_SDRAM_CAS_LATENCY 5 Default 5, Values [3..6] */
34/* HW_CFG_SDRAM_CHIP_SELECT_CNT 1 Default 1, Vaules [1..2] */
35/* HW_CFG_SDRAM_SPEED_GRADE 667 Default 667, Values [400,533,667,800] */
36/* HW_CFG_SDRAM_WIDTH_BITS 16 Default 16, Vaules [8,16] */
37/* HW_CFG_SDRAM_ADDR_BRC Default undefined and Row-Bank-Col (RBC) addressing used. Define to use Bank-Row-Col (BRC). */
38/* HW_CFG_SDRAM_CLK_ASYNC Default undefined and DDR clock is synchronous with AXI BUS clock. Define for ASYNC mode. */
39
40#if defined(CFG_GLOBAL_CHIP)
41 #if (CFG_GLOBAL_CHIP == FPGA11107)
42 #define HW_CFG_BUS_CLK_HZ 5000000
43 #define HW_CFG_DDR_CTLR_CLK_HZ 10000000
44 #define HW_CFG_DDR_PHY_OMIT
45 #define HW_CFG_UART_CLK_HZ 7500000
46 #else
47 #define HW_CFG_PLL_VCO_HZ 2000000000
48 #define HW_CFG_PLL2_VCO_HZ 1800000000
49 #define HW_CFG_ARM_CLK_HZ CAP_HW_CFG_ARM_CLK_HZ
50 #define HW_CFG_BUS_CLK_HZ 166666666
51 #define HW_CFG_DDR_CTLR_CLK_HZ 333333333
52 #define HW_CFG_DDR_PHY_CLK_HZ (2 * HW_CFG_DDR_CTLR_CLK_HZ)
53 #define HW_CFG_UART_CLK_HZ 142857142
54 #define HW_CFG_VPM_CLK_HZ CAP_HW_CFG_VPM_CLK_HZ
55 #endif
56#else
57 #define HW_CFG_PLL_VCO_HZ 1800000000
58 #define HW_CFG_PLL2_VCO_HZ 1800000000
59 #define HW_CFG_ARM_CLK_HZ 450000000
60 #define HW_CFG_BUS_CLK_HZ 150000000
61 #define HW_CFG_DDR_CTLR_CLK_HZ 300000000
62 #define HW_CFG_DDR_PHY_CLK_HZ (2 * HW_CFG_DDR_CTLR_CLK_HZ)
63 #define HW_CFG_UART_CLK_HZ 150000000
64 #define HW_CFG_VPM_CLK_HZ 300000000
65#endif
66
67/* ---- Public Constants and Types --------------------------------------- */
68/* ---- Public Variable Externs ------------------------------------------ */
69/* ---- Public Function Prototypes --------------------------------------- */
70
71
72#endif /* CSP_HW_CFG_H */
73
diff --git a/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h
new file mode 100644
index 00000000000..0aeb6a6fe7f
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h
@@ -0,0 +1,246 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/****************************************************************************/
16/**
17* @file intcHw_reg.h
18*
19* @brief platform specific interrupt controller bit assignments
20*
21* @note
22* None
23*/
24/****************************************************************************/
25
26#ifndef _INTCHW_REG_H
27#define _INTCHW_REG_H
28
29/* ---- Include Files ---------------------------------------------------- */
30#include <csp/stdint.h>
31#include <csp/reg.h>
32#include <mach/csp/mm_io.h>
33
34/* ---- Public Constants and Types --------------------------------------- */
35
36#define INTCHW_NUM_IRQ_PER_INTC 32 /* Maximum number of interrupt controllers */
37#define INTCHW_NUM_INTC 3
38
39/* Defines for interrupt controllers. This simplifies and cleans up the function calls. */
40#define INTCHW_INTC0 ((void *)MM_IO_BASE_INTC0)
41#define INTCHW_INTC1 ((void *)MM_IO_BASE_INTC1)
42#define INTCHW_SINTC ((void *)MM_IO_BASE_SINTC)
43
44/* INTC0 - interrupt controller 0 */
45#define INTCHW_INTC0_PIF_BITNUM 31 /* Peripheral interface interrupt */
46#define INTCHW_INTC0_CLCD_BITNUM 30 /* LCD Controller interrupt */
47#define INTCHW_INTC0_GE_BITNUM 29 /* Graphic engine interrupt */
48#define INTCHW_INTC0_APM_BITNUM 28 /* Audio process module interrupt */
49#define INTCHW_INTC0_ESW_BITNUM 27 /* Ethernet switch interrupt */
50#define INTCHW_INTC0_SPIH_BITNUM 26 /* SPI host interrupt */
51#define INTCHW_INTC0_TIMER3_BITNUM 25 /* Timer3 interrupt */
52#define INTCHW_INTC0_TIMER2_BITNUM 24 /* Timer2 interrupt */
53#define INTCHW_INTC0_TIMER1_BITNUM 23 /* Timer1 interrupt */
54#define INTCHW_INTC0_TIMER0_BITNUM 22 /* Timer0 interrupt */
55#define INTCHW_INTC0_SDIOH1_BITNUM 21 /* SDIO1 host interrupt */
56#define INTCHW_INTC0_SDIOH0_BITNUM 20 /* SDIO0 host interrupt */
57#define INTCHW_INTC0_USBD_BITNUM 19 /* USB device interrupt */
58#define INTCHW_INTC0_USBH1_BITNUM 18 /* USB1 host interrupt */
59#define INTCHW_INTC0_USBHD2_BITNUM 17 /* USB host2/device2 interrupt */
60#define INTCHW_INTC0_VPM_BITNUM 16 /* Voice process module interrupt */
61#define INTCHW_INTC0_DMA1C7_BITNUM 15 /* DMA1 channel 7 interrupt */
62#define INTCHW_INTC0_DMA1C6_BITNUM 14 /* DMA1 channel 6 interrupt */
63#define INTCHW_INTC0_DMA1C5_BITNUM 13 /* DMA1 channel 5 interrupt */
64#define INTCHW_INTC0_DMA1C4_BITNUM 12 /* DMA1 channel 4 interrupt */
65#define INTCHW_INTC0_DMA1C3_BITNUM 11 /* DMA1 channel 3 interrupt */
66#define INTCHW_INTC0_DMA1C2_BITNUM 10 /* DMA1 channel 2 interrupt */
67#define INTCHW_INTC0_DMA1C1_BITNUM 9 /* DMA1 channel 1 interrupt */
68#define INTCHW_INTC0_DMA1C0_BITNUM 8 /* DMA1 channel 0 interrupt */
69#define INTCHW_INTC0_DMA0C7_BITNUM 7 /* DMA0 channel 7 interrupt */
70#define INTCHW_INTC0_DMA0C6_BITNUM 6 /* DMA0 channel 6 interrupt */
71#define INTCHW_INTC0_DMA0C5_BITNUM 5 /* DMA0 channel 5 interrupt */
72#define INTCHW_INTC0_DMA0C4_BITNUM 4 /* DMA0 channel 4 interrupt */
73#define INTCHW_INTC0_DMA0C3_BITNUM 3 /* DMA0 channel 3 interrupt */
74#define INTCHW_INTC0_DMA0C2_BITNUM 2 /* DMA0 channel 2 interrupt */
75#define INTCHW_INTC0_DMA0C1_BITNUM 1 /* DMA0 channel 1 interrupt */
76#define INTCHW_INTC0_DMA0C0_BITNUM 0 /* DMA0 channel 0 interrupt */
77
78#define INTCHW_INTC0_PIF (1<<INTCHW_INTC0_PIF_BITNUM)
79#define INTCHW_INTC0_CLCD (1<<INTCHW_INTC0_CLCD_BITNUM)
80#define INTCHW_INTC0_GE (1<<INTCHW_INTC0_GE_BITNUM)
81#define INTCHW_INTC0_APM (1<<INTCHW_INTC0_APM_BITNUM)
82#define INTCHW_INTC0_ESW (1<<INTCHW_INTC0_ESW_BITNUM)
83#define INTCHW_INTC0_SPIH (1<<INTCHW_INTC0_SPIH_BITNUM)
84#define INTCHW_INTC0_TIMER3 (1<<INTCHW_INTC0_TIMER3_BITNUM)
85#define INTCHW_INTC0_TIMER2 (1<<INTCHW_INTC0_TIMER2_BITNUM)
86#define INTCHW_INTC0_TIMER1 (1<<INTCHW_INTC0_TIMER1_BITNUM)
87#define INTCHW_INTC0_TIMER0 (1<<INTCHW_INTC0_TIMER0_BITNUM)
88#define INTCHW_INTC0_SDIOH1 (1<<INTCHW_INTC0_SDIOH1_BITNUM)
89#define INTCHW_INTC0_SDIOH0 (1<<INTCHW_INTC0_SDIOH0_BITNUM)
90#define INTCHW_INTC0_USBD (1<<INTCHW_INTC0_USBD_BITNUM)
91#define INTCHW_INTC0_USBH1 (1<<INTCHW_INTC0_USBH1_BITNUM)
92#define INTCHW_INTC0_USBHD2 (1<<INTCHW_INTC0_USBHD2_BITNUM)
93#define INTCHW_INTC0_VPM (1<<INTCHW_INTC0_VPM_BITNUM)
94#define INTCHW_INTC0_DMA1C7 (1<<INTCHW_INTC0_DMA1C7_BITNUM)
95#define INTCHW_INTC0_DMA1C6 (1<<INTCHW_INTC0_DMA1C6_BITNUM)
96#define INTCHW_INTC0_DMA1C5 (1<<INTCHW_INTC0_DMA1C5_BITNUM)
97#define INTCHW_INTC0_DMA1C4 (1<<INTCHW_INTC0_DMA1C4_BITNUM)
98#define INTCHW_INTC0_DMA1C3 (1<<INTCHW_INTC0_DMA1C3_BITNUM)
99#define INTCHW_INTC0_DMA1C2 (1<<INTCHW_INTC0_DMA1C2_BITNUM)
100#define INTCHW_INTC0_DMA1C1 (1<<INTCHW_INTC0_DMA1C1_BITNUM)
101#define INTCHW_INTC0_DMA1C0 (1<<INTCHW_INTC0_DMA1C0_BITNUM)
102#define INTCHW_INTC0_DMA0C7 (1<<INTCHW_INTC0_DMA0C7_BITNUM)
103#define INTCHW_INTC0_DMA0C6 (1<<INTCHW_INTC0_DMA0C6_BITNUM)
104#define INTCHW_INTC0_DMA0C5 (1<<INTCHW_INTC0_DMA0C5_BITNUM)
105#define INTCHW_INTC0_DMA0C4 (1<<INTCHW_INTC0_DMA0C4_BITNUM)
106#define INTCHW_INTC0_DMA0C3 (1<<INTCHW_INTC0_DMA0C3_BITNUM)
107#define INTCHW_INTC0_DMA0C2 (1<<INTCHW_INTC0_DMA0C2_BITNUM)
108#define INTCHW_INTC0_DMA0C1 (1<<INTCHW_INTC0_DMA0C1_BITNUM)
109#define INTCHW_INTC0_DMA0C0 (1<<INTCHW_INTC0_DMA0C0_BITNUM)
110
111/* INTC1 - interrupt controller 1 */
112#define INTCHW_INTC1_DDRVPMP_BITNUM 27 /* DDR and VPM PLL clock phase relationship interrupt (Not for A0) */
113#define INTCHW_INTC1_DDRVPMT_BITNUM 26 /* DDR and VPM HW phase align timeout interrupt (Not for A0) */
114#define INTCHW_INTC1_DDRP_BITNUM 26 /* DDR and PLL clock phase relationship interrupt (For A0 only)) */
115#define INTCHW_INTC1_RTC2_BITNUM 25 /* Real time clock tamper interrupt */
116#define INTCHW_INTC1_VDEC_BITNUM 24 /* Hantro Video Decoder interrupt */
117/* Bits 13-23 are non-secure versions of the corresponding secure bits in SINTC bits 0-10. */
118#define INTCHW_INTC1_SPUM_BITNUM 23 /* Secure process module interrupt */
119#define INTCHW_INTC1_RTC1_BITNUM 22 /* Real time clock one-shot interrupt */
120#define INTCHW_INTC1_RTC0_BITNUM 21 /* Real time clock periodic interrupt */
121#define INTCHW_INTC1_RNG_BITNUM 20 /* Random number generator interrupt */
122#define INTCHW_INTC1_FMPU_BITNUM 19 /* Flash memory parition unit interrupt */
123#define INTCHW_INTC1_VMPU_BITNUM 18 /* VRAM memory partition interrupt */
124#define INTCHW_INTC1_DMPU_BITNUM 17 /* DDR2 memory partition interrupt */
125#define INTCHW_INTC1_KEYC_BITNUM 16 /* Key pad controller interrupt */
126#define INTCHW_INTC1_TSC_BITNUM 15 /* Touch screen controller interrupt */
127#define INTCHW_INTC1_UART0_BITNUM 14 /* UART 0 */
128#define INTCHW_INTC1_WDOG_BITNUM 13 /* Watchdog timer interrupt */
129
130#define INTCHW_INTC1_UART1_BITNUM 12 /* UART 1 */
131#define INTCHW_INTC1_PMUIRQ_BITNUM 11 /* ARM performance monitor interrupt */
132#define INTCHW_INTC1_COMMRX_BITNUM 10 /* ARM DDC receive interrupt */
133#define INTCHW_INTC1_COMMTX_BITNUM 9 /* ARM DDC transmit interrupt */
134#define INTCHW_INTC1_FLASHC_BITNUM 8 /* Flash controller interrupt */
135#define INTCHW_INTC1_GPHY_BITNUM 7 /* Gigabit Phy interrupt */
136#define INTCHW_INTC1_SPIS_BITNUM 6 /* SPI slave interrupt */
137#define INTCHW_INTC1_I2CS_BITNUM 5 /* I2C slave interrupt */
138#define INTCHW_INTC1_I2CH_BITNUM 4 /* I2C host interrupt */
139#define INTCHW_INTC1_I2S1_BITNUM 3 /* I2S1 interrupt */
140#define INTCHW_INTC1_I2S0_BITNUM 2 /* I2S0 interrupt */
141#define INTCHW_INTC1_GPIO1_BITNUM 1 /* GPIO bit 64//32 combined interrupt */
142#define INTCHW_INTC1_GPIO0_BITNUM 0 /* GPIO bit 31//0 combined interrupt */
143
144#define INTCHW_INTC1_DDRVPMT (1<<INTCHW_INTC1_DDRVPMT_BITNUM)
145#define INTCHW_INTC1_DDRVPMP (1<<INTCHW_INTC1_DDRVPMP_BITNUM)
146#define INTCHW_INTC1_DDRP (1<<INTCHW_INTC1_DDRP_BITNUM)
147#define INTCHW_INTC1_VDEC (1<<INTCHW_INTC1_VDEC_BITNUM)
148#define INTCHW_INTC1_SPUM (1<<INTCHW_INTC1_SPUM_BITNUM)
149#define INTCHW_INTC1_RTC2 (1<<INTCHW_INTC1_RTC2_BITNUM)
150#define INTCHW_INTC1_RTC1 (1<<INTCHW_INTC1_RTC1_BITNUM)
151#define INTCHW_INTC1_RTC0 (1<<INTCHW_INTC1_RTC0_BITNUM)
152#define INTCHW_INTC1_RNG (1<<INTCHW_INTC1_RNG_BITNUM)
153#define INTCHW_INTC1_FMPU (1<<INTCHW_INTC1_FMPU_BITNUM)
154#define INTCHW_INTC1_IMPU (1<<INTCHW_INTC1_IMPU_BITNUM)
155#define INTCHW_INTC1_DMPU (1<<INTCHW_INTC1_DMPU_BITNUM)
156#define INTCHW_INTC1_KEYC (1<<INTCHW_INTC1_KEYC_BITNUM)
157#define INTCHW_INTC1_TSC (1<<INTCHW_INTC1_TSC_BITNUM)
158#define INTCHW_INTC1_UART0 (1<<INTCHW_INTC1_UART0_BITNUM)
159#define INTCHW_INTC1_WDOG (1<<INTCHW_INTC1_WDOG_BITNUM)
160#define INTCHW_INTC1_UART1 (1<<INTCHW_INTC1_UART1_BITNUM)
161#define INTCHW_INTC1_PMUIRQ (1<<INTCHW_INTC1_PMUIRQ_BITNUM)
162#define INTCHW_INTC1_COMMRX (1<<INTCHW_INTC1_COMMRX_BITNUM)
163#define INTCHW_INTC1_COMMTX (1<<INTCHW_INTC1_COMMTX_BITNUM)
164#define INTCHW_INTC1_FLASHC (1<<INTCHW_INTC1_FLASHC_BITNUM)
165#define INTCHW_INTC1_GPHY (1<<INTCHW_INTC1_GPHY_BITNUM)
166#define INTCHW_INTC1_SPIS (1<<INTCHW_INTC1_SPIS_BITNUM)
167#define INTCHW_INTC1_I2CS (1<<INTCHW_INTC1_I2CS_BITNUM)
168#define INTCHW_INTC1_I2CH (1<<INTCHW_INTC1_I2CH_BITNUM)
169#define INTCHW_INTC1_I2S1 (1<<INTCHW_INTC1_I2S1_BITNUM)
170#define INTCHW_INTC1_I2S0 (1<<INTCHW_INTC1_I2S0_BITNUM)
171#define INTCHW_INTC1_GPIO1 (1<<INTCHW_INTC1_GPIO1_BITNUM)
172#define INTCHW_INTC1_GPIO0 (1<<INTCHW_INTC1_GPIO0_BITNUM)
173
174/* SINTC secure int controller */
175#define INTCHW_SINTC_RTC2_BITNUM 15 /* Real time clock tamper interrupt */
176#define INTCHW_SINTC_TIMER3_BITNUM 14 /* Secure timer3 interrupt */
177#define INTCHW_SINTC_TIMER2_BITNUM 13 /* Secure timer2 interrupt */
178#define INTCHW_SINTC_TIMER1_BITNUM 12 /* Secure timer1 interrupt */
179#define INTCHW_SINTC_TIMER0_BITNUM 11 /* Secure timer0 interrupt */
180#define INTCHW_SINTC_SPUM_BITNUM 10 /* Secure process module interrupt */
181#define INTCHW_SINTC_RTC1_BITNUM 9 /* Real time clock one-shot interrupt */
182#define INTCHW_SINTC_RTC0_BITNUM 8 /* Real time clock periodic interrupt */
183#define INTCHW_SINTC_RNG_BITNUM 7 /* Random number generator interrupt */
184#define INTCHW_SINTC_FMPU_BITNUM 6 /* Flash memory parition unit interrupt */
185#define INTCHW_SINTC_VMPU_BITNUM 5 /* VRAM memory partition interrupt */
186#define INTCHW_SINTC_DMPU_BITNUM 4 /* DDR2 memory partition interrupt */
187#define INTCHW_SINTC_KEYC_BITNUM 3 /* Key pad controller interrupt */
188#define INTCHW_SINTC_TSC_BITNUM 2 /* Touch screen controller interrupt */
189#define INTCHW_SINTC_UART0_BITNUM 1 /* UART0 interrupt */
190#define INTCHW_SINTC_WDOG_BITNUM 0 /* Watchdog timer interrupt */
191
192#define INTCHW_SINTC_TIMER3 (1<<INTCHW_SINTC_TIMER3_BITNUM)
193#define INTCHW_SINTC_TIMER2 (1<<INTCHW_SINTC_TIMER2_BITNUM)
194#define INTCHW_SINTC_TIMER1 (1<<INTCHW_SINTC_TIMER1_BITNUM)
195#define INTCHW_SINTC_TIMER0 (1<<INTCHW_SINTC_TIMER0_BITNUM)
196#define INTCHW_SINTC_SPUM (1<<INTCHW_SINTC_SPUM_BITNUM)
197#define INTCHW_SINTC_RTC2 (1<<INTCHW_SINTC_RTC2_BITNUM)
198#define INTCHW_SINTC_RTC1 (1<<INTCHW_SINTC_RTC1_BITNUM)
199#define INTCHW_SINTC_RTC0 (1<<INTCHW_SINTC_RTC0_BITNUM)
200#define INTCHW_SINTC_RNG (1<<INTCHW_SINTC_RNG_BITNUM)
201#define INTCHW_SINTC_FMPU (1<<INTCHW_SINTC_FMPU_BITNUM)
202#define INTCHW_SINTC_IMPU (1<<INTCHW_SINTC_IMPU_BITNUM)
203#define INTCHW_SINTC_DMPU (1<<INTCHW_SINTC_DMPU_BITNUM)
204#define INTCHW_SINTC_KEYC (1<<INTCHW_SINTC_KEYC_BITNUM)
205#define INTCHW_SINTC_TSC (1<<INTCHW_SINTC_TSC_BITNUM)
206#define INTCHW_SINTC_UART0 (1<<INTCHW_SINTC_UART0_BITNUM)
207#define INTCHW_SINTC_WDOG (1<<INTCHW_SINTC_WDOG_BITNUM)
208
209/* PL192 Vectored Interrupt Controller (VIC) layout */
210#define INTCHW_IRQSTATUS 0x00 /* IRQ status register */
211#define INTCHW_FIQSTATUS 0x04 /* FIQ status register */
212#define INTCHW_RAWINTR 0x08 /* Raw Interrupt Status register */
213#define INTCHW_INTSELECT 0x0c /* Interrupt Select Register */
214#define INTCHW_INTENABLE 0x10 /* Interrupt Enable Register */
215#define INTCHW_INTENCLEAR 0x14 /* Interrupt Enable Clear Register */
216#define INTCHW_SOFTINT 0x18 /* Soft Interrupt Register */
217#define INTCHW_SOFTINTCLEAR 0x1c /* Soft Interrupt Clear Register */
218#define INTCHW_PROTECTION 0x20 /* Protection Enable Register */
219#define INTCHW_SWPRIOMASK 0x24 /* Software Priority Mask Register */
220#define INTCHW_PRIODAISY 0x28 /* Priority Daisy Chain Register */
221#define INTCHW_VECTADDR0 0x100 /* Vector Address Registers */
222#define INTCHW_VECTPRIO0 0x200 /* Vector Priority Registers 0-31 */
223#define INTCHW_ADDRESS 0xf00 /* Vector Address Register 0-31 */
224#define INTCHW_PID 0xfe0 /* Peripheral ID Register 0-3 */
225#define INTCHW_PCELLID 0xff0 /* PrimeCell ID Register 0-3 */
226
227/* Example Usage: intcHw_irq_enable(INTCHW_INTC0, INTCHW_INTC0_TIMER0); */
228/* intcHw_irq_clear(INTCHW_INTC0, INTCHW_INTC0_TIMER0); */
229/* uint32_t bits = intcHw_irq_status(INTCHW_INTC0); */
230/* uint32_t bits = intcHw_irq_raw_status(INTCHW_INTC0); */
231
232/* ---- Public Variable Externs ------------------------------------------ */
233/* ---- Public Function Prototypes --------------------------------------- */
234/* Clear one or more IRQ interrupts. */
235static inline void intcHw_irq_disable(void *basep, uint32_t mask)
236{
237 __REG32(basep + INTCHW_INTENCLEAR) = mask;
238}
239
240/* Enables one or more IRQ interrupts. */
241static inline void intcHw_irq_enable(void *basep, uint32_t mask)
242{
243 __REG32(basep + INTCHW_INTENABLE) = mask;
244}
245
246#endif /* _INTCHW_REG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h b/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h
new file mode 100644
index 00000000000..ad58cf87337
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h
@@ -0,0 +1,101 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/****************************************************************************/
16/**
17* @file mm_addr.h
18*
19* @brief Memory Map address definitions
20*
21* @note
22* None
23*/
24/****************************************************************************/
25
26#ifndef _MM_ADDR_H
27#define _MM_ADDR_H
28
29/* ---- Include Files ---------------------------------------------------- */
30
31#if !defined(CSP_SIMULATION)
32#include <cfg_global.h>
33#endif
34
35/* ---- Public Constants and Types --------------------------------------- */
36
37/* Memory Map address definitions */
38
39#define MM_ADDR_DDR 0x00000000
40
41#define MM_ADDR_IO_VPM_EXTMEM_RSVD 0x0F000000 /* 16 MB - Reserved external memory for VPM use */
42
43#define MM_ADDR_IO_FLASHC 0x20000000
44#define MM_ADDR_IO_BROM 0x30000000
45#define MM_ADDR_IO_ARAM 0x30100000 /* 64 KB - extra cycle latency - WS switch */
46#define MM_ADDR_IO_DMA0 0x30200000
47#define MM_ADDR_IO_DMA1 0x30300000
48#define MM_ADDR_IO_ESW 0x30400000
49#define MM_ADDR_IO_CLCD 0x30500000
50#define MM_ADDR_IO_PIF 0x30580000
51#define MM_ADDR_IO_APM 0x30600000
52#define MM_ADDR_IO_SPUM 0x30700000
53#define MM_ADDR_IO_VPM_PROG 0x30800000
54#define MM_ADDR_IO_VPM_DATA 0x30A00000
55#define MM_ADDR_IO_VRAM 0x40000000 /* 64 KB - security block in front of it */
56#define MM_ADDR_IO_CHIPC 0x80000000
57#define MM_ADDR_IO_UMI 0x80001000
58#define MM_ADDR_IO_NAND 0x80001800
59#define MM_ADDR_IO_LEDM 0x80002000
60#define MM_ADDR_IO_PWM 0x80002040
61#define MM_ADDR_IO_VINTC 0x80003000
62#define MM_ADDR_IO_GPIO0 0x80004000
63#define MM_ADDR_IO_GPIO1 0x80004800
64#define MM_ADDR_IO_I2CS 0x80005000
65#define MM_ADDR_IO_SPIS 0x80006000
66#define MM_ADDR_IO_HPM 0x80007400
67#define MM_ADDR_IO_HPM_REMAP 0x80007800
68#define MM_ADDR_IO_TZPC 0x80008000
69#define MM_ADDR_IO_MPU 0x80009000
70#define MM_ADDR_IO_SPUMP 0x8000a000
71#define MM_ADDR_IO_PKA 0x8000b000
72#define MM_ADDR_IO_RNG 0x8000c000
73#define MM_ADDR_IO_KEYC 0x8000d000
74#define MM_ADDR_IO_BBL 0x8000e000
75#define MM_ADDR_IO_OTP 0x8000f000
76#define MM_ADDR_IO_I2S0 0x80010000
77#define MM_ADDR_IO_I2S1 0x80011000
78#define MM_ADDR_IO_UARTA 0x80012000
79#define MM_ADDR_IO_UARTB 0x80013000
80#define MM_ADDR_IO_I2CH 0x80014020
81#define MM_ADDR_IO_SPIH 0x80015000
82#define MM_ADDR_IO_TSC 0x80016000
83#define MM_ADDR_IO_TMR 0x80017000
84#define MM_ADDR_IO_WATCHDOG 0x80017800
85#define MM_ADDR_IO_ETM 0x80018000
86#define MM_ADDR_IO_DDRC 0x80019000
87#define MM_ADDR_IO_SINTC 0x80100000
88#define MM_ADDR_IO_INTC0 0x80200000
89#define MM_ADDR_IO_INTC1 0x80201000
90#define MM_ADDR_IO_GE 0x80300000
91#define MM_ADDR_IO_USB_CTLR0 0x80400000
92#define MM_ADDR_IO_USB_CTLR1 0x80410000
93#define MM_ADDR_IO_USB_PHY 0x80420000
94#define MM_ADDR_IO_SDIOH0 0x80500000
95#define MM_ADDR_IO_SDIOH1 0x80600000
96#define MM_ADDR_IO_VDEC 0x80700000
97
98/* ---- Public Variable Externs ------------------------------------------ */
99/* ---- Public Function Prototypes --------------------------------------- */
100
101#endif /* _MM_ADDR_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/mm_io.h b/arch/arm/mach-bcmring/include/mach/csp/mm_io.h
new file mode 100644
index 00000000000..de92ec6a01a
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/mm_io.h
@@ -0,0 +1,147 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/****************************************************************************/
16/**
17* @file mm_io.h
18*
19* @brief Memory Map I/O definitions
20*
21* @note
22* None
23*/
24/****************************************************************************/
25
26#ifndef _MM_IO_H
27#define _MM_IO_H
28
29/* ---- Include Files ---------------------------------------------------- */
30#include <mach/csp/mm_addr.h>
31
32#if !defined(CSP_SIMULATION)
33#include <cfg_global.h>
34#endif
35
36/* ---- Public Constants and Types --------------------------------------- */
37
38#if defined(CONFIG_MMU)
39
40/* This macro is referenced in <mach/io.h>
41 * Phys to Virtual 0xNyxxxxxx => 0xFNxxxxxx
42 * This macro is referenced in <asm/arch/io.h>
43 *
44 * Assume VPM address is the last x MB of memory. For VPM, map to
45 * 0xf0000000 and up.
46 */
47
48#ifndef MM_IO_PHYS_TO_VIRT
49#ifdef __ASSEMBLY__
50#define MM_IO_PHYS_TO_VIRT(phys) (0xF0000000 | (((phys) >> 4) & 0x0F000000) | ((phys) & 0xFFFFFF))
51#else
52#define MM_IO_PHYS_TO_VIRT(phys) (((phys) == MM_ADDR_IO_VPM_EXTMEM_RSVD) ? 0xF0000000 : \
53 (0xF0000000 | (((phys) >> 4) & 0x0F000000) | ((phys) & 0xFFFFFF)))
54#endif
55#endif
56
57/* Virtual to Physical 0xFNxxxxxx => 0xN0xxxxxx */
58
59#ifndef MM_IO_VIRT_TO_PHYS
60#ifdef __ASSEMBLY__
61#define MM_IO_VIRT_TO_PHYS(virt) ((((virt) & 0x0F000000) << 4) | ((virt) & 0xFFFFFF))
62#else
63#define MM_IO_VIRT_TO_PHYS(virt) (((virt) == 0xF0000000) ? MM_ADDR_IO_VPM_EXTMEM_RSVD : \
64 ((((virt) & 0x0F000000) << 4) | ((virt) & 0xFFFFFF)))
65#endif
66#endif
67
68#else
69
70#ifndef MM_IO_PHYS_TO_VIRT
71#define MM_IO_PHYS_TO_VIRT(phys) (phys)
72#endif
73
74#ifndef MM_IO_VIRT_TO_PHYS
75#define MM_IO_VIRT_TO_PHYS(virt) (virt)
76#endif
77
78#endif
79
80/* Registers in 0xExxxxxxx that should be moved to 0xFxxxxxxx */
81#define MM_IO_BASE_FLASHC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_FLASHC)
82#define MM_IO_BASE_NAND MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_NAND)
83#define MM_IO_BASE_UMI MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_UMI)
84
85#define MM_IO_START MM_ADDR_IO_FLASHC /* Physical beginning of IO mapped memory */
86#define MM_IO_BASE MM_IO_BASE_FLASHC /* Virtual beginning of IO mapped memory */
87
88#define MM_IO_BASE_BROM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_BROM)
89#define MM_IO_BASE_ARAM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_ARAM)
90#define MM_IO_BASE_DMA0 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_DMA0)
91#define MM_IO_BASE_DMA1 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_DMA1)
92#define MM_IO_BASE_ESW MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_ESW)
93#define MM_IO_BASE_CLCD MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_CLCD)
94#define MM_IO_BASE_PIF MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_PIF)
95#define MM_IO_BASE_APM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_APM)
96#define MM_IO_BASE_SPUM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SPUM)
97#define MM_IO_BASE_VPM_PROG MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VPM_PROG)
98#define MM_IO_BASE_VPM_DATA MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VPM_DATA)
99
100#define MM_IO_BASE_VRAM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VRAM)
101
102#define MM_IO_BASE_CHIPC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_CHIPC)
103#define MM_IO_BASE_DDRC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_DDRC)
104#define MM_IO_BASE_LEDM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_LEDM)
105#define MM_IO_BASE_PWM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_PWM)
106#define MM_IO_BASE_VINTC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VINTC)
107#define MM_IO_BASE_GPIO0 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_GPIO0)
108#define MM_IO_BASE_GPIO1 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_GPIO1)
109#define MM_IO_BASE_TMR MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_TMR)
110#define MM_IO_BASE_WATCHDOG MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_WATCHDOG)
111#define MM_IO_BASE_ETM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_ETM)
112#define MM_IO_BASE_HPM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_HPM)
113#define MM_IO_BASE_HPM_REMAP MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_HPM_REMAP)
114#define MM_IO_BASE_TZPC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_TZPC)
115#define MM_IO_BASE_MPU MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_MPU)
116#define MM_IO_BASE_SPUMP MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SPUMP)
117#define MM_IO_BASE_PKA MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_PKA)
118#define MM_IO_BASE_RNG MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_RNG)
119#define MM_IO_BASE_KEYC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_KEYC)
120#define MM_IO_BASE_BBL MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_BBL)
121#define MM_IO_BASE_OTP MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_OTP)
122#define MM_IO_BASE_I2S0 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_I2S0)
123#define MM_IO_BASE_I2S1 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_I2S1)
124#define MM_IO_BASE_UARTA MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_UARTA)
125#define MM_IO_BASE_UARTB MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_UARTB)
126#define MM_IO_BASE_I2CH MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_I2CH)
127#define MM_IO_BASE_SPIH MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SPIH)
128#define MM_IO_BASE_TSC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_TSC)
129#define MM_IO_BASE_I2CS MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_I2CS)
130#define MM_IO_BASE_SPIS MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SPIS)
131#define MM_IO_BASE_SINTC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SINTC)
132#define MM_IO_BASE_INTC0 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_INTC0)
133#define MM_IO_BASE_INTC1 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_INTC1)
134#define MM_IO_BASE_GE MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_GE)
135#define MM_IO_BASE_USB_CTLR0 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_USB_CTLR0)
136#define MM_IO_BASE_USB_CTLR1 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_USB_CTLR1)
137#define MM_IO_BASE_USB_PHY MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_USB_PHY)
138#define MM_IO_BASE_SDIOH0 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SDIOH0)
139#define MM_IO_BASE_SDIOH1 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SDIOH1)
140#define MM_IO_BASE_VDEC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VDEC)
141
142#define MM_IO_BASE_VPM_EXTMEM_RSVD MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VPM_EXTMEM_RSVD)
143
144/* ---- Public Variable Externs ------------------------------------------ */
145/* ---- Public Function Prototypes --------------------------------------- */
146
147#endif /* _MM_IO_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/secHw_def.h b/arch/arm/mach-bcmring/include/mach/csp/secHw_def.h
new file mode 100644
index 00000000000..d15f5f3ec2d
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/secHw_def.h
@@ -0,0 +1,100 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/****************************************************************************/
16/**
17* @file secHw_def.h
18*
19* @brief Definitions for configuring/testing secure blocks
20*
21* @note
22* None
23*/
24/****************************************************************************/
25
26#ifndef SECHW_DEF_H
27#define SECHW_DEF_H
28
29#include <mach/csp/mm_io.h>
30
31/* Bit mask for various secure device */
32#define secHw_BLK_MASK_CHIP_CONTROL 0x00000001
33#define secHw_BLK_MASK_KEY_SCAN 0x00000002
34#define secHw_BLK_MASK_TOUCH_SCREEN 0x00000004
35#define secHw_BLK_MASK_UART0 0x00000008
36#define secHw_BLK_MASK_UART1 0x00000010
37#define secHw_BLK_MASK_WATCHDOG 0x00000020
38#define secHw_BLK_MASK_SPUM 0x00000040
39#define secHw_BLK_MASK_DDR2 0x00000080
40#define secHw_BLK_MASK_EXT_MEM 0x00000100
41#define secHw_BLK_MASK_ESW 0x00000200
42#define secHw_BLK_MASK_SPU 0x00010000
43#define secHw_BLK_MASK_PKA 0x00020000
44#define secHw_BLK_MASK_RNG 0x00040000
45#define secHw_BLK_MASK_RTC 0x00080000
46#define secHw_BLK_MASK_OTP 0x00100000
47#define secHw_BLK_MASK_BOOT 0x00200000
48#define secHw_BLK_MASK_MPU 0x00400000
49#define secHw_BLK_MASK_TZCTRL 0x00800000
50#define secHw_BLK_MASK_INTR 0x01000000
51
52/* Trustzone register set */
53typedef struct {
54 volatile uint32_t status; /* read only - reflects status of writes of 2 write registers */
55 volatile uint32_t setUnsecure; /* write only. reads back as 0 */
56 volatile uint32_t setSecure; /* write only. reads back as 0 */
57} secHw_TZREG_t;
58
59/* There are 2 register sets. The first is for the lower 16 bits, the 2nd */
60/* is for the higher 16 bits. */
61
62typedef enum {
63 secHw_IDX_LS = 0,
64 secHw_IDX_MS = 1,
65 secHw_IDX_NUM
66} secHw_IDX_e;
67
68typedef struct {
69 volatile secHw_TZREG_t reg[secHw_IDX_NUM];
70} secHw_REGS_t;
71
72/****************************************************************************/
73/**
74* @brief Configures a device as a secure device
75*
76*/
77/****************************************************************************/
78static inline void secHw_setSecure(uint32_t mask /* mask of type secHw_BLK_MASK_XXXXXX */
79 );
80
81/****************************************************************************/
82/**
83* @brief Configures a device as a non-secure device
84*
85*/
86/****************************************************************************/
87static inline void secHw_setUnsecure(uint32_t mask /* mask of type secHw_BLK_MASK_XXXXXX */
88 );
89
90/****************************************************************************/
91/**
92* @brief Get the trustzone status for all components. 1 = non-secure, 0 = secure
93*
94*/
95/****************************************************************************/
96static inline uint32_t secHw_getStatus(void);
97
98#include <mach/csp/secHw_inline.h>
99
100#endif /* SECHW_DEF_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h b/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h
new file mode 100644
index 00000000000..9cd6a032ab7
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h
@@ -0,0 +1,79 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/****************************************************************************/
16/**
17* @file secHw_inline.h
18*
19* @brief Definitions for configuring/testing secure blocks
20*
21* @note
22* None
23*/
24/****************************************************************************/
25
26#ifndef SECHW_INLINE_H
27#define SECHW_INLINE_H
28
29/****************************************************************************/
30/**
31* @brief Configures a device as a secure device
32*
33*/
34/****************************************************************************/
35static inline void secHw_setSecure(uint32_t mask /* mask of type secHw_BLK_MASK_XXXXXX */
36 ) {
37 secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC;
38
39 if (mask & 0x0000FFFF) {
40 regp->reg[secHw_IDX_LS].setSecure = mask & 0x0000FFFF;
41 }
42
43 if (mask & 0xFFFF0000) {
44 regp->reg[secHw_IDX_MS].setSecure = mask >> 16;
45 }
46}
47
48/****************************************************************************/
49/**
50* @brief Configures a device as a non-secure device
51*
52*/
53/****************************************************************************/
54static inline void secHw_setUnsecure(uint32_t mask /* mask of type secHw_BLK_MASK_XXXXXX */
55 ) {
56 secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC;
57
58 if (mask & 0x0000FFFF) {
59 regp->reg[secHw_IDX_LS].setUnsecure = mask & 0x0000FFFF;
60 }
61 if (mask & 0xFFFF0000) {
62 regp->reg[secHw_IDX_MS].setUnsecure = mask >> 16;
63 }
64}
65
66/****************************************************************************/
67/**
68* @brief Get the trustzone status for all components. 1 = non-secure, 0 = secure
69*
70*/
71/****************************************************************************/
72static inline uint32_t secHw_getStatus(void)
73{
74 secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC;
75
76 return (regp->reg[1].status << 16) + regp->reg[0].status;
77}
78
79#endif /* SECHW_INLINE_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/tmrHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/tmrHw_reg.h
new file mode 100644
index 00000000000..3080ac7239a
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/tmrHw_reg.h
@@ -0,0 +1,82 @@
1/*****************************************************************************
2* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/****************************************************************************/
16/**
17* @file tmrHw_reg.h
18*
19* @brief Definitions for low level Timer registers
20*
21*/
22/****************************************************************************/
23#ifndef _TMRHW_REG_H
24#define _TMRHW_REG_H
25
26#include <mach/csp/mm_io.h>
27#include <mach/csp/hw_cfg.h>
28/* Base address */
29#define tmrHw_MODULE_BASE_ADDR MM_IO_BASE_TMR
30
31/*
32This platform has four different timers running at different clock speed
33
34Timer one (Timer ID 0) runs at 25 MHz
35Timer two (Timer ID 1) runs at 25 MHz
36Timer three (Timer ID 2) runs at 150 MHz
37Timer four (Timer ID 3) runs at 150 MHz
38*/
39#define tmrHw_LOW_FREQUENCY_MHZ 25 /* Always 25MHz from XTAL */
40#define tmrHw_LOW_FREQUENCY_HZ 25000000
41
42#if defined(CFG_GLOBAL_CHIP) && (CFG_GLOBAL_CHIP == FPGA11107)
43#define tmrHw_HIGH_FREQUENCY_MHZ 150 /* Always 150MHz for FPGA */
44#define tmrHw_HIGH_FREQUENCY_HZ 150000000
45#else
46#define tmrHw_HIGH_FREQUENCY_HZ HW_CFG_BUS_CLK_HZ
47#define tmrHw_HIGH_FREQUENCY_MHZ (HW_CFG_BUS_CLK_HZ / 1000000)
48#endif
49
50#define tmrHw_LOW_RESOLUTION_CLOCK tmrHw_LOW_FREQUENCY_HZ
51#define tmrHw_HIGH_RESOLUTION_CLOCK tmrHw_HIGH_FREQUENCY_HZ
52#define tmrHw_MAX_COUNT (0xFFFFFFFF) /* maximum number of count a timer can count */
53#define tmrHw_TIMER_NUM_COUNT (4) /* Number of timer module supported */
54
55typedef struct {
56 uint32_t LoadValue; /* Load value for timer */
57 uint32_t CurrentValue; /* Current value for timer */
58 uint32_t Control; /* Control register */
59 uint32_t InterruptClear; /* Interrupt clear register */
60 uint32_t RawInterruptStatus; /* Raw interrupt status */
61 uint32_t InterruptStatus; /* Masked interrupt status */
62 uint32_t BackgroundLoad; /* Background load value */
63 uint32_t padding; /* Padding register */
64} tmrHw_REG_t;
65
66/* Control bot masks */
67#define tmrHw_CONTROL_TIMER_ENABLE 0x00000080
68#define tmrHw_CONTROL_PERIODIC 0x00000040
69#define tmrHw_CONTROL_INTERRUPT_ENABLE 0x00000020
70#define tmrHw_CONTROL_PRESCALE_MASK 0x0000000C
71#define tmrHw_CONTROL_PRESCALE_1 0x00000000
72#define tmrHw_CONTROL_PRESCALE_16 0x00000004
73#define tmrHw_CONTROL_PRESCALE_256 0x00000008
74#define tmrHw_CONTROL_32BIT 0x00000002
75#define tmrHw_CONTROL_ONESHOT 0x00000001
76#define tmrHw_CONTROL_FREE_RUNNING 0x00000000
77
78#define tmrHw_CONTROL_MODE_MASK (tmrHw_CONTROL_PERIODIC | tmrHw_CONTROL_ONESHOT)
79
80#define pTmrHw ((volatile tmrHw_REG_t *)tmrHw_MODULE_BASE_ADDR)
81
82#endif /* _TMRHW_REG_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-15 17:37:24 -0400