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-rw-r--r--arch/arm/mach-at91/include/mach/at91_aic.h48
-rw-r--r--arch/arm/mach-at91/include/mach/at91_dbgu.h2
-rw-r--r--arch/arm/mach-at91/include/mach/at91_pit.h8
-rw-r--r--arch/arm/mach-at91/include/mach/at91_rtc.h24
-rw-r--r--arch/arm/mach-at91/include/mach/at91_shdwc.h16
-rw-r--r--arch/arm/mach-at91/include/mach/at91cap9.h27
-rw-r--r--arch/arm/mach-at91/include/mach/at91rm9200.h14
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9260.h23
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9261.h20
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9263.h33
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9_smc.h17
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9g45.h30
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9rl.h29
-rw-r--r--arch/arm/mach-at91/include/mach/at91x40.h1
-rw-r--r--arch/arm/mach-at91/include/mach/board.h42
-rw-r--r--arch/arm/mach-at91/include/mach/debug-macro.S10
-rw-r--r--arch/arm/mach-at91/include/mach/entry-macro.S11
-rw-r--r--arch/arm/mach-at91/include/mach/gpio.h336
-rw-r--r--arch/arm/mach-at91/include/mach/hardware.h12
-rw-r--r--arch/arm/mach-at91/include/mach/irqs.h2
-rw-r--r--arch/arm/mach-at91/include/mach/system.h9
-rw-r--r--arch/arm/mach-at91/include/mach/timex.h65
-rw-r--r--arch/arm/mach-at91/include/mach/uncompress.h6
23 files changed, 371 insertions, 414 deletions
diff --git a/arch/arm/mach-at91/include/mach/at91_aic.h b/arch/arm/mach-at91/include/mach/at91_aic.h
index 03566799d3b..3045781c473 100644
--- a/arch/arm/mach-at91/include/mach/at91_aic.h
+++ b/arch/arm/mach-at91/include/mach/at91_aic.h
@@ -16,7 +16,19 @@
16#ifndef AT91_AIC_H 16#ifndef AT91_AIC_H
17#define AT91_AIC_H 17#define AT91_AIC_H
18 18
19#define AT91_AIC_SMR(n) (AT91_AIC + ((n) * 4)) /* Source Mode Registers 0-31 */ 19#ifndef __ASSEMBLY__
20extern void __iomem *at91_aic_base;
21
22#define at91_aic_read(field) \
23 __raw_readl(at91_aic_base + field)
24
25#define at91_aic_write(field, value) \
26 __raw_writel(value, at91_aic_base + field);
27#else
28.extern at91_aic_base
29#endif
30
31#define AT91_AIC_SMR(n) ((n) * 4) /* Source Mode Registers 0-31 */
20#define AT91_AIC_PRIOR (7 << 0) /* Priority Level */ 32#define AT91_AIC_PRIOR (7 << 0) /* Priority Level */
21#define AT91_AIC_SRCTYPE (3 << 5) /* Interrupt Source Type */ 33#define AT91_AIC_SRCTYPE (3 << 5) /* Interrupt Source Type */
22#define AT91_AIC_SRCTYPE_LOW (0 << 5) 34#define AT91_AIC_SRCTYPE_LOW (0 << 5)
@@ -24,30 +36,30 @@
24#define AT91_AIC_SRCTYPE_HIGH (2 << 5) 36#define AT91_AIC_SRCTYPE_HIGH (2 << 5)
25#define AT91_AIC_SRCTYPE_RISING (3 << 5) 37#define AT91_AIC_SRCTYPE_RISING (3 << 5)
26 38
27#define AT91_AIC_SVR(n) (AT91_AIC + 0x80 + ((n) * 4)) /* Source Vector Registers 0-31 */ 39#define AT91_AIC_SVR(n) (0x80 + ((n) * 4)) /* Source Vector Registers 0-31 */
28#define AT91_AIC_IVR (AT91_AIC + 0x100) /* Interrupt Vector Register */ 40#define AT91_AIC_IVR 0x100 /* Interrupt Vector Register */
29#define AT91_AIC_FVR (AT91_AIC + 0x104) /* Fast Interrupt Vector Register */ 41#define AT91_AIC_FVR 0x104 /* Fast Interrupt Vector Register */
30#define AT91_AIC_ISR (AT91_AIC + 0x108) /* Interrupt Status Register */ 42#define AT91_AIC_ISR 0x108 /* Interrupt Status Register */
31#define AT91_AIC_IRQID (0x1f << 0) /* Current Interrupt Identifier */ 43#define AT91_AIC_IRQID (0x1f << 0) /* Current Interrupt Identifier */
32 44
33#define AT91_AIC_IPR (AT91_AIC + 0x10c) /* Interrupt Pending Register */ 45#define AT91_AIC_IPR 0x10c /* Interrupt Pending Register */
34#define AT91_AIC_IMR (AT91_AIC + 0x110) /* Interrupt Mask Register */ 46#define AT91_AIC_IMR 0x110 /* Interrupt Mask Register */
35#define AT91_AIC_CISR (AT91_AIC + 0x114) /* Core Interrupt Status Register */ 47#define AT91_AIC_CISR 0x114 /* Core Interrupt Status Register */
36#define AT91_AIC_NFIQ (1 << 0) /* nFIQ Status */ 48#define AT91_AIC_NFIQ (1 << 0) /* nFIQ Status */
37#define AT91_AIC_NIRQ (1 << 1) /* nIRQ Status */ 49#define AT91_AIC_NIRQ (1 << 1) /* nIRQ Status */
38 50
39#define AT91_AIC_IECR (AT91_AIC + 0x120) /* Interrupt Enable Command Register */ 51#define AT91_AIC_IECR 0x120 /* Interrupt Enable Command Register */
40#define AT91_AIC_IDCR (AT91_AIC + 0x124) /* Interrupt Disable Command Register */ 52#define AT91_AIC_IDCR 0x124 /* Interrupt Disable Command Register */
41#define AT91_AIC_ICCR (AT91_AIC + 0x128) /* Interrupt Clear Command Register */ 53#define AT91_AIC_ICCR 0x128 /* Interrupt Clear Command Register */
42#define AT91_AIC_ISCR (AT91_AIC + 0x12c) /* Interrupt Set Command Register */ 54#define AT91_AIC_ISCR 0x12c /* Interrupt Set Command Register */
43#define AT91_AIC_EOICR (AT91_AIC + 0x130) /* End of Interrupt Command Register */ 55#define AT91_AIC_EOICR 0x130 /* End of Interrupt Command Register */
44#define AT91_AIC_SPU (AT91_AIC + 0x134) /* Spurious Interrupt Vector Register */ 56#define AT91_AIC_SPU 0x134 /* Spurious Interrupt Vector Register */
45#define AT91_AIC_DCR (AT91_AIC + 0x138) /* Debug Control Register */ 57#define AT91_AIC_DCR 0x138 /* Debug Control Register */
46#define AT91_AIC_DCR_PROT (1 << 0) /* Protection Mode */ 58#define AT91_AIC_DCR_PROT (1 << 0) /* Protection Mode */
47#define AT91_AIC_DCR_GMSK (1 << 1) /* General Mask */ 59#define AT91_AIC_DCR_GMSK (1 << 1) /* General Mask */
48 60
49#define AT91_AIC_FFER (AT91_AIC + 0x140) /* Fast Forcing Enable Register [SAM9 only] */ 61#define AT91_AIC_FFER 0x140 /* Fast Forcing Enable Register [SAM9 only] */
50#define AT91_AIC_FFDR (AT91_AIC + 0x144) /* Fast Forcing Disable Register [SAM9 only] */ 62#define AT91_AIC_FFDR 0x144 /* Fast Forcing Disable Register [SAM9 only] */
51#define AT91_AIC_FFSR (AT91_AIC + 0x148) /* Fast Forcing Status Register [SAM9 only] */ 63#define AT91_AIC_FFSR 0x148 /* Fast Forcing Status Register [SAM9 only] */
52 64
53#endif 65#endif
diff --git a/arch/arm/mach-at91/include/mach/at91_dbgu.h b/arch/arm/mach-at91/include/mach/at91_dbgu.h
index dbfe455a4c4..2aa0c5e1349 100644
--- a/arch/arm/mach-at91/include/mach/at91_dbgu.h
+++ b/arch/arm/mach-at91/include/mach/at91_dbgu.h
@@ -19,7 +19,7 @@
19#define dbgu_readl(dbgu, field) \ 19#define dbgu_readl(dbgu, field) \
20 __raw_readl(AT91_VA_BASE_SYS + dbgu + AT91_DBGU_ ## field) 20 __raw_readl(AT91_VA_BASE_SYS + dbgu + AT91_DBGU_ ## field)
21 21
22#ifdef AT91_DBGU 22#if !defined(CONFIG_ARCH_AT91X40)
23#define AT91_DBGU_CR (0x00) /* Control Register */ 23#define AT91_DBGU_CR (0x00) /* Control Register */
24#define AT91_DBGU_MR (0x04) /* Mode Register */ 24#define AT91_DBGU_MR (0x04) /* Mode Register */
25#define AT91_DBGU_IER (0x08) /* Interrupt Enable Register */ 25#define AT91_DBGU_IER (0x08) /* Interrupt Enable Register */
diff --git a/arch/arm/mach-at91/include/mach/at91_pit.h b/arch/arm/mach-at91/include/mach/at91_pit.h
index 974d0bd05b5..d1f80ad7f4d 100644
--- a/arch/arm/mach-at91/include/mach/at91_pit.h
+++ b/arch/arm/mach-at91/include/mach/at91_pit.h
@@ -16,16 +16,16 @@
16#ifndef AT91_PIT_H 16#ifndef AT91_PIT_H
17#define AT91_PIT_H 17#define AT91_PIT_H
18 18
19#define AT91_PIT_MR (AT91_PIT + 0x00) /* Mode Register */ 19#define AT91_PIT_MR 0x00 /* Mode Register */
20#define AT91_PIT_PITIEN (1 << 25) /* Timer Interrupt Enable */ 20#define AT91_PIT_PITIEN (1 << 25) /* Timer Interrupt Enable */
21#define AT91_PIT_PITEN (1 << 24) /* Timer Enabled */ 21#define AT91_PIT_PITEN (1 << 24) /* Timer Enabled */
22#define AT91_PIT_PIV (0xfffff) /* Periodic Interval Value */ 22#define AT91_PIT_PIV (0xfffff) /* Periodic Interval Value */
23 23
24#define AT91_PIT_SR (AT91_PIT + 0x04) /* Status Register */ 24#define AT91_PIT_SR 0x04 /* Status Register */
25#define AT91_PIT_PITS (1 << 0) /* Timer Status */ 25#define AT91_PIT_PITS (1 << 0) /* Timer Status */
26 26
27#define AT91_PIT_PIVR (AT91_PIT + 0x08) /* Periodic Interval Value Register */ 27#define AT91_PIT_PIVR 0x08 /* Periodic Interval Value Register */
28#define AT91_PIT_PIIR (AT91_PIT + 0x0c) /* Periodic Interval Image Register */ 28#define AT91_PIT_PIIR 0x0c /* Periodic Interval Image Register */
29#define AT91_PIT_PICNT (0xfff << 20) /* Interval Counter */ 29#define AT91_PIT_PICNT (0xfff << 20) /* Interval Counter */
30#define AT91_PIT_CPIV (0xfffff) /* Inverval Value */ 30#define AT91_PIT_CPIV (0xfffff) /* Inverval Value */
31 31
diff --git a/arch/arm/mach-at91/include/mach/at91_rtc.h b/arch/arm/mach-at91/include/mach/at91_rtc.h
index e56f4701a3e..da1945e5f71 100644
--- a/arch/arm/mach-at91/include/mach/at91_rtc.h
+++ b/arch/arm/mach-at91/include/mach/at91_rtc.h
@@ -16,7 +16,7 @@
16#ifndef AT91_RTC_H 16#ifndef AT91_RTC_H
17#define AT91_RTC_H 17#define AT91_RTC_H
18 18
19#define AT91_RTC_CR (AT91_RTC + 0x00) /* Control Register */ 19#define AT91_RTC_CR 0x00 /* Control Register */
20#define AT91_RTC_UPDTIM (1 << 0) /* Update Request Time Register */ 20#define AT91_RTC_UPDTIM (1 << 0) /* Update Request Time Register */
21#define AT91_RTC_UPDCAL (1 << 1) /* Update Request Calendar Register */ 21#define AT91_RTC_UPDCAL (1 << 1) /* Update Request Calendar Register */
22#define AT91_RTC_TIMEVSEL (3 << 8) /* Time Event Selection */ 22#define AT91_RTC_TIMEVSEL (3 << 8) /* Time Event Selection */
@@ -29,44 +29,44 @@
29#define AT91_RTC_CALEVSEL_MONTH (1 << 16) 29#define AT91_RTC_CALEVSEL_MONTH (1 << 16)
30#define AT91_RTC_CALEVSEL_YEAR (2 << 16) 30#define AT91_RTC_CALEVSEL_YEAR (2 << 16)
31 31
32#define AT91_RTC_MR (AT91_RTC + 0x04) /* Mode Register */ 32#define AT91_RTC_MR 0x04 /* Mode Register */
33#define AT91_RTC_HRMOD (1 << 0) /* 12/24 Hour Mode */ 33#define AT91_RTC_HRMOD (1 << 0) /* 12/24 Hour Mode */
34 34
35#define AT91_RTC_TIMR (AT91_RTC + 0x08) /* Time Register */ 35#define AT91_RTC_TIMR 0x08 /* Time Register */
36#define AT91_RTC_SEC (0x7f << 0) /* Current Second */ 36#define AT91_RTC_SEC (0x7f << 0) /* Current Second */
37#define AT91_RTC_MIN (0x7f << 8) /* Current Minute */ 37#define AT91_RTC_MIN (0x7f << 8) /* Current Minute */
38#define AT91_RTC_HOUR (0x3f << 16) /* Current Hour */ 38#define AT91_RTC_HOUR (0x3f << 16) /* Current Hour */
39#define AT91_RTC_AMPM (1 << 22) /* Ante Meridiem Post Meridiem Indicator */ 39#define AT91_RTC_AMPM (1 << 22) /* Ante Meridiem Post Meridiem Indicator */
40 40
41#define AT91_RTC_CALR (AT91_RTC + 0x0c) /* Calendar Register */ 41#define AT91_RTC_CALR 0x0c /* Calendar Register */
42#define AT91_RTC_CENT (0x7f << 0) /* Current Century */ 42#define AT91_RTC_CENT (0x7f << 0) /* Current Century */
43#define AT91_RTC_YEAR (0xff << 8) /* Current Year */ 43#define AT91_RTC_YEAR (0xff << 8) /* Current Year */
44#define AT91_RTC_MONTH (0x1f << 16) /* Current Month */ 44#define AT91_RTC_MONTH (0x1f << 16) /* Current Month */
45#define AT91_RTC_DAY (7 << 21) /* Current Day */ 45#define AT91_RTC_DAY (7 << 21) /* Current Day */
46#define AT91_RTC_DATE (0x3f << 24) /* Current Date */ 46#define AT91_RTC_DATE (0x3f << 24) /* Current Date */
47 47
48#define AT91_RTC_TIMALR (AT91_RTC + 0x10) /* Time Alarm Register */ 48#define AT91_RTC_TIMALR 0x10 /* Time Alarm Register */
49#define AT91_RTC_SECEN (1 << 7) /* Second Alarm Enable */ 49#define AT91_RTC_SECEN (1 << 7) /* Second Alarm Enable */
50#define AT91_RTC_MINEN (1 << 15) /* Minute Alarm Enable */ 50#define AT91_RTC_MINEN (1 << 15) /* Minute Alarm Enable */
51#define AT91_RTC_HOUREN (1 << 23) /* Hour Alarm Enable */ 51#define AT91_RTC_HOUREN (1 << 23) /* Hour Alarm Enable */
52 52
53#define AT91_RTC_CALALR (AT91_RTC + 0x14) /* Calendar Alarm Register */ 53#define AT91_RTC_CALALR 0x14 /* Calendar Alarm Register */
54#define AT91_RTC_MTHEN (1 << 23) /* Month Alarm Enable */ 54#define AT91_RTC_MTHEN (1 << 23) /* Month Alarm Enable */
55#define AT91_RTC_DATEEN (1 << 31) /* Date Alarm Enable */ 55#define AT91_RTC_DATEEN (1 << 31) /* Date Alarm Enable */
56 56
57#define AT91_RTC_SR (AT91_RTC + 0x18) /* Status Register */ 57#define AT91_RTC_SR 0x18 /* Status Register */
58#define AT91_RTC_ACKUPD (1 << 0) /* Acknowledge for Update */ 58#define AT91_RTC_ACKUPD (1 << 0) /* Acknowledge for Update */
59#define AT91_RTC_ALARM (1 << 1) /* Alarm Flag */ 59#define AT91_RTC_ALARM (1 << 1) /* Alarm Flag */
60#define AT91_RTC_SECEV (1 << 2) /* Second Event */ 60#define AT91_RTC_SECEV (1 << 2) /* Second Event */
61#define AT91_RTC_TIMEV (1 << 3) /* Time Event */ 61#define AT91_RTC_TIMEV (1 << 3) /* Time Event */
62#define AT91_RTC_CALEV (1 << 4) /* Calendar Event */ 62#define AT91_RTC_CALEV (1 << 4) /* Calendar Event */
63 63
64#define AT91_RTC_SCCR (AT91_RTC + 0x1c) /* Status Clear Command Register */ 64#define AT91_RTC_SCCR 0x1c /* Status Clear Command Register */
65#define AT91_RTC_IER (AT91_RTC + 0x20) /* Interrupt Enable Register */ 65#define AT91_RTC_IER 0x20 /* Interrupt Enable Register */
66#define AT91_RTC_IDR (AT91_RTC + 0x24) /* Interrupt Disable Register */ 66#define AT91_RTC_IDR 0x24 /* Interrupt Disable Register */
67#define AT91_RTC_IMR (AT91_RTC + 0x28) /* Interrupt Mask Register */ 67#define AT91_RTC_IMR 0x28 /* Interrupt Mask Register */
68 68
69#define AT91_RTC_VER (AT91_RTC + 0x2c) /* Valid Entry Register */ 69#define AT91_RTC_VER 0x2c /* Valid Entry Register */
70#define AT91_RTC_NVTIM (1 << 0) /* Non valid Time */ 70#define AT91_RTC_NVTIM (1 << 0) /* Non valid Time */
71#define AT91_RTC_NVCAL (1 << 1) /* Non valid Calendar */ 71#define AT91_RTC_NVCAL (1 << 1) /* Non valid Calendar */
72#define AT91_RTC_NVTIMALR (1 << 2) /* Non valid Time Alarm */ 72#define AT91_RTC_NVTIMALR (1 << 2) /* Non valid Time Alarm */
diff --git a/arch/arm/mach-at91/include/mach/at91_shdwc.h b/arch/arm/mach-at91/include/mach/at91_shdwc.h
index c4ce07e8a8f..1d4fe822c77 100644
--- a/arch/arm/mach-at91/include/mach/at91_shdwc.h
+++ b/arch/arm/mach-at91/include/mach/at91_shdwc.h
@@ -16,11 +16,21 @@
16#ifndef AT91_SHDWC_H 16#ifndef AT91_SHDWC_H
17#define AT91_SHDWC_H 17#define AT91_SHDWC_H
18 18
19#define AT91_SHDW_CR (AT91_SHDWC + 0x00) /* Shut Down Control Register */ 19#ifndef __ASSEMBLY__
20extern void __iomem *at91_shdwc_base;
21
22#define at91_shdwc_read(field) \
23 __raw_readl(at91_shdwc_base + field)
24
25#define at91_shdwc_write(field, value) \
26 __raw_writel(value, at91_shdwc_base + field);
27#endif
28
29#define AT91_SHDW_CR 0x00 /* Shut Down Control Register */
20#define AT91_SHDW_SHDW (1 << 0) /* Shut Down command */ 30#define AT91_SHDW_SHDW (1 << 0) /* Shut Down command */
21#define AT91_SHDW_KEY (0xa5 << 24) /* KEY Password */ 31#define AT91_SHDW_KEY (0xa5 << 24) /* KEY Password */
22 32
23#define AT91_SHDW_MR (AT91_SHDWC + 0x04) /* Shut Down Mode Register */ 33#define AT91_SHDW_MR 0x04 /* Shut Down Mode Register */
24#define AT91_SHDW_WKMODE0 (3 << 0) /* Wake-up 0 Mode Selection */ 34#define AT91_SHDW_WKMODE0 (3 << 0) /* Wake-up 0 Mode Selection */
25#define AT91_SHDW_WKMODE0_NONE 0 35#define AT91_SHDW_WKMODE0_NONE 0
26#define AT91_SHDW_WKMODE0_HIGH 1 36#define AT91_SHDW_WKMODE0_HIGH 1
@@ -30,7 +40,7 @@
30#define AT91_SHDW_CPTWK0_(x) ((x) << 4) 40#define AT91_SHDW_CPTWK0_(x) ((x) << 4)
31#define AT91_SHDW_RTTWKEN (1 << 16) /* Real Time Timer Wake-up Enable */ 41#define AT91_SHDW_RTTWKEN (1 << 16) /* Real Time Timer Wake-up Enable */
32 42
33#define AT91_SHDW_SR (AT91_SHDWC + 0x08) /* Shut Down Status Register */ 43#define AT91_SHDW_SR 0x08 /* Shut Down Status Register */
34#define AT91_SHDW_WAKEUP0 (1 << 0) /* Wake-up 0 Status */ 44#define AT91_SHDW_WAKEUP0 (1 << 0) /* Wake-up 0 Status */
35#define AT91_SHDW_RTTWK (1 << 16) /* Real-time Timer Wake-up */ 45#define AT91_SHDW_RTTWK (1 << 16) /* Real-time Timer Wake-up */
36#define AT91_SHDW_RTCWK (1 << 17) /* Real-time Clock Wake-up [SAM9RL] */ 46#define AT91_SHDW_RTCWK (1 << 17) /* Real-time Clock Wake-up [SAM9RL] */
diff --git a/arch/arm/mach-at91/include/mach/at91cap9.h b/arch/arm/mach-at91/include/mach/at91cap9.h
index c5df1e8f195..4c0e2f6011d 100644
--- a/arch/arm/mach-at91/include/mach/at91cap9.h
+++ b/arch/arm/mach-at91/include/mach/at91cap9.h
@@ -79,29 +79,28 @@
79/* 79/*
80 * System Peripherals (offset from AT91_BASE_SYS) 80 * System Peripherals (offset from AT91_BASE_SYS)
81 */ 81 */
82#define AT91_ECC (0xffffe200 - AT91_BASE_SYS)
83#define AT91_BCRAMC (0xffffe400 - AT91_BASE_SYS) 82#define AT91_BCRAMC (0xffffe400 - AT91_BASE_SYS)
84#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS) 83#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS)
85#define AT91_SMC (0xffffe800 - AT91_BASE_SYS)
86#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS) 84#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS)
87#define AT91_CCFG (0xffffeb10 - AT91_BASE_SYS)
88#define AT91_DMA (0xffffec00 - AT91_BASE_SYS)
89#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
90#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
91#define AT91_PIOA (0xfffff200 - AT91_BASE_SYS)
92#define AT91_PIOB (0xfffff400 - AT91_BASE_SYS)
93#define AT91_PIOC (0xfffff600 - AT91_BASE_SYS)
94#define AT91_PIOD (0xfffff800 - AT91_BASE_SYS)
95#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) 85#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
96#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) 86#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
97#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
98#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
99#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
100#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
101#define AT91_GPBR (cpu_is_at91cap9_revB() ? \ 87#define AT91_GPBR (cpu_is_at91cap9_revB() ? \
102 (0xfffffd50 - AT91_BASE_SYS) : \ 88 (0xfffffd50 - AT91_BASE_SYS) : \
103 (0xfffffd60 - AT91_BASE_SYS)) 89 (0xfffffd60 - AT91_BASE_SYS))
104 90
91#define AT91CAP9_BASE_ECC 0xffffe200
92#define AT91CAP9_BASE_DMA 0xffffec00
93#define AT91CAP9_BASE_SMC 0xffffe800
94#define AT91CAP9_BASE_DBGU AT91_BASE_DBGU1
95#define AT91CAP9_BASE_PIOA 0xfffff200
96#define AT91CAP9_BASE_PIOB 0xfffff400
97#define AT91CAP9_BASE_PIOC 0xfffff600
98#define AT91CAP9_BASE_PIOD 0xfffff800
99#define AT91CAP9_BASE_SHDWC 0xfffffd10
100#define AT91CAP9_BASE_RTT 0xfffffd20
101#define AT91CAP9_BASE_PIT 0xfffffd30
102#define AT91CAP9_BASE_WDT 0xfffffd40
103
105#define AT91_USART0 AT91CAP9_BASE_US0 104#define AT91_USART0 AT91CAP9_BASE_US0
106#define AT91_USART1 AT91CAP9_BASE_US1 105#define AT91_USART1 AT91CAP9_BASE_US1
107#define AT91_USART2 AT91CAP9_BASE_US2 106#define AT91_USART2 AT91CAP9_BASE_US2
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200.h b/arch/arm/mach-at91/include/mach/at91rm9200.h
index e4037b50030..bacb5114181 100644
--- a/arch/arm/mach-at91/include/mach/at91rm9200.h
+++ b/arch/arm/mach-at91/include/mach/at91rm9200.h
@@ -79,17 +79,17 @@
79/* 79/*
80 * System Peripherals (offset from AT91_BASE_SYS) 80 * System Peripherals (offset from AT91_BASE_SYS)
81 */ 81 */
82#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) /* Advanced Interrupt Controller */
83#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) /* Debug Unit */
84#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) /* PIO Controller A */
85#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) /* PIO Controller B */
86#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) /* PIO Controller C */
87#define AT91_PIOD (0xfffffa00 - AT91_BASE_SYS) /* PIO Controller D */
88#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) /* Power Management Controller */ 82#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) /* Power Management Controller */
89#define AT91_ST (0xfffffd00 - AT91_BASE_SYS) /* System Timer */ 83#define AT91_ST (0xfffffd00 - AT91_BASE_SYS) /* System Timer */
90#define AT91_RTC (0xfffffe00 - AT91_BASE_SYS) /* Real-Time Clock */
91#define AT91_MC (0xffffff00 - AT91_BASE_SYS) /* Memory Controllers */ 84#define AT91_MC (0xffffff00 - AT91_BASE_SYS) /* Memory Controllers */
92 85
86#define AT91RM9200_BASE_DBGU AT91_BASE_DBGU0 /* Debug Unit */
87#define AT91RM9200_BASE_PIOA 0xfffff400 /* PIO Controller A */
88#define AT91RM9200_BASE_PIOB 0xfffff600 /* PIO Controller B */
89#define AT91RM9200_BASE_PIOC 0xfffff800 /* PIO Controller C */
90#define AT91RM9200_BASE_PIOD 0xfffffa00 /* PIO Controller D */
91#define AT91RM9200_BASE_RTC 0xfffffe00 /* Real-Time Clock */
92
93#define AT91_USART0 AT91RM9200_BASE_US0 93#define AT91_USART0 AT91RM9200_BASE_US0
94#define AT91_USART1 AT91RM9200_BASE_US1 94#define AT91_USART1 AT91RM9200_BASE_US1
95#define AT91_USART2 AT91RM9200_BASE_US2 95#define AT91_USART2 AT91RM9200_BASE_US2
diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h
index 9a791165913..f937c476bb6 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9260.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9260.h
@@ -80,24 +80,23 @@
80/* 80/*
81 * System Peripherals (offset from AT91_BASE_SYS) 81 * System Peripherals (offset from AT91_BASE_SYS)
82 */ 82 */
83#define AT91_ECC (0xffffe800 - AT91_BASE_SYS)
84#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS) 83#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
85#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
86#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) 84#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
87#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS)
88#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
89#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
90#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS)
91#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS)
92#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS)
93#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) 85#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
94#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) 86#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
95#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
96#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
97#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
98#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
99#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) 87#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
100 88
89#define AT91SAM9260_BASE_ECC 0xffffe800
90#define AT91SAM9260_BASE_SMC 0xffffec00
91#define AT91SAM9260_BASE_DBGU AT91_BASE_DBGU0
92#define AT91SAM9260_BASE_PIOA 0xfffff400
93#define AT91SAM9260_BASE_PIOB 0xfffff600
94#define AT91SAM9260_BASE_PIOC 0xfffff800
95#define AT91SAM9260_BASE_SHDWC 0xfffffd10
96#define AT91SAM9260_BASE_RTT 0xfffffd20
97#define AT91SAM9260_BASE_PIT 0xfffffd30
98#define AT91SAM9260_BASE_WDT 0xfffffd40
99
101#define AT91_USART0 AT91SAM9260_BASE_US0 100#define AT91_USART0 AT91SAM9260_BASE_US0
102#define AT91_USART1 AT91SAM9260_BASE_US1 101#define AT91_USART1 AT91SAM9260_BASE_US1
103#define AT91_USART2 AT91SAM9260_BASE_US2 102#define AT91_USART2 AT91SAM9260_BASE_US2
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h
index ce596204cef..175604e261b 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9261.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9261.h
@@ -66,21 +66,21 @@
66 * System Peripherals (offset from AT91_BASE_SYS) 66 * System Peripherals (offset from AT91_BASE_SYS)
67 */ 67 */
68#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS) 68#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
69#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
70#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) 69#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
71#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
72#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
73#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS)
74#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS)
75#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS)
76#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) 70#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
77#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) 71#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
78#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
79#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
80#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
81#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
82#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) 72#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
83 73
74#define AT91SAM9261_BASE_SMC 0xffffec00
75#define AT91SAM9261_BASE_DBGU AT91_BASE_DBGU0
76#define AT91SAM9261_BASE_PIOA 0xfffff400
77#define AT91SAM9261_BASE_PIOB 0xfffff600
78#define AT91SAM9261_BASE_PIOC 0xfffff800
79#define AT91SAM9261_BASE_SHDWC 0xfffffd10
80#define AT91SAM9261_BASE_RTT 0xfffffd20
81#define AT91SAM9261_BASE_PIT 0xfffffd30
82#define AT91SAM9261_BASE_WDT 0xfffffd40
83
84#define AT91_USART0 AT91SAM9261_BASE_US0 84#define AT91_USART0 AT91SAM9261_BASE_US0
85#define AT91_USART1 AT91SAM9261_BASE_US1 85#define AT91_USART1 AT91SAM9261_BASE_US1
86#define AT91_USART2 AT91SAM9261_BASE_US2 86#define AT91_USART2 AT91SAM9261_BASE_US2
diff --git a/arch/arm/mach-at91/include/mach/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h
index f1b92961a2b..80c915002d8 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9263.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9263.h
@@ -74,30 +74,29 @@
74/* 74/*
75 * System Peripherals (offset from AT91_BASE_SYS) 75 * System Peripherals (offset from AT91_BASE_SYS)
76 */ 76 */
77#define AT91_ECC0 (0xffffe000 - AT91_BASE_SYS)
78#define AT91_SDRAMC0 (0xffffe200 - AT91_BASE_SYS) 77#define AT91_SDRAMC0 (0xffffe200 - AT91_BASE_SYS)
79#define AT91_SMC0 (0xffffe400 - AT91_BASE_SYS)
80#define AT91_ECC1 (0xffffe600 - AT91_BASE_SYS)
81#define AT91_SDRAMC1 (0xffffe800 - AT91_BASE_SYS) 78#define AT91_SDRAMC1 (0xffffe800 - AT91_BASE_SYS)
82#define AT91_SMC1 (0xffffea00 - AT91_BASE_SYS)
83#define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS) 79#define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS)
84#define AT91_CCFG (0xffffed10 - AT91_BASE_SYS)
85#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
86#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
87#define AT91_PIOA (0xfffff200 - AT91_BASE_SYS)
88#define AT91_PIOB (0xfffff400 - AT91_BASE_SYS)
89#define AT91_PIOC (0xfffff600 - AT91_BASE_SYS)
90#define AT91_PIOD (0xfffff800 - AT91_BASE_SYS)
91#define AT91_PIOE (0xfffffa00 - AT91_BASE_SYS)
92#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) 80#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
93#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) 81#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
94#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
95#define AT91_RTT0 (0xfffffd20 - AT91_BASE_SYS)
96#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
97#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
98#define AT91_RTT1 (0xfffffd50 - AT91_BASE_SYS)
99#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) 82#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
100 83
84#define AT91SAM9263_BASE_ECC0 0xffffe000
85#define AT91SAM9263_BASE_SMC0 0xffffe400
86#define AT91SAM9263_BASE_ECC1 0xffffe600
87#define AT91SAM9263_BASE_SMC1 0xffffea00
88#define AT91SAM9263_BASE_DBGU AT91_BASE_DBGU1
89#define AT91SAM9263_BASE_PIOA 0xfffff200
90#define AT91SAM9263_BASE_PIOB 0xfffff400
91#define AT91SAM9263_BASE_PIOC 0xfffff600
92#define AT91SAM9263_BASE_PIOD 0xfffff800
93#define AT91SAM9263_BASE_PIOE 0xfffffa00
94#define AT91SAM9263_BASE_SHDWC 0xfffffd10
95#define AT91SAM9263_BASE_RTT0 0xfffffd20
96#define AT91SAM9263_BASE_PIT 0xfffffd30
97#define AT91SAM9263_BASE_WDT 0xfffffd40
98#define AT91SAM9263_BASE_RTT1 0xfffffd50
99
101#define AT91_USART0 AT91SAM9263_BASE_US0 100#define AT91_USART0 AT91SAM9263_BASE_US0
102#define AT91_USART1 AT91SAM9263_BASE_US1 101#define AT91_USART1 AT91SAM9263_BASE_US1
103#define AT91_USART2 AT91SAM9263_BASE_US2 102#define AT91_USART2 AT91SAM9263_BASE_US2
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_smc.h b/arch/arm/mach-at91/include/mach/at91sam9_smc.h
index 57de6207e57..eb18a70fa64 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9_smc.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_smc.h
@@ -16,7 +16,9 @@
16#ifndef AT91SAM9_SMC_H 16#ifndef AT91SAM9_SMC_H
17#define AT91SAM9_SMC_H 17#define AT91SAM9_SMC_H
18 18
19#define AT91_SMC_SETUP(n) (AT91_SMC + 0x00 + ((n)*0x10)) /* Setup Register for CS n */ 19#include <mach/cpu.h>
20
21#define AT91_SMC_SETUP 0x00 /* Setup Register for CS n */
20#define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */ 22#define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */
21#define AT91_SMC_NWESETUP_(x) ((x) << 0) 23#define AT91_SMC_NWESETUP_(x) ((x) << 0)
22#define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS Setup Length in Write Access */ 24#define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS Setup Length in Write Access */
@@ -26,7 +28,7 @@
26#define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS Setup Length in Read Access */ 28#define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS Setup Length in Read Access */
27#define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24) 29#define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24)
28 30
29#define AT91_SMC_PULSE(n) (AT91_SMC + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */ 31#define AT91_SMC_PULSE 0x04 /* Pulse Register for CS n */
30#define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE Pulse Length */ 32#define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE Pulse Length */
31#define AT91_SMC_NWEPULSE_(x) ((x) << 0) 33#define AT91_SMC_NWEPULSE_(x) ((x) << 0)
32#define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS Pulse Length in Write Access */ 34#define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS Pulse Length in Write Access */
@@ -36,13 +38,13 @@
36#define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS Pulse Length in Read Access */ 38#define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS Pulse Length in Read Access */
37#define AT91_SMC_NCS_RDPULSE_(x)((x) << 24) 39#define AT91_SMC_NCS_RDPULSE_(x)((x) << 24)
38 40
39#define AT91_SMC_CYCLE(n) (AT91_SMC + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */ 41#define AT91_SMC_CYCLE 0x08 /* Cycle Register for CS n */
40#define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total Write Cycle Length */ 42#define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total Write Cycle Length */
41#define AT91_SMC_NWECYCLE_(x) ((x) << 0) 43#define AT91_SMC_NWECYCLE_(x) ((x) << 0)
42#define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */ 44#define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */
43#define AT91_SMC_NRDCYCLE_(x) ((x) << 16) 45#define AT91_SMC_NRDCYCLE_(x) ((x) << 16)
44 46
45#define AT91_SMC_MODE(n) (AT91_SMC + 0x0c + ((n)*0x10)) /* Mode Register for CS n */ 47#define AT91_SMC_MODE 0x0c /* Mode Register for CS n */
46#define AT91_SMC_READMODE (1 << 0) /* Read Mode */ 48#define AT91_SMC_READMODE (1 << 0) /* Read Mode */
47#define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */ 49#define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */
48#define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */ 50#define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */
@@ -66,11 +68,4 @@
66#define AT91_SMC_PS_16 (2 << 28) 68#define AT91_SMC_PS_16 (2 << 28)
67#define AT91_SMC_PS_32 (3 << 28) 69#define AT91_SMC_PS_32 (3 << 28)
68 70
69#if defined(AT91_SMC1) /* The AT91SAM9263 has 2 Static Memory contollers */
70#define AT91_SMC1_SETUP(n) (AT91_SMC1 + 0x00 + ((n)*0x10)) /* Setup Register for CS n */
71#define AT91_SMC1_PULSE(n) (AT91_SMC1 + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */
72#define AT91_SMC1_CYCLE(n) (AT91_SMC1 + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */
73#define AT91_SMC1_MODE(n) (AT91_SMC1 + 0x0c + ((n)*0x10)) /* Mode Register for CS n */
74#endif
75
76#endif 71#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h
index 406bb649680..f0c23c960de 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9g45.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h
@@ -86,27 +86,27 @@
86/* 86/*
87 * System Peripherals (offset from AT91_BASE_SYS) 87 * System Peripherals (offset from AT91_BASE_SYS)
88 */ 88 */
89#define AT91_ECC (0xffffe200 - AT91_BASE_SYS)
90#define AT91_DDRSDRC1 (0xffffe400 - AT91_BASE_SYS) 89#define AT91_DDRSDRC1 (0xffffe400 - AT91_BASE_SYS)
91#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS) 90#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS)
92#define AT91_SMC (0xffffe800 - AT91_BASE_SYS)
93#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS) 91#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS)
94#define AT91_DMA (0xffffec00 - AT91_BASE_SYS)
95#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
96#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
97#define AT91_PIOA (0xfffff200 - AT91_BASE_SYS)
98#define AT91_PIOB (0xfffff400 - AT91_BASE_SYS)
99#define AT91_PIOC (0xfffff600 - AT91_BASE_SYS)
100#define AT91_PIOD (0xfffff800 - AT91_BASE_SYS)
101#define AT91_PIOE (0xfffffa00 - AT91_BASE_SYS)
102#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) 92#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
103#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) 93#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
104#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
105#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
106#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
107#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
108#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) 94#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
109#define AT91_RTC (0xfffffdb0 - AT91_BASE_SYS) 95
96#define AT91SAM9G45_BASE_ECC 0xffffe200
97#define AT91SAM9G45_BASE_DMA 0xffffec00
98#define AT91SAM9G45_BASE_SMC 0xffffe800
99#define AT91SAM9G45_BASE_DBGU AT91_BASE_DBGU1
100#define AT91SAM9G45_BASE_PIOA 0xfffff200
101#define AT91SAM9G45_BASE_PIOB 0xfffff400
102#define AT91SAM9G45_BASE_PIOC 0xfffff600
103#define AT91SAM9G45_BASE_PIOD 0xfffff800
104#define AT91SAM9G45_BASE_PIOE 0xfffffa00
105#define AT91SAM9G45_BASE_SHDWC 0xfffffd10
106#define AT91SAM9G45_BASE_RTT 0xfffffd20
107#define AT91SAM9G45_BASE_PIT 0xfffffd30
108#define AT91SAM9G45_BASE_WDT 0xfffffd40
109#define AT91SAM9G45_BASE_RTC 0xfffffdb0
110 110
111#define AT91_USART0 AT91SAM9G45_BASE_US0 111#define AT91_USART0 AT91SAM9G45_BASE_US0
112#define AT91_USART1 AT91SAM9G45_BASE_US1 112#define AT91_USART1 AT91SAM9G45_BASE_US1
diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl.h b/arch/arm/mach-at91/include/mach/at91sam9rl.h
index 1aabacd315d..2bb359e60b9 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9rl.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9rl.h
@@ -69,27 +69,26 @@
69/* 69/*
70 * System Peripherals (offset from AT91_BASE_SYS) 70 * System Peripherals (offset from AT91_BASE_SYS)
71 */ 71 */
72#define AT91_DMA (0xffffe600 - AT91_BASE_SYS)
73#define AT91_ECC (0xffffe800 - AT91_BASE_SYS)
74#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS) 72#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
75#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
76#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) 73#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
77#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS)
78#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
79#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
80#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS)
81#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS)
82#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS)
83#define AT91_PIOD (0xfffffa00 - AT91_BASE_SYS)
84#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) 74#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
85#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) 75#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
86#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
87#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
88#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
89#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
90#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS) 76#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS)
91#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) 77#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
92#define AT91_RTC (0xfffffe00 - AT91_BASE_SYS) 78
79#define AT91SAM9RL_BASE_DMA 0xffffe600
80#define AT91SAM9RL_BASE_ECC 0xffffe800
81#define AT91SAM9RL_BASE_SMC 0xffffec00
82#define AT91SAM9RL_BASE_DBGU AT91_BASE_DBGU0
83#define AT91SAM9RL_BASE_PIOA 0xfffff400
84#define AT91SAM9RL_BASE_PIOB 0xfffff600
85#define AT91SAM9RL_BASE_PIOC 0xfffff800
86#define AT91SAM9RL_BASE_PIOD 0xfffffa00
87#define AT91SAM9RL_BASE_SHDWC 0xfffffd10
88#define AT91SAM9RL_BASE_RTT 0xfffffd20
89#define AT91SAM9RL_BASE_PIT 0xfffffd30
90#define AT91SAM9RL_BASE_WDT 0xfffffd40
91#define AT91SAM9RL_BASE_RTC 0xfffffe00
93 92
94#define AT91_USART0 AT91SAM9RL_BASE_US0 93#define AT91_USART0 AT91SAM9RL_BASE_US0
95#define AT91_USART1 AT91SAM9RL_BASE_US1 94#define AT91_USART1 AT91SAM9RL_BASE_US1
diff --git a/arch/arm/mach-at91/include/mach/at91x40.h b/arch/arm/mach-at91/include/mach/at91x40.h
index a152ff87e68..a57829f4fd1 100644
--- a/arch/arm/mach-at91/include/mach/at91x40.h
+++ b/arch/arm/mach-at91/include/mach/at91x40.h
@@ -40,7 +40,6 @@
40#define AT91_PIOA (0xffff0000 - AT91_BASE_SYS) /* PIO Controller A */ 40#define AT91_PIOA (0xffff0000 - AT91_BASE_SYS) /* PIO Controller A */
41#define AT91_PS (0xffff4000 - AT91_BASE_SYS) /* Power Save */ 41#define AT91_PS (0xffff4000 - AT91_BASE_SYS) /* Power Save */
42#define AT91_WD (0xffff8000 - AT91_BASE_SYS) /* Watchdog Timer */ 42#define AT91_WD (0xffff8000 - AT91_BASE_SYS) /* Watchdog Timer */
43#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) /* Advanced Interrupt Controller */
44 43
45/* 44/*
46 * The AT91x40 series doesn't have a debug unit like the other AT91 parts. 45 * The AT91x40 series doesn't have a debug unit like the other AT91 parts.
diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
index eac92e995bb..d0b377b21bd 100644
--- a/arch/arm/mach-at91/include/mach/board.h
+++ b/arch/arm/mach-at91/include/mach/board.h
@@ -40,13 +40,14 @@
40#include <linux/atmel-mci.h> 40#include <linux/atmel-mci.h>
41#include <sound/atmel-ac97c.h> 41#include <sound/atmel-ac97c.h>
42#include <linux/serial.h> 42#include <linux/serial.h>
43#include <linux/platform_data/macb.h>
43 44
44 /* USB Device */ 45 /* USB Device */
45struct at91_udc_data { 46struct at91_udc_data {
46 u8 vbus_pin; /* high == host powering us */ 47 int vbus_pin; /* high == host powering us */
47 u8 vbus_active_low; /* vbus polarity */ 48 u8 vbus_active_low; /* vbus polarity */
48 u8 vbus_polled; /* Use polling, not interrupt */ 49 u8 vbus_polled; /* Use polling, not interrupt */
49 u8 pullup_pin; /* active == D+ pulled up */ 50 int pullup_pin; /* active == D+ pulled up */
50 u8 pullup_active_low; /* true == pullup_pin is active low */ 51 u8 pullup_active_low; /* true == pullup_pin is active low */
51}; 52};
52extern void __init at91_add_device_udc(struct at91_udc_data *data); 53extern void __init at91_add_device_udc(struct at91_udc_data *data);
@@ -56,10 +57,10 @@ extern void __init at91_add_device_usba(struct usba_platform_data *data);
56 57
57 /* Compact Flash */ 58 /* Compact Flash */
58struct at91_cf_data { 59struct at91_cf_data {
59 u8 irq_pin; /* I/O IRQ */ 60 int irq_pin; /* I/O IRQ */
60 u8 det_pin; /* Card detect */ 61 int det_pin; /* Card detect */
61 u8 vcc_pin; /* power switching */ 62 int vcc_pin; /* power switching */
62 u8 rst_pin; /* card reset */ 63 int rst_pin; /* card reset */
63 u8 chipselect; /* EBI Chip Select number */ 64 u8 chipselect; /* EBI Chip Select number */
64 u8 flags; 65 u8 flags;
65#define AT91_CF_TRUE_IDE 0x01 66#define AT91_CF_TRUE_IDE 0x01
@@ -70,37 +71,26 @@ extern void __init at91_add_device_cf(struct at91_cf_data *data);
70 /* MMC / SD */ 71 /* MMC / SD */
71 /* at91_mci platform config */ 72 /* at91_mci platform config */
72struct at91_mmc_data { 73struct at91_mmc_data {
73 u8 det_pin; /* card detect IRQ */ 74 int det_pin; /* card detect IRQ */
74 unsigned slot_b:1; /* uses Slot B */ 75 unsigned slot_b:1; /* uses Slot B */
75 unsigned wire4:1; /* (SD) supports DAT0..DAT3 */ 76 unsigned wire4:1; /* (SD) supports DAT0..DAT3 */
76 u8 wp_pin; /* (SD) writeprotect detect */ 77 int wp_pin; /* (SD) writeprotect detect */
77 u8 vcc_pin; /* power switching (high == on) */ 78 int vcc_pin; /* power switching (high == on) */
78}; 79};
79extern void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data); 80extern void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data);
80 81
81 /* atmel-mci platform config */ 82 /* atmel-mci platform config */
82extern void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data); 83extern void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data);
83 84
84 /* Ethernet (EMAC & MACB) */ 85extern void __init at91_add_device_eth(struct macb_platform_data *data);
85struct at91_eth_data {
86 u32 phy_mask;
87 u8 phy_irq_pin; /* PHY IRQ */
88 u8 is_rmii; /* using RMII interface? */
89};
90extern void __init at91_add_device_eth(struct at91_eth_data *data);
91
92#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) || defined(CONFIG_ARCH_AT91SAM9G20) || defined(CONFIG_ARCH_AT91CAP9) \
93 || defined(CONFIG_ARCH_AT91SAM9G45)
94#define eth_platform_data at91_eth_data
95#endif
96 86
97 /* USB Host */ 87 /* USB Host */
98struct at91_usbh_data { 88struct at91_usbh_data {
99 u8 ports; /* number of ports on root hub */ 89 u8 ports; /* number of ports on root hub */
100 u8 vbus_pin[2]; /* port power-control pin */ 90 int vbus_pin[2]; /* port power-control pin */
101 u8 vbus_pin_inverted; 91 u8 vbus_pin_inverted;
102 u8 overcurrent_supported; 92 u8 overcurrent_supported;
103 u8 overcurrent_pin[2]; 93 int overcurrent_pin[2];
104 u8 overcurrent_status[2]; 94 u8 overcurrent_status[2];
105 u8 overcurrent_changed[2]; 95 u8 overcurrent_changed[2];
106}; 96};
@@ -110,9 +100,9 @@ extern void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data);
110 100
111 /* NAND / SmartMedia */ 101 /* NAND / SmartMedia */
112struct atmel_nand_data { 102struct atmel_nand_data {
113 u8 enable_pin; /* chip enable */ 103 int enable_pin; /* chip enable */
114 u8 det_pin; /* card detect */ 104 int det_pin; /* card detect */
115 u8 rdy_pin; /* ready/busy */ 105 int rdy_pin; /* ready/busy */
116 u8 rdy_pin_active_low; /* rdy_pin value is inverted */ 106 u8 rdy_pin_active_low; /* rdy_pin value is inverted */
117 u8 ale; /* address line number connected to ALE */ 107 u8 ale; /* address line number connected to ALE */
118 u8 cle; /* address line number connected to CLE */ 108 u8 cle; /* address line number connected to CLE */
diff --git a/arch/arm/mach-at91/include/mach/debug-macro.S b/arch/arm/mach-at91/include/mach/debug-macro.S
index 0ed8648c645..c6bb9e2d9ba 100644
--- a/arch/arm/mach-at91/include/mach/debug-macro.S
+++ b/arch/arm/mach-at91/include/mach/debug-macro.S
@@ -14,9 +14,15 @@
14#include <mach/hardware.h> 14#include <mach/hardware.h>
15#include <mach/at91_dbgu.h> 15#include <mach/at91_dbgu.h>
16 16
17#if defined(CONFIG_AT91_DEBUG_LL_DBGU0)
18#define AT91_DBGU AT91_BASE_DBGU0
19#else
20#define AT91_DBGU AT91_BASE_DBGU1
21#endif
22
17 .macro addruart, rp, rv, tmp 23 .macro addruart, rp, rv, tmp
18 ldr \rp, =(AT91_BASE_SYS + AT91_DBGU) @ System peripherals (phys address) 24 ldr \rp, =AT91_DBGU @ System peripherals (phys address)
19 ldr \rv, =(AT91_VA_BASE_SYS + AT91_DBGU) @ System peripherals (virt address) 25 ldr \rv, =AT91_IO_P2V(AT91_DBGU) @ System peripherals (virt address)
20 .endm 26 .endm
21 27
22 .macro senduart,rd,rx 28 .macro senduart,rd,rx
diff --git a/arch/arm/mach-at91/include/mach/entry-macro.S b/arch/arm/mach-at91/include/mach/entry-macro.S
index 7ab68f97222..423eea0ed74 100644
--- a/arch/arm/mach-at91/include/mach/entry-macro.S
+++ b/arch/arm/mach-at91/include/mach/entry-macro.S
@@ -17,16 +17,17 @@
17 .endm 17 .endm
18 18
19 .macro get_irqnr_preamble, base, tmp 19 .macro get_irqnr_preamble, base, tmp
20 ldr \base, =(AT91_VA_BASE_SYS + AT91_AIC) @ base virtual address of AIC peripheral 20 ldr \base, =at91_aic_base @ base virtual address of AIC peripheral
21 ldr \base, [\base]
21 .endm 22 .endm
22 23
23 .macro arch_ret_to_user, tmp1, tmp2 24 .macro arch_ret_to_user, tmp1, tmp2
24 .endm 25 .endm
25 26
26 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 27 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
27 ldr \irqnr, [\base, #(AT91_AIC_IVR - AT91_AIC)] @ read IRQ vector register: de-asserts nIRQ to processor (and clears interrupt) 28 ldr \irqnr, [\base, #AT91_AIC_IVR] @ read IRQ vector register: de-asserts nIRQ to processor (and clears interrupt)
28 ldr \irqstat, [\base, #(AT91_AIC_ISR - AT91_AIC)] @ read interrupt source number 29 ldr \irqstat, [\base, #AT91_AIC_ISR] @ read interrupt source number
29 teq \irqstat, #0 @ ISR is 0 when no current interrupt, or spurious interrupt 30 teq \irqstat, #0 @ ISR is 0 when no current interrupt, or spurious interrupt
30 streq \tmp, [\base, #(AT91_AIC_EOICR - AT91_AIC)] @ not going to be handled further, then ACK it now. 31 streq \tmp, [\base, #AT91_AIC_EOICR] @ not going to be handled further, then ACK it now.
31 .endm 32 .endm
32 33
diff --git a/arch/arm/mach-at91/include/mach/gpio.h b/arch/arm/mach-at91/include/mach/gpio.h
index 2b9a1f51210..e3fd225121c 100644
--- a/arch/arm/mach-at91/include/mach/gpio.h
+++ b/arch/arm/mach-at91/include/mach/gpio.h
@@ -16,177 +16,175 @@
16#include <linux/kernel.h> 16#include <linux/kernel.h>
17#include <asm/irq.h> 17#include <asm/irq.h>
18 18
19#define PIN_BASE NR_AIC_IRQS
20
21#define MAX_GPIO_BANKS 5 19#define MAX_GPIO_BANKS 5
22#define NR_BUILTIN_GPIO (PIN_BASE + (MAX_GPIO_BANKS * 32)) 20#define NR_BUILTIN_GPIO (MAX_GPIO_BANKS * 32)
23 21
24/* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */ 22/* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */
25 23
26#define AT91_PIN_PA0 (PIN_BASE + 0x00 + 0) 24#define AT91_PIN_PA0 (0x00 + 0)
27#define AT91_PIN_PA1 (PIN_BASE + 0x00 + 1) 25#define AT91_PIN_PA1 (0x00 + 1)
28#define AT91_PIN_PA2 (PIN_BASE + 0x00 + 2) 26#define AT91_PIN_PA2 (0x00 + 2)
29#define AT91_PIN_PA3 (PIN_BASE + 0x00 + 3) 27#define AT91_PIN_PA3 (0x00 + 3)
30#define AT91_PIN_PA4 (PIN_BASE + 0x00 + 4) 28#define AT91_PIN_PA4 (0x00 + 4)
31#define AT91_PIN_PA5 (PIN_BASE + 0x00 + 5) 29#define AT91_PIN_PA5 (0x00 + 5)
32#define AT91_PIN_PA6 (PIN_BASE + 0x00 + 6) 30#define AT91_PIN_PA6 (0x00 + 6)
33#define AT91_PIN_PA7 (PIN_BASE + 0x00 + 7) 31#define AT91_PIN_PA7 (0x00 + 7)
34#define AT91_PIN_PA8 (PIN_BASE + 0x00 + 8) 32#define AT91_PIN_PA8 (0x00 + 8)
35#define AT91_PIN_PA9 (PIN_BASE + 0x00 + 9) 33#define AT91_PIN_PA9 (0x00 + 9)
36#define AT91_PIN_PA10 (PIN_BASE + 0x00 + 10) 34#define AT91_PIN_PA10 (0x00 + 10)
37#define AT91_PIN_PA11 (PIN_BASE + 0x00 + 11) 35#define AT91_PIN_PA11 (0x00 + 11)
38#define AT91_PIN_PA12 (PIN_BASE + 0x00 + 12) 36#define AT91_PIN_PA12 (0x00 + 12)
39#define AT91_PIN_PA13 (PIN_BASE + 0x00 + 13) 37#define AT91_PIN_PA13 (0x00 + 13)
40#define AT91_PIN_PA14 (PIN_BASE + 0x00 + 14) 38#define AT91_PIN_PA14 (0x00 + 14)
41#define AT91_PIN_PA15 (PIN_BASE + 0x00 + 15) 39#define AT91_PIN_PA15 (0x00 + 15)
42#define AT91_PIN_PA16 (PIN_BASE + 0x00 + 16) 40#define AT91_PIN_PA16 (0x00 + 16)
43#define AT91_PIN_PA17 (PIN_BASE + 0x00 + 17) 41#define AT91_PIN_PA17 (0x00 + 17)
44#define AT91_PIN_PA18 (PIN_BASE + 0x00 + 18) 42#define AT91_PIN_PA18 (0x00 + 18)
45#define AT91_PIN_PA19 (PIN_BASE + 0x00 + 19) 43#define AT91_PIN_PA19 (0x00 + 19)
46#define AT91_PIN_PA20 (PIN_BASE + 0x00 + 20) 44#define AT91_PIN_PA20 (0x00 + 20)
47#define AT91_PIN_PA21 (PIN_BASE + 0x00 + 21) 45#define AT91_PIN_PA21 (0x00 + 21)
48#define AT91_PIN_PA22 (PIN_BASE + 0x00 + 22) 46#define AT91_PIN_PA22 (0x00 + 22)
49#define AT91_PIN_PA23 (PIN_BASE + 0x00 + 23) 47#define AT91_PIN_PA23 (0x00 + 23)
50#define AT91_PIN_PA24 (PIN_BASE + 0x00 + 24) 48#define AT91_PIN_PA24 (0x00 + 24)
51#define AT91_PIN_PA25 (PIN_BASE + 0x00 + 25) 49#define AT91_PIN_PA25 (0x00 + 25)
52#define AT91_PIN_PA26 (PIN_BASE + 0x00 + 26) 50#define AT91_PIN_PA26 (0x00 + 26)
53#define AT91_PIN_PA27 (PIN_BASE + 0x00 + 27) 51#define AT91_PIN_PA27 (0x00 + 27)
54#define AT91_PIN_PA28 (PIN_BASE + 0x00 + 28) 52#define AT91_PIN_PA28 (0x00 + 28)
55#define AT91_PIN_PA29 (PIN_BASE + 0x00 + 29) 53#define AT91_PIN_PA29 (0x00 + 29)
56#define AT91_PIN_PA30 (PIN_BASE + 0x00 + 30) 54#define AT91_PIN_PA30 (0x00 + 30)
57#define AT91_PIN_PA31 (PIN_BASE + 0x00 + 31) 55#define AT91_PIN_PA31 (0x00 + 31)
58 56
59#define AT91_PIN_PB0 (PIN_BASE + 0x20 + 0) 57#define AT91_PIN_PB0 (0x20 + 0)
60#define AT91_PIN_PB1 (PIN_BASE + 0x20 + 1) 58#define AT91_PIN_PB1 (0x20 + 1)
61#define AT91_PIN_PB2 (PIN_BASE + 0x20 + 2) 59#define AT91_PIN_PB2 (0x20 + 2)
62#define AT91_PIN_PB3 (PIN_BASE + 0x20 + 3) 60#define AT91_PIN_PB3 (0x20 + 3)
63#define AT91_PIN_PB4 (PIN_BASE + 0x20 + 4) 61#define AT91_PIN_PB4 (0x20 + 4)
64#define AT91_PIN_PB5 (PIN_BASE + 0x20 + 5) 62#define AT91_PIN_PB5 (0x20 + 5)
65#define AT91_PIN_PB6 (PIN_BASE + 0x20 + 6) 63#define AT91_PIN_PB6 (0x20 + 6)
66#define AT91_PIN_PB7 (PIN_BASE + 0x20 + 7) 64#define AT91_PIN_PB7 (0x20 + 7)
67#define AT91_PIN_PB8 (PIN_BASE + 0x20 + 8) 65#define AT91_PIN_PB8 (0x20 + 8)
68#define AT91_PIN_PB9 (PIN_BASE + 0x20 + 9) 66#define AT91_PIN_PB9 (0x20 + 9)
69#define AT91_PIN_PB10 (PIN_BASE + 0x20 + 10) 67#define AT91_PIN_PB10 (0x20 + 10)
70#define AT91_PIN_PB11 (PIN_BASE + 0x20 + 11) 68#define AT91_PIN_PB11 (0x20 + 11)
71#define AT91_PIN_PB12 (PIN_BASE + 0x20 + 12) 69#define AT91_PIN_PB12 (0x20 + 12)
72#define AT91_PIN_PB13 (PIN_BASE + 0x20 + 13) 70#define AT91_PIN_PB13 (0x20 + 13)
73#define AT91_PIN_PB14 (PIN_BASE + 0x20 + 14) 71#define AT91_PIN_PB14 (0x20 + 14)
74#define AT91_PIN_PB15 (PIN_BASE + 0x20 + 15) 72#define AT91_PIN_PB15 (0x20 + 15)
75#define AT91_PIN_PB16 (PIN_BASE + 0x20 + 16) 73#define AT91_PIN_PB16 (0x20 + 16)
76#define AT91_PIN_PB17 (PIN_BASE + 0x20 + 17) 74#define AT91_PIN_PB17 (0x20 + 17)
77#define AT91_PIN_PB18 (PIN_BASE + 0x20 + 18) 75#define AT91_PIN_PB18 (0x20 + 18)
78#define AT91_PIN_PB19 (PIN_BASE + 0x20 + 19) 76#define AT91_PIN_PB19 (0x20 + 19)
79#define AT91_PIN_PB20 (PIN_BASE + 0x20 + 20) 77#define AT91_PIN_PB20 (0x20 + 20)
80#define AT91_PIN_PB21 (PIN_BASE + 0x20 + 21) 78#define AT91_PIN_PB21 (0x20 + 21)
81#define AT91_PIN_PB22 (PIN_BASE + 0x20 + 22) 79#define AT91_PIN_PB22 (0x20 + 22)
82#define AT91_PIN_PB23 (PIN_BASE + 0x20 + 23) 80#define AT91_PIN_PB23 (0x20 + 23)
83#define AT91_PIN_PB24 (PIN_BASE + 0x20 + 24) 81#define AT91_PIN_PB24 (0x20 + 24)
84#define AT91_PIN_PB25 (PIN_BASE + 0x20 + 25) 82#define AT91_PIN_PB25 (0x20 + 25)
85#define AT91_PIN_PB26 (PIN_BASE + 0x20 + 26) 83#define AT91_PIN_PB26 (0x20 + 26)
86#define AT91_PIN_PB27 (PIN_BASE + 0x20 + 27) 84#define AT91_PIN_PB27 (0x20 + 27)
87#define AT91_PIN_PB28 (PIN_BASE + 0x20 + 28) 85#define AT91_PIN_PB28 (0x20 + 28)
88#define AT91_PIN_PB29 (PIN_BASE + 0x20 + 29) 86#define AT91_PIN_PB29 (0x20 + 29)
89#define AT91_PIN_PB30 (PIN_BASE + 0x20 + 30) 87#define AT91_PIN_PB30 (0x20 + 30)
90#define AT91_PIN_PB31 (PIN_BASE + 0x20 + 31) 88#define AT91_PIN_PB31 (0x20 + 31)
91 89
92#define AT91_PIN_PC0 (PIN_BASE + 0x40 + 0) 90#define AT91_PIN_PC0 (0x40 + 0)
93#define AT91_PIN_PC1 (PIN_BASE + 0x40 + 1) 91#define AT91_PIN_PC1 (0x40 + 1)
94#define AT91_PIN_PC2 (PIN_BASE + 0x40 + 2) 92#define AT91_PIN_PC2 (0x40 + 2)
95#define AT91_PIN_PC3 (PIN_BASE + 0x40 + 3) 93#define AT91_PIN_PC3 (0x40 + 3)
96#define AT91_PIN_PC4 (PIN_BASE + 0x40 + 4) 94#define AT91_PIN_PC4 (0x40 + 4)
97#define AT91_PIN_PC5 (PIN_BASE + 0x40 + 5) 95#define AT91_PIN_PC5 (0x40 + 5)
98#define AT91_PIN_PC6 (PIN_BASE + 0x40 + 6) 96#define AT91_PIN_PC6 (0x40 + 6)
99#define AT91_PIN_PC7 (PIN_BASE + 0x40 + 7) 97#define AT91_PIN_PC7 (0x40 + 7)
100#define AT91_PIN_PC8 (PIN_BASE + 0x40 + 8) 98#define AT91_PIN_PC8 (0x40 + 8)
101#define AT91_PIN_PC9 (PIN_BASE + 0x40 + 9) 99#define AT91_PIN_PC9 (0x40 + 9)
102#define AT91_PIN_PC10 (PIN_BASE + 0x40 + 10) 100#define AT91_PIN_PC10 (0x40 + 10)
103#define AT91_PIN_PC11 (PIN_BASE + 0x40 + 11) 101#define AT91_PIN_PC11 (0x40 + 11)
104#define AT91_PIN_PC12 (PIN_BASE + 0x40 + 12) 102#define AT91_PIN_PC12 (0x40 + 12)
105#define AT91_PIN_PC13 (PIN_BASE + 0x40 + 13) 103#define AT91_PIN_PC13 (0x40 + 13)
106#define AT91_PIN_PC14 (PIN_BASE + 0x40 + 14) 104#define AT91_PIN_PC14 (0x40 + 14)
107#define AT91_PIN_PC15 (PIN_BASE + 0x40 + 15) 105#define AT91_PIN_PC15 (0x40 + 15)
108#define AT91_PIN_PC16 (PIN_BASE + 0x40 + 16) 106#define AT91_PIN_PC16 (0x40 + 16)
109#define AT91_PIN_PC17 (PIN_BASE + 0x40 + 17) 107#define AT91_PIN_PC17 (0x40 + 17)
110#define AT91_PIN_PC18 (PIN_BASE + 0x40 + 18) 108#define AT91_PIN_PC18 (0x40 + 18)
111#define AT91_PIN_PC19 (PIN_BASE + 0x40 + 19) 109#define AT91_PIN_PC19 (0x40 + 19)
112#define AT91_PIN_PC20 (PIN_BASE + 0x40 + 20) 110#define AT91_PIN_PC20 (0x40 + 20)
113#define AT91_PIN_PC21 (PIN_BASE + 0x40 + 21) 111#define AT91_PIN_PC21 (0x40 + 21)
114#define AT91_PIN_PC22 (PIN_BASE + 0x40 + 22) 112#define AT91_PIN_PC22 (0x40 + 22)
115#define AT91_PIN_PC23 (PIN_BASE + 0x40 + 23) 113#define AT91_PIN_PC23 (0x40 + 23)
116#define AT91_PIN_PC24 (PIN_BASE + 0x40 + 24) 114#define AT91_PIN_PC24 (0x40 + 24)
117#define AT91_PIN_PC25 (PIN_BASE + 0x40 + 25) 115#define AT91_PIN_PC25 (0x40 + 25)
118#define AT91_PIN_PC26 (PIN_BASE + 0x40 + 26) 116#define AT91_PIN_PC26 (0x40 + 26)
119#define AT91_PIN_PC27 (PIN_BASE + 0x40 + 27) 117#define AT91_PIN_PC27 (0x40 + 27)
120#define AT91_PIN_PC28 (PIN_BASE + 0x40 + 28) 118#define AT91_PIN_PC28 (0x40 + 28)
121#define AT91_PIN_PC29 (PIN_BASE + 0x40 + 29) 119#define AT91_PIN_PC29 (0x40 + 29)
122#define AT91_PIN_PC30 (PIN_BASE + 0x40 + 30) 120#define AT91_PIN_PC30 (0x40 + 30)
123#define AT91_PIN_PC31 (PIN_BASE + 0x40 + 31) 121#define AT91_PIN_PC31 (0x40 + 31)
124 122
125#define AT91_PIN_PD0 (PIN_BASE + 0x60 + 0) 123#define AT91_PIN_PD0 (0x60 + 0)
126#define AT91_PIN_PD1 (PIN_BASE + 0x60 + 1) 124#define AT91_PIN_PD1 (0x60 + 1)
127#define AT91_PIN_PD2 (PIN_BASE + 0x60 + 2) 125#define AT91_PIN_PD2 (0x60 + 2)
128#define AT91_PIN_PD3 (PIN_BASE + 0x60 + 3) 126#define AT91_PIN_PD3 (0x60 + 3)
129#define AT91_PIN_PD4 (PIN_BASE + 0x60 + 4) 127#define AT91_PIN_PD4 (0x60 + 4)
130#define AT91_PIN_PD5 (PIN_BASE + 0x60 + 5) 128#define AT91_PIN_PD5 (0x60 + 5)
131#define AT91_PIN_PD6 (PIN_BASE + 0x60 + 6) 129#define AT91_PIN_PD6 (0x60 + 6)
132#define AT91_PIN_PD7 (PIN_BASE + 0x60 + 7) 130#define AT91_PIN_PD7 (0x60 + 7)
133#define AT91_PIN_PD8 (PIN_BASE + 0x60 + 8) 131#define AT91_PIN_PD8 (0x60 + 8)
134#define AT91_PIN_PD9 (PIN_BASE + 0x60 + 9) 132#define AT91_PIN_PD9 (0x60 + 9)
135#define AT91_PIN_PD10 (PIN_BASE + 0x60 + 10) 133#define AT91_PIN_PD10 (0x60 + 10)
136#define AT91_PIN_PD11 (PIN_BASE + 0x60 + 11) 134#define AT91_PIN_PD11 (0x60 + 11)
137#define AT91_PIN_PD12 (PIN_BASE + 0x60 + 12) 135#define AT91_PIN_PD12 (0x60 + 12)
138#define AT91_PIN_PD13 (PIN_BASE + 0x60 + 13) 136#define AT91_PIN_PD13 (0x60 + 13)
139#define AT91_PIN_PD14 (PIN_BASE + 0x60 + 14) 137#define AT91_PIN_PD14 (0x60 + 14)
140#define AT91_PIN_PD15 (PIN_BASE + 0x60 + 15) 138#define AT91_PIN_PD15 (0x60 + 15)
141#define AT91_PIN_PD16 (PIN_BASE + 0x60 + 16) 139#define AT91_PIN_PD16 (0x60 + 16)
142#define AT91_PIN_PD17 (PIN_BASE + 0x60 + 17) 140#define AT91_PIN_PD17 (0x60 + 17)
143#define AT91_PIN_PD18 (PIN_BASE + 0x60 + 18) 141#define AT91_PIN_PD18 (0x60 + 18)
144#define AT91_PIN_PD19 (PIN_BASE + 0x60 + 19) 142#define AT91_PIN_PD19 (0x60 + 19)
145#define AT91_PIN_PD20 (PIN_BASE + 0x60 + 20) 143#define AT91_PIN_PD20 (0x60 + 20)
146#define AT91_PIN_PD21 (PIN_BASE + 0x60 + 21) 144#define AT91_PIN_PD21 (0x60 + 21)
147#define AT91_PIN_PD22 (PIN_BASE + 0x60 + 22) 145#define AT91_PIN_PD22 (0x60 + 22)
148#define AT91_PIN_PD23 (PIN_BASE + 0x60 + 23) 146#define AT91_PIN_PD23 (0x60 + 23)
149#define AT91_PIN_PD24 (PIN_BASE + 0x60 + 24) 147#define AT91_PIN_PD24 (0x60 + 24)
150#define AT91_PIN_PD25 (PIN_BASE + 0x60 + 25) 148#define AT91_PIN_PD25 (0x60 + 25)
151#define AT91_PIN_PD26 (PIN_BASE + 0x60 + 26) 149#define AT91_PIN_PD26 (0x60 + 26)
152#define AT91_PIN_PD27 (PIN_BASE + 0x60 + 27) 150#define AT91_PIN_PD27 (0x60 + 27)
153#define AT91_PIN_PD28 (PIN_BASE + 0x60 + 28) 151#define AT91_PIN_PD28 (0x60 + 28)
154#define AT91_PIN_PD29 (PIN_BASE + 0x60 + 29) 152#define AT91_PIN_PD29 (0x60 + 29)
155#define AT91_PIN_PD30 (PIN_BASE + 0x60 + 30) 153#define AT91_PIN_PD30 (0x60 + 30)
156#define AT91_PIN_PD31 (PIN_BASE + 0x60 + 31) 154#define AT91_PIN_PD31 (0x60 + 31)
157 155
158#define AT91_PIN_PE0 (PIN_BASE + 0x80 + 0) 156#define AT91_PIN_PE0 (0x80 + 0)
159#define AT91_PIN_PE1 (PIN_BASE + 0x80 + 1) 157#define AT91_PIN_PE1 (0x80 + 1)
160#define AT91_PIN_PE2 (PIN_BASE + 0x80 + 2) 158#define AT91_PIN_PE2 (0x80 + 2)
161#define AT91_PIN_PE3 (PIN_BASE + 0x80 + 3) 159#define AT91_PIN_PE3 (0x80 + 3)
162#define AT91_PIN_PE4 (PIN_BASE + 0x80 + 4) 160#define AT91_PIN_PE4 (0x80 + 4)
163#define AT91_PIN_PE5 (PIN_BASE + 0x80 + 5) 161#define AT91_PIN_PE5 (0x80 + 5)
164#define AT91_PIN_PE6 (PIN_BASE + 0x80 + 6) 162#define AT91_PIN_PE6 (0x80 + 6)
165#define AT91_PIN_PE7 (PIN_BASE + 0x80 + 7) 163#define AT91_PIN_PE7 (0x80 + 7)
166#define AT91_PIN_PE8 (PIN_BASE + 0x80 + 8) 164#define AT91_PIN_PE8 (0x80 + 8)
167#define AT91_PIN_PE9 (PIN_BASE + 0x80 + 9) 165#define AT91_PIN_PE9 (0x80 + 9)
168#define AT91_PIN_PE10 (PIN_BASE + 0x80 + 10) 166#define AT91_PIN_PE10 (0x80 + 10)
169#define AT91_PIN_PE11 (PIN_BASE + 0x80 + 11) 167#define AT91_PIN_PE11 (0x80 + 11)
170#define AT91_PIN_PE12 (PIN_BASE + 0x80 + 12) 168#define AT91_PIN_PE12 (0x80 + 12)
171#define AT91_PIN_PE13 (PIN_BASE + 0x80 + 13) 169#define AT91_PIN_PE13 (0x80 + 13)
172#define AT91_PIN_PE14 (PIN_BASE + 0x80 + 14) 170#define AT91_PIN_PE14 (0x80 + 14)
173#define AT91_PIN_PE15 (PIN_BASE + 0x80 + 15) 171#define AT91_PIN_PE15 (0x80 + 15)
174#define AT91_PIN_PE16 (PIN_BASE + 0x80 + 16) 172#define AT91_PIN_PE16 (0x80 + 16)
175#define AT91_PIN_PE17 (PIN_BASE + 0x80 + 17) 173#define AT91_PIN_PE17 (0x80 + 17)
176#define AT91_PIN_PE18 (PIN_BASE + 0x80 + 18) 174#define AT91_PIN_PE18 (0x80 + 18)
177#define AT91_PIN_PE19 (PIN_BASE + 0x80 + 19) 175#define AT91_PIN_PE19 (0x80 + 19)
178#define AT91_PIN_PE20 (PIN_BASE + 0x80 + 20) 176#define AT91_PIN_PE20 (0x80 + 20)
179#define AT91_PIN_PE21 (PIN_BASE + 0x80 + 21) 177#define AT91_PIN_PE21 (0x80 + 21)
180#define AT91_PIN_PE22 (PIN_BASE + 0x80 + 22) 178#define AT91_PIN_PE22 (0x80 + 22)
181#define AT91_PIN_PE23 (PIN_BASE + 0x80 + 23) 179#define AT91_PIN_PE23 (0x80 + 23)
182#define AT91_PIN_PE24 (PIN_BASE + 0x80 + 24) 180#define AT91_PIN_PE24 (0x80 + 24)
183#define AT91_PIN_PE25 (PIN_BASE + 0x80 + 25) 181#define AT91_PIN_PE25 (0x80 + 25)
184#define AT91_PIN_PE26 (PIN_BASE + 0x80 + 26) 182#define AT91_PIN_PE26 (0x80 + 26)
185#define AT91_PIN_PE27 (PIN_BASE + 0x80 + 27) 183#define AT91_PIN_PE27 (0x80 + 27)
186#define AT91_PIN_PE28 (PIN_BASE + 0x80 + 28) 184#define AT91_PIN_PE28 (0x80 + 28)
187#define AT91_PIN_PE29 (PIN_BASE + 0x80 + 29) 185#define AT91_PIN_PE29 (0x80 + 29)
188#define AT91_PIN_PE30 (PIN_BASE + 0x80 + 30) 186#define AT91_PIN_PE30 (0x80 + 30)
189#define AT91_PIN_PE31 (PIN_BASE + 0x80 + 31) 187#define AT91_PIN_PE31 (0x80 + 31)
190 188
191#ifndef __ASSEMBLY__ 189#ifndef __ASSEMBLY__
192/* setup setup routines, called from board init or driver probe() */ 190/* setup setup routines, called from board init or driver probe() */
@@ -215,8 +213,8 @@ extern void at91_gpio_resume(void);
215 213
216#include <asm/errno.h> 214#include <asm/errno.h>
217 215
218#define gpio_to_irq(gpio) (gpio) 216#define gpio_to_irq(gpio) (gpio + NR_AIC_IRQS)
219#define irq_to_gpio(irq) (irq) 217#define irq_to_gpio(irq) (irq - NR_AIC_IRQS)
220 218
221#endif /* __ASSEMBLY__ */ 219#endif /* __ASSEMBLY__ */
222 220
diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h
index 483478d8be6..2d0e4e99856 100644
--- a/arch/arm/mach-at91/include/mach/hardware.h
+++ b/arch/arm/mach-at91/include/mach/hardware.h
@@ -16,6 +16,12 @@
16 16
17#include <asm/sizes.h> 17#include <asm/sizes.h>
18 18
19/* DBGU base */
20/* rm9200, 9260/9g20, 9261/9g10, 9rl */
21#define AT91_BASE_DBGU0 0xfffff200
22/* 9263, 9g45, cap9 */
23#define AT91_BASE_DBGU1 0xffffee00
24
19#if defined(CONFIG_ARCH_AT91RM9200) 25#if defined(CONFIG_ARCH_AT91RM9200)
20#include <mach/at91rm9200.h> 26#include <mach/at91rm9200.h>
21#elif defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9G20) 27#elif defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9G20)
@@ -52,6 +58,12 @@
52#endif 58#endif
53 59
54/* 60/*
61 * On all at91 have the Advanced Interrupt Controller starts at address
62 * 0xfffff000
63 */
64#define AT91_AIC 0xfffff000
65
66/*
55 * Peripheral identifiers/interrupts. 67 * Peripheral identifiers/interrupts.
56 */ 68 */
57#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ 69#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
diff --git a/arch/arm/mach-at91/include/mach/irqs.h b/arch/arm/mach-at91/include/mach/irqs.h
index 36bd55f3fc6..ac8b7dfc85e 100644
--- a/arch/arm/mach-at91/include/mach/irqs.h
+++ b/arch/arm/mach-at91/include/mach/irqs.h
@@ -31,7 +31,7 @@
31 * Acknowledge interrupt with AIC after interrupt has been handled. 31 * Acknowledge interrupt with AIC after interrupt has been handled.
32 * (by kernel/irq.c) 32 * (by kernel/irq.c)
33 */ 33 */
34#define irq_finish(irq) do { at91_sys_write(AT91_AIC_EOICR, 0); } while (0) 34#define irq_finish(irq) do { at91_aic_write(AT91_AIC_EOICR, 0); } while (0)
35 35
36 36
37/* 37/*
diff --git a/arch/arm/mach-at91/include/mach/system.h b/arch/arm/mach-at91/include/mach/system.h
index 36af14bc13b..cbd64f3bcec 100644
--- a/arch/arm/mach-at91/include/mach/system.h
+++ b/arch/arm/mach-at91/include/mach/system.h
@@ -47,13 +47,4 @@ static inline void arch_idle(void)
47#endif 47#endif
48} 48}
49 49
50void (*at91_arch_reset)(void);
51
52static inline void arch_reset(char mode, const char *cmd)
53{
54 /* call the CPU-specific reset function */
55 if (at91_arch_reset)
56 (at91_arch_reset)();
57}
58
59#endif 50#endif
diff --git a/arch/arm/mach-at91/include/mach/timex.h b/arch/arm/mach-at91/include/mach/timex.h
index 85820ad801c..5e917a66edd 100644
--- a/arch/arm/mach-at91/include/mach/timex.h
+++ b/arch/arm/mach-at91/include/mach/timex.h
@@ -23,70 +23,15 @@
23 23
24#include <mach/hardware.h> 24#include <mach/hardware.h>
25 25
26#if defined(CONFIG_ARCH_AT91RM9200) 26#ifdef CONFIG_ARCH_AT91X40
27 27
28#define CLOCK_TICK_RATE (AT91_SLOW_CLOCK) 28#define AT91X40_MASTER_CLOCK 40000000
29 29#define CLOCK_TICK_RATE (AT91X40_MASTER_CLOCK)
30#elif defined(CONFIG_ARCH_AT91SAM9260)
31
32#if defined(CONFIG_MACH_USB_A9260) || defined(CONFIG_MACH_QIL_A9260)
33#define AT91SAM9_MASTER_CLOCK 90000000
34#else
35#define AT91SAM9_MASTER_CLOCK 99300000
36#endif
37
38#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16)
39
40#elif defined(CONFIG_ARCH_AT91SAM9261)
41
42#define AT91SAM9_MASTER_CLOCK 99300000
43#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16)
44
45#elif defined(CONFIG_ARCH_AT91SAM9G10)
46
47#define AT91SAM9_MASTER_CLOCK 133000000
48#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16)
49
50#elif defined(CONFIG_ARCH_AT91SAM9263)
51
52#if defined(CONFIG_MACH_USB_A9263)
53#define AT91SAM9_MASTER_CLOCK 90000000
54#else
55#define AT91SAM9_MASTER_CLOCK 99959500
56#endif
57
58#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16)
59
60#elif defined(CONFIG_ARCH_AT91SAM9RL)
61
62#define AT91SAM9_MASTER_CLOCK 100000000
63#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16)
64
65#elif defined(CONFIG_ARCH_AT91SAM9G20)
66 30
67#if defined(CONFIG_MACH_USB_A9G20)
68#define AT91SAM9_MASTER_CLOCK 133000000
69#else 31#else
70#define AT91SAM9_MASTER_CLOCK 132096000
71#endif
72
73#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16)
74
75#elif defined(CONFIG_ARCH_AT91SAM9G45)
76 32
77#define AT91SAM9_MASTER_CLOCK 133333333 33#define CLOCK_TICK_RATE 12345678
78#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16)
79
80#elif defined(CONFIG_ARCH_AT91CAP9)
81
82#define AT91CAP9_MASTER_CLOCK 100000000
83#define CLOCK_TICK_RATE (AT91CAP9_MASTER_CLOCK/16)
84
85#elif defined(CONFIG_ARCH_AT91X40)
86
87#define AT91X40_MASTER_CLOCK 40000000
88#define CLOCK_TICK_RATE (AT91X40_MASTER_CLOCK)
89 34
90#endif 35#endif
91 36
92#endif 37#endif /* __ASM_ARCH_TIMEX_H */
diff --git a/arch/arm/mach-at91/include/mach/uncompress.h b/arch/arm/mach-at91/include/mach/uncompress.h
index 18bdcdeb474..0234fd9d20d 100644
--- a/arch/arm/mach-at91/include/mach/uncompress.h
+++ b/arch/arm/mach-at91/include/mach/uncompress.h
@@ -24,8 +24,10 @@
24#include <linux/io.h> 24#include <linux/io.h>
25#include <linux/atmel_serial.h> 25#include <linux/atmel_serial.h>
26 26
27#if defined(CONFIG_AT91_EARLY_DBGU) 27#if defined(CONFIG_AT91_EARLY_DBGU0)
28#define UART_OFFSET (AT91_DBGU + AT91_BASE_SYS) 28#define UART_OFFSET AT91_BASE_DBGU0
29#elif defined(CONFIG_AT91_EARLY_DBGU1)
30#define UART_OFFSET AT91_BASE_DBGU1
29#elif defined(CONFIG_AT91_EARLY_USART0) 31#elif defined(CONFIG_AT91_EARLY_USART0)
30#define UART_OFFSET AT91_USART0 32#define UART_OFFSET AT91_USART0
31#elif defined(CONFIG_AT91_EARLY_USART1) 33#elif defined(CONFIG_AT91_EARLY_USART1)
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-31 23:32:02 -0500