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-rw-r--r--arch/arm/mach-at91/include/mach/at572d940hf.h123
-rw-r--r--arch/arm/mach-at91/include/mach/at572d940hf_matrix.h123
-rw-r--r--arch/arm/mach-at91/include/mach/at91cap9.h4
-rw-r--r--arch/arm/mach-at91/include/mach/at91rm9200.h2
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9260.h2
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9261.h2
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9263.h2
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9g45.h4
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9rl.h2
-rw-r--r--arch/arm/mach-at91/include/mach/at91x40.h2
-rw-r--r--arch/arm/mach-at91/include/mach/board.h6
-rw-r--r--arch/arm/mach-at91/include/mach/clkdev.h7
-rw-r--r--arch/arm/mach-at91/include/mach/cpu.h15
-rw-r--r--arch/arm/mach-at91/include/mach/hardware.h15
-rw-r--r--arch/arm/mach-at91/include/mach/memory.h2
-rw-r--r--arch/arm/mach-at91/include/mach/stamp9g20.h2
-rw-r--r--arch/arm/mach-at91/include/mach/system_rev.h25
-rw-r--r--arch/arm/mach-at91/include/mach/timex.h5
18 files changed, 48 insertions, 295 deletions
diff --git a/arch/arm/mach-at91/include/mach/at572d940hf.h b/arch/arm/mach-at91/include/mach/at572d940hf.h
deleted file mode 100644
index be510cfc56b..00000000000
--- a/arch/arm/mach-at91/include/mach/at572d940hf.h
+++ /dev/null
@@ -1,123 +0,0 @@
1/*
2 * include/mach/at572d940hf.h
3 *
4 * Antonio R. Costa <costa.antonior@gmail.com>
5 * Copyright (C) 2008 Atmel
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 *
21 */
22
23#ifndef AT572D940HF_H
24#define AT572D940HF_H
25
26/*
27 * Peripheral identifiers/interrupts.
28 */
29#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
30#define AT91_ID_SYS 1 /* System Peripherals */
31#define AT572D940HF_ID_PIOA 2 /* Parallel IO Controller A */
32#define AT572D940HF_ID_PIOB 3 /* Parallel IO Controller B */
33#define AT572D940HF_ID_PIOC 4 /* Parallel IO Controller C */
34#define AT572D940HF_ID_EMAC 5 /* MACB ethernet controller */
35#define AT572D940HF_ID_US0 6 /* USART 0 */
36#define AT572D940HF_ID_US1 7 /* USART 1 */
37#define AT572D940HF_ID_US2 8 /* USART 2 */
38#define AT572D940HF_ID_MCI 9 /* Multimedia Card Interface */
39#define AT572D940HF_ID_UDP 10 /* USB Device Port */
40#define AT572D940HF_ID_TWI0 11 /* Two-Wire Interface 0 */
41#define AT572D940HF_ID_SPI0 12 /* Serial Peripheral Interface 0 */
42#define AT572D940HF_ID_SPI1 13 /* Serial Peripheral Interface 1 */
43#define AT572D940HF_ID_SSC0 14 /* Serial Synchronous Controller 0 */
44#define AT572D940HF_ID_SSC1 15 /* Serial Synchronous Controller 1 */
45#define AT572D940HF_ID_SSC2 16 /* Serial Synchronous Controller 2 */
46#define AT572D940HF_ID_TC0 17 /* Timer Counter 0 */
47#define AT572D940HF_ID_TC1 18 /* Timer Counter 1 */
48#define AT572D940HF_ID_TC2 19 /* Timer Counter 2 */
49#define AT572D940HF_ID_UHP 20 /* USB Host port */
50#define AT572D940HF_ID_SSC3 21 /* Serial Synchronous Controller 3 */
51#define AT572D940HF_ID_TWI1 22 /* Two-Wire Interface 1 */
52#define AT572D940HF_ID_CAN0 23 /* CAN Controller 0 */
53#define AT572D940HF_ID_CAN1 24 /* CAN Controller 1 */
54#define AT572D940HF_ID_MHALT 25 /* mAgicV HALT line */
55#define AT572D940HF_ID_MSIRQ0 26 /* mAgicV SIRQ0 line */
56#define AT572D940HF_ID_MEXC 27 /* mAgicV exception line */
57#define AT572D940HF_ID_MEDMA 28 /* mAgicV end of DMA line */
58#define AT572D940HF_ID_IRQ0 29 /* External Interrupt Source (IRQ0) */
59#define AT572D940HF_ID_IRQ1 30 /* External Interrupt Source (IRQ1) */
60#define AT572D940HF_ID_IRQ2 31 /* External Interrupt Source (IRQ2) */
61
62
63/*
64 * User Peripheral physical base addresses.
65 */
66#define AT572D940HF_BASE_TCB 0xfffa0000
67#define AT572D940HF_BASE_TC0 0xfffa0000
68#define AT572D940HF_BASE_TC1 0xfffa0040
69#define AT572D940HF_BASE_TC2 0xfffa0080
70#define AT572D940HF_BASE_UDP 0xfffa4000
71#define AT572D940HF_BASE_MCI 0xfffa8000
72#define AT572D940HF_BASE_TWI0 0xfffac000
73#define AT572D940HF_BASE_US0 0xfffb0000
74#define AT572D940HF_BASE_US1 0xfffb4000
75#define AT572D940HF_BASE_US2 0xfffb8000
76#define AT572D940HF_BASE_SSC0 0xfffbc000
77#define AT572D940HF_BASE_SSC1 0xfffc0000
78#define AT572D940HF_BASE_SSC2 0xfffc4000
79#define AT572D940HF_BASE_SPI0 0xfffc8000
80#define AT572D940HF_BASE_SPI1 0xfffcc000
81#define AT572D940HF_BASE_SSC3 0xfffd0000
82#define AT572D940HF_BASE_TWI1 0xfffd4000
83#define AT572D940HF_BASE_EMAC 0xfffd8000
84#define AT572D940HF_BASE_CAN0 0xfffdc000
85#define AT572D940HF_BASE_CAN1 0xfffe0000
86#define AT91_BASE_SYS 0xffffea00
87
88
89/*
90 * System Peripherals (offset from AT91_BASE_SYS)
91 */
92#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
93#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
94#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
95#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
96#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
97#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS)
98#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS)
99#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS)
100#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
101#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
102#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
103#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
104#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
105
106#define AT91_USART0 AT572D940HF_ID_US0
107#define AT91_USART1 AT572D940HF_ID_US1
108#define AT91_USART2 AT572D940HF_ID_US2
109
110
111/*
112 * Internal Memory.
113 */
114#define AT572D940HF_SRAM_BASE 0x00300000 /* Internal SRAM base address */
115#define AT572D940HF_SRAM_SIZE (48 * SZ_1K) /* Internal SRAM size (48Kb) */
116
117#define AT572D940HF_ROM_BASE 0x00400000 /* Internal ROM base address */
118#define AT572D940HF_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */
119
120#define AT572D940HF_UHP_BASE 0x00500000 /* USB Host controller */
121
122
123#endif
diff --git a/arch/arm/mach-at91/include/mach/at572d940hf_matrix.h b/arch/arm/mach-at91/include/mach/at572d940hf_matrix.h
deleted file mode 100644
index b6751df0948..00000000000
--- a/arch/arm/mach-at91/include/mach/at572d940hf_matrix.h
+++ /dev/null
@@ -1,123 +0,0 @@
1/*
2 * include/mach//at572d940hf_matrix.h
3 *
4 * Antonio R. Costa <costa.antonior@gmail.com>
5 * Copyright (C) 2008 Atmel
6 *
7 * Copyright (C) 2005 SAN People
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#ifndef AT572D940HF_MATRIX_H
25#define AT572D940HF_MATRIX_H
26
27#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
28#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
29#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
30#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
31#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
32#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */
33
34#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
35#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
36#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
37#define AT91_MATRIX_ULBT_FOUR (2 << 0)
38#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
39#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
40
41#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
42#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
43#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
44#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
45#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
46#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
47#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
48#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
49#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
50#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
51#define AT91_MATRIX_FIXED_DEFMSTR (0x7 << 18) /* Fixed Index of Default Master */
52#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
53#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
54#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
55
56#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
57#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
58#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
59#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
60#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
61
62#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
63#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
64#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
65#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
66#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
67#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
68#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */
69
70#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
71#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
72#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
73
74#define AT91_MATRIX_SFR0 (AT91_MATRIX + 0x110) /* Special Function Register 0 */
75#define AT91_MATRIX_SFR1 (AT91_MATRIX + 0x114) /* Special Function Register 1 */
76#define AT91_MATRIX_SFR2 (AT91_MATRIX + 0x118) /* Special Function Register 2 */
77#define AT91_MATRIX_SFR3 (AT91_MATRIX + 0x11C) /* Special Function Register 3 */
78#define AT91_MATRIX_SFR4 (AT91_MATRIX + 0x120) /* Special Function Register 4 */
79#define AT91_MATRIX_SFR5 (AT91_MATRIX + 0x124) /* Special Function Register 5 */
80#define AT91_MATRIX_SFR6 (AT91_MATRIX + 0x128) /* Special Function Register 6 */
81#define AT91_MATRIX_SFR7 (AT91_MATRIX + 0x12C) /* Special Function Register 7 */
82#define AT91_MATRIX_SFR8 (AT91_MATRIX + 0x130) /* Special Function Register 8 */
83#define AT91_MATRIX_SFR9 (AT91_MATRIX + 0x134) /* Special Function Register 9 */
84#define AT91_MATRIX_SFR10 (AT91_MATRIX + 0x138) /* Special Function Register 10 */
85#define AT91_MATRIX_SFR11 (AT91_MATRIX + 0x13C) /* Special Function Register 11 */
86#define AT91_MATRIX_SFR12 (AT91_MATRIX + 0x140) /* Special Function Register 12 */
87#define AT91_MATRIX_SFR13 (AT91_MATRIX + 0x144) /* Special Function Register 13 */
88#define AT91_MATRIX_SFR14 (AT91_MATRIX + 0x148) /* Special Function Register 14 */
89#define AT91_MATRIX_SFR15 (AT91_MATRIX + 0x14C) /* Special Function Register 15 */
90
91
92/*
93 * The following registers / bits are not defined in the Datasheet (Revision A)
94 */
95
96#define AT91_MATRIX_TCR (AT91_MATRIX + 0x100) /* TCM Configuration Register */
97#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
98#define AT91_MATRIX_ITCM_0 (0 << 0)
99#define AT91_MATRIX_ITCM_16 (5 << 0)
100#define AT91_MATRIX_ITCM_32 (6 << 0)
101#define AT91_MATRIX_ITCM_64 (7 << 0)
102#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
103#define AT91_MATRIX_DTCM_0 (0 << 4)
104#define AT91_MATRIX_DTCM_16 (5 << 4)
105#define AT91_MATRIX_DTCM_32 (6 << 4)
106#define AT91_MATRIX_DTCM_64 (7 << 4)
107
108#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x11C) /* EBI Chip Select Assignment Register */
109#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
110#define AT91_MATRIX_CS1A_SMC (0 << 1)
111#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
112#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */
113#define AT91_MATRIX_CS3A_SMC (0 << 3)
114#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
115#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */
116#define AT91_MATRIX_CS4A_SMC (0 << 4)
117#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
118#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */
119#define AT91_MATRIX_CS5A_SMC (0 << 5)
120#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
121#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
122
123#endif
diff --git a/arch/arm/mach-at91/include/mach/at91cap9.h b/arch/arm/mach-at91/include/mach/at91cap9.h
index 9c6af973748..665993849a7 100644
--- a/arch/arm/mach-at91/include/mach/at91cap9.h
+++ b/arch/arm/mach-at91/include/mach/at91cap9.h
@@ -20,8 +20,6 @@
20/* 20/*
21 * Peripheral identifiers/interrupts. 21 * Peripheral identifiers/interrupts.
22 */ 22 */
23#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
24#define AT91_ID_SYS 1 /* System Peripherals */
25#define AT91CAP9_ID_PIOABCD 2 /* Parallel IO Controller A, B, C and D */ 23#define AT91CAP9_ID_PIOABCD 2 /* Parallel IO Controller A, B, C and D */
26#define AT91CAP9_ID_MPB0 3 /* MP Block Peripheral 0 */ 24#define AT91CAP9_ID_MPB0 3 /* MP Block Peripheral 0 */
27#define AT91CAP9_ID_MPB1 4 /* MP Block Peripheral 1 */ 25#define AT91CAP9_ID_MPB1 4 /* MP Block Peripheral 1 */
@@ -123,6 +121,4 @@
123#define AT91CAP9_UDPHS_FIFO 0x00600000 /* USB High Speed Device Port */ 121#define AT91CAP9_UDPHS_FIFO 0x00600000 /* USB High Speed Device Port */
124#define AT91CAP9_UHP_BASE 0x00700000 /* USB Host controller */ 122#define AT91CAP9_UHP_BASE 0x00700000 /* USB Host controller */
125 123
126#define CONFIG_DRAM_BASE AT91_CHIPSELECT_6
127
128#endif 124#endif
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200.h b/arch/arm/mach-at91/include/mach/at91rm9200.h
index 78983155a07..99e0f8d02d7 100644
--- a/arch/arm/mach-at91/include/mach/at91rm9200.h
+++ b/arch/arm/mach-at91/include/mach/at91rm9200.h
@@ -19,8 +19,6 @@
19/* 19/*
20 * Peripheral identifiers/interrupts. 20 * Peripheral identifiers/interrupts.
21 */ 21 */
22#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
23#define AT91_ID_SYS 1 /* System Peripheral */
24#define AT91RM9200_ID_PIOA 2 /* Parallel IO Controller A */ 22#define AT91RM9200_ID_PIOA 2 /* Parallel IO Controller A */
25#define AT91RM9200_ID_PIOB 3 /* Parallel IO Controller B */ 23#define AT91RM9200_ID_PIOB 3 /* Parallel IO Controller B */
26#define AT91RM9200_ID_PIOC 4 /* Parallel IO Controller C */ 24#define AT91RM9200_ID_PIOC 4 /* Parallel IO Controller C */
diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h
index 4e79036d3b8..8b6bf835cd7 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9260.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9260.h
@@ -20,8 +20,6 @@
20/* 20/*
21 * Peripheral identifiers/interrupts. 21 * Peripheral identifiers/interrupts.
22 */ 22 */
23#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
24#define AT91_ID_SYS 1 /* System Peripherals */
25#define AT91SAM9260_ID_PIOA 2 /* Parallel IO Controller A */ 23#define AT91SAM9260_ID_PIOA 2 /* Parallel IO Controller A */
26#define AT91SAM9260_ID_PIOB 3 /* Parallel IO Controller B */ 24#define AT91SAM9260_ID_PIOB 3 /* Parallel IO Controller B */
27#define AT91SAM9260_ID_PIOC 4 /* Parallel IO Controller C */ 25#define AT91SAM9260_ID_PIOC 4 /* Parallel IO Controller C */
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h
index 2b561851812..eafbddaf523 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9261.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9261.h
@@ -18,8 +18,6 @@
18/* 18/*
19 * Peripheral identifiers/interrupts. 19 * Peripheral identifiers/interrupts.
20 */ 20 */
21#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
22#define AT91_ID_SYS 1 /* System Peripherals */
23#define AT91SAM9261_ID_PIOA 2 /* Parallel IO Controller A */ 21#define AT91SAM9261_ID_PIOA 2 /* Parallel IO Controller A */
24#define AT91SAM9261_ID_PIOB 3 /* Parallel IO Controller B */ 22#define AT91SAM9261_ID_PIOB 3 /* Parallel IO Controller B */
25#define AT91SAM9261_ID_PIOC 4 /* Parallel IO Controller C */ 23#define AT91SAM9261_ID_PIOC 4 /* Parallel IO Controller C */
diff --git a/arch/arm/mach-at91/include/mach/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h
index 2091f1e42d4..e2d348213a7 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9263.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9263.h
@@ -18,8 +18,6 @@
18/* 18/*
19 * Peripheral identifiers/interrupts. 19 * Peripheral identifiers/interrupts.
20 */ 20 */
21#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
22#define AT91_ID_SYS 1 /* System Peripherals */
23#define AT91SAM9263_ID_PIOA 2 /* Parallel IO Controller A */ 21#define AT91SAM9263_ID_PIOA 2 /* Parallel IO Controller A */
24#define AT91SAM9263_ID_PIOB 3 /* Parallel IO Controller B */ 22#define AT91SAM9263_ID_PIOB 3 /* Parallel IO Controller B */
25#define AT91SAM9263_ID_PIOCDE 4 /* Parallel IO Controller C, D and E */ 23#define AT91SAM9263_ID_PIOCDE 4 /* Parallel IO Controller C, D and E */
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h
index a526869aee3..659304aa73d 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9g45.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h
@@ -18,8 +18,6 @@
18/* 18/*
19 * Peripheral identifiers/interrupts. 19 * Peripheral identifiers/interrupts.
20 */ 20 */
21#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
22#define AT91_ID_SYS 1 /* System Controller Interrupt */
23#define AT91SAM9G45_ID_PIOA 2 /* Parallel I/O Controller A */ 21#define AT91SAM9G45_ID_PIOA 2 /* Parallel I/O Controller A */
24#define AT91SAM9G45_ID_PIOB 3 /* Parallel I/O Controller B */ 22#define AT91SAM9G45_ID_PIOB 3 /* Parallel I/O Controller B */
25#define AT91SAM9G45_ID_PIOC 4 /* Parallel I/O Controller C */ 23#define AT91SAM9G45_ID_PIOC 4 /* Parallel I/O Controller C */
@@ -131,8 +129,6 @@
131#define AT91SAM9G45_EHCI_BASE 0x00800000 /* USB Host controller (EHCI) */ 129#define AT91SAM9G45_EHCI_BASE 0x00800000 /* USB Host controller (EHCI) */
132#define AT91SAM9G45_VDEC_BASE 0x00900000 /* Video Decoder Controller */ 130#define AT91SAM9G45_VDEC_BASE 0x00900000 /* Video Decoder Controller */
133 131
134#define CONFIG_DRAM_BASE AT91_CHIPSELECT_6
135
136#define CONSISTENT_DMA_SIZE SZ_4M 132#define CONSISTENT_DMA_SIZE SZ_4M
137 133
138/* 134/*
diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl.h b/arch/arm/mach-at91/include/mach/at91sam9rl.h
index 87ba8517ad9..41dbbe61055 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9rl.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9rl.h
@@ -17,8 +17,6 @@
17/* 17/*
18 * Peripheral identifiers/interrupts. 18 * Peripheral identifiers/interrupts.
19 */ 19 */
20#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
21#define AT91_ID_SYS 1 /* System Controller */
22#define AT91SAM9RL_ID_PIOA 2 /* Parallel IO Controller A */ 20#define AT91SAM9RL_ID_PIOA 2 /* Parallel IO Controller A */
23#define AT91SAM9RL_ID_PIOB 3 /* Parallel IO Controller B */ 21#define AT91SAM9RL_ID_PIOB 3 /* Parallel IO Controller B */
24#define AT91SAM9RL_ID_PIOC 4 /* Parallel IO Controller C */ 22#define AT91SAM9RL_ID_PIOC 4 /* Parallel IO Controller C */
diff --git a/arch/arm/mach-at91/include/mach/at91x40.h b/arch/arm/mach-at91/include/mach/at91x40.h
index 063ac44a020..a152ff87e68 100644
--- a/arch/arm/mach-at91/include/mach/at91x40.h
+++ b/arch/arm/mach-at91/include/mach/at91x40.h
@@ -15,8 +15,6 @@
15/* 15/*
16 * IRQ list. 16 * IRQ list.
17 */ 17 */
18#define AT91_ID_FIQ 0 /* FIQ */
19#define AT91_ID_SYS 1 /* System Peripheral */
20#define AT91X40_ID_USART0 2 /* USART port 0 */ 18#define AT91X40_ID_USART0 2 /* USART port 0 */
21#define AT91X40_ID_USART1 3 /* USART port 1 */ 19#define AT91X40_ID_USART1 3 /* USART port 1 */
22#define AT91X40_ID_TC0 4 /* Timer/Counter 0 */ 20#define AT91X40_ID_TC0 4 /* Timer/Counter 0 */
diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
index 2b499eb343a..ed544a0d5a1 100644
--- a/arch/arm/mach-at91/include/mach/board.h
+++ b/arch/arm/mach-at91/include/mach/board.h
@@ -90,7 +90,7 @@ struct at91_eth_data {
90extern void __init at91_add_device_eth(struct at91_eth_data *data); 90extern void __init at91_add_device_eth(struct at91_eth_data *data);
91 91
92#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) || defined(CONFIG_ARCH_AT91SAM9G20) || defined(CONFIG_ARCH_AT91CAP9) \ 92#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) || defined(CONFIG_ARCH_AT91SAM9G20) || defined(CONFIG_ARCH_AT91CAP9) \
93 || defined(CONFIG_ARCH_AT91SAM9G45) || defined(CONFIG_ARCH_AT572D940HF) 93 || defined(CONFIG_ARCH_AT91SAM9G45)
94#define eth_platform_data at91_eth_data 94#define eth_platform_data at91_eth_data
95#endif 95#endif
96 96
@@ -140,6 +140,7 @@ extern void __init at91_set_serial_console(unsigned portnr);
140extern struct platform_device *atmel_default_console_device; 140extern struct platform_device *atmel_default_console_device;
141 141
142struct atmel_uart_data { 142struct atmel_uart_data {
143 int num; /* port num */
143 short use_dma_tx; /* use transmit DMA? */ 144 short use_dma_tx; /* use transmit DMA? */
144 short use_dma_rx; /* use receive DMA? */ 145 short use_dma_rx; /* use receive DMA? */
145 void __iomem *regs; /* virt. base address, if any */ 146 void __iomem *regs; /* virt. base address, if any */
@@ -203,9 +204,6 @@ extern void __init at91_init_leds(u8 cpu_led, u8 timer_led);
203extern void __init at91_gpio_leds(struct gpio_led *leds, int nr); 204extern void __init at91_gpio_leds(struct gpio_led *leds, int nr);
204extern void __init at91_pwm_leds(struct gpio_led *leds, int nr); 205extern void __init at91_pwm_leds(struct gpio_led *leds, int nr);
205 206
206 /* AT572D940HF DSP */
207extern void __init at91_add_device_mAgic(void);
208
209/* FIXME: this needs a better location, but gets stuff building again */ 207/* FIXME: this needs a better location, but gets stuff building again */
210extern int at91_suspend_entering_slow_clock(void); 208extern int at91_suspend_entering_slow_clock(void);
211 209
diff --git a/arch/arm/mach-at91/include/mach/clkdev.h b/arch/arm/mach-at91/include/mach/clkdev.h
new file mode 100644
index 00000000000..04b37a89801
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/clkdev.h
@@ -0,0 +1,7 @@
1#ifndef __ASM_MACH_CLKDEV_H
2#define __ASM_MACH_CLKDEV_H
3
4#define __clk_get(clk) ({ 1; })
5#define __clk_put(clk) do { } while (0)
6
7#endif
diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h
index 0700f212530..df966c2bc2d 100644
--- a/arch/arm/mach-at91/include/mach/cpu.h
+++ b/arch/arm/mach-at91/include/mach/cpu.h
@@ -34,8 +34,6 @@
34#define ARCH_ID_AT91SAM9XE256 0x329a93a0 34#define ARCH_ID_AT91SAM9XE256 0x329a93a0
35#define ARCH_ID_AT91SAM9XE512 0x329aa3a0 35#define ARCH_ID_AT91SAM9XE512 0x329aa3a0
36 36
37#define ARCH_ID_AT572D940HF 0x0e0303e0
38
39#define ARCH_ID_AT91M40800 0x14080044 37#define ARCH_ID_AT91M40800 0x14080044
40#define ARCH_ID_AT91R40807 0x44080746 38#define ARCH_ID_AT91R40807 0x44080746
41#define ARCH_ID_AT91M40807 0x14080745 39#define ARCH_ID_AT91M40807 0x14080745
@@ -90,9 +88,16 @@ static inline unsigned long at91cap9_rev_identify(void)
90#endif 88#endif
91 89
92#ifdef CONFIG_ARCH_AT91RM9200 90#ifdef CONFIG_ARCH_AT91RM9200
91extern int rm9200_type;
92#define ARCH_REVISON_9200_BGA (0 << 0)
93#define ARCH_REVISON_9200_PQFP (1 << 0)
93#define cpu_is_at91rm9200() (at91_cpu_identify() == ARCH_ID_AT91RM9200) 94#define cpu_is_at91rm9200() (at91_cpu_identify() == ARCH_ID_AT91RM9200)
95#define cpu_is_at91rm9200_bga() (!cpu_is_at91rm9200_pqfp())
96#define cpu_is_at91rm9200_pqfp() (cpu_is_at91rm9200() && rm9200_type & ARCH_REVISON_9200_PQFP)
94#else 97#else
95#define cpu_is_at91rm9200() (0) 98#define cpu_is_at91rm9200() (0)
99#define cpu_is_at91rm9200_bga() (0)
100#define cpu_is_at91rm9200_pqfp() (0)
96#endif 101#endif
97 102
98#ifdef CONFIG_ARCH_AT91SAM9260 103#ifdef CONFIG_ARCH_AT91SAM9260
@@ -181,12 +186,6 @@ static inline unsigned long at91cap9_rev_identify(void)
181#define cpu_is_at91cap9_revC() (0) 186#define cpu_is_at91cap9_revC() (0)
182#endif 187#endif
183 188
184#ifdef CONFIG_ARCH_AT572D940HF
185#define cpu_is_at572d940hf() (at91_cpu_identify() == ARCH_ID_AT572D940HF)
186#else
187#define cpu_is_at572d940hf() (0)
188#endif
189
190/* 189/*
191 * Since this is ARM, we will never run on any AVR32 CPU. But these 190 * Since this is ARM, we will never run on any AVR32 CPU. But these
192 * definitions may reduce clutter in common drivers. 191 * definitions may reduce clutter in common drivers.
diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h
index 3d64a75e3ed..1008b9fb507 100644
--- a/arch/arm/mach-at91/include/mach/hardware.h
+++ b/arch/arm/mach-at91/include/mach/hardware.h
@@ -32,13 +32,17 @@
32#include <mach/at91cap9.h> 32#include <mach/at91cap9.h>
33#elif defined(CONFIG_ARCH_AT91X40) 33#elif defined(CONFIG_ARCH_AT91X40)
34#include <mach/at91x40.h> 34#include <mach/at91x40.h>
35#elif defined(CONFIG_ARCH_AT572D940HF)
36#include <mach/at572d940hf.h>
37#else 35#else
38#error "Unsupported AT91 processor" 36#error "Unsupported AT91 processor"
39#endif 37#endif
40 38
41 39
40/*
41 * Peripheral identifiers/interrupts.
42 */
43#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
44#define AT91_ID_SYS 1 /* System Peripherals */
45
42#ifdef CONFIG_MMU 46#ifdef CONFIG_MMU
43/* 47/*
44 * Remap the peripherals from address 0xFFF78000 .. 0xFFFFFFFF 48 * Remap the peripherals from address 0xFFF78000 .. 0xFFFFFFFF
@@ -82,13 +86,6 @@
82#define AT91_CHIPSELECT_6 0x70000000 86#define AT91_CHIPSELECT_6 0x70000000
83#define AT91_CHIPSELECT_7 0x80000000 87#define AT91_CHIPSELECT_7 0x80000000
84 88
85/* SDRAM */
86#ifdef CONFIG_DRAM_BASE
87#define AT91_SDRAM_BASE CONFIG_DRAM_BASE
88#else
89#define AT91_SDRAM_BASE AT91_CHIPSELECT_1
90#endif
91
92/* Clocks */ 89/* Clocks */
93#define AT91_SLOW_CLOCK 32768 /* slow clock */ 90#define AT91_SLOW_CLOCK 32768 /* slow clock */
94 91
diff --git a/arch/arm/mach-at91/include/mach/memory.h b/arch/arm/mach-at91/include/mach/memory.h
index c2cfe504064..401c207f2f3 100644
--- a/arch/arm/mach-at91/include/mach/memory.h
+++ b/arch/arm/mach-at91/include/mach/memory.h
@@ -23,6 +23,4 @@
23 23
24#include <mach/hardware.h> 24#include <mach/hardware.h>
25 25
26#define PLAT_PHYS_OFFSET (AT91_SDRAM_BASE)
27
28#endif 26#endif
diff --git a/arch/arm/mach-at91/include/mach/stamp9g20.h b/arch/arm/mach-at91/include/mach/stamp9g20.h
index 6120f9c46d5..f62c0abca4b 100644
--- a/arch/arm/mach-at91/include/mach/stamp9g20.h
+++ b/arch/arm/mach-at91/include/mach/stamp9g20.h
@@ -1,7 +1,7 @@
1#ifndef __MACH_STAMP9G20_H 1#ifndef __MACH_STAMP9G20_H
2#define __MACH_STAMP9G20_H 2#define __MACH_STAMP9G20_H
3 3
4void stamp9g20_map_io(void); 4void stamp9g20_init_early(void);
5void stamp9g20_board_init(void); 5void stamp9g20_board_init(void);
6 6
7#endif 7#endif
diff --git a/arch/arm/mach-at91/include/mach/system_rev.h b/arch/arm/mach-at91/include/mach/system_rev.h
new file mode 100644
index 00000000000..b855ee75f72
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/system_rev.h
@@ -0,0 +1,25 @@
1/*
2 * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
3 *
4 * Under GPLv2 only
5 */
6
7#ifndef __ARCH_SYSTEM_REV_H__
8#define __ARCH_SYSTEM_REV_H__
9
10/*
11 * board revision encoding
12 * mach specific
13 * the 16-31 bit are reserved for at91 generic information
14 *
15 * bit 31:
16 * 0 => nand 16 bit
17 * 1 => nand 8 bit
18 */
19#define BOARD_HAVE_NAND_8BIT (1 << 31)
20static int inline board_have_nand_8bit(void)
21{
22 return system_rev & BOARD_HAVE_NAND_8BIT;
23}
24
25#endif /* __ARCH_SYSTEM_REV_H__ */
diff --git a/arch/arm/mach-at91/include/mach/timex.h b/arch/arm/mach-at91/include/mach/timex.h
index 05a6e8af80c..31ac2d97f14 100644
--- a/arch/arm/mach-at91/include/mach/timex.h
+++ b/arch/arm/mach-at91/include/mach/timex.h
@@ -82,11 +82,6 @@
82#define AT91X40_MASTER_CLOCK 40000000 82#define AT91X40_MASTER_CLOCK 40000000
83#define CLOCK_TICK_RATE (AT91X40_MASTER_CLOCK) 83#define CLOCK_TICK_RATE (AT91X40_MASTER_CLOCK)
84 84
85#elif defined(CONFIG_ARCH_AT572D940HF)
86
87#define AT572D940HF_MASTER_CLOCK 80000000
88#define CLOCK_TICK_RATE (AT572D940HF_MASTER_CLOCK/16)
89
90#endif 85#endif
91 86
92#endif 87#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-16 12:02:20 -0500