diff options
Diffstat (limited to 'arch/arm/mach-at91/include/mach')
| -rw-r--r-- | arch/arm/mach-at91/include/mach/at91_pmc.h | 26 |
1 files changed, 20 insertions, 6 deletions
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h index 9561e33b8a9..64589eaaaee 100644 --- a/arch/arm/mach-at91/include/mach/at91_pmc.h +++ b/arch/arm/mach-at91/include/mach/at91_pmc.h | |||
| @@ -23,7 +23,7 @@ | |||
| 23 | #define AT91_PMC_PCK (1 << 0) /* Processor Clock */ | 23 | #define AT91_PMC_PCK (1 << 0) /* Processor Clock */ |
| 24 | #define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */ | 24 | #define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */ |
| 25 | #define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */ | 25 | #define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */ |
| 26 | #define AT91CAP9_PMC_DDR (1 << 2) /* DDR Clock [AT91CAP9 revC only] */ | 26 | #define AT91CAP9_PMC_DDR (1 << 2) /* DDR Clock [CAP9 revC & some SAM9 only] */ |
| 27 | #define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */ | 27 | #define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */ |
| 28 | #define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */ | 28 | #define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */ |
| 29 | #define AT91CAP9_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91CAP9 only] */ | 29 | #define AT91CAP9_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91CAP9 only] */ |
| @@ -39,11 +39,11 @@ | |||
| 39 | #define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */ | 39 | #define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */ |
| 40 | #define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */ | 40 | #define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */ |
| 41 | 41 | ||
| 42 | #define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [SAM9RL, CAP9] */ | 42 | #define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [some SAM9, CAP9] */ |
| 43 | #define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */ | 43 | #define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */ |
| 44 | #define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */ | 44 | #define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */ |
| 45 | #define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */ | 45 | #define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */ |
| 46 | #define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI PLL Start-up Time */ | 46 | #define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI BIAS Start-up Time */ |
| 47 | 47 | ||
| 48 | #define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */ | 48 | #define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */ |
| 49 | #define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ | 49 | #define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ |
| @@ -72,6 +72,7 @@ | |||
| 72 | #define AT91_PMC_CSS_MAIN (1 << 0) | 72 | #define AT91_PMC_CSS_MAIN (1 << 0) |
| 73 | #define AT91_PMC_CSS_PLLA (2 << 0) | 73 | #define AT91_PMC_CSS_PLLA (2 << 0) |
| 74 | #define AT91_PMC_CSS_PLLB (3 << 0) | 74 | #define AT91_PMC_CSS_PLLB (3 << 0) |
| 75 | #define AT91_PMC_CSS_UPLL (3 << 0) /* [some SAM9 only] */ | ||
| 75 | #define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */ | 76 | #define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */ |
| 76 | #define AT91_PMC_PRES_1 (0 << 2) | 77 | #define AT91_PMC_PRES_1 (0 << 2) |
| 77 | #define AT91_PMC_PRES_2 (1 << 2) | 78 | #define AT91_PMC_PRES_2 (1 << 2) |
| @@ -88,12 +89,25 @@ | |||
| 88 | #define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9,CAP9 only] */ | 89 | #define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9,CAP9 only] */ |
| 89 | #define AT91SAM9_PMC_MDIV_2 (1 << 8) | 90 | #define AT91SAM9_PMC_MDIV_2 (1 << 8) |
| 90 | #define AT91SAM9_PMC_MDIV_4 (2 << 8) | 91 | #define AT91SAM9_PMC_MDIV_4 (2 << 8) |
| 91 | #define AT91SAM9_PMC_MDIV_6 (3 << 8) | 92 | #define AT91SAM9_PMC_MDIV_6 (3 << 8) /* [some SAM9 only] */ |
| 93 | #define AT91SAM9_PMC_MDIV_3 (3 << 8) /* [some SAM9 only] */ | ||
| 92 | #define AT91_PMC_PDIV (1 << 12) /* Processor Clock Division [some SAM9 only] */ | 94 | #define AT91_PMC_PDIV (1 << 12) /* Processor Clock Division [some SAM9 only] */ |
| 93 | #define AT91_PMC_PDIV_1 (0 << 12) | 95 | #define AT91_PMC_PDIV_1 (0 << 12) |
| 94 | #define AT91_PMC_PDIV_2 (1 << 12) | 96 | #define AT91_PMC_PDIV_2 (1 << 12) |
| 97 | #define AT91_PMC_PLLADIV2 (1 << 12) /* PLLA divisor by 2 [some SAM9 only] */ | ||
| 98 | #define AT91_PMC_PLLADIV2_OFF (0 << 12) | ||
| 99 | #define AT91_PMC_PLLADIV2_ON (1 << 12) | ||
| 95 | 100 | ||
| 96 | #define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */ | 101 | #define AT91_PMC_USB (AT91_PMC + 0x38) /* USB Clock Register [some SAM9 only] */ |
| 102 | #define AT91_PMC_USBS (0x1 << 0) /* USB OHCI Input clock selection */ | ||
| 103 | #define AT91_PMC_USBS_PLLA (0 << 0) | ||
| 104 | #define AT91_PMC_USBS_UPLL (1 << 0) | ||
| 105 | #define AT91_PMC_OHCIUSBDIV (0xF << 8) /* Divider for USB OHCI Clock */ | ||
| 106 | |||
| 107 | #define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-N Registers */ | ||
| 108 | #define AT91_PMC_CSSMCK (0x1 << 8) /* CSS or Master Clock Selection */ | ||
| 109 | #define AT91_PMC_CSSMCK_CSS (0 << 8) | ||
| 110 | #define AT91_PMC_CSSMCK_MCK (1 << 8) | ||
| 97 | 111 | ||
| 98 | #define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */ | 112 | #define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */ |
| 99 | #define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */ | 113 | #define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */ |
| @@ -102,7 +116,7 @@ | |||
| 102 | #define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */ | 116 | #define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */ |
| 103 | #define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */ | 117 | #define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */ |
| 104 | #define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */ | 118 | #define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */ |
| 105 | #define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [AT91CAP9 only] */ | 119 | #define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [some SAM9, AT91CAP9 only] */ |
| 106 | #define AT91_PMC_OSCSEL (1 << 7) /* Slow Clock Oscillator [AT91CAP9 revC only] */ | 120 | #define AT91_PMC_OSCSEL (1 << 7) /* Slow Clock Oscillator [AT91CAP9 revC only] */ |
| 107 | #define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */ | 121 | #define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */ |
| 108 | #define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ | 122 | #define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ |