diff options
Diffstat (limited to 'arch/arm/mach-at91/include/mach/at91_pmc.h')
| -rw-r--r-- | arch/arm/mach-at91/include/mach/at91_pmc.h | 60 |
1 files changed, 48 insertions, 12 deletions
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h index dbdd6ae473d..f9fdbbe0c53 100644 --- a/arch/arm/mach-at91/include/mach/at91_pmc.h +++ b/arch/arm/mach-at91/include/mach/at91_pmc.h | |||
| @@ -45,9 +45,13 @@ | |||
| 45 | #define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI BIAS Start-up Time */ | 45 | #define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI BIAS Start-up Time */ |
| 46 | 46 | ||
| 47 | #define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */ | 47 | #define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */ |
| 48 | #define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ | 48 | #define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ |
| 49 | #define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x] */ | 49 | #define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass */ |
| 50 | #define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ | 50 | #define AT91_PMC_MOSCRCEN (1 << 3) /* Main On-Chip RC Oscillator Enable [some SAM9] */ |
| 51 | #define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ | ||
| 52 | #define AT91_PMC_KEY (0x37 << 16) /* MOR Writing Key */ | ||
| 53 | #define AT91_PMC_MOSCSEL (1 << 24) /* Main Oscillator Selection [some SAM9] */ | ||
| 54 | #define AT91_PMC_CFDEN (1 << 25) /* Clock Failure Detector Enable [some SAM9] */ | ||
| 51 | 55 | ||
| 52 | #define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */ | 56 | #define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */ |
| 53 | #define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */ | 57 | #define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */ |
| @@ -72,14 +76,24 @@ | |||
| 72 | #define AT91_PMC_CSS_PLLA (2 << 0) | 76 | #define AT91_PMC_CSS_PLLA (2 << 0) |
| 73 | #define AT91_PMC_CSS_PLLB (3 << 0) | 77 | #define AT91_PMC_CSS_PLLB (3 << 0) |
| 74 | #define AT91_PMC_CSS_UPLL (3 << 0) /* [some SAM9 only] */ | 78 | #define AT91_PMC_CSS_UPLL (3 << 0) /* [some SAM9 only] */ |
| 75 | #define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */ | 79 | #define PMC_PRES_OFFSET 2 |
| 76 | #define AT91_PMC_PRES_1 (0 << 2) | 80 | #define AT91_PMC_PRES (7 << PMC_PRES_OFFSET) /* Master Clock Prescaler */ |
| 77 | #define AT91_PMC_PRES_2 (1 << 2) | 81 | #define AT91_PMC_PRES_1 (0 << PMC_PRES_OFFSET) |
| 78 | #define AT91_PMC_PRES_4 (2 << 2) | 82 | #define AT91_PMC_PRES_2 (1 << PMC_PRES_OFFSET) |
| 79 | #define AT91_PMC_PRES_8 (3 << 2) | 83 | #define AT91_PMC_PRES_4 (2 << PMC_PRES_OFFSET) |
| 80 | #define AT91_PMC_PRES_16 (4 << 2) | 84 | #define AT91_PMC_PRES_8 (3 << PMC_PRES_OFFSET) |
| 81 | #define AT91_PMC_PRES_32 (5 << 2) | 85 | #define AT91_PMC_PRES_16 (4 << PMC_PRES_OFFSET) |
| 82 | #define AT91_PMC_PRES_64 (6 << 2) | 86 | #define AT91_PMC_PRES_32 (5 << PMC_PRES_OFFSET) |
| 87 | #define AT91_PMC_PRES_64 (6 << PMC_PRES_OFFSET) | ||
| 88 | #define PMC_ALT_PRES_OFFSET 4 | ||
| 89 | #define AT91_PMC_ALT_PRES (7 << PMC_ALT_PRES_OFFSET) /* Master Clock Prescaler [alternate location] */ | ||
| 90 | #define AT91_PMC_ALT_PRES_1 (0 << PMC_ALT_PRES_OFFSET) | ||
| 91 | #define AT91_PMC_ALT_PRES_2 (1 << PMC_ALT_PRES_OFFSET) | ||
| 92 | #define AT91_PMC_ALT_PRES_4 (2 << PMC_ALT_PRES_OFFSET) | ||
| 93 | #define AT91_PMC_ALT_PRES_8 (3 << PMC_ALT_PRES_OFFSET) | ||
| 94 | #define AT91_PMC_ALT_PRES_16 (4 << PMC_ALT_PRES_OFFSET) | ||
| 95 | #define AT91_PMC_ALT_PRES_32 (5 << PMC_ALT_PRES_OFFSET) | ||
| 96 | #define AT91_PMC_ALT_PRES_64 (6 << PMC_ALT_PRES_OFFSET) | ||
| 83 | #define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */ | 97 | #define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */ |
| 84 | #define AT91RM9200_PMC_MDIV_1 (0 << 8) /* [AT91RM9200 only] */ | 98 | #define AT91RM9200_PMC_MDIV_1 (0 << 8) /* [AT91RM9200 only] */ |
| 85 | #define AT91RM9200_PMC_MDIV_2 (1 << 8) | 99 | #define AT91RM9200_PMC_MDIV_2 (1 << 8) |
| @@ -103,7 +117,14 @@ | |||
| 103 | #define AT91_PMC_USBS_UPLL (1 << 0) | 117 | #define AT91_PMC_USBS_UPLL (1 << 0) |
| 104 | #define AT91_PMC_OHCIUSBDIV (0xF << 8) /* Divider for USB OHCI Clock */ | 118 | #define AT91_PMC_OHCIUSBDIV (0xF << 8) /* Divider for USB OHCI Clock */ |
| 105 | 119 | ||
| 120 | #define AT91_PMC_SMD (AT91_PMC + 0x3c) /* Soft Modem Clock Register [some SAM9 only] */ | ||
| 121 | #define AT91_PMC_SMDS (0x1 << 0) /* SMD input clock selection */ | ||
| 122 | #define AT91_PMC_SMD_DIV (0x1f << 8) /* SMD input clock divider */ | ||
| 123 | #define AT91_PMC_SMDDIV(n) (((n) << 8) & AT91_PMC_SMD_DIV) | ||
| 124 | |||
| 106 | #define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-N Registers */ | 125 | #define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-N Registers */ |
| 126 | #define AT91_PMC_ALT_PCKR_CSS (0x7 << 0) /* Programmable Clock Source Selection [alternate length] */ | ||
| 127 | #define AT91_PMC_CSS_MASTER (4 << 0) /* [some SAM9 only] */ | ||
| 107 | #define AT91_PMC_CSSMCK (0x1 << 8) /* CSS or Master Clock Selection */ | 128 | #define AT91_PMC_CSSMCK (0x1 << 8) /* CSS or Master Clock Selection */ |
| 108 | #define AT91_PMC_CSSMCK_CSS (0 << 8) | 129 | #define AT91_PMC_CSSMCK_CSS (0 << 8) |
| 109 | #define AT91_PMC_CSSMCK_MCK (1 << 8) | 130 | #define AT91_PMC_CSSMCK_MCK (1 << 8) |
| @@ -120,10 +141,25 @@ | |||
| 120 | #define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ | 141 | #define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ |
| 121 | #define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */ | 142 | #define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */ |
| 122 | #define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */ | 143 | #define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */ |
| 144 | #define AT91_PMC_MOSCSELS (1 << 16) /* Main Oscillator Selection [some SAM9] */ | ||
| 145 | #define AT91_PMC_MOSCRCS (1 << 17) /* Main On-Chip RC [some SAM9] */ | ||
| 146 | #define AT91_PMC_CFDEV (1 << 18) /* Clock Failure Detector Event [some SAM9] */ | ||
| 123 | #define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */ | 147 | #define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */ |
| 124 | 148 | ||
| 125 | #define AT91_PMC_PROT (AT91_PMC + 0xe4) /* Write Protect Mode Register [some SAM9] */ | 149 | #define AT91_PMC_PROT (AT91_PMC + 0xe4) /* Write Protect Mode Register [some SAM9] */ |
| 126 | #define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */ | 150 | #define AT91_PMC_WPEN (0x1 << 0) /* Write Protect Enable */ |
| 151 | #define AT91_PMC_WPKEY (0xffffff << 8) /* Write Protect Key */ | ||
| 152 | #define AT91_PMC_PROTKEY (0x504d43 << 8) /* Activation Code */ | ||
| 153 | |||
| 154 | #define AT91_PMC_WPSR (AT91_PMC + 0xe8) /* Write Protect Status Register [some SAM9] */ | ||
| 155 | #define AT91_PMC_WPVS (0x1 << 0) /* Write Protect Violation Status */ | ||
| 156 | #define AT91_PMC_WPVSRC (0xffff << 8) /* Write Protect Violation Source */ | ||
| 127 | 157 | ||
| 158 | #define AT91_PMC_PCR (AT91_PMC + 0x10c) /* Peripheral Control Register [some SAM9] */ | ||
| 159 | #define AT91_PMC_PCR_PID (0x3f << 0) /* Peripheral ID */ | ||
| 160 | #define AT91_PMC_PCR_CMD (0x1 << 12) /* Command */ | ||
| 161 | #define AT91_PMC_PCR_DIV (0x3 << 16) /* Divisor Value */ | ||
| 162 | #define AT91_PMC_PCRDIV(n) (((n) << 16) & AT91_PMC_PCR_DIV) | ||
| 163 | #define AT91_PMC_PCR_EN (0x1 << 28) /* Enable */ | ||
| 128 | 164 | ||
| 129 | #endif | 165 | #endif |