diff options
Diffstat (limited to 'arch/arm/mach-at91/include/mach/at91_aic.h')
| -rw-r--r-- | arch/arm/mach-at91/include/mach/at91_aic.h | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/arch/arm/mach-at91/include/mach/at91_aic.h b/arch/arm/mach-at91/include/mach/at91_aic.h index fd42a85b7eb..eaea66197fa 100644 --- a/arch/arm/mach-at91/include/mach/at91_aic.h +++ b/arch/arm/mach-at91/include/mach/at91_aic.h | |||
| @@ -30,11 +30,16 @@ extern void __iomem *at91_aic_base; | |||
| 30 | 30 | ||
| 31 | /* Number of irq lines managed by AIC */ | 31 | /* Number of irq lines managed by AIC */ |
| 32 | #define NR_AIC_IRQS 32 | 32 | #define NR_AIC_IRQS 32 |
| 33 | #define NR_AIC5_IRQS 128 | ||
| 34 | |||
| 35 | #define AT91_AIC5_SSR 0x0 /* Source Select Register [AIC5] */ | ||
| 36 | #define AT91_AIC5_INTSEL_MSK (0x7f << 0) /* Interrupt Line Selection Mask */ | ||
| 33 | 37 | ||
| 34 | #define AT91_AIC_IRQ_MIN_PRIORITY 0 | 38 | #define AT91_AIC_IRQ_MIN_PRIORITY 0 |
| 35 | #define AT91_AIC_IRQ_MAX_PRIORITY 7 | 39 | #define AT91_AIC_IRQ_MAX_PRIORITY 7 |
| 36 | 40 | ||
| 37 | #define AT91_AIC_SMR(n) ((n) * 4) /* Source Mode Registers 0-31 */ | 41 | #define AT91_AIC_SMR(n) ((n) * 4) /* Source Mode Registers 0-31 */ |
| 42 | #define AT91_AIC5_SMR 0x4 /* Source Mode Register [AIC5] */ | ||
| 38 | #define AT91_AIC_PRIOR (7 << 0) /* Priority Level */ | 43 | #define AT91_AIC_PRIOR (7 << 0) /* Priority Level */ |
| 39 | #define AT91_AIC_SRCTYPE (3 << 5) /* Interrupt Source Type */ | 44 | #define AT91_AIC_SRCTYPE (3 << 5) /* Interrupt Source Type */ |
| 40 | #define AT91_AIC_SRCTYPE_LOW (0 << 5) | 45 | #define AT91_AIC_SRCTYPE_LOW (0 << 5) |
| @@ -43,31 +48,52 @@ extern void __iomem *at91_aic_base; | |||
| 43 | #define AT91_AIC_SRCTYPE_RISING (3 << 5) | 48 | #define AT91_AIC_SRCTYPE_RISING (3 << 5) |
| 44 | 49 | ||
| 45 | #define AT91_AIC_SVR(n) (0x80 + ((n) * 4)) /* Source Vector Registers 0-31 */ | 50 | #define AT91_AIC_SVR(n) (0x80 + ((n) * 4)) /* Source Vector Registers 0-31 */ |
| 51 | #define AT91_AIC5_SVR 0x8 /* Source Vector Register [AIC5] */ | ||
| 46 | #define AT91_AIC_IVR 0x100 /* Interrupt Vector Register */ | 52 | #define AT91_AIC_IVR 0x100 /* Interrupt Vector Register */ |
| 53 | #define AT91_AIC5_IVR 0x10 /* Interrupt Vector Register [AIC5] */ | ||
| 47 | #define AT91_AIC_FVR 0x104 /* Fast Interrupt Vector Register */ | 54 | #define AT91_AIC_FVR 0x104 /* Fast Interrupt Vector Register */ |
| 55 | #define AT91_AIC5_FVR 0x14 /* Fast Interrupt Vector Register [AIC5] */ | ||
| 48 | #define AT91_AIC_ISR 0x108 /* Interrupt Status Register */ | 56 | #define AT91_AIC_ISR 0x108 /* Interrupt Status Register */ |
| 57 | #define AT91_AIC5_ISR 0x18 /* Interrupt Status Register [AIC5] */ | ||
| 49 | #define AT91_AIC_IRQID (0x1f << 0) /* Current Interrupt Identifier */ | 58 | #define AT91_AIC_IRQID (0x1f << 0) /* Current Interrupt Identifier */ |
| 50 | 59 | ||
| 51 | #define AT91_AIC_IPR 0x10c /* Interrupt Pending Register */ | 60 | #define AT91_AIC_IPR 0x10c /* Interrupt Pending Register */ |
| 61 | #define AT91_AIC5_IPR0 0x20 /* Interrupt Pending Register 0 [AIC5] */ | ||
| 62 | #define AT91_AIC5_IPR1 0x24 /* Interrupt Pending Register 1 [AIC5] */ | ||
| 63 | #define AT91_AIC5_IPR2 0x28 /* Interrupt Pending Register 2 [AIC5] */ | ||
| 64 | #define AT91_AIC5_IPR3 0x2c /* Interrupt Pending Register 3 [AIC5] */ | ||
| 52 | #define AT91_AIC_IMR 0x110 /* Interrupt Mask Register */ | 65 | #define AT91_AIC_IMR 0x110 /* Interrupt Mask Register */ |
| 66 | #define AT91_AIC5_IMR 0x30 /* Interrupt Mask Register [AIC5] */ | ||
| 53 | #define AT91_AIC_CISR 0x114 /* Core Interrupt Status Register */ | 67 | #define AT91_AIC_CISR 0x114 /* Core Interrupt Status Register */ |
| 68 | #define AT91_AIC5_CISR 0x34 /* Core Interrupt Status Register [AIC5] */ | ||
| 54 | #define AT91_AIC_NFIQ (1 << 0) /* nFIQ Status */ | 69 | #define AT91_AIC_NFIQ (1 << 0) /* nFIQ Status */ |
| 55 | #define AT91_AIC_NIRQ (1 << 1) /* nIRQ Status */ | 70 | #define AT91_AIC_NIRQ (1 << 1) /* nIRQ Status */ |
| 56 | 71 | ||
| 57 | #define AT91_AIC_IECR 0x120 /* Interrupt Enable Command Register */ | 72 | #define AT91_AIC_IECR 0x120 /* Interrupt Enable Command Register */ |
| 73 | #define AT91_AIC5_IECR 0x40 /* Interrupt Enable Command Register [AIC5] */ | ||
| 58 | #define AT91_AIC_IDCR 0x124 /* Interrupt Disable Command Register */ | 74 | #define AT91_AIC_IDCR 0x124 /* Interrupt Disable Command Register */ |
| 75 | #define AT91_AIC5_IDCR 0x44 /* Interrupt Disable Command Register [AIC5] */ | ||
| 59 | #define AT91_AIC_ICCR 0x128 /* Interrupt Clear Command Register */ | 76 | #define AT91_AIC_ICCR 0x128 /* Interrupt Clear Command Register */ |
| 77 | #define AT91_AIC5_ICCR 0x48 /* Interrupt Clear Command Register [AIC5] */ | ||
| 60 | #define AT91_AIC_ISCR 0x12c /* Interrupt Set Command Register */ | 78 | #define AT91_AIC_ISCR 0x12c /* Interrupt Set Command Register */ |
| 79 | #define AT91_AIC5_ISCR 0x4c /* Interrupt Set Command Register [AIC5] */ | ||
| 61 | #define AT91_AIC_EOICR 0x130 /* End of Interrupt Command Register */ | 80 | #define AT91_AIC_EOICR 0x130 /* End of Interrupt Command Register */ |
| 81 | #define AT91_AIC5_EOICR 0x38 /* End of Interrupt Command Register [AIC5] */ | ||
| 62 | #define AT91_AIC_SPU 0x134 /* Spurious Interrupt Vector Register */ | 82 | #define AT91_AIC_SPU 0x134 /* Spurious Interrupt Vector Register */ |
| 83 | #define AT91_AIC5_SPU 0x3c /* Spurious Interrupt Vector Register [AIC5] */ | ||
| 63 | #define AT91_AIC_DCR 0x138 /* Debug Control Register */ | 84 | #define AT91_AIC_DCR 0x138 /* Debug Control Register */ |
| 85 | #define AT91_AIC5_DCR 0x6c /* Debug Control Register [AIC5] */ | ||
| 64 | #define AT91_AIC_DCR_PROT (1 << 0) /* Protection Mode */ | 86 | #define AT91_AIC_DCR_PROT (1 << 0) /* Protection Mode */ |
| 65 | #define AT91_AIC_DCR_GMSK (1 << 1) /* General Mask */ | 87 | #define AT91_AIC_DCR_GMSK (1 << 1) /* General Mask */ |
| 66 | 88 | ||
| 67 | #define AT91_AIC_FFER 0x140 /* Fast Forcing Enable Register [SAM9 only] */ | 89 | #define AT91_AIC_FFER 0x140 /* Fast Forcing Enable Register [SAM9 only] */ |
| 90 | #define AT91_AIC5_FFER 0x50 /* Fast Forcing Enable Register [AIC5] */ | ||
| 68 | #define AT91_AIC_FFDR 0x144 /* Fast Forcing Disable Register [SAM9 only] */ | 91 | #define AT91_AIC_FFDR 0x144 /* Fast Forcing Disable Register [SAM9 only] */ |
| 92 | #define AT91_AIC5_FFDR 0x54 /* Fast Forcing Disable Register [AIC5] */ | ||
| 69 | #define AT91_AIC_FFSR 0x148 /* Fast Forcing Status Register [SAM9 only] */ | 93 | #define AT91_AIC_FFSR 0x148 /* Fast Forcing Status Register [SAM9 only] */ |
| 94 | #define AT91_AIC5_FFSR 0x58 /* Fast Forcing Status Register [AIC5] */ | ||
| 70 | 95 | ||
| 71 | void at91_aic_handle_irq(struct pt_regs *regs); | 96 | void at91_aic_handle_irq(struct pt_regs *regs); |
| 97 | void at91_aic5_handle_irq(struct pt_regs *regs); | ||
| 72 | 98 | ||
| 73 | #endif | 99 | #endif |