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-rw-r--r--arch/arm/mach-at91/include/mach/at91_aic.h53
-rw-r--r--arch/arm/mach-at91/include/mach/at91_pit.h32
-rw-r--r--arch/arm/mach-at91/include/mach/at91_rstc.h41
-rw-r--r--arch/arm/mach-at91/include/mach/at91_rtc.h75
-rw-r--r--arch/arm/mach-at91/include/mach/at91_shdwc.h38
-rw-r--r--arch/arm/mach-at91/include/mach/at91_spi.h81
-rw-r--r--arch/arm/mach-at91/include/mach/at91_ssc.h106
-rw-r--r--arch/arm/mach-at91/include/mach/at91_tc.h146
-rw-r--r--arch/arm/mach-at91/include/mach/at91_twi.h68
-rw-r--r--arch/arm/mach-at91/include/mach/at91cap9.h123
-rw-r--r--arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h108
-rw-r--r--arch/arm/mach-at91/include/mach/at91cap9_matrix.h137
-rw-r--r--arch/arm/mach-at91/include/mach/at91rm9200_emac.h138
-rw-r--r--arch/arm/mach-at91/include/mach/at_hdmac.h102
-rw-r--r--arch/arm/mach-at91/include/mach/board.h210
-rw-r--r--arch/arm/mach-at91/include/mach/entry-macro.S32
-rw-r--r--arch/arm/mach-at91/include/mach/gsia18s.h33
-rw-r--r--arch/arm/mach-at91/include/mach/irqs.h48
-rw-r--r--arch/arm/mach-at91/include/mach/stamp9g20.h7
-rw-r--r--arch/arm/mach-at91/include/mach/system.h59
-rw-r--r--arch/arm/mach-at91/include/mach/vmalloc.h26
21 files changed, 1663 insertions, 0 deletions
diff --git a/arch/arm/mach-at91/include/mach/at91_aic.h b/arch/arm/mach-at91/include/mach/at91_aic.h
new file mode 100644
index 00000000000..03566799d3b
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_aic.h
@@ -0,0 +1,53 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91_aic.h
3 *
4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People
6 *
7 * Advanced Interrupt Controller (AIC) - System peripherals registers.
8 * Based on AT91RM9200 datasheet revision E.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef AT91_AIC_H
17#define AT91_AIC_H
18
19#define AT91_AIC_SMR(n) (AT91_AIC + ((n) * 4)) /* Source Mode Registers 0-31 */
20#define AT91_AIC_PRIOR (7 << 0) /* Priority Level */
21#define AT91_AIC_SRCTYPE (3 << 5) /* Interrupt Source Type */
22#define AT91_AIC_SRCTYPE_LOW (0 << 5)
23#define AT91_AIC_SRCTYPE_FALLING (1 << 5)
24#define AT91_AIC_SRCTYPE_HIGH (2 << 5)
25#define AT91_AIC_SRCTYPE_RISING (3 << 5)
26
27#define AT91_AIC_SVR(n) (AT91_AIC + 0x80 + ((n) * 4)) /* Source Vector Registers 0-31 */
28#define AT91_AIC_IVR (AT91_AIC + 0x100) /* Interrupt Vector Register */
29#define AT91_AIC_FVR (AT91_AIC + 0x104) /* Fast Interrupt Vector Register */
30#define AT91_AIC_ISR (AT91_AIC + 0x108) /* Interrupt Status Register */
31#define AT91_AIC_IRQID (0x1f << 0) /* Current Interrupt Identifier */
32
33#define AT91_AIC_IPR (AT91_AIC + 0x10c) /* Interrupt Pending Register */
34#define AT91_AIC_IMR (AT91_AIC + 0x110) /* Interrupt Mask Register */
35#define AT91_AIC_CISR (AT91_AIC + 0x114) /* Core Interrupt Status Register */
36#define AT91_AIC_NFIQ (1 << 0) /* nFIQ Status */
37#define AT91_AIC_NIRQ (1 << 1) /* nIRQ Status */
38
39#define AT91_AIC_IECR (AT91_AIC + 0x120) /* Interrupt Enable Command Register */
40#define AT91_AIC_IDCR (AT91_AIC + 0x124) /* Interrupt Disable Command Register */
41#define AT91_AIC_ICCR (AT91_AIC + 0x128) /* Interrupt Clear Command Register */
42#define AT91_AIC_ISCR (AT91_AIC + 0x12c) /* Interrupt Set Command Register */
43#define AT91_AIC_EOICR (AT91_AIC + 0x130) /* End of Interrupt Command Register */
44#define AT91_AIC_SPU (AT91_AIC + 0x134) /* Spurious Interrupt Vector Register */
45#define AT91_AIC_DCR (AT91_AIC + 0x138) /* Debug Control Register */
46#define AT91_AIC_DCR_PROT (1 << 0) /* Protection Mode */
47#define AT91_AIC_DCR_GMSK (1 << 1) /* General Mask */
48
49#define AT91_AIC_FFER (AT91_AIC + 0x140) /* Fast Forcing Enable Register [SAM9 only] */
50#define AT91_AIC_FFDR (AT91_AIC + 0x144) /* Fast Forcing Disable Register [SAM9 only] */
51#define AT91_AIC_FFSR (AT91_AIC + 0x148) /* Fast Forcing Status Register [SAM9 only] */
52
53#endif
diff --git a/arch/arm/mach-at91/include/mach/at91_pit.h b/arch/arm/mach-at91/include/mach/at91_pit.h
new file mode 100644
index 00000000000..974d0bd05b5
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_pit.h
@@ -0,0 +1,32 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91_pit.h
3 *
4 * Copyright (C) 2007 Andrew Victor
5 * Copyright (C) 2007 Atmel Corporation.
6 *
7 * Periodic Interval Timer (PIT) - System peripherals regsters.
8 * Based on AT91SAM9261 datasheet revision D.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef AT91_PIT_H
17#define AT91_PIT_H
18
19#define AT91_PIT_MR (AT91_PIT + 0x00) /* Mode Register */
20#define AT91_PIT_PITIEN (1 << 25) /* Timer Interrupt Enable */
21#define AT91_PIT_PITEN (1 << 24) /* Timer Enabled */
22#define AT91_PIT_PIV (0xfffff) /* Periodic Interval Value */
23
24#define AT91_PIT_SR (AT91_PIT + 0x04) /* Status Register */
25#define AT91_PIT_PITS (1 << 0) /* Timer Status */
26
27#define AT91_PIT_PIVR (AT91_PIT + 0x08) /* Periodic Interval Value Register */
28#define AT91_PIT_PIIR (AT91_PIT + 0x0c) /* Periodic Interval Image Register */
29#define AT91_PIT_PICNT (0xfff << 20) /* Interval Counter */
30#define AT91_PIT_CPIV (0xfffff) /* Inverval Value */
31
32#endif
diff --git a/arch/arm/mach-at91/include/mach/at91_rstc.h b/arch/arm/mach-at91/include/mach/at91_rstc.h
new file mode 100644
index 00000000000..cbd2bf052c1
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_rstc.h
@@ -0,0 +1,41 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91_rstc.h
3 *
4 * Copyright (C) 2007 Andrew Victor
5 * Copyright (C) 2007 Atmel Corporation.
6 *
7 * Reset Controller (RSTC) - System peripherals regsters.
8 * Based on AT91SAM9261 datasheet revision D.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef AT91_RSTC_H
17#define AT91_RSTC_H
18
19#define AT91_RSTC_CR (AT91_RSTC + 0x00) /* Reset Controller Control Register */
20#define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */
21#define AT91_RSTC_PERRST (1 << 2) /* Peripheral Reset */
22#define AT91_RSTC_EXTRST (1 << 3) /* External Reset */
23#define AT91_RSTC_KEY (0xa5 << 24) /* KEY Password */
24
25#define AT91_RSTC_SR (AT91_RSTC + 0x04) /* Reset Controller Status Register */
26#define AT91_RSTC_URSTS (1 << 0) /* User Reset Status */
27#define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */
28#define AT91_RSTC_RSTTYP_GENERAL (0 << 8)
29#define AT91_RSTC_RSTTYP_WAKEUP (1 << 8)
30#define AT91_RSTC_RSTTYP_WATCHDOG (2 << 8)
31#define AT91_RSTC_RSTTYP_SOFTWARE (3 << 8)
32#define AT91_RSTC_RSTTYP_USER (4 << 8)
33#define AT91_RSTC_NRSTL (1 << 16) /* NRST Pin Level */
34#define AT91_RSTC_SRCMP (1 << 17) /* Software Reset Command in Progress */
35
36#define AT91_RSTC_MR (AT91_RSTC + 0x08) /* Reset Controller Mode Register */
37#define AT91_RSTC_URSTEN (1 << 0) /* User Reset Enable */
38#define AT91_RSTC_URSTIEN (1 << 4) /* User Reset Interrupt Enable */
39#define AT91_RSTC_ERSTL (0xf << 8) /* External Reset Length */
40
41#endif
diff --git a/arch/arm/mach-at91/include/mach/at91_rtc.h b/arch/arm/mach-at91/include/mach/at91_rtc.h
new file mode 100644
index 00000000000..e56f4701a3e
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_rtc.h
@@ -0,0 +1,75 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91_rtc.h
3 *
4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People
6 *
7 * Real Time Clock (RTC) - System peripheral registers.
8 * Based on AT91RM9200 datasheet revision E.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef AT91_RTC_H
17#define AT91_RTC_H
18
19#define AT91_RTC_CR (AT91_RTC + 0x00) /* Control Register */
20#define AT91_RTC_UPDTIM (1 << 0) /* Update Request Time Register */
21#define AT91_RTC_UPDCAL (1 << 1) /* Update Request Calendar Register */
22#define AT91_RTC_TIMEVSEL (3 << 8) /* Time Event Selection */
23#define AT91_RTC_TIMEVSEL_MINUTE (0 << 8)
24#define AT91_RTC_TIMEVSEL_HOUR (1 << 8)
25#define AT91_RTC_TIMEVSEL_DAY24 (2 << 8)
26#define AT91_RTC_TIMEVSEL_DAY12 (3 << 8)
27#define AT91_RTC_CALEVSEL (3 << 16) /* Calendar Event Selection */
28#define AT91_RTC_CALEVSEL_WEEK (0 << 16)
29#define AT91_RTC_CALEVSEL_MONTH (1 << 16)
30#define AT91_RTC_CALEVSEL_YEAR (2 << 16)
31
32#define AT91_RTC_MR (AT91_RTC + 0x04) /* Mode Register */
33#define AT91_RTC_HRMOD (1 << 0) /* 12/24 Hour Mode */
34
35#define AT91_RTC_TIMR (AT91_RTC + 0x08) /* Time Register */
36#define AT91_RTC_SEC (0x7f << 0) /* Current Second */
37#define AT91_RTC_MIN (0x7f << 8) /* Current Minute */
38#define AT91_RTC_HOUR (0x3f << 16) /* Current Hour */
39#define AT91_RTC_AMPM (1 << 22) /* Ante Meridiem Post Meridiem Indicator */
40
41#define AT91_RTC_CALR (AT91_RTC + 0x0c) /* Calendar Register */
42#define AT91_RTC_CENT (0x7f << 0) /* Current Century */
43#define AT91_RTC_YEAR (0xff << 8) /* Current Year */
44#define AT91_RTC_MONTH (0x1f << 16) /* Current Month */
45#define AT91_RTC_DAY (7 << 21) /* Current Day */
46#define AT91_RTC_DATE (0x3f << 24) /* Current Date */
47
48#define AT91_RTC_TIMALR (AT91_RTC + 0x10) /* Time Alarm Register */
49#define AT91_RTC_SECEN (1 << 7) /* Second Alarm Enable */
50#define AT91_RTC_MINEN (1 << 15) /* Minute Alarm Enable */
51#define AT91_RTC_HOUREN (1 << 23) /* Hour Alarm Enable */
52
53#define AT91_RTC_CALALR (AT91_RTC + 0x14) /* Calendar Alarm Register */
54#define AT91_RTC_MTHEN (1 << 23) /* Month Alarm Enable */
55#define AT91_RTC_DATEEN (1 << 31) /* Date Alarm Enable */
56
57#define AT91_RTC_SR (AT91_RTC + 0x18) /* Status Register */
58#define AT91_RTC_ACKUPD (1 << 0) /* Acknowledge for Update */
59#define AT91_RTC_ALARM (1 << 1) /* Alarm Flag */
60#define AT91_RTC_SECEV (1 << 2) /* Second Event */
61#define AT91_RTC_TIMEV (1 << 3) /* Time Event */
62#define AT91_RTC_CALEV (1 << 4) /* Calendar Event */
63
64#define AT91_RTC_SCCR (AT91_RTC + 0x1c) /* Status Clear Command Register */
65#define AT91_RTC_IER (AT91_RTC + 0x20) /* Interrupt Enable Register */
66#define AT91_RTC_IDR (AT91_RTC + 0x24) /* Interrupt Disable Register */
67#define AT91_RTC_IMR (AT91_RTC + 0x28) /* Interrupt Mask Register */
68
69#define AT91_RTC_VER (AT91_RTC + 0x2c) /* Valid Entry Register */
70#define AT91_RTC_NVTIM (1 << 0) /* Non valid Time */
71#define AT91_RTC_NVCAL (1 << 1) /* Non valid Calendar */
72#define AT91_RTC_NVTIMALR (1 << 2) /* Non valid Time Alarm */
73#define AT91_RTC_NVCALALR (1 << 3) /* Non valid Calendar Alarm */
74
75#endif
diff --git a/arch/arm/mach-at91/include/mach/at91_shdwc.h b/arch/arm/mach-at91/include/mach/at91_shdwc.h
new file mode 100644
index 00000000000..c4ce07e8a8f
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_shdwc.h
@@ -0,0 +1,38 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91_shdwc.h
3 *
4 * Copyright (C) 2007 Andrew Victor
5 * Copyright (C) 2007 Atmel Corporation.
6 *
7 * Shutdown Controller (SHDWC) - System peripherals regsters.
8 * Based on AT91SAM9261 datasheet revision D.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef AT91_SHDWC_H
17#define AT91_SHDWC_H
18
19#define AT91_SHDW_CR (AT91_SHDWC + 0x00) /* Shut Down Control Register */
20#define AT91_SHDW_SHDW (1 << 0) /* Shut Down command */
21#define AT91_SHDW_KEY (0xa5 << 24) /* KEY Password */
22
23#define AT91_SHDW_MR (AT91_SHDWC + 0x04) /* Shut Down Mode Register */
24#define AT91_SHDW_WKMODE0 (3 << 0) /* Wake-up 0 Mode Selection */
25#define AT91_SHDW_WKMODE0_NONE 0
26#define AT91_SHDW_WKMODE0_HIGH 1
27#define AT91_SHDW_WKMODE0_LOW 2
28#define AT91_SHDW_WKMODE0_ANYLEVEL 3
29#define AT91_SHDW_CPTWK0 (0xf << 4) /* Counter On Wake Up 0 */
30#define AT91_SHDW_CPTWK0_(x) ((x) << 4)
31#define AT91_SHDW_RTTWKEN (1 << 16) /* Real Time Timer Wake-up Enable */
32
33#define AT91_SHDW_SR (AT91_SHDWC + 0x08) /* Shut Down Status Register */
34#define AT91_SHDW_WAKEUP0 (1 << 0) /* Wake-up 0 Status */
35#define AT91_SHDW_RTTWK (1 << 16) /* Real-time Timer Wake-up */
36#define AT91_SHDW_RTCWK (1 << 17) /* Real-time Clock Wake-up [SAM9RL] */
37
38#endif
diff --git a/arch/arm/mach-at91/include/mach/at91_spi.h b/arch/arm/mach-at91/include/mach/at91_spi.h
new file mode 100644
index 00000000000..2f6ba0c5636
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_spi.h
@@ -0,0 +1,81 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91_spi.h
3 *
4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People
6 *
7 * Serial Peripheral Interface (SPI) registers.
8 * Based on AT91RM9200 datasheet revision E.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef AT91_SPI_H
17#define AT91_SPI_H
18
19#define AT91_SPI_CR 0x00 /* Control Register */
20#define AT91_SPI_SPIEN (1 << 0) /* SPI Enable */
21#define AT91_SPI_SPIDIS (1 << 1) /* SPI Disable */
22#define AT91_SPI_SWRST (1 << 7) /* SPI Software Reset */
23#define AT91_SPI_LASTXFER (1 << 24) /* Last Transfer [SAM9261 only] */
24
25#define AT91_SPI_MR 0x04 /* Mode Register */
26#define AT91_SPI_MSTR (1 << 0) /* Master/Slave Mode */
27#define AT91_SPI_PS (1 << 1) /* Peripheral Select */
28#define AT91_SPI_PS_FIXED (0 << 1)
29#define AT91_SPI_PS_VARIABLE (1 << 1)
30#define AT91_SPI_PCSDEC (1 << 2) /* Chip Select Decode */
31#define AT91_SPI_DIV32 (1 << 3) /* Clock Selection [AT91RM9200 only] */
32#define AT91_SPI_MODFDIS (1 << 4) /* Mode Fault Detection */
33#define AT91_SPI_LLB (1 << 7) /* Local Loopback Enable */
34#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */
35#define AT91_SPI_DLYBCS (0xff << 24) /* Delay Between Chip Selects */
36
37#define AT91_SPI_RDR 0x08 /* Receive Data Register */
38#define AT91_SPI_RD (0xffff << 0) /* Receive Data */
39#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */
40
41#define AT91_SPI_TDR 0x0c /* Transmit Data Register */
42#define AT91_SPI_TD (0xffff << 0) /* Transmit Data */
43#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */
44#define AT91_SPI_LASTXFER (1 << 24) /* Last Transfer [SAM9261 only] */
45
46#define AT91_SPI_SR 0x10 /* Status Register */
47#define AT91_SPI_RDRF (1 << 0) /* Receive Data Register Full */
48#define AT91_SPI_TDRE (1 << 1) /* Transmit Data Register Full */
49#define AT91_SPI_MODF (1 << 2) /* Mode Fault Error */
50#define AT91_SPI_OVRES (1 << 3) /* Overrun Error Status */
51#define AT91_SPI_ENDRX (1 << 4) /* End of RX buffer */
52#define AT91_SPI_ENDTX (1 << 5) /* End of TX buffer */
53#define AT91_SPI_RXBUFF (1 << 6) /* RX Buffer Full */
54#define AT91_SPI_TXBUFE (1 << 7) /* TX Buffer Empty */
55#define AT91_SPI_NSSR (1 << 8) /* NSS Rising [SAM9261 only] */
56#define AT91_SPI_TXEMPTY (1 << 9) /* Transmission Register Empty [SAM9261 only] */
57#define AT91_SPI_SPIENS (1 << 16) /* SPI Enable Status */
58
59#define AT91_SPI_IER 0x14 /* Interrupt Enable Register */
60#define AT91_SPI_IDR 0x18 /* Interrupt Disable Register */
61#define AT91_SPI_IMR 0x1c /* Interrupt Mask Register */
62
63#define AT91_SPI_CSR(n) (0x30 + ((n) * 4)) /* Chip Select Registers 0-3 */
64#define AT91_SPI_CPOL (1 << 0) /* Clock Polarity */
65#define AT91_SPI_NCPHA (1 << 1) /* Clock Phase */
66#define AT91_SPI_CSAAT (1 << 3) /* Chip Select Active After Transfer [SAM9261 only] */
67#define AT91_SPI_BITS (0xf << 4) /* Bits Per Transfer */
68#define AT91_SPI_BITS_8 (0 << 4)
69#define AT91_SPI_BITS_9 (1 << 4)
70#define AT91_SPI_BITS_10 (2 << 4)
71#define AT91_SPI_BITS_11 (3 << 4)
72#define AT91_SPI_BITS_12 (4 << 4)
73#define AT91_SPI_BITS_13 (5 << 4)
74#define AT91_SPI_BITS_14 (6 << 4)
75#define AT91_SPI_BITS_15 (7 << 4)
76#define AT91_SPI_BITS_16 (8 << 4)
77#define AT91_SPI_SCBR (0xff << 8) /* Serial Clock Baud Rate */
78#define AT91_SPI_DLYBS (0xff << 16) /* Delay before SPCK */
79#define AT91_SPI_DLYBCT (0xff << 24) /* Delay between Consecutive Transfers */
80
81#endif
diff --git a/arch/arm/mach-at91/include/mach/at91_ssc.h b/arch/arm/mach-at91/include/mach/at91_ssc.h
new file mode 100644
index 00000000000..a81114c11c7
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_ssc.h
@@ -0,0 +1,106 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91_ssc.h
3 *
4 * Copyright (C) SAN People
5 *
6 * Serial Synchronous Controller (SSC) registers.
7 * Based on AT91RM9200 datasheet revision E.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#ifndef AT91_SSC_H
16#define AT91_SSC_H
17
18#define AT91_SSC_CR 0x00 /* Control Register */
19#define AT91_SSC_RXEN (1 << 0) /* Receive Enable */
20#define AT91_SSC_RXDIS (1 << 1) /* Receive Disable */
21#define AT91_SSC_TXEN (1 << 8) /* Transmit Enable */
22#define AT91_SSC_TXDIS (1 << 9) /* Transmit Disable */
23#define AT91_SSC_SWRST (1 << 15) /* Software Reset */
24
25#define AT91_SSC_CMR 0x04 /* Clock Mode Register */
26#define AT91_SSC_CMR_DIV (0xfff << 0) /* Clock Divider */
27
28#define AT91_SSC_RCMR 0x10 /* Receive Clock Mode Register */
29#define AT91_SSC_CKS (3 << 0) /* Clock Selection */
30#define AT91_SSC_CKS_DIV (0 << 0)
31#define AT91_SSC_CKS_CLOCK (1 << 0)
32#define AT91_SSC_CKS_PIN (2 << 0)
33#define AT91_SSC_CKO (7 << 2) /* Clock Output Mode Selection */
34#define AT91_SSC_CKO_NONE (0 << 2)
35#define AT91_SSC_CKO_CONTINUOUS (1 << 2)
36#define AT91_SSC_CKI (1 << 5) /* Clock Inversion */
37#define AT91_SSC_CKI_FALLING (0 << 5)
38#define AT91_SSC_CK_RISING (1 << 5)
39#define AT91_SSC_CKG (1 << 6) /* Receive Clock Gating Selection [AT91SAM9261 only] */
40#define AT91_SSC_CKG_NONE (0 << 6)
41#define AT91_SSC_CKG_RFLOW (1 << 6)
42#define AT91_SSC_CKG_RFHIGH (2 << 6)
43#define AT91_SSC_START (0xf << 8) /* Start Selection */
44#define AT91_SSC_START_CONTINUOUS (0 << 8)
45#define AT91_SSC_START_TX_RX (1 << 8)
46#define AT91_SSC_START_LOW_RF (2 << 8)
47#define AT91_SSC_START_HIGH_RF (3 << 8)
48#define AT91_SSC_START_FALLING_RF (4 << 8)
49#define AT91_SSC_START_RISING_RF (5 << 8)
50#define AT91_SSC_START_LEVEL_RF (6 << 8)
51#define AT91_SSC_START_EDGE_RF (7 << 8)
52#define AT91_SSC_STOP (1 << 12) /* Receive Stop Selection [AT91SAM9261 only] */
53#define AT91_SSC_STTDLY (0xff << 16) /* Start Delay */
54#define AT91_SSC_PERIOD (0xff << 24) /* Period Divider Selection */
55
56#define AT91_SSC_RFMR 0x14 /* Receive Frame Mode Register */
57#define AT91_SSC_DATALEN (0x1f << 0) /* Data Length */
58#define AT91_SSC_LOOP (1 << 5) /* Loop Mode */
59#define AT91_SSC_MSBF (1 << 7) /* Most Significant Bit First */
60#define AT91_SSC_DATNB (0xf << 8) /* Data Number per Frame */
61#define AT91_SSC_FSLEN (0xf << 16) /* Frame Sync Length */
62#define AT91_SSC_FSOS (7 << 20) /* Frame Sync Output Selection */
63#define AT91_SSC_FSOS_NONE (0 << 20)
64#define AT91_SSC_FSOS_NEGATIVE (1 << 20)
65#define AT91_SSC_FSOS_POSITIVE (2 << 20)
66#define AT91_SSC_FSOS_LOW (3 << 20)
67#define AT91_SSC_FSOS_HIGH (4 << 20)
68#define AT91_SSC_FSOS_TOGGLE (5 << 20)
69#define AT91_SSC_FSEDGE (1 << 24) /* Frame Sync Edge Detection */
70#define AT91_SSC_FSEDGE_POSITIVE (0 << 24)
71#define AT91_SSC_FSEDGE_NEGATIVE (1 << 24)
72
73#define AT91_SSC_TCMR 0x18 /* Transmit Clock Mode Register */
74#define AT91_SSC_TFMR 0x1c /* Transmit Fram Mode Register */
75#define AT91_SSC_DATDEF (1 << 5) /* Data Default Value */
76#define AT91_SSC_FSDEN (1 << 23) /* Frame Sync Data Enable */
77
78#define AT91_SSC_RHR 0x20 /* Receive Holding Register */
79#define AT91_SSC_THR 0x24 /* Transmit Holding Register */
80#define AT91_SSC_RSHR 0x30 /* Receive Sync Holding Register */
81#define AT91_SSC_TSHR 0x34 /* Transmit Sync Holding Register */
82
83#define AT91_SSC_RC0R 0x38 /* Receive Compare 0 Register [AT91SAM9261 only] */
84#define AT91_SSC_RC1R 0x3c /* Receive Compare 1 Register [AT91SAM9261 only] */
85
86#define AT91_SSC_SR 0x40 /* Status Register */
87#define AT91_SSC_TXRDY (1 << 0) /* Transmit Ready */
88#define AT91_SSC_TXEMPTY (1 << 1) /* Transmit Empty */
89#define AT91_SSC_ENDTX (1 << 2) /* End of Transmission */
90#define AT91_SSC_TXBUFE (1 << 3) /* Transmit Buffer Empty */
91#define AT91_SSC_RXRDY (1 << 4) /* Receive Ready */
92#define AT91_SSC_OVRUN (1 << 5) /* Receive Overrun */
93#define AT91_SSC_ENDRX (1 << 6) /* End of Reception */
94#define AT91_SSC_RXBUFF (1 << 7) /* Receive Buffer Full */
95#define AT91_SSC_CP0 (1 << 8) /* Compare 0 [AT91SAM9261 only] */
96#define AT91_SSC_CP1 (1 << 9) /* Compare 1 [AT91SAM9261 only] */
97#define AT91_SSC_TXSYN (1 << 10) /* Transmit Sync */
98#define AT91_SSC_RXSYN (1 << 11) /* Receive Sync */
99#define AT91_SSC_TXENA (1 << 16) /* Transmit Enable */
100#define AT91_SSC_RXENA (1 << 17) /* Receive Enable */
101
102#define AT91_SSC_IER 0x44 /* Interrupt Enable Register */
103#define AT91_SSC_IDR 0x48 /* Interrupt Disable Register */
104#define AT91_SSC_IMR 0x4c /* Interrupt Mask Register */
105
106#endif
diff --git a/arch/arm/mach-at91/include/mach/at91_tc.h b/arch/arm/mach-at91/include/mach/at91_tc.h
new file mode 100644
index 00000000000..46a317fd716
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_tc.h
@@ -0,0 +1,146 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91_tc.h
3 *
4 * Copyright (C) SAN People
5 *
6 * Timer/Counter Unit (TC) registers.
7 * Based on AT91RM9200 datasheet revision E.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#ifndef AT91_TC_H
16#define AT91_TC_H
17
18#define AT91_TC_BCR 0xc0 /* TC Block Control Register */
19#define AT91_TC_SYNC (1 << 0) /* Synchro Command */
20
21#define AT91_TC_BMR 0xc4 /* TC Block Mode Register */
22#define AT91_TC_TC0XC0S (3 << 0) /* External Clock Signal 0 Selection */
23#define AT91_TC_TC0XC0S_TCLK0 (0 << 0)
24#define AT91_TC_TC0XC0S_NONE (1 << 0)
25#define AT91_TC_TC0XC0S_TIOA1 (2 << 0)
26#define AT91_TC_TC0XC0S_TIOA2 (3 << 0)
27#define AT91_TC_TC1XC1S (3 << 2) /* External Clock Signal 1 Selection */
28#define AT91_TC_TC1XC1S_TCLK1 (0 << 2)
29#define AT91_TC_TC1XC1S_NONE (1 << 2)
30#define AT91_TC_TC1XC1S_TIOA0 (2 << 2)
31#define AT91_TC_TC1XC1S_TIOA2 (3 << 2)
32#define AT91_TC_TC2XC2S (3 << 4) /* External Clock Signal 2 Selection */
33#define AT91_TC_TC2XC2S_TCLK2 (0 << 4)
34#define AT91_TC_TC2XC2S_NONE (1 << 4)
35#define AT91_TC_TC2XC2S_TIOA0 (2 << 4)
36#define AT91_TC_TC2XC2S_TIOA1 (3 << 4)
37
38
39#define AT91_TC_CCR 0x00 /* Channel Control Register */
40#define AT91_TC_CLKEN (1 << 0) /* Counter Clock Enable Command */
41#define AT91_TC_CLKDIS (1 << 1) /* Counter CLock Disable Command */
42#define AT91_TC_SWTRG (1 << 2) /* Software Trigger Command */
43
44#define AT91_TC_CMR 0x04 /* Channel Mode Register */
45#define AT91_TC_TCCLKS (7 << 0) /* Capture/Waveform Mode: Clock Selection */
46#define AT91_TC_TIMER_CLOCK1 (0 << 0)
47#define AT91_TC_TIMER_CLOCK2 (1 << 0)
48#define AT91_TC_TIMER_CLOCK3 (2 << 0)
49#define AT91_TC_TIMER_CLOCK4 (3 << 0)
50#define AT91_TC_TIMER_CLOCK5 (4 << 0)
51#define AT91_TC_XC0 (5 << 0)
52#define AT91_TC_XC1 (6 << 0)
53#define AT91_TC_XC2 (7 << 0)
54#define AT91_TC_CLKI (1 << 3) /* Capture/Waveform Mode: Clock Invert */
55#define AT91_TC_BURST (3 << 4) /* Capture/Waveform Mode: Burst Signal Selection */
56#define AT91_TC_LDBSTOP (1 << 6) /* Capture Mode: Counter Clock Stopped with TB Loading */
57#define AT91_TC_LDBDIS (1 << 7) /* Capture Mode: Counter Clock Disable with RB Loading */
58#define AT91_TC_ETRGEDG (3 << 8) /* Capture Mode: External Trigger Edge Selection */
59#define AT91_TC_ABETRG (1 << 10) /* Capture Mode: TIOA or TIOB External Trigger Selection */
60#define AT91_TC_CPCTRG (1 << 14) /* Capture Mode: RC Compare Trigger Enable */
61#define AT91_TC_WAVE (1 << 15) /* Capture/Waveform mode */
62#define AT91_TC_LDRA (3 << 16) /* Capture Mode: RA Loading Selection */
63#define AT91_TC_LDRB (3 << 18) /* Capture Mode: RB Loading Selection */
64
65#define AT91_TC_CPCSTOP (1 << 6) /* Waveform Mode: Counter Clock Stopped with RC Compare */
66#define AT91_TC_CPCDIS (1 << 7) /* Waveform Mode: Counter Clock Disable with RC Compare */
67#define AT91_TC_EEVTEDG (3 << 8) /* Waveform Mode: External Event Edge Selection */
68#define AT91_TC_EEVTEDG_NONE (0 << 8)
69#define AT91_TC_EEVTEDG_RISING (1 << 8)
70#define AT91_TC_EEVTEDG_FALLING (2 << 8)
71#define AT91_TC_EEVTEDG_BOTH (3 << 8)
72#define AT91_TC_EEVT (3 << 10) /* Waveform Mode: External Event Selection */
73#define AT91_TC_EEVT_TIOB (0 << 10)
74#define AT91_TC_EEVT_XC0 (1 << 10)
75#define AT91_TC_EEVT_XC1 (2 << 10)
76#define AT91_TC_EEVT_XC2 (3 << 10)
77#define AT91_TC_ENETRG (1 << 12) /* Waveform Mode: External Event Trigger Enable */
78#define AT91_TC_WAVESEL (3 << 13) /* Waveform Mode: Waveform Selection */
79#define AT91_TC_WAVESEL_UP (0 << 13)
80#define AT91_TC_WAVESEL_UP_AUTO (2 << 13)
81#define AT91_TC_WAVESEL_UPDOWN (1 << 13)
82#define AT91_TC_WAVESEL_UPDOWN_AUTO (3 << 13)
83#define AT91_TC_ACPA (3 << 16) /* Waveform Mode: RA Compare Effect on TIOA */
84#define AT91_TC_ACPA_NONE (0 << 16)
85#define AT91_TC_ACPA_SET (1 << 16)
86#define AT91_TC_ACPA_CLEAR (2 << 16)
87#define AT91_TC_ACPA_TOGGLE (3 << 16)
88#define AT91_TC_ACPC (3 << 18) /* Waveform Mode: RC Compre Effect on TIOA */
89#define AT91_TC_ACPC_NONE (0 << 18)
90#define AT91_TC_ACPC_SET (1 << 18)
91#define AT91_TC_ACPC_CLEAR (2 << 18)
92#define AT91_TC_ACPC_TOGGLE (3 << 18)
93#define AT91_TC_AEEVT (3 << 20) /* Waveform Mode: External Event Effect on TIOA */
94#define AT91_TC_AEEVT_NONE (0 << 20)
95#define AT91_TC_AEEVT_SET (1 << 20)
96#define AT91_TC_AEEVT_CLEAR (2 << 20)
97#define AT91_TC_AEEVT_TOGGLE (3 << 20)
98#define AT91_TC_ASWTRG (3 << 22) /* Waveform Mode: Software Trigger Effect on TIOA */
99#define AT91_TC_ASWTRG_NONE (0 << 22)
100#define AT91_TC_ASWTRG_SET (1 << 22)
101#define AT91_TC_ASWTRG_CLEAR (2 << 22)
102#define AT91_TC_ASWTRG_TOGGLE (3 << 22)
103#define AT91_TC_BCPB (3 << 24) /* Waveform Mode: RB Compare Effect on TIOB */
104#define AT91_TC_BCPB_NONE (0 << 24)
105#define AT91_TC_BCPB_SET (1 << 24)
106#define AT91_TC_BCPB_CLEAR (2 << 24)
107#define AT91_TC_BCPB_TOGGLE (3 << 24)
108#define AT91_TC_BCPC (3 << 26) /* Waveform Mode: RC Compare Effect on TIOB */
109#define AT91_TC_BCPC_NONE (0 << 26)
110#define AT91_TC_BCPC_SET (1 << 26)
111#define AT91_TC_BCPC_CLEAR (2 << 26)
112#define AT91_TC_BCPC_TOGGLE (3 << 26)
113#define AT91_TC_BEEVT (3 << 28) /* Waveform Mode: External Event Effect on TIOB */
114#define AT91_TC_BEEVT_NONE (0 << 28)
115#define AT91_TC_BEEVT_SET (1 << 28)
116#define AT91_TC_BEEVT_CLEAR (2 << 28)
117#define AT91_TC_BEEVT_TOGGLE (3 << 28)
118#define AT91_TC_BSWTRG (3 << 30) /* Waveform Mode: Software Trigger Effect on TIOB */
119#define AT91_TC_BSWTRG_NONE (0 << 30)
120#define AT91_TC_BSWTRG_SET (1 << 30)
121#define AT91_TC_BSWTRG_CLEAR (2 << 30)
122#define AT91_TC_BSWTRG_TOGGLE (3 << 30)
123
124#define AT91_TC_CV 0x10 /* Counter Value */
125#define AT91_TC_RA 0x14 /* Register A */
126#define AT91_TC_RB 0x18 /* Register B */
127#define AT91_TC_RC 0x1c /* Register C */
128
129#define AT91_TC_SR 0x20 /* Status Register */
130#define AT91_TC_COVFS (1 << 0) /* Counter Overflow Status */
131#define AT91_TC_LOVRS (1 << 1) /* Load Overrun Status */
132#define AT91_TC_CPAS (1 << 2) /* RA Compare Status */
133#define AT91_TC_CPBS (1 << 3) /* RB Compare Status */
134#define AT91_TC_CPCS (1 << 4) /* RC Compare Status */
135#define AT91_TC_LDRAS (1 << 5) /* RA Loading Status */
136#define AT91_TC_LDRBS (1 << 6) /* RB Loading Status */
137#define AT91_TC_ETRGS (1 << 7) /* External Trigger Status */
138#define AT91_TC_CLKSTA (1 << 16) /* Clock Enabling Status */
139#define AT91_TC_MTIOA (1 << 17) /* TIOA Mirror */
140#define AT91_TC_MTIOB (1 << 18) /* TIOB Mirror */
141
142#define AT91_TC_IER 0x24 /* Interrupt Enable Register */
143#define AT91_TC_IDR 0x28 /* Interrupt Disable Register */
144#define AT91_TC_IMR 0x2c /* Interrupt Mask Register */
145
146#endif
diff --git a/arch/arm/mach-at91/include/mach/at91_twi.h b/arch/arm/mach-at91/include/mach/at91_twi.h
new file mode 100644
index 00000000000..bb2880f6ba3
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_twi.h
@@ -0,0 +1,68 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91_twi.h
3 *
4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People
6 *
7 * Two-wire Interface (TWI) registers.
8 * Based on AT91RM9200 datasheet revision E.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef AT91_TWI_H
17#define AT91_TWI_H
18
19#define AT91_TWI_CR 0x00 /* Control Register */
20#define AT91_TWI_START (1 << 0) /* Send a Start Condition */
21#define AT91_TWI_STOP (1 << 1) /* Send a Stop Condition */
22#define AT91_TWI_MSEN (1 << 2) /* Master Transfer Enable */
23#define AT91_TWI_MSDIS (1 << 3) /* Master Transfer Disable */
24#define AT91_TWI_SVEN (1 << 4) /* Slave Transfer Enable [SAM9260 only] */
25#define AT91_TWI_SVDIS (1 << 5) /* Slave Transfer Disable [SAM9260 only] */
26#define AT91_TWI_SWRST (1 << 7) /* Software Reset */
27
28#define AT91_TWI_MMR 0x04 /* Master Mode Register */
29#define AT91_TWI_IADRSZ (3 << 8) /* Internal Device Address Size */
30#define AT91_TWI_IADRSZ_NO (0 << 8)
31#define AT91_TWI_IADRSZ_1 (1 << 8)
32#define AT91_TWI_IADRSZ_2 (2 << 8)
33#define AT91_TWI_IADRSZ_3 (3 << 8)
34#define AT91_TWI_MREAD (1 << 12) /* Master Read Direction */
35#define AT91_TWI_DADR (0x7f << 16) /* Device Address */
36
37#define AT91_TWI_SMR 0x08 /* Slave Mode Register [SAM9260 only] */
38#define AT91_TWI_SADR (0x7f << 16) /* Slave Address */
39
40#define AT91_TWI_IADR 0x0c /* Internal Address Register */
41
42#define AT91_TWI_CWGR 0x10 /* Clock Waveform Generator Register */
43#define AT91_TWI_CLDIV (0xff << 0) /* Clock Low Divisor */
44#define AT91_TWI_CHDIV (0xff << 8) /* Clock High Divisor */
45#define AT91_TWI_CKDIV (7 << 16) /* Clock Divider */
46
47#define AT91_TWI_SR 0x20 /* Status Register */
48#define AT91_TWI_TXCOMP (1 << 0) /* Transmission Complete */
49#define AT91_TWI_RXRDY (1 << 1) /* Receive Holding Register Ready */
50#define AT91_TWI_TXRDY (1 << 2) /* Transmit Holding Register Ready */
51#define AT91_TWI_SVREAD (1 << 3) /* Slave Read [SAM9260 only] */
52#define AT91_TWI_SVACC (1 << 4) /* Slave Access [SAM9260 only] */
53#define AT91_TWI_GACC (1 << 5) /* General Call Access [SAM9260 only] */
54#define AT91_TWI_OVRE (1 << 6) /* Overrun Error [AT91RM9200 only] */
55#define AT91_TWI_UNRE (1 << 7) /* Underrun Error [AT91RM9200 only] */
56#define AT91_TWI_NACK (1 << 8) /* Not Acknowledged */
57#define AT91_TWI_ARBLST (1 << 9) /* Arbitration Lost [SAM9260 only] */
58#define AT91_TWI_SCLWS (1 << 10) /* Clock Wait State [SAM9260 only] */
59#define AT91_TWI_EOSACC (1 << 11) /* End of Slave Address [SAM9260 only] */
60
61#define AT91_TWI_IER 0x24 /* Interrupt Enable Register */
62#define AT91_TWI_IDR 0x28 /* Interrupt Disable Register */
63#define AT91_TWI_IMR 0x2c /* Interrupt Mask Register */
64#define AT91_TWI_RHR 0x30 /* Receive Holding Register */
65#define AT91_TWI_THR 0x34 /* Transmit Holding Register */
66
67#endif
68
diff --git a/arch/arm/mach-at91/include/mach/at91cap9.h b/arch/arm/mach-at91/include/mach/at91cap9.h
new file mode 100644
index 00000000000..c5df1e8f195
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91cap9.h
@@ -0,0 +1,123 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91cap9.h
3 *
4 * Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
5 * Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
6 * Copyright (C) 2007 Atmel Corporation.
7 *
8 * Common definitions.
9 * Based on AT91CAP9 datasheet revision B (Preliminary).
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
17#ifndef AT91CAP9_H
18#define AT91CAP9_H
19
20/*
21 * Peripheral identifiers/interrupts.
22 */
23#define AT91CAP9_ID_PIOABCD 2 /* Parallel IO Controller A, B, C and D */
24#define AT91CAP9_ID_MPB0 3 /* MP Block Peripheral 0 */
25#define AT91CAP9_ID_MPB1 4 /* MP Block Peripheral 1 */
26#define AT91CAP9_ID_MPB2 5 /* MP Block Peripheral 2 */
27#define AT91CAP9_ID_MPB3 6 /* MP Block Peripheral 3 */
28#define AT91CAP9_ID_MPB4 7 /* MP Block Peripheral 4 */
29#define AT91CAP9_ID_US0 8 /* USART 0 */
30#define AT91CAP9_ID_US1 9 /* USART 1 */
31#define AT91CAP9_ID_US2 10 /* USART 2 */
32#define AT91CAP9_ID_MCI0 11 /* Multimedia Card Interface 0 */
33#define AT91CAP9_ID_MCI1 12 /* Multimedia Card Interface 1 */
34#define AT91CAP9_ID_CAN 13 /* CAN */
35#define AT91CAP9_ID_TWI 14 /* Two-Wire Interface */
36#define AT91CAP9_ID_SPI0 15 /* Serial Peripheral Interface 0 */
37#define AT91CAP9_ID_SPI1 16 /* Serial Peripheral Interface 0 */
38#define AT91CAP9_ID_SSC0 17 /* Serial Synchronous Controller 0 */
39#define AT91CAP9_ID_SSC1 18 /* Serial Synchronous Controller 1 */
40#define AT91CAP9_ID_AC97C 19 /* AC97 Controller */
41#define AT91CAP9_ID_TCB 20 /* Timer Counter 0, 1 and 2 */
42#define AT91CAP9_ID_PWMC 21 /* Pulse Width Modulation Controller */
43#define AT91CAP9_ID_EMAC 22 /* Ethernet */
44#define AT91CAP9_ID_AESTDES 23 /* Advanced Encryption Standard, Triple DES */
45#define AT91CAP9_ID_ADC 24 /* Analog-to-Digital Converter */
46#define AT91CAP9_ID_ISI 25 /* Image Sensor Interface */
47#define AT91CAP9_ID_LCDC 26 /* LCD Controller */
48#define AT91CAP9_ID_DMA 27 /* DMA Controller */
49#define AT91CAP9_ID_UDPHS 28 /* USB High Speed Device Port */
50#define AT91CAP9_ID_UHP 29 /* USB Host Port */
51#define AT91CAP9_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */
52#define AT91CAP9_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */
53
54/*
55 * User Peripheral physical base addresses.
56 */
57#define AT91CAP9_BASE_UDPHS 0xfff78000
58#define AT91CAP9_BASE_TCB0 0xfff7c000
59#define AT91CAP9_BASE_TC0 0xfff7c000
60#define AT91CAP9_BASE_TC1 0xfff7c040
61#define AT91CAP9_BASE_TC2 0xfff7c080
62#define AT91CAP9_BASE_MCI0 0xfff80000
63#define AT91CAP9_BASE_MCI1 0xfff84000
64#define AT91CAP9_BASE_TWI 0xfff88000
65#define AT91CAP9_BASE_US0 0xfff8c000
66#define AT91CAP9_BASE_US1 0xfff90000
67#define AT91CAP9_BASE_US2 0xfff94000
68#define AT91CAP9_BASE_SSC0 0xfff98000
69#define AT91CAP9_BASE_SSC1 0xfff9c000
70#define AT91CAP9_BASE_AC97C 0xfffa0000
71#define AT91CAP9_BASE_SPI0 0xfffa4000
72#define AT91CAP9_BASE_SPI1 0xfffa8000
73#define AT91CAP9_BASE_CAN 0xfffac000
74#define AT91CAP9_BASE_PWMC 0xfffb8000
75#define AT91CAP9_BASE_EMAC 0xfffbc000
76#define AT91CAP9_BASE_ADC 0xfffc0000
77#define AT91CAP9_BASE_ISI 0xfffc4000
78
79/*
80 * System Peripherals (offset from AT91_BASE_SYS)
81 */
82#define AT91_ECC (0xffffe200 - AT91_BASE_SYS)
83#define AT91_BCRAMC (0xffffe400 - AT91_BASE_SYS)
84#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS)
85#define AT91_SMC (0xffffe800 - AT91_BASE_SYS)
86#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS)
87#define AT91_CCFG (0xffffeb10 - AT91_BASE_SYS)
88#define AT91_DMA (0xffffec00 - AT91_BASE_SYS)
89#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
90#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
91#define AT91_PIOA (0xfffff200 - AT91_BASE_SYS)
92#define AT91_PIOB (0xfffff400 - AT91_BASE_SYS)
93#define AT91_PIOC (0xfffff600 - AT91_BASE_SYS)
94#define AT91_PIOD (0xfffff800 - AT91_BASE_SYS)
95#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
96#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
97#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
98#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
99#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
100#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
101#define AT91_GPBR (cpu_is_at91cap9_revB() ? \
102 (0xfffffd50 - AT91_BASE_SYS) : \
103 (0xfffffd60 - AT91_BASE_SYS))
104
105#define AT91_USART0 AT91CAP9_BASE_US0
106#define AT91_USART1 AT91CAP9_BASE_US1
107#define AT91_USART2 AT91CAP9_BASE_US2
108
109
110/*
111 * Internal Memory.
112 */
113#define AT91CAP9_SRAM_BASE 0x00100000 /* Internal SRAM base address */
114#define AT91CAP9_SRAM_SIZE (32 * SZ_1K) /* Internal SRAM size (32Kb) */
115
116#define AT91CAP9_ROM_BASE 0x00400000 /* Internal ROM base address */
117#define AT91CAP9_ROM_SIZE (32 * SZ_1K) /* Internal ROM size (32Kb) */
118
119#define AT91CAP9_LCDC_BASE 0x00500000 /* LCD Controller */
120#define AT91CAP9_UDPHS_FIFO 0x00600000 /* USB High Speed Device Port */
121#define AT91CAP9_UHP_BASE 0x00700000 /* USB Host controller */
122
123#endif
diff --git a/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h b/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h
new file mode 100644
index 00000000000..976f4a6c335
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h
@@ -0,0 +1,108 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h
3 *
4 * (C) 2008 Andrew Victor
5 *
6 * DDR/SDR Controller (DDRSDRC) - System peripherals registers.
7 * Based on AT91CAP9 datasheet revision B.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#ifndef AT91CAP9_DDRSDR_H
16#define AT91CAP9_DDRSDR_H
17
18#define AT91_DDRSDRC_MR 0x00 /* Mode Register */
19#define AT91_DDRSDRC_MODE (0xf << 0) /* Command Mode */
20#define AT91_DDRSDRC_MODE_NORMAL 0
21#define AT91_DDRSDRC_MODE_NOP 1
22#define AT91_DDRSDRC_MODE_PRECHARGE 2
23#define AT91_DDRSDRC_MODE_LMR 3
24#define AT91_DDRSDRC_MODE_REFRESH 4
25#define AT91_DDRSDRC_MODE_EXT_LMR 5
26#define AT91_DDRSDRC_MODE_DEEP 6
27
28#define AT91_DDRSDRC_RTR 0x04 /* Refresh Timer Register */
29#define AT91_DDRSDRC_COUNT (0xfff << 0) /* Refresh Timer Counter */
30
31#define AT91_DDRSDRC_CR 0x08 /* Configuration Register */
32#define AT91_DDRSDRC_NC (3 << 0) /* Number of Column Bits */
33#define AT91_DDRSDRC_NC_SDR8 (0 << 0)
34#define AT91_DDRSDRC_NC_SDR9 (1 << 0)
35#define AT91_DDRSDRC_NC_SDR10 (2 << 0)
36#define AT91_DDRSDRC_NC_SDR11 (3 << 0)
37#define AT91_DDRSDRC_NC_DDR9 (0 << 0)
38#define AT91_DDRSDRC_NC_DDR10 (1 << 0)
39#define AT91_DDRSDRC_NC_DDR11 (2 << 0)
40#define AT91_DDRSDRC_NC_DDR12 (3 << 0)
41#define AT91_DDRSDRC_NR (3 << 2) /* Number of Row Bits */
42#define AT91_DDRSDRC_NR_11 (0 << 2)
43#define AT91_DDRSDRC_NR_12 (1 << 2)
44#define AT91_DDRSDRC_NR_13 (2 << 2)
45#define AT91_DDRSDRC_CAS (7 << 4) /* CAS Latency */
46#define AT91_DDRSDRC_CAS_2 (2 << 4)
47#define AT91_DDRSDRC_CAS_3 (3 << 4)
48#define AT91_DDRSDRC_CAS_25 (6 << 4)
49#define AT91_DDRSDRC_DLL (1 << 7) /* Reset DLL */
50#define AT91_DDRSDRC_DICDS (1 << 8) /* Output impedance control */
51
52#define AT91_DDRSDRC_T0PR 0x0C /* Timing 0 Register */
53#define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */
54#define AT91_DDRSDRC_TRCD (0xf << 4) /* Row to Column delay */
55#define AT91_DDRSDRC_TWR (0xf << 8) /* Write recovery delay */
56#define AT91_DDRSDRC_TRC (0xf << 12) /* Row cycle delay */
57#define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */
58#define AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */
59#define AT91_DDRSDRC_TWTR (1 << 24) /* Internal Write to Read delay */
60#define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */
61
62#define AT91_DDRSDRC_T1PR 0x10 /* Timing 1 Register */
63#define AT91_DDRSDRC_TRFC (0x1f << 0) /* Row Cycle Delay */
64#define AT91_DDRSDRC_TXSNR (0xff << 8) /* Exit self-refresh to non-read */
65#define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */
66#define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */
67
68#define AT91_DDRSDRC_LPR 0x18 /* Low Power Register */
69#define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */
70#define AT91_DDRSDRC_LPCB_DISABLE 0
71#define AT91_DDRSDRC_LPCB_SELF_REFRESH 1
72#define AT91_DDRSDRC_LPCB_POWER_DOWN 2
73#define AT91_DDRSDRC_LPCB_DEEP_POWER_DOWN 3
74#define AT91_DDRSDRC_CLKFR (1 << 2) /* Clock Frozen */
75#define AT91_DDRSDRC_PASR (7 << 4) /* Partial Array Self Refresh */
76#define AT91_DDRSDRC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */
77#define AT91_DDRSDRC_DS (3 << 10) /* Drive Strength */
78#define AT91_DDRSDRC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */
79#define AT91_DDRSDRC_TIMEOUT_0_CLK_CYCLES (0 << 12)
80#define AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES (1 << 12)
81#define AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES (2 << 12)
82
83#define AT91_DDRSDRC_MDR 0x1C /* Memory Device Register */
84#define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */
85#define AT91_DDRSDRC_MD_SDR 0
86#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1
87#define AT91_DDRSDRC_MD_DDR 2
88#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3
89
90#define AT91_DDRSDRC_DLLR 0x20 /* DLL Information Register */
91#define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */
92#define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */
93#define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */
94#define AT91_DDRSDRC_SDCOVF (1 << 3) /* Slave Delay Correction Overflow */
95#define AT91_DDRSDRC_SDCUDF (1 << 4) /* Slave Delay Correction Underflow */
96#define AT91_DDRSDRC_SDERF (1 << 5) /* Slave Delay Correction error */
97#define AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */
98#define AT91_DDRSDRC_SDVAL (0xff << 16) /* Slave Delay value */
99#define AT91_DDRSDRC_SDCVAL (0xff << 24) /* Slave Delay Correction value */
100
101/* Register access macros */
102#define at91_ramc_read(num, reg) \
103 at91_sys_read(AT91_DDRSDRC##num + reg)
104#define at91_ramc_write(num, reg, value) \
105 at91_sys_write(AT91_DDRSDRC##num + reg, value)
106
107
108#endif
diff --git a/arch/arm/mach-at91/include/mach/at91cap9_matrix.h b/arch/arm/mach-at91/include/mach/at91cap9_matrix.h
new file mode 100644
index 00000000000..4b9d4aff4b4
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91cap9_matrix.h
@@ -0,0 +1,137 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91cap9_matrix.h
3 *
4 * Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
5 * Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
6 * Copyright (C) 2006 Atmel Corporation.
7 *
8 * Memory Controllers (MATRIX, EBI) - System peripherals registers.
9 * Based on AT91CAP9 datasheet revision B (Preliminary).
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
17#ifndef AT91CAP9_MATRIX_H
18#define AT91CAP9_MATRIX_H
19
20#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
21#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
22#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
23#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
24#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
25#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */
26#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */
27#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */
28#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */
29#define AT91_MATRIX_MCFG9 (AT91_MATRIX + 0x24) /* Master Configuration Register 9 */
30#define AT91_MATRIX_MCFG10 (AT91_MATRIX + 0x28) /* Master Configuration Register 10 */
31#define AT91_MATRIX_MCFG11 (AT91_MATRIX + 0x2C) /* Master Configuration Register 11 */
32#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
33#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
34#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
35#define AT91_MATRIX_ULBT_FOUR (2 << 0)
36#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
37#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
38
39#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
40#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
41#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
42#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
43#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
44#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */
45#define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */
46#define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */
47#define AT91_MATRIX_SCFG8 (AT91_MATRIX + 0x60) /* Slave Configuration Register 8 */
48#define AT91_MATRIX_SCFG9 (AT91_MATRIX + 0x64) /* Slave Configuration Register 9 */
49#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
50#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
51#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
52#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
53#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
54#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
55#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
56#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
57#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
58
59#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
60#define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */
61#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
62#define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */
63#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
64#define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */
65#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
66#define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */
67#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
68#define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */
69#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */
70#define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */
71#define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */
72#define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */
73#define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */
74#define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */
75#define AT91_MATRIX_PRAS8 (AT91_MATRIX + 0xC0) /* Priority Register A for Slave 8 */
76#define AT91_MATRIX_PRBS8 (AT91_MATRIX + 0xC4) /* Priority Register B for Slave 8 */
77#define AT91_MATRIX_PRAS9 (AT91_MATRIX + 0xC8) /* Priority Register A for Slave 9 */
78#define AT91_MATRIX_PRBS9 (AT91_MATRIX + 0xCC) /* Priority Register B for Slave 9 */
79#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
80#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
81#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
82#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
83#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
84#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
85#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */
86#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */
87#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */
88#define AT91_MATRIX_M9PR (3 << 4) /* Master 9 Priority (in Register B) */
89#define AT91_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */
90#define AT91_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */
91
92#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
93#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
94#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
95#define AT91_MATRIX_RCB2 (1 << 2)
96#define AT91_MATRIX_RCB3 (1 << 3)
97#define AT91_MATRIX_RCB4 (1 << 4)
98#define AT91_MATRIX_RCB5 (1 << 5)
99#define AT91_MATRIX_RCB6 (1 << 6)
100#define AT91_MATRIX_RCB7 (1 << 7)
101#define AT91_MATRIX_RCB8 (1 << 8)
102#define AT91_MATRIX_RCB9 (1 << 9)
103#define AT91_MATRIX_RCB10 (1 << 10)
104#define AT91_MATRIX_RCB11 (1 << 11)
105
106#define AT91_MPBS0_SFR (AT91_MATRIX + 0x114) /* MPBlock Slave 0 Special Function Register */
107#define AT91_MPBS1_SFR (AT91_MATRIX + 0x11C) /* MPBlock Slave 1 Special Function Register */
108
109#define AT91_MATRIX_UDPHS (AT91_MATRIX + 0x118) /* USBHS Special Function Register [AT91CAP9 only] */
110#define AT91_MATRIX_SELECT_UDPHS (0 << 31) /* select High Speed UDP */
111#define AT91_MATRIX_SELECT_UDP (1 << 31) /* select standard UDP */
112#define AT91_MATRIX_UDPHS_BYPASS_LOCK (1 << 30) /* bypass lock bit */
113
114#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI Chip Select Assignment Register */
115#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
116#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
117#define AT91_MATRIX_EBI_CS1A_BCRAMC (1 << 1)
118#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */
119#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3)
120#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
121#define AT91_MATRIX_EBI_CS4A (1 << 4) /* Chip Select 4 Assignment */
122#define AT91_MATRIX_EBI_CS4A_SMC (0 << 4)
123#define AT91_MATRIX_EBI_CS4A_SMC_CF1 (1 << 4)
124#define AT91_MATRIX_EBI_CS5A (1 << 5) /* Chip Select 5 Assignment */
125#define AT91_MATRIX_EBI_CS5A_SMC (0 << 5)
126#define AT91_MATRIX_EBI_CS5A_SMC_CF2 (1 << 5)
127#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
128#define AT91_MATRIX_EBI_DQSPDC (1 << 9) /* Data Qualifier Strobe Pull-Down Configuration */
129#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */
130#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
131#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
132
133#define AT91_MPBS2_SFR (AT91_MATRIX + 0x12C) /* MPBlock Slave 2 Special Function Register */
134#define AT91_MPBS3_SFR (AT91_MATRIX + 0x130) /* MPBlock Slave 3 Special Function Register */
135#define AT91_APB_SFR (AT91_MATRIX + 0x134) /* APB Bridge Special Function Register */
136
137#endif
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200_emac.h b/arch/arm/mach-at91/include/mach/at91rm9200_emac.h
new file mode 100644
index 00000000000..b8260cd8041
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91rm9200_emac.h
@@ -0,0 +1,138 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91rm9200_emac.h
3 *
4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People
6 *
7 * Ethernet MAC registers.
8 * Based on AT91RM9200 datasheet revision E.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef AT91RM9200_EMAC_H
17#define AT91RM9200_EMAC_H
18
19#define AT91_EMAC_CTL 0x00 /* Control Register */
20#define AT91_EMAC_LB (1 << 0) /* Loopback */
21#define AT91_EMAC_LBL (1 << 1) /* Loopback Local */
22#define AT91_EMAC_RE (1 << 2) /* Receive Enable */
23#define AT91_EMAC_TE (1 << 3) /* Transmit Enable */
24#define AT91_EMAC_MPE (1 << 4) /* Management Port Enable */
25#define AT91_EMAC_CSR (1 << 5) /* Clear Statistics Registers */
26#define AT91_EMAC_INCSTAT (1 << 6) /* Increment Statistics Registers */
27#define AT91_EMAC_WES (1 << 7) /* Write Enable for Statistics Registers */
28#define AT91_EMAC_BP (1 << 8) /* Back Pressure */
29
30#define AT91_EMAC_CFG 0x04 /* Configuration Register */
31#define AT91_EMAC_SPD (1 << 0) /* Speed */
32#define AT91_EMAC_FD (1 << 1) /* Full Duplex */
33#define AT91_EMAC_BR (1 << 2) /* Bit Rate */
34#define AT91_EMAC_CAF (1 << 4) /* Copy All Frames */
35#define AT91_EMAC_NBC (1 << 5) /* No Broadcast */
36#define AT91_EMAC_MTI (1 << 6) /* Multicast Hash Enable */
37#define AT91_EMAC_UNI (1 << 7) /* Unicast Hash Enable */
38#define AT91_EMAC_BIG (1 << 8) /* Receive 1522 Bytes */
39#define AT91_EMAC_EAE (1 << 9) /* External Address Match Enable */
40#define AT91_EMAC_CLK (3 << 10) /* MDC Clock Divisor */
41#define AT91_EMAC_CLK_DIV8 (0 << 10)
42#define AT91_EMAC_CLK_DIV16 (1 << 10)
43#define AT91_EMAC_CLK_DIV32 (2 << 10)
44#define AT91_EMAC_CLK_DIV64 (3 << 10)
45#define AT91_EMAC_RTY (1 << 12) /* Retry Test */
46#define AT91_EMAC_RMII (1 << 13) /* Reduce MII (RMII) */
47
48#define AT91_EMAC_SR 0x08 /* Status Register */
49#define AT91_EMAC_SR_LINK (1 << 0) /* Link */
50#define AT91_EMAC_SR_MDIO (1 << 1) /* MDIO pin */
51#define AT91_EMAC_SR_IDLE (1 << 2) /* PHY idle */
52
53#define AT91_EMAC_TAR 0x0c /* Transmit Address Register */
54
55#define AT91_EMAC_TCR 0x10 /* Transmit Control Register */
56#define AT91_EMAC_LEN (0x7ff << 0) /* Transmit Frame Length */
57#define AT91_EMAC_NCRC (1 << 15) /* No CRC */
58
59#define AT91_EMAC_TSR 0x14 /* Transmit Status Register */
60#define AT91_EMAC_TSR_OVR (1 << 0) /* Transmit Buffer Overrun */
61#define AT91_EMAC_TSR_COL (1 << 1) /* Collision Occurred */
62#define AT91_EMAC_TSR_RLE (1 << 2) /* Retry Limit Exceeded */
63#define AT91_EMAC_TSR_IDLE (1 << 3) /* Transmitter Idle */
64#define AT91_EMAC_TSR_BNQ (1 << 4) /* Transmit Buffer not Queued */
65#define AT91_EMAC_TSR_COMP (1 << 5) /* Transmit Complete */
66#define AT91_EMAC_TSR_UND (1 << 6) /* Transmit Underrun */
67
68#define AT91_EMAC_RBQP 0x18 /* Receive Buffer Queue Pointer */
69
70#define AT91_EMAC_RSR 0x20 /* Receive Status Register */
71#define AT91_EMAC_RSR_BNA (1 << 0) /* Buffer Not Available */
72#define AT91_EMAC_RSR_REC (1 << 1) /* Frame Received */
73#define AT91_EMAC_RSR_OVR (1 << 2) /* RX Overrun */
74
75#define AT91_EMAC_ISR 0x24 /* Interrupt Status Register */
76#define AT91_EMAC_DONE (1 << 0) /* Management Done */
77#define AT91_EMAC_RCOM (1 << 1) /* Receive Complete */
78#define AT91_EMAC_RBNA (1 << 2) /* Receive Buffer Not Available */
79#define AT91_EMAC_TOVR (1 << 3) /* Transmit Buffer Overrun */
80#define AT91_EMAC_TUND (1 << 4) /* Transmit Buffer Underrun */
81#define AT91_EMAC_RTRY (1 << 5) /* Retry Limit */
82#define AT91_EMAC_TBRE (1 << 6) /* Transmit Buffer Register Empty */
83#define AT91_EMAC_TCOM (1 << 7) /* Transmit Complete */
84#define AT91_EMAC_TIDLE (1 << 8) /* Transmit Idle */
85#define AT91_EMAC_LINK (1 << 9) /* Link */
86#define AT91_EMAC_ROVR (1 << 10) /* RX Overrun */
87#define AT91_EMAC_ABT (1 << 11) /* Abort */
88
89#define AT91_EMAC_IER 0x28 /* Interrupt Enable Register */
90#define AT91_EMAC_IDR 0x2c /* Interrupt Disable Register */
91#define AT91_EMAC_IMR 0x30 /* Interrupt Mask Register */
92
93#define AT91_EMAC_MAN 0x34 /* PHY Maintenance Register */
94#define AT91_EMAC_DATA (0xffff << 0) /* MDIO Data */
95#define AT91_EMAC_REGA (0x1f << 18) /* MDIO Register */
96#define AT91_EMAC_PHYA (0x1f << 23) /* MDIO PHY Address */
97#define AT91_EMAC_RW (3 << 28) /* Read/Write operation */
98#define AT91_EMAC_RW_W (1 << 28)
99#define AT91_EMAC_RW_R (2 << 28)
100#define AT91_EMAC_MAN_802_3 0x40020000 /* IEEE 802.3 value */
101
102/*
103 * Statistics Registers.
104 */
105#define AT91_EMAC_FRA 0x40 /* Frames Transmitted OK */
106#define AT91_EMAC_SCOL 0x44 /* Single Collision Frame */
107#define AT91_EMAC_MCOL 0x48 /* Multiple Collision Frame */
108#define AT91_EMAC_OK 0x4c /* Frames Received OK */
109#define AT91_EMAC_SEQE 0x50 /* Frame Check Sequence Error */
110#define AT91_EMAC_ALE 0x54 /* Alignmemt Error */
111#define AT91_EMAC_DTE 0x58 /* Deffered Transmission Frame */
112#define AT91_EMAC_LCOL 0x5c /* Late Collision */
113#define AT91_EMAC_ECOL 0x60 /* Excessive Collision */
114#define AT91_EMAC_TUE 0x64 /* Transmit Underrun Error */
115#define AT91_EMAC_CSE 0x68 /* Carrier Sense Error */
116#define AT91_EMAC_DRFC 0x6c /* Discard RX Frame */
117#define AT91_EMAC_ROV 0x70 /* Receive Overrun */
118#define AT91_EMAC_CDE 0x74 /* Code Error */
119#define AT91_EMAC_ELR 0x78 /* Excessive Length Error */
120#define AT91_EMAC_RJB 0x7c /* Receive Jabber */
121#define AT91_EMAC_USF 0x80 /* Undersize Frame */
122#define AT91_EMAC_SQEE 0x84 /* SQE Test Error */
123
124/*
125 * Address Registers.
126 */
127#define AT91_EMAC_HSL 0x90 /* Hash Address Low [31:0] */
128#define AT91_EMAC_HSH 0x94 /* Hash Address High [63:32] */
129#define AT91_EMAC_SA1L 0x98 /* Specific Address 1 Low, bytes 0-3 */
130#define AT91_EMAC_SA1H 0x9c /* Specific Address 1 High, bytes 4-5 */
131#define AT91_EMAC_SA2L 0xa0 /* Specific Address 2 Low, bytes 0-3 */
132#define AT91_EMAC_SA2H 0xa4 /* Specific Address 2 High, bytes 4-5 */
133#define AT91_EMAC_SA3L 0xa8 /* Specific Address 3 Low, bytes 0-3 */
134#define AT91_EMAC_SA3H 0xac /* Specific Address 3 High, bytes 4-5 */
135#define AT91_EMAC_SA4L 0xb0 /* Specific Address 4 Low, bytes 0-3 */
136#define AT91_EMAC_SA4H 0xb4 /* Specific Address 4 High, bytes 4-5 */
137
138#endif
diff --git a/arch/arm/mach-at91/include/mach/at_hdmac.h b/arch/arm/mach-at91/include/mach/at_hdmac.h
new file mode 100644
index 00000000000..187cb58345c
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at_hdmac.h
@@ -0,0 +1,102 @@
1/*
2 * Header file for the Atmel AHB DMA Controller driver
3 *
4 * Copyright (C) 2008 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11#ifndef AT_HDMAC_H
12#define AT_HDMAC_H
13
14#include <linux/dmaengine.h>
15
16/**
17 * struct at_dma_platform_data - Controller configuration parameters
18 * @nr_channels: Number of channels supported by hardware (max 8)
19 * @cap_mask: dma_capability flags supported by the platform
20 */
21struct at_dma_platform_data {
22 unsigned int nr_channels;
23 dma_cap_mask_t cap_mask;
24};
25
26/**
27 * enum at_dma_slave_width - DMA slave register access width.
28 * @AT_DMA_SLAVE_WIDTH_8BIT: Do 8-bit slave register accesses
29 * @AT_DMA_SLAVE_WIDTH_16BIT: Do 16-bit slave register accesses
30 * @AT_DMA_SLAVE_WIDTH_32BIT: Do 32-bit slave register accesses
31 */
32enum at_dma_slave_width {
33 AT_DMA_SLAVE_WIDTH_8BIT = 0,
34 AT_DMA_SLAVE_WIDTH_16BIT,
35 AT_DMA_SLAVE_WIDTH_32BIT,
36};
37
38/**
39 * struct at_dma_slave - Controller-specific information about a slave
40 * @dma_dev: required DMA master device
41 * @tx_reg: physical address of data register used for
42 * memory-to-peripheral transfers
43 * @rx_reg: physical address of data register used for
44 * peripheral-to-memory transfers
45 * @reg_width: peripheral register width
46 * @cfg: Platform-specific initializer for the CFG register
47 * @ctrla: Platform-specific initializer for the CTRLA register
48 */
49struct at_dma_slave {
50 struct device *dma_dev;
51 dma_addr_t tx_reg;
52 dma_addr_t rx_reg;
53 enum at_dma_slave_width reg_width;
54 u32 cfg;
55 u32 ctrla;
56};
57
58
59/* Platform-configurable bits in CFG */
60#define ATC_SRC_PER(h) (0xFU & (h)) /* Channel src rq associated with periph handshaking ifc h */
61#define ATC_DST_PER(h) ((0xFU & (h)) << 4) /* Channel dst rq associated with periph handshaking ifc h */
62#define ATC_SRC_REP (0x1 << 8) /* Source Replay Mod */
63#define ATC_SRC_H2SEL (0x1 << 9) /* Source Handshaking Mod */
64#define ATC_SRC_H2SEL_SW (0x0 << 9)
65#define ATC_SRC_H2SEL_HW (0x1 << 9)
66#define ATC_DST_REP (0x1 << 12) /* Destination Replay Mod */
67#define ATC_DST_H2SEL (0x1 << 13) /* Destination Handshaking Mod */
68#define ATC_DST_H2SEL_SW (0x0 << 13)
69#define ATC_DST_H2SEL_HW (0x1 << 13)
70#define ATC_SOD (0x1 << 16) /* Stop On Done */
71#define ATC_LOCK_IF (0x1 << 20) /* Interface Lock */
72#define ATC_LOCK_B (0x1 << 21) /* AHB Bus Lock */
73#define ATC_LOCK_IF_L (0x1 << 22) /* Master Interface Arbiter Lock */
74#define ATC_LOCK_IF_L_CHUNK (0x0 << 22)
75#define ATC_LOCK_IF_L_BUFFER (0x1 << 22)
76#define ATC_AHB_PROT_MASK (0x7 << 24) /* AHB Protection */
77#define ATC_FIFOCFG_MASK (0x3 << 28) /* FIFO Request Configuration */
78#define ATC_FIFOCFG_LARGESTBURST (0x0 << 28)
79#define ATC_FIFOCFG_HALFFIFO (0x1 << 28)
80#define ATC_FIFOCFG_ENOUGHSPACE (0x2 << 28)
81
82/* Platform-configurable bits in CTRLA */
83#define ATC_SCSIZE_MASK (0x7 << 16) /* Source Chunk Transfer Size */
84#define ATC_SCSIZE_1 (0x0 << 16)
85#define ATC_SCSIZE_4 (0x1 << 16)
86#define ATC_SCSIZE_8 (0x2 << 16)
87#define ATC_SCSIZE_16 (0x3 << 16)
88#define ATC_SCSIZE_32 (0x4 << 16)
89#define ATC_SCSIZE_64 (0x5 << 16)
90#define ATC_SCSIZE_128 (0x6 << 16)
91#define ATC_SCSIZE_256 (0x7 << 16)
92#define ATC_DCSIZE_MASK (0x7 << 20) /* Destination Chunk Transfer Size */
93#define ATC_DCSIZE_1 (0x0 << 20)
94#define ATC_DCSIZE_4 (0x1 << 20)
95#define ATC_DCSIZE_8 (0x2 << 20)
96#define ATC_DCSIZE_16 (0x3 << 20)
97#define ATC_DCSIZE_32 (0x4 << 20)
98#define ATC_DCSIZE_64 (0x5 << 20)
99#define ATC_DCSIZE_128 (0x6 << 20)
100#define ATC_DCSIZE_256 (0x7 << 20)
101
102#endif /* AT_HDMAC_H */
diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
new file mode 100644
index 00000000000..ed544a0d5a1
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/board.h
@@ -0,0 +1,210 @@
1/*
2 * arch/arm/mach-at91/include/mach/board.h
3 *
4 * Copyright (C) 2005 HP Labs
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21/*
22 * These are data structures found in platform_device.dev.platform_data,
23 * and describing board-specific data needed by drivers. For example,
24 * which pin is used for a given GPIO role.
25 *
26 * In 2.6, drivers should strongly avoid board-specific knowledge so
27 * that supporting new boards normally won't require driver patches.
28 * Most board-specific knowledge should be in arch/.../board-*.c files.
29 */
30
31#ifndef __ASM_ARCH_BOARD_H
32#define __ASM_ARCH_BOARD_H
33
34#include <linux/mtd/partitions.h>
35#include <linux/device.h>
36#include <linux/i2c.h>
37#include <linux/leds.h>
38#include <linux/spi/spi.h>
39#include <linux/usb/atmel_usba_udc.h>
40#include <linux/atmel-mci.h>
41#include <sound/atmel-ac97c.h>
42#include <linux/serial.h>
43
44 /* USB Device */
45struct at91_udc_data {
46 u8 vbus_pin; /* high == host powering us */
47 u8 vbus_active_low; /* vbus polarity */
48 u8 vbus_polled; /* Use polling, not interrupt */
49 u8 pullup_pin; /* active == D+ pulled up */
50 u8 pullup_active_low; /* true == pullup_pin is active low */
51};
52extern void __init at91_add_device_udc(struct at91_udc_data *data);
53
54 /* USB High Speed Device */
55extern void __init at91_add_device_usba(struct usba_platform_data *data);
56
57 /* Compact Flash */
58struct at91_cf_data {
59 u8 irq_pin; /* I/O IRQ */
60 u8 det_pin; /* Card detect */
61 u8 vcc_pin; /* power switching */
62 u8 rst_pin; /* card reset */
63 u8 chipselect; /* EBI Chip Select number */
64 u8 flags;
65#define AT91_CF_TRUE_IDE 0x01
66#define AT91_IDE_SWAP_A0_A2 0x02
67};
68extern void __init at91_add_device_cf(struct at91_cf_data *data);
69
70 /* MMC / SD */
71 /* at91_mci platform config */
72struct at91_mmc_data {
73 u8 det_pin; /* card detect IRQ */
74 unsigned slot_b:1; /* uses Slot B */
75 unsigned wire4:1; /* (SD) supports DAT0..DAT3 */
76 u8 wp_pin; /* (SD) writeprotect detect */
77 u8 vcc_pin; /* power switching (high == on) */
78};
79extern void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data);
80
81 /* atmel-mci platform config */
82extern void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data);
83
84 /* Ethernet (EMAC & MACB) */
85struct at91_eth_data {
86 u32 phy_mask;
87 u8 phy_irq_pin; /* PHY IRQ */
88 u8 is_rmii; /* using RMII interface? */
89};
90extern void __init at91_add_device_eth(struct at91_eth_data *data);
91
92#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) || defined(CONFIG_ARCH_AT91SAM9G20) || defined(CONFIG_ARCH_AT91CAP9) \
93 || defined(CONFIG_ARCH_AT91SAM9G45)
94#define eth_platform_data at91_eth_data
95#endif
96
97 /* USB Host */
98struct at91_usbh_data {
99 u8 ports; /* number of ports on root hub */
100 u8 vbus_pin[2]; /* port power-control pin */
101};
102extern void __init at91_add_device_usbh(struct at91_usbh_data *data);
103extern void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data);
104extern void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data);
105
106 /* NAND / SmartMedia */
107struct atmel_nand_data {
108 u8 enable_pin; /* chip enable */
109 u8 det_pin; /* card detect */
110 u8 rdy_pin; /* ready/busy */
111 u8 rdy_pin_active_low; /* rdy_pin value is inverted */
112 u8 ale; /* address line number connected to ALE */
113 u8 cle; /* address line number connected to CLE */
114 u8 bus_width_16; /* buswidth is 16 bit */
115 struct mtd_partition* (*partition_info)(int, int*);
116};
117extern void __init at91_add_device_nand(struct atmel_nand_data *data);
118
119 /* I2C*/
120#if defined(CONFIG_ARCH_AT91SAM9G45)
121extern void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices);
122#else
123extern void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices);
124#endif
125
126 /* SPI */
127extern void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices);
128
129 /* Serial */
130#define ATMEL_UART_CTS 0x01
131#define ATMEL_UART_RTS 0x02
132#define ATMEL_UART_DSR 0x04
133#define ATMEL_UART_DTR 0x08
134#define ATMEL_UART_DCD 0x10
135#define ATMEL_UART_RI 0x20
136
137extern void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins);
138extern void __init at91_set_serial_console(unsigned portnr);
139
140extern struct platform_device *atmel_default_console_device;
141
142struct atmel_uart_data {
143 int num; /* port num */
144 short use_dma_tx; /* use transmit DMA? */
145 short use_dma_rx; /* use receive DMA? */
146 void __iomem *regs; /* virt. base address, if any */
147 struct serial_rs485 rs485; /* rs485 settings */
148};
149extern void __init at91_add_device_serial(void);
150
151/*
152 * PWM
153 */
154#define AT91_PWM0 0
155#define AT91_PWM1 1
156#define AT91_PWM2 2
157#define AT91_PWM3 3
158
159extern void __init at91_add_device_pwm(u32 mask);
160
161/*
162 * SSC -- accessed through ssc_request(id). Drivers don't bind to SSC
163 * platform devices. Their SSC ID is part of their configuration data,
164 * along with information about which SSC signals they should use.
165 */
166#define ATMEL_SSC_TK 0x01
167#define ATMEL_SSC_TF 0x02
168#define ATMEL_SSC_TD 0x04
169#define ATMEL_SSC_TX (ATMEL_SSC_TK | ATMEL_SSC_TF | ATMEL_SSC_TD)
170
171#define ATMEL_SSC_RK 0x10
172#define ATMEL_SSC_RF 0x20
173#define ATMEL_SSC_RD 0x40
174#define ATMEL_SSC_RX (ATMEL_SSC_RK | ATMEL_SSC_RF | ATMEL_SSC_RD)
175
176extern void __init at91_add_device_ssc(unsigned id, unsigned pins);
177
178 /* LCD Controller */
179struct atmel_lcdfb_info;
180extern void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data);
181
182 /* AC97 */
183extern void __init at91_add_device_ac97(struct ac97c_platform_data *data);
184
185 /* ISI */
186extern void __init at91_add_device_isi(void);
187
188 /* Touchscreen Controller */
189struct at91_tsadcc_data {
190 unsigned int adc_clock;
191 u8 pendet_debounce;
192 u8 ts_sample_hold_time;
193};
194extern void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data);
195
196/* CAN */
197struct at91_can_data {
198 void (*transceiver_switch)(int on);
199};
200extern void __init at91_add_device_can(struct at91_can_data *data);
201
202 /* LEDs */
203extern void __init at91_init_leds(u8 cpu_led, u8 timer_led);
204extern void __init at91_gpio_leds(struct gpio_led *leds, int nr);
205extern void __init at91_pwm_leds(struct gpio_led *leds, int nr);
206
207/* FIXME: this needs a better location, but gets stuff building again */
208extern int at91_suspend_entering_slow_clock(void);
209
210#endif
diff --git a/arch/arm/mach-at91/include/mach/entry-macro.S b/arch/arm/mach-at91/include/mach/entry-macro.S
new file mode 100644
index 00000000000..7ab68f97222
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/entry-macro.S
@@ -0,0 +1,32 @@
1/*
2 * arch/arm/mach-at91/include/mach/entry-macro.S
3 *
4 * Copyright (C) 2003-2005 SAN People
5 *
6 * Low-level IRQ helper macros for AT91RM9200 platforms
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <mach/hardware.h>
14#include <mach/at91_aic.h>
15
16 .macro disable_fiq
17 .endm
18
19 .macro get_irqnr_preamble, base, tmp
20 ldr \base, =(AT91_VA_BASE_SYS + AT91_AIC) @ base virtual address of AIC peripheral
21 .endm
22
23 .macro arch_ret_to_user, tmp1, tmp2
24 .endm
25
26 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
27 ldr \irqnr, [\base, #(AT91_AIC_IVR - AT91_AIC)] @ read IRQ vector register: de-asserts nIRQ to processor (and clears interrupt)
28 ldr \irqstat, [\base, #(AT91_AIC_ISR - AT91_AIC)] @ read interrupt source number
29 teq \irqstat, #0 @ ISR is 0 when no current interrupt, or spurious interrupt
30 streq \tmp, [\base, #(AT91_AIC_EOICR - AT91_AIC)] @ not going to be handled further, then ACK it now.
31 .endm
32
diff --git a/arch/arm/mach-at91/include/mach/gsia18s.h b/arch/arm/mach-at91/include/mach/gsia18s.h
new file mode 100644
index 00000000000..307c194926f
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/gsia18s.h
@@ -0,0 +1,33 @@
1/* Buttons */
2#define GPIO_TRIG_NET_IN AT91_PIN_PB21
3#define GPIO_CARD_UNMOUNT_0 AT91_PIN_PB13
4#define GPIO_CARD_UNMOUNT_1 AT91_PIN_PB12
5#define GPIO_KEY_POWER AT91_PIN_PA25
6
7/* PCF8574 0x20 GPIO - U1 on the GS_IA18-CB_V3 board */
8#define GS_IA18_S_PCF_GPIO_BASE0 NR_BUILTIN_GPIO
9#define PCF_GPIO_HDC_POWER (GS_IA18_S_PCF_GPIO_BASE0 + 0)
10#define PCF_GPIO_WIFI_SETUP (GS_IA18_S_PCF_GPIO_BASE0 + 1)
11#define PCF_GPIO_WIFI_ENABLE (GS_IA18_S_PCF_GPIO_BASE0 + 2)
12#define PCF_GPIO_WIFI_RESET (GS_IA18_S_PCF_GPIO_BASE0 + 3)
13#define PCF_GPIO_ETH_DETECT 4 /* this is a GPI */
14#define PCF_GPIO_GPS_SETUP (GS_IA18_S_PCF_GPIO_BASE0 + 5)
15#define PCF_GPIO_GPS_STANDBY (GS_IA18_S_PCF_GPIO_BASE0 + 6)
16#define PCF_GPIO_GPS_POWER (GS_IA18_S_PCF_GPIO_BASE0 + 7)
17
18/* PCF8574 0x22 GPIO - U1 on the GS_2G_OPT1-A_V0 board (Alarm) */
19#define GS_IA18_S_PCF_GPIO_BASE1 (GS_IA18_S_PCF_GPIO_BASE0 + 8)
20#define PCF_GPIO_ALARM1 (GS_IA18_S_PCF_GPIO_BASE1 + 0)
21#define PCF_GPIO_ALARM2 (GS_IA18_S_PCF_GPIO_BASE1 + 1)
22#define PCF_GPIO_ALARM3 (GS_IA18_S_PCF_GPIO_BASE1 + 2)
23#define PCF_GPIO_ALARM4 (GS_IA18_S_PCF_GPIO_BASE1 + 3)
24/* bits 4, 5, 6 not used */
25#define PCF_GPIO_ALARM_V_RELAY_ON (GS_IA18_S_PCF_GPIO_BASE1 + 7)
26
27/* PCF8574 0x24 GPIO U1 on the GS_2G-OPT23-A_V0 board (Modem) */
28#define GS_IA18_S_PCF_GPIO_BASE2 (GS_IA18_S_PCF_GPIO_BASE1 + 8)
29#define PCF_GPIO_MODEM_POWER (GS_IA18_S_PCF_GPIO_BASE2 + 0)
30#define PCF_GPIO_MODEM_RESET (GS_IA18_S_PCF_GPIO_BASE2 + 3)
31/* bits 1, 2, 4, 5 not used */
32#define PCF_GPIO_TRX_RESET (GS_IA18_S_PCF_GPIO_BASE2 + 6)
33/* bit 7 not used */
diff --git a/arch/arm/mach-at91/include/mach/irqs.h b/arch/arm/mach-at91/include/mach/irqs.h
new file mode 100644
index 00000000000..36bd55f3fc6
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/irqs.h
@@ -0,0 +1,48 @@
1/*
2 * arch/arm/mach-at91/include/mach/irqs.h
3 *
4 * Copyright (C) 2004 SAN People
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#ifndef __ASM_ARCH_IRQS_H
22#define __ASM_ARCH_IRQS_H
23
24#include <linux/io.h>
25#include <mach/at91_aic.h>
26
27#define NR_AIC_IRQS 32
28
29
30/*
31 * Acknowledge interrupt with AIC after interrupt has been handled.
32 * (by kernel/irq.c)
33 */
34#define irq_finish(irq) do { at91_sys_write(AT91_AIC_EOICR, 0); } while (0)
35
36
37/*
38 * IRQ interrupt symbols are the AT91xxx_ID_* symbols
39 * for IRQs handled directly through the AIC, or else the AT91_PIN_*
40 * symbols in gpio.h for ones handled indirectly as GPIOs.
41 * We make provision for 5 banks of GPIO.
42 */
43#define NR_IRQS (NR_AIC_IRQS + (5 * 32))
44
45/* FIQ is AIC source 0. */
46#define FIQ_START AT91_ID_FIQ
47
48#endif
diff --git a/arch/arm/mach-at91/include/mach/stamp9g20.h b/arch/arm/mach-at91/include/mach/stamp9g20.h
new file mode 100644
index 00000000000..f62c0abca4b
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/stamp9g20.h
@@ -0,0 +1,7 @@
1#ifndef __MACH_STAMP9G20_H
2#define __MACH_STAMP9G20_H
3
4void stamp9g20_init_early(void);
5void stamp9g20_board_init(void);
6
7#endif
diff --git a/arch/arm/mach-at91/include/mach/system.h b/arch/arm/mach-at91/include/mach/system.h
new file mode 100644
index 00000000000..36af14bc13b
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/system.h
@@ -0,0 +1,59 @@
1/*
2 * arch/arm/mach-at91/include/mach/system.h
3 *
4 * Copyright (C) 2003 SAN People
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#ifndef __ASM_ARCH_SYSTEM_H
22#define __ASM_ARCH_SYSTEM_H
23
24#include <mach/hardware.h>
25#include <mach/at91_st.h>
26#include <mach/at91_dbgu.h>
27#include <mach/at91_pmc.h>
28
29static inline void arch_idle(void)
30{
31 /*
32 * Disable the processor clock. The processor will be automatically
33 * re-enabled by an interrupt or by a reset.
34 */
35#ifdef AT91_PS
36 at91_sys_write(AT91_PS_CR, AT91_PS_CR_CPU);
37#else
38 at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
39#endif
40#ifndef CONFIG_CPU_ARM920T
41 /*
42 * Set the processor (CP15) into 'Wait for Interrupt' mode.
43 * Post-RM9200 processors need this in conjunction with the above
44 * to save power when idle.
45 */
46 cpu_do_idle();
47#endif
48}
49
50void (*at91_arch_reset)(void);
51
52static inline void arch_reset(char mode, const char *cmd)
53{
54 /* call the CPU-specific reset function */
55 if (at91_arch_reset)
56 (at91_arch_reset)();
57}
58
59#endif
diff --git a/arch/arm/mach-at91/include/mach/vmalloc.h b/arch/arm/mach-at91/include/mach/vmalloc.h
new file mode 100644
index 00000000000..8eb459f3f5b
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/vmalloc.h
@@ -0,0 +1,26 @@
1/*
2 * arch/arm/mach-at91/include/mach/vmalloc.h
3 *
4 * Copyright (C) 2003 SAN People
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#ifndef __ASM_ARCH_VMALLOC_H
22#define __ASM_ARCH_VMALLOC_H
23
24#define VMALLOC_END (AT91_VIRT_BASE & PGDIR_MASK)
25
26#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-13 22:27:29 -0400