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1/include/ "tegra30.dtsi"
2
3/**
4 * This file contains common DT entry for all fab version of Cardhu.
5 * There is multiple fab version of Cardhu starting from A01 to A07.
6 * Cardhu fab version A01 and A03 are not supported. Cardhu fab version
7 * A02 will have different sets of GPIOs for fixed regulator compare to
8 * Cardhu fab version A04. The Cardhu fab version A05, A06, A07 are
9 * compatible with fab version A04. Based on Cardhu fab version, the
10 * related dts file need to be chosen like for Cardhu fab version A02,
11 * use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use
12 * tegra30-cardhu-a04.dts.
13 * The identification of board is done in two ways, by looking the sticker
14 * on PCB and by reading board id eeprom.
15 * The stciker will have number like 600-81291-1000-002 C.3. In this 4th
16 * number is the fab version like here it is 002 and hence fab version A02.
17 * The (downstream internal) U-Boot of Cardhu display the board-id as
18 * follows:
19 * BoardID: 0C5B, SKU: 0A01, Fab: 02, Rev: 45.00
20 * In this Fab version is 02 i.e. A02.
21 * The BoardID I2C eeprom is interfaced through i2c5 (pwr_i2c address 0x56).
22 * The location 0x8 of this eeprom contains the Fab version. It is 1 byte
23 * wide.
24 */
25
26/ {
27 model = "NVIDIA Tegra30 Cardhu evaluation board";
28 compatible = "nvidia,cardhu", "nvidia,tegra30";
29
30 memory {
31 reg = <0x80000000 0x40000000>;
32 };
33
34 pinmux {
35 pinctrl-names = "default";
36 pinctrl-0 = <&state_default>;
37
38 state_default: pinmux {
39 sdmmc1_clk_pz0 {
40 nvidia,pins = "sdmmc1_clk_pz0";
41 nvidia,function = "sdmmc1";
42 nvidia,pull = <0>;
43 nvidia,tristate = <0>;
44 };
45 sdmmc1_cmd_pz1 {
46 nvidia,pins = "sdmmc1_cmd_pz1",
47 "sdmmc1_dat0_py7",
48 "sdmmc1_dat1_py6",
49 "sdmmc1_dat2_py5",
50 "sdmmc1_dat3_py4";
51 nvidia,function = "sdmmc1";
52 nvidia,pull = <2>;
53 nvidia,tristate = <0>;
54 };
55 sdmmc4_clk_pcc4 {
56 nvidia,pins = "sdmmc4_clk_pcc4",
57 "sdmmc4_rst_n_pcc3";
58 nvidia,function = "sdmmc4";
59 nvidia,pull = <0>;
60 nvidia,tristate = <0>;
61 };
62 sdmmc4_dat0_paa0 {
63 nvidia,pins = "sdmmc4_dat0_paa0",
64 "sdmmc4_dat1_paa1",
65 "sdmmc4_dat2_paa2",
66 "sdmmc4_dat3_paa3",
67 "sdmmc4_dat4_paa4",
68 "sdmmc4_dat5_paa5",
69 "sdmmc4_dat6_paa6",
70 "sdmmc4_dat7_paa7";
71 nvidia,function = "sdmmc4";
72 nvidia,pull = <2>;
73 nvidia,tristate = <0>;
74 };
75 dap2_fs_pa2 {
76 nvidia,pins = "dap2_fs_pa2",
77 "dap2_sclk_pa3",
78 "dap2_din_pa4",
79 "dap2_dout_pa5";
80 nvidia,function = "i2s1";
81 nvidia,pull = <0>;
82 nvidia,tristate = <0>;
83 };
84 };
85 };
86
87 serial@70006000 {
88 status = "okay";
89 clock-frequency = <408000000>;
90 };
91
92 i2c@7000c000 {
93 status = "okay";
94 clock-frequency = <100000>;
95 };
96
97 i2c@7000c400 {
98 status = "okay";
99 clock-frequency = <100000>;
100 };
101
102 i2c@7000c500 {
103 status = "okay";
104 clock-frequency = <100000>;
105
106 /* ALS and Proximity sensor */
107 isl29028@44 {
108 compatible = "isil,isl29028";
109 reg = <0x44>;
110 interrupt-parent = <&gpio>;
111 interrupts = <88 0x04>; /*gpio PL0 */
112 };
113 };
114
115 i2c@7000c700 {
116 status = "okay";
117 clock-frequency = <100000>;
118 };
119
120 i2c@7000d000 {
121 status = "okay";
122 clock-frequency = <100000>;
123
124 wm8903: wm8903@1a {
125 compatible = "wlf,wm8903";
126 reg = <0x1a>;
127 interrupt-parent = <&gpio>;
128 interrupts = <179 0x04>; /* gpio PW3 */
129
130 gpio-controller;
131 #gpio-cells = <2>;
132
133 micdet-cfg = <0>;
134 micdet-delay = <100>;
135 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
136 };
137
138 tps62361 {
139 compatible = "ti,tps62361";
140 reg = <0x60>;
141
142 regulator-name = "tps62361-vout";
143 regulator-min-microvolt = <500000>;
144 regulator-max-microvolt = <1500000>;
145 regulator-boot-on;
146 regulator-always-on;
147 ti,vsel0-state-high;
148 ti,vsel1-state-high;
149 };
150
151 pmic: tps65911@2d {
152 compatible = "ti,tps65911";
153 reg = <0x2d>;
154
155 interrupts = <0 86 0x4>;
156 #interrupt-cells = <2>;
157 interrupt-controller;
158
159 #gpio-cells = <2>;
160 gpio-controller;
161
162 vcc1-supply = <&vdd_ac_bat_reg>;
163 vcc2-supply = <&vdd_ac_bat_reg>;
164 vcc3-supply = <&vio_reg>;
165 vcc5-supply = <&vdd_ac_bat_reg>;
166 vcc6-supply = <&vdd2_reg>;
167 vcc7-supply = <&vdd_ac_bat_reg>;
168 vccio-supply = <&vdd_ac_bat_reg>;
169
170 regulators {
171 #address-cells = <1>;
172 #size-cells = <0>;
173
174 vdd1_reg: regulator@0 {
175 reg = <0>;
176 regulator-compatible = "vdd1";
177 regulator-name = "vddio_ddr_1v2";
178 regulator-min-microvolt = <1200000>;
179 regulator-max-microvolt = <1200000>;
180 regulator-always-on;
181 };
182
183 vdd2_reg: regulator@1 {
184 reg = <1>;
185 regulator-compatible = "vdd2";
186 regulator-name = "vdd_1v5_gen";
187 regulator-min-microvolt = <1500000>;
188 regulator-max-microvolt = <1500000>;
189 regulator-always-on;
190 };
191
192 vddctrl_reg: regulator@2 {
193 reg = <2>;
194 regulator-compatible = "vddctrl";
195 regulator-name = "vdd_cpu,vdd_sys";
196 regulator-min-microvolt = <1000000>;
197 regulator-max-microvolt = <1000000>;
198 regulator-always-on;
199 };
200
201 vio_reg: regulator@3 {
202 reg = <3>;
203 regulator-compatible = "vio";
204 regulator-name = "vdd_1v8_gen";
205 regulator-min-microvolt = <1800000>;
206 regulator-max-microvolt = <1800000>;
207 regulator-always-on;
208 };
209
210 ldo1_reg: regulator@4 {
211 reg = <4>;
212 regulator-compatible = "ldo1";
213 regulator-name = "vdd_pexa,vdd_pexb";
214 regulator-min-microvolt = <1050000>;
215 regulator-max-microvolt = <1050000>;
216 };
217
218 ldo2_reg: regulator@5 {
219 reg = <5>;
220 regulator-compatible = "ldo2";
221 regulator-name = "vdd_sata,avdd_plle";
222 regulator-min-microvolt = <1050000>;
223 regulator-max-microvolt = <1050000>;
224 };
225
226 /* LDO3 is not connected to anything */
227
228 ldo4_reg: regulator@7 {
229 reg = <7>;
230 regulator-compatible = "ldo4";
231 regulator-name = "vdd_rtc";
232 regulator-min-microvolt = <1200000>;
233 regulator-max-microvolt = <1200000>;
234 regulator-always-on;
235 };
236
237 ldo6_reg: regulator@9 {
238 reg = <9>;
239 regulator-compatible = "ldo6";
240 regulator-name = "avdd_dsi_csi,pwrdet_mipi";
241 regulator-min-microvolt = <1200000>;
242 regulator-max-microvolt = <1200000>;
243 };
244
245 ldo7_reg: regulator@10 {
246 reg = <10>;
247 regulator-compatible = "ldo7";
248 regulator-name = "vdd_pllm,x,u,a_p_c_s";
249 regulator-min-microvolt = <1200000>;
250 regulator-max-microvolt = <1200000>;
251 regulator-always-on;
252 };
253
254 ldo8_reg: regulator@11 {
255 reg = <11>;
256 regulator-compatible = "ldo8";
257 regulator-name = "vdd_ddr_hs";
258 regulator-min-microvolt = <1000000>;
259 regulator-max-microvolt = <1000000>;
260 regulator-always-on;
261 };
262 };
263 };
264 };
265
266 ahub {
267 i2s@70080400 {
268 status = "okay";
269 };
270 };
271
272 pmc {
273 status = "okay";
274 nvidia,invert-interrupt;
275 };
276
277 sdhci@78000000 {
278 status = "okay";
279 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
280 wp-gpios = <&gpio 155 0>; /* gpio PT3 */
281 power-gpios = <&gpio 31 0>; /* gpio PD7 */
282 bus-width = <4>;
283 };
284
285 sdhci@78000600 {
286 status = "okay";
287 bus-width = <8>;
288 };
289
290 regulators {
291 compatible = "simple-bus";
292 #address-cells = <1>;
293 #size-cells = <0>;
294
295 vdd_ac_bat_reg: regulator@0 {
296 compatible = "regulator-fixed";
297 reg = <0>;
298 regulator-name = "vdd_ac_bat";
299 regulator-min-microvolt = <5000000>;
300 regulator-max-microvolt = <5000000>;
301 regulator-always-on;
302 };
303 };
304
305 sound {
306 compatible = "nvidia,tegra-audio-wm8903-cardhu",
307 "nvidia,tegra-audio-wm8903";
308 nvidia,model = "NVIDIA Tegra Cardhu";
309
310 nvidia,audio-routing =
311 "Headphone Jack", "HPOUTR",
312 "Headphone Jack", "HPOUTL",
313 "Int Spk", "ROP",
314 "Int Spk", "RON",
315 "Int Spk", "LOP",
316 "Int Spk", "LON",
317 "Mic Jack", "MICBIAS",
318 "IN1L", "Mic Jack";
319
320 nvidia,i2s-controller = <&tegra_i2s1>;
321 nvidia,audio-codec = <&wm8903>;
322
323 nvidia,spkr-en-gpios = <&wm8903 2 0>;
324 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
325 };
326};
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-22 03:39:52 -0400