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-rw-r--r--Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm.txt67
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/brg.txt21
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/i2c.txt41
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/pic.txt18
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/usb.txt15
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/cpm_qe/gpio.txt38
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/cpm_qe/network.txt45
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt58
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/firmware.txt24
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/par_io.txt51
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/pincfg.txt60
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/ucc.txt70
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/usb.txt37
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/cpm_qe/serial.txt21
14 files changed, 566 insertions, 0 deletions
diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm.txt
new file mode 100644
index 00000000000..088fc471e03
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm.txt
@@ -0,0 +1,67 @@
1* Freescale Communications Processor Module
2
3NOTE: This is an interim binding, and will likely change slightly,
4as more devices are supported. The QE bindings especially are
5incomplete.
6
7* Root CPM node
8
9Properties:
10- compatible : "fsl,cpm1", "fsl,cpm2", or "fsl,qe".
11- reg : A 48-byte region beginning with CPCR.
12
13Example:
14 cpm@119c0 {
15 #address-cells = <1>;
16 #size-cells = <1>;
17 #interrupt-cells = <2>;
18 compatible = "fsl,mpc8272-cpm", "fsl,cpm2";
19 reg = <119c0 30>;
20 }
21
22* Properties common to mulitple CPM/QE devices
23
24- fsl,cpm-command : This value is ORed with the opcode and command flag
25 to specify the device on which a CPM command operates.
26
27- fsl,cpm-brg : Indicates which baud rate generator the device
28 is associated with. If absent, an unused BRG
29 should be dynamically allocated. If zero, the
30 device uses an external clock rather than a BRG.
31
32- reg : Unless otherwise specified, the first resource represents the
33 scc/fcc/ucc registers, and the second represents the device's
34 parameter RAM region (if it has one).
35
36* Multi-User RAM (MURAM)
37
38The multi-user/dual-ported RAM is expressed as a bus under the CPM node.
39
40Ranges must be set up subject to the following restrictions:
41
42- Children's reg nodes must be offsets from the start of all muram, even
43 if the user-data area does not begin at zero.
44- If multiple range entries are used, the difference between the parent
45 address and the child address must be the same in all, so that a single
46 mapping can cover them all while maintaining the ability to determine
47 CPM-side offsets with pointer subtraction. It is recommended that
48 multiple range entries not be used.
49- A child address of zero must be translatable, even if no reg resources
50 contain it.
51
52A child "data" node must exist, compatible with "fsl,cpm-muram-data", to
53indicate the portion of muram that is usable by the OS for arbitrary
54purposes. The data node may have an arbitrary number of reg resources,
55all of which contribute to the allocatable muram pool.
56
57Example, based on mpc8272:
58 muram@0 {
59 #address-cells = <1>;
60 #size-cells = <1>;
61 ranges = <0 0 10000>;
62
63 data@0 {
64 compatible = "fsl,cpm-muram-data";
65 reg = <0 2000 9800 800>;
66 };
67 };
diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/brg.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/brg.txt
new file mode 100644
index 00000000000..4c7d45eaf02
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/brg.txt
@@ -0,0 +1,21 @@
1* Baud Rate Generators
2
3Currently defined compatibles:
4fsl,cpm-brg
5fsl,cpm1-brg
6fsl,cpm2-brg
7
8Properties:
9- reg : There may be an arbitrary number of reg resources; BRG
10 numbers are assigned to these in order.
11- clock-frequency : Specifies the base frequency driving
12 the BRG.
13
14Example:
15 brg@119f0 {
16 compatible = "fsl,mpc8272-brg",
17 "fsl,cpm2-brg",
18 "fsl,cpm-brg";
19 reg = <119f0 10 115f0 10>;
20 clock-frequency = <d#25000000>;
21 };
diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/i2c.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/i2c.txt
new file mode 100644
index 00000000000..87bc6048667
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/i2c.txt
@@ -0,0 +1,41 @@
1* I2C
2
3The I2C controller is expressed as a bus under the CPM node.
4
5Properties:
6- compatible : "fsl,cpm1-i2c", "fsl,cpm2-i2c"
7- reg : On CPM2 devices, the second resource doesn't specify the I2C
8 Parameter RAM itself, but the I2C_BASE field of the CPM2 Parameter RAM
9 (typically 0x8afc 0x2).
10- #address-cells : Should be one. The cell is the i2c device address with
11 the r/w bit set to zero.
12- #size-cells : Should be zero.
13- clock-frequency : Can be used to set the i2c clock frequency. If
14 unspecified, a default frequency of 60kHz is being used.
15The following two properties are deprecated. They are only used by legacy
16i2c drivers to find the bus to probe:
17- linux,i2c-index : Can be used to hard code an i2c bus number. By default,
18 the bus number is dynamically assigned by the i2c core.
19- linux,i2c-class : Can be used to override the i2c class. The class is used
20 by legacy i2c device drivers to find a bus in a specific context like
21 system management, video or sound. By default, I2C_CLASS_HWMON (1) is
22 being used. The definition of the classes can be found in
23 include/i2c/i2c.h
24
25Example, based on mpc823:
26
27 i2c@860 {
28 compatible = "fsl,mpc823-i2c",
29 "fsl,cpm1-i2c";
30 reg = <0x860 0x20 0x3c80 0x30>;
31 interrupts = <16>;
32 interrupt-parent = <&CPM_PIC>;
33 fsl,cpm-command = <0x10>;
34 #address-cells = <1>;
35 #size-cells = <0>;
36
37 rtc@68 {
38 compatible = "dallas,ds1307";
39 reg = <0x68>;
40 };
41 };
diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/pic.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/pic.txt
new file mode 100644
index 00000000000..8e3ee168161
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/pic.txt
@@ -0,0 +1,18 @@
1* Interrupt Controllers
2
3Currently defined compatibles:
4- fsl,cpm1-pic
5 - only one interrupt cell
6- fsl,pq1-pic
7- fsl,cpm2-pic
8 - second interrupt cell is level/sense:
9 - 2 is falling edge
10 - 8 is active low
11
12Example:
13 interrupt-controller@10c00 {
14 #interrupt-cells = <2>;
15 interrupt-controller;
16 reg = <10c00 80>;
17 compatible = "mpc8272-pic", "fsl,cpm2-pic";
18 };
diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/usb.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/usb.txt
new file mode 100644
index 00000000000..74bfda4bb82
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/usb.txt
@@ -0,0 +1,15 @@
1* USB (Universal Serial Bus Controller)
2
3Properties:
4- compatible : "fsl,cpm1-usb", "fsl,cpm2-usb", "fsl,qe-usb"
5
6Example:
7 usb@11bc0 {
8 #address-cells = <1>;
9 #size-cells = <0>;
10 compatible = "fsl,cpm2-usb";
11 reg = <11b60 18 8b00 100>;
12 interrupts = <b 8>;
13 interrupt-parent = <&PIC>;
14 fsl,cpm-command = <2e600000>;
15 };
diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/gpio.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/gpio.txt
new file mode 100644
index 00000000000..1815dfede1b
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/gpio.txt
@@ -0,0 +1,38 @@
1Every GPIO controller node must have #gpio-cells property defined,
2this information will be used to translate gpio-specifiers.
3
4On CPM1 devices, all ports are using slightly different register layouts.
5Ports A, C and D are 16bit ports and Ports B and E are 32bit ports.
6
7On CPM2 devices, all ports are 32bit ports and use a common register layout.
8
9Required properties:
10- compatible : "fsl,cpm1-pario-bank-a", "fsl,cpm1-pario-bank-b",
11 "fsl,cpm1-pario-bank-c", "fsl,cpm1-pario-bank-d",
12 "fsl,cpm1-pario-bank-e", "fsl,cpm2-pario-bank"
13- #gpio-cells : Should be two. The first cell is the pin number and the
14 second cell is used to specify optional paramters (currently unused).
15- gpio-controller : Marks the port as GPIO controller.
16
17Example of three SOC GPIO banks defined as gpio-controller nodes:
18
19 CPM1_PIO_A: gpio-controller@950 {
20 #gpio-cells = <2>;
21 compatible = "fsl,cpm1-pario-bank-a";
22 reg = <0x950 0x10>;
23 gpio-controller;
24 };
25
26 CPM1_PIO_B: gpio-controller@ab8 {
27 #gpio-cells = <2>;
28 compatible = "fsl,cpm1-pario-bank-b";
29 reg = <0xab8 0x10>;
30 gpio-controller;
31 };
32
33 CPM1_PIO_E: gpio-controller@ac8 {
34 #gpio-cells = <2>;
35 compatible = "fsl,cpm1-pario-bank-e";
36 reg = <0xac8 0x18>;
37 gpio-controller;
38 };
diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/network.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/network.txt
new file mode 100644
index 00000000000..0e426944658
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/network.txt
@@ -0,0 +1,45 @@
1* Network
2
3Currently defined compatibles:
4- fsl,cpm1-scc-enet
5- fsl,cpm2-scc-enet
6- fsl,cpm1-fec-enet
7- fsl,cpm2-fcc-enet (third resource is GFEMR)
8- fsl,qe-enet
9
10Example:
11
12 ethernet@11300 {
13 device_type = "network";
14 compatible = "fsl,mpc8272-fcc-enet",
15 "fsl,cpm2-fcc-enet";
16 reg = <11300 20 8400 100 11390 1>;
17 local-mac-address = [ 00 00 00 00 00 00 ];
18 interrupts = <20 8>;
19 interrupt-parent = <&PIC>;
20 phy-handle = <&PHY0>;
21 fsl,cpm-command = <12000300>;
22 };
23
24* MDIO
25
26Currently defined compatibles:
27fsl,pq1-fec-mdio (reg is same as first resource of FEC device)
28fsl,cpm2-mdio-bitbang (reg is port C registers)
29
30Properties for fsl,cpm2-mdio-bitbang:
31fsl,mdio-pin : pin of port C controlling mdio data
32fsl,mdc-pin : pin of port C controlling mdio clock
33
34Example:
35 mdio@10d40 {
36 device_type = "mdio";
37 compatible = "fsl,mpc8272ads-mdio-bitbang",
38 "fsl,mpc8272-mdio-bitbang",
39 "fsl,cpm2-mdio-bitbang";
40 reg = <10d40 14>;
41 #address-cells = <1>;
42 #size-cells = <0>;
43 fsl,mdio-pin = <12>;
44 fsl,mdc-pin = <13>;
45 };
diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt
new file mode 100644
index 00000000000..78790d58dc2
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt
@@ -0,0 +1,58 @@
1* Freescale QUICC Engine module (QE)
2This represents qe module that is installed on PowerQUICC II Pro.
3
4NOTE: This is an interim binding; it should be updated to fit
5in with the CPM binding later in this document.
6
7Basically, it is a bus of devices, that could act more or less
8as a complete entity (UCC, USB etc ). All of them should be siblings on
9the "root" qe node, using the common properties from there.
10The description below applies to the qe of MPC8360 and
11more nodes and properties would be extended in the future.
12
13i) Root QE device
14
15Required properties:
16- compatible : should be "fsl,qe";
17- model : precise model of the QE, Can be "QE", "CPM", or "CPM2"
18- reg : offset and length of the device registers.
19- bus-frequency : the clock frequency for QUICC Engine.
20
21Recommended properties
22- brg-frequency : the internal clock source frequency for baud-rate
23 generators in Hz.
24
25Example:
26 qe@e0100000 {
27 #address-cells = <1>;
28 #size-cells = <1>;
29 #interrupt-cells = <2>;
30 compatible = "fsl,qe";
31 ranges = <0 e0100000 00100000>;
32 reg = <e0100000 480>;
33 brg-frequency = <0>;
34 bus-frequency = <179A7B00>;
35 }
36
37* Multi-User RAM (MURAM)
38
39Required properties:
40- compatible : should be "fsl,qe-muram", "fsl,cpm-muram".
41- mode : the could be "host" or "slave".
42- ranges : Should be defined as specified in 1) to describe the
43 translation of MURAM addresses.
44- data-only : sub-node which defines the address area under MURAM
45 bus that can be allocated as data/parameter
46
47Example:
48
49 muram@10000 {
50 compatible = "fsl,qe-muram", "fsl,cpm-muram";
51 ranges = <0 00010000 0000c000>;
52
53 data-only@0{
54 compatible = "fsl,qe-muram-data",
55 "fsl,cpm-muram-data";
56 reg = <0 c000>;
57 };
58 };
diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/firmware.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/firmware.txt
new file mode 100644
index 00000000000..6c238f59b2a
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/firmware.txt
@@ -0,0 +1,24 @@
1* Uploaded QE firmware
2
3 If a new firwmare has been uploaded to the QE (usually by the
4 boot loader), then a 'firmware' child node should be added to the QE
5 node. This node provides information on the uploaded firmware that
6 device drivers may need.
7
8 Required properties:
9 - id: The string name of the firmware. This is taken from the 'id'
10 member of the qe_firmware structure of the uploaded firmware.
11 Device drivers can search this string to determine if the
12 firmware they want is already present.
13 - extended-modes: The Extended Modes bitfield, taken from the
14 firmware binary. It is a 64-bit number represented
15 as an array of two 32-bit numbers.
16 - virtual-traps: The virtual traps, taken from the firmware binary.
17 It is an array of 8 32-bit numbers.
18
19Example:
20 firmware {
21 id = "Soft-UART";
22 extended-modes = <0 0>;
23 virtual-traps = <0 0 0 0 0 0 0 0>;
24 };
diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/par_io.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/par_io.txt
new file mode 100644
index 00000000000..60984260207
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/par_io.txt
@@ -0,0 +1,51 @@
1* Parallel I/O Ports
2
3This node configures Parallel I/O ports for CPUs with QE support.
4The node should reside in the "soc" node of the tree. For each
5device that using parallel I/O ports, a child node should be created.
6See the definition of the Pin configuration nodes below for more
7information.
8
9Required properties:
10- device_type : should be "par_io".
11- reg : offset to the register set and its length.
12- num-ports : number of Parallel I/O ports
13
14Example:
15par_io@1400 {
16 reg = <1400 100>;
17 #address-cells = <1>;
18 #size-cells = <0>;
19 device_type = "par_io";
20 num-ports = <7>;
21 ucc_pin@01 {
22 ......
23 };
24
25Note that "par_io" nodes are obsolete, and should not be used for
26the new device trees. Instead, each Par I/O bank should be represented
27via its own gpio-controller node:
28
29Required properties:
30- #gpio-cells : should be "2".
31- compatible : should be "fsl,<chip>-qe-pario-bank",
32 "fsl,mpc8323-qe-pario-bank".
33- reg : offset to the register set and its length.
34- gpio-controller : node to identify gpio controllers.
35
36Example:
37 qe_pio_a: gpio-controller@1400 {
38 #gpio-cells = <2>;
39 compatible = "fsl,mpc8360-qe-pario-bank",
40 "fsl,mpc8323-qe-pario-bank";
41 reg = <0x1400 0x18>;
42 gpio-controller;
43 };
44
45 qe_pio_e: gpio-controller@1460 {
46 #gpio-cells = <2>;
47 compatible = "fsl,mpc8360-qe-pario-bank",
48 "fsl,mpc8323-qe-pario-bank";
49 reg = <0x1460 0x18>;
50 gpio-controller;
51 };
diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/pincfg.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/pincfg.txt
new file mode 100644
index 00000000000..c5b43061db3
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/pincfg.txt
@@ -0,0 +1,60 @@
1* Pin configuration nodes
2
3Required properties:
4- linux,phandle : phandle of this node; likely referenced by a QE
5 device.
6- pio-map : array of pin configurations. Each pin is defined by 6
7 integers. The six numbers are respectively: port, pin, dir,
8 open_drain, assignment, has_irq.
9 - port : port number of the pin; 0-6 represent port A-G in UM.
10 - pin : pin number in the port.
11 - dir : direction of the pin, should encode as follows:
12
13 0 = The pin is disabled
14 1 = The pin is an output
15 2 = The pin is an input
16 3 = The pin is I/O
17
18 - open_drain : indicates the pin is normal or wired-OR:
19
20 0 = The pin is actively driven as an output
21 1 = The pin is an open-drain driver. As an output, the pin is
22 driven active-low, otherwise it is three-stated.
23
24 - assignment : function number of the pin according to the Pin Assignment
25 tables in User Manual. Each pin can have up to 4 possible functions in
26 QE and two options for CPM.
27 - has_irq : indicates if the pin is used as source of external
28 interrupts.
29
30Example:
31 ucc_pin@01 {
32 linux,phandle = <140001>;
33 pio-map = <
34 /* port pin dir open_drain assignment has_irq */
35 0 3 1 0 1 0 /* TxD0 */
36 0 4 1 0 1 0 /* TxD1 */
37 0 5 1 0 1 0 /* TxD2 */
38 0 6 1 0 1 0 /* TxD3 */
39 1 6 1 0 3 0 /* TxD4 */
40 1 7 1 0 1 0 /* TxD5 */
41 1 9 1 0 2 0 /* TxD6 */
42 1 a 1 0 2 0 /* TxD7 */
43 0 9 2 0 1 0 /* RxD0 */
44 0 a 2 0 1 0 /* RxD1 */
45 0 b 2 0 1 0 /* RxD2 */
46 0 c 2 0 1 0 /* RxD3 */
47 0 d 2 0 1 0 /* RxD4 */
48 1 1 2 0 2 0 /* RxD5 */
49 1 0 2 0 2 0 /* RxD6 */
50 1 4 2 0 2 0 /* RxD7 */
51 0 7 1 0 1 0 /* TX_EN */
52 0 8 1 0 1 0 /* TX_ER */
53 0 f 2 0 1 0 /* RX_DV */
54 0 10 2 0 1 0 /* RX_ER */
55 0 0 2 0 1 0 /* RX_CLK */
56 2 9 1 0 3 0 /* GTX_CLK - CLK10 */
57 2 8 2 0 1 0>; /* GTX125 - CLK9 */
58 };
59
60
diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/ucc.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/ucc.txt
new file mode 100644
index 00000000000..e47734bee3f
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/ucc.txt
@@ -0,0 +1,70 @@
1* UCC (Unified Communications Controllers)
2
3Required properties:
4- device_type : should be "network", "hldc", "uart", "transparent"
5 "bisync", "atm", or "serial".
6- compatible : could be "ucc_geth" or "fsl_atm" and so on.
7- cell-index : the ucc number(1-8), corresponding to UCCx in UM.
8- reg : Offset and length of the register set for the device
9- interrupts : <a b> where a is the interrupt number and b is a
10 field that represents an encoding of the sense and level
11 information for the interrupt. This should be encoded based on
12 the information in section 2) depending on the type of interrupt
13 controller you have.
14- interrupt-parent : the phandle for the interrupt controller that
15 services interrupts for this device.
16- pio-handle : The phandle for the Parallel I/O port configuration.
17- port-number : for UART drivers, the port number to use, between 0 and 3.
18 This usually corresponds to the /dev/ttyQE device, e.g. <0> = /dev/ttyQE0.
19 The port number is added to the minor number of the device. Unlike the
20 CPM UART driver, the port-number is required for the QE UART driver.
21- soft-uart : for UART drivers, if specified this means the QE UART device
22 driver should use "Soft-UART" mode, which is needed on some SOCs that have
23 broken UART hardware. Soft-UART is provided via a microcode upload.
24- rx-clock-name: the UCC receive clock source
25 "none": clock source is disabled
26 "brg1" through "brg16": clock source is BRG1-BRG16, respectively
27 "clk1" through "clk24": clock source is CLK1-CLK24, respectively
28- tx-clock-name: the UCC transmit clock source
29 "none": clock source is disabled
30 "brg1" through "brg16": clock source is BRG1-BRG16, respectively
31 "clk1" through "clk24": clock source is CLK1-CLK24, respectively
32The following two properties are deprecated. rx-clock has been replaced
33with rx-clock-name, and tx-clock has been replaced with tx-clock-name.
34Drivers that currently use the deprecated properties should continue to
35do so, in order to support older device trees, but they should be updated
36to check for the new properties first.
37- rx-clock : represents the UCC receive clock source.
38 0x00 : clock source is disabled;
39 0x1~0x10 : clock source is BRG1~BRG16 respectively;
40 0x11~0x28: clock source is QE_CLK1~QE_CLK24 respectively.
41- tx-clock: represents the UCC transmit clock source;
42 0x00 : clock source is disabled;
43 0x1~0x10 : clock source is BRG1~BRG16 respectively;
44 0x11~0x28: clock source is QE_CLK1~QE_CLK24 respectively.
45
46Required properties for network device_type:
47- mac-address : list of bytes representing the ethernet address.
48- phy-handle : The phandle for the PHY connected to this controller.
49
50Recommended properties:
51- phy-connection-type : a string naming the controller/PHY interface type,
52 i.e., "mii" (default), "rmii", "gmii", "rgmii", "rgmii-id" (Internal
53 Delay), "rgmii-txid" (delay on TX only), "rgmii-rxid" (delay on RX only),
54 "tbi", or "rtbi".
55
56Example:
57 ucc@2000 {
58 device_type = "network";
59 compatible = "ucc_geth";
60 cell-index = <1>;
61 reg = <2000 200>;
62 interrupts = <a0 0>;
63 interrupt-parent = <700>;
64 mac-address = [ 00 04 9f 00 23 23 ];
65 rx-clock = "none";
66 tx-clock = "clk9";
67 phy-handle = <212000>;
68 phy-connection-type = "gmii";
69 pio-handle = <140001>;
70 };
diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/usb.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/usb.txt
new file mode 100644
index 00000000000..9ccd5f30405
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/usb.txt
@@ -0,0 +1,37 @@
1Freescale QUICC Engine USB Controller
2
3Required properties:
4- compatible : should be "fsl,<chip>-qe-usb", "fsl,mpc8323-qe-usb".
5- reg : the first two cells should contain usb registers location and
6 length, the next two two cells should contain PRAM location and
7 length.
8- interrupts : should contain USB interrupt.
9- interrupt-parent : interrupt source phandle.
10- fsl,fullspeed-clock : specifies the full speed USB clock source:
11 "none": clock source is disabled
12 "brg1" through "brg16": clock source is BRG1-BRG16, respectively
13 "clk1" through "clk24": clock source is CLK1-CLK24, respectively
14- fsl,lowspeed-clock : specifies the low speed USB clock source:
15 "none": clock source is disabled
16 "brg1" through "brg16": clock source is BRG1-BRG16, respectively
17 "clk1" through "clk24": clock source is CLK1-CLK24, respectively
18- hub-power-budget : USB power budget for the root hub, in mA.
19- gpios : should specify GPIOs in this order: USBOE, USBTP, USBTN, USBRP,
20 USBRN, SPEED (optional), and POWER (optional).
21
22Example:
23
24usb@6c0 {
25 compatible = "fsl,mpc8360-qe-usb", "fsl,mpc8323-qe-usb";
26 reg = <0x6c0 0x40 0x8b00 0x100>;
27 interrupts = <11>;
28 interrupt-parent = <&qeic>;
29 fsl,fullspeed-clock = "clk21";
30 gpios = <&qe_pio_b 2 0 /* USBOE */
31 &qe_pio_b 3 0 /* USBTP */
32 &qe_pio_b 8 0 /* USBTN */
33 &qe_pio_b 9 0 /* USBRP */
34 &qe_pio_b 11 0 /* USBRN */
35 &qe_pio_e 20 0 /* SPEED */
36 &qe_pio_e 21 0 /* POWER */>;
37};
diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/serial.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/serial.txt
new file mode 100644
index 00000000000..b35f3482e3e
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/serial.txt
@@ -0,0 +1,21 @@
1* Serial
2
3Currently defined compatibles:
4- fsl,cpm1-smc-uart
5- fsl,cpm2-smc-uart
6- fsl,cpm1-scc-uart
7- fsl,cpm2-scc-uart
8- fsl,qe-uart
9
10Example:
11
12 serial@11a00 {
13 device_type = "serial";
14 compatible = "fsl,mpc8272-scc-uart",
15 "fsl,cpm2-scc-uart";
16 reg = <11a00 20 8000 100>;
17 interrupts = <28 8>;
18 interrupt-parent = <&PIC>;
19 fsl,cpm-brg = <1>;
20 fsl,cpm-command = <00800000>;
21 };
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-19 17:38:27 -0400