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diff --git a/Documentation/devicetree/bindings/i2c/arm-versatile.txt b/Documentation/devicetree/bindings/i2c/arm-versatile.txt
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index 00000000000..361d31c51b6
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+++ b/Documentation/devicetree/bindings/i2c/arm-versatile.txt
@@ -0,0 +1,10 @@
+i2c Controller on ARM Versatile platform:
+
+Required properties:
+- compatible : Must be "arm,versatile-i2c";
+- reg
+- #address-cells = <1>;
+- #size-cells = <0>;
+
+Optional properties:
+- Child nodes conforming to i2c bus binding
diff --git a/Documentation/devicetree/bindings/i2c/ce4100-i2c.txt b/Documentation/devicetree/bindings/i2c/ce4100-i2c.txt
new file mode 100644
index 00000000000..569b1624851
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+++ b/Documentation/devicetree/bindings/i2c/ce4100-i2c.txt
@@ -0,0 +1,93 @@
+CE4100 I2C
+----------
+
+CE4100 has one PCI device which is described as the I2C-Controller. This
+PCI device has three PCI-bars, each bar contains a complete I2C
+controller. So we have a total of three independent I2C-Controllers
+which share only an interrupt line.
+The driver is probed via the PCI-ID and is gathering the information of
+attached devices from the devices tree.
+Grant Likely recommended to use the ranges property to map the PCI-Bar
+number to its physical address and to use this to find the child nodes
+of the specific I2C controller. This were his exact words:
+
+       Here's where the magic happens.  Each entry in
+       ranges describes how the parent pci address space
+       (middle group of 3) is translated to the local
+       address space (first group of 2) and the size of
+       each range (last cell).  In this particular case,
+       the first cell of the local address is chosen to be
+       1:1 mapped to the BARs, and the second is the
+       offset from be base of the BAR (which would be
+       non-zero if you had 2 or more devices mapped off
+       the same BAR)
+
+       ranges allows the address mapping to be described
+       in a way that the OS can interpret without
+       requiring custom device driver code.
+
+This is an example which is used on FalconFalls:
+------------------------------------------------
+        i2c-controller@b,2 {
+                #address-cells = <2>;
+                #size-cells = <1>;
+                compatible = "pci8086,2e68.2",
+                                "pci8086,2e68",
+                                "pciclass,ff0000",
+                                "pciclass,ff00";
+
+                reg = <0x15a00 0x0 0x0 0x0 0x0>;
+                interrupts = <16 1>;
+
+                /* as described by Grant, the first number in the group of
+                * three is the bar number followed by the 64bit bar address
+                * followed by size of the mapping. The bar address
+                * requires also a valid translation in parents ranges
+                * property.
+                */
+                ranges = <0 0   0x02000000 0 0xdffe0500 0x100
+                          1 0   0x02000000 0 0xdffe0600 0x100
+                          2 0   0x02000000 0 0xdffe0700 0x100>;
+
+                i2c@0 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "intel,ce4100-i2c-controller";
+
+                        /* The first number in the reg property is the
+                        * number of the bar
+                        */
+                        reg = <0 0 0x100>;
+
+                        /* This I2C controller has no devices */
+                };
+
+                i2c@1 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "intel,ce4100-i2c-controller";
+                        reg = <1 0 0x100>;
+
+                        /* This I2C controller has one gpio controller */
+                        gpio@26 {
+                                #gpio-cells = <2>;
+                                compatible = "ti,pcf8575";
+                                reg = <0x26>;
+                                gpio-controller;
+                        };
+                };
+
+                i2c@2 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "intel,ce4100-i2c-controller";
+                        reg = <2 0 0x100>;
+
+                        gpio@26 {
+                                #gpio-cells = <2>;
+                                compatible = "ti,pcf8575";
+                                reg = <0x26>;
+                                gpio-controller;
+                        };
+                };
+        };
diff --git a/Documentation/devicetree/bindings/i2c/fsl-i2c.txt b/Documentation/devicetree/bindings/i2c/fsl-i2c.txt
new file mode 100644
index 00000000000..1eacd6b20ed
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+++ b/Documentation/devicetree/bindings/i2c/fsl-i2c.txt
@@ -0,0 +1,64 @@
+* I2C
+
+Required properties :
+
+ - reg : Offset and length of the register set for the device
+ - compatible : should be "fsl,CHIP-i2c" where CHIP is the name of a
+   compatible processor, e.g. mpc8313, mpc8543, mpc8544, mpc5121,
+   mpc5200 or mpc5200b. For the mpc5121, an additional node
+   "fsl,mpc5121-i2c-ctrl" is required as shown in the example below.
+
+Recommended properties :
+
+ - interrupts : <a b> where a is the interrupt number and b is a
+   field that represents an encoding of the sense and level
+   information for the interrupt.  This should be encoded based on
+   the information in section 2) depending on the type of interrupt
+   controller you have.
+ - interrupt-parent : the phandle for the interrupt controller that
+   services interrupts for this device.
+ - fsl,preserve-clocking : boolean; if defined, the clock settings
+   from the bootloader are preserved (not touched).
+ - clock-frequency : desired I2C bus clock frequency in Hz.
+ - fsl,timeout : I2C bus timeout in microseconds.
+
+Examples :
+
+        /* MPC5121 based board */
+        i2c@1740 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "fsl,mpc5121-i2c", "fsl-i2c";
+                reg = <0x1740 0x20>;
+                interrupts = <11 0x8>;
+                interrupt-parent = <&ipic>;
+                clock-frequency = <100000>;
+        };
+
+        i2ccontrol@1760 {
+                compatible = "fsl,mpc5121-i2c-ctrl";
+                reg = <0x1760 0x8>;
+        };
+
+        /* MPC5200B based board */
+        i2c@3d00 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
+                reg = <0x3d00 0x40>;
+                interrupts = <2 15 0>;
+                interrupt-parent = <&mpc5200_pic>;
+                fsl,preserve-clocking;
+        };
+
+        /* MPC8544 base board */
+        i2c@3100 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "fsl,mpc8544-i2c", "fsl-i2c";
+                reg = <0x3100 0x100>;
+                interrupts = <43 2>;
+                interrupt-parent = <&mpic>;
+                clock-frequency = <400000>;
+                fsl,timeout = <10000>;
+        };