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-rw-r--r--Documentation/devicetree/bindings/arm/gic.txt4
1 files changed, 4 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/gic.txt b/Documentation/devicetree/bindings/arm/gic.txt
index 52916b4aa1f..9b4b82a721b 100644
--- a/Documentation/devicetree/bindings/arm/gic.txt
+++ b/Documentation/devicetree/bindings/arm/gic.txt
@@ -42,6 +42,10 @@ Optional
42- interrupts : Interrupt source of the parent interrupt controller. Only 42- interrupts : Interrupt source of the parent interrupt controller. Only
43 present on secondary GICs. 43 present on secondary GICs.
44 44
45- cpu-offset : per-cpu offset within the distributor and cpu interface
46 regions, used when the GIC doesn't have banked registers. The offset is
47 cpu-offset * cpu-nr.
48
45Example: 49Example:
46 50
47 intc: interrupt-controller@fff11000 { 51 intc: interrupt-controller@fff11000 {