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-rw-r--r--arch/arm/mach-omap1/clock.c77
-rw-r--r--arch/arm/mach-omap1/clock.h63
-rw-r--r--arch/arm/plat-omap/include/mach/clock.h1
3 files changed, 53 insertions, 88 deletions
diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c
index 7c455431790..1e477af666e 100644
--- a/arch/arm/mach-omap1/clock.c
+++ b/arch/arm/mach-omap1/clock.c
@@ -163,7 +163,7 @@ static void omap1_watchdog_recalc(struct clk * clk)
163 163
164static void omap1_uart_recalc(struct clk * clk) 164static void omap1_uart_recalc(struct clk * clk)
165{ 165{
166 unsigned int val = omap_readl(clk->enable_reg); 166 unsigned int val = __raw_readl(clk->enable_reg);
167 if (val & clk->enable_bit) 167 if (val & clk->enable_bit)
168 clk->rate = 48000000; 168 clk->rate = 48000000;
169 else 169 else
@@ -517,14 +517,14 @@ static int omap1_set_uart_rate(struct clk * clk, unsigned long rate)
517{ 517{
518 unsigned int val; 518 unsigned int val;
519 519
520 val = omap_readl(clk->enable_reg); 520 val = __raw_readl(clk->enable_reg);
521 if (rate == 12000000) 521 if (rate == 12000000)
522 val &= ~(1 << clk->enable_bit); 522 val &= ~(1 << clk->enable_bit);
523 else if (rate == 48000000) 523 else if (rate == 48000000)
524 val |= (1 << clk->enable_bit); 524 val |= (1 << clk->enable_bit);
525 else 525 else
526 return -EINVAL; 526 return -EINVAL;
527 omap_writel(val, clk->enable_reg); 527 __raw_writel(val, clk->enable_reg);
528 clk->rate = rate; 528 clk->rate = rate;
529 529
530 return 0; 530 return 0;
@@ -543,8 +543,8 @@ static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate)
543 else 543 else
544 ratio_bits = (dsor - 2) << 2; 544 ratio_bits = (dsor - 2) << 2;
545 545
546 ratio_bits |= omap_readw(clk->enable_reg) & ~0xfd; 546 ratio_bits |= __raw_readw(clk->enable_reg) & ~0xfd;
547 omap_writew(ratio_bits, clk->enable_reg); 547 __raw_writew(ratio_bits, clk->enable_reg);
548 548
549 return 0; 549 return 0;
550} 550}
@@ -583,8 +583,8 @@ static void omap1_init_ext_clk(struct clk * clk)
583 __u16 ratio_bits; 583 __u16 ratio_bits;
584 584
585 /* Determine current rate and ensure clock is based on 96MHz APLL */ 585 /* Determine current rate and ensure clock is based on 96MHz APLL */
586 ratio_bits = omap_readw(clk->enable_reg) & ~1; 586 ratio_bits = __raw_readw(clk->enable_reg) & ~1;
587 omap_writew(ratio_bits, clk->enable_reg); 587 __raw_writew(ratio_bits, clk->enable_reg);
588 588
589 ratio_bits = (ratio_bits & 0xfc) >> 2; 589 ratio_bits = (ratio_bits & 0xfc) >> 2;
590 if (ratio_bits > 6) 590 if (ratio_bits > 6)
@@ -646,25 +646,13 @@ static int omap1_clk_enable_generic(struct clk *clk)
646 } 646 }
647 647
648 if (clk->flags & ENABLE_REG_32BIT) { 648 if (clk->flags & ENABLE_REG_32BIT) {
649 if (clk->flags & VIRTUAL_IO_ADDRESS) { 649 regval32 = __raw_readl(clk->enable_reg);
650 regval32 = __raw_readl(clk->enable_reg); 650 regval32 |= (1 << clk->enable_bit);
651 regval32 |= (1 << clk->enable_bit); 651 __raw_writel(regval32, clk->enable_reg);
652 __raw_writel(regval32, clk->enable_reg);
653 } else {
654 regval32 = omap_readl(clk->enable_reg);
655 regval32 |= (1 << clk->enable_bit);
656 omap_writel(regval32, clk->enable_reg);
657 }
658 } else { 652 } else {
659 if (clk->flags & VIRTUAL_IO_ADDRESS) { 653 regval16 = __raw_readw(clk->enable_reg);
660 regval16 = __raw_readw(clk->enable_reg); 654 regval16 |= (1 << clk->enable_bit);
661 regval16 |= (1 << clk->enable_bit); 655 __raw_writew(regval16, clk->enable_reg);
662 __raw_writew(regval16, clk->enable_reg);
663 } else {
664 regval16 = omap_readw(clk->enable_reg);
665 regval16 |= (1 << clk->enable_bit);
666 omap_writew(regval16, clk->enable_reg);
667 }
668 } 656 }
669 657
670 return 0; 658 return 0;
@@ -679,25 +667,13 @@ static void omap1_clk_disable_generic(struct clk *clk)
679 return; 667 return;
680 668
681 if (clk->flags & ENABLE_REG_32BIT) { 669 if (clk->flags & ENABLE_REG_32BIT) {
682 if (clk->flags & VIRTUAL_IO_ADDRESS) { 670 regval32 = __raw_readl(clk->enable_reg);
683 regval32 = __raw_readl(clk->enable_reg); 671 regval32 &= ~(1 << clk->enable_bit);
684 regval32 &= ~(1 << clk->enable_bit); 672 __raw_writel(regval32, clk->enable_reg);
685 __raw_writel(regval32, clk->enable_reg);
686 } else {
687 regval32 = omap_readl(clk->enable_reg);
688 regval32 &= ~(1 << clk->enable_bit);
689 omap_writel(regval32, clk->enable_reg);
690 }
691 } else { 673 } else {
692 if (clk->flags & VIRTUAL_IO_ADDRESS) { 674 regval16 = __raw_readw(clk->enable_reg);
693 regval16 = __raw_readw(clk->enable_reg); 675 regval16 &= ~(1 << clk->enable_bit);
694 regval16 &= ~(1 << clk->enable_bit); 676 __raw_writew(regval16, clk->enable_reg);
695 __raw_writew(regval16, clk->enable_reg);
696 } else {
697 regval16 = omap_readw(clk->enable_reg);
698 regval16 &= ~(1 << clk->enable_bit);
699 omap_writew(regval16, clk->enable_reg);
700 }
701 } 677 }
702} 678}
703 679
@@ -745,17 +721,10 @@ static void __init omap1_clk_disable_unused(struct clk *clk)
745 } 721 }
746 722
747 /* Is the clock already disabled? */ 723 /* Is the clock already disabled? */
748 if (clk->flags & ENABLE_REG_32BIT) { 724 if (clk->flags & ENABLE_REG_32BIT)
749 if (clk->flags & VIRTUAL_IO_ADDRESS) 725 regval32 = __raw_readl(clk->enable_reg);
750 regval32 = __raw_readl(clk->enable_reg); 726 else
751 else 727 regval32 = __raw_readw(clk->enable_reg);
752 regval32 = omap_readl(clk->enable_reg);
753 } else {
754 if (clk->flags & VIRTUAL_IO_ADDRESS)
755 regval32 = __raw_readw(clk->enable_reg);
756 else
757 regval32 = omap_readw(clk->enable_reg);
758 }
759 728
760 if ((regval32 & (1 << clk->enable_bit)) == 0) 729 if ((regval32 & (1 << clk->enable_bit)) == 0)
761 return; 730 return;
diff --git a/arch/arm/mach-omap1/clock.h b/arch/arm/mach-omap1/clock.h
index ed343af5f12..1b4dd056d9b 100644
--- a/arch/arm/mach-omap1/clock.h
+++ b/arch/arm/mach-omap1/clock.h
@@ -165,7 +165,7 @@ static struct arm_idlect1_clk ck_dpll1out = {
165 .parent = &ck_dpll1, 165 .parent = &ck_dpll1,
166 .flags = CLOCK_IDLE_CONTROL | 166 .flags = CLOCK_IDLE_CONTROL |
167 ENABLE_REG_32BIT | RATE_PROPAGATES, 167 ENABLE_REG_32BIT | RATE_PROPAGATES,
168 .enable_reg = (void __iomem *)ARM_IDLECT2, 168 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
169 .enable_bit = EN_CKOUT_ARM, 169 .enable_bit = EN_CKOUT_ARM,
170 .recalc = &followparent_recalc, 170 .recalc = &followparent_recalc,
171 }, 171 },
@@ -177,7 +177,7 @@ static struct clk sossi_ck = {
177 .ops = &clkops_generic, 177 .ops = &clkops_generic,
178 .parent = &ck_dpll1out.clk, 178 .parent = &ck_dpll1out.clk,
179 .flags = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT, 179 .flags = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT,
180 .enable_reg = (void __iomem *)MOD_CONF_CTRL_1, 180 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1),
181 .enable_bit = 16, 181 .enable_bit = 16,
182 .recalc = &omap1_sossi_recalc, 182 .recalc = &omap1_sossi_recalc,
183 .set_rate = &omap1_set_sossi_rate, 183 .set_rate = &omap1_set_sossi_rate,
@@ -200,7 +200,7 @@ static struct arm_idlect1_clk armper_ck = {
200 .ops = &clkops_generic, 200 .ops = &clkops_generic,
201 .parent = &ck_dpll1, 201 .parent = &ck_dpll1,
202 .flags = CLOCK_IDLE_CONTROL, 202 .flags = CLOCK_IDLE_CONTROL,
203 .enable_reg = (void __iomem *)ARM_IDLECT2, 203 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
204 .enable_bit = EN_PERCK, 204 .enable_bit = EN_PERCK,
205 .rate_offset = CKCTL_PERDIV_OFFSET, 205 .rate_offset = CKCTL_PERDIV_OFFSET,
206 .recalc = &omap1_ckctl_recalc, 206 .recalc = &omap1_ckctl_recalc,
@@ -214,7 +214,7 @@ static struct clk arm_gpio_ck = {
214 .name = "arm_gpio_ck", 214 .name = "arm_gpio_ck",
215 .ops = &clkops_generic, 215 .ops = &clkops_generic,
216 .parent = &ck_dpll1, 216 .parent = &ck_dpll1,
217 .enable_reg = (void __iomem *)ARM_IDLECT2, 217 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
218 .enable_bit = EN_GPIOCK, 218 .enable_bit = EN_GPIOCK,
219 .recalc = &followparent_recalc, 219 .recalc = &followparent_recalc,
220}; 220};
@@ -225,7 +225,7 @@ static struct arm_idlect1_clk armxor_ck = {
225 .ops = &clkops_generic, 225 .ops = &clkops_generic,
226 .parent = &ck_ref, 226 .parent = &ck_ref,
227 .flags = CLOCK_IDLE_CONTROL, 227 .flags = CLOCK_IDLE_CONTROL,
228 .enable_reg = (void __iomem *)ARM_IDLECT2, 228 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
229 .enable_bit = EN_XORPCK, 229 .enable_bit = EN_XORPCK,
230 .recalc = &followparent_recalc, 230 .recalc = &followparent_recalc,
231 }, 231 },
@@ -238,7 +238,7 @@ static struct arm_idlect1_clk armtim_ck = {
238 .ops = &clkops_generic, 238 .ops = &clkops_generic,
239 .parent = &ck_ref, 239 .parent = &ck_ref,
240 .flags = CLOCK_IDLE_CONTROL, 240 .flags = CLOCK_IDLE_CONTROL,
241 .enable_reg = (void __iomem *)ARM_IDLECT2, 241 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
242 .enable_bit = EN_TIMCK, 242 .enable_bit = EN_TIMCK,
243 .recalc = &followparent_recalc, 243 .recalc = &followparent_recalc,
244 }, 244 },
@@ -251,7 +251,7 @@ static struct arm_idlect1_clk armwdt_ck = {
251 .ops = &clkops_generic, 251 .ops = &clkops_generic,
252 .parent = &ck_ref, 252 .parent = &ck_ref,
253 .flags = CLOCK_IDLE_CONTROL, 253 .flags = CLOCK_IDLE_CONTROL,
254 .enable_reg = (void __iomem *)ARM_IDLECT2, 254 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
255 .enable_bit = EN_WDTCK, 255 .enable_bit = EN_WDTCK,
256 .recalc = &omap1_watchdog_recalc, 256 .recalc = &omap1_watchdog_recalc,
257 }, 257 },
@@ -274,7 +274,7 @@ static struct clk dsp_ck = {
274 .name = "dsp_ck", 274 .name = "dsp_ck",
275 .ops = &clkops_generic, 275 .ops = &clkops_generic,
276 .parent = &ck_dpll1, 276 .parent = &ck_dpll1,
277 .enable_reg = (void __iomem *)ARM_CKCTL, 277 .enable_reg = OMAP1_IO_ADDRESS(ARM_CKCTL),
278 .enable_bit = EN_DSPCK, 278 .enable_bit = EN_DSPCK,
279 .rate_offset = CKCTL_DSPDIV_OFFSET, 279 .rate_offset = CKCTL_DSPDIV_OFFSET,
280 .recalc = &omap1_ckctl_recalc, 280 .recalc = &omap1_ckctl_recalc,
@@ -296,7 +296,6 @@ static struct clk dspper_ck = {
296 .name = "dspper_ck", 296 .name = "dspper_ck",
297 .ops = &clkops_dspck, 297 .ops = &clkops_dspck,
298 .parent = &ck_dpll1, 298 .parent = &ck_dpll1,
299 .flags = VIRTUAL_IO_ADDRESS,
300 .enable_reg = DSP_IDLECT2, 299 .enable_reg = DSP_IDLECT2,
301 .enable_bit = EN_PERCK, 300 .enable_bit = EN_PERCK,
302 .rate_offset = CKCTL_PERDIV_OFFSET, 301 .rate_offset = CKCTL_PERDIV_OFFSET,
@@ -309,7 +308,6 @@ static struct clk dspxor_ck = {
309 .name = "dspxor_ck", 308 .name = "dspxor_ck",
310 .ops = &clkops_dspck, 309 .ops = &clkops_dspck,
311 .parent = &ck_ref, 310 .parent = &ck_ref,
312 .flags = VIRTUAL_IO_ADDRESS,
313 .enable_reg = DSP_IDLECT2, 311 .enable_reg = DSP_IDLECT2,
314 .enable_bit = EN_XORPCK, 312 .enable_bit = EN_XORPCK,
315 .recalc = &followparent_recalc, 313 .recalc = &followparent_recalc,
@@ -319,7 +317,6 @@ static struct clk dsptim_ck = {
319 .name = "dsptim_ck", 317 .name = "dsptim_ck",
320 .ops = &clkops_dspck, 318 .ops = &clkops_dspck,
321 .parent = &ck_ref, 319 .parent = &ck_ref,
322 .flags = VIRTUAL_IO_ADDRESS,
323 .enable_reg = DSP_IDLECT2, 320 .enable_reg = DSP_IDLECT2,
324 .enable_bit = EN_DSPTIMCK, 321 .enable_bit = EN_DSPTIMCK,
325 .recalc = &followparent_recalc, 322 .recalc = &followparent_recalc,
@@ -364,7 +361,7 @@ static struct clk l3_ocpi_ck = {
364 .name = "l3_ocpi_ck", 361 .name = "l3_ocpi_ck",
365 .ops = &clkops_generic, 362 .ops = &clkops_generic,
366 .parent = &tc_ck.clk, 363 .parent = &tc_ck.clk,
367 .enable_reg = (void __iomem *)ARM_IDLECT3, 364 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
368 .enable_bit = EN_OCPI_CK, 365 .enable_bit = EN_OCPI_CK,
369 .recalc = &followparent_recalc, 366 .recalc = &followparent_recalc,
370}; 367};
@@ -373,7 +370,7 @@ static struct clk tc1_ck = {
373 .name = "tc1_ck", 370 .name = "tc1_ck",
374 .ops = &clkops_generic, 371 .ops = &clkops_generic,
375 .parent = &tc_ck.clk, 372 .parent = &tc_ck.clk,
376 .enable_reg = (void __iomem *)ARM_IDLECT3, 373 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
377 .enable_bit = EN_TC1_CK, 374 .enable_bit = EN_TC1_CK,
378 .recalc = &followparent_recalc, 375 .recalc = &followparent_recalc,
379}; 376};
@@ -382,7 +379,7 @@ static struct clk tc2_ck = {
382 .name = "tc2_ck", 379 .name = "tc2_ck",
383 .ops = &clkops_generic, 380 .ops = &clkops_generic,
384 .parent = &tc_ck.clk, 381 .parent = &tc_ck.clk,
385 .enable_reg = (void __iomem *)ARM_IDLECT3, 382 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
386 .enable_bit = EN_TC2_CK, 383 .enable_bit = EN_TC2_CK,
387 .recalc = &followparent_recalc, 384 .recalc = &followparent_recalc,
388}; 385};
@@ -408,7 +405,7 @@ static struct arm_idlect1_clk api_ck = {
408 .ops = &clkops_generic, 405 .ops = &clkops_generic,
409 .parent = &tc_ck.clk, 406 .parent = &tc_ck.clk,
410 .flags = CLOCK_IDLE_CONTROL, 407 .flags = CLOCK_IDLE_CONTROL,
411 .enable_reg = (void __iomem *)ARM_IDLECT2, 408 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
412 .enable_bit = EN_APICK, 409 .enable_bit = EN_APICK,
413 .recalc = &followparent_recalc, 410 .recalc = &followparent_recalc,
414 }, 411 },
@@ -421,7 +418,7 @@ static struct arm_idlect1_clk lb_ck = {
421 .ops = &clkops_generic, 418 .ops = &clkops_generic,
422 .parent = &tc_ck.clk, 419 .parent = &tc_ck.clk,
423 .flags = CLOCK_IDLE_CONTROL, 420 .flags = CLOCK_IDLE_CONTROL,
424 .enable_reg = (void __iomem *)ARM_IDLECT2, 421 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
425 .enable_bit = EN_LBCK, 422 .enable_bit = EN_LBCK,
426 .recalc = &followparent_recalc, 423 .recalc = &followparent_recalc,
427 }, 424 },
@@ -446,7 +443,7 @@ static struct clk lcd_ck_16xx = {
446 .name = "lcd_ck", 443 .name = "lcd_ck",
447 .ops = &clkops_generic, 444 .ops = &clkops_generic,
448 .parent = &ck_dpll1, 445 .parent = &ck_dpll1,
449 .enable_reg = (void __iomem *)ARM_IDLECT2, 446 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
450 .enable_bit = EN_LCDCK, 447 .enable_bit = EN_LCDCK,
451 .rate_offset = CKCTL_LCDDIV_OFFSET, 448 .rate_offset = CKCTL_LCDDIV_OFFSET,
452 .recalc = &omap1_ckctl_recalc, 449 .recalc = &omap1_ckctl_recalc,
@@ -460,7 +457,7 @@ static struct arm_idlect1_clk lcd_ck_1510 = {
460 .ops = &clkops_generic, 457 .ops = &clkops_generic,
461 .parent = &ck_dpll1, 458 .parent = &ck_dpll1,
462 .flags = CLOCK_IDLE_CONTROL, 459 .flags = CLOCK_IDLE_CONTROL,
463 .enable_reg = (void __iomem *)ARM_IDLECT2, 460 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
464 .enable_bit = EN_LCDCK, 461 .enable_bit = EN_LCDCK,
465 .rate_offset = CKCTL_LCDDIV_OFFSET, 462 .rate_offset = CKCTL_LCDDIV_OFFSET,
466 .recalc = &omap1_ckctl_recalc, 463 .recalc = &omap1_ckctl_recalc,
@@ -477,7 +474,7 @@ static struct clk uart1_1510 = {
477 .parent = &armper_ck.clk, 474 .parent = &armper_ck.clk,
478 .rate = 12000000, 475 .rate = 12000000,
479 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, 476 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
480 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, 477 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
481 .enable_bit = 29, /* Chooses between 12MHz and 48MHz */ 478 .enable_bit = 29, /* Chooses between 12MHz and 48MHz */
482 .set_rate = &omap1_set_uart_rate, 479 .set_rate = &omap1_set_uart_rate,
483 .recalc = &omap1_uart_recalc, 480 .recalc = &omap1_uart_recalc,
@@ -492,7 +489,7 @@ static struct uart_clk uart1_16xx = {
492 .rate = 48000000, 489 .rate = 48000000,
493 .flags = RATE_FIXED | ENABLE_REG_32BIT | 490 .flags = RATE_FIXED | ENABLE_REG_32BIT |
494 CLOCK_NO_IDLE_PARENT, 491 CLOCK_NO_IDLE_PARENT,
495 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, 492 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
496 .enable_bit = 29, 493 .enable_bit = 29,
497 }, 494 },
498 .sysc_addr = 0xfffb0054, 495 .sysc_addr = 0xfffb0054,
@@ -505,7 +502,7 @@ static struct clk uart2_ck = {
505 .parent = &armper_ck.clk, 502 .parent = &armper_ck.clk,
506 .rate = 12000000, 503 .rate = 12000000,
507 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, 504 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
508 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, 505 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
509 .enable_bit = 30, /* Chooses between 12MHz and 48MHz */ 506 .enable_bit = 30, /* Chooses between 12MHz and 48MHz */
510 .set_rate = &omap1_set_uart_rate, 507 .set_rate = &omap1_set_uart_rate,
511 .recalc = &omap1_uart_recalc, 508 .recalc = &omap1_uart_recalc,
@@ -518,7 +515,7 @@ static struct clk uart3_1510 = {
518 .parent = &armper_ck.clk, 515 .parent = &armper_ck.clk,
519 .rate = 12000000, 516 .rate = 12000000,
520 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, 517 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
521 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, 518 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
522 .enable_bit = 31, /* Chooses between 12MHz and 48MHz */ 519 .enable_bit = 31, /* Chooses between 12MHz and 48MHz */
523 .set_rate = &omap1_set_uart_rate, 520 .set_rate = &omap1_set_uart_rate,
524 .recalc = &omap1_uart_recalc, 521 .recalc = &omap1_uart_recalc,
@@ -533,7 +530,7 @@ static struct uart_clk uart3_16xx = {
533 .rate = 48000000, 530 .rate = 48000000,
534 .flags = RATE_FIXED | ENABLE_REG_32BIT | 531 .flags = RATE_FIXED | ENABLE_REG_32BIT |
535 CLOCK_NO_IDLE_PARENT, 532 CLOCK_NO_IDLE_PARENT,
536 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, 533 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
537 .enable_bit = 31, 534 .enable_bit = 31,
538 }, 535 },
539 .sysc_addr = 0xfffb9854, 536 .sysc_addr = 0xfffb9854,
@@ -545,7 +542,7 @@ static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */
545 /* Direct from ULPD, no parent */ 542 /* Direct from ULPD, no parent */
546 .rate = 6000000, 543 .rate = 6000000,
547 .flags = RATE_FIXED | ENABLE_REG_32BIT, 544 .flags = RATE_FIXED | ENABLE_REG_32BIT,
548 .enable_reg = (void __iomem *)ULPD_CLOCK_CTRL, 545 .enable_reg = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL),
549 .enable_bit = USB_MCLK_EN_BIT, 546 .enable_bit = USB_MCLK_EN_BIT,
550}; 547};
551 548
@@ -555,7 +552,7 @@ static struct clk usb_hhc_ck1510 = {
555 /* Direct from ULPD, no parent */ 552 /* Direct from ULPD, no parent */
556 .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */ 553 .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
557 .flags = RATE_FIXED | ENABLE_REG_32BIT, 554 .flags = RATE_FIXED | ENABLE_REG_32BIT,
558 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, 555 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
559 .enable_bit = USB_HOST_HHC_UHOST_EN, 556 .enable_bit = USB_HOST_HHC_UHOST_EN,
560}; 557};
561 558
@@ -566,7 +563,7 @@ static struct clk usb_hhc_ck16xx = {
566 .rate = 48000000, 563 .rate = 48000000,
567 /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */ 564 /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
568 .flags = RATE_FIXED | ENABLE_REG_32BIT, 565 .flags = RATE_FIXED | ENABLE_REG_32BIT,
569 .enable_reg = (void __iomem *)OTG_BASE + 0x08 /* OTG_SYSCON_2 */, 566 .enable_reg = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */
570 .enable_bit = 8 /* UHOST_EN */, 567 .enable_bit = 8 /* UHOST_EN */,
571}; 568};
572 569
@@ -576,7 +573,7 @@ static struct clk usb_dc_ck = {
576 /* Direct from ULPD, no parent */ 573 /* Direct from ULPD, no parent */
577 .rate = 48000000, 574 .rate = 48000000,
578 .flags = RATE_FIXED, 575 .flags = RATE_FIXED,
579 .enable_reg = (void __iomem *)SOFT_REQ_REG, 576 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
580 .enable_bit = 4, 577 .enable_bit = 4,
581}; 578};
582 579
@@ -586,15 +583,15 @@ static struct clk mclk_1510 = {
586 /* Direct from ULPD, no parent. May be enabled by ext hardware. */ 583 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
587 .rate = 12000000, 584 .rate = 12000000,
588 .flags = RATE_FIXED, 585 .flags = RATE_FIXED,
589 .enable_reg = (void __iomem *)SOFT_REQ_REG, 586 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
590 .enable_bit = 6, 587 .enable_bit = 6,
591}; 588};
592 589
593static struct clk mclk_16xx = { 590static struct clk mclk_16xx = {
594 .name = "mclk", 591 .name = "mclk",
595 .ops = &clkops_generic, 592 .ops = &clkops_generic,
596 /* Direct from ULPD, no parent. May be enabled by ext hardware. */ 593 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
597 .enable_reg = (void __iomem *)COM_CLK_DIV_CTRL_SEL, 594 .enable_reg = OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL),
598 .enable_bit = COM_ULPD_PLL_CLK_REQ, 595 .enable_bit = COM_ULPD_PLL_CLK_REQ,
599 .set_rate = &omap1_set_ext_clk_rate, 596 .set_rate = &omap1_set_ext_clk_rate,
600 .round_rate = &omap1_round_ext_clk_rate, 597 .round_rate = &omap1_round_ext_clk_rate,
@@ -613,7 +610,7 @@ static struct clk bclk_16xx = {
613 .name = "bclk", 610 .name = "bclk",
614 .ops = &clkops_generic, 611 .ops = &clkops_generic,
615 /* Direct from ULPD, no parent. May be enabled by ext hardware. */ 612 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
616 .enable_reg = (void __iomem *)SWD_CLK_DIV_CTRL_SEL, 613 .enable_reg = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL),
617 .enable_bit = SWD_ULPD_PLL_CLK_REQ, 614 .enable_bit = SWD_ULPD_PLL_CLK_REQ,
618 .set_rate = &omap1_set_ext_clk_rate, 615 .set_rate = &omap1_set_ext_clk_rate,
619 .round_rate = &omap1_round_ext_clk_rate, 616 .round_rate = &omap1_round_ext_clk_rate,
@@ -627,7 +624,7 @@ static struct clk mmc1_ck = {
627 .parent = &armper_ck.clk, 624 .parent = &armper_ck.clk,
628 .rate = 48000000, 625 .rate = 48000000,
629 .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, 626 .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
630 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, 627 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
631 .enable_bit = 23, 628 .enable_bit = 23,
632}; 629};
633 630
@@ -639,7 +636,7 @@ static struct clk mmc2_ck = {
639 .parent = &armper_ck.clk, 636 .parent = &armper_ck.clk,
640 .rate = 48000000, 637 .rate = 48000000,
641 .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, 638 .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
642 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, 639 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
643 .enable_bit = 20, 640 .enable_bit = 20,
644}; 641};
645 642
diff --git a/arch/arm/plat-omap/include/mach/clock.h b/arch/arm/plat-omap/include/mach/clock.h
index cd69111cd33..8705902de1d 100644
--- a/arch/arm/plat-omap/include/mach/clock.h
+++ b/arch/arm/plat-omap/include/mach/clock.h
@@ -134,7 +134,6 @@ extern const struct clkops clkops_null;
134#define RATE_PROPAGATES (1 << 2) /* Program children too */ 134#define RATE_PROPAGATES (1 << 2) /* Program children too */
135/* bits 3-4 are free */ 135/* bits 3-4 are free */
136#define ENABLE_REG_32BIT (1 << 5) /* Use 32-bit access */ 136#define ENABLE_REG_32BIT (1 << 5) /* Use 32-bit access */
137#define VIRTUAL_IO_ADDRESS (1 << 6) /* Clock in virtual address */
138#define CLOCK_IDLE_CONTROL (1 << 7) 137#define CLOCK_IDLE_CONTROL (1 << 7)
139#define CLOCK_NO_IDLE_PARENT (1 << 8) 138#define CLOCK_NO_IDLE_PARENT (1 << 8)
140#define DELAYED_APP (1 << 9) /* Delay application of clock */ 139#define DELAYED_APP (1 << 9) /* Delay application of clock */
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-22 00:40:56 -0400