diff options
-rw-r--r-- | arch/x86/include/asm/perf_event.h | 38 | ||||
-rw-r--r-- | arch/x86/kernel/cpu/perf_event_amd.c | 4 | ||||
-rw-r--r-- | arch/x86/oprofile/op_model_amd.c | 37 |
3 files changed, 40 insertions, 39 deletions
diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h index e47cb6167e8..e9e277c6991 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h | |||
@@ -46,14 +46,17 @@ | |||
46 | #define AMD64_RAW_EVENT_MASK \ | 46 | #define AMD64_RAW_EVENT_MASK \ |
47 | (X86_RAW_EVENT_MASK | \ | 47 | (X86_RAW_EVENT_MASK | \ |
48 | AMD64_EVENTSEL_EVENT) | 48 | AMD64_EVENTSEL_EVENT) |
49 | #define AMD64_NUM_COUNTERS 4 | ||
50 | #define AMD64_NUM_COUNTERS_F15H 6 | ||
51 | #define AMD64_NUM_COUNTERS_MAX AMD64_NUM_COUNTERS_F15H | ||
49 | 52 | ||
50 | #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL 0x3c | 53 | #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL 0x3c |
51 | #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK (0x00 << 8) | 54 | #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK (0x00 << 8) |
52 | #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX 0 | 55 | #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX 0 |
53 | #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT \ | 56 | #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT \ |
54 | (1 << (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX)) | 57 | (1 << (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX)) |
55 | 58 | ||
56 | #define ARCH_PERFMON_BRANCH_MISSES_RETIRED 6 | 59 | #define ARCH_PERFMON_BRANCH_MISSES_RETIRED 6 |
57 | 60 | ||
58 | /* | 61 | /* |
59 | * Intel "Architectural Performance Monitoring" CPUID | 62 | * Intel "Architectural Performance Monitoring" CPUID |
@@ -113,6 +116,35 @@ union cpuid10_edx { | |||
113 | */ | 116 | */ |
114 | #define X86_PMC_IDX_FIXED_BTS (X86_PMC_IDX_FIXED + 16) | 117 | #define X86_PMC_IDX_FIXED_BTS (X86_PMC_IDX_FIXED + 16) |
115 | 118 | ||
119 | /* | ||
120 | * IBS cpuid feature detection | ||
121 | */ | ||
122 | |||
123 | #define IBS_CPUID_FEATURES 0x8000001b | ||
124 | |||
125 | /* | ||
126 | * Same bit mask as for IBS cpuid feature flags (Fn8000_001B_EAX), but | ||
127 | * bit 0 is used to indicate the existence of IBS. | ||
128 | */ | ||
129 | #define IBS_CAPS_AVAIL (1U<<0) | ||
130 | #define IBS_CAPS_FETCHSAM (1U<<1) | ||
131 | #define IBS_CAPS_OPSAM (1U<<2) | ||
132 | #define IBS_CAPS_RDWROPCNT (1U<<3) | ||
133 | #define IBS_CAPS_OPCNT (1U<<4) | ||
134 | #define IBS_CAPS_BRNTRGT (1U<<5) | ||
135 | #define IBS_CAPS_OPCNTEXT (1U<<6) | ||
136 | |||
137 | #define IBS_CAPS_DEFAULT (IBS_CAPS_AVAIL \ | ||
138 | | IBS_CAPS_FETCHSAM \ | ||
139 | | IBS_CAPS_OPSAM) | ||
140 | |||
141 | /* | ||
142 | * IBS APIC setup | ||
143 | */ | ||
144 | #define IBSCTL 0x1cc | ||
145 | #define IBSCTL_LVT_OFFSET_VALID (1ULL<<8) | ||
146 | #define IBSCTL_LVT_OFFSET_MASK 0x0F | ||
147 | |||
116 | /* IbsFetchCtl bits/masks */ | 148 | /* IbsFetchCtl bits/masks */ |
117 | #define IBS_FETCH_RAND_EN (1ULL<<57) | 149 | #define IBS_FETCH_RAND_EN (1ULL<<57) |
118 | #define IBS_FETCH_VAL (1ULL<<49) | 150 | #define IBS_FETCH_VAL (1ULL<<49) |
diff --git a/arch/x86/kernel/cpu/perf_event_amd.c b/arch/x86/kernel/cpu/perf_event_amd.c index db8e603ff0c..aeefd45697a 100644 --- a/arch/x86/kernel/cpu/perf_event_amd.c +++ b/arch/x86/kernel/cpu/perf_event_amd.c | |||
@@ -411,7 +411,7 @@ static __initconst const struct x86_pmu amd_pmu = { | |||
411 | .perfctr = MSR_K7_PERFCTR0, | 411 | .perfctr = MSR_K7_PERFCTR0, |
412 | .event_map = amd_pmu_event_map, | 412 | .event_map = amd_pmu_event_map, |
413 | .max_events = ARRAY_SIZE(amd_perfmon_event_map), | 413 | .max_events = ARRAY_SIZE(amd_perfmon_event_map), |
414 | .num_counters = 4, | 414 | .num_counters = AMD64_NUM_COUNTERS, |
415 | .cntval_bits = 48, | 415 | .cntval_bits = 48, |
416 | .cntval_mask = (1ULL << 48) - 1, | 416 | .cntval_mask = (1ULL << 48) - 1, |
417 | .apic = 1, | 417 | .apic = 1, |
@@ -575,7 +575,7 @@ static __initconst const struct x86_pmu amd_pmu_f15h = { | |||
575 | .perfctr = MSR_F15H_PERF_CTR, | 575 | .perfctr = MSR_F15H_PERF_CTR, |
576 | .event_map = amd_pmu_event_map, | 576 | .event_map = amd_pmu_event_map, |
577 | .max_events = ARRAY_SIZE(amd_perfmon_event_map), | 577 | .max_events = ARRAY_SIZE(amd_perfmon_event_map), |
578 | .num_counters = 6, | 578 | .num_counters = AMD64_NUM_COUNTERS_F15H, |
579 | .cntval_bits = 48, | 579 | .cntval_bits = 48, |
580 | .cntval_mask = (1ULL << 48) - 1, | 580 | .cntval_mask = (1ULL << 48) - 1, |
581 | .apic = 1, | 581 | .apic = 1, |
diff --git a/arch/x86/oprofile/op_model_amd.c b/arch/x86/oprofile/op_model_amd.c index 9cbb710dc94..e947e5cb2e6 100644 --- a/arch/x86/oprofile/op_model_amd.c +++ b/arch/x86/oprofile/op_model_amd.c | |||
@@ -29,8 +29,6 @@ | |||
29 | #include "op_x86_model.h" | 29 | #include "op_x86_model.h" |
30 | #include "op_counter.h" | 30 | #include "op_counter.h" |
31 | 31 | ||
32 | #define NUM_COUNTERS 4 | ||
33 | #define NUM_COUNTERS_F15H 6 | ||
34 | #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX | 32 | #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX |
35 | #define NUM_VIRT_COUNTERS 32 | 33 | #define NUM_VIRT_COUNTERS 32 |
36 | #else | 34 | #else |
@@ -70,35 +68,6 @@ static struct ibs_config ibs_config; | |||
70 | static struct ibs_state ibs_state; | 68 | static struct ibs_state ibs_state; |
71 | 69 | ||
72 | /* | 70 | /* |
73 | * IBS cpuid feature detection | ||
74 | */ | ||
75 | |||
76 | #define IBS_CPUID_FEATURES 0x8000001b | ||
77 | |||
78 | /* | ||
79 | * Same bit mask as for IBS cpuid feature flags (Fn8000_001B_EAX), but | ||
80 | * bit 0 is used to indicate the existence of IBS. | ||
81 | */ | ||
82 | #define IBS_CAPS_AVAIL (1U<<0) | ||
83 | #define IBS_CAPS_FETCHSAM (1U<<1) | ||
84 | #define IBS_CAPS_OPSAM (1U<<2) | ||
85 | #define IBS_CAPS_RDWROPCNT (1U<<3) | ||
86 | #define IBS_CAPS_OPCNT (1U<<4) | ||
87 | #define IBS_CAPS_BRNTRGT (1U<<5) | ||
88 | #define IBS_CAPS_OPCNTEXT (1U<<6) | ||
89 | |||
90 | #define IBS_CAPS_DEFAULT (IBS_CAPS_AVAIL \ | ||
91 | | IBS_CAPS_FETCHSAM \ | ||
92 | | IBS_CAPS_OPSAM) | ||
93 | |||
94 | /* | ||
95 | * IBS APIC setup | ||
96 | */ | ||
97 | #define IBSCTL 0x1cc | ||
98 | #define IBSCTL_LVT_OFFSET_VALID (1ULL<<8) | ||
99 | #define IBSCTL_LVT_OFFSET_MASK 0x0F | ||
100 | |||
101 | /* | ||
102 | * IBS randomization macros | 71 | * IBS randomization macros |
103 | */ | 72 | */ |
104 | #define IBS_RANDOM_BITS 12 | 73 | #define IBS_RANDOM_BITS 12 |
@@ -439,7 +408,7 @@ static int op_amd_fill_in_addresses(struct op_msrs * const msrs) | |||
439 | goto fail; | 408 | goto fail; |
440 | } | 409 | } |
441 | /* both registers must be reserved */ | 410 | /* both registers must be reserved */ |
442 | if (num_counters == NUM_COUNTERS_F15H) { | 411 | if (num_counters == AMD64_NUM_COUNTERS_F15H) { |
443 | msrs->counters[i].addr = MSR_F15H_PERF_CTR + (i << 1); | 412 | msrs->counters[i].addr = MSR_F15H_PERF_CTR + (i << 1); |
444 | msrs->controls[i].addr = MSR_F15H_PERF_CTL + (i << 1); | 413 | msrs->controls[i].addr = MSR_F15H_PERF_CTL + (i << 1); |
445 | } else { | 414 | } else { |
@@ -741,9 +710,9 @@ static int op_amd_init(struct oprofile_operations *ops) | |||
741 | ops->create_files = setup_ibs_files; | 710 | ops->create_files = setup_ibs_files; |
742 | 711 | ||
743 | if (boot_cpu_data.x86 == 0x15) { | 712 | if (boot_cpu_data.x86 == 0x15) { |
744 | num_counters = NUM_COUNTERS_F15H; | 713 | num_counters = AMD64_NUM_COUNTERS_F15H; |
745 | } else { | 714 | } else { |
746 | num_counters = NUM_COUNTERS; | 715 | num_counters = AMD64_NUM_COUNTERS; |
747 | } | 716 | } |
748 | 717 | ||
749 | op_amd_spec.num_counters = num_counters; | 718 | op_amd_spec.num_counters = num_counters; |