diff options
| -rw-r--r-- | drivers/clk/ux500/u8500_clk.c | 9 |
1 files changed, 3 insertions, 6 deletions
diff --git a/drivers/clk/ux500/u8500_clk.c b/drivers/clk/ux500/u8500_clk.c index ab30ce87614..1f6bfb8f873 100644 --- a/drivers/clk/ux500/u8500_clk.c +++ b/drivers/clk/ux500/u8500_clk.c | |||
| @@ -160,12 +160,6 @@ void u8500_clk_init(void) | |||
| 160 | clk = clk_reg_prcmu_gate("uiccclk", NULL, PRCMU_UICCCLK, CLK_IS_ROOT); | 160 | clk = clk_reg_prcmu_gate("uiccclk", NULL, PRCMU_UICCCLK, CLK_IS_ROOT); |
| 161 | clk_register_clkdev(clk, NULL, "uicc"); | 161 | clk_register_clkdev(clk, NULL, "uicc"); |
| 162 | 162 | ||
| 163 | /* | ||
| 164 | * FIXME: The MTU clocks might need some kind of "parent muxed join" | ||
| 165 | * and these have no K-clocks. For now, we ignore the missing | ||
| 166 | * connection to the corresponding P-clocks, p6_mtu0_clk and | ||
| 167 | * p6_mtu1_clk. Instead timclk is used which is the valid parent. | ||
| 168 | */ | ||
| 169 | clk = clk_reg_prcmu_gate("timclk", NULL, PRCMU_TIMCLK, CLK_IS_ROOT); | 163 | clk = clk_reg_prcmu_gate("timclk", NULL, PRCMU_TIMCLK, CLK_IS_ROOT); |
| 170 | clk_register_clkdev(clk, NULL, "mtu0"); | 164 | clk_register_clkdev(clk, NULL, "mtu0"); |
| 171 | clk_register_clkdev(clk, NULL, "mtu1"); | 165 | clk_register_clkdev(clk, NULL, "mtu1"); |
| @@ -379,8 +373,11 @@ void u8500_clk_init(void) | |||
| 379 | 373 | ||
| 380 | clk = clk_reg_prcc_pclk("p6_pclk6", "per6clk", U8500_CLKRST6_BASE, | 374 | clk = clk_reg_prcc_pclk("p6_pclk6", "per6clk", U8500_CLKRST6_BASE, |
| 381 | BIT(6), 0); | 375 | BIT(6), 0); |
| 376 | clk_register_clkdev(clk, "apb_pclk", "mtu0"); | ||
| 377 | |||
| 382 | clk = clk_reg_prcc_pclk("p6_pclk7", "per6clk", U8500_CLKRST6_BASE, | 378 | clk = clk_reg_prcc_pclk("p6_pclk7", "per6clk", U8500_CLKRST6_BASE, |
| 383 | BIT(7), 0); | 379 | BIT(7), 0); |
| 380 | clk_register_clkdev(clk, "apb_pclk", "mtu1"); | ||
| 384 | 381 | ||
| 385 | /* PRCC K-clocks | 382 | /* PRCC K-clocks |
| 386 | * | 383 | * |
