1 files changed, 5 insertions, 24 deletions

diff --git a/arch/i386/kernel/smpboot.c b/arch/i386/kernel/smpboot.c
index 346f27f4c79..b4e6f32de45 100644
--- a/arch/i386/kernel/smpboot.c
+++ b/arch/i386/kernel/smpboot.c
@@ -1130,34 +1130,15 @@ exit:
 }
 #endif
 
-static void smp_tune_scheduling (void)
+static void smp_tune_scheduling(void)
 {
         unsigned long cachesize;       /* kB   */
-        unsigned long bandwidth = 350; /* MB/s */
-        /*
-         * Rough estimation for SMP scheduling, this is the number of
-         * cycles it takes for a fully memory-limited process to flush
-         * the SMP-local cache.
-         *
-         * (For a P5 this pretty much means we will choose another idle
-         *  CPU almost always at wakeup time (this is due to the small
-         *  L1 cache), on PIIs it's around 50-100 usecs, depending on
-         *  the cache size)
-         */
 
-        if (!cpu_khz) {
-                /*
-                 * this basically disables processor-affinity
-                 * scheduling on SMP without a TSC.
-                 */
-                return;
-        } else {
+        if (cpu_khz) {
                 cachesize = boot_cpu_data.x86_cache_size;
-                if (cachesize == -1) {
-                        cachesize = 16; /* Pentiums, 2x8kB cache */
-                        bandwidth = 100;
-                }
-                max_cache_size = cachesize * 1024;
+
+                if (cachesize > 0)
+                        max_cache_size = cachesize * 1024;
         }
 }