aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--arch/arm/mach-exynos/Makefile9
-rw-r--r--arch/arm/mach-exynos/clock-exynos4210.c3
-rw-r--r--arch/arm/mach-exynos/clock-exynos4212.c3
-rw-r--r--arch/arm/mach-exynos/clock.c3
-rw-r--r--arch/arm/mach-exynos/common.c723
-rw-r--r--arch/arm/mach-exynos/common.h39
-rw-r--r--arch/arm/mach-exynos/cpu.c298
-rw-r--r--arch/arm/mach-exynos/include/mach/map.h12
-rw-r--r--arch/arm/mach-exynos/init.c42
-rw-r--r--arch/arm/mach-exynos/irq-combiner.c124
-rw-r--r--arch/arm/mach-exynos/irq-eint.c237
-rw-r--r--arch/arm/mach-exynos/mach-armlex4210.c5
-rw-r--r--arch/arm/mach-exynos/mach-nuri.c5
-rw-r--r--arch/arm/mach-exynos/mach-origen.c5
-rw-r--r--arch/arm/mach-exynos/mach-smdk4x12.c5
-rw-r--r--arch/arm/mach-exynos/mach-smdkv310.c5
-rw-r--r--arch/arm/mach-exynos/mach-universal_c210.c5
-rw-r--r--arch/arm/plat-s5p/Makefile1
-rw-r--r--arch/arm/plat-s5p/cpu.c104
-rw-r--r--arch/arm/plat-samsung/include/plat/cpu.h2
-rw-r--r--arch/arm/plat-samsung/include/plat/exynos4.h35
21 files changed, 793 insertions, 872 deletions
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 59069a35e40..bcb9efc576e 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -10,15 +10,17 @@ obj-m :=
10obj-n := 10obj-n :=
11obj- := 11obj- :=
12 12
13# Core support for EXYNOS4 system 13# Core
14 14
15obj-$(CONFIG_ARCH_EXYNOS4) += cpu.o init.o clock.o irq-combiner.o setup-i2c0.o 15obj-$(CONFIG_ARCH_EXYNOS4) += common.o clock.o
16obj-$(CONFIG_ARCH_EXYNOS4) += irq-eint.o dma.o pmu.o
17obj-$(CONFIG_CPU_EXYNOS4210) += clock-exynos4210.o 16obj-$(CONFIG_CPU_EXYNOS4210) += clock-exynos4210.o
18obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o 17obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o
18
19obj-$(CONFIG_PM) += pm.o 19obj-$(CONFIG_PM) += pm.o
20obj-$(CONFIG_CPU_IDLE) += cpuidle.o 20obj-$(CONFIG_CPU_IDLE) += cpuidle.o
21 21
22obj-$(CONFIG_ARCH_EXYNOS4) += dma.o pmu.o
23
22obj-$(CONFIG_SMP) += platsmp.o headsmp.o 24obj-$(CONFIG_SMP) += platsmp.o headsmp.o
23 25
24obj-$(CONFIG_EXYNOS4_MCT) += mct.o 26obj-$(CONFIG_EXYNOS4_MCT) += mct.o
@@ -45,6 +47,7 @@ obj-$(CONFIG_EXYNOS4_DEV_PD) += dev-pd.o
45obj-$(CONFIG_EXYNOS4_DEV_SYSMMU) += dev-sysmmu.o 47obj-$(CONFIG_EXYNOS4_DEV_SYSMMU) += dev-sysmmu.o
46obj-$(CONFIG_EXYNOS4_DEV_DWMCI) += dev-dwmci.o 48obj-$(CONFIG_EXYNOS4_DEV_DWMCI) += dev-dwmci.o
47 49
50obj-$(CONFIG_ARCH_EXYNOS4) += setup-i2c0.o
48obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o 51obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o
49obj-$(CONFIG_EXYNOS4_SETUP_FIMD0) += setup-fimd0.o 52obj-$(CONFIG_EXYNOS4_SETUP_FIMD0) += setup-fimd0.o
50obj-$(CONFIG_EXYNOS4_SETUP_I2C1) += setup-i2c1.o 53obj-$(CONFIG_EXYNOS4_SETUP_I2C1) += setup-i2c1.o
diff --git a/arch/arm/mach-exynos/clock-exynos4210.c b/arch/arm/mach-exynos/clock-exynos4210.c
index b9d5ef670eb..a5823a7f249 100644
--- a/arch/arm/mach-exynos/clock-exynos4210.c
+++ b/arch/arm/mach-exynos/clock-exynos4210.c
@@ -23,7 +23,6 @@
23#include <plat/pll.h> 23#include <plat/pll.h>
24#include <plat/s5p-clock.h> 24#include <plat/s5p-clock.h>
25#include <plat/clock-clksrc.h> 25#include <plat/clock-clksrc.h>
26#include <plat/exynos4.h>
27#include <plat/pm.h> 26#include <plat/pm.h>
28 27
29#include <mach/hardware.h> 28#include <mach/hardware.h>
@@ -31,6 +30,8 @@
31#include <mach/regs-clock.h> 30#include <mach/regs-clock.h>
32#include <mach/exynos4-clock.h> 31#include <mach/exynos4-clock.h>
33 32
33#include "common.h"
34
34static struct sleep_save exynos4210_clock_save[] = { 35static struct sleep_save exynos4210_clock_save[] = {
35 SAVE_ITEM(S5P_CLKSRC_IMAGE), 36 SAVE_ITEM(S5P_CLKSRC_IMAGE),
36 SAVE_ITEM(S5P_CLKSRC_LCD1), 37 SAVE_ITEM(S5P_CLKSRC_LCD1),
diff --git a/arch/arm/mach-exynos/clock-exynos4212.c b/arch/arm/mach-exynos/clock-exynos4212.c
index 77d5decb34f..26a668b0d10 100644
--- a/arch/arm/mach-exynos/clock-exynos4212.c
+++ b/arch/arm/mach-exynos/clock-exynos4212.c
@@ -23,7 +23,6 @@
23#include <plat/pll.h> 23#include <plat/pll.h>
24#include <plat/s5p-clock.h> 24#include <plat/s5p-clock.h>
25#include <plat/clock-clksrc.h> 25#include <plat/clock-clksrc.h>
26#include <plat/exynos4.h>
27#include <plat/pm.h> 26#include <plat/pm.h>
28 27
29#include <mach/hardware.h> 28#include <mach/hardware.h>
@@ -31,6 +30,8 @@
31#include <mach/regs-clock.h> 30#include <mach/regs-clock.h>
32#include <mach/exynos4-clock.h> 31#include <mach/exynos4-clock.h>
33 32
33#include "common.h"
34
34static struct sleep_save exynos4212_clock_save[] = { 35static struct sleep_save exynos4212_clock_save[] = {
35 SAVE_ITEM(S5P_CLKSRC_IMAGE), 36 SAVE_ITEM(S5P_CLKSRC_IMAGE),
36 SAVE_ITEM(S5P_CLKDIV_IMAGE), 37 SAVE_ITEM(S5P_CLKDIV_IMAGE),
diff --git a/arch/arm/mach-exynos/clock.c b/arch/arm/mach-exynos/clock.c
index 2894f0adef5..83616a039b1 100644
--- a/arch/arm/mach-exynos/clock.c
+++ b/arch/arm/mach-exynos/clock.c
@@ -21,7 +21,6 @@
21#include <plat/pll.h> 21#include <plat/pll.h>
22#include <plat/s5p-clock.h> 22#include <plat/s5p-clock.h>
23#include <plat/clock-clksrc.h> 23#include <plat/clock-clksrc.h>
24#include <plat/exynos4.h>
25#include <plat/pm.h> 24#include <plat/pm.h>
26 25
27#include <mach/map.h> 26#include <mach/map.h>
@@ -29,6 +28,8 @@
29#include <mach/sysmmu.h> 28#include <mach/sysmmu.h>
30#include <mach/exynos4-clock.h> 29#include <mach/exynos4-clock.h>
31 30
31#include "common.h"
32
32static struct sleep_save exynos4_clock_save[] = { 33static struct sleep_save exynos4_clock_save[] = {
33 SAVE_ITEM(S5P_CLKDIV_LEFTBUS), 34 SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
34 SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS), 35 SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
new file mode 100644
index 00000000000..eecac125307
--- /dev/null
+++ b/arch/arm/mach-exynos/common.c
@@ -0,0 +1,723 @@
1/*
2 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Common Codes for EXYNOS
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/kernel.h>
13#include <linux/interrupt.h>
14#include <linux/irq.h>
15#include <linux/io.h>
16#include <linux/sysdev.h>
17#include <linux/gpio.h>
18#include <linux/sched.h>
19#include <linux/serial_core.h>
20
21#include <asm/proc-fns.h>
22#include <asm/hardware/cache-l2x0.h>
23#include <asm/hardware/gic.h>
24#include <asm/mach/map.h>
25#include <asm/mach/irq.h>
26
27#include <mach/regs-irq.h>
28#include <mach/regs-pmu.h>
29#include <mach/regs-gpio.h>
30
31#include <plat/cpu.h>
32#include <plat/clock.h>
33#include <plat/devs.h>
34#include <plat/pm.h>
35#include <plat/reset.h>
36#include <plat/sdhci.h>
37#include <plat/gpio-cfg.h>
38#include <plat/adc-core.h>
39#include <plat/fb-core.h>
40#include <plat/fimc-core.h>
41#include <plat/iic-core.h>
42#include <plat/tv-core.h>
43#include <plat/regs-serial.h>
44
45#include "common.h"
46
47unsigned int gic_bank_offset __read_mostly;
48
49static const char name_exynos4210[] = "EXYNOS4210";
50static const char name_exynos4212[] = "EXYNOS4212";
51static const char name_exynos4412[] = "EXYNOS4412";
52
53static struct cpu_table cpu_ids[] __initdata = {
54 {
55 .idcode = EXYNOS4210_CPU_ID,
56 .idmask = EXYNOS4_CPU_MASK,
57 .map_io = exynos4_map_io,
58 .init_clocks = exynos4_init_clocks,
59 .init_uarts = exynos4_init_uarts,
60 .init = exynos_init,
61 .name = name_exynos4210,
62 }, {
63 .idcode = EXYNOS4212_CPU_ID,
64 .idmask = EXYNOS4_CPU_MASK,
65 .map_io = exynos4_map_io,
66 .init_clocks = exynos4_init_clocks,
67 .init_uarts = exynos4_init_uarts,
68 .init = exynos_init,
69 .name = name_exynos4212,
70 }, {
71 .idcode = EXYNOS4412_CPU_ID,
72 .idmask = EXYNOS4_CPU_MASK,
73 .map_io = exynos4_map_io,
74 .init_clocks = exynos4_init_clocks,
75 .init_uarts = exynos4_init_uarts,
76 .init = exynos_init,
77 .name = name_exynos4412,
78 },
79};
80
81/* Initial IO mappings */
82
83static struct map_desc exynos_iodesc[] __initdata = {
84 {
85 .virtual = (unsigned long)S5P_VA_CHIPID,
86 .pfn = __phys_to_pfn(EXYNOS4_PA_CHIPID),
87 .length = SZ_4K,
88 .type = MT_DEVICE,
89 }, {
90 .virtual = (unsigned long)S3C_VA_SYS,
91 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSCON),
92 .length = SZ_64K,
93 .type = MT_DEVICE,
94 }, {
95 .virtual = (unsigned long)S3C_VA_TIMER,
96 .pfn = __phys_to_pfn(EXYNOS4_PA_TIMER),
97 .length = SZ_16K,
98 .type = MT_DEVICE,
99 }, {
100 .virtual = (unsigned long)S3C_VA_WATCHDOG,
101 .pfn = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
102 .length = SZ_4K,
103 .type = MT_DEVICE,
104 }, {
105 .virtual = (unsigned long)S5P_VA_SROMC,
106 .pfn = __phys_to_pfn(EXYNOS4_PA_SROMC),
107 .length = SZ_4K,
108 .type = MT_DEVICE,
109 }, {
110 .virtual = (unsigned long)S5P_VA_SYSTIMER,
111 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
112 .length = SZ_4K,
113 .type = MT_DEVICE,
114 }, {
115 .virtual = (unsigned long)S5P_VA_PMU,
116 .pfn = __phys_to_pfn(EXYNOS4_PA_PMU),
117 .length = SZ_64K,
118 .type = MT_DEVICE,
119 }, {
120 .virtual = (unsigned long)S5P_VA_COMBINER_BASE,
121 .pfn = __phys_to_pfn(EXYNOS4_PA_COMBINER),
122 .length = SZ_4K,
123 .type = MT_DEVICE,
124 }, {
125 .virtual = (unsigned long)S5P_VA_GIC_CPU,
126 .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
127 .length = SZ_64K,
128 .type = MT_DEVICE,
129 }, {
130 .virtual = (unsigned long)S5P_VA_GIC_DIST,
131 .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
132 .length = SZ_64K,
133 .type = MT_DEVICE,
134 }, {
135 .virtual = (unsigned long)S3C_VA_UART,
136 .pfn = __phys_to_pfn(EXYNOS4_PA_UART),
137 .length = SZ_512K,
138 .type = MT_DEVICE,
139 },
140};
141
142static struct map_desc exynos4_iodesc[] __initdata = {
143 {
144 .virtual = (unsigned long)S5P_VA_CMU,
145 .pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
146 .length = SZ_128K,
147 .type = MT_DEVICE,
148 }, {
149 .virtual = (unsigned long)S5P_VA_COREPERI_BASE,
150 .pfn = __phys_to_pfn(EXYNOS4_PA_COREPERI),
151 .length = SZ_8K,
152 .type = MT_DEVICE,
153 }, {
154 .virtual = (unsigned long)S5P_VA_L2CC,
155 .pfn = __phys_to_pfn(EXYNOS4_PA_L2CC),
156 .length = SZ_4K,
157 .type = MT_DEVICE,
158 }, {
159 .virtual = (unsigned long)S5P_VA_GPIO1,
160 .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO1),
161 .length = SZ_4K,
162 .type = MT_DEVICE,
163 }, {
164 .virtual = (unsigned long)S5P_VA_GPIO2,
165 .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO2),
166 .length = SZ_4K,
167 .type = MT_DEVICE,
168 }, {
169 .virtual = (unsigned long)S5P_VA_GPIO3,
170 .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO3),
171 .length = SZ_256,
172 .type = MT_DEVICE,
173 }, {
174 .virtual = (unsigned long)S5P_VA_DMC0,
175 .pfn = __phys_to_pfn(EXYNOS4_PA_DMC0),
176 .length = SZ_4K,
177 .type = MT_DEVICE,
178 }, {
179 .virtual = (unsigned long)S5P_VA_SROMC,
180 .pfn = __phys_to_pfn(EXYNOS4_PA_SROMC),
181 .length = SZ_4K,
182 .type = MT_DEVICE,
183 }, {
184 .virtual = (unsigned long)S3C_VA_USB_HSPHY,
185 .pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY),
186 .length = SZ_4K,
187 .type = MT_DEVICE,
188 },
189};
190
191static struct map_desc exynos4_iodesc0[] __initdata = {
192 {
193 .virtual = (unsigned long)S5P_VA_SYSRAM,
194 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
195 .length = SZ_4K,
196 .type = MT_DEVICE,
197 },
198};
199
200static struct map_desc exynos4_iodesc1[] __initdata = {
201 {
202 .virtual = (unsigned long)S5P_VA_SYSRAM,
203 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
204 .length = SZ_4K,
205 .type = MT_DEVICE,
206 },
207};
208
209static void exynos_idle(void)
210{
211 if (!need_resched())
212 cpu_do_idle();
213
214 local_irq_enable();
215}
216
217static void exynos4_sw_reset(void)
218{
219 __raw_writel(0x1, S5P_SWRESET);
220}
221
222/*
223 * exynos_map_io
224 *
225 * register the standard cpu IO areas
226 */
227
228void __init exynos_init_io(struct map_desc *mach_desc, int size)
229{
230 /* initialize the io descriptors we need for initialization */
231 iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));
232 if (mach_desc)
233 iotable_init(mach_desc, size);
234
235 /* detect cpu id and rev. */
236 s5p_init_cpu(S5P_VA_CHIPID);
237
238 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
239}
240
241void __init exynos4_map_io(void)
242{
243 iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
244
245 if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
246 iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
247 else
248 iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
249
250 /* initialize device information early */
251 exynos4_default_sdhci0();
252 exynos4_default_sdhci1();
253 exynos4_default_sdhci2();
254 exynos4_default_sdhci3();
255
256 s3c_adc_setname("samsung-adc-v3");
257
258 s3c_fimc_setname(0, "exynos4-fimc");
259 s3c_fimc_setname(1, "exynos4-fimc");
260 s3c_fimc_setname(2, "exynos4-fimc");
261 s3c_fimc_setname(3, "exynos4-fimc");
262
263 /* The I2C bus controllers are directly compatible with s3c2440 */
264 s3c_i2c0_setname("s3c2440-i2c");
265 s3c_i2c1_setname("s3c2440-i2c");
266 s3c_i2c2_setname("s3c2440-i2c");
267
268 s5p_fb_setname(0, "exynos4-fb");
269 s5p_hdmi_setname("exynos4-hdmi");
270}
271
272void __init exynos4_init_clocks(int xtal)
273{
274 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
275
276 s3c24xx_register_baseclocks(xtal);
277 s5p_register_clocks(xtal);
278
279 if (soc_is_exynos4210())
280 exynos4210_register_clocks();
281 else if (soc_is_exynos4212() || soc_is_exynos4412())
282 exynos4212_register_clocks();
283
284 exynos4_register_clocks();
285 exynos4_setup_clocks();
286}
287
288#define COMBINER_ENABLE_SET 0x0
289#define COMBINER_ENABLE_CLEAR 0x4
290#define COMBINER_INT_STATUS 0xC
291
292static DEFINE_SPINLOCK(irq_controller_lock);
293
294struct combiner_chip_data {
295 unsigned int irq_offset;
296 unsigned int irq_mask;
297 void __iomem *base;
298};
299
300static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
301
302static inline void __iomem *combiner_base(struct irq_data *data)
303{
304 struct combiner_chip_data *combiner_data =
305 irq_data_get_irq_chip_data(data);
306
307 return combiner_data->base;
308}
309
310static void combiner_mask_irq(struct irq_data *data)
311{
312 u32 mask = 1 << (data->irq % 32);
313
314 __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
315}
316
317static void combiner_unmask_irq(struct irq_data *data)
318{
319 u32 mask = 1 << (data->irq % 32);
320
321 __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
322}
323
324static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
325{
326 struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
327 struct irq_chip *chip = irq_get_chip(irq);
328 unsigned int cascade_irq, combiner_irq;
329 unsigned long status;
330
331 chained_irq_enter(chip, desc);
332
333 spin_lock(&irq_controller_lock);
334 status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
335 spin_unlock(&irq_controller_lock);
336 status &= chip_data->irq_mask;
337
338 if (status == 0)
339 goto out;
340
341 combiner_irq = __ffs(status);
342
343 cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
344 if (unlikely(cascade_irq >= NR_IRQS))
345 do_bad_IRQ(cascade_irq, desc);
346 else
347 generic_handle_irq(cascade_irq);
348
349 out:
350 chained_irq_exit(chip, desc);
351}
352
353static struct irq_chip combiner_chip = {
354 .name = "COMBINER",
355 .irq_mask = combiner_mask_irq,
356 .irq_unmask = combiner_unmask_irq,
357};
358
359static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
360{
361 if (combiner_nr >= MAX_COMBINER_NR)
362 BUG();
363 if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
364 BUG();
365 irq_set_chained_handler(irq, combiner_handle_cascade_irq);
366}
367
368static void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
369 unsigned int irq_start)
370{
371 unsigned int i;
372
373 if (combiner_nr >= MAX_COMBINER_NR)
374 BUG();
375
376 combiner_data[combiner_nr].base = base;
377 combiner_data[combiner_nr].irq_offset = irq_start;
378 combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
379
380 /* Disable all interrupts */
381
382 __raw_writel(combiner_data[combiner_nr].irq_mask,
383 base + COMBINER_ENABLE_CLEAR);
384
385 /* Setup the Linux IRQ subsystem */
386
387 for (i = irq_start; i < combiner_data[combiner_nr].irq_offset
388 + MAX_IRQ_IN_COMBINER; i++) {
389 irq_set_chip_and_handler(i, &combiner_chip, handle_level_irq);
390 irq_set_chip_data(i, &combiner_data[combiner_nr]);
391 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
392 }
393}
394
395static void exynos4_gic_irq_fix_base(struct irq_data *d)
396{
397 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
398
399 gic_data->cpu_base = S5P_VA_GIC_CPU +
400 (gic_bank_offset * smp_processor_id());
401
402 gic_data->dist_base = S5P_VA_GIC_DIST +
403 (gic_bank_offset * smp_processor_id());
404}
405
406void __init exynos4_init_irq(void)
407{
408 int irq;
409
410 gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
411
412 gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
413 gic_arch_extn.irq_eoi = exynos4_gic_irq_fix_base;
414 gic_arch_extn.irq_unmask = exynos4_gic_irq_fix_base;
415 gic_arch_extn.irq_mask = exynos4_gic_irq_fix_base;
416
417 for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
418
419 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
420 COMBINER_IRQ(irq, 0));
421 combiner_cascade_irq(irq, IRQ_SPI(irq));
422 }
423
424 /*
425 * The parameters of s5p_init_irq() are for VIC init.
426 * Theses parameters should be NULL and 0 because EXYNOS4
427 * uses GIC instead of VIC.
428 */
429 s5p_init_irq(NULL, 0);
430}
431
432struct sysdev_class exynos4_sysclass = {
433 .name = "exynos4-core",
434};
435
436static struct sys_device exynos4_sysdev = {
437 .cls = &exynos4_sysclass,
438};
439
440static int __init exynos4_core_init(void)
441{
442 return sysdev_class_register(&exynos4_sysclass);
443}
444core_initcall(exynos4_core_init);
445
446#ifdef CONFIG_CACHE_L2X0
447static int __init exynos4_l2x0_cache_init(void)
448{
449 /* TAG, Data Latency Control: 2cycle */
450 __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
451
452 if (soc_is_exynos4210())
453 __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
454 else if (soc_is_exynos4212() || soc_is_exynos4412())
455 __raw_writel(0x120, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
456
457 /* L2X0 Prefetch Control */
458 __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
459
460 /* L2X0 Power Control */
461 __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
462 S5P_VA_L2CC + L2X0_POWER_CTRL);
463
464 l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);
465
466 return 0;
467}
468
469early_initcall(exynos4_l2x0_cache_init);
470#endif
471
472int __init exynos_init(void)
473{
474 printk(KERN_INFO "EXYNOS: Initializing architecture\n");
475
476 /* set idle function */
477 pm_idle = exynos_idle;
478
479 /* set sw_reset function */
480 if (soc_is_exynos4210() || soc_is_exynos4212() || soc_is_exynos4412())
481 s5p_reset_hook = exynos4_sw_reset;
482
483 return sysdev_register(&exynos4_sysdev);
484}
485
486static struct s3c24xx_uart_clksrc exynos4_serial_clocks[] = {
487 [0] = {
488 .name = "uclk1",
489 .divisor = 1,
490 .min_baud = 0,
491 .max_baud = 0,
492 },
493};
494
495/* uart registration process */
496
497void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
498{
499 struct s3c2410_uartcfg *tcfg = cfg;
500 u32 ucnt;
501
502 for (ucnt = 0; ucnt < no; ucnt++, tcfg++) {
503 if (!tcfg->clocks) {
504 tcfg->has_fracval = 1;
505 tcfg->clocks = exynos4_serial_clocks;
506 tcfg->clocks_size = ARRAY_SIZE(exynos4_serial_clocks);
507 }
508 tcfg->flags |= NO_NEED_CHECK_CLKSRC;
509 }
510
511 s3c24xx_init_uartdevs("s5pv210-uart", s5p_uart_resources, cfg, no);
512}
513
514static DEFINE_SPINLOCK(eint_lock);
515
516static unsigned int eint0_15_data[16];
517
518static unsigned int exynos4_get_irq_nr(unsigned int number)
519{
520 u32 ret = 0;
521
522 switch (number) {
523 case 0 ... 3:
524 ret = (number + IRQ_EINT0);
525 break;
526 case 4 ... 7:
527 ret = (number + (IRQ_EINT4 - 4));
528 break;
529 case 8 ... 15:
530 ret = (number + (IRQ_EINT8 - 8));
531 break;
532 default:
533 printk(KERN_ERR "number available : %d\n", number);
534 }
535
536 return ret;
537}
538
539static inline void exynos4_irq_eint_mask(struct irq_data *data)
540{
541 u32 mask;
542
543 spin_lock(&eint_lock);
544 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
545 mask |= eint_irq_to_bit(data->irq);
546 __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
547 spin_unlock(&eint_lock);
548}
549
550static void exynos4_irq_eint_unmask(struct irq_data *data)
551{
552 u32 mask;
553
554 spin_lock(&eint_lock);
555 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
556 mask &= ~(eint_irq_to_bit(data->irq));
557 __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
558 spin_unlock(&eint_lock);
559}
560
561static inline void exynos4_irq_eint_ack(struct irq_data *data)
562{
563 __raw_writel(eint_irq_to_bit(data->irq),
564 S5P_EINT_PEND(EINT_REG_NR(data->irq)));
565}
566
567static void exynos4_irq_eint_maskack(struct irq_data *data)
568{
569 exynos4_irq_eint_mask(data);
570 exynos4_irq_eint_ack(data);
571}
572
573static int exynos4_irq_eint_set_type(struct irq_data *data, unsigned int type)
574{
575 int offs = EINT_OFFSET(data->irq);
576 int shift;
577 u32 ctrl, mask;
578 u32 newvalue = 0;
579
580 switch (type) {
581 case IRQ_TYPE_EDGE_RISING:
582 newvalue = S5P_IRQ_TYPE_EDGE_RISING;
583 break;
584
585 case IRQ_TYPE_EDGE_FALLING:
586 newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
587 break;
588
589 case IRQ_TYPE_EDGE_BOTH:
590 newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
591 break;
592
593 case IRQ_TYPE_LEVEL_LOW:
594 newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
595 break;
596
597 case IRQ_TYPE_LEVEL_HIGH:
598 newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
599 break;
600
601 default:
602 printk(KERN_ERR "No such irq type %d", type);
603 return -EINVAL;
604 }
605
606 shift = (offs & 0x7) * 4;
607 mask = 0x7 << shift;
608
609 spin_lock(&eint_lock);
610 ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq)));
611 ctrl &= ~mask;
612 ctrl |= newvalue << shift;
613 __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq)));
614 spin_unlock(&eint_lock);
615
616 switch (offs) {
617 case 0 ... 7:
618 s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE);
619 break;
620 case 8 ... 15:
621 s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE);
622 break;
623 case 16 ... 23:
624 s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE);
625 break;
626 case 24 ... 31:
627 s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE);
628 break;
629 default:
630 printk(KERN_ERR "No such irq number %d", offs);
631 }
632
633 return 0;
634}
635
636static struct irq_chip exynos4_irq_eint = {
637 .name = "exynos4-eint",
638 .irq_mask = exynos4_irq_eint_mask,
639 .irq_unmask = exynos4_irq_eint_unmask,
640 .irq_mask_ack = exynos4_irq_eint_maskack,
641 .irq_ack = exynos4_irq_eint_ack,
642 .irq_set_type = exynos4_irq_eint_set_type,
643#ifdef CONFIG_PM
644 .irq_set_wake = s3c_irqext_wake,
645#endif
646};
647
648/*
649 * exynos4_irq_demux_eint
650 *
651 * This function demuxes the IRQ from from EINTs 16 to 31.
652 * It is designed to be inlined into the specific handler
653 * s5p_irq_demux_eintX_Y.
654 *
655 * Each EINT pend/mask registers handle eight of them.
656 */
657static inline void exynos4_irq_demux_eint(unsigned int start)
658{
659 unsigned int irq;
660
661 u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start)));
662 u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start)));
663
664 status &= ~mask;
665 status &= 0xff;
666
667 while (status) {
668 irq = fls(status) - 1;
669 generic_handle_irq(irq + start);
670 status &= ~(1 << irq);
671 }
672}
673
674static void exynos4_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
675{
676 struct irq_chip *chip = irq_get_chip(irq);
677 chained_irq_enter(chip, desc);
678 exynos4_irq_demux_eint(IRQ_EINT(16));
679 exynos4_irq_demux_eint(IRQ_EINT(24));
680 chained_irq_exit(chip, desc);
681}
682
683static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
684{
685 u32 *irq_data = irq_get_handler_data(irq);
686 struct irq_chip *chip = irq_get_chip(irq);
687
688 chained_irq_enter(chip, desc);
689 chip->irq_mask(&desc->irq_data);
690
691 if (chip->irq_ack)
692 chip->irq_ack(&desc->irq_data);
693
694 generic_handle_irq(*irq_data);
695
696 chip->irq_unmask(&desc->irq_data);
697 chained_irq_exit(chip, desc);
698}
699
700int __init exynos4_init_irq_eint(void)
701{
702 int irq;
703
704 for (irq = 0 ; irq <= 31 ; irq++) {
705 irq_set_chip_and_handler(IRQ_EINT(irq), &exynos4_irq_eint,
706 handle_level_irq);
707 set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
708 }
709
710 irq_set_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31);
711
712 for (irq = 0 ; irq <= 15 ; irq++) {
713 eint0_15_data[irq] = IRQ_EINT(irq);
714
715 irq_set_handler_data(exynos4_get_irq_nr(irq),
716 &eint0_15_data[irq]);
717 irq_set_chained_handler(exynos4_get_irq_nr(irq),
718 exynos4_irq_eint0_15);
719 }
720
721 return 0;
722}
723arch_initcall(exynos4_init_irq_eint);
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
new file mode 100644
index 00000000000..0476c5f0887
--- /dev/null
+++ b/arch/arm/mach-exynos/common.h
@@ -0,0 +1,39 @@
1/*
2 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Common Header for EXYNOS machines
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H
13#define __ARCH_ARM_MACH_EXYNOS_COMMON_H
14
15void exynos_init_io(struct map_desc *mach_desc, int size);
16void exynos4_init_irq(void);
17
18void exynos4_register_clocks(void);
19void exynos4_setup_clocks(void);
20
21void exynos4210_register_clocks(void);
22void exynos4212_register_clocks(void);
23
24extern struct sys_timer exynos4_timer;
25
26#ifdef CONFIG_ARCH_EXYNOS
27extern int exynos_init(void);
28extern void exynos4_map_io(void);
29extern void exynos4_init_clocks(int xtal);
30extern void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
31
32#else
33#define exynos4_init_clocks NULL
34#define exynos4_init_uarts NULL
35#define exynos4_map_io NULL
36#define exynos_init NULL
37#endif
38
39#endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */
diff --git a/arch/arm/mach-exynos/cpu.c b/arch/arm/mach-exynos/cpu.c
deleted file mode 100644
index 90ec247f3b3..00000000000
--- a/arch/arm/mach-exynos/cpu.c
+++ /dev/null
@@ -1,298 +0,0 @@
1/* linux/arch/arm/mach-exynos/cpu.c
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/sched.h>
12#include <linux/sysdev.h>
13
14#include <asm/mach/map.h>
15#include <asm/mach/irq.h>
16
17#include <asm/proc-fns.h>
18#include <asm/hardware/cache-l2x0.h>
19#include <asm/hardware/gic.h>
20
21#include <plat/cpu.h>
22#include <plat/clock.h>
23#include <plat/devs.h>
24#include <plat/exynos4.h>
25#include <plat/adc-core.h>
26#include <plat/sdhci.h>
27#include <plat/fb-core.h>
28#include <plat/fimc-core.h>
29#include <plat/iic-core.h>
30#include <plat/reset.h>
31#include <plat/tv-core.h>
32
33#include <mach/regs-irq.h>
34#include <mach/regs-pmu.h>
35
36unsigned int gic_bank_offset __read_mostly;
37
38extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
39 unsigned int irq_start);
40extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
41
42/* Initial IO mappings */
43static struct map_desc exynos_iodesc[] __initdata = {
44 {
45 .virtual = (unsigned long)S5P_VA_SYSTIMER,
46 .pfn = __phys_to_pfn(EXYNOS_PA_SYSTIMER),
47 .length = SZ_4K,
48 .type = MT_DEVICE,
49 }, {
50 .virtual = (unsigned long)S5P_VA_PMU,
51 .pfn = __phys_to_pfn(EXYNOS_PA_PMU),
52 .length = SZ_64K,
53 .type = MT_DEVICE,
54 }, {
55 .virtual = (unsigned long)S5P_VA_COMBINER_BASE,
56 .pfn = __phys_to_pfn(EXYNOS_PA_COMBINER),
57 .length = SZ_4K,
58 .type = MT_DEVICE,
59 }, {
60 .virtual = (unsigned long)S5P_VA_GIC_CPU,
61 .pfn = __phys_to_pfn(EXYNOS_PA_GIC_CPU),
62 .length = SZ_64K,
63 .type = MT_DEVICE,
64 }, {
65 .virtual = (unsigned long)S5P_VA_GIC_DIST,
66 .pfn = __phys_to_pfn(EXYNOS_PA_GIC_DIST),
67 .length = SZ_64K,
68 .type = MT_DEVICE,
69 }, {
70 .virtual = (unsigned long)S3C_VA_UART,
71 .pfn = __phys_to_pfn(S3C_PA_UART),
72 .length = SZ_512K,
73 .type = MT_DEVICE,
74 },
75};
76
77static struct map_desc exynos4_iodesc[] __initdata = {
78 {
79 .virtual = (unsigned long)S5P_VA_CMU,
80 .pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
81 .length = SZ_128K,
82 .type = MT_DEVICE,
83 }, {
84 .virtual = (unsigned long)S5P_VA_COREPERI_BASE,
85 .pfn = __phys_to_pfn(EXYNOS4_PA_COREPERI),
86 .length = SZ_8K,
87 .type = MT_DEVICE,
88 }, {
89 .virtual = (unsigned long)S5P_VA_L2CC,
90 .pfn = __phys_to_pfn(EXYNOS4_PA_L2CC),
91 .length = SZ_4K,
92 .type = MT_DEVICE,
93 }, {
94 .virtual = (unsigned long)S5P_VA_GPIO1,
95 .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO1),
96 .length = SZ_4K,
97 .type = MT_DEVICE,
98 }, {
99 .virtual = (unsigned long)S5P_VA_GPIO2,
100 .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO2),
101 .length = SZ_4K,
102 .type = MT_DEVICE,
103 }, {
104 .virtual = (unsigned long)S5P_VA_GPIO3,
105 .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO3),
106 .length = SZ_256,
107 .type = MT_DEVICE,
108 }, {
109 .virtual = (unsigned long)S5P_VA_DMC0,
110 .pfn = __phys_to_pfn(EXYNOS4_PA_DMC0),
111 .length = SZ_4K,
112 .type = MT_DEVICE,
113 }, {
114 .virtual = (unsigned long)S5P_VA_SROMC,
115 .pfn = __phys_to_pfn(EXYNOS4_PA_SROMC),
116 .length = SZ_4K,
117 .type = MT_DEVICE,
118 }, {
119 .virtual = (unsigned long)S3C_VA_USB_HSPHY,
120 .pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY),
121 .length = SZ_4K,
122 .type = MT_DEVICE,
123 },
124};
125
126static struct map_desc exynos4_iodesc0[] __initdata = {
127 {
128 .virtual = (unsigned long)S5P_VA_SYSRAM,
129 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
130 .length = SZ_4K,
131 .type = MT_DEVICE,
132 },
133};
134
135static struct map_desc exynos4_iodesc1[] __initdata = {
136 {
137 .virtual = (unsigned long)S5P_VA_SYSRAM,
138 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
139 .length = SZ_4K,
140 .type = MT_DEVICE,
141 },
142};
143
144static void exynos_idle(void)
145{
146 if (!need_resched())
147 cpu_do_idle();
148
149 local_irq_enable();
150}
151
152static void exynos4_sw_reset(void)
153{
154 __raw_writel(0x1, S5P_SWRESET);
155}
156
157/*
158 * exynos_map_io
159 *
160 * register the standard cpu IO areas
161 */
162void __init exynos4_map_io(void)
163{
164 iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));
165 iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
166
167 if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
168 iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
169 else
170 iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
171
172 /* initialize device information early */
173 exynos4_default_sdhci0();
174 exynos4_default_sdhci1();
175 exynos4_default_sdhci2();
176 exynos4_default_sdhci3();
177
178 s3c_adc_setname("samsung-adc-v3");
179
180 s3c_fimc_setname(0, "exynos4-fimc");
181 s3c_fimc_setname(1, "exynos4-fimc");
182 s3c_fimc_setname(2, "exynos4-fimc");
183 s3c_fimc_setname(3, "exynos4-fimc");
184
185 /* The I2C bus controllers are directly compatible with s3c2440 */
186 s3c_i2c0_setname("s3c2440-i2c");
187 s3c_i2c1_setname("s3c2440-i2c");
188 s3c_i2c2_setname("s3c2440-i2c");
189
190 s5p_fb_setname(0, "exynos4-fb");
191 s5p_hdmi_setname("exynos4-hdmi");
192}
193
194void __init exynos4_init_clocks(int xtal)
195{
196 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
197
198 s3c24xx_register_baseclocks(xtal);
199 s5p_register_clocks(xtal);
200
201 if (soc_is_exynos4210())
202 exynos4210_register_clocks();
203 else if (soc_is_exynos4212() || soc_is_exynos4412())
204 exynos4212_register_clocks();
205
206 exynos4_register_clocks();
207 exynos4_setup_clocks();
208}
209
210static void exynos4_gic_irq_fix_base(struct irq_data *d)
211{
212 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
213
214 gic_data->cpu_base = S5P_VA_GIC_CPU +
215 (gic_bank_offset * smp_processor_id());
216
217 gic_data->dist_base = S5P_VA_GIC_DIST +
218 (gic_bank_offset * smp_processor_id());
219}
220
221void __init exynos4_init_irq(void)
222{
223 int irq;
224
225 gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
226
227 gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
228 gic_arch_extn.irq_eoi = exynos4_gic_irq_fix_base;
229 gic_arch_extn.irq_unmask = exynos4_gic_irq_fix_base;
230 gic_arch_extn.irq_mask = exynos4_gic_irq_fix_base;
231
232 for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
233
234 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
235 COMBINER_IRQ(irq, 0));
236 combiner_cascade_irq(irq, IRQ_SPI(irq));
237 }
238
239 /* The parameters of s5p_init_irq() are for VIC init.
240 * Theses parameters should be NULL and 0 because EXYNOS4
241 * uses GIC instead of VIC.
242 */
243 s5p_init_irq(NULL, 0);
244}
245
246struct sysdev_class exynos4_sysclass = {
247 .name = "exynos4-core",
248};
249
250static struct sys_device exynos4_sysdev = {
251 .cls = &exynos4_sysclass,
252};
253
254static int __init exynos4_core_init(void)
255{
256 return sysdev_class_register(&exynos4_sysclass);
257}
258core_initcall(exynos4_core_init);
259
260#ifdef CONFIG_CACHE_L2X0
261static int __init exynos4_l2x0_cache_init(void)
262{
263 /* TAG, Data Latency Control: 2cycle */
264 __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
265
266 if (soc_is_exynos4210())
267 __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
268 else if (soc_is_exynos4212() || soc_is_exynos4412())
269 __raw_writel(0x120, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
270
271 /* L2X0 Prefetch Control */
272 __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
273
274 /* L2X0 Power Control */
275 __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
276 S5P_VA_L2CC + L2X0_POWER_CTRL);
277
278 l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);
279
280 return 0;
281}
282
283early_initcall(exynos4_l2x0_cache_init);
284#endif
285
286int __init exynos_init(void)
287{
288 printk(KERN_INFO "EXYNOS: Initializing architecture\n");
289
290 /* set idle function */
291 pm_idle = exynos_idle;
292
293 /* set sw_reset function */
294 if (soc_is_exynos4210() || soc_is_exynos4212() || soc_is_exynos4412())
295 s5p_reset_hook = exynos4_sw_reset;
296
297 return sysdev_register(&exynos4_sysdev);
298}
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 058541d45af..d1829860a0e 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -149,7 +149,6 @@
149#define S3C_PA_WDT EXYNOS4_PA_WATCHDOG 149#define S3C_PA_WDT EXYNOS4_PA_WATCHDOG
150#define S3C_PA_UART EXYNOS4_PA_UART 150#define S3C_PA_UART EXYNOS4_PA_UART
151 151
152#define S5P_PA_CHIPID EXYNOS4_PA_CHIPID
153#define S5P_PA_EHCI EXYNOS4_PA_EHCI 152#define S5P_PA_EHCI EXYNOS4_PA_EHCI
154#define S5P_PA_FIMC0 EXYNOS4_PA_FIMC0 153#define S5P_PA_FIMC0 EXYNOS4_PA_FIMC0
155#define S5P_PA_FIMC1 EXYNOS4_PA_FIMC1 154#define S5P_PA_FIMC1 EXYNOS4_PA_FIMC1
@@ -166,26 +165,17 @@
166#define S5P_PA_ONENAND_DMA EXYNOS4_PA_ONENAND_DMA 165#define S5P_PA_ONENAND_DMA EXYNOS4_PA_ONENAND_DMA
167#define S5P_PA_SDO EXYNOS4_PA_SDO 166#define S5P_PA_SDO EXYNOS4_PA_SDO
168#define S5P_PA_SDRAM EXYNOS4_PA_SDRAM 167#define S5P_PA_SDRAM EXYNOS4_PA_SDRAM
169#define S5P_PA_SROMC EXYNOS4_PA_SROMC
170#define S5P_PA_SYSCON EXYNOS4_PA_SYSCON
171#define S5P_PA_TIMER EXYNOS4_PA_TIMER
172#define S5P_PA_VP EXYNOS4_PA_VP 168#define S5P_PA_VP EXYNOS4_PA_VP
173 169
174#define SAMSUNG_PA_ADC EXYNOS4_PA_ADC 170#define SAMSUNG_PA_ADC EXYNOS4_PA_ADC
175#define SAMSUNG_PA_ADC1 EXYNOS4_PA_ADC1 171#define SAMSUNG_PA_ADC1 EXYNOS4_PA_ADC1
176#define SAMSUNG_PA_KEYPAD EXYNOS4_PA_KEYPAD 172#define SAMSUNG_PA_KEYPAD EXYNOS4_PA_KEYPAD
177 173
178#define EXYNOS_PA_COMBINER EXYNOS4_PA_COMBINER
179#define EXYNOS_PA_GIC_CPU EXYNOS4_PA_GIC_CPU
180#define EXYNOS_PA_GIC_DIST EXYNOS4_PA_GIC_DIST
181#define EXYNOS_PA_PMU EXYNOS4_PA_PMU
182#define EXYNOS_PA_SYSTIMER EXYNOS4_PA_SYSTIMER
183
184/* Compatibility UART */ 174/* Compatibility UART */
185 175
186#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET)) 176#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
187 177
188#define S5P_PA_UART(x) (S3C_PA_UART + ((x) * S3C_UART_OFFSET)) 178#define S5P_PA_UART(x) (EXYNOS4_PA_UART + ((x) * S3C_UART_OFFSET))
189#define S5P_PA_UART0 S5P_PA_UART(0) 179#define S5P_PA_UART0 S5P_PA_UART(0)
190#define S5P_PA_UART1 S5P_PA_UART(1) 180#define S5P_PA_UART1 S5P_PA_UART(1)
191#define S5P_PA_UART2 S5P_PA_UART(2) 181#define S5P_PA_UART2 S5P_PA_UART(2)
diff --git a/arch/arm/mach-exynos/init.c b/arch/arm/mach-exynos/init.c
deleted file mode 100644
index a8a83e3881a..00000000000
--- a/arch/arm/mach-exynos/init.c
+++ /dev/null
@@ -1,42 +0,0 @@
1/* linux/arch/arm/mach-exynos4/init.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/serial_core.h>
12
13#include <plat/cpu.h>
14#include <plat/devs.h>
15#include <plat/regs-serial.h>
16
17static struct s3c24xx_uart_clksrc exynos4_serial_clocks[] = {
18 [0] = {
19 .name = "uclk1",
20 .divisor = 1,
21 .min_baud = 0,
22 .max_baud = 0,
23 },
24};
25
26/* uart registration process */
27void __init exynos4_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
28{
29 struct s3c2410_uartcfg *tcfg = cfg;
30 u32 ucnt;
31
32 for (ucnt = 0; ucnt < no; ucnt++, tcfg++) {
33 if (!tcfg->clocks) {
34 tcfg->has_fracval = 1;
35 tcfg->clocks = exynos4_serial_clocks;
36 tcfg->clocks_size = ARRAY_SIZE(exynos4_serial_clocks);
37 }
38 tcfg->flags |= NO_NEED_CHECK_CLKSRC;
39 }
40
41 s3c24xx_init_uartdevs("s5pv210-uart", s5p_uart_resources, cfg, no);
42}
diff --git a/arch/arm/mach-exynos/irq-combiner.c b/arch/arm/mach-exynos/irq-combiner.c
deleted file mode 100644
index 5a2758ab055..00000000000
--- a/arch/arm/mach-exynos/irq-combiner.c
+++ /dev/null
@@ -1,124 +0,0 @@
1/* linux/arch/arm/mach-exynos4/irq-combiner.c
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Based on arch/arm/common/gic.c
7 *
8 * IRQ COMBINER support
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/io.h>
16
17#include <asm/mach/irq.h>
18
19#define COMBINER_ENABLE_SET 0x0
20#define COMBINER_ENABLE_CLEAR 0x4
21#define COMBINER_INT_STATUS 0xC
22
23static DEFINE_SPINLOCK(irq_controller_lock);
24
25struct combiner_chip_data {
26 unsigned int irq_offset;
27 unsigned int irq_mask;
28 void __iomem *base;
29};
30
31static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
32
33static inline void __iomem *combiner_base(struct irq_data *data)
34{
35 struct combiner_chip_data *combiner_data =
36 irq_data_get_irq_chip_data(data);
37
38 return combiner_data->base;
39}
40
41static void combiner_mask_irq(struct irq_data *data)
42{
43 u32 mask = 1 << (data->irq % 32);
44
45 __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
46}
47
48static void combiner_unmask_irq(struct irq_data *data)
49{
50 u32 mask = 1 << (data->irq % 32);
51
52 __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
53}
54
55static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
56{
57 struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
58 struct irq_chip *chip = irq_get_chip(irq);
59 unsigned int cascade_irq, combiner_irq;
60 unsigned long status;
61
62 chained_irq_enter(chip, desc);
63
64 spin_lock(&irq_controller_lock);
65 status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
66 spin_unlock(&irq_controller_lock);
67 status &= chip_data->irq_mask;
68
69 if (status == 0)
70 goto out;
71
72 combiner_irq = __ffs(status);
73
74 cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
75 if (unlikely(cascade_irq >= NR_IRQS))
76 do_bad_IRQ(cascade_irq, desc);
77 else
78 generic_handle_irq(cascade_irq);
79
80 out:
81 chained_irq_exit(chip, desc);
82}
83
84static struct irq_chip combiner_chip = {
85 .name = "COMBINER",
86 .irq_mask = combiner_mask_irq,
87 .irq_unmask = combiner_unmask_irq,
88};
89
90void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
91{
92 if (combiner_nr >= MAX_COMBINER_NR)
93 BUG();
94 if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
95 BUG();
96 irq_set_chained_handler(irq, combiner_handle_cascade_irq);
97}
98
99void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
100 unsigned int irq_start)
101{
102 unsigned int i;
103
104 if (combiner_nr >= MAX_COMBINER_NR)
105 BUG();
106
107 combiner_data[combiner_nr].base = base;
108 combiner_data[combiner_nr].irq_offset = irq_start;
109 combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
110
111 /* Disable all interrupts */
112
113 __raw_writel(combiner_data[combiner_nr].irq_mask,
114 base + COMBINER_ENABLE_CLEAR);
115
116 /* Setup the Linux IRQ subsystem */
117
118 for (i = irq_start; i < combiner_data[combiner_nr].irq_offset
119 + MAX_IRQ_IN_COMBINER; i++) {
120 irq_set_chip_and_handler(i, &combiner_chip, handle_level_irq);
121 irq_set_chip_data(i, &combiner_data[combiner_nr]);
122 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
123 }
124}
diff --git a/arch/arm/mach-exynos/irq-eint.c b/arch/arm/mach-exynos/irq-eint.c
deleted file mode 100644
index badb8c66fc9..00000000000
--- a/arch/arm/mach-exynos/irq-eint.c
+++ /dev/null
@@ -1,237 +0,0 @@
1/* linux/arch/arm/mach-exynos4/irq-eint.c
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 - IRQ EINT support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/interrupt.h>
15#include <linux/irq.h>
16#include <linux/io.h>
17#include <linux/sysdev.h>
18#include <linux/gpio.h>
19
20#include <plat/pm.h>
21#include <plat/cpu.h>
22#include <plat/gpio-cfg.h>
23
24#include <mach/regs-gpio.h>
25
26#include <asm/mach/irq.h>
27
28static DEFINE_SPINLOCK(eint_lock);
29
30static unsigned int eint0_15_data[16];
31
32static unsigned int exynos4_get_irq_nr(unsigned int number)
33{
34 u32 ret = 0;
35
36 switch (number) {
37 case 0 ... 3:
38 ret = (number + IRQ_EINT0);
39 break;
40 case 4 ... 7:
41 ret = (number + (IRQ_EINT4 - 4));
42 break;
43 case 8 ... 15:
44 ret = (number + (IRQ_EINT8 - 8));
45 break;
46 default:
47 printk(KERN_ERR "number available : %d\n", number);
48 }
49
50 return ret;
51}
52
53static inline void exynos4_irq_eint_mask(struct irq_data *data)
54{
55 u32 mask;
56
57 spin_lock(&eint_lock);
58 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
59 mask |= eint_irq_to_bit(data->irq);
60 __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
61 spin_unlock(&eint_lock);
62}
63
64static void exynos4_irq_eint_unmask(struct irq_data *data)
65{
66 u32 mask;
67
68 spin_lock(&eint_lock);
69 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
70 mask &= ~(eint_irq_to_bit(data->irq));
71 __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
72 spin_unlock(&eint_lock);
73}
74
75static inline void exynos4_irq_eint_ack(struct irq_data *data)
76{
77 __raw_writel(eint_irq_to_bit(data->irq),
78 S5P_EINT_PEND(EINT_REG_NR(data->irq)));
79}
80
81static void exynos4_irq_eint_maskack(struct irq_data *data)
82{
83 exynos4_irq_eint_mask(data);
84 exynos4_irq_eint_ack(data);
85}
86
87static int exynos4_irq_eint_set_type(struct irq_data *data, unsigned int type)
88{
89 int offs = EINT_OFFSET(data->irq);
90 int shift;
91 u32 ctrl, mask;
92 u32 newvalue = 0;
93
94 switch (type) {
95 case IRQ_TYPE_EDGE_RISING:
96 newvalue = S5P_IRQ_TYPE_EDGE_RISING;
97 break;
98
99 case IRQ_TYPE_EDGE_FALLING:
100 newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
101 break;
102
103 case IRQ_TYPE_EDGE_BOTH:
104 newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
105 break;
106
107 case IRQ_TYPE_LEVEL_LOW:
108 newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
109 break;
110
111 case IRQ_TYPE_LEVEL_HIGH:
112 newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
113 break;
114
115 default:
116 printk(KERN_ERR "No such irq type %d", type);
117 return -EINVAL;
118 }
119
120 shift = (offs & 0x7) * 4;
121 mask = 0x7 << shift;
122
123 spin_lock(&eint_lock);
124 ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq)));
125 ctrl &= ~mask;
126 ctrl |= newvalue << shift;
127 __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq)));
128 spin_unlock(&eint_lock);
129
130 switch (offs) {
131 case 0 ... 7:
132 s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE);
133 break;
134 case 8 ... 15:
135 s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE);
136 break;
137 case 16 ... 23:
138 s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE);
139 break;
140 case 24 ... 31:
141 s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE);
142 break;
143 default:
144 printk(KERN_ERR "No such irq number %d", offs);
145 }
146
147 return 0;
148}
149
150static struct irq_chip exynos4_irq_eint = {
151 .name = "exynos4-eint",
152 .irq_mask = exynos4_irq_eint_mask,
153 .irq_unmask = exynos4_irq_eint_unmask,
154 .irq_mask_ack = exynos4_irq_eint_maskack,
155 .irq_ack = exynos4_irq_eint_ack,
156 .irq_set_type = exynos4_irq_eint_set_type,
157#ifdef CONFIG_PM
158 .irq_set_wake = s3c_irqext_wake,
159#endif
160};
161
162/* exynos4_irq_demux_eint
163 *
164 * This function demuxes the IRQ from from EINTs 16 to 31.
165 * It is designed to be inlined into the specific handler
166 * s5p_irq_demux_eintX_Y.
167 *
168 * Each EINT pend/mask registers handle eight of them.
169 */
170static inline void exynos4_irq_demux_eint(unsigned int start)
171{
172 unsigned int irq;
173
174 u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start)));
175 u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start)));
176
177 status &= ~mask;
178 status &= 0xff;
179
180 while (status) {
181 irq = fls(status) - 1;
182 generic_handle_irq(irq + start);
183 status &= ~(1 << irq);
184 }
185}
186
187static void exynos4_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
188{
189 struct irq_chip *chip = irq_get_chip(irq);
190 chained_irq_enter(chip, desc);
191 exynos4_irq_demux_eint(IRQ_EINT(16));
192 exynos4_irq_demux_eint(IRQ_EINT(24));
193 chained_irq_exit(chip, desc);
194}
195
196static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
197{
198 u32 *irq_data = irq_get_handler_data(irq);
199 struct irq_chip *chip = irq_get_chip(irq);
200
201 chained_irq_enter(chip, desc);
202 chip->irq_mask(&desc->irq_data);
203
204 if (chip->irq_ack)
205 chip->irq_ack(&desc->irq_data);
206
207 generic_handle_irq(*irq_data);
208
209 chip->irq_unmask(&desc->irq_data);
210 chained_irq_exit(chip, desc);
211}
212
213int __init exynos4_init_irq_eint(void)
214{
215 int irq;
216
217 for (irq = 0 ; irq <= 31 ; irq++) {
218 irq_set_chip_and_handler(IRQ_EINT(irq), &exynos4_irq_eint,
219 handle_level_irq);
220 set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
221 }
222
223 irq_set_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31);
224
225 for (irq = 0 ; irq <= 15 ; irq++) {
226 eint0_15_data[irq] = IRQ_EINT(irq);
227
228 irq_set_handler_data(exynos4_get_irq_nr(irq),
229 &eint0_15_data[irq]);
230 irq_set_chained_handler(exynos4_get_irq_nr(irq),
231 exynos4_irq_eint0_15);
232 }
233
234 return 0;
235}
236
237arch_initcall(exynos4_init_irq_eint);
diff --git a/arch/arm/mach-exynos/mach-armlex4210.c b/arch/arm/mach-exynos/mach-armlex4210.c
index f0ca6c157d2..eeba808625a 100644
--- a/arch/arm/mach-exynos/mach-armlex4210.c
+++ b/arch/arm/mach-exynos/mach-armlex4210.c
@@ -20,7 +20,6 @@
20 20
21#include <plat/cpu.h> 21#include <plat/cpu.h>
22#include <plat/devs.h> 22#include <plat/devs.h>
23#include <plat/exynos4.h>
24#include <plat/gpio-cfg.h> 23#include <plat/gpio-cfg.h>
25#include <plat/regs-serial.h> 24#include <plat/regs-serial.h>
26#include <plat/regs-srom.h> 25#include <plat/regs-srom.h>
@@ -28,6 +27,8 @@
28 27
29#include <mach/map.h> 28#include <mach/map.h>
30 29
30#include "common.h"
31
31/* Following are default values for UCON, ULCON and UFCON UART registers */ 32/* Following are default values for UCON, ULCON and UFCON UART registers */
32#define ARMLEX4210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 33#define ARMLEX4210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
33 S3C2410_UCON_RXILEVEL | \ 34 S3C2410_UCON_RXILEVEL | \
@@ -187,7 +188,7 @@ static void __init armlex4210_smsc911x_init(void)
187 188
188static void __init armlex4210_map_io(void) 189static void __init armlex4210_map_io(void)
189{ 190{
190 s5p_init_io(NULL, 0, S5P_VA_CHIPID); 191 exynos_init_io(NULL, 0);
191 s3c24xx_init_clocks(24000000); 192 s3c24xx_init_clocks(24000000);
192 s3c24xx_init_uarts(armlex4210_uartcfgs, 193 s3c24xx_init_uarts(armlex4210_uartcfgs,
193 ARRAY_SIZE(armlex4210_uartcfgs)); 194 ARRAY_SIZE(armlex4210_uartcfgs));
diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
index 236bbe18716..97cd5af1505 100644
--- a/arch/arm/mach-exynos/mach-nuri.c
+++ b/arch/arm/mach-exynos/mach-nuri.c
@@ -37,7 +37,6 @@
37#include <plat/adc.h> 37#include <plat/adc.h>
38#include <plat/regs-fb-v4.h> 38#include <plat/regs-fb-v4.h>
39#include <plat/regs-serial.h> 39#include <plat/regs-serial.h>
40#include <plat/exynos4.h>
41#include <plat/cpu.h> 40#include <plat/cpu.h>
42#include <plat/devs.h> 41#include <plat/devs.h>
43#include <plat/fb.h> 42#include <plat/fb.h>
@@ -54,6 +53,8 @@
54 53
55#include <mach/map.h> 54#include <mach/map.h>
56 55
56#include "common.h"
57
57/* Following are default values for UCON, ULCON and UFCON UART registers */ 58/* Following are default values for UCON, ULCON and UFCON UART registers */
58#define NURI_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 59#define NURI_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
59 S3C2410_UCON_RXILEVEL | \ 60 S3C2410_UCON_RXILEVEL | \
@@ -1283,7 +1284,7 @@ static struct platform_device *nuri_devices[] __initdata = {
1283 1284
1284static void __init nuri_map_io(void) 1285static void __init nuri_map_io(void)
1285{ 1286{
1286 s5p_init_io(NULL, 0, S5P_VA_CHIPID); 1287 exynos_init_io(NULL, 0);
1287 s3c24xx_init_clocks(24000000); 1288 s3c24xx_init_clocks(24000000);
1288 s3c24xx_init_uarts(nuri_uartcfgs, ARRAY_SIZE(nuri_uartcfgs)); 1289 s3c24xx_init_uarts(nuri_uartcfgs, ARRAY_SIZE(nuri_uartcfgs));
1289} 1290}
diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c
index f80b563f2be..cc2c6708276 100644
--- a/arch/arm/mach-exynos/mach-origen.c
+++ b/arch/arm/mach-exynos/mach-origen.c
@@ -28,7 +28,6 @@
28 28
29#include <plat/regs-serial.h> 29#include <plat/regs-serial.h>
30#include <plat/regs-fb-v4.h> 30#include <plat/regs-fb-v4.h>
31#include <plat/exynos4.h>
32#include <plat/cpu.h> 31#include <plat/cpu.h>
33#include <plat/devs.h> 32#include <plat/devs.h>
34#include <plat/sdhci.h> 33#include <plat/sdhci.h>
@@ -43,6 +42,8 @@
43 42
44#include <mach/map.h> 43#include <mach/map.h>
45 44
45#include "common.h"
46
46/* Following are default values for UCON, ULCON and UFCON UART registers */ 47/* Following are default values for UCON, ULCON and UFCON UART registers */
47#define ORIGEN_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 48#define ORIGEN_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
48 S3C2410_UCON_RXILEVEL | \ 49 S3C2410_UCON_RXILEVEL | \
@@ -638,7 +639,7 @@ static void s5p_tv_setup(void)
638 639
639static void __init origen_map_io(void) 640static void __init origen_map_io(void)
640{ 641{
641 s5p_init_io(NULL, 0, S5P_VA_CHIPID); 642 exynos_init_io(NULL, 0);
642 s3c24xx_init_clocks(24000000); 643 s3c24xx_init_clocks(24000000);
643 s3c24xx_init_uarts(origen_uartcfgs, ARRAY_SIZE(origen_uartcfgs)); 644 s3c24xx_init_uarts(origen_uartcfgs, ARRAY_SIZE(origen_uartcfgs));
644} 645}
diff --git a/arch/arm/mach-exynos/mach-smdk4x12.c b/arch/arm/mach-exynos/mach-smdk4x12.c
index fcf2e0e23d5..2f4cb89aadb 100644
--- a/arch/arm/mach-exynos/mach-smdk4x12.c
+++ b/arch/arm/mach-exynos/mach-smdk4x12.c
@@ -27,7 +27,6 @@
27#include <plat/clock.h> 27#include <plat/clock.h>
28#include <plat/cpu.h> 28#include <plat/cpu.h>
29#include <plat/devs.h> 29#include <plat/devs.h>
30#include <plat/exynos4.h>
31#include <plat/gpio-cfg.h> 30#include <plat/gpio-cfg.h>
32#include <plat/iic.h> 31#include <plat/iic.h>
33#include <plat/keypad.h> 32#include <plat/keypad.h>
@@ -36,6 +35,8 @@
36 35
37#include <mach/map.h> 36#include <mach/map.h>
38 37
38#include "common.h"
39
39/* Following are default values for UCON, ULCON and UFCON UART registers */ 40/* Following are default values for UCON, ULCON and UFCON UART registers */
40#define SMDK4X12_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 41#define SMDK4X12_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
41 S3C2410_UCON_RXILEVEL | \ 42 S3C2410_UCON_RXILEVEL | \
@@ -249,7 +250,7 @@ static void __init smdk4x12_map_io(void)
249{ 250{
250 clk_xusbxti.rate = 24000000; 251 clk_xusbxti.rate = 24000000;
251 252
252 s5p_init_io(NULL, 0, S5P_VA_CHIPID); 253 exynos_init_io(NULL, 0);
253 s3c24xx_init_clocks(clk_xusbxti.rate); 254 s3c24xx_init_clocks(clk_xusbxti.rate);
254 s3c24xx_init_uarts(smdk4x12_uartcfgs, ARRAY_SIZE(smdk4x12_uartcfgs)); 255 s3c24xx_init_uarts(smdk4x12_uartcfgs, ARRAY_SIZE(smdk4x12_uartcfgs));
255} 256}
diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c
index cec2afabe7b..cf21d666d12 100644
--- a/arch/arm/mach-exynos/mach-smdkv310.c
+++ b/arch/arm/mach-exynos/mach-smdkv310.c
@@ -27,7 +27,6 @@
27#include <plat/regs-serial.h> 27#include <plat/regs-serial.h>
28#include <plat/regs-srom.h> 28#include <plat/regs-srom.h>
29#include <plat/regs-fb-v4.h> 29#include <plat/regs-fb-v4.h>
30#include <plat/exynos4.h>
31#include <plat/cpu.h> 30#include <plat/cpu.h>
32#include <plat/devs.h> 31#include <plat/devs.h>
33#include <plat/fb.h> 32#include <plat/fb.h>
@@ -43,6 +42,8 @@
43 42
44#include <mach/map.h> 43#include <mach/map.h>
45 44
45#include "common.h"
46
46/* Following are default values for UCON, ULCON and UFCON UART registers */ 47/* Following are default values for UCON, ULCON and UFCON UART registers */
47#define SMDKV310_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 48#define SMDKV310_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
48 S3C2410_UCON_RXILEVEL | \ 49 S3C2410_UCON_RXILEVEL | \
@@ -332,7 +333,7 @@ static void s5p_tv_setup(void)
332 333
333static void __init smdkv310_map_io(void) 334static void __init smdkv310_map_io(void)
334{ 335{
335 s5p_init_io(NULL, 0, S5P_VA_CHIPID); 336 exynos_init_io(NULL, 0);
336 s3c24xx_init_clocks(24000000); 337 s3c24xx_init_clocks(24000000);
337 s3c24xx_init_uarts(smdkv310_uartcfgs, ARRAY_SIZE(smdkv310_uartcfgs)); 338 s3c24xx_init_uarts(smdkv310_uartcfgs, ARRAY_SIZE(smdkv310_uartcfgs));
338} 339}
diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
index a2a177ff4b4..4826eabf9be 100644
--- a/arch/arm/mach-exynos/mach-universal_c210.c
+++ b/arch/arm/mach-exynos/mach-universal_c210.c
@@ -27,7 +27,6 @@
27#include <asm/mach-types.h> 27#include <asm/mach-types.h>
28 28
29#include <plat/regs-serial.h> 29#include <plat/regs-serial.h>
30#include <plat/exynos4.h>
31#include <plat/cpu.h> 30#include <plat/cpu.h>
32#include <plat/devs.h> 31#include <plat/devs.h>
33#include <plat/iic.h> 32#include <plat/iic.h>
@@ -47,6 +46,8 @@
47#include <media/s5p_fimc.h> 46#include <media/s5p_fimc.h>
48#include <media/m5mols.h> 47#include <media/m5mols.h>
49 48
49#include "common.h"
50
50/* Following are default values for UCON, ULCON and UFCON UART registers */ 51/* Following are default values for UCON, ULCON and UFCON UART registers */
51#define UNIVERSAL_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 52#define UNIVERSAL_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
52 S3C2410_UCON_RXILEVEL | \ 53 S3C2410_UCON_RXILEVEL | \
@@ -992,7 +993,7 @@ static struct platform_device *universal_devices[] __initdata = {
992 993
993static void __init universal_map_io(void) 994static void __init universal_map_io(void)
994{ 995{
995 s5p_init_io(NULL, 0, S5P_VA_CHIPID); 996 exynos_init_io(NULL, 0);
996 s3c24xx_init_clocks(24000000); 997 s3c24xx_init_clocks(24000000);
997 s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs)); 998 s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
998} 999}
diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile
index 876344038b8..30d8c3016e6 100644
--- a/arch/arm/plat-s5p/Makefile
+++ b/arch/arm/plat-s5p/Makefile
@@ -13,7 +13,6 @@ obj- :=
13# Core files 13# Core files
14 14
15obj-y += dev-uart.o 15obj-y += dev-uart.o
16obj-y += cpu.o
17obj-y += clock.o 16obj-y += clock.o
18obj-y += irq.o 17obj-y += irq.o
19obj-$(CONFIG_S5P_EXT_INT) += irq-eint.o 18obj-$(CONFIG_S5P_EXT_INT) += irq-eint.o
diff --git a/arch/arm/plat-s5p/cpu.c b/arch/arm/plat-s5p/cpu.c
deleted file mode 100644
index 63c3fadf64e..00000000000
--- a/arch/arm/plat-s5p/cpu.c
+++ /dev/null
@@ -1,104 +0,0 @@
1/* linux/arch/arm/plat-s5p/cpu.c
2 *
3 * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P CPU Support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/init.h>
14#include <linux/module.h>
15
16#include <asm/mach/arch.h>
17#include <asm/mach/map.h>
18
19#include <mach/map.h>
20#include <mach/regs-clock.h>
21
22#include <plat/cpu.h>
23#include <plat/exynos4.h>
24
25/* table of supported CPUs */
26
27static const char name_exynos4210[] = "EXYNOS4210";
28static const char name_exynos4212[] = "EXYNOS4212";
29static const char name_exynos4412[] = "EXYNOS4412";
30
31static struct cpu_table cpu_ids[] __initdata = {
32 {
33 .idcode = EXYNOS4210_CPU_ID,
34 .idmask = EXYNOS4_CPU_MASK,
35 .map_io = exynos4_map_io,
36 .init_clocks = exynos4_init_clocks,
37 .init_uarts = exynos4_init_uarts,
38 .init = exynos_init,
39 .name = name_exynos4210,
40 }, {
41 .idcode = EXYNOS4212_CPU_ID,
42 .idmask = EXYNOS4_CPU_MASK,
43 .map_io = exynos4_map_io,
44 .init_clocks = exynos4_init_clocks,
45 .init_uarts = exynos4_init_uarts,
46 .init = exynos_init,
47 .name = name_exynos4212,
48 }, {
49 .idcode = EXYNOS4412_CPU_ID,
50 .idmask = EXYNOS4_CPU_MASK,
51 .map_io = exynos4_map_io,
52 .init_clocks = exynos4_init_clocks,
53 .init_uarts = exynos4_init_uarts,
54 .init = exynos_init,
55 .name = name_exynos4412,
56 },
57};
58
59/* minimal IO mapping */
60
61static struct map_desc s5p_iodesc[] __initdata = {
62 {
63 .virtual = (unsigned long)S5P_VA_CHIPID,
64 .pfn = __phys_to_pfn(S5P_PA_CHIPID),
65 .length = SZ_4K,
66 .type = MT_DEVICE,
67 }, {
68 .virtual = (unsigned long)S3C_VA_SYS,
69 .pfn = __phys_to_pfn(S5P_PA_SYSCON),
70 .length = SZ_64K,
71 .type = MT_DEVICE,
72 }, {
73 .virtual = (unsigned long)S3C_VA_TIMER,
74 .pfn = __phys_to_pfn(S5P_PA_TIMER),
75 .length = SZ_16K,
76 .type = MT_DEVICE,
77 }, {
78 .virtual = (unsigned long)S3C_VA_WATCHDOG,
79 .pfn = __phys_to_pfn(S3C_PA_WDT),
80 .length = SZ_4K,
81 .type = MT_DEVICE,
82 }, {
83 .virtual = (unsigned long)S5P_VA_SROMC,
84 .pfn = __phys_to_pfn(S5P_PA_SROMC),
85 .length = SZ_4K,
86 .type = MT_DEVICE,
87 },
88};
89
90/* read cpu identification code */
91
92void __init s5p_init_io(struct map_desc *mach_desc,
93 int size, void __iomem *cpuid_addr)
94{
95 /* initialize the io descriptors we need for initialization */
96 iotable_init(s5p_iodesc, ARRAY_SIZE(s5p_iodesc));
97 if (mach_desc)
98 iotable_init(mach_desc, size);
99
100 /* detect cpu id and rev. */
101 s5p_init_cpu(cpuid_addr);
102
103 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
104}
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index abbdadb4047..258d9d8a94f 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -155,8 +155,6 @@ extern void s3c24xx_init_irq(void);
155extern void s5p_init_irq(u32 *vic, u32 num_vic); 155extern void s5p_init_irq(u32 *vic, u32 num_vic);
156 156
157extern void s3c24xx_init_io(struct map_desc *mach_desc, int size); 157extern void s3c24xx_init_io(struct map_desc *mach_desc, int size);
158extern void s5p_init_io(struct map_desc *mach_desc,
159 int size, void __iomem *cpuid_addr);
160 158
161extern void s3c24xx_init_cpu(void); 159extern void s3c24xx_init_cpu(void);
162extern void s3c64xx_init_cpu(void); 160extern void s3c64xx_init_cpu(void);
diff --git a/arch/arm/plat-samsung/include/plat/exynos4.h b/arch/arm/plat-samsung/include/plat/exynos4.h
deleted file mode 100644
index f546e88ebc9..00000000000
--- a/arch/arm/plat-samsung/include/plat/exynos4.h
+++ /dev/null
@@ -1,35 +0,0 @@
1/* linux/arch/arm/plat-samsung/include/plat/exynos4.h
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Header file for exynos4 cpu support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13/* Common init code for EXYNOS4 related SoCs */
14
15extern void exynos4_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
16extern void exynos4_register_clocks(void);
17extern void exynos4210_register_clocks(void);
18extern void exynos4212_register_clocks(void);
19extern void exynos4_setup_clocks(void);
20
21#ifdef CONFIG_ARCH_EXYNOS
22extern int exynos_init(void);
23extern void exynos4_init_irq(void);
24extern void exynos4_map_io(void);
25extern void exynos4_init_clocks(int xtal);
26extern struct sys_timer exynos4_timer;
27
28#define exynos4_init_uarts exynos4_common_init_uarts
29
30#else
31#define exynos4_init_clocks NULL
32#define exynos4_init_uarts NULL
33#define exynos4_map_io NULL
34#define exynos_init NULL
35#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-21 11:30:27 -0400