1 files changed, 101 insertions, 37 deletions
diff --git a/drivers/staging/cxd2099/cxd2099.c b/drivers/staging/cxd2099/cxd2099.c
index 6ec30c1fd4c..39d21157a9b 100644
--- a/drivers/staging/cxd2099/cxd2099.c
+++ b/drivers/staging/cxd2099/cxd2099.c
@@ -294,8 +294,6 @@ static void cam_mode(struct cxd *ci, int mode)
-#define CHK_ERROR(s) if ((status = s)) break
 static int init(struct cxd *ci)
 {
        int status;
@@ -303,55 +301,121 @@ static int init(struct cxd *ci)
        mutex_lock(&ci->lock);
        ci->mode = -1;
        do {
-                CHK_ERROR(write_reg(ci, 0x00, 0x00));
+                status = write_reg(ci, 0x00, 0x00);
-                CHK_ERROR(write_reg(ci, 0x01, 0x00));
+                if (status < 0)
-                CHK_ERROR(write_reg(ci, 0x02, 0x10));
+                        break;
-                CHK_ERROR(write_reg(ci, 0x03, 0x00));
+                status = write_reg(ci, 0x01, 0x00);
-                CHK_ERROR(write_reg(ci, 0x05, 0xFF));
+                if (status < 0)
-                CHK_ERROR(write_reg(ci, 0x06, 0x1F));
+                        break;
-                CHK_ERROR(write_reg(ci, 0x07, 0x1F));
+                status = write_reg(ci, 0x02, 0x10);
-                CHK_ERROR(write_reg(ci, 0x08, 0x28));
+                if (status < 0)
-                CHK_ERROR(write_reg(ci, 0x14, 0x20));
+                        break;
+                status = write_reg(ci, 0x03, 0x00);
-                /* CHK_ERROR(write_reg(ci, 0x09, 0x4D));*/ /* Input Mode C, BYPass Serial, TIVAL = low, MSB */
+                if (status < 0)
-                CHK_ERROR(write_reg(ci, 0x0A, 0xA7)); /* TOSTRT = 8, Mode B (gated clock), falling Edge, Serial, POL=HIGH, MSB */
+                        break;
+                status = write_reg(ci, 0x05, 0xFF);
-                CHK_ERROR(write_reg(ci, 0x0B, 0x33));
+                if (status < 0)
-                CHK_ERROR(write_reg(ci, 0x0C, 0x33));
+                        break;
+                status = write_reg(ci, 0x06, 0x1F);
-                CHK_ERROR(write_regm(ci, 0x14, 0x00, 0x0F));
+                if (status < 0)
-                CHK_ERROR(write_reg(ci, 0x15, ci->clk_reg_b));
+                        break;
-                CHK_ERROR(write_regm(ci, 0x16, 0x00, 0x0F));
+                status = write_reg(ci, 0x07, 0x1F);
-                CHK_ERROR(write_reg(ci, 0x17, ci->clk_reg_f));
+                if (status < 0)
+                        break;
+                status = write_reg(ci, 0x08, 0x28);
+                if (status < 0)
+                        break;
+                status = write_reg(ci, 0x14, 0x20);
+                if (status < 0)
+                        break;
+#if 0
+                status = write_reg(ci, 0x09, 0x4D); /* Input Mode C, BYPass Serial, TIVAL = low, MSB */
+                if (status < 0)
+                        break;
+#endif
+                status = write_reg(ci, 0x0A, 0xA7); /* TOSTRT = 8, Mode B (gated clock), falling Edge, Serial, POL=HIGH, MSB */
+                if (status < 0)
+                        break;
+                status = write_reg(ci, 0x0B, 0x33);
+                if (status < 0)
+                        break;
+                status = write_reg(ci, 0x0C, 0x33);
+                if (status < 0)
+                        break;
+                status = write_regm(ci, 0x14, 0x00, 0x0F);
+                if (status < 0)
+                        break;
+                status = write_reg(ci, 0x15, ci->clk_reg_b);
+                if (status < 0)
+                        break;
+                status = write_regm(ci, 0x16, 0x00, 0x0F);
+                if (status < 0)
+                        break;
+                status = write_reg(ci, 0x17, ci->clk_reg_f);
+                if (status < 0)
+                        break;
                if (ci->cfg.clock_mode) {
                        if (ci->cfg.polarity) {
-                                CHK_ERROR(write_reg(ci, 0x09, 0x6f));
+                                status = write_reg(ci, 0x09, 0x6f);
+                                if (status < 0)
+                                        break;
                        } else {
-                                CHK_ERROR(write_reg(ci, 0x09, 0x6d));
+                                status = write_reg(ci, 0x09, 0x6d);
+                                if (status < 0)
+                                        break;
                        }
-                        CHK_ERROR(write_reg(ci, 0x20, 0x68));
+                        status = write_reg(ci, 0x20, 0x68);
-                        CHK_ERROR(write_reg(ci, 0x21, 0x00));
+                        if (status < 0)
-                        CHK_ERROR(write_reg(ci, 0x22, 0x02));
+                                break;
+                        status = write_reg(ci, 0x21, 0x00);
+                        if (status < 0)
+                                break;
+                        status = write_reg(ci, 0x22, 0x02);
+                        if (status < 0)
+                                break;
                } else {
                        if (ci->cfg.polarity) {
-                                CHK_ERROR(write_reg(ci, 0x09, 0x4f));
+                                status = write_reg(ci, 0x09, 0x4f);
+                                if (status < 0)
+                                        break;
                        } else {
-                                CHK_ERROR(write_reg(ci, 0x09, 0x4d));
+                                status = write_reg(ci, 0x09, 0x4d);
+                                if (status < 0)
+                                        break;
                        }
-                        CHK_ERROR(write_reg(ci, 0x20, 0x28));
+                        status = write_reg(ci, 0x20, 0x28);
-                        CHK_ERROR(write_reg(ci, 0x21, 0x00));
+                        if (status < 0)
-                        CHK_ERROR(write_reg(ci, 0x22, 0x07));
+                                break;
+                        status = write_reg(ci, 0x21, 0x00);
+                        if (status < 0)
+                                break;
+                        status = write_reg(ci, 0x22, 0x07);
+                        if (status < 0)
+                                break;
                }
-                CHK_ERROR(write_regm(ci, 0x20, 0x80, 0x80));
+                status = write_regm(ci, 0x20, 0x80, 0x80);
-                CHK_ERROR(write_regm(ci, 0x03, 0x02, 0x02));
+                if (status < 0)
-                CHK_ERROR(write_reg(ci, 0x01, 0x04));
+                        break;
-                CHK_ERROR(write_reg(ci, 0x00, 0x31));
+                status = write_regm(ci, 0x03, 0x02, 0x02);
+                if (status < 0)
+                        break;
+                status = write_reg(ci, 0x01, 0x04);
+                if (status < 0)
+                        break;
+                status = write_reg(ci, 0x00, 0x31);
+                if (status < 0)
+                        break;
                /* Put TS in bypass */
-                CHK_ERROR(write_regm(ci, 0x09, 0x08, 0x08));
+                status = write_regm(ci, 0x09, 0x08, 0x08);
+                if (status < 0)
+                        break;
                ci->cammode = -1;
                cam_mode(ci, 0);
        } while (0);

diff --git a/drivers/staging/cxd2099/cxd2099.c b/drivers/staging/cxd2099/cxd2099.c index 6ec30c1fd4c..39d21157a9b 100644 --- a/drivers/staging/cxd2099/cxd2099.c +++ b/drivers/staging/cxd2099/cxd2099.c
@@ -294,8 +294,6 @@ static void cam_mode(struct cxd *ci, int mode)
294		294
295		295
296		296
297	#define CHK_ERROR(s) if ((status = s)) break
298
299	static int init(struct cxd *ci)	297	static int init(struct cxd *ci)
300	{	298	{
301	int status;	299	int status;
@@ -303,55 +301,121 @@ static int init(struct cxd *ci)
303	mutex_lock(&ci->lock);	301	mutex_lock(&ci->lock);
304	ci->mode = -1;	302	ci->mode = -1;
305	do {	303	do {
306	CHK_ERROR(write_reg(ci, 0x00, 0x00));	304	status = write_reg(ci, 0x00, 0x00);
307	CHK_ERROR(write_reg(ci, 0x01, 0x00));	305	if (status < 0)
308	CHK_ERROR(write_reg(ci, 0x02, 0x10));	306	break;
309	CHK_ERROR(write_reg(ci, 0x03, 0x00));	307	status = write_reg(ci, 0x01, 0x00);
310	CHK_ERROR(write_reg(ci, 0x05, 0xFF));	308	if (status < 0)
311	CHK_ERROR(write_reg(ci, 0x06, 0x1F));	309	break;
312	CHK_ERROR(write_reg(ci, 0x07, 0x1F));	310	status = write_reg(ci, 0x02, 0x10);
313	CHK_ERROR(write_reg(ci, 0x08, 0x28));	311	if (status < 0)
314	CHK_ERROR(write_reg(ci, 0x14, 0x20));	312	break;
315		313	status = write_reg(ci, 0x03, 0x00);
316	/* CHK_ERROR(write_reg(ci, 0x09, 0x4D));/ / Input Mode C, BYPass Serial, TIVAL = low, MSB */	314	if (status < 0)
317	CHK_ERROR(write_reg(ci, 0x0A, 0xA7)); /* TOSTRT = 8, Mode B (gated clock), falling Edge, Serial, POL=HIGH, MSB */	315	break;
318		316	status = write_reg(ci, 0x05, 0xFF);
319	CHK_ERROR(write_reg(ci, 0x0B, 0x33));	317	if (status < 0)
320	CHK_ERROR(write_reg(ci, 0x0C, 0x33));	318	break;
321		319	status = write_reg(ci, 0x06, 0x1F);
322	CHK_ERROR(write_regm(ci, 0x14, 0x00, 0x0F));	320	if (status < 0)
323	CHK_ERROR(write_reg(ci, 0x15, ci->clk_reg_b));	321	break;
324	CHK_ERROR(write_regm(ci, 0x16, 0x00, 0x0F));	322	status = write_reg(ci, 0x07, 0x1F);
325	CHK_ERROR(write_reg(ci, 0x17, ci->clk_reg_f));	323	if (status < 0)
		324	break;
		325	status = write_reg(ci, 0x08, 0x28);
		326	if (status < 0)
		327	break;
		328	status = write_reg(ci, 0x14, 0x20);
		329	if (status < 0)
		330	break;
		331
		332	#if 0
		333	status = write_reg(ci, 0x09, 0x4D); /* Input Mode C, BYPass Serial, TIVAL = low, MSB */
		334	if (status < 0)
		335	break;
		336	#endif
		337	status = write_reg(ci, 0x0A, 0xA7); /* TOSTRT = 8, Mode B (gated clock), falling Edge, Serial, POL=HIGH, MSB */
		338	if (status < 0)
		339	break;
		340
		341	status = write_reg(ci, 0x0B, 0x33);
		342	if (status < 0)
		343	break;
		344	status = write_reg(ci, 0x0C, 0x33);
		345	if (status < 0)
		346	break;
		347
		348	status = write_regm(ci, 0x14, 0x00, 0x0F);
		349	if (status < 0)
		350	break;
		351	status = write_reg(ci, 0x15, ci->clk_reg_b);
		352	if (status < 0)
		353	break;
		354	status = write_regm(ci, 0x16, 0x00, 0x0F);
		355	if (status < 0)
		356	break;
		357	status = write_reg(ci, 0x17, ci->clk_reg_f);
		358	if (status < 0)
		359	break;
326		360
327	if (ci->cfg.clock_mode) {	361	if (ci->cfg.clock_mode) {
328	if (ci->cfg.polarity) {	362	if (ci->cfg.polarity) {
329	CHK_ERROR(write_reg(ci, 0x09, 0x6f));	363	status = write_reg(ci, 0x09, 0x6f);
		364	if (status < 0)
		365	break;
330	} else {	366	} else {
331	CHK_ERROR(write_reg(ci, 0x09, 0x6d));	367	status = write_reg(ci, 0x09, 0x6d);
		368	if (status < 0)
		369	break;
332	}	370	}
333	CHK_ERROR(write_reg(ci, 0x20, 0x68));	371	status = write_reg(ci, 0x20, 0x68);
334	CHK_ERROR(write_reg(ci, 0x21, 0x00));	372	if (status < 0)
335	CHK_ERROR(write_reg(ci, 0x22, 0x02));	373	break;
		374	status = write_reg(ci, 0x21, 0x00);
		375	if (status < 0)
		376	break;
		377	status = write_reg(ci, 0x22, 0x02);
		378	if (status < 0)
		379	break;
336	} else {	380	} else {
337	if (ci->cfg.polarity) {	381	if (ci->cfg.polarity) {
338	CHK_ERROR(write_reg(ci, 0x09, 0x4f));	382	status = write_reg(ci, 0x09, 0x4f);
		383	if (status < 0)
		384	break;
339	} else {	385	} else {
340	CHK_ERROR(write_reg(ci, 0x09, 0x4d));	386	status = write_reg(ci, 0x09, 0x4d);
		387	if (status < 0)
		388	break;
341	}	389	}
342		390
343	CHK_ERROR(write_reg(ci, 0x20, 0x28));	391	status = write_reg(ci, 0x20, 0x28);
344	CHK_ERROR(write_reg(ci, 0x21, 0x00));	392	if (status < 0)
345	CHK_ERROR(write_reg(ci, 0x22, 0x07));	393	break;
		394	status = write_reg(ci, 0x21, 0x00);
		395	if (status < 0)
		396	break;
		397	status = write_reg(ci, 0x22, 0x07);
		398	if (status < 0)
		399	break;
346	}	400	}
347		401
348	CHK_ERROR(write_regm(ci, 0x20, 0x80, 0x80));	402	status = write_regm(ci, 0x20, 0x80, 0x80);
349	CHK_ERROR(write_regm(ci, 0x03, 0x02, 0x02));	403	if (status < 0)
350	CHK_ERROR(write_reg(ci, 0x01, 0x04));	404	break;
351	CHK_ERROR(write_reg(ci, 0x00, 0x31));	405	status = write_regm(ci, 0x03, 0x02, 0x02);
		406	if (status < 0)
		407	break;
		408	status = write_reg(ci, 0x01, 0x04);
		409	if (status < 0)
		410	break;
		411	status = write_reg(ci, 0x00, 0x31);
		412	if (status < 0)
		413	break;
352		414
353	/* Put TS in bypass */	415	/* Put TS in bypass */
354	CHK_ERROR(write_regm(ci, 0x09, 0x08, 0x08));	416	status = write_regm(ci, 0x09, 0x08, 0x08);
		417	if (status < 0)
		418	break;
355	ci->cammode = -1;	419	ci->cammode = -1;
356	cam_mode(ci, 0);	420	cam_mode(ci, 0);
357	} while (0);	421	} while (0);