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-rw-r--r--drivers/usb/host/ehci-fsl.c11
-rw-r--r--drivers/usb/host/ehci-fsl.h1
2 files changed, 2 insertions, 10 deletions
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index c26a82e83f6..b556a72264d 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -239,7 +239,7 @@ static void ehci_fsl_setup_phy(struct ehci_hcd *ehci,
239 ehci_writel(ehci, portsc, &ehci->regs->port_status[port_offset]); 239 ehci_writel(ehci, portsc, &ehci->regs->port_status[port_offset]);
240} 240}
241 241
242static int ehci_fsl_usb_setup(struct ehci_hcd *ehci) 242static void ehci_fsl_usb_setup(struct ehci_hcd *ehci)
243{ 243{
244 struct usb_hcd *hcd = ehci_to_hcd(ehci); 244 struct usb_hcd *hcd = ehci_to_hcd(ehci);
245 struct fsl_usb2_platform_data *pdata; 245 struct fsl_usb2_platform_data *pdata;
@@ -299,19 +299,12 @@ static int ehci_fsl_usb_setup(struct ehci_hcd *ehci)
299#endif 299#endif
300 out_be32(non_ehci + FSL_SOC_USB_SICTRL, 0x00000001); 300 out_be32(non_ehci + FSL_SOC_USB_SICTRL, 0x00000001);
301 } 301 }
302
303 if (!(in_be32(non_ehci + FSL_SOC_USB_CTRL) & CTRL_PHY_CLK_VALID)) {
304 printk(KERN_WARNING "fsl-ehci: USB PHY clock invalid\n");
305 return -ENODEV;
306 }
307 return 0;
308} 302}
309 303
310/* called after powerup, by probe or system-pm "wakeup" */ 304/* called after powerup, by probe or system-pm "wakeup" */
311static int ehci_fsl_reinit(struct ehci_hcd *ehci) 305static int ehci_fsl_reinit(struct ehci_hcd *ehci)
312{ 306{
313 if (ehci_fsl_usb_setup(ehci)) 307 ehci_fsl_usb_setup(ehci);
314 return -ENODEV;
315 ehci_port_power(ehci, 0); 308 ehci_port_power(ehci, 0);
316 309
317 return 0; 310 return 0;
diff --git a/drivers/usb/host/ehci-fsl.h b/drivers/usb/host/ehci-fsl.h
index bdf43e2adc5..49180622116 100644
--- a/drivers/usb/host/ehci-fsl.h
+++ b/drivers/usb/host/ehci-fsl.h
@@ -45,6 +45,5 @@
45#define FSL_SOC_USB_PRICTRL 0x40c /* NOTE: big-endian */ 45#define FSL_SOC_USB_PRICTRL 0x40c /* NOTE: big-endian */
46#define FSL_SOC_USB_SICTRL 0x410 /* NOTE: big-endian */ 46#define FSL_SOC_USB_SICTRL 0x410 /* NOTE: big-endian */
47#define FSL_SOC_USB_CTRL 0x500 /* NOTE: big-endian */ 47#define FSL_SOC_USB_CTRL 0x500 /* NOTE: big-endian */
48#define CTRL_PHY_CLK_VALID (1 << 17)
49#define SNOOP_SIZE_2GB 0x1e 48#define SNOOP_SIZE_2GB 0x1e
50#endif /* _EHCI_FSL_H */ 49#endif /* _EHCI_FSL_H */