194 files changed, 15423 insertions, 2353 deletions

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index d46f1da18a3..0c55582a49c 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -716,7 +716,6 @@ config CAVIUM_OCTEON_SIMULATOR
         select DMA_COHERENT
         select SYS_SUPPORTS_64BIT_KERNEL
         select SYS_SUPPORTS_BIG_ENDIAN
-        select SYS_SUPPORTS_HIGHMEM
         select SYS_SUPPORTS_HOTPLUG_CPU
         select SYS_HAS_CPU_CAVIUM_OCTEON
         select HOLES_IN_ZONE
@@ -732,7 +731,6 @@ config CAVIUM_OCTEON_REFERENCE_BOARD
         select DMA_COHERENT
         select SYS_SUPPORTS_64BIT_KERNEL
         select SYS_SUPPORTS_BIG_ENDIAN
-        select SYS_SUPPORTS_HIGHMEM
         select SYS_SUPPORTS_HOTPLUG_CPU
         select SYS_HAS_EARLY_PRINTK
         select SYS_HAS_CPU_CAVIUM_OCTEON
@@ -761,7 +759,6 @@ config NLM_XLR_BOARD
         depends on EXPERIMENTAL
         select BOOT_ELF32
         select NLM_COMMON
-        select NLM_XLR
         select SYS_HAS_CPU_XLR
         select SYS_SUPPORTS_SMP
         select HW_HAS_PCI
@@ -776,6 +773,7 @@ config NLM_XLR_BOARD
         select CEVT_R4K
         select CSRC_R4K
         select IRQ_CPU
+        select ARCH_SUPPORTS_MSI
         select ZONE_DMA if 64BIT
         select SYNC_R4K
         select SYS_HAS_EARLY_PRINTK
@@ -783,6 +781,33 @@ config NLM_XLR_BOARD
           Support for systems based on Netlogic XLR and XLS processors.
           Say Y here if you have a XLR or XLS based board.
 
+config NLM_XLP_BOARD
+        bool "Netlogic XLP based systems"
+        depends on EXPERIMENTAL
+        select BOOT_ELF32
+        select NLM_COMMON
+        select SYS_HAS_CPU_XLP
+        select SYS_SUPPORTS_SMP
+        select HW_HAS_PCI
+        select SWAP_IO_SPACE
+        select SYS_SUPPORTS_32BIT_KERNEL
+        select SYS_SUPPORTS_64BIT_KERNEL
+        select 64BIT_PHYS_ADDR
+        select SYS_SUPPORTS_BIG_ENDIAN
+        select SYS_SUPPORTS_LITTLE_ENDIAN
+        select SYS_SUPPORTS_HIGHMEM
+        select DMA_COHERENT
+        select NR_CPUS_DEFAULT_32
+        select CEVT_R4K
+        select CSRC_R4K
+        select IRQ_CPU
+        select ZONE_DMA if 64BIT
+        select SYNC_R4K
+        select SYS_HAS_EARLY_PRINTK
+        help
+          This board is based on Netlogic XLP Processor.
+          Say Y here if you have a XLP based board.
+
 endchoice
 
 source "arch/mips/alchemy/Kconfig"
@@ -1413,51 +1438,36 @@ config CPU_CAVIUM_OCTEON
 config CPU_BMIPS3300
         bool "BMIPS3300"
         depends on SYS_HAS_CPU_BMIPS3300
-        select DMA_NONCOHERENT
-        select IRQ_CPU
-        select SWAP_IO_SPACE
-        select SYS_SUPPORTS_32BIT_KERNEL
-        select WEAK_ORDERING
+        select CPU_BMIPS
         help
           Broadcom BMIPS3300 processors.
 
 config CPU_BMIPS4350
         bool "BMIPS4350"
         depends on SYS_HAS_CPU_BMIPS4350
-        select CPU_SUPPORTS_32BIT_KERNEL
-        select DMA_NONCOHERENT
-        select IRQ_CPU
-        select SWAP_IO_SPACE
+        select CPU_BMIPS
         select SYS_SUPPORTS_SMP
         select SYS_SUPPORTS_HOTPLUG_CPU
-        select WEAK_ORDERING
         help
           Broadcom BMIPS4350 ("VIPER") processors.
 
 config CPU_BMIPS4380
         bool "BMIPS4380"
         depends on SYS_HAS_CPU_BMIPS4380
-        select CPU_SUPPORTS_32BIT_KERNEL
-        select DMA_NONCOHERENT
-        select IRQ_CPU
-        select SWAP_IO_SPACE
+        select CPU_BMIPS
         select SYS_SUPPORTS_SMP
         select SYS_SUPPORTS_HOTPLUG_CPU
-        select WEAK_ORDERING
         help
           Broadcom BMIPS4380 processors.
 
 config CPU_BMIPS5000
         bool "BMIPS5000"
         depends on SYS_HAS_CPU_BMIPS5000
-        select CPU_SUPPORTS_32BIT_KERNEL
+        select CPU_BMIPS
         select CPU_SUPPORTS_HIGHMEM
-        select DMA_NONCOHERENT
-        select IRQ_CPU
-        select SWAP_IO_SPACE
+        select MIPS_CPU_SCACHE
         select SYS_SUPPORTS_SMP
         select SYS_SUPPORTS_HOTPLUG_CPU
-        select WEAK_ORDERING
         help
           Broadcom BMIPS5000 processors.
 
@@ -1472,6 +1482,19 @@ config CPU_XLR
         select CPU_SUPPORTS_HUGEPAGES
         help
           Netlogic Microsystems XLR/XLS processors.
+
+config CPU_XLP
+        bool "Netlogic XLP SoC"
+        depends on SYS_HAS_CPU_XLP
+        select CPU_SUPPORTS_32BIT_KERNEL
+        select CPU_SUPPORTS_64BIT_KERNEL
+        select CPU_SUPPORTS_HIGHMEM
+        select CPU_HAS_LLSC
+        select WEAK_ORDERING
+        select WEAK_REORDERING_BEYOND_LLSC
+        select CPU_HAS_PREFETCH
+        help
+          Netlogic Microsystems XLP processors.
 endchoice
 
 if CPU_LOONGSON2F
@@ -1518,6 +1541,15 @@ config CPU_LOONGSON2
         select CPU_SUPPORTS_64BIT_KERNEL
         select CPU_SUPPORTS_HIGHMEM
 
+config CPU_BMIPS
+        bool
+        select CPU_MIPS32
+        select CPU_SUPPORTS_32BIT_KERNEL
+        select DMA_NONCOHERENT
+        select IRQ_CPU
+        select SWAP_IO_SPACE
+        select WEAK_ORDERING
+
 config SYS_HAS_CPU_LOONGSON2E
         bool
 
@@ -1605,6 +1637,9 @@ config SYS_HAS_CPU_BMIPS5000
 config SYS_HAS_CPU_XLR
         bool
 
+config SYS_HAS_CPU_XLP
+        bool
+
 #
 # CPU may reorder R->R, R->W, W->R, W->W
 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
@@ -1992,6 +2027,9 @@ config CPU_HAS_SMARTMIPS
 config CPU_HAS_WB
         bool
 
+config XKS01
+        bool
+
 #
 # Vectored interrupt mode is an R2 feature
 #
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 0be318609fc..4fedf5a51d9 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -157,6 +157,7 @@ ifeq (,$(findstring march=octeon, $(cflags-$(CONFIG_CPU_CAVIUM_OCTEON))))
 cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += -Wa,-march=octeon
 endif
 cflags-$(CONFIG_CAVIUM_CN63XXP1) += -Wa,-mfix-cn63xxp1
+cflags-$(CONFIG_CPU_BMIPS)      += -march=mips32 -Wa,-mips32 -Wa,--trap
 
 cflags-$(CONFIG_CPU_R4000_WORKAROUNDS)  += $(call cc-option,-mfix-r4000,)
 cflags-$(CONFIG_CPU_R4400_WORKAROUNDS)  += $(call cc-option,-mfix-r4400,)
diff --git a/arch/mips/ar7/gpio.c b/arch/mips/ar7/gpio.c
index bb571bcdb8f..d8dbd8f0c1d 100644
--- a/arch/mips/ar7/gpio.c
+++ b/arch/mips/ar7/gpio.c
@@ -217,7 +217,7 @@ struct titan_gpio_cfg {
         u32 func;
 };
 
-static struct titan_gpio_cfg titan_gpio_table[] = {
+static const struct titan_gpio_cfg titan_gpio_table[] = {
         /* reg, start bit, mux value */
         {4, 24, 1},
         {4, 26, 1},
diff --git a/arch/mips/ar7/platform.c b/arch/mips/ar7/platform.c
index 60102392af0..1a24d317e7a 100644
--- a/arch/mips/ar7/platform.c
+++ b/arch/mips/ar7/platform.c
@@ -462,6 +462,40 @@ static struct gpio_led fb_fon_leds[] = {
         },
 };
 
+static struct gpio_led gt701_leds[] = {
+        {
+                .name                   = "inet:green",
+                .gpio                   = 13,
+                .active_low             = 1,
+        },
+        {
+                .name                   = "usb",
+                .gpio                   = 12,
+                .active_low             = 1,
+        },
+        {
+                .name                   = "inet:red",
+                .gpio                   = 9,
+                .active_low             = 1,
+        },
+        {
+                .name                   = "power:red",
+                .gpio                   = 7,
+                .active_low             = 1,
+        },
+        {
+                .name                   = "power:green",
+                .gpio                   = 8,
+                .active_low             = 1,
+                .default_trigger        = "default-on",
+        },
+        {
+                .name                   = "ethernet",
+                .gpio                   = 10,
+                .active_low             = 1,
+        },
+};
+
 static struct gpio_led_platform_data ar7_led_data;
 
 static struct platform_device ar7_gpio_leds = {
@@ -503,6 +537,9 @@ static void __init detect_leds(void)
         } else if (strstr(prid, "CYWM") || strstr(prid, "CYWL")) {
                 ar7_led_data.num_leds = ARRAY_SIZE(titan_leds);
                 ar7_led_data.leds = titan_leds;
+        } else if (strstr(prid, "GT701")) {
+                ar7_led_data.num_leds = ARRAY_SIZE(gt701_leds);
+                ar7_led_data.leds = gt701_leds;
         }
 }
 
diff --git a/arch/mips/ar7/prom.c b/arch/mips/ar7/prom.c
index 8088c6fdb83..a23adc49d50 100644
--- a/arch/mips/ar7/prom.c
+++ b/arch/mips/ar7/prom.c
@@ -69,7 +69,7 @@ struct psbl_rec {
         u32     ffs_size;
 };
 
-static __initdata char psp_env_version[] = "TIENV0.8";
+static const char psp_env_version[] __initconst = "TIENV0.8";
 
 struct psp_env_chunk {
         u8      num;
@@ -84,7 +84,7 @@ struct psp_var_map_entry {
         char    *value;
 };
 
-static struct psp_var_map_entry psp_var_map[] = {
+static const struct psp_var_map_entry psp_var_map[] = {
         {  1,   "cpufrequency" },
         {  2,   "memsize" },
         {  3,   "flashsize" },
diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig
index 47707410582..e0fae8f4442 100644
--- a/arch/mips/ath79/Kconfig
+++ b/arch/mips/ath79/Kconfig
@@ -2,13 +2,26 @@ if ATH79
 
 menu "Atheros AR71XX/AR724X/AR913X machine selection"
 
+config ATH79_MACH_AP121
+        bool "Atheros AP121 reference board"
+        select SOC_AR933X
+        select ATH79_DEV_GPIO_BUTTONS
+        select ATH79_DEV_LEDS_GPIO
+        select ATH79_DEV_SPI
+        select ATH79_DEV_USB
+        select ATH79_DEV_WMAC
+        help
+          Say 'Y' here if you want your kernel to support the
+          Atheros AP121 reference board.
+
 config ATH79_MACH_AP81
         bool "Atheros AP81 reference board"
         select SOC_AR913X
-        select ATH79_DEV_AR913X_WMAC
         select ATH79_DEV_GPIO_BUTTONS
         select ATH79_DEV_LEDS_GPIO
         select ATH79_DEV_SPI
+        select ATH79_DEV_USB
+        select ATH79_DEV_WMAC
         help
           Say 'Y' here if you want your kernel to support the
           Atheros AP81 reference board.
@@ -19,10 +32,21 @@ config ATH79_MACH_PB44
         select ATH79_DEV_GPIO_BUTTONS
         select ATH79_DEV_LEDS_GPIO
         select ATH79_DEV_SPI
+        select ATH79_DEV_USB
         help
           Say 'Y' here if you want your kernel to support the
           Atheros PB44 reference board.
 
+config ATH79_MACH_UBNT_XM
+        bool "Ubiquiti Networks XM (rev 1.0) board"
+        select SOC_AR724X
+        select ATH79_DEV_GPIO_BUTTONS
+        select ATH79_DEV_LEDS_GPIO
+        select ATH79_DEV_SPI
+        help
+          Say 'Y' here if you want your kernel to support the
+          Ubiquiti Networks XM (rev 1.0) board.
+
 endmenu
 
 config SOC_AR71XX
@@ -33,14 +57,15 @@ config SOC_AR71XX
 config SOC_AR724X
         select USB_ARCH_HAS_EHCI
         select USB_ARCH_HAS_OHCI
+        select HW_HAS_PCI
         def_bool n
 
 config SOC_AR913X
         select USB_ARCH_HAS_EHCI
         def_bool n
 
-config ATH79_DEV_AR913X_WMAC
-        depends on SOC_AR913X
+config SOC_AR933X
+        select USB_ARCH_HAS_EHCI
         def_bool n
 
 config ATH79_DEV_GPIO_BUTTONS
@@ -52,4 +77,11 @@ config ATH79_DEV_LEDS_GPIO
 config ATH79_DEV_SPI
         def_bool n
 
+config ATH79_DEV_USB
+        def_bool n
+
+config ATH79_DEV_WMAC
+        depends on (SOC_AR913X || SOC_AR933X)
+        def_bool n
+
 endif
diff --git a/arch/mips/ath79/Makefile b/arch/mips/ath79/Makefile
index c33d4653007..3b911e09dbe 100644
--- a/arch/mips/ath79/Makefile
+++ b/arch/mips/ath79/Makefile
@@ -16,13 +16,16 @@ obj-$(CONFIG_EARLY_PRINTK)		+= early_printk.o
 # Devices
 #
 obj-y                                   += dev-common.o
-obj-$(CONFIG_ATH79_DEV_AR913X_WMAC)     += dev-ar913x-wmac.o
 obj-$(CONFIG_ATH79_DEV_GPIO_BUTTONS)    += dev-gpio-buttons.o
 obj-$(CONFIG_ATH79_DEV_LEDS_GPIO)       += dev-leds-gpio.o
 obj-$(CONFIG_ATH79_DEV_SPI)             += dev-spi.o
+obj-$(CONFIG_ATH79_DEV_USB)             += dev-usb.o
+obj-$(CONFIG_ATH79_DEV_WMAC)            += dev-wmac.o
 
 #
 # Machines
 #
+obj-$(CONFIG_ATH79_MACH_AP121)          += mach-ap121.o
 obj-$(CONFIG_ATH79_MACH_AP81)           += mach-ap81.o
 obj-$(CONFIG_ATH79_MACH_PB44)           += mach-pb44.o
+obj-$(CONFIG_ATH79_MACH_UBNT_XM)        += mach-ubnt-xm.o
diff --git a/arch/mips/ath79/clock.c b/arch/mips/ath79/clock.c
index 680bde99a26..54d0eb4db98 100644
--- a/arch/mips/ath79/clock.c
+++ b/arch/mips/ath79/clock.c
@@ -110,6 +110,59 @@ static void __init ar913x_clocks_init(void)
         ath79_uart_clk.rate = ath79_ahb_clk.rate;
 }
 
+static void __init ar933x_clocks_init(void)
+{
+        u32 clock_ctrl;
+        u32 cpu_config;
+        u32 freq;
+        u32 t;
+
+        t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
+        if (t & AR933X_BOOTSTRAP_REF_CLK_40)
+                ath79_ref_clk.rate = (40 * 1000 * 1000);
+        else
+                ath79_ref_clk.rate = (25 * 1000 * 1000);
+
+        clock_ctrl = ath79_pll_rr(AR933X_PLL_CLOCK_CTRL_REG);
+        if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
+                ath79_cpu_clk.rate = ath79_ref_clk.rate;
+                ath79_ahb_clk.rate = ath79_ref_clk.rate;
+                ath79_ddr_clk.rate = ath79_ref_clk.rate;
+        } else {
+                cpu_config = ath79_pll_rr(AR933X_PLL_CPU_CONFIG_REG);
+
+                t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
+                    AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
+                freq = ath79_ref_clk.rate / t;
+
+                t = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) &
+                    AR933X_PLL_CPU_CONFIG_NINT_MASK;
+                freq *= t;
+
+                t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
+                    AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
+                if (t == 0)
+                        t = 1;
+
+                freq >>= t;
+
+                t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) &
+                     AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1;
+                ath79_cpu_clk.rate = freq / t;
+
+                t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) &
+                      AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1;
+                ath79_ddr_clk.rate = freq / t;
+
+                t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) &
+                     AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1;
+                ath79_ahb_clk.rate = freq / t;
+        }
+
+        ath79_wdt_clk.rate = ath79_ref_clk.rate;
+        ath79_uart_clk.rate = ath79_ref_clk.rate;
+}
+
 void __init ath79_clocks_init(void)
 {
         if (soc_is_ar71xx())
@@ -118,6 +171,8 @@ void __init ath79_clocks_init(void)
                 ar724x_clocks_init();
         else if (soc_is_ar913x())
                 ar913x_clocks_init();
+        else if (soc_is_ar933x())
+                ar933x_clocks_init();
         else
                 BUG();
 
diff --git a/arch/mips/ath79/common.c b/arch/mips/ath79/common.c
index 58f60e722a0..f0fda982b96 100644
--- a/arch/mips/ath79/common.c
+++ b/arch/mips/ath79/common.c
@@ -30,6 +30,7 @@ u32 ath79_ddr_freq;
 EXPORT_SYMBOL_GPL(ath79_ddr_freq);
 
 enum ath79_soc_type ath79_soc;
+unsigned int ath79_soc_rev;
 
 void __iomem *ath79_pll_base;
 void __iomem *ath79_reset_base;
@@ -64,6 +65,8 @@ void ath79_device_reset_set(u32 mask)
                 reg = AR724X_RESET_REG_RESET_MODULE;
         else if (soc_is_ar913x())
                 reg = AR913X_RESET_REG_RESET_MODULE;
+        else if (soc_is_ar933x())
+                reg = AR933X_RESET_REG_RESET_MODULE;
         else
                 BUG();
 
@@ -86,6 +89,8 @@ void ath79_device_reset_clear(u32 mask)
                 reg = AR724X_RESET_REG_RESET_MODULE;
         else if (soc_is_ar913x())
                 reg = AR913X_RESET_REG_RESET_MODULE;
+        else if (soc_is_ar933x())
+                reg = AR933X_RESET_REG_RESET_MODULE;
         else
                 BUG();
 
diff --git a/arch/mips/ath79/dev-ar913x-wmac.c b/arch/mips/ath79/dev-ar913x-wmac.c
deleted file mode 100644
index 48f425a5ba2..00000000000
--- a/arch/mips/ath79/dev-ar913x-wmac.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- *  Atheros AR913X SoC built-in WMAC device support
- *
- *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
- *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
- *
- *  This program is free software; you can redistribute it and/or modify it
- *  under the terms of the GNU General Public License version 2 as published
- *  by the Free Software Foundation.
- */
-
-#include <linux/init.h>
-#include <linux/delay.h>
-#include <linux/irq.h>
-#include <linux/platform_device.h>
-#include <linux/ath9k_platform.h>
-
-#include <asm/mach-ath79/ath79.h>
-#include <asm/mach-ath79/ar71xx_regs.h>
-#include "dev-ar913x-wmac.h"
-
-static struct ath9k_platform_data ar913x_wmac_data;
-
-static struct resource ar913x_wmac_resources[] = {
-        {
-                .start  = AR913X_WMAC_BASE,
-                .end    = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = ATH79_CPU_IRQ_IP2,
-                .end    = ATH79_CPU_IRQ_IP2,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device ar913x_wmac_device = {
-        .name           = "ath9k",
-        .id             = -1,
-        .resource       = ar913x_wmac_resources,
-        .num_resources  = ARRAY_SIZE(ar913x_wmac_resources),
-        .dev = {
-                .platform_data = &ar913x_wmac_data,
-        },
-};
-
-void __init ath79_register_ar913x_wmac(u8 *cal_data)
-{
-        if (cal_data)
-                memcpy(ar913x_wmac_data.eeprom_data, cal_data,
-                       sizeof(ar913x_wmac_data.eeprom_data));
-
-        /* reset the WMAC */
-        ath79_device_reset_set(AR913X_RESET_AMBA2WMAC);
-        mdelay(10);
-
-        ath79_device_reset_clear(AR913X_RESET_AMBA2WMAC);
-        mdelay(10);
-
-        platform_device_register(&ar913x_wmac_device);
-}
diff --git a/arch/mips/ath79/dev-common.c b/arch/mips/ath79/dev-common.c
index 3b82e325beb..f4956f80907 100644
--- a/arch/mips/ath79/dev-common.c
+++ b/arch/mips/ath79/dev-common.c
@@ -20,6 +20,7 @@
 
 #include <asm/mach-ath79/ath79.h>
 #include <asm/mach-ath79/ar71xx_regs.h>
+#include <asm/mach-ath79/ar933x_uart_platform.h>
 #include "common.h"
 #include "dev-common.h"
 
@@ -54,6 +55,30 @@ static struct platform_device ath79_uart_device = {
         },
 };
 
+static struct resource ar933x_uart_resources[] = {
+        {
+                .start  = AR933X_UART_BASE,
+                .end    = AR933X_UART_BASE + AR71XX_UART_SIZE - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = ATH79_MISC_IRQ_UART,
+                .end    = ATH79_MISC_IRQ_UART,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct ar933x_uart_platform_data ar933x_uart_data;
+static struct platform_device ar933x_uart_device = {
+        .name           = "ar933x-uart",
+        .id             = -1,
+        .resource       = ar933x_uart_resources,
+        .num_resources  = ARRAY_SIZE(ar933x_uart_resources),
+        .dev = {
+                .platform_data  = &ar933x_uart_data,
+        },
+};
+
 void __init ath79_register_uart(void)
 {
         struct clk *clk;
@@ -62,8 +87,17 @@ void __init ath79_register_uart(void)
         if (IS_ERR(clk))
                 panic("unable to get UART clock, err=%ld", PTR_ERR(clk));
 
-        ath79_uart_data[0].uartclk = clk_get_rate(clk);
-        platform_device_register(&ath79_uart_device);
+        if (soc_is_ar71xx() ||
+            soc_is_ar724x() ||
+            soc_is_ar913x()) {
+                ath79_uart_data[0].uartclk = clk_get_rate(clk);
+                platform_device_register(&ath79_uart_device);
+        } else if (soc_is_ar933x()) {
+                ar933x_uart_data.uartclk = clk_get_rate(clk);
+                platform_device_register(&ar933x_uart_device);
+        } else {
+                BUG();
+        }
 }
 
 static struct platform_device ath79_wdt_device = {
diff --git a/arch/mips/ath79/dev-usb.c b/arch/mips/ath79/dev-usb.c
new file mode 100644
index 00000000000..002d6d2afe0
--- /dev/null
+++ b/arch/mips/ath79/dev-usb.c
@@ -0,0 +1,197 @@
+/*
+ *  Atheros AR7XXX/AR9XXX USB Host Controller device
+ *
+ *  Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ *  Parts of this file are based on Atheros' 2.6.15 BSP
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/irq.h>
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+
+#include <asm/mach-ath79/ath79.h>
+#include <asm/mach-ath79/ar71xx_regs.h>
+#include "common.h"
+#include "dev-usb.h"
+
+static struct resource ath79_ohci_resources[] = {
+        [0] = {
+                /* .start and .end fields are filled dynamically */
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = ATH79_MISC_IRQ_OHCI,
+                .end    = ATH79_MISC_IRQ_OHCI,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static u64 ath79_ohci_dmamask = DMA_BIT_MASK(32);
+static struct platform_device ath79_ohci_device = {
+        .name           = "ath79-ohci",
+        .id             = -1,
+        .resource       = ath79_ohci_resources,
+        .num_resources  = ARRAY_SIZE(ath79_ohci_resources),
+        .dev = {
+                .dma_mask               = &ath79_ohci_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
+
+static struct resource ath79_ehci_resources[] = {
+        [0] = {
+                /* .start and .end fields are filled dynamically */
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = ATH79_CPU_IRQ_USB,
+                .end    = ATH79_CPU_IRQ_USB,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static u64 ath79_ehci_dmamask = DMA_BIT_MASK(32);
+static struct platform_device ath79_ehci_device = {
+        .name           = "ath79-ehci",
+        .id             = -1,
+        .resource       = ath79_ehci_resources,
+        .num_resources  = ARRAY_SIZE(ath79_ehci_resources),
+        .dev = {
+                .dma_mask               = &ath79_ehci_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
+
+#define AR71XX_USB_RESET_MASK   (AR71XX_RESET_USB_HOST | \
+                                 AR71XX_RESET_USB_PHY | \
+                                 AR71XX_RESET_USB_OHCI_DLL)
+
+static void __init ath79_usb_setup(void)
+{
+        void __iomem *usb_ctrl_base;
+
+        ath79_device_reset_set(AR71XX_USB_RESET_MASK);
+        mdelay(1000);
+        ath79_device_reset_clear(AR71XX_USB_RESET_MASK);
+
+        usb_ctrl_base = ioremap(AR71XX_USB_CTRL_BASE, AR71XX_USB_CTRL_SIZE);
+
+        /* Turning on the Buff and Desc swap bits */
+        __raw_writel(0xf0000, usb_ctrl_base + AR71XX_USB_CTRL_REG_CONFIG);
+
+        /* WAR for HW bug. Here it adjusts the duration between two SOFS */
+        __raw_writel(0x20c00, usb_ctrl_base + AR71XX_USB_CTRL_REG_FLADJ);
+
+        iounmap(usb_ctrl_base);
+
+        mdelay(900);
+
+        ath79_ohci_resources[0].start = AR71XX_OHCI_BASE;
+        ath79_ohci_resources[0].end = AR71XX_OHCI_BASE + AR71XX_OHCI_SIZE - 1;
+        platform_device_register(&ath79_ohci_device);
+
+        ath79_ehci_resources[0].start = AR71XX_EHCI_BASE;
+        ath79_ehci_resources[0].end = AR71XX_EHCI_BASE + AR71XX_EHCI_SIZE - 1;
+        ath79_ehci_device.name = "ar71xx-ehci";
+        platform_device_register(&ath79_ehci_device);
+}
+
+static void __init ar7240_usb_setup(void)
+{
+        void __iomem *usb_ctrl_base;
+
+        ath79_device_reset_clear(AR7240_RESET_OHCI_DLL);
+        ath79_device_reset_set(AR7240_RESET_USB_HOST);
+
+        mdelay(1000);
+
+        ath79_device_reset_set(AR7240_RESET_OHCI_DLL);
+        ath79_device_reset_clear(AR7240_RESET_USB_HOST);
+
+        usb_ctrl_base = ioremap(AR7240_USB_CTRL_BASE, AR7240_USB_CTRL_SIZE);
+
+        /* WAR for HW bug. Here it adjusts the duration between two SOFS */
+        __raw_writel(0x3, usb_ctrl_base + AR71XX_USB_CTRL_REG_FLADJ);
+
+        iounmap(usb_ctrl_base);
+
+        ath79_ohci_resources[0].start = AR7240_OHCI_BASE;
+        ath79_ohci_resources[0].end = AR7240_OHCI_BASE + AR7240_OHCI_SIZE - 1;
+        platform_device_register(&ath79_ohci_device);
+}
+
+static void __init ar724x_usb_setup(void)
+{
+        ath79_device_reset_set(AR724X_RESET_USBSUS_OVERRIDE);
+        mdelay(10);
+
+        ath79_device_reset_clear(AR724X_RESET_USB_HOST);
+        mdelay(10);
+
+        ath79_device_reset_clear(AR724X_RESET_USB_PHY);
+        mdelay(10);
+
+        ath79_ehci_resources[0].start = AR724X_EHCI_BASE;
+        ath79_ehci_resources[0].end = AR724X_EHCI_BASE + AR724X_EHCI_SIZE - 1;
+        ath79_ehci_device.name = "ar724x-ehci";
+        platform_device_register(&ath79_ehci_device);
+}
+
+static void __init ar913x_usb_setup(void)
+{
+        ath79_device_reset_set(AR913X_RESET_USBSUS_OVERRIDE);
+        mdelay(10);
+
+        ath79_device_reset_clear(AR913X_RESET_USB_HOST);
+        mdelay(10);
+
+        ath79_device_reset_clear(AR913X_RESET_USB_PHY);
+        mdelay(10);
+
+        ath79_ehci_resources[0].start = AR913X_EHCI_BASE;
+        ath79_ehci_resources[0].end = AR913X_EHCI_BASE + AR913X_EHCI_SIZE - 1;
+        ath79_ehci_device.name = "ar913x-ehci";
+        platform_device_register(&ath79_ehci_device);
+}
+
+static void __init ar933x_usb_setup(void)
+{
+        ath79_device_reset_set(AR933X_RESET_USBSUS_OVERRIDE);
+        mdelay(10);
+
+        ath79_device_reset_clear(AR933X_RESET_USB_HOST);
+        mdelay(10);
+
+        ath79_device_reset_clear(AR933X_RESET_USB_PHY);
+        mdelay(10);
+
+        ath79_ehci_resources[0].start = AR933X_EHCI_BASE;
+        ath79_ehci_resources[0].end = AR933X_EHCI_BASE + AR933X_EHCI_SIZE - 1;
+        ath79_ehci_device.name = "ar933x-ehci";
+        platform_device_register(&ath79_ehci_device);
+}
+
+void __init ath79_register_usb(void)
+{
+        if (soc_is_ar71xx())
+                ath79_usb_setup();
+        else if (soc_is_ar7240())
+                ar7240_usb_setup();
+        else if (soc_is_ar7241() || soc_is_ar7242())
+                ar724x_usb_setup();
+        else if (soc_is_ar913x())
+                ar913x_usb_setup();
+        else if (soc_is_ar933x())
+                ar933x_usb_setup();
+        else
+                BUG();
+}
diff --git a/arch/mips/ath79/dev-ar913x-wmac.h b/arch/mips/ath79/dev-usb.h
index 579d562bbda..4b86a69ca08 100644
--- a/arch/mips/ath79/dev-ar913x-wmac.h
+++ b/arch/mips/ath79/dev-usb.h
@@ -1,5 +1,5 @@
 /*
- *  Atheros AR913X SoC built-in WMAC device support
+ *  Atheros AR71XX/AR724X/AR913X USB Host Controller support
  *
  *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
@@ -9,9 +9,9 @@
  *  by the Free Software Foundation.
  */
 
-#ifndef _ATH79_DEV_AR913X_WMAC_H
-#define _ATH79_DEV_AR913X_WMAC_H
+#ifndef _ATH79_DEV_USB_H
+#define _ATH79_DEV_USB_H
 
-void ath79_register_ar913x_wmac(u8 *cal_data);
+void ath79_register_usb(void);
 
-#endif /* _ATH79_DEV_AR913X_WMAC_H */
+#endif /* _ATH79_DEV_USB_H */
diff --git a/arch/mips/ath79/dev-wmac.c b/arch/mips/ath79/dev-wmac.c
new file mode 100644
index 00000000000..24f546985b6
--- /dev/null
+++ b/arch/mips/ath79/dev-wmac.c
@@ -0,0 +1,109 @@
+/*
+ *  Atheros AR913X/AR933X SoC built-in WMAC device support
+ *
+ *  Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/irq.h>
+#include <linux/platform_device.h>
+#include <linux/ath9k_platform.h>
+
+#include <asm/mach-ath79/ath79.h>
+#include <asm/mach-ath79/ar71xx_regs.h>
+#include "dev-wmac.h"
+
+static struct ath9k_platform_data ath79_wmac_data;
+
+static struct resource ath79_wmac_resources[] = {
+        {
+                /* .start and .end fields are filled dynamically */
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = ATH79_CPU_IRQ_IP2,
+                .end    = ATH79_CPU_IRQ_IP2,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device ath79_wmac_device = {
+        .name           = "ath9k",
+        .id             = -1,
+        .resource       = ath79_wmac_resources,
+        .num_resources  = ARRAY_SIZE(ath79_wmac_resources),
+        .dev = {
+                .platform_data = &ath79_wmac_data,
+        },
+};
+
+static void __init ar913x_wmac_setup(void)
+{
+        /* reset the WMAC */
+        ath79_device_reset_set(AR913X_RESET_AMBA2WMAC);
+        mdelay(10);
+
+        ath79_device_reset_clear(AR913X_RESET_AMBA2WMAC);
+        mdelay(10);
+
+        ath79_wmac_resources[0].start = AR913X_WMAC_BASE;
+        ath79_wmac_resources[0].end = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1;
+}
+
+
+static int ar933x_wmac_reset(void)
+{
+        ath79_device_reset_clear(AR933X_RESET_WMAC);
+        ath79_device_reset_set(AR933X_RESET_WMAC);
+
+        return 0;
+}
+
+static int ar933x_r1_get_wmac_revision(void)
+{
+        return ath79_soc_rev;
+}
+
+static void __init ar933x_wmac_setup(void)
+{
+        u32 t;
+
+        ar933x_wmac_reset();
+
+        ath79_wmac_device.name = "ar933x_wmac";
+
+        ath79_wmac_resources[0].start = AR933X_WMAC_BASE;
+        ath79_wmac_resources[0].end = AR933X_WMAC_BASE + AR933X_WMAC_SIZE - 1;
+
+        t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
+        if (t & AR933X_BOOTSTRAP_REF_CLK_40)
+                ath79_wmac_data.is_clk_25mhz = false;
+        else
+                ath79_wmac_data.is_clk_25mhz = true;
+
+        if (ath79_soc_rev == 1)
+                ath79_wmac_data.get_mac_revision = ar933x_r1_get_wmac_revision;
+
+        ath79_wmac_data.external_reset = ar933x_wmac_reset;
+}
+
+void __init ath79_register_wmac(u8 *cal_data)
+{
+        if (soc_is_ar913x())
+                ar913x_wmac_setup();
+        if (soc_is_ar933x())
+                ar933x_wmac_setup();
+        else
+                BUG();
+
+        if (cal_data)
+                memcpy(ath79_wmac_data.eeprom_data, cal_data,
+                       sizeof(ath79_wmac_data.eeprom_data));
+
+        platform_device_register(&ath79_wmac_device);
+}
diff --git a/arch/mips/ath79/dev-wmac.h b/arch/mips/ath79/dev-wmac.h
new file mode 100644
index 00000000000..c9cd8709f09
--- /dev/null
+++ b/arch/mips/ath79/dev-wmac.h
@@ -0,0 +1,17 @@
+/*
+ *  Atheros AR913X/AR933X SoC built-in WMAC device support
+ *
+ *  Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#ifndef _ATH79_DEV_WMAC_H
+#define _ATH79_DEV_WMAC_H
+
+void ath79_register_wmac(u8 *cal_data);
+
+#endif /* _ATH79_DEV_WMAC_H */
diff --git a/arch/mips/ath79/early_printk.c b/arch/mips/ath79/early_printk.c
index 7499b0e9df2..6a51ced7a29 100644
--- a/arch/mips/ath79/early_printk.c
+++ b/arch/mips/ath79/early_printk.c
@@ -1,7 +1,7 @@
 /*
- *  Atheros AR71XX/AR724X/AR913X SoC early printk support
+ *  Atheros AR7XXX/AR9XXX SoC early printk support
  *
- *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  *
  *  This program is free software; you can redistribute it and/or modify it
@@ -10,27 +10,85 @@
  */
 
 #include <linux/io.h>
+#include <linux/errno.h>
 #include <linux/serial_reg.h>
 #include <asm/addrspace.h>
 
+#include <asm/mach-ath79/ath79.h>
 #include <asm/mach-ath79/ar71xx_regs.h>
+#include <asm/mach-ath79/ar933x_uart.h>
 
-static inline void prom_wait_thre(void __iomem *base)
+static void (*_prom_putchar) (unsigned char);
+
+static inline void prom_putchar_wait(void __iomem *reg, u32 mask, u32 val)
 {
-        u32 lsr;
+        u32 t;
 
         do {
-                lsr = __raw_readl(base + UART_LSR * 4);
-                if (lsr & UART_LSR_THRE)
+                t = __raw_readl(reg);
+                if ((t & mask) == val)
                         break;
         } while (1);
 }
 
-void prom_putchar(unsigned char ch)
+static void prom_putchar_ar71xx(unsigned char ch)
 {
         void __iomem *base = (void __iomem *)(KSEG1ADDR(AR71XX_UART_BASE));
 
-        prom_wait_thre(base);
+        prom_putchar_wait(base + UART_LSR * 4, UART_LSR_THRE, UART_LSR_THRE);
         __raw_writel(ch, base + UART_TX * 4);
-        prom_wait_thre(base);
+        prom_putchar_wait(base + UART_LSR * 4, UART_LSR_THRE, UART_LSR_THRE);
+}
+
+static void prom_putchar_ar933x(unsigned char ch)
+{
+        void __iomem *base = (void __iomem *)(KSEG1ADDR(AR933X_UART_BASE));
+
+        prom_putchar_wait(base + AR933X_UART_DATA_REG, AR933X_UART_DATA_TX_CSR,
+                          AR933X_UART_DATA_TX_CSR);
+        __raw_writel(AR933X_UART_DATA_TX_CSR | ch, base + AR933X_UART_DATA_REG);
+        prom_putchar_wait(base + AR933X_UART_DATA_REG, AR933X_UART_DATA_TX_CSR,
+                          AR933X_UART_DATA_TX_CSR);
+}
+
+static void prom_putchar_dummy(unsigned char ch)
+{
+        /* nothing to do */
+}
+
+static void prom_putchar_init(void)
+{
+        void __iomem *base;
+        u32 id;
+
+        base = (void __iomem *)(KSEG1ADDR(AR71XX_RESET_BASE));
+        id = __raw_readl(base + AR71XX_RESET_REG_REV_ID);
+        id &= REV_ID_MAJOR_MASK;
+
+        switch (id) {
+        case REV_ID_MAJOR_AR71XX:
+        case REV_ID_MAJOR_AR7240:
+        case REV_ID_MAJOR_AR7241:
+        case REV_ID_MAJOR_AR7242:
+        case REV_ID_MAJOR_AR913X:
+                _prom_putchar = prom_putchar_ar71xx;
+                break;
+
+        case REV_ID_MAJOR_AR9330:
+        case REV_ID_MAJOR_AR9331:
+                _prom_putchar = prom_putchar_ar933x;
+                break;
+
+        default:
+                _prom_putchar = prom_putchar_dummy;
+                break;
+        }
+}
+
+void prom_putchar(unsigned char ch)
+{
+        if (!_prom_putchar)
+                prom_putchar_init();
+
+        _prom_putchar(ch);
 }
diff --git a/arch/mips/ath79/gpio.c b/arch/mips/ath79/gpio.c
index a0c426b8212..a2f8ca630ed 100644
--- a/arch/mips/ath79/gpio.c
+++ b/arch/mips/ath79/gpio.c
@@ -153,6 +153,8 @@ void __init ath79_gpio_init(void)
                 ath79_gpio_count = AR724X_GPIO_COUNT;
         else if (soc_is_ar913x())
                 ath79_gpio_count = AR913X_GPIO_COUNT;
+        else if (soc_is_ar933x())
+                ath79_gpio_count = AR933X_GPIO_COUNT;
         else
                 BUG();
 
diff --git a/arch/mips/ath79/irq.c b/arch/mips/ath79/irq.c
index ac610d5fe3b..1b073de4468 100644
--- a/arch/mips/ath79/irq.c
+++ b/arch/mips/ath79/irq.c
@@ -46,6 +46,15 @@ static void ath79_misc_irq_handler(unsigned int irq, struct irq_desc *desc)
         else if (pending & MISC_INT_TIMER)
                 generic_handle_irq(ATH79_MISC_IRQ_TIMER);
 
+        else if (pending & MISC_INT_TIMER2)
+                generic_handle_irq(ATH79_MISC_IRQ_TIMER2);
+
+        else if (pending & MISC_INT_TIMER3)
+                generic_handle_irq(ATH79_MISC_IRQ_TIMER3);
+
+        else if (pending & MISC_INT_TIMER4)
+                generic_handle_irq(ATH79_MISC_IRQ_TIMER4);
+
         else if (pending & MISC_INT_OHCI)
                 generic_handle_irq(ATH79_MISC_IRQ_OHCI);
 
@@ -58,6 +67,9 @@ static void ath79_misc_irq_handler(unsigned int irq, struct irq_desc *desc)
         else if (pending & MISC_INT_WDOG)
                 generic_handle_irq(ATH79_MISC_IRQ_WDOG);
 
+        else if (pending & MISC_INT_ETHSW)
+                generic_handle_irq(ATH79_MISC_IRQ_ETHSW);
+
         else
                 spurious_interrupt();
 }
@@ -117,7 +129,7 @@ static void __init ath79_misc_irq_init(void)
 
         if (soc_is_ar71xx() || soc_is_ar913x())
                 ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask;
-        else if (soc_is_ar724x())
+        else if (soc_is_ar724x() || soc_is_ar933x())
                 ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
         else
                 BUG();
@@ -174,6 +186,9 @@ void __init arch_init_irq(void)
         } else if (soc_is_ar913x()) {
                 ath79_ip2_flush_reg = AR913X_DDR_REG_FLUSH_WMAC;
                 ath79_ip3_flush_reg = AR913X_DDR_REG_FLUSH_USB;
+        } else if (soc_is_ar933x()) {
+                ath79_ip2_flush_reg = AR933X_DDR_REG_FLUSH_WMAC;
+                ath79_ip3_flush_reg = AR933X_DDR_REG_FLUSH_USB;
         } else
                 BUG();
 
diff --git a/arch/mips/ath79/mach-ap121.c b/arch/mips/ath79/mach-ap121.c
new file mode 100644
index 00000000000..4c20200d7c7
--- /dev/null
+++ b/arch/mips/ath79/mach-ap121.c
@@ -0,0 +1,92 @@
+/*
+ *  Atheros AP121 board support
+ *
+ *  Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#include "machtypes.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+#include "dev-spi.h"
+#include "dev-usb.h"
+#include "dev-wmac.h"
+
+#define AP121_GPIO_LED_WLAN             0
+#define AP121_GPIO_LED_USB              1
+
+#define AP121_GPIO_BTN_JUMPSTART        11
+#define AP121_GPIO_BTN_RESET            12
+
+#define AP121_KEYS_POLL_INTERVAL        20      /* msecs */
+#define AP121_KEYS_DEBOUNCE_INTERVAL    (3 * AP121_KEYS_POLL_INTERVAL)
+
+#define AP121_CAL_DATA_ADDR     0x1fff1000
+
+static struct gpio_led ap121_leds_gpio[] __initdata = {
+        {
+                .name           = "ap121:green:usb",
+                .gpio           = AP121_GPIO_LED_USB,
+                .active_low     = 0,
+        },
+        {
+                .name           = "ap121:green:wlan",
+                .gpio           = AP121_GPIO_LED_WLAN,
+                .active_low     = 0,
+        },
+};
+
+static struct gpio_keys_button ap121_gpio_keys[] __initdata = {
+        {
+                .desc           = "jumpstart button",
+                .type           = EV_KEY,
+                .code           = KEY_WPS_BUTTON,
+                .debounce_interval = AP121_KEYS_DEBOUNCE_INTERVAL,
+                .gpio           = AP121_GPIO_BTN_JUMPSTART,
+                .active_low     = 1,
+        },
+        {
+                .desc           = "reset button",
+                .type           = EV_KEY,
+                .code           = KEY_RESTART,
+                .debounce_interval = AP121_KEYS_DEBOUNCE_INTERVAL,
+                .gpio           = AP121_GPIO_BTN_RESET,
+                .active_low     = 1,
+        }
+};
+
+static struct spi_board_info ap121_spi_info[] = {
+        {
+                .bus_num        = 0,
+                .chip_select    = 0,
+                .max_speed_hz   = 25000000,
+                .modalias       = "mx25l1606e",
+        }
+};
+
+static struct ath79_spi_platform_data ap121_spi_data = {
+        .bus_num        = 0,
+        .num_chipselect = 1,
+};
+
+static void __init ap121_setup(void)
+{
+        u8 *cal_data = (u8 *) KSEG1ADDR(AP121_CAL_DATA_ADDR);
+
+        ath79_register_leds_gpio(-1, ARRAY_SIZE(ap121_leds_gpio),
+                                 ap121_leds_gpio);
+        ath79_register_gpio_keys_polled(-1, AP121_KEYS_POLL_INTERVAL,
+                                        ARRAY_SIZE(ap121_gpio_keys),
+                                        ap121_gpio_keys);
+
+        ath79_register_spi(&ap121_spi_data, ap121_spi_info,
+                           ARRAY_SIZE(ap121_spi_info));
+        ath79_register_usb();
+        ath79_register_wmac(cal_data);
+}
+
+MIPS_MACHINE(ATH79_MACH_AP121, "AP121", "Atheros AP121 reference board",
+             ap121_setup);
diff --git a/arch/mips/ath79/mach-ap81.c b/arch/mips/ath79/mach-ap81.c
index eee4c121deb..abe19836331 100644
--- a/arch/mips/ath79/mach-ap81.c
+++ b/arch/mips/ath79/mach-ap81.c
@@ -10,10 +10,11 @@
  */
 
 #include "machtypes.h"
-#include "dev-ar913x-wmac.h"
+#include "dev-wmac.h"
 #include "dev-gpio-buttons.h"
 #include "dev-leds-gpio.h"
 #include "dev-spi.h"
+#include "dev-usb.h"
 
 #define AP81_GPIO_LED_STATUS    1
 #define AP81_GPIO_LED_AOSS      3
@@ -91,7 +92,8 @@ static void __init ap81_setup(void)
                                         ap81_gpio_keys);
         ath79_register_spi(&ap81_spi_data, ap81_spi_info,
                            ARRAY_SIZE(ap81_spi_info));
-        ath79_register_ar913x_wmac(cal_data);
+        ath79_register_wmac(cal_data);
+        ath79_register_usb();
 }
 
 MIPS_MACHINE(ATH79_MACH_AP81, "AP81", "Atheros AP81 reference board",
diff --git a/arch/mips/ath79/mach-pb44.c b/arch/mips/ath79/mach-pb44.c
index ec7b7a135d5..fe9701a3229 100644
--- a/arch/mips/ath79/mach-pb44.c
+++ b/arch/mips/ath79/mach-pb44.c
@@ -18,6 +18,7 @@
 #include "dev-gpio-buttons.h"
 #include "dev-leds-gpio.h"
 #include "dev-spi.h"
+#include "dev-usb.h"
 
 #define PB44_GPIO_I2C_SCL       0
 #define PB44_GPIO_I2C_SDA       1
@@ -112,6 +113,7 @@ static void __init pb44_init(void)
                                         pb44_gpio_keys);
         ath79_register_spi(&pb44_spi_data, pb44_spi_info,
                            ARRAY_SIZE(pb44_spi_info));
+        ath79_register_usb();
 }
 
 MIPS_MACHINE(ATH79_MACH_PB44, "PB44", "Atheros PB44 reference board",
diff --git a/arch/mips/ath79/mach-ubnt-xm.c b/arch/mips/ath79/mach-ubnt-xm.c
new file mode 100644
index 00000000000..3c311a53934
--- /dev/null
+++ b/arch/mips/ath79/mach-ubnt-xm.c
@@ -0,0 +1,119 @@
+/*
+ *  Ubiquiti Networks XM (rev 1.0) board support
+ *
+ *  Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
+ *
+ *  Derived from: mach-pb44.c
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/pci.h>
+
+#ifdef CONFIG_PCI
+#include <linux/ath9k_platform.h>
+#include <asm/mach-ath79/pci-ath724x.h>
+#endif /* CONFIG_PCI */
+
+#include "machtypes.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+#include "dev-spi.h"
+
+#define UBNT_XM_GPIO_LED_L1             0
+#define UBNT_XM_GPIO_LED_L2             1
+#define UBNT_XM_GPIO_LED_L3             11
+#define UBNT_XM_GPIO_LED_L4             7
+
+#define UBNT_XM_GPIO_BTN_RESET          12
+
+#define UBNT_XM_KEYS_POLL_INTERVAL      20
+#define UBNT_XM_KEYS_DEBOUNCE_INTERVAL  (3 * UBNT_XM_KEYS_POLL_INTERVAL)
+
+#define UBNT_XM_PCI_IRQ                 48
+#define UBNT_XM_EEPROM_ADDR             (u8 *) KSEG1ADDR(0x1fff1000)
+
+static struct gpio_led ubnt_xm_leds_gpio[] __initdata = {
+        {
+                .name           = "ubnt-xm:red:link1",
+                .gpio           = UBNT_XM_GPIO_LED_L1,
+                .active_low     = 0,
+        }, {
+                .name           = "ubnt-xm:orange:link2",
+                .gpio           = UBNT_XM_GPIO_LED_L2,
+                .active_low     = 0,
+        }, {
+                .name           = "ubnt-xm:green:link3",
+                .gpio           = UBNT_XM_GPIO_LED_L3,
+                .active_low     = 0,
+        }, {
+                .name           = "ubnt-xm:green:link4",
+                .gpio           = UBNT_XM_GPIO_LED_L4,
+                .active_low     = 0,
+        },
+};
+
+static struct gpio_keys_button ubnt_xm_gpio_keys[] __initdata = {
+        {
+                .desc                   = "reset",
+                .type                   = EV_KEY,
+                .code                   = KEY_RESTART,
+                .debounce_interval      = UBNT_XM_KEYS_DEBOUNCE_INTERVAL,
+                .gpio                   = UBNT_XM_GPIO_BTN_RESET,
+                .active_low             = 1,
+        }
+};
+
+static struct spi_board_info ubnt_xm_spi_info[] = {
+        {
+                .bus_num        = 0,
+                .chip_select    = 0,
+                .max_speed_hz   = 25000000,
+                .modalias       = "mx25l6405d",
+        }
+};
+
+static struct ath79_spi_platform_data ubnt_xm_spi_data = {
+        .bus_num                = 0,
+        .num_chipselect         = 1,
+};
+
+#ifdef CONFIG_PCI
+static struct ath9k_platform_data ubnt_xm_eeprom_data;
+
+static struct ath724x_pci_data ubnt_xm_pci_data[] = {
+        {
+                .irq    = UBNT_XM_PCI_IRQ,
+                .pdata  = &ubnt_xm_eeprom_data,
+        },
+};
+#endif /* CONFIG_PCI */
+
+static void __init ubnt_xm_init(void)
+{
+        ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_xm_leds_gpio),
+                                 ubnt_xm_leds_gpio);
+
+        ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL,
+                                        ARRAY_SIZE(ubnt_xm_gpio_keys),
+                                        ubnt_xm_gpio_keys);
+
+        ath79_register_spi(&ubnt_xm_spi_data, ubnt_xm_spi_info,
+                           ARRAY_SIZE(ubnt_xm_spi_info));
+
+#ifdef CONFIG_PCI
+        memcpy(ubnt_xm_eeprom_data.eeprom_data, UBNT_XM_EEPROM_ADDR,
+               sizeof(ubnt_xm_eeprom_data.eeprom_data));
+
+        ath724x_pci_add_data(ubnt_xm_pci_data, ARRAY_SIZE(ubnt_xm_pci_data));
+#endif /* CONFIG_PCI */
+
+}
+
+MIPS_MACHINE(ATH79_MACH_UBNT_XM,
+             "UBNT-XM",
+             "Ubiquiti Networks XM (rev 1.0) board",
+             ubnt_xm_init);
diff --git a/arch/mips/ath79/machtypes.h b/arch/mips/ath79/machtypes.h
index 3940fe470b2..9a1f3826626 100644
--- a/arch/mips/ath79/machtypes.h
+++ b/arch/mips/ath79/machtypes.h
@@ -16,8 +16,10 @@
 
 enum ath79_mach_type {
         ATH79_MACH_GENERIC = 0,
+        ATH79_MACH_AP121,               /* Atheros AP121 reference board */
         ATH79_MACH_AP81,                /* Atheros AP81 reference board */
         ATH79_MACH_PB44,                /* Atheros PB44 reference board */
+        ATH79_MACH_UBNT_XM,             /* Ubiquiti Networks XM board rev 1.0 */
 };
 
 #endif /* _ATH79_MACHTYPE_H */
diff --git a/arch/mips/ath79/setup.c b/arch/mips/ath79/setup.c
index 1cf60e1d9dd..80a7d4023d7 100644
--- a/arch/mips/ath79/setup.c
+++ b/arch/mips/ath79/setup.c
@@ -101,19 +101,31 @@ static void __init ath79_detect_sys_type(void)
         case REV_ID_MAJOR_AR7240:
                 ath79_soc = ATH79_SOC_AR7240;
                 chip = "7240";
-                rev = (id & AR724X_REV_ID_REVISION_MASK);
+                rev = id & AR724X_REV_ID_REVISION_MASK;
                 break;
 
         case REV_ID_MAJOR_AR7241:
                 ath79_soc = ATH79_SOC_AR7241;
                 chip = "7241";
-                rev = (id & AR724X_REV_ID_REVISION_MASK);
+                rev = id & AR724X_REV_ID_REVISION_MASK;
                 break;
 
         case REV_ID_MAJOR_AR7242:
                 ath79_soc = ATH79_SOC_AR7242;
                 chip = "7242";
-                rev = (id & AR724X_REV_ID_REVISION_MASK);
+                rev = id & AR724X_REV_ID_REVISION_MASK;
+                break;
+
+        case REV_ID_MAJOR_AR9330:
+                ath79_soc = ATH79_SOC_AR9330;
+                chip = "9330";
+                rev = id & AR933X_REV_ID_REVISION_MASK;
+                break;
+
+        case REV_ID_MAJOR_AR9331:
+                ath79_soc = ATH79_SOC_AR9331;
+                chip = "9331";
+                rev = id & AR933X_REV_ID_REVISION_MASK;
                 break;
 
         case REV_ID_MAJOR_AR913X:
@@ -137,6 +149,8 @@ static void __init ath79_detect_sys_type(void)
                 panic("ath79: unknown SoC, id:0x%08x", id);
         }
 
+        ath79_soc_rev = rev;
+
         sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
         pr_info("SoC: %s\n", ath79_sys_type);
 }
diff --git a/arch/mips/bcm63xx/Kconfig b/arch/mips/bcm63xx/Kconfig
index fb177d6df06..6b1b9ad8d85 100644
--- a/arch/mips/bcm63xx/Kconfig
+++ b/arch/mips/bcm63xx/Kconfig
@@ -20,6 +20,10 @@ config BCM63XX_CPU_6348
 config BCM63XX_CPU_6358
         bool "support 6358 CPU"
         select HW_HAS_PCI
+
+config BCM63XX_CPU_6368
+        bool "support 6368 CPU"
+        select HW_HAS_PCI
 endmenu
 
 source "arch/mips/bcm63xx/boards/Kconfig"
diff --git a/arch/mips/bcm63xx/boards/board_bcm963xx.c b/arch/mips/bcm63xx/boards/board_bcm963xx.c
index 40b223b603b..e62461f817d 100644
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
@@ -709,15 +709,9 @@ void __init board_prom_init(void)
         char cfe_version[32];
         u32 val;
 
-        /* read base address of boot chip select (0)
-         * 6345 does not have MPI but boots from standard
-         * MIPS Flash address */
-        if (BCMCPU_IS_6345())
-                val = 0x1fc00000;
-        else {
-                val = bcm_mpi_readl(MPI_CSBASE_REG(0));
-                val &= MPI_CSBASE_BASE_MASK;
-        }
+        /* read base address of boot chip select (0) */
+        val = bcm_mpi_readl(MPI_CSBASE_REG(0));
+        val &= MPI_CSBASE_BASE_MASK;
         boot_addr = (u8 *)KSEG1ADDR(val);
 
         /* dump cfe version */
@@ -797,18 +791,6 @@ void __init board_prom_init(void)
         }
 
         bcm_gpio_writel(val, GPIO_MODE_REG);
-
-        /* Generate MAC address for WLAN and
-         * register our SPROM */
-#ifdef CONFIG_SSB_PCIHOST
-        if (!board_get_mac_address(bcm63xx_sprom.il0mac)) {
-                memcpy(bcm63xx_sprom.et0mac, bcm63xx_sprom.il0mac, ETH_ALEN);
-                memcpy(bcm63xx_sprom.et1mac, bcm63xx_sprom.il0mac, ETH_ALEN);
-                if (ssb_arch_register_fallback_sprom(
-                                &bcm63xx_get_fallback_sprom) < 0)
-                        printk(KERN_ERR PFX "failed to register fallback SPROM\n");
-        }
-#endif
 }
 
 /*
@@ -892,13 +874,23 @@ int __init board_register_devices(void)
         if (board.has_dsp)
                 bcm63xx_dsp_register(&board.dsp);
 
-        /* read base address of boot chip select (0) */
-        if (BCMCPU_IS_6345())
-                val = 0x1fc00000;
-        else {
-                val = bcm_mpi_readl(MPI_CSBASE_REG(0));
-                val &= MPI_CSBASE_BASE_MASK;
+        /* Generate MAC address for WLAN and register our SPROM,
+         * do this after registering enet devices
+         */
+#ifdef CONFIG_SSB_PCIHOST
+        if (!board_get_mac_address(bcm63xx_sprom.il0mac)) {
+                memcpy(bcm63xx_sprom.et0mac, bcm63xx_sprom.il0mac, ETH_ALEN);
+                memcpy(bcm63xx_sprom.et1mac, bcm63xx_sprom.il0mac, ETH_ALEN);
+                if (ssb_arch_register_fallback_sprom(
+                                &bcm63xx_get_fallback_sprom) < 0)
+                        pr_err(PFX "failed to register fallback SPROM\n");
         }
+#endif
+
+        /* read base address of boot chip select (0) */
+        val = bcm_mpi_readl(MPI_CSBASE_REG(0));
+        val &= MPI_CSBASE_BASE_MASK;
+
         mtd_resources[0].start = val;
         mtd_resources[0].end = 0x1FFFFFFF;
 
diff --git a/arch/mips/bcm63xx/clk.c b/arch/mips/bcm63xx/clk.c
index 2c68ee9ccee..9d57c71b7b5 100644
--- a/arch/mips/bcm63xx/clk.c
+++ b/arch/mips/bcm63xx/clk.c
@@ -10,6 +10,7 @@
 #include <linux/mutex.h>
 #include <linux/err.h>
 #include <linux/clk.h>
+#include <linux/delay.h>
 #include <bcm63xx_cpu.h>
 #include <bcm63xx_io.h>
 #include <bcm63xx_regs.h>
@@ -113,6 +114,34 @@ static struct clk clk_ephy = {
 };
 
 /*
+ * Ethernet switch clock
+ */
+static void enetsw_set(struct clk *clk, int enable)
+{
+        if (!BCMCPU_IS_6368())
+                return;
+        bcm_hwclock_set(CKCTL_6368_ROBOSW_CLK_EN |
+                        CKCTL_6368_SWPKT_USB_EN |
+                        CKCTL_6368_SWPKT_SAR_EN, enable);
+        if (enable) {
+                u32 val;
+
+                /* reset switch core afer clock change */
+                val = bcm_perf_readl(PERF_SOFTRESET_6368_REG);
+                val &= ~SOFTRESET_6368_ENETSW_MASK;
+                bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
+                msleep(10);
+                val |= SOFTRESET_6368_ENETSW_MASK;
+                bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
+                msleep(10);
+        }
+}
+
+static struct clk clk_enetsw = {
+        .set    = enetsw_set,
+};
+
+/*
  * PCM clock
  */
 static void pcm_set(struct clk *clk, int enable)
@@ -131,9 +160,10 @@ static struct clk clk_pcm = {
  */
 static void usbh_set(struct clk *clk, int enable)
 {
-        if (!BCMCPU_IS_6348())
-                return;
-        bcm_hwclock_set(CKCTL_6348_USBH_EN, enable);
+        if (BCMCPU_IS_6348())
+                bcm_hwclock_set(CKCTL_6348_USBH_EN, enable);
+        else if (BCMCPU_IS_6368())
+                bcm_hwclock_set(CKCTL_6368_USBH_CLK_EN, enable);
 }
 
 static struct clk clk_usbh = {
@@ -162,6 +192,36 @@ static struct clk clk_spi = {
 };
 
 /*
+ * XTM clock
+ */
+static void xtm_set(struct clk *clk, int enable)
+{
+        if (!BCMCPU_IS_6368())
+                return;
+
+        bcm_hwclock_set(CKCTL_6368_SAR_CLK_EN |
+                        CKCTL_6368_SWPKT_SAR_EN, enable);
+
+        if (enable) {
+                u32 val;
+
+                /* reset sar core afer clock change */
+                val = bcm_perf_readl(PERF_SOFTRESET_6368_REG);
+                val &= ~SOFTRESET_6368_SAR_MASK;
+                bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
+                mdelay(1);
+                val |= SOFTRESET_6368_SAR_MASK;
+                bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
+                mdelay(1);
+        }
+}
+
+
+static struct clk clk_xtm = {
+        .set    = xtm_set,
+};
+
+/*
  * Internal peripheral clock
  */
 static struct clk clk_periph = {
@@ -204,12 +264,16 @@ struct clk *clk_get(struct device *dev, const char *id)
                 return &clk_enet0;
         if (!strcmp(id, "enet1"))
                 return &clk_enet1;
+        if (!strcmp(id, "enetsw"))
+                return &clk_enetsw;
         if (!strcmp(id, "ephy"))
                 return &clk_ephy;
         if (!strcmp(id, "usbh"))
                 return &clk_usbh;
         if (!strcmp(id, "spi"))
                 return &clk_spi;
+        if (!strcmp(id, "xtm"))
+                return &clk_xtm;
         if (!strcmp(id, "periph"))
                 return &clk_periph;
         if (BCMCPU_IS_6358() && !strcmp(id, "pcm"))
diff --git a/arch/mips/bcm63xx/cpu.c b/arch/mips/bcm63xx/cpu.c
index 7c7e4d4486c..8f0d6c7725e 100644
--- a/arch/mips/bcm63xx/cpu.c
+++ b/arch/mips/bcm63xx/cpu.c
@@ -29,166 +29,47 @@ static u16 bcm63xx_cpu_rev;
 static unsigned int bcm63xx_cpu_freq;
 static unsigned int bcm63xx_memory_size;
 
-/*
- * 6338 register sets and irqs
- */
-static const unsigned long bcm96338_regs_base[] = {
-        [RSET_DSL_LMEM]         = BCM_6338_DSL_LMEM_BASE,
-        [RSET_PERF]             = BCM_6338_PERF_BASE,
-        [RSET_TIMER]            = BCM_6338_TIMER_BASE,
-        [RSET_WDT]              = BCM_6338_WDT_BASE,
-        [RSET_UART0]            = BCM_6338_UART0_BASE,
-        [RSET_UART1]            = BCM_6338_UART1_BASE,
-        [RSET_GPIO]             = BCM_6338_GPIO_BASE,
-        [RSET_SPI]              = BCM_6338_SPI_BASE,
-        [RSET_OHCI0]            = BCM_6338_OHCI0_BASE,
-        [RSET_OHCI_PRIV]        = BCM_6338_OHCI_PRIV_BASE,
-        [RSET_USBH_PRIV]        = BCM_6338_USBH_PRIV_BASE,
-        [RSET_UDC0]             = BCM_6338_UDC0_BASE,
-        [RSET_MPI]              = BCM_6338_MPI_BASE,
-        [RSET_PCMCIA]           = BCM_6338_PCMCIA_BASE,
-        [RSET_SDRAM]            = BCM_6338_SDRAM_BASE,
-        [RSET_DSL]              = BCM_6338_DSL_BASE,
-        [RSET_ENET0]            = BCM_6338_ENET0_BASE,
-        [RSET_ENET1]            = BCM_6338_ENET1_BASE,
-        [RSET_ENETDMA]          = BCM_6338_ENETDMA_BASE,
-        [RSET_MEMC]             = BCM_6338_MEMC_BASE,
-        [RSET_DDR]              = BCM_6338_DDR_BASE,
+static const unsigned long bcm6338_regs_base[] = {
+        __GEN_CPU_REGS_TABLE(6338)
 };
 
-static const int bcm96338_irqs[] = {
-        [IRQ_TIMER]             = BCM_6338_TIMER_IRQ,
-        [IRQ_UART0]             = BCM_6338_UART0_IRQ,
-        [IRQ_DSL]               = BCM_6338_DSL_IRQ,
-        [IRQ_ENET0]             = BCM_6338_ENET0_IRQ,
-        [IRQ_ENET_PHY]          = BCM_6338_ENET_PHY_IRQ,
-        [IRQ_ENET0_RXDMA]       = BCM_6338_ENET0_RXDMA_IRQ,
-        [IRQ_ENET0_TXDMA]       = BCM_6338_ENET0_TXDMA_IRQ,
+static const int bcm6338_irqs[] = {
+        __GEN_CPU_IRQ_TABLE(6338)
 };
 
-/*
- * 6345 register sets and irqs
- */
-static const unsigned long bcm96345_regs_base[] = {
-        [RSET_DSL_LMEM]         = BCM_6345_DSL_LMEM_BASE,
-        [RSET_PERF]             = BCM_6345_PERF_BASE,
-        [RSET_TIMER]            = BCM_6345_TIMER_BASE,
-        [RSET_WDT]              = BCM_6345_WDT_BASE,
-        [RSET_UART0]            = BCM_6345_UART0_BASE,
-        [RSET_UART1]            = BCM_6345_UART1_BASE,
-        [RSET_GPIO]             = BCM_6345_GPIO_BASE,
-        [RSET_SPI]              = BCM_6345_SPI_BASE,
-        [RSET_UDC0]             = BCM_6345_UDC0_BASE,
-        [RSET_OHCI0]            = BCM_6345_OHCI0_BASE,
-        [RSET_OHCI_PRIV]        = BCM_6345_OHCI_PRIV_BASE,
-        [RSET_USBH_PRIV]        = BCM_6345_USBH_PRIV_BASE,
-        [RSET_MPI]              = BCM_6345_MPI_BASE,
-        [RSET_PCMCIA]           = BCM_6345_PCMCIA_BASE,
-        [RSET_DSL]              = BCM_6345_DSL_BASE,
-        [RSET_ENET0]            = BCM_6345_ENET0_BASE,
-        [RSET_ENET1]            = BCM_6345_ENET1_BASE,
-        [RSET_ENETDMA]          = BCM_6345_ENETDMA_BASE,
-        [RSET_EHCI0]            = BCM_6345_EHCI0_BASE,
-        [RSET_SDRAM]            = BCM_6345_SDRAM_BASE,
-        [RSET_MEMC]             = BCM_6345_MEMC_BASE,
-        [RSET_DDR]              = BCM_6345_DDR_BASE,
+static const unsigned long bcm6345_regs_base[] = {
+        __GEN_CPU_REGS_TABLE(6345)
 };
 
-static const int bcm96345_irqs[] = {
-        [IRQ_TIMER]             = BCM_6345_TIMER_IRQ,
-        [IRQ_UART0]             = BCM_6345_UART0_IRQ,
-        [IRQ_DSL]               = BCM_6345_DSL_IRQ,
-        [IRQ_ENET0]             = BCM_6345_ENET0_IRQ,
-        [IRQ_ENET_PHY]          = BCM_6345_ENET_PHY_IRQ,
-        [IRQ_ENET0_RXDMA]       = BCM_6345_ENET0_RXDMA_IRQ,
-        [IRQ_ENET0_TXDMA]       = BCM_6345_ENET0_TXDMA_IRQ,
+static const int bcm6345_irqs[] = {
+        __GEN_CPU_IRQ_TABLE(6345)
 };
 
-/*
- * 6348 register sets and irqs
- */
-static const unsigned long bcm96348_regs_base[] = {
-        [RSET_DSL_LMEM]         = BCM_6348_DSL_LMEM_BASE,
-        [RSET_PERF]             = BCM_6348_PERF_BASE,
-        [RSET_TIMER]            = BCM_6348_TIMER_BASE,
-        [RSET_WDT]              = BCM_6348_WDT_BASE,
-        [RSET_UART0]            = BCM_6348_UART0_BASE,
-        [RSET_UART1]            = BCM_6348_UART1_BASE,
-        [RSET_GPIO]             = BCM_6348_GPIO_BASE,
-        [RSET_SPI]              = BCM_6348_SPI_BASE,
-        [RSET_OHCI0]            = BCM_6348_OHCI0_BASE,
-        [RSET_OHCI_PRIV]        = BCM_6348_OHCI_PRIV_BASE,
-        [RSET_USBH_PRIV]        = BCM_6348_USBH_PRIV_BASE,
-        [RSET_MPI]              = BCM_6348_MPI_BASE,
-        [RSET_PCMCIA]           = BCM_6348_PCMCIA_BASE,
-        [RSET_SDRAM]            = BCM_6348_SDRAM_BASE,
-        [RSET_DSL]              = BCM_6348_DSL_BASE,
-        [RSET_ENET0]            = BCM_6348_ENET0_BASE,
-        [RSET_ENET1]            = BCM_6348_ENET1_BASE,
-        [RSET_ENETDMA]          = BCM_6348_ENETDMA_BASE,
-        [RSET_MEMC]             = BCM_6348_MEMC_BASE,
-        [RSET_DDR]              = BCM_6348_DDR_BASE,
+static const unsigned long bcm6348_regs_base[] = {
+        __GEN_CPU_REGS_TABLE(6348)
 };
 
-static const int bcm96348_irqs[] = {
-        [IRQ_TIMER]             = BCM_6348_TIMER_IRQ,
-        [IRQ_UART0]             = BCM_6348_UART0_IRQ,
-        [IRQ_DSL]               = BCM_6348_DSL_IRQ,
-        [IRQ_ENET0]             = BCM_6348_ENET0_IRQ,
-        [IRQ_ENET1]             = BCM_6348_ENET1_IRQ,
-        [IRQ_ENET_PHY]          = BCM_6348_ENET_PHY_IRQ,
-        [IRQ_OHCI0]             = BCM_6348_OHCI0_IRQ,
-        [IRQ_PCMCIA]            = BCM_6348_PCMCIA_IRQ,
-        [IRQ_ENET0_RXDMA]       = BCM_6348_ENET0_RXDMA_IRQ,
-        [IRQ_ENET0_TXDMA]       = BCM_6348_ENET0_TXDMA_IRQ,
-        [IRQ_ENET1_RXDMA]       = BCM_6348_ENET1_RXDMA_IRQ,
-        [IRQ_ENET1_TXDMA]       = BCM_6348_ENET1_TXDMA_IRQ,
-        [IRQ_PCI]               = BCM_6348_PCI_IRQ,
+static const int bcm6348_irqs[] = {
+        __GEN_CPU_IRQ_TABLE(6348)
+
 };
 
-/*
- * 6358 register sets and irqs
- */
-static const unsigned long bcm96358_regs_base[] = {
-        [RSET_DSL_LMEM]         = BCM_6358_DSL_LMEM_BASE,
-        [RSET_PERF]             = BCM_6358_PERF_BASE,
-        [RSET_TIMER]            = BCM_6358_TIMER_BASE,
-        [RSET_WDT]              = BCM_6358_WDT_BASE,
-        [RSET_UART0]            = BCM_6358_UART0_BASE,
-        [RSET_UART1]            = BCM_6358_UART1_BASE,
-        [RSET_GPIO]             = BCM_6358_GPIO_BASE,
-        [RSET_SPI]              = BCM_6358_SPI_BASE,
-        [RSET_OHCI0]            = BCM_6358_OHCI0_BASE,
-        [RSET_EHCI0]            = BCM_6358_EHCI0_BASE,
-        [RSET_OHCI_PRIV]        = BCM_6358_OHCI_PRIV_BASE,
-        [RSET_USBH_PRIV]        = BCM_6358_USBH_PRIV_BASE,
-        [RSET_MPI]              = BCM_6358_MPI_BASE,
-        [RSET_PCMCIA]           = BCM_6358_PCMCIA_BASE,
-        [RSET_SDRAM]            = BCM_6358_SDRAM_BASE,
-        [RSET_DSL]              = BCM_6358_DSL_BASE,
-        [RSET_ENET0]            = BCM_6358_ENET0_BASE,
-        [RSET_ENET1]            = BCM_6358_ENET1_BASE,
-        [RSET_ENETDMA]          = BCM_6358_ENETDMA_BASE,
-        [RSET_MEMC]             = BCM_6358_MEMC_BASE,
-        [RSET_DDR]              = BCM_6358_DDR_BASE,
+static const unsigned long bcm6358_regs_base[] = {
+        __GEN_CPU_REGS_TABLE(6358)
+};
+
+static const int bcm6358_irqs[] = {
+        __GEN_CPU_IRQ_TABLE(6358)
+
 };
 
-static const int bcm96358_irqs[] = {
-        [IRQ_TIMER]             = BCM_6358_TIMER_IRQ,
-        [IRQ_UART0]             = BCM_6358_UART0_IRQ,
-        [IRQ_UART1]             = BCM_6358_UART1_IRQ,
-        [IRQ_DSL]               = BCM_6358_DSL_IRQ,
-        [IRQ_ENET0]             = BCM_6358_ENET0_IRQ,
-        [IRQ_ENET1]             = BCM_6358_ENET1_IRQ,
-        [IRQ_ENET_PHY]          = BCM_6358_ENET_PHY_IRQ,
-        [IRQ_OHCI0]             = BCM_6358_OHCI0_IRQ,
-        [IRQ_EHCI0]             = BCM_6358_EHCI0_IRQ,
-        [IRQ_PCMCIA]            = BCM_6358_PCMCIA_IRQ,
-        [IRQ_ENET0_RXDMA]       = BCM_6358_ENET0_RXDMA_IRQ,
-        [IRQ_ENET0_TXDMA]       = BCM_6358_ENET0_TXDMA_IRQ,
-        [IRQ_ENET1_RXDMA]       = BCM_6358_ENET1_RXDMA_IRQ,
-        [IRQ_ENET1_TXDMA]       = BCM_6358_ENET1_TXDMA_IRQ,
-        [IRQ_PCI]               = BCM_6358_PCI_IRQ,
+static const unsigned long bcm6368_regs_base[] = {
+        __GEN_CPU_REGS_TABLE(6368)
+};
+
+static const int bcm6368_irqs[] = {
+        __GEN_CPU_IRQ_TABLE(6368)
+
 };
 
 u16 __bcm63xx_get_cpu_id(void)
@@ -217,20 +98,19 @@ unsigned int bcm63xx_get_memory_size(void)
 
 static unsigned int detect_cpu_clock(void)
 {
-        unsigned int tmp, n1 = 0, n2 = 0, m1 = 0;
-
-        /* BCM6338 has a fixed 240 Mhz frequency */
-        if (BCMCPU_IS_6338())
+        switch (bcm63xx_get_cpu_id()) {
+        case BCM6338_CPU_ID:
+                /* BCM6338 has a fixed 240 Mhz frequency */
                 return 240000000;
 
-        /* BCM6345 has a fixed 140Mhz frequency */
-        if (BCMCPU_IS_6345())
+        case BCM6345_CPU_ID:
+                /* BCM6345 has a fixed 140Mhz frequency */
                 return 140000000;
 
-        /*
-         * frequency depends on PLL configuration:
-         */
-        if (BCMCPU_IS_6348()) {
+        case BCM6348_CPU_ID:
+        {
+                unsigned int tmp, n1, n2, m1;
+
                 /* 16MHz * (N1 + 1) * (N2 + 2) / (M1_CPU + 1) */
                 tmp = bcm_perf_readl(PERF_MIPSPLLCTL_REG);
                 n1 = (tmp & MIPSPLLCTL_N1_MASK) >> MIPSPLLCTL_N1_SHIFT;
@@ -239,17 +119,47 @@ static unsigned int detect_cpu_clock(void)
                 n1 += 1;
                 n2 += 2;
                 m1 += 1;
+                return (16 * 1000000 * n1 * n2) / m1;
         }
 
-        if (BCMCPU_IS_6358()) {
+        case BCM6358_CPU_ID:
+        {
+                unsigned int tmp, n1, n2, m1;
+
                 /* 16MHz * N1 * N2 / M1_CPU */
                 tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_REG);
                 n1 = (tmp & DMIPSPLLCFG_N1_MASK) >> DMIPSPLLCFG_N1_SHIFT;
                 n2 = (tmp & DMIPSPLLCFG_N2_MASK) >> DMIPSPLLCFG_N2_SHIFT;
                 m1 = (tmp & DMIPSPLLCFG_M1_MASK) >> DMIPSPLLCFG_M1_SHIFT;
+                return (16 * 1000000 * n1 * n2) / m1;
         }
 
-        return (16 * 1000000 * n1 * n2) / m1;
+        case BCM6368_CPU_ID:
+        {
+                unsigned int tmp, p1, p2, ndiv, m1;
+
+                /* (64MHz / P1) * P2 * NDIV / M1_CPU */
+                tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_6368_REG);
+
+                p1 = (tmp & DMIPSPLLCFG_6368_P1_MASK) >>
+                        DMIPSPLLCFG_6368_P1_SHIFT;
+
+                p2 = (tmp & DMIPSPLLCFG_6368_P2_MASK) >>
+                        DMIPSPLLCFG_6368_P2_SHIFT;
+
+                ndiv = (tmp & DMIPSPLLCFG_6368_NDIV_MASK) >>
+                        DMIPSPLLCFG_6368_NDIV_SHIFT;
+
+                tmp = bcm_ddr_readl(DDR_DMIPSPLLDIV_6368_REG);
+                m1 = (tmp & DMIPSPLLDIV_6368_MDIV_MASK) >>
+                        DMIPSPLLDIV_6368_MDIV_SHIFT;
+
+                return (((64 * 1000000) / p1) * p2 * ndiv) / m1;
+        }
+
+        default:
+                BUG();
+        }
 }
 
 /*
@@ -260,8 +170,10 @@ static unsigned int detect_memory_size(void)
         unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
         u32 val;
 
-        if (BCMCPU_IS_6345())
-                return (8 * 1024 * 1024);
+        if (BCMCPU_IS_6345()) {
+                val = bcm_sdram_readl(SDRAM_MBASE_REG);
+                return (val * 8 * 1024 * 1024);
+        }
 
         if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) {
                 val = bcm_sdram_readl(SDRAM_CFG_REG);
@@ -271,7 +183,7 @@ static unsigned int detect_memory_size(void)
                 banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1;
         }
 
-        if (BCMCPU_IS_6358()) {
+        if (BCMCPU_IS_6358() || BCMCPU_IS_6368()) {
                 val = bcm_memc_readl(MEMC_CFG_REG);
                 rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT;
                 cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT;
@@ -301,24 +213,33 @@ void __init bcm63xx_cpu_init(void)
         case CPU_BMIPS3300:
                 if ((read_c0_prid() & 0xff00) == PRID_IMP_BMIPS3300_ALT) {
                         expected_cpu_id = BCM6348_CPU_ID;
-                        bcm63xx_regs_base = bcm96348_regs_base;
-                        bcm63xx_irqs = bcm96348_irqs;
+                        bcm63xx_regs_base = bcm6348_regs_base;
+                        bcm63xx_irqs = bcm6348_irqs;
                 } else {
                         __cpu_name[cpu] = "Broadcom BCM6338";
                         expected_cpu_id = BCM6338_CPU_ID;
-                        bcm63xx_regs_base = bcm96338_regs_base;
-                        bcm63xx_irqs = bcm96338_irqs;
+                        bcm63xx_regs_base = bcm6338_regs_base;
+                        bcm63xx_irqs = bcm6338_irqs;
                 }
                 break;
         case CPU_BMIPS32:
                 expected_cpu_id = BCM6345_CPU_ID;
-                bcm63xx_regs_base = bcm96345_regs_base;
-                bcm63xx_irqs = bcm96345_irqs;
+                bcm63xx_regs_base = bcm6345_regs_base;
+                bcm63xx_irqs = bcm6345_irqs;
                 break;
         case CPU_BMIPS4350:
-                expected_cpu_id = BCM6358_CPU_ID;
-                bcm63xx_regs_base = bcm96358_regs_base;
-                bcm63xx_irqs = bcm96358_irqs;
+                switch (read_c0_prid() & 0xf0) {
+                case 0x10:
+                        expected_cpu_id = BCM6358_CPU_ID;
+                        bcm63xx_regs_base = bcm6358_regs_base;
+                        bcm63xx_irqs = bcm6358_irqs;
+                        break;
+                case 0x30:
+                        expected_cpu_id = BCM6368_CPU_ID;
+                        bcm63xx_regs_base = bcm6368_regs_base;
+                        bcm63xx_irqs = bcm6368_irqs;
+                        break;
+                }
                 break;
         }
 
diff --git a/arch/mips/bcm63xx/dev-uart.c b/arch/mips/bcm63xx/dev-uart.c
index c2963da0253..d6e42c60832 100644
--- a/arch/mips/bcm63xx/dev-uart.c
+++ b/arch/mips/bcm63xx/dev-uart.c
@@ -54,7 +54,7 @@ int __init bcm63xx_uart_register(unsigned int id)
         if (id >= ARRAY_SIZE(bcm63xx_uart_devices))
                 return -ENODEV;
 
-        if (id == 1 && !BCMCPU_IS_6358())
+        if (id == 1 && (!BCMCPU_IS_6358() && !BCMCPU_IS_6368()))
                 return -ENODEV;
 
         if (id == 0) {
diff --git a/arch/mips/bcm63xx/gpio.c b/arch/mips/bcm63xx/gpio.c
index f560fe7d38d..a6c2135dbf3 100644
--- a/arch/mips/bcm63xx/gpio.c
+++ b/arch/mips/bcm63xx/gpio.c
@@ -4,7 +4,7 @@
  * for more details.
  *
  * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
- * Copyright (C) 2008 Florian Fainelli <florian@openwrt.org>
+ * Copyright (C) 2008-2011 Florian Fainelli <florian@openwrt.org>
  */
 
 #include <linux/kernel.h>
@@ -18,6 +18,34 @@
 #include <bcm63xx_io.h>
 #include <bcm63xx_regs.h>
 
+#ifndef BCMCPU_RUNTIME_DETECT
+#define gpio_out_low_reg        GPIO_DATA_LO_REG
+#ifdef CONFIG_BCM63XX_CPU_6345
+#ifdef gpio_out_low_reg
+#undef gpio_out_low_reg
+#define gpio_out_low_reg        GPIO_DATA_LO_REG_6345
+#endif /* gpio_out_low_reg */
+#endif /* CONFIG_BCM63XX_CPU_6345 */
+
+static inline void bcm63xx_gpio_out_low_reg_init(void)
+{
+}
+#else /* ! BCMCPU_RUNTIME_DETECT */
+static u32 gpio_out_low_reg;
+
+static void bcm63xx_gpio_out_low_reg_init(void)
+{
+        switch (bcm63xx_get_cpu_id()) {
+        case BCM6345_CPU_ID:
+                gpio_out_low_reg = GPIO_DATA_LO_REG_6345;
+                break;
+        default:
+                gpio_out_low_reg = GPIO_DATA_LO_REG;
+                break;
+        }
+}
+#endif /* ! BCMCPU_RUNTIME_DETECT */
+
 static DEFINE_SPINLOCK(bcm63xx_gpio_lock);
 static u32 gpio_out_low, gpio_out_high;
 
@@ -33,7 +61,7 @@ static void bcm63xx_gpio_set(struct gpio_chip *chip,
                 BUG();
 
         if (gpio < 32) {
-                reg = GPIO_DATA_LO_REG;
+                reg = gpio_out_low_reg;
                 mask = 1 << gpio;
                 v = &gpio_out_low;
         } else {
@@ -60,7 +88,7 @@ static int bcm63xx_gpio_get(struct gpio_chip *chip, unsigned gpio)
                 BUG();
 
         if (gpio < 32) {
-                reg = GPIO_DATA_LO_REG;
+                reg = gpio_out_low_reg;
                 mask = 1 << gpio;
         } else {
                 reg = GPIO_DATA_HI_REG;
@@ -125,8 +153,11 @@ static struct gpio_chip bcm63xx_gpio_chip = {
 
 int __init bcm63xx_gpio_init(void)
 {
-        gpio_out_low = bcm_gpio_readl(GPIO_DATA_LO_REG);
-        gpio_out_high = bcm_gpio_readl(GPIO_DATA_HI_REG);
+        bcm63xx_gpio_out_low_reg_init();
+
+        gpio_out_low = bcm_gpio_readl(gpio_out_low_reg);
+        if (!BCMCPU_IS_6345())
+                gpio_out_high = bcm_gpio_readl(GPIO_DATA_HI_REG);
         bcm63xx_gpio_chip.ngpio = bcm63xx_gpio_count();
         pr_info("registering %d GPIOs\n", bcm63xx_gpio_chip.ngpio);
 
diff --git a/arch/mips/bcm63xx/irq.c b/arch/mips/bcm63xx/irq.c
index 162e11b4ed7..9a216a451d9 100644
--- a/arch/mips/bcm63xx/irq.c
+++ b/arch/mips/bcm63xx/irq.c
@@ -19,19 +19,187 @@
 #include <bcm63xx_io.h>
 #include <bcm63xx_irq.h>
 
+static void __dispatch_internal(void) __maybe_unused;
+static void __dispatch_internal_64(void) __maybe_unused;
+static void __internal_irq_mask_32(unsigned int irq) __maybe_unused;
+static void __internal_irq_mask_64(unsigned int irq) __maybe_unused;
+static void __internal_irq_unmask_32(unsigned int irq) __maybe_unused;
+static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused;
+
+#ifndef BCMCPU_RUNTIME_DETECT
+#ifdef CONFIG_BCM63XX_CPU_6338
+#define irq_stat_reg            PERF_IRQSTAT_6338_REG
+#define irq_mask_reg            PERF_IRQMASK_6338_REG
+#define irq_bits                32
+#define is_ext_irq_cascaded     0
+#define ext_irq_start           0
+#define ext_irq_end             0
+#define ext_irq_count           4
+#define ext_irq_cfg_reg1        PERF_EXTIRQ_CFG_REG_6338
+#define ext_irq_cfg_reg2        0
+#endif
+#ifdef CONFIG_BCM63XX_CPU_6345
+#define irq_stat_reg            PERF_IRQSTAT_6345_REG
+#define irq_mask_reg            PERF_IRQMASK_6345_REG
+#define irq_bits                32
+#define is_ext_irq_cascaded     0
+#define ext_irq_start           0
+#define ext_irq_end             0
+#define ext_irq_count           0
+#define ext_irq_cfg_reg1        0
+#define ext_irq_cfg_reg2        0
+#endif
+#ifdef CONFIG_BCM63XX_CPU_6348
+#define irq_stat_reg            PERF_IRQSTAT_6348_REG
+#define irq_mask_reg            PERF_IRQMASK_6348_REG
+#define irq_bits                32
+#define is_ext_irq_cascaded     0
+#define ext_irq_start           0
+#define ext_irq_end             0
+#define ext_irq_count           4
+#define ext_irq_cfg_reg1        PERF_EXTIRQ_CFG_REG_6348
+#define ext_irq_cfg_reg2        0
+#endif
+#ifdef CONFIG_BCM63XX_CPU_6358
+#define irq_stat_reg            PERF_IRQSTAT_6358_REG
+#define irq_mask_reg            PERF_IRQMASK_6358_REG
+#define irq_bits                32
+#define is_ext_irq_cascaded     1
+#define ext_irq_start           (BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE)
+#define ext_irq_end             (BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE)
+#define ext_irq_count           4
+#define ext_irq_cfg_reg1        PERF_EXTIRQ_CFG_REG_6358
+#define ext_irq_cfg_reg2        0
+#endif
+#ifdef CONFIG_BCM63XX_CPU_6368
+#define irq_stat_reg            PERF_IRQSTAT_6368_REG
+#define irq_mask_reg            PERF_IRQMASK_6368_REG
+#define irq_bits                64
+#define is_ext_irq_cascaded     1
+#define ext_irq_start           (BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE)
+#define ext_irq_end             (BCM_6368_EXT_IRQ5 - IRQ_INTERNAL_BASE)
+#define ext_irq_count           6
+#define ext_irq_cfg_reg1        PERF_EXTIRQ_CFG_REG_6368
+#define ext_irq_cfg_reg2        PERF_EXTIRQ_CFG_REG2_6368
+#endif
+
+#if irq_bits == 32
+#define dispatch_internal                       __dispatch_internal
+#define internal_irq_mask                       __internal_irq_mask_32
+#define internal_irq_unmask                     __internal_irq_unmask_32
+#else
+#define dispatch_internal                       __dispatch_internal_64
+#define internal_irq_mask                       __internal_irq_mask_64
+#define internal_irq_unmask                     __internal_irq_unmask_64
+#endif
+
+#define irq_stat_addr   (bcm63xx_regset_address(RSET_PERF) + irq_stat_reg)
+#define irq_mask_addr   (bcm63xx_regset_address(RSET_PERF) + irq_mask_reg)
+
+static inline void bcm63xx_init_irq(void)
+{
+}
+#else /* ! BCMCPU_RUNTIME_DETECT */
+
+static u32 irq_stat_addr, irq_mask_addr;
+static void (*dispatch_internal)(void);
+static int is_ext_irq_cascaded;
+static unsigned int ext_irq_count;
+static unsigned int ext_irq_start, ext_irq_end;
+static unsigned int ext_irq_cfg_reg1, ext_irq_cfg_reg2;
+static void (*internal_irq_mask)(unsigned int irq);
+static void (*internal_irq_unmask)(unsigned int irq);
+
+static void bcm63xx_init_irq(void)
+{
+        int irq_bits;
+
+        irq_stat_addr = bcm63xx_regset_address(RSET_PERF);
+        irq_mask_addr = bcm63xx_regset_address(RSET_PERF);
+
+        switch (bcm63xx_get_cpu_id()) {
+        case BCM6338_CPU_ID:
+                irq_stat_addr += PERF_IRQSTAT_6338_REG;
+                irq_mask_addr += PERF_IRQMASK_6338_REG;
+                irq_bits = 32;
+                break;
+        case BCM6345_CPU_ID:
+                irq_stat_addr += PERF_IRQSTAT_6345_REG;
+                irq_mask_addr += PERF_IRQMASK_6345_REG;
+                irq_bits = 32;
+                break;
+        case BCM6348_CPU_ID:
+                irq_stat_addr += PERF_IRQSTAT_6348_REG;
+                irq_mask_addr += PERF_IRQMASK_6348_REG;
+                irq_bits = 32;
+                ext_irq_count = 4;
+                ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6348;
+                break;
+        case BCM6358_CPU_ID:
+                irq_stat_addr += PERF_IRQSTAT_6358_REG;
+                irq_mask_addr += PERF_IRQMASK_6358_REG;
+                irq_bits = 32;
+                ext_irq_count = 4;
+                is_ext_irq_cascaded = 1;
+                ext_irq_start = BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE;
+                ext_irq_end = BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE;
+                ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358;
+                break;
+        case BCM6368_CPU_ID:
+                irq_stat_addr += PERF_IRQSTAT_6368_REG;
+                irq_mask_addr += PERF_IRQMASK_6368_REG;
+                irq_bits = 64;
+                ext_irq_count = 6;
+                is_ext_irq_cascaded = 1;
+                ext_irq_start = BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE;
+                ext_irq_end = BCM_6368_EXT_IRQ5 - IRQ_INTERNAL_BASE;
+                ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6368;
+                ext_irq_cfg_reg2 = PERF_EXTIRQ_CFG_REG2_6368;
+                break;
+        default:
+                BUG();
+        }
+
+        if (irq_bits == 32) {
+                dispatch_internal = __dispatch_internal;
+                internal_irq_mask = __internal_irq_mask_32;
+                internal_irq_unmask = __internal_irq_unmask_32;
+        } else {
+                dispatch_internal = __dispatch_internal_64;
+                internal_irq_mask = __internal_irq_mask_64;
+                internal_irq_unmask = __internal_irq_unmask_64;
+        }
+}
+#endif /* ! BCMCPU_RUNTIME_DETECT */
+
+static inline u32 get_ext_irq_perf_reg(int irq)
+{
+        if (irq < 4)
+                return ext_irq_cfg_reg1;
+        return ext_irq_cfg_reg2;
+}
+
+static inline void handle_internal(int intbit)
+{
+        if (is_ext_irq_cascaded &&
+            intbit >= ext_irq_start && intbit <= ext_irq_end)
+                do_IRQ(intbit - ext_irq_start + IRQ_EXTERNAL_BASE);
+        else
+                do_IRQ(intbit + IRQ_INTERNAL_BASE);
+}
+
 /*
  * dispatch internal devices IRQ (uart, enet, watchdog, ...). do not
  * prioritize any interrupt relatively to another. the static counter
  * will resume the loop where it ended the last time we left this
  * function.
  */
-static void bcm63xx_irq_dispatch_internal(void)
+static void __dispatch_internal(void)
 {
         u32 pending;
         static int i;
 
-        pending = bcm_perf_readl(PERF_IRQMASK_REG) &
-                bcm_perf_readl(PERF_IRQSTAT_REG);
+        pending = bcm_readl(irq_stat_addr) & bcm_readl(irq_mask_addr);
 
         if (!pending)
                 return ;
@@ -41,7 +209,28 @@ static void bcm63xx_irq_dispatch_internal(void)
 
                 i = (i + 1) & 0x1f;
                 if (pending & (1 << to_call)) {
-                        do_IRQ(to_call + IRQ_INTERNAL_BASE);
+                        handle_internal(to_call);
+                        break;
+                }
+        }
+}
+
+static void __dispatch_internal_64(void)
+{
+        u64 pending;
+        static int i;
+
+        pending = bcm_readq(irq_stat_addr) & bcm_readq(irq_mask_addr);
+
+        if (!pending)
+                return ;
+
+        while (1) {
+                int to_call = i;
+
+                i = (i + 1) & 0x3f;
+                if (pending & (1ull << to_call)) {
+                        handle_internal(to_call);
                         break;
                 }
         }
@@ -60,15 +249,17 @@ asmlinkage void plat_irq_dispatch(void)
                 if (cause & CAUSEF_IP7)
                         do_IRQ(7);
                 if (cause & CAUSEF_IP2)
-                        bcm63xx_irq_dispatch_internal();
-                if (cause & CAUSEF_IP3)
-                        do_IRQ(IRQ_EXT_0);
-                if (cause & CAUSEF_IP4)
-                        do_IRQ(IRQ_EXT_1);
-                if (cause & CAUSEF_IP5)
-                        do_IRQ(IRQ_EXT_2);
-                if (cause & CAUSEF_IP6)
-                        do_IRQ(IRQ_EXT_3);
+                        dispatch_internal();
+                if (!is_ext_irq_cascaded) {
+                        if (cause & CAUSEF_IP3)
+                                do_IRQ(IRQ_EXT_0);
+                        if (cause & CAUSEF_IP4)
+                                do_IRQ(IRQ_EXT_1);
+                        if (cause & CAUSEF_IP5)
+                                do_IRQ(IRQ_EXT_2);
+                        if (cause & CAUSEF_IP6)
+                                do_IRQ(IRQ_EXT_3);
+                }
         } while (1);
 }
 
@@ -76,24 +267,50 @@ asmlinkage void plat_irq_dispatch(void)
  * internal IRQs operations: only mask/unmask on PERF irq mask
  * register.
  */
-static inline void bcm63xx_internal_irq_mask(struct irq_data *d)
+static void __internal_irq_mask_32(unsigned int irq)
 {
-        unsigned int irq = d->irq - IRQ_INTERNAL_BASE;
         u32 mask;
 
-        mask = bcm_perf_readl(PERF_IRQMASK_REG);
+        mask = bcm_readl(irq_mask_addr);
         mask &= ~(1 << irq);
-        bcm_perf_writel(mask, PERF_IRQMASK_REG);
+        bcm_writel(mask, irq_mask_addr);
 }
 
-static void bcm63xx_internal_irq_unmask(struct irq_data *d)
+static void __internal_irq_mask_64(unsigned int irq)
+{
+        u64 mask;
+
+        mask = bcm_readq(irq_mask_addr);
+        mask &= ~(1ull << irq);
+        bcm_writeq(mask, irq_mask_addr);
+}
+
+static void __internal_irq_unmask_32(unsigned int irq)
 {
-        unsigned int irq = d->irq - IRQ_INTERNAL_BASE;
         u32 mask;
 
-        mask = bcm_perf_readl(PERF_IRQMASK_REG);
+        mask = bcm_readl(irq_mask_addr);
         mask |= (1 << irq);
-        bcm_perf_writel(mask, PERF_IRQMASK_REG);
+        bcm_writel(mask, irq_mask_addr);
+}
+
+static void __internal_irq_unmask_64(unsigned int irq)
+{
+        u64 mask;
+
+        mask = bcm_readq(irq_mask_addr);
+        mask |= (1ull << irq);
+        bcm_writeq(mask, irq_mask_addr);
+}
+
+static void bcm63xx_internal_irq_mask(struct irq_data *d)
+{
+        internal_irq_mask(d->irq - IRQ_INTERNAL_BASE);
+}
+
+static void bcm63xx_internal_irq_unmask(struct irq_data *d)
+{
+        internal_irq_unmask(d->irq - IRQ_INTERNAL_BASE);
 }
 
 /*
@@ -102,94 +319,131 @@ static void bcm63xx_internal_irq_unmask(struct irq_data *d)
  */
 static void bcm63xx_external_irq_mask(struct irq_data *d)
 {
-        unsigned int irq = d->irq - IRQ_EXT_BASE;
-        u32 reg;
+        unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
+        u32 reg, regaddr;
 
-        reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
-        reg &= ~EXTIRQ_CFG_MASK(irq);
-        bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
+        regaddr = get_ext_irq_perf_reg(irq);
+        reg = bcm_perf_readl(regaddr);
+
+        if (BCMCPU_IS_6348())
+                reg &= ~EXTIRQ_CFG_MASK_6348(irq % 4);
+        else
+                reg &= ~EXTIRQ_CFG_MASK(irq % 4);
+
+        bcm_perf_writel(reg, regaddr);
+        if (is_ext_irq_cascaded)
+                internal_irq_mask(irq + ext_irq_start);
 }
 
 static void bcm63xx_external_irq_unmask(struct irq_data *d)
 {
-        unsigned int irq = d->irq - IRQ_EXT_BASE;
-        u32 reg;
+        unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
+        u32 reg, regaddr;
 
-        reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
-        reg |= EXTIRQ_CFG_MASK(irq);
-        bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
+        regaddr = get_ext_irq_perf_reg(irq);
+        reg = bcm_perf_readl(regaddr);
+
+        if (BCMCPU_IS_6348())
+                reg |= EXTIRQ_CFG_MASK_6348(irq % 4);
+        else
+                reg |= EXTIRQ_CFG_MASK(irq % 4);
+
+        bcm_perf_writel(reg, regaddr);
+
+        if (is_ext_irq_cascaded)
+                internal_irq_unmask(irq + ext_irq_start);
 }
 
 static void bcm63xx_external_irq_clear(struct irq_data *d)
 {
-        unsigned int irq = d->irq - IRQ_EXT_BASE;
-        u32 reg;
+        unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
+        u32 reg, regaddr;
 
-        reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
-        reg |= EXTIRQ_CFG_CLEAR(irq);
-        bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
-}
+        regaddr = get_ext_irq_perf_reg(irq);
+        reg = bcm_perf_readl(regaddr);
 
-static unsigned int bcm63xx_external_irq_startup(struct irq_data *d)
-{
-        set_c0_status(0x100 << (d->irq - IRQ_MIPS_BASE));
-        irq_enable_hazard();
-        bcm63xx_external_irq_unmask(d);
-        return 0;
-}
+        if (BCMCPU_IS_6348())
+                reg |= EXTIRQ_CFG_CLEAR_6348(irq % 4);
+        else
+                reg |= EXTIRQ_CFG_CLEAR(irq % 4);
 
-static void bcm63xx_external_irq_shutdown(struct irq_data *d)
-{
-        bcm63xx_external_irq_mask(d);
-        clear_c0_status(0x100 << (d->irq - IRQ_MIPS_BASE));
-        irq_disable_hazard();
+        bcm_perf_writel(reg, regaddr);
 }
 
 static int bcm63xx_external_irq_set_type(struct irq_data *d,
                                          unsigned int flow_type)
 {
-        unsigned int irq = d->irq - IRQ_EXT_BASE;
-        u32 reg;
+        unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
+        u32 reg, regaddr;
+        int levelsense, sense, bothedge;
 
         flow_type &= IRQ_TYPE_SENSE_MASK;
 
         if (flow_type == IRQ_TYPE_NONE)
                 flow_type = IRQ_TYPE_LEVEL_LOW;
 
-        reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
+        levelsense = sense = bothedge = 0;
         switch (flow_type) {
         case IRQ_TYPE_EDGE_BOTH:
-                reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
-                reg |= EXTIRQ_CFG_BOTHEDGE(irq);
+                bothedge = 1;
                 break;
 
         case IRQ_TYPE_EDGE_RISING:
-                reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
-                reg |= EXTIRQ_CFG_SENSE(irq);
-                reg &= ~EXTIRQ_CFG_BOTHEDGE(irq);
+                sense = 1;
                 break;
 
         case IRQ_TYPE_EDGE_FALLING:
-                reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
-                reg &= ~EXTIRQ_CFG_SENSE(irq);
-                reg &= ~EXTIRQ_CFG_BOTHEDGE(irq);
                 break;
 
         case IRQ_TYPE_LEVEL_HIGH:
-                reg |= EXTIRQ_CFG_LEVELSENSE(irq);
-                reg |= EXTIRQ_CFG_SENSE(irq);
+                levelsense = 1;
+                sense = 1;
                 break;
 
         case IRQ_TYPE_LEVEL_LOW:
-                reg |= EXTIRQ_CFG_LEVELSENSE(irq);
-                reg &= ~EXTIRQ_CFG_SENSE(irq);
+                levelsense = 1;
                 break;
 
         default:
                 printk(KERN_ERR "bogus flow type combination given !\n");
                 return -EINVAL;
         }
-        bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
+
+        regaddr = get_ext_irq_perf_reg(irq);
+        reg = bcm_perf_readl(regaddr);
+        irq %= 4;
+
+        if (BCMCPU_IS_6348()) {
+                if (levelsense)
+                        reg |= EXTIRQ_CFG_LEVELSENSE_6348(irq);
+                else
+                        reg &= ~EXTIRQ_CFG_LEVELSENSE_6348(irq);
+                if (sense)
+                        reg |= EXTIRQ_CFG_SENSE_6348(irq);
+                else
+                        reg &= ~EXTIRQ_CFG_SENSE_6348(irq);
+                if (bothedge)
+                        reg |= EXTIRQ_CFG_BOTHEDGE_6348(irq);
+                else
+                        reg &= ~EXTIRQ_CFG_BOTHEDGE_6348(irq);
+        }
+
+        if (BCMCPU_IS_6338() || BCMCPU_IS_6358() || BCMCPU_IS_6368()) {
+                if (levelsense)
+                        reg |= EXTIRQ_CFG_LEVELSENSE(irq);
+                else
+                        reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
+                if (sense)
+                        reg |= EXTIRQ_CFG_SENSE(irq);
+                else
+                        reg &= ~EXTIRQ_CFG_SENSE(irq);
+                if (bothedge)
+                        reg |= EXTIRQ_CFG_BOTHEDGE(irq);
+                else
+                        reg &= ~EXTIRQ_CFG_BOTHEDGE(irq);
+        }
+
+        bcm_perf_writel(reg, regaddr);
 
         irqd_set_trigger_type(d, flow_type);
         if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
@@ -208,9 +462,6 @@ static struct irq_chip bcm63xx_internal_irq_chip = {
 
 static struct irq_chip bcm63xx_external_irq_chip = {
         .name           = "bcm63xx_epic",
-        .irq_startup    = bcm63xx_external_irq_startup,
-        .irq_shutdown   = bcm63xx_external_irq_shutdown,
-
         .irq_ack        = bcm63xx_external_irq_clear,
 
         .irq_mask       = bcm63xx_external_irq_mask,
@@ -225,18 +476,30 @@ static struct irqaction cpu_ip2_cascade_action = {
         .flags          = IRQF_NO_THREAD,
 };
 
+static struct irqaction cpu_ext_cascade_action = {
+        .handler        = no_action,
+        .name           = "cascade_extirq",
+        .flags          = IRQF_NO_THREAD,
+};
+
 void __init arch_init_irq(void)
 {
         int i;
 
+        bcm63xx_init_irq();
         mips_cpu_irq_init();
         for (i = IRQ_INTERNAL_BASE; i < NR_IRQS; ++i)
                 irq_set_chip_and_handler(i, &bcm63xx_internal_irq_chip,
                                          handle_level_irq);
 
-        for (i = IRQ_EXT_BASE; i < IRQ_EXT_BASE + 4; ++i)
+        for (i = IRQ_EXTERNAL_BASE; i < IRQ_EXTERNAL_BASE + ext_irq_count; ++i)
                 irq_set_chip_and_handler(i, &bcm63xx_external_irq_chip,
                                          handle_edge_irq);
 
-        setup_irq(IRQ_MIPS_BASE + 2, &cpu_ip2_cascade_action);
+        if (!is_ext_irq_cascaded) {
+                for (i = 3; i < 3 + ext_irq_count; ++i)
+                        setup_irq(MIPS_CPU_IRQ_BASE + i, &cpu_ext_cascade_action);
+        }
+
+        setup_irq(MIPS_CPU_IRQ_BASE + 2, &cpu_ip2_cascade_action);
 }
diff --git a/arch/mips/bcm63xx/prom.c b/arch/mips/bcm63xx/prom.c
index be252efa075..99d7f405cbe 100644
--- a/arch/mips/bcm63xx/prom.c
+++ b/arch/mips/bcm63xx/prom.c
@@ -32,9 +32,12 @@ void __init prom_init(void)
                 mask = CKCTL_6345_ALL_SAFE_EN;
         else if (BCMCPU_IS_6348())
                 mask = CKCTL_6348_ALL_SAFE_EN;
-        else
-                /* BCMCPU_IS_6358() */
+        else if (BCMCPU_IS_6358())
                 mask = CKCTL_6358_ALL_SAFE_EN;
+        else if (BCMCPU_IS_6368())
+                mask = CKCTL_6368_ALL_SAFE_EN;
+        else
+                mask = 0;
 
         reg = bcm_perf_readl(PERF_CKCTL_REG);
         reg &= ~mask;
diff --git a/arch/mips/bcm63xx/setup.c b/arch/mips/bcm63xx/setup.c
index d0056598fbf..d209f85d87b 100644
--- a/arch/mips/bcm63xx/setup.c
+++ b/arch/mips/bcm63xx/setup.c
@@ -63,13 +63,33 @@ static void bcm6348_a1_reboot(void)
 
 void bcm63xx_machine_reboot(void)
 {
-        u32 reg;
+        u32 reg, perf_regs[2] = { 0, 0 };
+        unsigned int i;
 
         /* mask and clear all external irq */
-        reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
-        reg &= ~EXTIRQ_CFG_MASK_ALL;
-        reg |= EXTIRQ_CFG_CLEAR_ALL;
-        bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
+        switch (bcm63xx_get_cpu_id()) {
+        case BCM6338_CPU_ID:
+                perf_regs[0] = PERF_EXTIRQ_CFG_REG_6338;
+                break;
+        case BCM6348_CPU_ID:
+                perf_regs[0] = PERF_EXTIRQ_CFG_REG_6348;
+                break;
+        case BCM6358_CPU_ID:
+                perf_regs[0] = PERF_EXTIRQ_CFG_REG_6358;
+                break;
+        }
+
+        for (i = 0; i < 2; i++) {
+                reg = bcm_perf_readl(perf_regs[i]);
+                if (BCMCPU_IS_6348()) {
+                        reg &= ~EXTIRQ_CFG_MASK_ALL_6348;
+                        reg |= EXTIRQ_CFG_CLEAR_ALL_6348;
+                } else {
+                        reg &= ~EXTIRQ_CFG_MASK_ALL;
+                        reg |= EXTIRQ_CFG_CLEAR_ALL;
+                }
+                bcm_perf_writel(reg, perf_regs[i]);
+        }
 
         if (BCMCPU_IS_6348() && (bcm63xx_get_cpu_rev() == 0xa1))
                 bcm6348_a1_reboot();
@@ -124,4 +144,4 @@ int __init bcm63xx_register_devices(void)
         return board_register_devices();
 }
 
-arch_initcall(bcm63xx_register_devices);
+device_initcall(bcm63xx_register_devices);
diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig
index cad555ebeca..f9e275a50d9 100644
--- a/arch/mips/cavium-octeon/Kconfig
+++ b/arch/mips/cavium-octeon/Kconfig
@@ -86,10 +86,6 @@ config ARCH_SPARSEMEM_ENABLE
         def_bool y
         select SPARSEMEM_STATIC
 
-config CAVIUM_OCTEON_HELPER
-        def_bool y
-        depends on OCTEON_ETHERNET || PCI
-
 config IOMMU_HELPER
         bool
 
diff --git a/arch/mips/cavium-octeon/dma-octeon.c b/arch/mips/cavium-octeon/dma-octeon.c
index ea4febaa4bb..b6bb92c16a4 100644
--- a/arch/mips/cavium-octeon/dma-octeon.c
+++ b/arch/mips/cavium-octeon/dma-octeon.c
@@ -61,6 +61,16 @@ static phys_addr_t octeon_gen1_dma_to_phys(struct device *dev, dma_addr_t daddr)
         return daddr;
 }
 
+static dma_addr_t octeon_gen2_phys_to_dma(struct device *dev, phys_addr_t paddr)
+{
+        return octeon_hole_phys_to_dma(paddr);
+}
+
+static phys_addr_t octeon_gen2_dma_to_phys(struct device *dev, dma_addr_t daddr)
+{
+        return octeon_hole_dma_to_phys(daddr);
+}
+
 static dma_addr_t octeon_big_phys_to_dma(struct device *dev, phys_addr_t paddr)
 {
         if (paddr >= 0x410000000ull && paddr < 0x420000000ull)
@@ -262,11 +272,11 @@ void __init plat_swiotlb_setup(void)
 
         for (i = 0 ; i < boot_mem_map.nr_map; i++) {
                 struct boot_mem_map_entry *e = &boot_mem_map.map[i];
-                if (e->type != BOOT_MEM_RAM)
+                if (e->type != BOOT_MEM_RAM && e->type != BOOT_MEM_INIT_RAM)
                         continue;
 
                 /* These addresses map low for PCI. */
-                if (e->addr > 0x410000000ull)
+                if (e->addr > 0x410000000ull && !OCTEON_IS_MODEL(OCTEON_CN6XXX))
                         continue;
 
                 addr_size += e->size;
@@ -296,6 +306,11 @@ void __init plat_swiotlb_setup(void)
                 swiotlbsize = 64 * (1<<20);
         }
 #endif
+#ifdef CONFIG_USB_OCTEON_OHCI
+        /* OCTEON II ohci is only 32-bit. */
+        if (OCTEON_IS_MODEL(OCTEON_CN6XXX) && max_addr >= 0x100000000ul)
+                swiotlbsize = 64 * (1<<20);
+#endif
         swiotlb_nslabs = swiotlbsize >> IO_TLB_SHIFT;
         swiotlb_nslabs = ALIGN(swiotlb_nslabs, IO_TLB_SEGSIZE);
         swiotlbsize = swiotlb_nslabs << IO_TLB_SHIFT;
@@ -330,6 +345,10 @@ struct dma_map_ops *octeon_pci_dma_map_ops;
 void __init octeon_pci_dma_init(void)
 {
         switch (octeon_dma_bar_type) {
+        case OCTEON_DMA_BAR_TYPE_PCIE2:
+                _octeon_pci_dma_map_ops.phys_to_dma = octeon_gen2_phys_to_dma;
+                _octeon_pci_dma_map_ops.dma_to_phys = octeon_gen2_dma_to_phys;
+                break;
         case OCTEON_DMA_BAR_TYPE_PCIE:
                 _octeon_pci_dma_map_ops.phys_to_dma = octeon_gen1_phys_to_dma;
                 _octeon_pci_dma_map_ops.dma_to_phys = octeon_gen1_dma_to_phys;
diff --git a/arch/mips/cavium-octeon/executive/Makefile b/arch/mips/cavium-octeon/executive/Makefile
index 7f41c5be219..b6d6e841a98 100644
--- a/arch/mips/cavium-octeon/executive/Makefile
+++ b/arch/mips/cavium-octeon/executive/Makefile
@@ -10,5 +10,10 @@
 #
 
 obj-y += cvmx-bootmem.o cvmx-l2c.o cvmx-sysinfo.o octeon-model.o
+obj-y += cvmx-pko.o cvmx-spi.o cvmx-cmd-queue.o \
+        cvmx-helper-board.o cvmx-helper.o cvmx-helper-xaui.o \
+        cvmx-helper-rgmii.o cvmx-helper-sgmii.o cvmx-helper-npi.o \
+        cvmx-helper-loop.o cvmx-helper-spi.o cvmx-helper-util.o \
+        cvmx-interrupt-decodes.o cvmx-interrupt-rsl.o
 
-obj-$(CONFIG_CAVIUM_OCTEON_HELPER) += cvmx-helper-errata.o cvmx-helper-jtag.o
+obj-y += cvmx-helper-errata.o cvmx-helper-jtag.o
diff --git a/drivers/staging/octeon/cvmx-cmd-queue.c b/arch/mips/cavium-octeon/executive/cvmx-cmd-queue.c
index e9809d37516..132bccc66a9 100644
--- a/drivers/staging/octeon/cvmx-cmd-queue.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-cmd-queue.c
@@ -34,13 +34,13 @@
 
 #include <asm/octeon/octeon.h>
 
-#include "cvmx-config.h"
-#include "cvmx-fpa.h"
-#include "cvmx-cmd-queue.h"
+#include <asm/octeon/cvmx-config.h>
+#include <asm/octeon/cvmx-fpa.h>
+#include <asm/octeon/cvmx-cmd-queue.h>
 
 #include <asm/octeon/cvmx-npei-defs.h>
 #include <asm/octeon/cvmx-pexp-defs.h>
-#include "cvmx-pko-defs.h"
+#include <asm/octeon/cvmx-pko-defs.h>
 
 /**
  * This application uses this pointer to access the global queue
diff --git a/drivers/staging/octeon/cvmx-fpa.c b/arch/mips/cavium-octeon/executive/cvmx-fpa.c
index ad44b8bd805..ad44b8bd805 100644
--- a/drivers/staging/octeon/cvmx-fpa.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-fpa.c
diff --git a/drivers/staging/octeon/cvmx-helper-board.c b/arch/mips/cavium-octeon/executive/cvmx-helper-board.c
index 57d35dc63dd..fd2015331a2 100644
--- a/drivers/staging/octeon/cvmx-helper-board.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-board.c
@@ -34,16 +34,16 @@
 #include <asm/octeon/octeon.h>
 #include <asm/octeon/cvmx-bootinfo.h>
 
-#include "cvmx-config.h"
+#include <asm/octeon/cvmx-config.h>
 
-#include "cvmx-mdio.h"
+#include <asm/octeon/cvmx-mdio.h>
 
-#include "cvmx-helper.h"
-#include "cvmx-helper-util.h"
-#include "cvmx-helper-board.h"
+#include <asm/octeon/cvmx-helper.h>
+#include <asm/octeon/cvmx-helper-util.h>
+#include <asm/octeon/cvmx-helper-board.h>
 
-#include "cvmx-gmxx-defs.h"
-#include "cvmx-asxx-defs.h"
+#include <asm/octeon/cvmx-gmxx-defs.h>
+#include <asm/octeon/cvmx-asxx-defs.h>
 
 /**
  * cvmx_override_board_link_get(int ipd_port) is a function
@@ -117,6 +117,10 @@ int cvmx_helper_board_get_mii_address(int ipd_port)
         case CVMX_BOARD_TYPE_EBH5200:
         case CVMX_BOARD_TYPE_EBH5201:
         case CVMX_BOARD_TYPE_EBT5200:
+                /* Board has 2 management ports */
+                if ((ipd_port >= CVMX_HELPER_BOARD_MGMT_IPD_PORT) &&
+                    (ipd_port < (CVMX_HELPER_BOARD_MGMT_IPD_PORT + 2)))
+                        return ipd_port - CVMX_HELPER_BOARD_MGMT_IPD_PORT;
                 /*
                  * Board has 4 SGMII ports. The PHYs start right after the MII
                  * ports MII0 = 0, MII1 = 1, SGMII = 2-5.
@@ -128,6 +132,9 @@ int cvmx_helper_board_get_mii_address(int ipd_port)
         case CVMX_BOARD_TYPE_EBH5600:
         case CVMX_BOARD_TYPE_EBH5601:
         case CVMX_BOARD_TYPE_EBH5610:
+                /* Board has 1 management port */
+                if (ipd_port == CVMX_HELPER_BOARD_MGMT_IPD_PORT)
+                        return 0;
                 /*
                  * Board has 8 SGMII ports. 4 connect out, two connect
                  * to a switch, and 2 loop to each other
@@ -147,6 +154,19 @@ int cvmx_helper_board_get_mii_address(int ipd_port)
                         return ipd_port - 16 + 1;
                 else
                         return -1;
+        case CVMX_BOARD_TYPE_NIC_XLE_10G:
+        case CVMX_BOARD_TYPE_NIC10E:
+                return -1;
+        case CVMX_BOARD_TYPE_NIC4E:
+                if (ipd_port >= 0 && ipd_port <= 3)
+                        return (ipd_port + 0x1f) & 0x1f;
+                else
+                        return -1;
+        case CVMX_BOARD_TYPE_NIC2E:
+                if (ipd_port >= 0 && ipd_port <= 1)
+                        return ipd_port + 1;
+                else
+                        return -1;
         case CVMX_BOARD_TYPE_BBGW_REF:
                 /*
                  * No PHYs are connected to Octeon, everything is
@@ -493,7 +513,6 @@ int cvmx_helper_board_link_set_phy(int phy_addr,
                 cvmx_mdio_phy_reg_control_t reg_control;
                 cvmx_mdio_phy_reg_status_t reg_status;
                 cvmx_mdio_phy_reg_autoneg_adver_t reg_autoneg_adver;
-                cvmx_mdio_phy_reg_extended_status_t reg_extended_status;
                 cvmx_mdio_phy_reg_control_1000_t reg_control_1000;
 
                 reg_status.u16 =
@@ -508,9 +527,6 @@ int cvmx_helper_board_link_set_phy(int phy_addr,
                 reg_autoneg_adver.s.advert_100base_tx_full = 0;
                 reg_autoneg_adver.s.advert_100base_tx_half = 0;
                 if (reg_status.s.capable_extended_status) {
-                        reg_extended_status.u16 =
-                            cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
-                                           CVMX_MDIO_PHY_REG_EXTENDED_STATUS);
                         reg_control_1000.u16 =
                             cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
                                            CVMX_MDIO_PHY_REG_CONTROL_1000);
diff --git a/drivers/staging/octeon/cvmx-helper-fpa.c b/arch/mips/cavium-octeon/executive/cvmx-helper-fpa.c
index c239e5f4ab9..c239e5f4ab9 100644
--- a/drivers/staging/octeon/cvmx-helper-fpa.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-fpa.c
diff --git a/drivers/staging/octeon/cvmx-helper-loop.c b/arch/mips/cavium-octeon/executive/cvmx-helper-loop.c
index 55a571a6952..bfbd46115e7 100644
--- a/drivers/staging/octeon/cvmx-helper-loop.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-loop.c
@@ -31,10 +31,10 @@
  */
 #include <asm/octeon/octeon.h>
 
-#include "cvmx-config.h"
+#include <asm/octeon/cvmx-config.h>
 
-#include "cvmx-helper.h"
-#include "cvmx-pip-defs.h"
+#include <asm/octeon/cvmx-helper.h>
+#include <asm/octeon/cvmx-pip-defs.h>
 
 /**
  * Probe a LOOP interface and determine the number of ports
diff --git a/drivers/staging/octeon/cvmx-helper-npi.c b/arch/mips/cavium-octeon/executive/cvmx-helper-npi.c
index 7388a1e72b3..cc94cfa545b 100644
--- a/drivers/staging/octeon/cvmx-helper-npi.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-npi.c
@@ -31,11 +31,11 @@
  */
 #include <asm/octeon/octeon.h>
 
-#include "cvmx-config.h"
+#include <asm/octeon/cvmx-config.h>
 
-#include "cvmx-helper.h"
+#include <asm/octeon/cvmx-helper.h>
 
-#include "cvmx-pip-defs.h"
+#include <asm/octeon/cvmx-pip-defs.h>
 
 /**
  * Probe a NPI interface and determine the number of ports
diff --git a/drivers/staging/octeon/cvmx-helper-rgmii.c b/arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c
index aa2d5d7fee2..82b21843421 100644
--- a/drivers/staging/octeon/cvmx-helper-rgmii.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c
@@ -31,18 +31,18 @@
  */
 #include <asm/octeon/octeon.h>
 
-#include "cvmx-config.h"
+#include <asm/octeon/cvmx-config.h>
 
 
-#include "cvmx-mdio.h"
-#include "cvmx-pko.h"
-#include "cvmx-helper.h"
-#include "cvmx-helper-board.h"
+#include <asm/octeon/cvmx-mdio.h>
+#include <asm/octeon/cvmx-pko.h>
+#include <asm/octeon/cvmx-helper.h>
+#include <asm/octeon/cvmx-helper-board.h>
 
 #include <asm/octeon/cvmx-npi-defs.h>
-#include "cvmx-gmxx-defs.h"
-#include "cvmx-asxx-defs.h"
-#include "cvmx-dbg-defs.h"
+#include <asm/octeon/cvmx-gmxx-defs.h>
+#include <asm/octeon/cvmx-asxx-defs.h>
+#include <asm/octeon/cvmx-dbg-defs.h>
 
 void __cvmx_interrupt_gmxx_enable(int interface);
 void __cvmx_interrupt_asxx_enable(int block);
@@ -326,6 +326,7 @@ int __cvmx_helper_rgmii_link_set(int ipd_port,
                        cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(interface)) &
                                      ~(1 << index));
 
+        memset(pko_mem_queue_qos_save, 0, sizeof(pko_mem_queue_qos_save));
         /* Disable all queues so that TX should become idle */
         for (i = 0; i < cvmx_pko_get_num_queues(ipd_port); i++) {
                 int queue = cvmx_pko_get_base_queue(ipd_port) + i;
diff --git a/drivers/staging/octeon/cvmx-helper-sgmii.c b/arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c
index 6214e3b6d97..0c0bf5d30e7 100644
--- a/drivers/staging/octeon/cvmx-helper-sgmii.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c
@@ -32,14 +32,14 @@
 
 #include <asm/octeon/octeon.h>
 
-#include "cvmx-config.h"
+#include <asm/octeon/cvmx-config.h>
 
-#include "cvmx-mdio.h"
-#include "cvmx-helper.h"
-#include "cvmx-helper-board.h"
+#include <asm/octeon/cvmx-mdio.h>
+#include <asm/octeon/cvmx-helper.h>
+#include <asm/octeon/cvmx-helper-board.h>
 
-#include "cvmx-gmxx-defs.h"
-#include "cvmx-pcsx-defs.h"
+#include <asm/octeon/cvmx-gmxx-defs.h>
+#include <asm/octeon/cvmx-pcsx-defs.h>
 
 void __cvmx_interrupt_gmxx_enable(int interface);
 void __cvmx_interrupt_pcsx_intx_en_reg_enable(int index, int block);
@@ -326,6 +326,10 @@ static int __cvmx_helper_sgmii_hardware_init(int interface, int num_ports)
         return 0;
 }
 
+int __cvmx_helper_sgmii_enumerate(int interface)
+{
+        return 4;
+}
 /**
  * Probe a SGMII interface and determine the number of ports
  * connected to it. The SGMII interface should still be down after
@@ -347,7 +351,7 @@ int __cvmx_helper_sgmii_probe(int interface)
         mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
         mode.s.en = 1;
         cvmx_write_csr(CVMX_GMXX_INF_MODE(interface), mode.u64);
-        return 4;
+        return __cvmx_helper_sgmii_enumerate(interface);
 }
 
 /**
diff --git a/drivers/staging/octeon/cvmx-helper-spi.c b/arch/mips/cavium-octeon/executive/cvmx-helper-spi.c
index 8ba6c832471..2830e4bdf7f 100644
--- a/drivers/staging/octeon/cvmx-helper-spi.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-spi.c
@@ -35,12 +35,12 @@ void __cvmx_interrupt_stxx_int_msk_enable(int index);
  */
 #include <asm/octeon/octeon.h>
 
-#include "cvmx-config.h"
-#include "cvmx-spi.h"
-#include "cvmx-helper.h"
+#include <asm/octeon/cvmx-config.h>
+#include <asm/octeon/cvmx-spi.h>
+#include <asm/octeon/cvmx-helper.h>
 
-#include "cvmx-pip-defs.h"
-#include "cvmx-pko-defs.h"
+#include <asm/octeon/cvmx-pip-defs.h>
+#include <asm/octeon/cvmx-pko-defs.h>
 
 /*
  * CVMX_HELPER_SPI_TIMEOUT is used to determine how long the SPI
@@ -51,6 +51,16 @@ void __cvmx_interrupt_stxx_int_msk_enable(int index);
 #define CVMX_HELPER_SPI_TIMEOUT 10
 #endif
 
+int __cvmx_helper_spi_enumerate(int interface)
+{
+        if ((cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM) &&
+            cvmx_spi4000_is_present(interface)) {
+                return 10;
+        } else {
+                return 16;
+        }
+}
+
 /**
  * Probe a SPI interface and determine the number of ports
  * connected to it. The SPI interface should still be down after
diff --git a/drivers/staging/octeon/cvmx-helper-util.c b/arch/mips/cavium-octeon/executive/cvmx-helper-util.c
index 131182bf5ab..116dea17acf 100644
--- a/drivers/staging/octeon/cvmx-helper-util.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-util.c
@@ -32,16 +32,16 @@
 
 #include <asm/octeon/octeon.h>
 
-#include "cvmx-config.h"
+#include <asm/octeon/cvmx-config.h>
 
-#include "cvmx-fpa.h"
-#include "cvmx-pip.h"
-#include "cvmx-pko.h"
-#include "cvmx-ipd.h"
-#include "cvmx-spi.h"
+#include <asm/octeon/cvmx-fpa.h>
+#include <asm/octeon/cvmx-pip.h>
+#include <asm/octeon/cvmx-pko.h>
+#include <asm/octeon/cvmx-ipd.h>
+#include <asm/octeon/cvmx-spi.h>
 
-#include "cvmx-helper.h"
-#include "cvmx-helper-util.h"
+#include <asm/octeon/cvmx-helper.h>
+#include <asm/octeon/cvmx-helper-util.h>
 
 #include <asm/octeon/cvmx-ipd-defs.h>
 
diff --git a/drivers/staging/octeon/cvmx-helper-xaui.c b/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c
index a11e6769e23..1723248e987 100644
--- a/drivers/staging/octeon/cvmx-helper-xaui.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c
@@ -33,17 +33,30 @@
 
 #include <asm/octeon/octeon.h>
 
-#include "cvmx-config.h"
+#include <asm/octeon/cvmx-config.h>
 
-#include "cvmx-helper.h"
+#include <asm/octeon/cvmx-helper.h>
 
-#include "cvmx-pko-defs.h"
-#include "cvmx-gmxx-defs.h"
-#include "cvmx-pcsxx-defs.h"
+#include <asm/octeon/cvmx-pko-defs.h>
+#include <asm/octeon/cvmx-gmxx-defs.h>
+#include <asm/octeon/cvmx-pcsxx-defs.h>
 
 void __cvmx_interrupt_gmxx_enable(int interface);
 void __cvmx_interrupt_pcsx_intx_en_reg_enable(int index, int block);
 void __cvmx_interrupt_pcsxx_int_en_reg_enable(int index);
+
+int __cvmx_helper_xaui_enumerate(int interface)
+{
+        union cvmx_gmxx_hg2_control gmx_hg2_control;
+
+        /* If HiGig2 is enabled return 16 ports, otherwise return 1 port */
+        gmx_hg2_control.u64 = cvmx_read_csr(CVMX_GMXX_HG2_CONTROL(interface));
+        if (gmx_hg2_control.s.hg2tx_en)
+                return 16;
+        else
+                return 1;
+}
+
 /**
  * Probe a XAUI interface and determine the number of ports
  * connected to it. The XAUI interface should still be down
@@ -56,7 +69,6 @@ void __cvmx_interrupt_pcsxx_int_en_reg_enable(int index);
 int __cvmx_helper_xaui_probe(int interface)
 {
         int i;
-        union cvmx_gmxx_hg2_control gmx_hg2_control;
         union cvmx_gmxx_inf_mode mode;
 
         /*
@@ -90,13 +102,7 @@ int __cvmx_helper_xaui_probe(int interface)
                 pko_mem_port_ptrs.s.pid = interface * 16 + i;
                 cvmx_write_csr(CVMX_PKO_MEM_PORT_PTRS, pko_mem_port_ptrs.u64);
         }
-
-        /* If HiGig2 is enabled return 16 ports, otherwise return 1 port */
-        gmx_hg2_control.u64 = cvmx_read_csr(CVMX_GMXX_HG2_CONTROL(interface));
-        if (gmx_hg2_control.s.hg2tx_en)
-                return 16;
-        else
-                return 1;
+        return __cvmx_helper_xaui_enumerate(interface);
 }
 
 /**
diff --git a/drivers/staging/octeon/cvmx-helper.c b/arch/mips/cavium-octeon/executive/cvmx-helper.c
index e9c5c836cef..fa496385635 100644
--- a/drivers/staging/octeon/cvmx-helper.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper.c
@@ -32,19 +32,19 @@
  */
 #include <asm/octeon/octeon.h>
 
-#include "cvmx-config.h"
+#include <asm/octeon/cvmx-config.h>
 
-#include "cvmx-fpa.h"
-#include "cvmx-pip.h"
-#include "cvmx-pko.h"
-#include "cvmx-ipd.h"
-#include "cvmx-spi.h"
-#include "cvmx-helper.h"
-#include "cvmx-helper-board.h"
+#include <asm/octeon/cvmx-fpa.h>
+#include <asm/octeon/cvmx-pip.h>
+#include <asm/octeon/cvmx-pko.h>
+#include <asm/octeon/cvmx-ipd.h>
+#include <asm/octeon/cvmx-spi.h>
+#include <asm/octeon/cvmx-helper.h>
+#include <asm/octeon/cvmx-helper-board.h>
 
-#include "cvmx-pip-defs.h"
-#include "cvmx-smix-defs.h"
-#include "cvmx-asxx-defs.h"
+#include <asm/octeon/cvmx-pip-defs.h>
+#include <asm/octeon/cvmx-smix-defs.h>
+#include <asm/octeon/cvmx-asxx-defs.h>
 
 /**
  * cvmx_override_pko_queue_priority(int ipd_port, uint64_t
@@ -234,21 +234,16 @@ static int __cvmx_helper_port_setup_ipd(int ipd_port)
 }
 
 /**
- * This function probes an interface to determine the actual
- * number of hardware ports connected to it. It doesn't setup the
- * ports or enable them. The main goal here is to set the global
- * interface_port_count[interface] correctly. Hardware setup of the
- * ports will be performed later.
+ * This function sets the interface_port_count[interface] correctly,
+ * without modifying any hardware configuration.  Hardware setup of
+ * the ports will be performed later.
  *
  * @interface: Interface to probe
  *
  * Returns Zero on success, negative on failure
  */
-int cvmx_helper_interface_probe(int interface)
+int cvmx_helper_interface_enumerate(int interface)
 {
-        /* At this stage in the game we don't want packets to be moving yet.
-           The following probe calls should perform hardware setup
-           needed to determine port counts. Receive must still be disabled */
         switch (cvmx_helper_interface_get_mode(interface)) {
                 /* These types don't support ports to IPD/PKO */
         case CVMX_HELPER_INTERFACE_MODE_DISABLED:
@@ -258,7 +253,7 @@ int cvmx_helper_interface_probe(int interface)
                 /* XAUI is a single high speed port */
         case CVMX_HELPER_INTERFACE_MODE_XAUI:
                 interface_port_count[interface] =
-                    __cvmx_helper_xaui_probe(interface);
+                    __cvmx_helper_xaui_enumerate(interface);
                 break;
                 /*
                  * RGMII/GMII/MII are all treated about the same. Most
@@ -267,7 +262,7 @@ int cvmx_helper_interface_probe(int interface)
         case CVMX_HELPER_INTERFACE_MODE_RGMII:
         case CVMX_HELPER_INTERFACE_MODE_GMII:
                 interface_port_count[interface] =
-                    __cvmx_helper_rgmii_probe(interface);
+                    __cvmx_helper_rgmii_enumerate(interface);
                 break;
                 /*
                  * SPI4 can have 1-16 ports depending on the device at
@@ -275,7 +270,7 @@ int cvmx_helper_interface_probe(int interface)
                  */
         case CVMX_HELPER_INTERFACE_MODE_SPI:
                 interface_port_count[interface] =
-                    __cvmx_helper_spi_probe(interface);
+                    __cvmx_helper_spi_enumerate(interface);
                 break;
                 /*
                  * SGMII can have 1-4 ports depending on how many are
@@ -284,12 +279,12 @@ int cvmx_helper_interface_probe(int interface)
         case CVMX_HELPER_INTERFACE_MODE_SGMII:
         case CVMX_HELPER_INTERFACE_MODE_PICMG:
                 interface_port_count[interface] =
-                    __cvmx_helper_sgmii_probe(interface);
+                    __cvmx_helper_sgmii_enumerate(interface);
                 break;
                 /* PCI target Network Packet Interface */
         case CVMX_HELPER_INTERFACE_MODE_NPI:
                 interface_port_count[interface] =
-                    __cvmx_helper_npi_probe(interface);
+                    __cvmx_helper_npi_enumerate(interface);
                 break;
                 /*
                  * Special loopback only ports. These are not the same
@@ -297,7 +292,7 @@ int cvmx_helper_interface_probe(int interface)
                  */
         case CVMX_HELPER_INTERFACE_MODE_LOOP:
                 interface_port_count[interface] =
-                    __cvmx_helper_loop_probe(interface);
+                    __cvmx_helper_loop_enumerate(interface);
                 break;
         }
 
@@ -313,6 +308,74 @@ int cvmx_helper_interface_probe(int interface)
 }
 
 /**
+ * This function probes an interface to determine the actual
+ * number of hardware ports connected to it. It doesn't setup the
+ * ports or enable them. The main goal here is to set the global
+ * interface_port_count[interface] correctly. Hardware setup of the
+ * ports will be performed later.
+ *
+ * @interface: Interface to probe
+ *
+ * Returns Zero on success, negative on failure
+ */
+int cvmx_helper_interface_probe(int interface)
+{
+        cvmx_helper_interface_enumerate(interface);
+        /* At this stage in the game we don't want packets to be moving yet.
+           The following probe calls should perform hardware setup
+           needed to determine port counts. Receive must still be disabled */
+        switch (cvmx_helper_interface_get_mode(interface)) {
+                /* These types don't support ports to IPD/PKO */
+        case CVMX_HELPER_INTERFACE_MODE_DISABLED:
+        case CVMX_HELPER_INTERFACE_MODE_PCIE:
+                break;
+                /* XAUI is a single high speed port */
+        case CVMX_HELPER_INTERFACE_MODE_XAUI:
+                __cvmx_helper_xaui_probe(interface);
+                break;
+                /*
+                 * RGMII/GMII/MII are all treated about the same. Most
+                 * functions refer to these ports as RGMII.
+                 */
+        case CVMX_HELPER_INTERFACE_MODE_RGMII:
+        case CVMX_HELPER_INTERFACE_MODE_GMII:
+                __cvmx_helper_rgmii_probe(interface);
+                break;
+                /*
+                 * SPI4 can have 1-16 ports depending on the device at
+                 * the other end.
+                 */
+        case CVMX_HELPER_INTERFACE_MODE_SPI:
+                __cvmx_helper_spi_probe(interface);
+                break;
+                /*
+                 * SGMII can have 1-4 ports depending on how many are
+                 * hooked up.
+                 */
+        case CVMX_HELPER_INTERFACE_MODE_SGMII:
+        case CVMX_HELPER_INTERFACE_MODE_PICMG:
+                __cvmx_helper_sgmii_probe(interface);
+                break;
+                /* PCI target Network Packet Interface */
+        case CVMX_HELPER_INTERFACE_MODE_NPI:
+                __cvmx_helper_npi_probe(interface);
+                break;
+                /*
+                 * Special loopback only ports. These are not the same
+                 * as other ports in loopback mode.
+                 */
+        case CVMX_HELPER_INTERFACE_MODE_LOOP:
+                __cvmx_helper_loop_probe(interface);
+                break;
+        }
+
+        /* Make sure all global variables propagate to other cores */
+        CVMX_SYNCWS;
+
+        return 0;
+}
+
+/**
  * Setup the IPD/PIP for the ports on an interface. Packet
  * classification and tagging are set for every port on the
  * interface. The number of ports on the interface must already
@@ -548,7 +611,6 @@ int __cvmx_helper_errata_fix_ipd_ptr_alignment(void)
         union cvmx_gmxx_prtx_cfg gmx_cfg;
         int retry_cnt;
         int retry_loop_cnt;
-        int mtu;
         int i;
         cvmx_helper_link_info_t link_info;
 
@@ -662,10 +724,6 @@ int __cvmx_helper_errata_fix_ipd_ptr_alignment(void)
                 cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)),
                                1 << INDEX(FIX_IPD_OUTPORT));
 
-                mtu =
-                    cvmx_read_csr(CVMX_GMXX_RXX_JABBER
-                                  (INDEX(FIX_IPD_OUTPORT),
-                                   INTERFACE(FIX_IPD_OUTPORT)));
                 cvmx_write_csr(CVMX_GMXX_RXX_JABBER
                                (INDEX(FIX_IPD_OUTPORT),
                                 INTERFACE(FIX_IPD_OUTPORT)), 65392 - 14 - 4);
diff --git a/drivers/staging/octeon/cvmx-interrupt-decodes.c b/arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c
index a3337e382ee..e59d1b79f24 100644
--- a/drivers/staging/octeon/cvmx-interrupt-decodes.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c
@@ -34,11 +34,11 @@
 
 #include <asm/octeon/octeon.h>
 
-#include "cvmx-gmxx-defs.h"
-#include "cvmx-pcsx-defs.h"
-#include "cvmx-pcsxx-defs.h"
-#include "cvmx-spxx-defs.h"
-#include "cvmx-stxx-defs.h"
+#include <asm/octeon/cvmx-gmxx-defs.h>
+#include <asm/octeon/cvmx-pcsx-defs.h>
+#include <asm/octeon/cvmx-pcsxx-defs.h>
+#include <asm/octeon/cvmx-spxx-defs.h>
+#include <asm/octeon/cvmx-stxx-defs.h>
 
 #ifndef PRINT_ERROR
 #define PRINT_ERROR(format, ...)
diff --git a/drivers/staging/octeon/cvmx-interrupt-rsl.c b/arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c
index df50048cfbc..bea7538ea4e 100644
--- a/drivers/staging/octeon/cvmx-interrupt-rsl.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c
@@ -32,8 +32,8 @@
 
 #include <asm/octeon/octeon.h>
 
-#include "cvmx-asxx-defs.h"
-#include "cvmx-gmxx-defs.h"
+#include <asm/octeon/cvmx-asxx-defs.h>
+#include <asm/octeon/cvmx-gmxx-defs.h>
 
 #ifndef PRINT_ERROR
 #define PRINT_ERROR(format, ...)
diff --git a/drivers/staging/octeon/cvmx-pko.c b/arch/mips/cavium-octeon/executive/cvmx-pko.c
index 50a2c9bd5a5..f557084b109 100644
--- a/drivers/staging/octeon/cvmx-pko.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-pko.c
@@ -31,9 +31,9 @@
 
 #include <asm/octeon/octeon.h>
 
-#include "cvmx-config.h"
-#include "cvmx-pko.h"
-#include "cvmx-helper.h"
+#include <asm/octeon/cvmx-config.h>
+#include <asm/octeon/cvmx-pko.h>
+#include <asm/octeon/cvmx-helper.h>
 
 /**
  * Internal state of packet output
@@ -54,7 +54,7 @@ void cvmx_pko_initialize_global(void)
         /*
          * Set the size of the PKO command buffers to an odd number of
          * 64bit words. This allows the normal two word send to stay
-         * aligned and never span a command word buffer.
+         * aligned and never span a comamnd word buffer.
          */
         config.u64 = 0;
         config.s.pool = CVMX_FPA_OUTPUT_BUFFER_POOL;
diff --git a/drivers/staging/octeon/cvmx-spi.c b/arch/mips/cavium-octeon/executive/cvmx-spi.c
index 82794d920ce..74afb1710cd 100644
--- a/drivers/staging/octeon/cvmx-spi.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-spi.c
@@ -31,14 +31,14 @@
  */
 #include <asm/octeon/octeon.h>
 
-#include "cvmx-config.h"
+#include <asm/octeon/cvmx-config.h>
 
-#include "cvmx-pko.h"
-#include "cvmx-spi.h"
+#include <asm/octeon/cvmx-pko.h>
+#include <asm/octeon/cvmx-spi.h>
 
-#include "cvmx-spxx-defs.h"
-#include "cvmx-stxx-defs.h"
-#include "cvmx-srxx-defs.h"
+#include <asm/octeon/cvmx-spxx-defs.h>
+#include <asm/octeon/cvmx-stxx-defs.h>
+#include <asm/octeon/cvmx-srxx-defs.h>
 
 #define INVOKE_CB(function_p, args...)          \
         do {                                    \
diff --git a/arch/mips/cavium-octeon/executive/octeon-model.c b/arch/mips/cavium-octeon/executive/octeon-model.c
index c8d35684504..f4c1b36fdf6 100644
--- a/arch/mips/cavium-octeon/executive/octeon-model.c
+++ b/arch/mips/cavium-octeon/executive/octeon-model.c
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -25,10 +25,6 @@
  * Contact Cavium Networks for more information
  ***********************license end**************************************/
 
-/*
- * File defining functions for working with different Octeon
- * models.
- */
 #include <asm/octeon/octeon.h>
 
 /**
@@ -69,11 +65,12 @@ const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer)
         char fuse_model[10];
         uint32_t fuse_data = 0;
 
-        fus3.u64 = cvmx_read_csr(CVMX_L2D_FUS3);
+        fus3.u64 = 0;
+        if (!OCTEON_IS_MODEL(OCTEON_CN6XXX))
+                fus3.u64 = cvmx_read_csr(CVMX_L2D_FUS3);
         fus_dat2.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT2);
         fus_dat3.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT3);
-
-        num_cores = cvmx_octeon_num_cores();
+        num_cores = cvmx_pop(cvmx_read_csr(CVMX_CIU_FUSE));
 
         /* Make sure the non existent devices look disabled */
         switch ((chip_id >> 8) & 0xff) {
@@ -108,7 +105,7 @@ const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer)
          * Assume pass number is encoded using <5:3><2:0>. Exceptions
          * will be fixed later.
          */
-        sprintf(pass, "%u.%u", ((chip_id >> 3) & 7) + 1, chip_id & 7);
+        sprintf(pass, "%d.%d", (int)((chip_id >> 3) & 7) + 1, (int)chip_id & 7);
 
         /*
          * Use the number of cores to determine the last 2 digits of
@@ -116,6 +113,12 @@ const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer)
          * later.
          */
         switch (num_cores) {
+        case 32:
+                core_model = "80";
+                break;
+        case 24:
+                core_model = "70";
+                break;
         case 16:
                 core_model = "60";
                 break;
@@ -246,8 +249,8 @@ const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer)
                 break;
         case 3:         /* CN58XX */
                 family = "58";
-                /* Special case. 4 core, no crypto */
-                if ((num_cores == 4) && fus_dat2.cn38xx.nocrypto)
+                /* Special case. 4 core, half cache (CP with half cache) */
+                if ((num_cores == 4) && fus3.cn58xx.crip_1024k && !strncmp(suffix, "CP", 2))
                         core_model = "29";
 
                 /* Pass 1 uses different encodings for pass numbers */
@@ -285,6 +288,9 @@ const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer)
                                 suffix = "NSP";
                                 if (fus_dat3.s.nozip)
                                         suffix = "SCP";
+
+                                if (fus_dat3.s.bar2_en)
+                                        suffix = "NSPB2";
                         }
                         if (fus3.cn56xx.crip_1024k)
                                 family = "54";
@@ -301,6 +307,60 @@ const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer)
                 else
                         family = "52";
                 break;
+        case 0x93:              /* CN61XX */
+                family = "61";
+                if (fus_dat2.cn61xx.nocrypto && fus_dat2.cn61xx.dorm_crypto)
+                        suffix = "AP";
+                if (fus_dat2.cn61xx.nocrypto)
+                        suffix = "CP";
+                else if (fus_dat2.cn61xx.dorm_crypto)
+                        suffix = "DAP";
+                else if (fus_dat3.cn61xx.nozip)
+                        suffix = "SCP";
+                break;
+        case 0x90:              /* CN63XX */
+                family = "63";
+                if (fus_dat3.s.l2c_crip == 2)
+                        family = "62";
+                if (num_cores == 6)     /* Other core counts match generic */
+                        core_model = "35";
+                if (fus_dat2.cn63xx.nocrypto)
+                        suffix = "CP";
+                else if (fus_dat2.cn63xx.dorm_crypto)
+                        suffix = "DAP";
+                else if (fus_dat3.cn63xx.nozip)
+                        suffix = "SCP";
+                else
+                        suffix = "AAP";
+                break;
+        case 0x92:              /* CN66XX */
+                family = "66";
+                if (num_cores == 6)     /* Other core counts match generic */
+                        core_model = "35";
+                if (fus_dat2.cn66xx.nocrypto && fus_dat2.cn66xx.dorm_crypto)
+                        suffix = "AP";
+                if (fus_dat2.cn66xx.nocrypto)
+                        suffix = "CP";
+                else if (fus_dat2.cn66xx.dorm_crypto)
+                        suffix = "DAP";
+                else if (fus_dat3.cn66xx.nozip)
+                        suffix = "SCP";
+                else
+                        suffix = "AAP";
+                break;
+        case 0x91:              /* CN68XX */
+                family = "68";
+                if (fus_dat2.cn68xx.nocrypto && fus_dat3.cn68xx.nozip)
+                        suffix = "CP";
+                else if (fus_dat2.cn68xx.dorm_crypto)
+                        suffix = "DAP";
+                else if (fus_dat3.cn68xx.nozip)
+                        suffix = "SCP";
+                else if (fus_dat2.cn68xx.nocrypto)
+                        suffix = "SP";
+                else
+                        suffix = "AAP";
+                break;
         default:
                 family = "XX";
                 core_model = "XX";
@@ -310,49 +370,40 @@ const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer)
         }
 
         clock_mhz = octeon_get_clock_rate() / 1000000;
-
         if (family[0] != '3') {
+                int fuse_base = 384 / 8;
+                if (family[0] == '6')
+                        fuse_base = 832 / 8;
+
                 /* Check for model in fuses, overrides normal decode */
                 /* This is _not_ valid for Octeon CN3XXX models */
-                fuse_data |= cvmx_fuse_read_byte(51);
+                fuse_data |= cvmx_fuse_read_byte(fuse_base + 3);
                 fuse_data = fuse_data << 8;
-                fuse_data |= cvmx_fuse_read_byte(50);
+                fuse_data |= cvmx_fuse_read_byte(fuse_base + 2);
                 fuse_data = fuse_data << 8;
-                fuse_data |= cvmx_fuse_read_byte(49);
+                fuse_data |= cvmx_fuse_read_byte(fuse_base + 1);
                 fuse_data = fuse_data << 8;
-                fuse_data |= cvmx_fuse_read_byte(48);
+                fuse_data |= cvmx_fuse_read_byte(fuse_base);
                 if (fuse_data & 0x7ffff) {
                         int model = fuse_data & 0x3fff;
                         int suffix = (fuse_data >> 14) & 0x1f;
                         if (suffix && model) {
-                                /*
-                                 * Have both number and suffix in
-                                 * fuses, so both
-                                 */
-                                sprintf(fuse_model, "%d%c",
-                                        model, 'A' + suffix - 1);
+                                /* Have both number and suffix in fuses, so both */
+                                sprintf(fuse_model, "%d%c", model, 'A' + suffix - 1);
                                 core_model = "";
                                 family = fuse_model;
                         } else if (suffix && !model) {
-                                /*
-                                 * Only have suffix, so add suffix to
-                                 * 'normal' model number.
-                                 */
-                                sprintf(fuse_model, "%s%c", core_model,
-                                        'A' + suffix - 1);
+                                /* Only have suffix, so add suffix to 'normal' model number */
+                                sprintf(fuse_model, "%s%c", core_model, 'A' + suffix - 1);
                                 core_model = fuse_model;
                         } else {
-                                /*
-                                 * Don't have suffix, so just use
-                                 * model from fuses.
-                                 */
+                                /* Don't have suffix, so just use model from fuses */
                                 sprintf(fuse_model, "%d", model);
                                 core_model = "";
                                 family = fuse_model;
                         }
                 }
         }
-        sprintf(buffer, "CN%s%sp%s-%d-%s",
-                family, core_model, pass, clock_mhz, suffix);
+        sprintf(buffer, "CN%s%sp%s-%d-%s", family, core_model, pass, clock_mhz, suffix);
         return buffer;
 }
diff --git a/arch/mips/configs/nlm_xlp_defconfig b/arch/mips/configs/nlm_xlp_defconfig
new file mode 100644
index 00000000000..4479fd669ac
--- /dev/null
+++ b/arch/mips/configs/nlm_xlp_defconfig
@@ -0,0 +1,570 @@
+CONFIG_NLM_XLP_BOARD=y
+CONFIG_64BIT=y
+CONFIG_KSM=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=65536
+CONFIG_SMP=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+# CONFIG_SECCOMP is not set
+CONFIG_USE_OF=y
+CONFIG_EXPERIMENTAL=y
+CONFIG_CROSS_COMPILE="mips-linux-gnu-"
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_AUDIT=y
+CONFIG_CGROUPS=y
+CONFIG_NAMESPACES=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE="usr/dev_file_list usr/rootfs.xlp"
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
+CONFIG_INITRAMFS_COMPRESSION_LZMA=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_EMBEDDED=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_PROFILING=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_BLK_DEV_INTEGRITY=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_BINFMT_MISC=y
+CONFIG_MIPS32_COMPAT=y
+CONFIG_MIPS32_O32=y
+CONFIG_MIPS32_N32=y
+CONFIG_PM_RUNTIME=y
+CONFIG_PM_DEBUG=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_XFRM_USER=m
+CONFIG_NET_KEY=m
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_NET_IPIP=m
+CONFIG_IP_MROUTE=y
+CONFIG_IP_PIMSM_V1=y
+CONFIG_IP_PIMSM_V2=y
+CONFIG_SYN_COOKIES=y
+CONFIG_INET_AH=m
+CONFIG_INET_ESP=m
+CONFIG_INET_IPCOMP=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=m
+CONFIG_INET_XFRM_MODE_TUNNEL=m
+CONFIG_INET_XFRM_MODE_BEET=m
+CONFIG_TCP_CONG_ADVANCED=y
+CONFIG_TCP_CONG_HSTCP=m
+CONFIG_TCP_CONG_HYBLA=m
+CONFIG_TCP_CONG_SCALABLE=m
+CONFIG_TCP_CONG_LP=m
+CONFIG_TCP_CONG_VENO=m
+CONFIG_TCP_CONG_YEAH=m
+CONFIG_TCP_CONG_ILLINOIS=m
+CONFIG_TCP_MD5SIG=y
+CONFIG_IPV6=y
+CONFIG_IPV6_PRIVACY=y
+CONFIG_INET6_AH=m
+CONFIG_INET6_ESP=m
+CONFIG_INET6_IPCOMP=m
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
+CONFIG_IPV6_SIT=m
+CONFIG_IPV6_TUNNEL=m
+CONFIG_IPV6_MULTIPLE_TABLES=y
+CONFIG_NETLABEL=y
+CONFIG_NETFILTER=y
+CONFIG_NF_CONNTRACK=m
+CONFIG_NF_CONNTRACK_SECMARK=y
+CONFIG_NF_CONNTRACK_EVENTS=y
+CONFIG_NF_CT_PROTO_UDPLITE=m
+CONFIG_NF_CONNTRACK_AMANDA=m
+CONFIG_NF_CONNTRACK_FTP=m
+CONFIG_NF_CONNTRACK_H323=m
+CONFIG_NF_CONNTRACK_IRC=m
+CONFIG_NF_CONNTRACK_NETBIOS_NS=m
+CONFIG_NF_CONNTRACK_PPTP=m
+CONFIG_NF_CONNTRACK_SANE=m
+CONFIG_NF_CONNTRACK_SIP=m
+CONFIG_NF_CONNTRACK_TFTP=m
+CONFIG_NF_CT_NETLINK=m
+CONFIG_NETFILTER_TPROXY=m
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
+CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m
+CONFIG_NETFILTER_XT_TARGET_DSCP=m
+CONFIG_NETFILTER_XT_TARGET_MARK=m
+CONFIG_NETFILTER_XT_TARGET_NFLOG=m
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
+CONFIG_NETFILTER_XT_TARGET_TPROXY=m
+CONFIG_NETFILTER_XT_TARGET_TRACE=m
+CONFIG_NETFILTER_XT_TARGET_SECMARK=m
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
+CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
+CONFIG_NETFILTER_XT_MATCH_COMMENT=m
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_NETFILTER_XT_MATCH_DSCP=m
+CONFIG_NETFILTER_XT_MATCH_ESP=m
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_HELPER=m
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
+CONFIG_NETFILTER_XT_MATCH_LENGTH=m
+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
+CONFIG_NETFILTER_XT_MATCH_MAC=m
+CONFIG_NETFILTER_XT_MATCH_MARK=m
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
+CONFIG_NETFILTER_XT_MATCH_OSF=m
+CONFIG_NETFILTER_XT_MATCH_OWNER=m
+CONFIG_NETFILTER_XT_MATCH_POLICY=m
+CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
+CONFIG_NETFILTER_XT_MATCH_QUOTA=m
+CONFIG_NETFILTER_XT_MATCH_RATEEST=m
+CONFIG_NETFILTER_XT_MATCH_REALM=m
+CONFIG_NETFILTER_XT_MATCH_RECENT=m
+CONFIG_NETFILTER_XT_MATCH_SOCKET=m
+CONFIG_NETFILTER_XT_MATCH_STATE=m
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
+CONFIG_NETFILTER_XT_MATCH_STRING=m
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
+CONFIG_NETFILTER_XT_MATCH_TIME=m
+CONFIG_NETFILTER_XT_MATCH_U32=m
+CONFIG_IP_VS=m
+CONFIG_IP_VS_IPV6=y
+CONFIG_IP_VS_PROTO_TCP=y
+CONFIG_IP_VS_PROTO_UDP=y
+CONFIG_IP_VS_PROTO_ESP=y
+CONFIG_IP_VS_PROTO_AH=y
+CONFIG_IP_VS_RR=m
+CONFIG_IP_VS_WRR=m
+CONFIG_IP_VS_LC=m
+CONFIG_IP_VS_WLC=m
+CONFIG_IP_VS_LBLC=m
+CONFIG_IP_VS_LBLCR=m
+CONFIG_IP_VS_DH=m
+CONFIG_IP_VS_SH=m
+CONFIG_IP_VS_SED=m
+CONFIG_IP_VS_NQ=m
+CONFIG_IP_VS_FTP=m
+CONFIG_NF_CONNTRACK_IPV4=m
+CONFIG_IP_NF_QUEUE=m
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_MATCH_AH=m
+CONFIG_IP_NF_MATCH_ECN=m
+CONFIG_IP_NF_MATCH_TTL=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_IP_NF_TARGET_LOG=m
+CONFIG_IP_NF_TARGET_ULOG=m
+CONFIG_NF_NAT=m
+CONFIG_IP_NF_TARGET_MASQUERADE=m
+CONFIG_IP_NF_TARGET_NETMAP=m
+CONFIG_IP_NF_TARGET_REDIRECT=m
+CONFIG_IP_NF_MANGLE=m
+CONFIG_IP_NF_TARGET_CLUSTERIP=m
+CONFIG_IP_NF_TARGET_ECN=m
+CONFIG_IP_NF_TARGET_TTL=m
+CONFIG_IP_NF_RAW=m
+CONFIG_IP_NF_SECURITY=m
+CONFIG_IP_NF_ARPTABLES=m
+CONFIG_IP_NF_ARPFILTER=m
+CONFIG_IP_NF_ARP_MANGLE=m
+CONFIG_NF_CONNTRACK_IPV6=m
+CONFIG_IP6_NF_QUEUE=m
+CONFIG_IP6_NF_IPTABLES=m
+CONFIG_IP6_NF_MATCH_AH=m
+CONFIG_IP6_NF_MATCH_EUI64=m
+CONFIG_IP6_NF_MATCH_FRAG=m
+CONFIG_IP6_NF_MATCH_OPTS=m
+CONFIG_IP6_NF_MATCH_HL=m
+CONFIG_IP6_NF_MATCH_IPV6HEADER=m
+CONFIG_IP6_NF_MATCH_MH=m
+CONFIG_IP6_NF_MATCH_RT=m
+CONFIG_IP6_NF_TARGET_HL=m
+CONFIG_IP6_NF_TARGET_LOG=m
+CONFIG_IP6_NF_FILTER=m
+CONFIG_IP6_NF_TARGET_REJECT=m
+CONFIG_IP6_NF_MANGLE=m
+CONFIG_IP6_NF_RAW=m
+CONFIG_IP6_NF_SECURITY=m
+CONFIG_DECNET_NF_GRABULATOR=m
+CONFIG_BRIDGE_NF_EBTABLES=m
+CONFIG_BRIDGE_EBT_BROUTE=m
+CONFIG_BRIDGE_EBT_T_FILTER=m
+CONFIG_BRIDGE_EBT_T_NAT=m
+CONFIG_BRIDGE_EBT_802_3=m
+CONFIG_BRIDGE_EBT_AMONG=m
+CONFIG_BRIDGE_EBT_ARP=m
+CONFIG_BRIDGE_EBT_IP=m
+CONFIG_BRIDGE_EBT_IP6=m
+CONFIG_BRIDGE_EBT_LIMIT=m
+CONFIG_BRIDGE_EBT_MARK=m
+CONFIG_BRIDGE_EBT_PKTTYPE=m
+CONFIG_BRIDGE_EBT_STP=m
+CONFIG_BRIDGE_EBT_VLAN=m
+CONFIG_BRIDGE_EBT_ARPREPLY=m
+CONFIG_BRIDGE_EBT_DNAT=m
+CONFIG_BRIDGE_EBT_MARK_T=m
+CONFIG_BRIDGE_EBT_REDIRECT=m
+CONFIG_BRIDGE_EBT_SNAT=m
+CONFIG_BRIDGE_EBT_LOG=m
+CONFIG_BRIDGE_EBT_ULOG=m
+CONFIG_BRIDGE_EBT_NFLOG=m
+CONFIG_IP_DCCP=m
+CONFIG_RDS=m
+CONFIG_RDS_TCP=m
+CONFIG_TIPC=m
+CONFIG_ATM=m
+CONFIG_ATM_CLIP=m
+CONFIG_ATM_LANE=m
+CONFIG_ATM_MPOA=m
+CONFIG_ATM_BR2684=m
+CONFIG_BRIDGE=m
+CONFIG_VLAN_8021Q=m
+CONFIG_VLAN_8021Q_GVRP=y
+CONFIG_DECNET=m
+CONFIG_LLC2=m
+CONFIG_IPX=m
+CONFIG_ATALK=m
+CONFIG_DEV_APPLETALK=m
+CONFIG_IPDDP=m
+CONFIG_IPDDP_ENCAP=y
+CONFIG_IPDDP_DECAP=y
+CONFIG_X25=m
+CONFIG_LAPB=m
+CONFIG_ECONET=m
+CONFIG_ECONET_AUNUDP=y
+CONFIG_ECONET_NATIVE=y
+CONFIG_WAN_ROUTER=m
+CONFIG_PHONET=m
+CONFIG_IEEE802154=m
+CONFIG_NET_SCHED=y
+CONFIG_NET_SCH_CBQ=m
+CONFIG_NET_SCH_HTB=m
+CONFIG_NET_SCH_HFSC=m
+CONFIG_NET_SCH_ATM=m
+CONFIG_NET_SCH_PRIO=m
+CONFIG_NET_SCH_MULTIQ=m
+CONFIG_NET_SCH_RED=m
+CONFIG_NET_SCH_SFQ=m
+CONFIG_NET_SCH_TEQL=m
+CONFIG_NET_SCH_TBF=m
+CONFIG_NET_SCH_GRED=m
+CONFIG_NET_SCH_DSMARK=m
+CONFIG_NET_SCH_NETEM=m
+CONFIG_NET_SCH_DRR=m
+CONFIG_NET_SCH_INGRESS=m
+CONFIG_NET_CLS_BASIC=m
+CONFIG_NET_CLS_TCINDEX=m
+CONFIG_NET_CLS_ROUTE4=m
+CONFIG_NET_CLS_FW=m
+CONFIG_NET_CLS_U32=m
+CONFIG_CLS_U32_MARK=y
+CONFIG_NET_CLS_RSVP=m
+CONFIG_NET_CLS_RSVP6=m
+CONFIG_NET_CLS_FLOW=m
+CONFIG_NET_EMATCH=y
+CONFIG_NET_EMATCH_CMP=m
+CONFIG_NET_EMATCH_NBYTE=m
+CONFIG_NET_EMATCH_U32=m
+CONFIG_NET_EMATCH_META=m
+CONFIG_NET_EMATCH_TEXT=m
+CONFIG_NET_CLS_ACT=y
+CONFIG_NET_ACT_POLICE=m
+CONFIG_NET_ACT_GACT=m
+CONFIG_GACT_PROB=y
+CONFIG_NET_ACT_MIRRED=m
+CONFIG_NET_ACT_IPT=m
+CONFIG_NET_ACT_NAT=m
+CONFIG_NET_ACT_PEDIT=m
+CONFIG_NET_ACT_SIMP=m
+CONFIG_NET_ACT_SKBEDIT=m
+CONFIG_DCB=y
+CONFIG_NET_PKTGEN=m
+# CONFIG_WIRELESS is not set
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_STANDALONE is not set
+CONFIG_CONNECTOR=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_CRYPTOLOOP=m
+CONFIG_BLK_DEV_NBD=m
+CONFIG_BLK_DEV_OSD=m
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=65536
+CONFIG_CDROM_PKTCDVD=y
+CONFIG_RAID_ATTRS=m
+CONFIG_SCSI=y
+CONFIG_SCSI_TGT=m
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_ST=m
+CONFIG_CHR_DEV_OSST=m
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_CHR_DEV_SCH=m
+CONFIG_SCSI_MULTI_LUN=y
+CONFIG_SCSI_CONSTANTS=y
+CONFIG_SCSI_LOGGING=y
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_SCSI_SPI_ATTRS=m
+CONFIG_SCSI_FC_TGT_ATTRS=y
+CONFIG_SCSI_SAS_LIBSAS=m
+CONFIG_SCSI_SRP_ATTRS=m
+CONFIG_SCSI_SRP_TGT_ATTRS=y
+CONFIG_ISCSI_TCP=m
+CONFIG_LIBFCOE=m
+CONFIG_SCSI_DEBUG=m
+CONFIG_SCSI_DH=y
+CONFIG_SCSI_DH_RDAC=m
+CONFIG_SCSI_DH_HP_SW=m
+CONFIG_SCSI_DH_EMC=m
+CONFIG_SCSI_DH_ALUA=m
+CONFIG_SCSI_OSD_INITIATOR=m
+CONFIG_SCSI_OSD_ULD=m
+# CONFIG_INPUT_MOUSEDEV is not set
+CONFIG_INPUT_EVDEV=y
+CONFIG_INPUT_EVBUG=m
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO_I8042 is not set
+CONFIG_SERIO_SERPORT=m
+CONFIG_SERIO_LIBPS2=y
+CONFIG_SERIO_RAW=m
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_DEVPTS_MULTIPLE_INSTANCES=y
+CONFIG_LEGACY_PTY_COUNT=0
+CONFIG_SERIAL_NONSTANDARD=y
+CONFIG_N_HDLC=m
+# CONFIG_DEVKMEM is not set
+CONFIG_STALDRV=y
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=48
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250_RSA=y
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_TIMERIOMEM=m
+CONFIG_RAW_DRIVER=m
+# CONFIG_HWMON is not set
+# CONFIG_VGA_CONSOLE is not set
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+CONFIG_UIO=y
+CONFIG_UIO_PDRV=m
+CONFIG_UIO_PDRV_GENIRQ=m
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+CONFIG_GFS2_FS=m
+CONFIG_GFS2_FS_LOCKING_DLM=y
+CONFIG_OCFS2_FS=m
+CONFIG_BTRFS_FS=m
+CONFIG_BTRFS_FS_POSIX_ACL=y
+CONFIG_NILFS2_FS=m
+CONFIG_QUOTA_NETLINK_INTERFACE=y
+# CONFIG_PRINT_QUOTA_WARNING is not set
+CONFIG_QFMT_V1=m
+CONFIG_QFMT_V2=m
+CONFIG_AUTOFS4_FS=m
+CONFIG_FUSE_FS=y
+CONFIG_CUSE=m
+CONFIG_FSCACHE=m
+CONFIG_FSCACHE_STATS=y
+CONFIG_FSCACHE_HISTOGRAM=y
+CONFIG_CACHEFILES=m
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=m
+CONFIG_NTFS_FS=m
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_ADFS_FS=m
+CONFIG_AFFS_FS=m
+CONFIG_ECRYPT_FS=y
+CONFIG_HFS_FS=m
+CONFIG_HFSPLUS_FS=m
+CONFIG_BEFS_FS=m
+CONFIG_BFS_FS=m
+CONFIG_EFS_FS=m
+CONFIG_CRAMFS=m
+CONFIG_SQUASHFS=m
+CONFIG_VXFS_FS=m
+CONFIG_MINIX_FS=m
+CONFIG_OMFS_FS=m
+CONFIG_HPFS_FS=m
+CONFIG_QNX4FS_FS=m
+CONFIG_ROMFS_FS=m
+CONFIG_SYSV_FS=m
+CONFIG_UFS_FS=m
+CONFIG_EXOFS_FS=m
+CONFIG_NFS_FS=m
+CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_NFS_FSCACHE=y
+CONFIG_NFSD=m
+CONFIG_NFSD_V3_ACL=y
+CONFIG_NFSD_V4=y
+CONFIG_CIFS=m
+CONFIG_CIFS_WEAK_PW_HASH=y
+CONFIG_CIFS_UPCALL=y
+CONFIG_CIFS_XATTR=y
+CONFIG_CIFS_POSIX=y
+CONFIG_CIFS_DFS_UPCALL=y
+CONFIG_NCP_FS=m
+CONFIG_NCPFS_PACKET_SIGNING=y
+CONFIG_NCPFS_IOCTL_LOCKING=y
+CONFIG_NCPFS_STRONG=y
+CONFIG_NCPFS_NFS_NS=y
+CONFIG_NCPFS_OS2_NS=y
+CONFIG_NCPFS_NLS=y
+CONFIG_NCPFS_EXTRAS=y
+CONFIG_CODA_FS=m
+CONFIG_AFS_FS=m
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_ACORN_PARTITION=y
+CONFIG_ACORN_PARTITION_ICS=y
+CONFIG_ACORN_PARTITION_RISCIX=y
+CONFIG_OSF_PARTITION=y
+CONFIG_AMIGA_PARTITION=y
+CONFIG_ATARI_PARTITION=y
+CONFIG_MAC_PARTITION=y
+CONFIG_BSD_DISKLABEL=y
+CONFIG_MINIX_SUBPARTITION=y
+CONFIG_SOLARIS_X86_PARTITION=y
+CONFIG_UNIXWARE_DISKLABEL=y
+CONFIG_LDM_PARTITION=y
+CONFIG_SGI_PARTITION=y
+CONFIG_ULTRIX_PARTITION=y
+CONFIG_SUN_PARTITION=y
+CONFIG_KARMA_PARTITION=y
+CONFIG_EFI_PARTITION=y
+CONFIG_SYSV68_PARTITION=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="cp437"
+CONFIG_NLS_CODEPAGE_437=m
+CONFIG_NLS_CODEPAGE_737=m
+CONFIG_NLS_CODEPAGE_775=m
+CONFIG_NLS_CODEPAGE_850=m
+CONFIG_NLS_CODEPAGE_852=m
+CONFIG_NLS_CODEPAGE_855=m
+CONFIG_NLS_CODEPAGE_857=m
+CONFIG_NLS_CODEPAGE_860=m
+CONFIG_NLS_CODEPAGE_861=m
+CONFIG_NLS_CODEPAGE_862=m
+CONFIG_NLS_CODEPAGE_863=m
+CONFIG_NLS_CODEPAGE_864=m
+CONFIG_NLS_CODEPAGE_865=m
+CONFIG_NLS_CODEPAGE_866=m
+CONFIG_NLS_CODEPAGE_869=m
+CONFIG_NLS_CODEPAGE_936=m
+CONFIG_NLS_CODEPAGE_950=m
+CONFIG_NLS_CODEPAGE_932=m
+CONFIG_NLS_CODEPAGE_949=m
+CONFIG_NLS_CODEPAGE_874=m
+CONFIG_NLS_ISO8859_8=m
+CONFIG_NLS_CODEPAGE_1250=m
+CONFIG_NLS_CODEPAGE_1251=m
+CONFIG_NLS_ASCII=m
+CONFIG_NLS_ISO8859_1=m
+CONFIG_NLS_ISO8859_2=m
+CONFIG_NLS_ISO8859_3=m
+CONFIG_NLS_ISO8859_4=m
+CONFIG_NLS_ISO8859_5=m
+CONFIG_NLS_ISO8859_6=m
+CONFIG_NLS_ISO8859_7=m
+CONFIG_NLS_ISO8859_9=m
+CONFIG_NLS_ISO8859_13=m
+CONFIG_NLS_ISO8859_14=m
+CONFIG_NLS_ISO8859_15=m
+CONFIG_NLS_KOI8_R=m
+CONFIG_NLS_KOI8_U=m
+CONFIG_PRINTK_TIME=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_FRAME_WARN=1024
+CONFIG_UNUSED_SYMBOLS=y
+CONFIG_DETECT_HUNG_TASK=y
+CONFIG_SCHEDSTATS=y
+CONFIG_TIMER_STATS=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_SCHED_TRACER=y
+CONFIG_BLK_DEV_IO_TRACE=y
+CONFIG_KGDB=y
+CONFIG_SECURITY=y
+CONFIG_SECURITY_NETWORK=y
+CONFIG_LSM_MMAP_MIN_ADDR=0
+CONFIG_SECURITY_SELINUX=y
+CONFIG_SECURITY_SELINUX_BOOTPARAM=y
+CONFIG_SECURITY_SELINUX_BOOTPARAM_VALUE=0
+CONFIG_SECURITY_SELINUX_DISABLE=y
+CONFIG_SECURITY_SMACK=y
+CONFIG_SECURITY_TOMOYO=y
+CONFIG_CRYPTO_NULL=m
+CONFIG_CRYPTO_CRYPTD=m
+CONFIG_CRYPTO_TEST=m
+CONFIG_CRYPTO_CCM=m
+CONFIG_CRYPTO_GCM=m
+CONFIG_CRYPTO_CTS=m
+CONFIG_CRYPTO_LRW=m
+CONFIG_CRYPTO_PCBC=m
+CONFIG_CRYPTO_XTS=m
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_XCBC=m
+CONFIG_CRYPTO_VMAC=m
+CONFIG_CRYPTO_MICHAEL_MIC=m
+CONFIG_CRYPTO_RMD128=m
+CONFIG_CRYPTO_RMD160=m
+CONFIG_CRYPTO_RMD256=m
+CONFIG_CRYPTO_RMD320=m
+CONFIG_CRYPTO_SHA256=m
+CONFIG_CRYPTO_SHA512=m
+CONFIG_CRYPTO_TGR192=m
+CONFIG_CRYPTO_WP512=m
+CONFIG_CRYPTO_ANUBIS=m
+CONFIG_CRYPTO_BLOWFISH=m
+CONFIG_CRYPTO_CAMELLIA=m
+CONFIG_CRYPTO_CAST5=m
+CONFIG_CRYPTO_CAST6=m
+CONFIG_CRYPTO_FCRYPT=m
+CONFIG_CRYPTO_KHAZAD=m
+CONFIG_CRYPTO_SALSA20=m
+CONFIG_CRYPTO_SEED=m
+CONFIG_CRYPTO_SERPENT=m
+CONFIG_CRYPTO_TEA=m
+CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_ZLIB=m
+CONFIG_CRYPTO_LZO=m
+CONFIG_CRC_CCITT=m
+CONFIG_CRC7=m
diff --git a/arch/mips/configs/nlm_xlr_defconfig b/arch/mips/configs/nlm_xlr_defconfig
index e4b399fdaa6..7c68666fdd6 100644
--- a/arch/mips/configs/nlm_xlr_defconfig
+++ b/arch/mips/configs/nlm_xlr_defconfig
@@ -8,7 +8,7 @@ CONFIG_HIGH_RES_TIMERS=y
 CONFIG_PREEMPT_VOLUNTARY=y
 CONFIG_KEXEC=y
 CONFIG_EXPERIMENTAL=y
-CONFIG_CROSS_COMPILE="mips64-unknown-linux-gnu-"
+CONFIG_CROSS_COMPILE="mips-linux-gnu-"
 # CONFIG_LOCALVERSION_AUTO is not set
 CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
@@ -22,15 +22,13 @@ CONFIG_AUDIT=y
 CONFIG_NAMESPACES=y
 CONFIG_SCHED_AUTOGROUP=y
 CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE="usr/dev_file_list usr/rootfs"
+CONFIG_INITRAMFS_SOURCE="usr/dev_file_list usr/rootfs.xlr"
 CONFIG_RD_BZIP2=y
 CONFIG_RD_LZMA=y
 CONFIG_INITRAMFS_COMPRESSION_GZIP=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_EXPERT=y
 CONFIG_KALLSYMS_ALL=y
 # CONFIG_ELF_CORE is not set
-# CONFIG_PCSPKR_PLATFORM is not set
 # CONFIG_PERF_EVENTS is not set
 # CONFIG_COMPAT_BRK is not set
 CONFIG_PROFILING=y
@@ -39,6 +37,9 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_MODVERSIONS=y
 CONFIG_MODULE_SRCVERSION_ALL=y
 CONFIG_BLK_DEV_INTEGRITY=y
+CONFIG_PCI=y
+CONFIG_PCI_MSI=y
+CONFIG_PCI_DEBUG=y
 CONFIG_BINFMT_MISC=m
 CONFIG_PM_RUNTIME=y
 CONFIG_PM_DEBUG=y
@@ -297,12 +298,10 @@ CONFIG_NET_ACT_SIMP=m
 CONFIG_NET_ACT_SKBEDIT=m
 CONFIG_DCB=y
 CONFIG_NET_PKTGEN=m
-# CONFIG_WIRELESS is not set
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
 # CONFIG_STANDALONE is not set
 CONFIG_CONNECTOR=y
-CONFIG_MTD=m
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_CRYPTOLOOP=m
 CONFIG_BLK_DEV_NBD=m
@@ -339,6 +338,9 @@ CONFIG_SCSI_DH_EMC=m
 CONFIG_SCSI_DH_ALUA=m
 CONFIG_SCSI_OSD_INITIATOR=m
 CONFIG_SCSI_OSD_ULD=m
+CONFIG_NETDEVICES=y
+CONFIG_E1000E=y
+CONFIG_SKY2=y
 # CONFIG_INPUT_MOUSEDEV is not set
 CONFIG_INPUT_EVDEV=y
 CONFIG_INPUT_EVBUG=m
@@ -443,7 +445,6 @@ CONFIG_CIFS_UPCALL=y
 CONFIG_CIFS_XATTR=y
 CONFIG_CIFS_POSIX=y
 CONFIG_CIFS_DFS_UPCALL=y
-CONFIG_CIFS_EXPERIMENTAL=y
 CONFIG_NCP_FS=m
 CONFIG_NCPFS_PACKET_SIGNING=y
 CONFIG_NCPFS_IOCTL_LOCKING=y
@@ -516,7 +517,6 @@ CONFIG_PRINTK_TIME=y
 # CONFIG_ENABLE_WARN_DEPRECATED is not set
 # CONFIG_ENABLE_MUST_CHECK is not set
 CONFIG_UNUSED_SYMBOLS=y
-CONFIG_DEBUG_KERNEL=y
 CONFIG_DETECT_HUNG_TASK=y
 CONFIG_SCHEDSTATS=y
 CONFIG_TIMER_STATS=y
diff --git a/arch/mips/include/asm/bmips.h b/arch/mips/include/asm/bmips.h
new file mode 100644
index 00000000000..552a65a0cf2
--- /dev/null
+++ b/arch/mips/include/asm/bmips.h
@@ -0,0 +1,110 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2011 by Kevin Cernekee (cernekee@gmail.com)
+ *
+ * Definitions for BMIPS processors
+ */
+#ifndef _ASM_BMIPS_H
+#define _ASM_BMIPS_H
+
+#include <linux/compiler.h>
+#include <linux/linkage.h>
+#include <asm/addrspace.h>
+#include <asm/mipsregs.h>
+#include <asm/hazards.h>
+
+/* NOTE: the CBR register returns a PA, and it can be above 0xff00_0000 */
+#define BMIPS_GET_CBR()                 ((void __iomem *)(CKSEG1 | \
+                                         (unsigned long) \
+                                         ((read_c0_brcm_cbr() >> 18) << 18)))
+
+#define BMIPS_RAC_CONFIG                0x00000000
+#define BMIPS_RAC_ADDRESS_RANGE         0x00000004
+#define BMIPS_RAC_CONFIG_1              0x00000008
+#define BMIPS_L2_CONFIG                 0x0000000c
+#define BMIPS_LMB_CONTROL               0x0000001c
+#define BMIPS_SYSTEM_BASE               0x00000020
+#define BMIPS_PERF_GLOBAL_CONTROL       0x00020000
+#define BMIPS_PERF_CONTROL_0            0x00020004
+#define BMIPS_PERF_CONTROL_1            0x00020008
+#define BMIPS_PERF_COUNTER_0            0x00020010
+#define BMIPS_PERF_COUNTER_1            0x00020014
+#define BMIPS_PERF_COUNTER_2            0x00020018
+#define BMIPS_PERF_COUNTER_3            0x0002001c
+#define BMIPS_RELO_VECTOR_CONTROL_0     0x00030000
+#define BMIPS_RELO_VECTOR_CONTROL_1     0x00038000
+
+#define BMIPS_NMI_RESET_VEC             0x80000000
+#define BMIPS_WARM_RESTART_VEC          0x80000380
+
+#define ZSCM_REG_BASE                   0x97000000
+
+#if !defined(__ASSEMBLY__)
+
+#include <linux/cpumask.h>
+#include <asm/r4kcache.h>
+
+extern struct plat_smp_ops bmips_smp_ops;
+extern char bmips_reset_nmi_vec;
+extern char bmips_reset_nmi_vec_end;
+extern char bmips_smp_movevec;
+extern char bmips_smp_int_vec;
+extern char bmips_smp_int_vec_end;
+
+extern int bmips_smp_enabled;
+extern int bmips_cpu_offset;
+extern cpumask_t bmips_booted_mask;
+
+extern void bmips_ebase_setup(void);
+extern asmlinkage void plat_wired_tlb_setup(void);
+
+static inline unsigned long bmips_read_zscm_reg(unsigned int offset)
+{
+        unsigned long ret;
+
+        __asm__ __volatile__(
+                ".set push\n"
+                ".set noreorder\n"
+                "cache %1, 0(%2)\n"
+                "sync\n"
+                "_ssnop\n"
+                "_ssnop\n"
+                "_ssnop\n"
+                "_ssnop\n"
+                "_ssnop\n"
+                "_ssnop\n"
+                "_ssnop\n"
+                "mfc0 %0, $28, 3\n"
+                "_ssnop\n"
+                ".set pop\n"
+                : "=&r" (ret)
+                : "i" (Index_Load_Tag_S), "r" (ZSCM_REG_BASE + offset)
+                : "memory");
+        return ret;
+}
+
+static inline void bmips_write_zscm_reg(unsigned int offset, unsigned long data)
+{
+        __asm__ __volatile__(
+                ".set push\n"
+                ".set noreorder\n"
+                "mtc0 %0, $28, 3\n"
+                "_ssnop\n"
+                "_ssnop\n"
+                "_ssnop\n"
+                "cache %1, 0(%2)\n"
+                "_ssnop\n"
+                "_ssnop\n"
+                "_ssnop\n"
+                : /* no outputs */
+                : "r" (data),
+                  "i" (Index_Store_Tag_S), "r" (ZSCM_REG_BASE + offset)
+                : "memory");
+}
+
+#endif /* !defined(__ASSEMBLY__) */
+
+#endif /* _ASM_BMIPS_H */
diff --git a/arch/mips/include/asm/branch.h b/arch/mips/include/asm/branch.h
index 37c6857c8d4..888766ae1f8 100644
--- a/arch/mips/include/asm/branch.h
+++ b/arch/mips/include/asm/branch.h
@@ -9,6 +9,7 @@
 #define _ASM_BRANCH_H
 
 #include <asm/ptrace.h>
+#include <asm/inst.h>
 
 static inline int delay_slot(struct pt_regs *regs)
 {
@@ -23,7 +24,11 @@ static inline unsigned long exception_epc(struct pt_regs *regs)
         return regs->cp0_epc + 4;
 }
 
+#define BRANCH_LIKELY_TAKEN 0x0001
+
 extern int __compute_return_epc(struct pt_regs *regs);
+extern int __compute_return_epc_for_insn(struct pt_regs *regs,
+                                         union mips_instruction insn);
 
 static inline int compute_return_epc(struct pt_regs *regs)
 {
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 79e4a0dad0d..f9fa2a479dd 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -171,6 +171,9 @@
 #define PRID_IMP_NETLOGIC_XLS404B       0x4f00
 #define PRID_IMP_NETLOGIC_AU13XX        0x8000
 
+#define PRID_IMP_NETLOGIC_XLP8XX        0x1000
+#define PRID_IMP_NETLOGIC_XLP3XX        0x1100
+
 /*
  * Definitions for 7:0 on legacy processors
  */
@@ -264,7 +267,7 @@ enum cpu_type_enum {
          */
         CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
         CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2,
-        CPU_XLR,
+        CPU_XLR, CPU_XLP,
 
         CPU_LAST
 };
diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h
index 4e332165d7b..b4c20e4f87c 100644
--- a/arch/mips/include/asm/hazards.h
+++ b/arch/mips/include/asm/hazards.h
@@ -87,7 +87,8 @@ do {									\
         : "=r" (tmp));                                                  \
 } while (0)
 
-#elif defined(CONFIG_CPU_MIPSR1) && !defined(CONFIG_MIPS_ALCHEMY)
+#elif (defined(CONFIG_CPU_MIPSR1) && !defined(CONFIG_MIPS_ALCHEMY)) || \
+        defined(CONFIG_CPU_BMIPS)
 
 /*
  * These are slightly complicated by the fact that we guarantee R1 kernels to
@@ -139,8 +140,8 @@ do {									\
 } while (0)
 
 #elif defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \
-      defined(CONFIG_CPU_LOONGSON2) || defined(CONFIG_CPU_R10000) || \
-      defined(CONFIG_CPU_R5500)
+        defined(CONFIG_CPU_LOONGSON2) || defined(CONFIG_CPU_R10000) || \
+        defined(CONFIG_CPU_R5500)
 
 /*
  * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
diff --git a/arch/mips/include/asm/kprobes.h b/arch/mips/include/asm/kprobes.h
index e6ea4d4d720..1fbbca01e68 100644
--- a/arch/mips/include/asm/kprobes.h
+++ b/arch/mips/include/asm/kprobes.h
@@ -74,6 +74,8 @@ struct prev_kprobe {
                 : MAX_JPROBES_STACK_SIZE)
 
 
+#define SKIP_DELAYSLOT 0x0001
+
 /* per-cpu kprobe control block */
 struct kprobe_ctlblk {
         unsigned long kprobe_status;
@@ -82,6 +84,9 @@ struct kprobe_ctlblk {
         unsigned long kprobe_saved_epc;
         unsigned long jprobe_saved_sp;
         struct pt_regs jprobe_saved_regs;
+        /* Per-thread fields, used while emulating branches */
+        unsigned long flags;
+        unsigned long target_epc;
         u8 jprobes_stack[MAX_JPROBES_STACK_SIZE];
         struct prev_kprobe prev_kprobe;
 };
diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
index cda1c8070b2..2f0becb4ec8 100644
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
@@ -20,6 +20,10 @@
 #include <linux/bitops.h>
 
 #define AR71XX_APB_BASE         0x18000000
+#define AR71XX_EHCI_BASE        0x1b000000
+#define AR71XX_EHCI_SIZE        0x1000
+#define AR71XX_OHCI_BASE        0x1c000000
+#define AR71XX_OHCI_SIZE        0x1000
 #define AR71XX_SPI_BASE         0x1f000000
 #define AR71XX_SPI_SIZE         0x01000000
 
@@ -27,6 +31,8 @@
 #define AR71XX_DDR_CTRL_SIZE    0x100
 #define AR71XX_UART_BASE        (AR71XX_APB_BASE + 0x00020000)
 #define AR71XX_UART_SIZE        0x100
+#define AR71XX_USB_CTRL_BASE    (AR71XX_APB_BASE + 0x00030000)
+#define AR71XX_USB_CTRL_SIZE    0x100
 #define AR71XX_GPIO_BASE        (AR71XX_APB_BASE + 0x00040000)
 #define AR71XX_GPIO_SIZE        0x100
 #define AR71XX_PLL_BASE         (AR71XX_APB_BASE + 0x00050000)
@@ -34,9 +40,26 @@
 #define AR71XX_RESET_BASE       (AR71XX_APB_BASE + 0x00060000)
 #define AR71XX_RESET_SIZE       0x100
 
+#define AR7240_USB_CTRL_BASE    (AR71XX_APB_BASE + 0x00030000)
+#define AR7240_USB_CTRL_SIZE    0x100
+#define AR7240_OHCI_BASE        0x1b000000
+#define AR7240_OHCI_SIZE        0x1000
+
+#define AR724X_EHCI_BASE        0x1b000000
+#define AR724X_EHCI_SIZE        0x1000
+
+#define AR913X_EHCI_BASE        0x1b000000
+#define AR913X_EHCI_SIZE        0x1000
 #define AR913X_WMAC_BASE        (AR71XX_APB_BASE + 0x000C0000)
 #define AR913X_WMAC_SIZE        0x30000
 
+#define AR933X_UART_BASE        (AR71XX_APB_BASE + 0x00020000)
+#define AR933X_UART_SIZE        0x14
+#define AR933X_WMAC_BASE        (AR71XX_APB_BASE + 0x00100000)
+#define AR933X_WMAC_SIZE        0x20000
+#define AR933X_EHCI_BASE        0x1b000000
+#define AR933X_EHCI_SIZE        0x1000
+
 /*
  * DDR_CTRL block
  */
@@ -63,6 +86,11 @@
 #define AR913X_DDR_REG_FLUSH_USB        0x84
 #define AR913X_DDR_REG_FLUSH_WMAC       0x88
 
+#define AR933X_DDR_REG_FLUSH_GE0        0x7c
+#define AR933X_DDR_REG_FLUSH_GE1        0x80
+#define AR933X_DDR_REG_FLUSH_USB        0x84
+#define AR933X_DDR_REG_FLUSH_WMAC       0x88
+
 /*
  * PLL block
  */
@@ -104,6 +132,30 @@
 #define AR913X_AHB_DIV_SHIFT            19
 #define AR913X_AHB_DIV_MASK             0x1
 
+#define AR933X_PLL_CPU_CONFIG_REG       0x00
+#define AR933X_PLL_CLOCK_CTRL_REG       0x08
+
+#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT        10
+#define AR933X_PLL_CPU_CONFIG_NINT_MASK         0x3f
+#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT      16
+#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK       0x1f
+#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT      23
+#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK       0x7
+
+#define AR933X_PLL_CLOCK_CTRL_BYPASS            BIT(2)
+#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT     5
+#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK      0x3
+#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT     10
+#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK      0x3
+#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT     15
+#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK      0x7
+
+/*
+ * USB_CONFIG block
+ */
+#define AR71XX_USB_CTRL_REG_FLADJ       0x00
+#define AR71XX_USB_CTRL_REG_CONFIG      0x04
+
 /*
  * RESET block
  */
@@ -130,6 +182,13 @@
 
 #define AR724X_RESET_REG_RESET_MODULE           0x1c
 
+#define AR933X_RESET_REG_RESET_MODULE           0x1c
+#define AR933X_RESET_REG_BOOTSTRAP              0xac
+
+#define MISC_INT_ETHSW                  BIT(12)
+#define MISC_INT_TIMER4                 BIT(10)
+#define MISC_INT_TIMER3                 BIT(9)
+#define MISC_INT_TIMER2                 BIT(8)
 #define MISC_INT_DMA                    BIT(7)
 #define MISC_INT_OHCI                   BIT(6)
 #define MISC_INT_PERFC                  BIT(5)
@@ -158,14 +217,29 @@
 #define AR71XX_RESET_PCI_BUS            BIT(1)
 #define AR71XX_RESET_PCI_CORE           BIT(0)
 
+#define AR7240_RESET_USB_HOST           BIT(5)
+#define AR7240_RESET_OHCI_DLL           BIT(3)
+
 #define AR724X_RESET_GE1_MDIO           BIT(23)
 #define AR724X_RESET_GE0_MDIO           BIT(22)
 #define AR724X_RESET_PCIE_PHY_SERIAL    BIT(10)
 #define AR724X_RESET_PCIE_PHY           BIT(7)
 #define AR724X_RESET_PCIE               BIT(6)
-#define AR724X_RESET_OHCI_DLL           BIT(3)
+#define AR724X_RESET_USB_HOST           BIT(5)
+#define AR724X_RESET_USB_PHY            BIT(4)
+#define AR724X_RESET_USBSUS_OVERRIDE    BIT(3)
 
 #define AR913X_RESET_AMBA2WMAC          BIT(22)
+#define AR913X_RESET_USBSUS_OVERRIDE    BIT(10)
+#define AR913X_RESET_USB_HOST           BIT(5)
+#define AR913X_RESET_USB_PHY            BIT(4)
+
+#define AR933X_RESET_WMAC               BIT(11)
+#define AR933X_RESET_USB_HOST           BIT(5)
+#define AR933X_RESET_USB_PHY            BIT(4)
+#define AR933X_RESET_USBSUS_OVERRIDE    BIT(3)
+
+#define AR933X_BOOTSTRAP_REF_CLK_40     BIT(0)
 
 #define REV_ID_MAJOR_MASK               0xfff0
 #define REV_ID_MAJOR_AR71XX             0x00a0
@@ -173,6 +247,8 @@
 #define REV_ID_MAJOR_AR7240             0x00c0
 #define REV_ID_MAJOR_AR7241             0x0100
 #define REV_ID_MAJOR_AR7242             0x1100
+#define REV_ID_MAJOR_AR9330             0x0110
+#define REV_ID_MAJOR_AR9331             0x1110
 
 #define AR71XX_REV_ID_MINOR_MASK        0x3
 #define AR71XX_REV_ID_MINOR_AR7130      0x0
@@ -187,6 +263,8 @@
 #define AR913X_REV_ID_REVISION_MASK     0x3
 #define AR913X_REV_ID_REVISION_SHIFT    2
 
+#define AR933X_REV_ID_REVISION_MASK     0x3
+
 #define AR724X_REV_ID_REVISION_MASK     0x3
 
 /*
@@ -229,5 +307,6 @@
 #define AR71XX_GPIO_COUNT               16
 #define AR724X_GPIO_COUNT               18
 #define AR913X_GPIO_COUNT               22
+#define AR933X_GPIO_COUNT               30
 
 #endif /* __ASM_MACH_AR71XX_REGS_H */
diff --git a/arch/mips/include/asm/mach-ath79/ar933x_uart.h b/arch/mips/include/asm/mach-ath79/ar933x_uart.h
new file mode 100644
index 00000000000..52730555937
--- /dev/null
+++ b/arch/mips/include/asm/mach-ath79/ar933x_uart.h
@@ -0,0 +1,67 @@
+/*
+ *  Atheros AR933X UART defines
+ *
+ *  Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#ifndef __AR933X_UART_H
+#define __AR933X_UART_H
+
+#define AR933X_UART_REGS_SIZE           20
+#define AR933X_UART_FIFO_SIZE           16
+
+#define AR933X_UART_DATA_REG            0x00
+#define AR933X_UART_CS_REG              0x04
+#define AR933X_UART_CLOCK_REG           0x08
+#define AR933X_UART_INT_REG             0x0c
+#define AR933X_UART_INT_EN_REG          0x10
+
+#define AR933X_UART_DATA_TX_RX_MASK     0xff
+#define AR933X_UART_DATA_RX_CSR         BIT(8)
+#define AR933X_UART_DATA_TX_CSR         BIT(9)
+
+#define AR933X_UART_CS_PARITY_S         0
+#define AR933X_UART_CS_PARITY_M         0x3
+#define   AR933X_UART_CS_PARITY_NONE    0
+#define   AR933X_UART_CS_PARITY_ODD     1
+#define   AR933X_UART_CS_PARITY_EVEN    2
+#define AR933X_UART_CS_IF_MODE_S        2
+#define AR933X_UART_CS_IF_MODE_M        0x3
+#define   AR933X_UART_CS_IF_MODE_NONE   0
+#define   AR933X_UART_CS_IF_MODE_DTE    1
+#define   AR933X_UART_CS_IF_MODE_DCE    2
+#define AR933X_UART_CS_FLOW_CTRL_S      4
+#define AR933X_UART_CS_FLOW_CTRL_M      0x3
+#define AR933X_UART_CS_DMA_EN           BIT(6)
+#define AR933X_UART_CS_TX_READY_ORIDE   BIT(7)
+#define AR933X_UART_CS_RX_READY_ORIDE   BIT(8)
+#define AR933X_UART_CS_TX_READY         BIT(9)
+#define AR933X_UART_CS_RX_BREAK         BIT(10)
+#define AR933X_UART_CS_TX_BREAK         BIT(11)
+#define AR933X_UART_CS_HOST_INT         BIT(12)
+#define AR933X_UART_CS_HOST_INT_EN      BIT(13)
+#define AR933X_UART_CS_TX_BUSY          BIT(14)
+#define AR933X_UART_CS_RX_BUSY          BIT(15)
+
+#define AR933X_UART_CLOCK_STEP_M        0xffff
+#define AR933X_UART_CLOCK_SCALE_M       0xfff
+#define AR933X_UART_CLOCK_SCALE_S       16
+#define AR933X_UART_CLOCK_STEP_M        0xffff
+
+#define AR933X_UART_INT_RX_VALID        BIT(0)
+#define AR933X_UART_INT_TX_READY        BIT(1)
+#define AR933X_UART_INT_RX_FRAMING_ERR  BIT(2)
+#define AR933X_UART_INT_RX_OFLOW_ERR    BIT(3)
+#define AR933X_UART_INT_TX_OFLOW_ERR    BIT(4)
+#define AR933X_UART_INT_RX_PARITY_ERR   BIT(5)
+#define AR933X_UART_INT_RX_BREAK_ON     BIT(6)
+#define AR933X_UART_INT_RX_BREAK_OFF    BIT(7)
+#define AR933X_UART_INT_RX_FULL         BIT(8)
+#define AR933X_UART_INT_TX_EMPTY        BIT(9)
+#define AR933X_UART_INT_ALLINTS         0x3ff
+
+#endif /* __AR933X_UART_H */
diff --git a/arch/mips/include/asm/mach-ath79/ar933x_uart_platform.h b/arch/mips/include/asm/mach-ath79/ar933x_uart_platform.h
new file mode 100644
index 00000000000..6cb30f2b719
--- /dev/null
+++ b/arch/mips/include/asm/mach-ath79/ar933x_uart_platform.h
@@ -0,0 +1,18 @@
+/*
+ *  Platform data definition for Atheros AR933X UART
+ *
+ *  Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#ifndef _AR933X_UART_PLATFORM_H
+#define _AR933X_UART_PLATFORM_H
+
+struct ar933x_uart_platform_data {
+        unsigned        uartclk;
+};
+
+#endif /* _AR933X_UART_PLATFORM_H */
diff --git a/arch/mips/include/asm/mach-ath79/ath79.h b/arch/mips/include/asm/mach-ath79/ath79.h
index 6a9f168506f..6d0c6c9d562 100644
--- a/arch/mips/include/asm/mach-ath79/ath79.h
+++ b/arch/mips/include/asm/mach-ath79/ath79.h
@@ -26,10 +26,13 @@ enum ath79_soc_type {
         ATH79_SOC_AR7241,
         ATH79_SOC_AR7242,
         ATH79_SOC_AR9130,
-        ATH79_SOC_AR9132
+        ATH79_SOC_AR9132,
+        ATH79_SOC_AR9330,
+        ATH79_SOC_AR9331,
 };
 
 extern enum ath79_soc_type ath79_soc;
+extern unsigned int ath79_soc_rev;
 
 static inline int soc_is_ar71xx(void)
 {
@@ -66,6 +69,12 @@ static inline int soc_is_ar913x(void)
                 ath79_soc == ATH79_SOC_AR9132);
 }
 
+static inline int soc_is_ar933x(void)
+{
+        return (ath79_soc == ATH79_SOC_AR9330 ||
+                ath79_soc == ATH79_SOC_AR9331);
+}
+
 extern void __iomem *ath79_ddr_base;
 extern void __iomem *ath79_pll_base;
 extern void __iomem *ath79_reset_base;
diff --git a/arch/mips/include/asm/mach-ath79/irq.h b/arch/mips/include/asm/mach-ath79/irq.h
index 189bc6eb9c1..519958fe4e3 100644
--- a/arch/mips/include/asm/mach-ath79/irq.h
+++ b/arch/mips/include/asm/mach-ath79/irq.h
@@ -10,10 +10,10 @@
 #define __ASM_MACH_ATH79_IRQ_H
 
 #define MIPS_CPU_IRQ_BASE       0
-#define NR_IRQS                 16
+#define NR_IRQS                 40
 
 #define ATH79_MISC_IRQ_BASE     8
-#define ATH79_MISC_IRQ_COUNT    8
+#define ATH79_MISC_IRQ_COUNT    32
 
 #define ATH79_CPU_IRQ_IP2       (MIPS_CPU_IRQ_BASE + 2)
 #define ATH79_CPU_IRQ_USB       (MIPS_CPU_IRQ_BASE + 3)
@@ -30,6 +30,10 @@
 #define ATH79_MISC_IRQ_PERFC    (ATH79_MISC_IRQ_BASE + 5)
 #define ATH79_MISC_IRQ_OHCI     (ATH79_MISC_IRQ_BASE + 6)
 #define ATH79_MISC_IRQ_DMA      (ATH79_MISC_IRQ_BASE + 7)
+#define ATH79_MISC_IRQ_TIMER2   (ATH79_MISC_IRQ_BASE + 8)
+#define ATH79_MISC_IRQ_TIMER3   (ATH79_MISC_IRQ_BASE + 9)
+#define ATH79_MISC_IRQ_TIMER4   (ATH79_MISC_IRQ_BASE + 10)
+#define ATH79_MISC_IRQ_ETHSW    (ATH79_MISC_IRQ_BASE + 12)
 
 #include_next <irq.h>
 
diff --git a/arch/mips/include/asm/mach-ath79/pci-ath724x.h b/arch/mips/include/asm/mach-ath79/pci-ath724x.h
new file mode 100644
index 00000000000..454885fa30c
--- /dev/null
+++ b/arch/mips/include/asm/mach-ath79/pci-ath724x.h
@@ -0,0 +1,21 @@
+/*
+ *  Atheros 724x PCI support
+ *
+ *  Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#ifndef __ASM_MACH_ATH79_PCI_ATH724X_H
+#define __ASM_MACH_ATH79_PCI_ATH724X_H
+
+struct ath724x_pci_data {
+        int irq;
+        void *pdata;
+};
+
+void ath724x_pci_add_data(struct ath724x_pci_data *data, int size);
+
+#endif /* __ASM_MACH_ATH79_PCI_ATH724X_H */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
index 96a2391ad85..5b8d15bb5fe 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
@@ -13,6 +13,7 @@
 #define BCM6345_CPU_ID          0x6345
 #define BCM6348_CPU_ID          0x6348
 #define BCM6358_CPU_ID          0x6358
+#define BCM6368_CPU_ID          0x6368
 
 void __init bcm63xx_cpu_init(void);
 u16 __bcm63xx_get_cpu_id(void);
@@ -71,6 +72,19 @@ unsigned int bcm63xx_get_cpu_freq(void);
 # define BCMCPU_IS_6358()       (0)
 #endif
 
+#ifdef CONFIG_BCM63XX_CPU_6368
+# ifdef bcm63xx_get_cpu_id
+#  undef bcm63xx_get_cpu_id
+#  define bcm63xx_get_cpu_id()  __bcm63xx_get_cpu_id()
+#  define BCMCPU_RUNTIME_DETECT
+# else
+#  define bcm63xx_get_cpu_id()  BCM6368_CPU_ID
+# endif
+# define BCMCPU_IS_6368()       (bcm63xx_get_cpu_id() == BCM6368_CPU_ID)
+#else
+# define BCMCPU_IS_6368()       (0)
+#endif
+
 #ifndef bcm63xx_get_cpu_id
 #error "No CPU support configured"
 #endif
@@ -88,6 +102,7 @@ enum bcm63xx_regs_set {
         RSET_UART1,
         RSET_GPIO,
         RSET_SPI,
+        RSET_SPI2,
         RSET_UDC0,
         RSET_OHCI0,
         RSET_OHCI_PRIV,
@@ -98,10 +113,23 @@ enum bcm63xx_regs_set {
         RSET_ENET0,
         RSET_ENET1,
         RSET_ENETDMA,
+        RSET_ENETDMAC,
+        RSET_ENETDMAS,
+        RSET_ENETSW,
         RSET_EHCI0,
         RSET_SDRAM,
         RSET_MEMC,
         RSET_DDR,
+        RSET_M2M,
+        RSET_ATM,
+        RSET_XTM,
+        RSET_XTMDMA,
+        RSET_XTMDMAC,
+        RSET_XTMDMAS,
+        RSET_PCM,
+        RSET_PCMDMA,
+        RSET_PCMDMAC,
+        RSET_PCMDMAS,
 };
 
 #define RSET_DSL_LMEM_SIZE              (64 * 1024 * 4)
@@ -109,11 +137,18 @@ enum bcm63xx_regs_set {
 #define RSET_WDT_SIZE                   12
 #define RSET_ENET_SIZE                  2048
 #define RSET_ENETDMA_SIZE               2048
+#define RSET_ENETSW_SIZE                65536
 #define RSET_UART_SIZE                  24
 #define RSET_UDC_SIZE                   256
 #define RSET_OHCI_SIZE                  256
 #define RSET_EHCI_SIZE                  256
 #define RSET_PCMCIA_SIZE                12
+#define RSET_M2M_SIZE                   256
+#define RSET_ATM_SIZE                   4096
+#define RSET_XTM_SIZE                   10240
+#define RSET_XTMDMA_SIZE                256
+#define RSET_XTMDMAC_SIZE(chans)        (16 * (chans))
+#define RSET_XTMDMAS_SIZE(chans)        (16 * (chans))
 
 /*
  * 6338 register sets base address
@@ -127,6 +162,7 @@ enum bcm63xx_regs_set {
 #define BCM_6338_UART1_BASE             (0xdeadbeef)
 #define BCM_6338_GPIO_BASE              (0xfffe0400)
 #define BCM_6338_SPI_BASE               (0xfffe0c00)
+#define BCM_6338_SPI2_BASE              (0xdeadbeef)
 #define BCM_6338_UDC0_BASE              (0xdeadbeef)
 #define BCM_6338_USBDMA_BASE            (0xfffe2400)
 #define BCM_6338_OHCI0_BASE             (0xdeadbeef)
@@ -136,15 +172,27 @@ enum bcm63xx_regs_set {
 #define BCM_6338_PCMCIA_BASE            (0xdeadbeef)
 #define BCM_6338_SDRAM_REGS_BASE        (0xfffe3100)
 #define BCM_6338_DSL_BASE               (0xfffe1000)
-#define BCM_6338_SAR_BASE               (0xfffe2000)
 #define BCM_6338_UBUS_BASE              (0xdeadbeef)
 #define BCM_6338_ENET0_BASE             (0xfffe2800)
 #define BCM_6338_ENET1_BASE             (0xdeadbeef)
 #define BCM_6338_ENETDMA_BASE           (0xfffe2400)
+#define BCM_6338_ENETDMAC_BASE          (0xfffe2500)
+#define BCM_6338_ENETDMAS_BASE          (0xfffe2600)
+#define BCM_6338_ENETSW_BASE            (0xdeadbeef)
 #define BCM_6338_EHCI0_BASE             (0xdeadbeef)
 #define BCM_6338_SDRAM_BASE             (0xfffe3100)
 #define BCM_6338_MEMC_BASE              (0xdeadbeef)
 #define BCM_6338_DDR_BASE               (0xdeadbeef)
+#define BCM_6338_M2M_BASE               (0xdeadbeef)
+#define BCM_6338_ATM_BASE               (0xfffe2000)
+#define BCM_6338_XTM_BASE               (0xdeadbeef)
+#define BCM_6338_XTMDMA_BASE            (0xdeadbeef)
+#define BCM_6338_XTMDMAC_BASE           (0xdeadbeef)
+#define BCM_6338_XTMDMAS_BASE           (0xdeadbeef)
+#define BCM_6338_PCM_BASE               (0xdeadbeef)
+#define BCM_6338_PCMDMA_BASE            (0xdeadbeef)
+#define BCM_6338_PCMDMAC_BASE           (0xdeadbeef)
+#define BCM_6338_PCMDMAS_BASE           (0xdeadbeef)
 
 /*
  * 6345 register sets base address
@@ -158,24 +206,37 @@ enum bcm63xx_regs_set {
 #define BCM_6345_UART1_BASE             (0xdeadbeef)
 #define BCM_6345_GPIO_BASE              (0xfffe0400)
 #define BCM_6345_SPI_BASE               (0xdeadbeef)
+#define BCM_6345_SPI2_BASE              (0xdeadbeef)
 #define BCM_6345_UDC0_BASE              (0xdeadbeef)
 #define BCM_6345_USBDMA_BASE            (0xfffe2800)
 #define BCM_6345_ENET0_BASE             (0xfffe1800)
 #define BCM_6345_ENETDMA_BASE           (0xfffe2800)
+#define BCM_6345_ENETDMAC_BASE          (0xfffe2900)
+#define BCM_6345_ENETDMAS_BASE          (0xfffe2a00)
+#define BCM_6345_ENETSW_BASE            (0xdeadbeef)
 #define BCM_6345_PCMCIA_BASE            (0xfffe2028)
-#define BCM_6345_MPI_BASE               (0xdeadbeef)
+#define BCM_6345_MPI_BASE               (0xfffe2000)
 #define BCM_6345_OHCI0_BASE             (0xfffe2100)
 #define BCM_6345_OHCI_PRIV_BASE         (0xfffe2200)
 #define BCM_6345_USBH_PRIV_BASE         (0xdeadbeef)
 #define BCM_6345_SDRAM_REGS_BASE        (0xfffe2300)
 #define BCM_6345_DSL_BASE               (0xdeadbeef)
-#define BCM_6345_SAR_BASE               (0xdeadbeef)
 #define BCM_6345_UBUS_BASE              (0xdeadbeef)
 #define BCM_6345_ENET1_BASE             (0xdeadbeef)
 #define BCM_6345_EHCI0_BASE             (0xdeadbeef)
 #define BCM_6345_SDRAM_BASE             (0xfffe2300)
 #define BCM_6345_MEMC_BASE              (0xdeadbeef)
 #define BCM_6345_DDR_BASE               (0xdeadbeef)
+#define BCM_6345_M2M_BASE               (0xdeadbeef)
+#define BCM_6345_ATM_BASE               (0xfffe4000)
+#define BCM_6345_XTM_BASE               (0xdeadbeef)
+#define BCM_6345_XTMDMA_BASE            (0xdeadbeef)
+#define BCM_6345_XTMDMAC_BASE           (0xdeadbeef)
+#define BCM_6345_XTMDMAS_BASE           (0xdeadbeef)
+#define BCM_6345_PCM_BASE               (0xdeadbeef)
+#define BCM_6345_PCMDMA_BASE            (0xdeadbeef)
+#define BCM_6345_PCMDMAC_BASE           (0xdeadbeef)
+#define BCM_6345_PCMDMAS_BASE           (0xdeadbeef)
 
 /*
  * 6348 register sets base address
@@ -188,6 +249,7 @@ enum bcm63xx_regs_set {
 #define BCM_6348_UART1_BASE             (0xdeadbeef)
 #define BCM_6348_GPIO_BASE              (0xfffe0400)
 #define BCM_6348_SPI_BASE               (0xfffe0c00)
+#define BCM_6348_SPI2_BASE              (0xdeadbeef)
 #define BCM_6348_UDC0_BASE              (0xfffe1000)
 #define BCM_6348_OHCI0_BASE             (0xfffe1b00)
 #define BCM_6348_OHCI_PRIV_BASE         (0xfffe1c00)
@@ -195,14 +257,27 @@ enum bcm63xx_regs_set {
 #define BCM_6348_MPI_BASE               (0xfffe2000)
 #define BCM_6348_PCMCIA_BASE            (0xfffe2054)
 #define BCM_6348_SDRAM_REGS_BASE        (0xfffe2300)
+#define BCM_6348_M2M_BASE               (0xfffe2800)
 #define BCM_6348_DSL_BASE               (0xfffe3000)
 #define BCM_6348_ENET0_BASE             (0xfffe6000)
 #define BCM_6348_ENET1_BASE             (0xfffe6800)
 #define BCM_6348_ENETDMA_BASE           (0xfffe7000)
+#define BCM_6348_ENETDMAC_BASE          (0xfffe7100)
+#define BCM_6348_ENETDMAS_BASE          (0xfffe7200)
+#define BCM_6348_ENETSW_BASE            (0xdeadbeef)
 #define BCM_6348_EHCI0_BASE             (0xdeadbeef)
 #define BCM_6348_SDRAM_BASE             (0xfffe2300)
 #define BCM_6348_MEMC_BASE              (0xdeadbeef)
 #define BCM_6348_DDR_BASE               (0xdeadbeef)
+#define BCM_6348_ATM_BASE               (0xfffe4000)
+#define BCM_6348_XTM_BASE               (0xdeadbeef)
+#define BCM_6348_XTMDMA_BASE            (0xdeadbeef)
+#define BCM_6348_XTMDMAC_BASE           (0xdeadbeef)
+#define BCM_6348_XTMDMAS_BASE           (0xdeadbeef)
+#define BCM_6348_PCM_BASE               (0xdeadbeef)
+#define BCM_6348_PCMDMA_BASE            (0xdeadbeef)
+#define BCM_6348_PCMDMAC_BASE           (0xdeadbeef)
+#define BCM_6348_PCMDMAS_BASE           (0xdeadbeef)
 
 /*
  * 6358 register sets base address
@@ -215,6 +290,7 @@ enum bcm63xx_regs_set {
 #define BCM_6358_UART1_BASE             (0xfffe0120)
 #define BCM_6358_GPIO_BASE              (0xfffe0080)
 #define BCM_6358_SPI_BASE               (0xdeadbeef)
+#define BCM_6358_SPI2_BASE              (0xfffe0800)
 #define BCM_6358_UDC0_BASE              (0xfffe0800)
 #define BCM_6358_OHCI0_BASE             (0xfffe1400)
 #define BCM_6358_OHCI_PRIV_BASE         (0xdeadbeef)
@@ -222,214 +298,175 @@ enum bcm63xx_regs_set {
 #define BCM_6358_MPI_BASE               (0xfffe1000)
 #define BCM_6358_PCMCIA_BASE            (0xfffe1054)
 #define BCM_6358_SDRAM_REGS_BASE        (0xfffe2300)
+#define BCM_6358_M2M_BASE               (0xdeadbeef)
 #define BCM_6358_DSL_BASE               (0xfffe3000)
 #define BCM_6358_ENET0_BASE             (0xfffe4000)
 #define BCM_6358_ENET1_BASE             (0xfffe4800)
 #define BCM_6358_ENETDMA_BASE           (0xfffe5000)
+#define BCM_6358_ENETDMAC_BASE          (0xfffe5100)
+#define BCM_6358_ENETDMAS_BASE          (0xfffe5200)
+#define BCM_6358_ENETSW_BASE            (0xdeadbeef)
 #define BCM_6358_EHCI0_BASE             (0xfffe1300)
 #define BCM_6358_SDRAM_BASE             (0xdeadbeef)
 #define BCM_6358_MEMC_BASE              (0xfffe1200)
 #define BCM_6358_DDR_BASE               (0xfffe12a0)
+#define BCM_6358_ATM_BASE               (0xfffe2000)
+#define BCM_6358_XTM_BASE               (0xdeadbeef)
+#define BCM_6358_XTMDMA_BASE            (0xdeadbeef)
+#define BCM_6358_XTMDMAC_BASE           (0xdeadbeef)
+#define BCM_6358_XTMDMAS_BASE           (0xdeadbeef)
+#define BCM_6358_PCM_BASE               (0xfffe1600)
+#define BCM_6358_PCMDMA_BASE            (0xfffe1800)
+#define BCM_6358_PCMDMAC_BASE           (0xfffe1900)
+#define BCM_6358_PCMDMAS_BASE           (0xfffe1a00)
+
+
+/*
+ * 6368 register sets base address
+ */
+#define BCM_6368_DSL_LMEM_BASE          (0xdeadbeef)
+#define BCM_6368_PERF_BASE              (0xb0000000)
+#define BCM_6368_TIMER_BASE             (0xb0000040)
+#define BCM_6368_WDT_BASE               (0xb000005c)
+#define BCM_6368_UART0_BASE             (0xb0000100)
+#define BCM_6368_UART1_BASE             (0xb0000120)
+#define BCM_6368_GPIO_BASE              (0xb0000080)
+#define BCM_6368_SPI_BASE               (0xdeadbeef)
+#define BCM_6368_SPI2_BASE              (0xb0000800)
+#define BCM_6368_UDC0_BASE              (0xdeadbeef)
+#define BCM_6368_OHCI0_BASE             (0xb0001600)
+#define BCM_6368_OHCI_PRIV_BASE         (0xdeadbeef)
+#define BCM_6368_USBH_PRIV_BASE         (0xb0001700)
+#define BCM_6368_MPI_BASE               (0xb0001000)
+#define BCM_6368_PCMCIA_BASE            (0xb0001054)
+#define BCM_6368_SDRAM_REGS_BASE        (0xdeadbeef)
+#define BCM_6368_M2M_BASE               (0xdeadbeef)
+#define BCM_6368_DSL_BASE               (0xdeadbeef)
+#define BCM_6368_ENET0_BASE             (0xdeadbeef)
+#define BCM_6368_ENET1_BASE             (0xdeadbeef)
+#define BCM_6368_ENETDMA_BASE           (0xb0006800)
+#define BCM_6368_ENETDMAC_BASE          (0xb0006a00)
+#define BCM_6368_ENETDMAS_BASE          (0xb0006c00)
+#define BCM_6368_ENETSW_BASE            (0xb0f00000)
+#define BCM_6368_EHCI0_BASE             (0xb0001500)
+#define BCM_6368_SDRAM_BASE             (0xdeadbeef)
+#define BCM_6368_MEMC_BASE              (0xb0001200)
+#define BCM_6368_DDR_BASE               (0xb0001280)
+#define BCM_6368_ATM_BASE               (0xdeadbeef)
+#define BCM_6368_XTM_BASE               (0xb0001800)
+#define BCM_6368_XTMDMA_BASE            (0xb0005000)
+#define BCM_6368_XTMDMAC_BASE           (0xb0005200)
+#define BCM_6368_XTMDMAS_BASE           (0xb0005400)
+#define BCM_6368_PCM_BASE               (0xb0004000)
+#define BCM_6368_PCMDMA_BASE            (0xb0005800)
+#define BCM_6368_PCMDMAC_BASE           (0xb0005a00)
+#define BCM_6368_PCMDMAS_BASE           (0xb0005c00)
 
 
 extern const unsigned long *bcm63xx_regs_base;
 
+#define __GEN_RSET_BASE(__cpu, __rset)                                  \
+        case RSET_## __rset :                                           \
+                return BCM_## __cpu ##_## __rset ##_BASE;
+
+#define __GEN_RSET(__cpu)                                               \
+        switch (set) {                                                  \
+        __GEN_RSET_BASE(__cpu, DSL_LMEM)                                \
+        __GEN_RSET_BASE(__cpu, PERF)                                    \
+        __GEN_RSET_BASE(__cpu, TIMER)                                   \
+        __GEN_RSET_BASE(__cpu, WDT)                                     \
+        __GEN_RSET_BASE(__cpu, UART0)                                   \
+        __GEN_RSET_BASE(__cpu, UART1)                                   \
+        __GEN_RSET_BASE(__cpu, GPIO)                                    \
+        __GEN_RSET_BASE(__cpu, SPI)                                     \
+        __GEN_RSET_BASE(__cpu, SPI2)                                    \
+        __GEN_RSET_BASE(__cpu, UDC0)                                    \
+        __GEN_RSET_BASE(__cpu, OHCI0)                                   \
+        __GEN_RSET_BASE(__cpu, OHCI_PRIV)                               \
+        __GEN_RSET_BASE(__cpu, USBH_PRIV)                               \
+        __GEN_RSET_BASE(__cpu, MPI)                                     \
+        __GEN_RSET_BASE(__cpu, PCMCIA)                                  \
+        __GEN_RSET_BASE(__cpu, DSL)                                     \
+        __GEN_RSET_BASE(__cpu, ENET0)                                   \
+        __GEN_RSET_BASE(__cpu, ENET1)                                   \
+        __GEN_RSET_BASE(__cpu, ENETDMA)                                 \
+        __GEN_RSET_BASE(__cpu, ENETDMAC)                                \
+        __GEN_RSET_BASE(__cpu, ENETDMAS)                                \
+        __GEN_RSET_BASE(__cpu, ENETSW)                                  \
+        __GEN_RSET_BASE(__cpu, EHCI0)                                   \
+        __GEN_RSET_BASE(__cpu, SDRAM)                                   \
+        __GEN_RSET_BASE(__cpu, MEMC)                                    \
+        __GEN_RSET_BASE(__cpu, DDR)                                     \
+        __GEN_RSET_BASE(__cpu, M2M)                                     \
+        __GEN_RSET_BASE(__cpu, ATM)                                     \
+        __GEN_RSET_BASE(__cpu, XTM)                                     \
+        __GEN_RSET_BASE(__cpu, XTMDMA)                                  \
+        __GEN_RSET_BASE(__cpu, XTMDMAC)                                 \
+        __GEN_RSET_BASE(__cpu, XTMDMAS)                                 \
+        __GEN_RSET_BASE(__cpu, PCM)                                     \
+        __GEN_RSET_BASE(__cpu, PCMDMA)                                  \
+        __GEN_RSET_BASE(__cpu, PCMDMAC)                                 \
+        __GEN_RSET_BASE(__cpu, PCMDMAS)                                 \
+        }
+
+#define __GEN_CPU_REGS_TABLE(__cpu)                                     \
+        [RSET_DSL_LMEM]         = BCM_## __cpu ##_DSL_LMEM_BASE,        \
+        [RSET_PERF]             = BCM_## __cpu ##_PERF_BASE,            \
+        [RSET_TIMER]            = BCM_## __cpu ##_TIMER_BASE,           \
+        [RSET_WDT]              = BCM_## __cpu ##_WDT_BASE,             \
+        [RSET_UART0]            = BCM_## __cpu ##_UART0_BASE,           \
+        [RSET_UART1]            = BCM_## __cpu ##_UART1_BASE,           \
+        [RSET_GPIO]             = BCM_## __cpu ##_GPIO_BASE,            \
+        [RSET_SPI]              = BCM_## __cpu ##_SPI_BASE,             \
+        [RSET_SPI2]             = BCM_## __cpu ##_SPI2_BASE,            \
+        [RSET_UDC0]             = BCM_## __cpu ##_UDC0_BASE,            \
+        [RSET_OHCI0]            = BCM_## __cpu ##_OHCI0_BASE,           \
+        [RSET_OHCI_PRIV]        = BCM_## __cpu ##_OHCI_PRIV_BASE,       \
+        [RSET_USBH_PRIV]        = BCM_## __cpu ##_USBH_PRIV_BASE,       \
+        [RSET_MPI]              = BCM_## __cpu ##_MPI_BASE,             \
+        [RSET_PCMCIA]           = BCM_## __cpu ##_PCMCIA_BASE,          \
+        [RSET_DSL]              = BCM_## __cpu ##_DSL_BASE,             \
+        [RSET_ENET0]            = BCM_## __cpu ##_ENET0_BASE,           \
+        [RSET_ENET1]            = BCM_## __cpu ##_ENET1_BASE,           \
+        [RSET_ENETDMA]          = BCM_## __cpu ##_ENETDMA_BASE,         \
+        [RSET_ENETDMAC]         = BCM_## __cpu ##_ENETDMAC_BASE,        \
+        [RSET_ENETDMAS]         = BCM_## __cpu ##_ENETDMAS_BASE,        \
+        [RSET_ENETSW]           = BCM_## __cpu ##_ENETSW_BASE,          \
+        [RSET_EHCI0]            = BCM_## __cpu ##_EHCI0_BASE,           \
+        [RSET_SDRAM]            = BCM_## __cpu ##_SDRAM_BASE,           \
+        [RSET_MEMC]             = BCM_## __cpu ##_MEMC_BASE,            \
+        [RSET_DDR]              = BCM_## __cpu ##_DDR_BASE,             \
+        [RSET_M2M]              = BCM_## __cpu ##_M2M_BASE,             \
+        [RSET_ATM]              = BCM_## __cpu ##_ATM_BASE,             \
+        [RSET_XTM]              = BCM_## __cpu ##_XTM_BASE,             \
+        [RSET_XTMDMA]           = BCM_## __cpu ##_XTMDMA_BASE,          \
+        [RSET_XTMDMAC]          = BCM_## __cpu ##_XTMDMAC_BASE,         \
+        [RSET_XTMDMAS]          = BCM_## __cpu ##_XTMDMAS_BASE,         \
+        [RSET_PCM]              = BCM_## __cpu ##_PCM_BASE,             \
+        [RSET_PCMDMA]           = BCM_## __cpu ##_PCMDMA_BASE,          \
+        [RSET_PCMDMAC]          = BCM_## __cpu ##_PCMDMAC_BASE,         \
+        [RSET_PCMDMAS]          = BCM_## __cpu ##_PCMDMAS_BASE,         \
+
+
 static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
 {
 #ifdef BCMCPU_RUNTIME_DETECT
         return bcm63xx_regs_base[set];
 #else
 #ifdef CONFIG_BCM63XX_CPU_6338
-        switch (set) {
-        case RSET_DSL_LMEM:
-                return BCM_6338_DSL_LMEM_BASE;
-        case RSET_PERF:
-                return BCM_6338_PERF_BASE;
-        case RSET_TIMER:
-                return BCM_6338_TIMER_BASE;
-        case RSET_WDT:
-                return BCM_6338_WDT_BASE;
-        case RSET_UART0:
-                return BCM_6338_UART0_BASE;
-        case RSET_UART1:
-                return BCM_6338_UART1_BASE;
-        case RSET_GPIO:
-                return BCM_6338_GPIO_BASE;
-        case RSET_SPI:
-                return BCM_6338_SPI_BASE;
-        case RSET_UDC0:
-                return BCM_6338_UDC0_BASE;
-        case RSET_OHCI0:
-                return BCM_6338_OHCI0_BASE;
-        case RSET_OHCI_PRIV:
-                return BCM_6338_OHCI_PRIV_BASE;
-        case RSET_USBH_PRIV:
-                return BCM_6338_USBH_PRIV_BASE;
-        case RSET_MPI:
-                return BCM_6338_MPI_BASE;
-        case RSET_PCMCIA:
-                return BCM_6338_PCMCIA_BASE;
-        case RSET_DSL:
-                return BCM_6338_DSL_BASE;
-        case RSET_ENET0:
-                return BCM_6338_ENET0_BASE;
-        case RSET_ENET1:
-                return BCM_6338_ENET1_BASE;
-        case RSET_ENETDMA:
-                return BCM_6338_ENETDMA_BASE;
-        case RSET_EHCI0:
-                return BCM_6338_EHCI0_BASE;
-        case RSET_SDRAM:
-                return BCM_6338_SDRAM_BASE;
-        case RSET_MEMC:
-                return BCM_6338_MEMC_BASE;
-        case RSET_DDR:
-                return BCM_6338_DDR_BASE;
-        }
+        __GEN_RSET(6338)
 #endif
 #ifdef CONFIG_BCM63XX_CPU_6345
-        switch (set) {
-        case RSET_DSL_LMEM:
-                return BCM_6345_DSL_LMEM_BASE;
-        case RSET_PERF:
-                return BCM_6345_PERF_BASE;
-        case RSET_TIMER:
-                return BCM_6345_TIMER_BASE;
-        case RSET_WDT:
-                return BCM_6345_WDT_BASE;
-        case RSET_UART0:
-                return BCM_6345_UART0_BASE;
-        case RSET_UART1:
-                return BCM_6345_UART1_BASE;
-        case RSET_GPIO:
-                return BCM_6345_GPIO_BASE;
-        case RSET_SPI:
-                return BCM_6345_SPI_BASE;
-        case RSET_UDC0:
-                return BCM_6345_UDC0_BASE;
-        case RSET_OHCI0:
-                return BCM_6345_OHCI0_BASE;
-        case RSET_OHCI_PRIV:
-                return BCM_6345_OHCI_PRIV_BASE;
-        case RSET_USBH_PRIV:
-                return BCM_6345_USBH_PRIV_BASE;
-        case RSET_MPI:
-                return BCM_6345_MPI_BASE;
-        case RSET_PCMCIA:
-                return BCM_6345_PCMCIA_BASE;
-        case RSET_DSL:
-                return BCM_6345_DSL_BASE;
-        case RSET_ENET0:
-                return BCM_6345_ENET0_BASE;
-        case RSET_ENET1:
-                return BCM_6345_ENET1_BASE;
-        case RSET_ENETDMA:
-                return BCM_6345_ENETDMA_BASE;
-        case RSET_EHCI0:
-                return BCM_6345_EHCI0_BASE;
-        case RSET_SDRAM:
-                return BCM_6345_SDRAM_BASE;
-        case RSET_MEMC:
-                return BCM_6345_MEMC_BASE;
-        case RSET_DDR:
-                return BCM_6345_DDR_BASE;
-        }
+        __GEN_RSET(6345)
 #endif
 #ifdef CONFIG_BCM63XX_CPU_6348
-        switch (set) {
-        case RSET_DSL_LMEM:
-                return BCM_6348_DSL_LMEM_BASE;
-        case RSET_PERF:
-                return BCM_6348_PERF_BASE;
-        case RSET_TIMER:
-                return BCM_6348_TIMER_BASE;
-        case RSET_WDT:
-                return BCM_6348_WDT_BASE;
-        case RSET_UART0:
-                return BCM_6348_UART0_BASE;
-        case RSET_UART1:
-                return BCM_6348_UART1_BASE;
-        case RSET_GPIO:
-                return BCM_6348_GPIO_BASE;
-        case RSET_SPI:
-                return BCM_6348_SPI_BASE;
-        case RSET_UDC0:
-                return BCM_6348_UDC0_BASE;
-        case RSET_OHCI0:
-                return BCM_6348_OHCI0_BASE;
-        case RSET_OHCI_PRIV:
-                return BCM_6348_OHCI_PRIV_BASE;
-        case RSET_USBH_PRIV:
-                return BCM_6348_USBH_PRIV_BASE;
-        case RSET_MPI:
-                return BCM_6348_MPI_BASE;
-        case RSET_PCMCIA:
-                return BCM_6348_PCMCIA_BASE;
-        case RSET_DSL:
-                return BCM_6348_DSL_BASE;
-        case RSET_ENET0:
-                return BCM_6348_ENET0_BASE;
-        case RSET_ENET1:
-                return BCM_6348_ENET1_BASE;
-        case RSET_ENETDMA:
-                return BCM_6348_ENETDMA_BASE;
-        case RSET_EHCI0:
-                return BCM_6348_EHCI0_BASE;
-        case RSET_SDRAM:
-                return BCM_6348_SDRAM_BASE;
-        case RSET_MEMC:
-                return BCM_6348_MEMC_BASE;
-        case RSET_DDR:
-                return BCM_6348_DDR_BASE;
-        }
+        __GEN_RSET(6348)
 #endif
 #ifdef CONFIG_BCM63XX_CPU_6358
-        switch (set) {
-        case RSET_DSL_LMEM:
-                return BCM_6358_DSL_LMEM_BASE;
-        case RSET_PERF:
-                return BCM_6358_PERF_BASE;
-        case RSET_TIMER:
-                return BCM_6358_TIMER_BASE;
-        case RSET_WDT:
-                return BCM_6358_WDT_BASE;
-        case RSET_UART0:
-                return BCM_6358_UART0_BASE;
-        case RSET_UART1:
-                return BCM_6358_UART1_BASE;
-        case RSET_GPIO:
-                return BCM_6358_GPIO_BASE;
-        case RSET_SPI:
-                return BCM_6358_SPI_BASE;
-        case RSET_UDC0:
-                return BCM_6358_UDC0_BASE;
-        case RSET_OHCI0:
-                return BCM_6358_OHCI0_BASE;
-        case RSET_OHCI_PRIV:
-                return BCM_6358_OHCI_PRIV_BASE;
-        case RSET_USBH_PRIV:
-                return BCM_6358_USBH_PRIV_BASE;
-        case RSET_MPI:
-                return BCM_6358_MPI_BASE;
-        case RSET_PCMCIA:
-                return BCM_6358_PCMCIA_BASE;
-        case RSET_ENET0:
-                return BCM_6358_ENET0_BASE;
-        case RSET_ENET1:
-                return BCM_6358_ENET1_BASE;
-        case RSET_ENETDMA:
-                return BCM_6358_ENETDMA_BASE;
-        case RSET_DSL:
-                return BCM_6358_DSL_BASE;
-        case RSET_EHCI0:
-                return BCM_6358_EHCI0_BASE;
-        case RSET_SDRAM:
-                return BCM_6358_SDRAM_BASE;
-        case RSET_MEMC:
-                return BCM_6358_MEMC_BASE;
-        case RSET_DDR:
-                return BCM_6358_DDR_BASE;
-        }
+        __GEN_RSET(6358)
+#endif
+#ifdef CONFIG_BCM63XX_CPU_6368
+        __GEN_RSET(6368)
 #endif
 #endif
         /* unreached */
@@ -449,75 +486,114 @@ enum bcm63xx_irq {
         IRQ_ENET_PHY,
         IRQ_OHCI0,
         IRQ_EHCI0,
-        IRQ_PCMCIA0,
         IRQ_ENET0_RXDMA,
         IRQ_ENET0_TXDMA,
         IRQ_ENET1_RXDMA,
         IRQ_ENET1_TXDMA,
         IRQ_PCI,
         IRQ_PCMCIA,
+        IRQ_ATM,
+        IRQ_ENETSW_RXDMA0,
+        IRQ_ENETSW_RXDMA1,
+        IRQ_ENETSW_RXDMA2,
+        IRQ_ENETSW_RXDMA3,
+        IRQ_ENETSW_TXDMA0,
+        IRQ_ENETSW_TXDMA1,
+        IRQ_ENETSW_TXDMA2,
+        IRQ_ENETSW_TXDMA3,
+        IRQ_XTM,
+        IRQ_XTM_DMA0,
 };
 
 /*
  * 6338 irqs
  */
 #define BCM_6338_TIMER_IRQ              (IRQ_INTERNAL_BASE + 0)
-#define BCM_6338_SPI_IRQ                (IRQ_INTERNAL_BASE + 1)
 #define BCM_6338_UART0_IRQ              (IRQ_INTERNAL_BASE + 2)
-#define BCM_6338_DG_IRQ                 (IRQ_INTERNAL_BASE + 4)
+#define BCM_6338_UART1_IRQ              0
 #define BCM_6338_DSL_IRQ                (IRQ_INTERNAL_BASE + 5)
-#define BCM_6338_ATM_IRQ                (IRQ_INTERNAL_BASE + 6)
-#define BCM_6338_UDC0_IRQ               (IRQ_INTERNAL_BASE + 7)
 #define BCM_6338_ENET0_IRQ              (IRQ_INTERNAL_BASE + 8)
+#define BCM_6338_ENET1_IRQ              0
 #define BCM_6338_ENET_PHY_IRQ           (IRQ_INTERNAL_BASE + 9)
-#define BCM_6338_SDRAM_IRQ              (IRQ_INTERNAL_BASE + 10)
-#define BCM_6338_USB_CNTL_RX_DMA_IRQ    (IRQ_INTERNAL_BASE + 11)
-#define BCM_6338_USB_CNTL_TX_DMA_IRQ    (IRQ_INTERNAL_BASE + 12)
-#define BCM_6338_USB_BULK_RX_DMA_IRQ    (IRQ_INTERNAL_BASE + 13)
-#define BCM_6338_USB_BULK_TX_DMA_IRQ    (IRQ_INTERNAL_BASE + 14)
+#define BCM_6338_OHCI0_IRQ              0
+#define BCM_6338_EHCI0_IRQ              0
 #define BCM_6338_ENET0_RXDMA_IRQ        (IRQ_INTERNAL_BASE + 15)
 #define BCM_6338_ENET0_TXDMA_IRQ        (IRQ_INTERNAL_BASE + 16)
-#define BCM_6338_SDIO_IRQ               (IRQ_INTERNAL_BASE + 17)
+#define BCM_6338_ENET1_RXDMA_IRQ        0
+#define BCM_6338_ENET1_TXDMA_IRQ        0
+#define BCM_6338_PCI_IRQ                0
+#define BCM_6338_PCMCIA_IRQ             0
+#define BCM_6338_ATM_IRQ                0
+#define BCM_6338_ENETSW_RXDMA0_IRQ      0
+#define BCM_6338_ENETSW_RXDMA1_IRQ      0
+#define BCM_6338_ENETSW_RXDMA2_IRQ      0
+#define BCM_6338_ENETSW_RXDMA3_IRQ      0
+#define BCM_6338_ENETSW_TXDMA0_IRQ      0
+#define BCM_6338_ENETSW_TXDMA1_IRQ      0
+#define BCM_6338_ENETSW_TXDMA2_IRQ      0
+#define BCM_6338_ENETSW_TXDMA3_IRQ      0
+#define BCM_6338_XTM_IRQ                0
+#define BCM_6338_XTM_DMA0_IRQ           0
 
 /*
  * 6345 irqs
  */
 #define BCM_6345_TIMER_IRQ              (IRQ_INTERNAL_BASE + 0)
 #define BCM_6345_UART0_IRQ              (IRQ_INTERNAL_BASE + 2)
+#define BCM_6345_UART1_IRQ              0
 #define BCM_6345_DSL_IRQ                (IRQ_INTERNAL_BASE + 3)
-#define BCM_6345_ATM_IRQ                (IRQ_INTERNAL_BASE + 4)
-#define BCM_6345_USB_IRQ                (IRQ_INTERNAL_BASE + 5)
 #define BCM_6345_ENET0_IRQ              (IRQ_INTERNAL_BASE + 8)
+#define BCM_6345_ENET1_IRQ              0
 #define BCM_6345_ENET_PHY_IRQ           (IRQ_INTERNAL_BASE + 12)
+#define BCM_6345_OHCI0_IRQ              0
+#define BCM_6345_EHCI0_IRQ              0
 #define BCM_6345_ENET0_RXDMA_IRQ        (IRQ_INTERNAL_BASE + 13 + 1)
 #define BCM_6345_ENET0_TXDMA_IRQ        (IRQ_INTERNAL_BASE + 13 + 2)
-#define BCM_6345_EBI_RX_IRQ             (IRQ_INTERNAL_BASE + 13 + 5)
-#define BCM_6345_EBI_TX_IRQ             (IRQ_INTERNAL_BASE + 13 + 6)
-#define BCM_6345_RESERVED_RX_IRQ        (IRQ_INTERNAL_BASE + 13 + 9)
-#define BCM_6345_RESERVED_TX_IRQ        (IRQ_INTERNAL_BASE + 13 + 10)
-#define BCM_6345_USB_BULK_RX_DMA_IRQ    (IRQ_INTERNAL_BASE + 13 + 13)
-#define BCM_6345_USB_BULK_TX_DMA_IRQ    (IRQ_INTERNAL_BASE + 13 + 14)
-#define BCM_6345_USB_CNTL_RX_DMA_IRQ    (IRQ_INTERNAL_BASE + 13 + 15)
-#define BCM_6345_USB_CNTL_TX_DMA_IRQ    (IRQ_INTERNAL_BASE + 13 + 16)
-#define BCM_6345_USB_ISO_RX_DMA_IRQ     (IRQ_INTERNAL_BASE + 13 + 17)
-#define BCM_6345_USB_ISO_TX_DMA_IRQ     (IRQ_INTERNAL_BASE + 13 + 18)
+#define BCM_6345_ENET1_RXDMA_IRQ        0
+#define BCM_6345_ENET1_TXDMA_IRQ        0
+#define BCM_6345_PCI_IRQ                0
+#define BCM_6345_PCMCIA_IRQ             0
+#define BCM_6345_ATM_IRQ                0
+#define BCM_6345_ENETSW_RXDMA0_IRQ      0
+#define BCM_6345_ENETSW_RXDMA1_IRQ      0
+#define BCM_6345_ENETSW_RXDMA2_IRQ      0
+#define BCM_6345_ENETSW_RXDMA3_IRQ      0
+#define BCM_6345_ENETSW_TXDMA0_IRQ      0
+#define BCM_6345_ENETSW_TXDMA1_IRQ      0
+#define BCM_6345_ENETSW_TXDMA2_IRQ      0
+#define BCM_6345_ENETSW_TXDMA3_IRQ      0
+#define BCM_6345_XTM_IRQ                0
+#define BCM_6345_XTM_DMA0_IRQ           0
 
 /*
  * 6348 irqs
  */
 #define BCM_6348_TIMER_IRQ              (IRQ_INTERNAL_BASE + 0)
 #define BCM_6348_UART0_IRQ              (IRQ_INTERNAL_BASE + 2)
+#define BCM_6348_UART1_IRQ              0
 #define BCM_6348_DSL_IRQ                (IRQ_INTERNAL_BASE + 4)
-#define BCM_6348_ENET1_IRQ              (IRQ_INTERNAL_BASE + 7)
 #define BCM_6348_ENET0_IRQ              (IRQ_INTERNAL_BASE + 8)
+#define BCM_6348_ENET1_IRQ              (IRQ_INTERNAL_BASE + 7)
 #define BCM_6348_ENET_PHY_IRQ           (IRQ_INTERNAL_BASE + 9)
 #define BCM_6348_OHCI0_IRQ              (IRQ_INTERNAL_BASE + 12)
+#define BCM_6348_EHCI0_IRQ              0
 #define BCM_6348_ENET0_RXDMA_IRQ        (IRQ_INTERNAL_BASE + 20)
 #define BCM_6348_ENET0_TXDMA_IRQ        (IRQ_INTERNAL_BASE + 21)
 #define BCM_6348_ENET1_RXDMA_IRQ        (IRQ_INTERNAL_BASE + 22)
 #define BCM_6348_ENET1_TXDMA_IRQ        (IRQ_INTERNAL_BASE + 23)
-#define BCM_6348_PCMCIA_IRQ             (IRQ_INTERNAL_BASE + 24)
 #define BCM_6348_PCI_IRQ                (IRQ_INTERNAL_BASE + 24)
+#define BCM_6348_PCMCIA_IRQ             (IRQ_INTERNAL_BASE + 24)
+#define BCM_6348_ATM_IRQ                (IRQ_INTERNAL_BASE + 5)
+#define BCM_6348_ENETSW_RXDMA0_IRQ      0
+#define BCM_6348_ENETSW_RXDMA1_IRQ      0
+#define BCM_6348_ENETSW_RXDMA2_IRQ      0
+#define BCM_6348_ENETSW_RXDMA3_IRQ      0
+#define BCM_6348_ENETSW_TXDMA0_IRQ      0
+#define BCM_6348_ENETSW_TXDMA1_IRQ      0
+#define BCM_6348_ENETSW_TXDMA2_IRQ      0
+#define BCM_6348_ENETSW_TXDMA3_IRQ      0
+#define BCM_6348_XTM_IRQ                0
+#define BCM_6348_XTM_DMA0_IRQ           0
 
 /*
  * 6358 irqs
@@ -525,21 +601,108 @@ enum bcm63xx_irq {
 #define BCM_6358_TIMER_IRQ              (IRQ_INTERNAL_BASE + 0)
 #define BCM_6358_UART0_IRQ              (IRQ_INTERNAL_BASE + 2)
 #define BCM_6358_UART1_IRQ              (IRQ_INTERNAL_BASE + 3)
-#define BCM_6358_OHCI0_IRQ              (IRQ_INTERNAL_BASE + 5)
-#define BCM_6358_ENET1_IRQ              (IRQ_INTERNAL_BASE + 6)
+#define BCM_6358_DSL_IRQ                (IRQ_INTERNAL_BASE + 29)
 #define BCM_6358_ENET0_IRQ              (IRQ_INTERNAL_BASE + 8)
+#define BCM_6358_ENET1_IRQ              (IRQ_INTERNAL_BASE + 6)
 #define BCM_6358_ENET_PHY_IRQ           (IRQ_INTERNAL_BASE + 9)
+#define BCM_6358_OHCI0_IRQ              (IRQ_INTERNAL_BASE + 5)
 #define BCM_6358_EHCI0_IRQ              (IRQ_INTERNAL_BASE + 10)
 #define BCM_6358_ENET0_RXDMA_IRQ        (IRQ_INTERNAL_BASE + 15)
 #define BCM_6358_ENET0_TXDMA_IRQ        (IRQ_INTERNAL_BASE + 16)
 #define BCM_6358_ENET1_RXDMA_IRQ        (IRQ_INTERNAL_BASE + 17)
 #define BCM_6358_ENET1_TXDMA_IRQ        (IRQ_INTERNAL_BASE + 18)
-#define BCM_6358_DSL_IRQ                (IRQ_INTERNAL_BASE + 29)
 #define BCM_6358_PCI_IRQ                (IRQ_INTERNAL_BASE + 31)
 #define BCM_6358_PCMCIA_IRQ             (IRQ_INTERNAL_BASE + 24)
+#define BCM_6358_ATM_IRQ                (IRQ_INTERNAL_BASE + 19)
+#define BCM_6358_ENETSW_RXDMA0_IRQ      0
+#define BCM_6358_ENETSW_RXDMA1_IRQ      0
+#define BCM_6358_ENETSW_RXDMA2_IRQ      0
+#define BCM_6358_ENETSW_RXDMA3_IRQ      0
+#define BCM_6358_ENETSW_TXDMA0_IRQ      0
+#define BCM_6358_ENETSW_TXDMA1_IRQ      0
+#define BCM_6358_ENETSW_TXDMA2_IRQ      0
+#define BCM_6358_ENETSW_TXDMA3_IRQ      0
+#define BCM_6358_XTM_IRQ                0
+#define BCM_6358_XTM_DMA0_IRQ           0
+
+#define BCM_6358_PCM_DMA0_IRQ           (IRQ_INTERNAL_BASE + 23)
+#define BCM_6358_PCM_DMA1_IRQ           (IRQ_INTERNAL_BASE + 24)
+#define BCM_6358_EXT_IRQ0               (IRQ_INTERNAL_BASE + 25)
+#define BCM_6358_EXT_IRQ1               (IRQ_INTERNAL_BASE + 26)
+#define BCM_6358_EXT_IRQ2               (IRQ_INTERNAL_BASE + 27)
+#define BCM_6358_EXT_IRQ3               (IRQ_INTERNAL_BASE + 28)
+
+/*
+ * 6368 irqs
+ */
+#define BCM_6368_HIGH_IRQ_BASE          (IRQ_INTERNAL_BASE + 32)
+
+#define BCM_6368_TIMER_IRQ              (IRQ_INTERNAL_BASE + 0)
+#define BCM_6368_UART0_IRQ              (IRQ_INTERNAL_BASE + 2)
+#define BCM_6368_UART1_IRQ              (IRQ_INTERNAL_BASE + 3)
+#define BCM_6368_DSL_IRQ                (IRQ_INTERNAL_BASE + 4)
+#define BCM_6368_ENET0_IRQ              0
+#define BCM_6368_ENET1_IRQ              0
+#define BCM_6368_ENET_PHY_IRQ           (IRQ_INTERNAL_BASE + 15)
+#define BCM_6368_OHCI0_IRQ              (IRQ_INTERNAL_BASE + 5)
+#define BCM_6368_EHCI0_IRQ              (IRQ_INTERNAL_BASE + 7)
+#define BCM_6368_PCMCIA_IRQ             0
+#define BCM_6368_ENET0_RXDMA_IRQ        0
+#define BCM_6368_ENET0_TXDMA_IRQ        0
+#define BCM_6368_ENET1_RXDMA_IRQ        0
+#define BCM_6368_ENET1_TXDMA_IRQ        0
+#define BCM_6368_PCI_IRQ                (IRQ_INTERNAL_BASE + 13)
+#define BCM_6368_ATM_IRQ                0
+#define BCM_6368_ENETSW_RXDMA0_IRQ      (BCM_6368_HIGH_IRQ_BASE + 0)
+#define BCM_6368_ENETSW_RXDMA1_IRQ      (BCM_6368_HIGH_IRQ_BASE + 1)
+#define BCM_6368_ENETSW_RXDMA2_IRQ      (BCM_6368_HIGH_IRQ_BASE + 2)
+#define BCM_6368_ENETSW_RXDMA3_IRQ      (BCM_6368_HIGH_IRQ_BASE + 3)
+#define BCM_6368_ENETSW_TXDMA0_IRQ      (BCM_6368_HIGH_IRQ_BASE + 4)
+#define BCM_6368_ENETSW_TXDMA1_IRQ      (BCM_6368_HIGH_IRQ_BASE + 5)
+#define BCM_6368_ENETSW_TXDMA2_IRQ      (BCM_6368_HIGH_IRQ_BASE + 6)
+#define BCM_6368_ENETSW_TXDMA3_IRQ      (BCM_6368_HIGH_IRQ_BASE + 7)
+#define BCM_6368_XTM_IRQ                (IRQ_INTERNAL_BASE + 11)
+#define BCM_6368_XTM_DMA0_IRQ           (BCM_6368_HIGH_IRQ_BASE + 8)
+
+#define BCM_6368_PCM_DMA0_IRQ           (BCM_6368_HIGH_IRQ_BASE + 30)
+#define BCM_6368_PCM_DMA1_IRQ           (BCM_6368_HIGH_IRQ_BASE + 31)
+#define BCM_6368_EXT_IRQ0               (IRQ_INTERNAL_BASE + 20)
+#define BCM_6368_EXT_IRQ1               (IRQ_INTERNAL_BASE + 21)
+#define BCM_6368_EXT_IRQ2               (IRQ_INTERNAL_BASE + 22)
+#define BCM_6368_EXT_IRQ3               (IRQ_INTERNAL_BASE + 23)
+#define BCM_6368_EXT_IRQ4               (IRQ_INTERNAL_BASE + 24)
+#define BCM_6368_EXT_IRQ5               (IRQ_INTERNAL_BASE + 25)
 
 extern const int *bcm63xx_irqs;
 
+#define __GEN_CPU_IRQ_TABLE(__cpu)                                      \
+        [IRQ_TIMER]             = BCM_## __cpu ##_TIMER_IRQ,            \
+        [IRQ_UART0]             = BCM_## __cpu ##_UART0_IRQ,            \
+        [IRQ_UART1]             = BCM_## __cpu ##_UART1_IRQ,            \
+        [IRQ_DSL]               = BCM_## __cpu ##_DSL_IRQ,              \
+        [IRQ_ENET0]             = BCM_## __cpu ##_ENET0_IRQ,            \
+        [IRQ_ENET1]             = BCM_## __cpu ##_ENET1_IRQ,            \
+        [IRQ_ENET_PHY]          = BCM_## __cpu ##_ENET_PHY_IRQ,         \
+        [IRQ_OHCI0]             = BCM_## __cpu ##_OHCI0_IRQ,            \
+        [IRQ_EHCI0]             = BCM_## __cpu ##_EHCI0_IRQ,            \
+        [IRQ_ENET0_RXDMA]       = BCM_## __cpu ##_ENET0_RXDMA_IRQ,      \
+        [IRQ_ENET0_TXDMA]       = BCM_## __cpu ##_ENET0_TXDMA_IRQ,      \
+        [IRQ_ENET1_RXDMA]       = BCM_## __cpu ##_ENET1_RXDMA_IRQ,      \
+        [IRQ_ENET1_TXDMA]       = BCM_## __cpu ##_ENET1_TXDMA_IRQ,      \
+        [IRQ_PCI]               = BCM_## __cpu ##_PCI_IRQ,              \
+        [IRQ_PCMCIA]            = BCM_## __cpu ##_PCMCIA_IRQ,           \
+        [IRQ_ATM]               = BCM_## __cpu ##_ATM_IRQ,              \
+        [IRQ_ENETSW_RXDMA0]     = BCM_## __cpu ##_ENETSW_RXDMA0_IRQ,    \
+        [IRQ_ENETSW_RXDMA1]     = BCM_## __cpu ##_ENETSW_RXDMA1_IRQ,    \
+        [IRQ_ENETSW_RXDMA2]     = BCM_## __cpu ##_ENETSW_RXDMA2_IRQ,    \
+        [IRQ_ENETSW_RXDMA3]     = BCM_## __cpu ##_ENETSW_RXDMA3_IRQ,    \
+        [IRQ_ENETSW_TXDMA0]     = BCM_## __cpu ##_ENETSW_TXDMA0_IRQ,    \
+        [IRQ_ENETSW_TXDMA1]     = BCM_## __cpu ##_ENETSW_TXDMA1_IRQ,    \
+        [IRQ_ENETSW_TXDMA2]     = BCM_## __cpu ##_ENETSW_TXDMA2_IRQ,    \
+        [IRQ_ENETSW_TXDMA3]     = BCM_## __cpu ##_ENETSW_TXDMA3_IRQ,    \
+        [IRQ_XTM]               = BCM_## __cpu ##_XTM_IRQ,              \
+        [IRQ_XTM_DMA0]          = BCM_## __cpu ##_XTM_DMA0_IRQ,         \
+
 static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq)
 {
         return bcm63xx_irqs[irq];
@@ -550,4 +713,8 @@ static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq)
  */
 unsigned int bcm63xx_get_memory_size(void);
 
+void bcm63xx_machine_halt(void);
+
+void bcm63xx_machine_reboot(void);
+
 #endif /* !BCM63XX_CPU_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
index 3999ec0aa7f..3d5de96d403 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
@@ -14,6 +14,8 @@ static inline unsigned long bcm63xx_gpio_count(void)
                 return 8;
         case BCM6345_CPU_ID:
                 return 16;
+        case BCM6368_CPU_ID:
+                return 38;
         case BCM6348_CPU_ID:
         default:
                 return 37;
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
index 91180fac6ed..72477a6441d 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
@@ -49,9 +49,11 @@
 #define bcm_readb(a)    (*(volatile unsigned char *)    BCM_REGS_VA(a))
 #define bcm_readw(a)    (*(volatile unsigned short *)   BCM_REGS_VA(a))
 #define bcm_readl(a)    (*(volatile unsigned int *)     BCM_REGS_VA(a))
+#define bcm_readq(a)    (*(volatile u64 *)              BCM_REGS_VA(a))
 #define bcm_writeb(v, a) (*(volatile unsigned char *) BCM_REGS_VA((a)) = (v))
 #define bcm_writew(v, a) (*(volatile unsigned short *) BCM_REGS_VA((a)) = (v))
 #define bcm_writel(v, a) (*(volatile unsigned int *) BCM_REGS_VA((a)) = (v))
+#define bcm_writeq(v, a) (*(volatile u64 *) BCM_REGS_VA((a)) = (v))
 
 /*
  * IO helpers to access register set for current CPU
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h
index 5f95577c821..0c3074b871b 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h
@@ -3,13 +3,11 @@
 
 #include <bcm63xx_cpu.h>
 
-#define IRQ_MIPS_BASE                   0
 #define IRQ_INTERNAL_BASE               8
-
-#define IRQ_EXT_BASE                    (IRQ_MIPS_BASE + 3)
-#define IRQ_EXT_0                       (IRQ_EXT_BASE + 0)
-#define IRQ_EXT_1                       (IRQ_EXT_BASE + 1)
-#define IRQ_EXT_2                       (IRQ_EXT_BASE + 2)
-#define IRQ_EXT_3                       (IRQ_EXT_BASE + 3)
+#define IRQ_EXTERNAL_BASE               100
+#define IRQ_EXT_0                       (IRQ_EXTERNAL_BASE + 0)
+#define IRQ_EXT_1                       (IRQ_EXTERNAL_BASE + 1)
+#define IRQ_EXT_2                       (IRQ_EXTERNAL_BASE + 2)
+#define IRQ_EXT_3                       (IRQ_EXTERNAL_BASE + 3)
 
 #endif /* ! BCM63XX_IRQ_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
index 0ed5230243c..94d4faad29a 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -83,30 +83,86 @@
                                         CKCTL_6358_USBSU_EN |           \
                                         CKCTL_6358_EPHY_EN)
 
+#define CKCTL_6368_VDSL_QPROC_EN        (1 << 2)
+#define CKCTL_6368_VDSL_AFE_EN          (1 << 3)
+#define CKCTL_6368_VDSL_BONDING_EN      (1 << 4)
+#define CKCTL_6368_VDSL_EN              (1 << 5)
+#define CKCTL_6368_PHYMIPS_EN           (1 << 6)
+#define CKCTL_6368_SWPKT_USB_EN         (1 << 7)
+#define CKCTL_6368_SWPKT_SAR_EN         (1 << 8)
+#define CKCTL_6368_SPI_CLK_EN           (1 << 9)
+#define CKCTL_6368_USBD_CLK_EN          (1 << 10)
+#define CKCTL_6368_SAR_CLK_EN           (1 << 11)
+#define CKCTL_6368_ROBOSW_CLK_EN        (1 << 12)
+#define CKCTL_6368_UTOPIA_CLK_EN        (1 << 13)
+#define CKCTL_6368_PCM_CLK_EN           (1 << 14)
+#define CKCTL_6368_USBH_CLK_EN          (1 << 15)
+#define CKCTL_6368_DISABLE_GLESS_EN     (1 << 16)
+#define CKCTL_6368_NAND_CLK_EN          (1 << 17)
+#define CKCTL_6368_IPSEC_CLK_EN         (1 << 17)
+
+#define CKCTL_6368_ALL_SAFE_EN          (CKCTL_6368_SWPKT_USB_EN |      \
+                                        CKCTL_6368_SWPKT_SAR_EN |       \
+                                        CKCTL_6368_SPI_CLK_EN |         \
+                                        CKCTL_6368_USBD_CLK_EN |        \
+                                        CKCTL_6368_SAR_CLK_EN |         \
+                                        CKCTL_6368_ROBOSW_CLK_EN |      \
+                                        CKCTL_6368_UTOPIA_CLK_EN |      \
+                                        CKCTL_6368_PCM_CLK_EN |         \
+                                        CKCTL_6368_USBH_CLK_EN |        \
+                                        CKCTL_6368_DISABLE_GLESS_EN |   \
+                                        CKCTL_6368_NAND_CLK_EN |        \
+                                        CKCTL_6368_IPSEC_CLK_EN)
+
 /* System PLL Control register  */
 #define PERF_SYS_PLL_CTL_REG            0x8
 #define SYS_PLL_SOFT_RESET              0x1
 
 /* Interrupt Mask register */
-#define PERF_IRQMASK_REG                0xc
+#define PERF_IRQMASK_6338_REG           0xc
+#define PERF_IRQMASK_6345_REG           0xc
+#define PERF_IRQMASK_6348_REG           0xc
+#define PERF_IRQMASK_6358_REG           0xc
+#define PERF_IRQMASK_6368_REG           0x20
 
 /* Interrupt Status register */
-#define PERF_IRQSTAT_REG                0x10
+#define PERF_IRQSTAT_6338_REG           0x10
+#define PERF_IRQSTAT_6345_REG           0x10
+#define PERF_IRQSTAT_6348_REG           0x10
+#define PERF_IRQSTAT_6358_REG           0x10
+#define PERF_IRQSTAT_6368_REG           0x28
 
 /* External Interrupt Configuration register */
-#define PERF_EXTIRQ_CFG_REG             0x14
+#define PERF_EXTIRQ_CFG_REG_6338        0x14
+#define PERF_EXTIRQ_CFG_REG_6348        0x14
+#define PERF_EXTIRQ_CFG_REG_6358        0x14
+#define PERF_EXTIRQ_CFG_REG_6368        0x18
+
+#define PERF_EXTIRQ_CFG_REG2_6368       0x1c
+
+/* for 6348 only */
+#define EXTIRQ_CFG_SENSE_6348(x)        (1 << (x))
+#define EXTIRQ_CFG_STAT_6348(x)         (1 << (x + 5))
+#define EXTIRQ_CFG_CLEAR_6348(x)        (1 << (x + 10))
+#define EXTIRQ_CFG_MASK_6348(x)         (1 << (x + 15))
+#define EXTIRQ_CFG_BOTHEDGE_6348(x)     (1 << (x + 20))
+#define EXTIRQ_CFG_LEVELSENSE_6348(x)   (1 << (x + 25))
+#define EXTIRQ_CFG_CLEAR_ALL_6348       (0xf << 10)
+#define EXTIRQ_CFG_MASK_ALL_6348        (0xf << 15)
+
+/* for all others */
 #define EXTIRQ_CFG_SENSE(x)             (1 << (x))
-#define EXTIRQ_CFG_STAT(x)              (1 << (x + 5))
-#define EXTIRQ_CFG_CLEAR(x)             (1 << (x + 10))
-#define EXTIRQ_CFG_MASK(x)              (1 << (x + 15))
-#define EXTIRQ_CFG_BOTHEDGE(x)          (1 << (x + 20))
-#define EXTIRQ_CFG_LEVELSENSE(x)        (1 << (x + 25))
-
-#define EXTIRQ_CFG_CLEAR_ALL            (0xf << 10)
-#define EXTIRQ_CFG_MASK_ALL             (0xf << 15)
+#define EXTIRQ_CFG_STAT(x)              (1 << (x + 4))
+#define EXTIRQ_CFG_CLEAR(x)             (1 << (x + 8))
+#define EXTIRQ_CFG_MASK(x)              (1 << (x + 12))
+#define EXTIRQ_CFG_BOTHEDGE(x)          (1 << (x + 16))
+#define EXTIRQ_CFG_LEVELSENSE(x)        (1 << (x + 20))
+#define EXTIRQ_CFG_CLEAR_ALL            (0xf << 8)
+#define EXTIRQ_CFG_MASK_ALL             (0xf << 12)
 
 /* Soft Reset register */
 #define PERF_SOFTRESET_REG              0x28
+#define PERF_SOFTRESET_6368_REG         0x10
 
 #define SOFTRESET_6338_SPI_MASK         (1 << 0)
 #define SOFTRESET_6338_ENET_MASK        (1 << 2)
@@ -147,6 +203,15 @@
                                   SOFTRESET_6348_ACLC_MASK |            \
                                   SOFTRESET_6348_ADSLMIPSPLL_MASK)
 
+#define SOFTRESET_6368_SPI_MASK         (1 << 0)
+#define SOFTRESET_6368_MPI_MASK         (1 << 3)
+#define SOFTRESET_6368_EPHY_MASK        (1 << 6)
+#define SOFTRESET_6368_SAR_MASK         (1 << 7)
+#define SOFTRESET_6368_ENETSW_MASK      (1 << 10)
+#define SOFTRESET_6368_USBS_MASK        (1 << 11)
+#define SOFTRESET_6368_USBH_MASK        (1 << 12)
+#define SOFTRESET_6368_PCM_MASK         (1 << 13)
+
 /* MIPS PLL control register */
 #define PERF_MIPSPLLCTL_REG             0x34
 #define MIPSPLLCTL_N1_SHIFT             20
@@ -372,6 +437,7 @@
 #define GPIO_CTL_LO_REG                 0x4
 #define GPIO_DATA_HI_REG                0x8
 #define GPIO_DATA_LO_REG                0xC
+#define GPIO_DATA_LO_REG_6345           0x8
 
 /* GPIO mux registers and constants */
 #define GPIO_MODE_REG                   0x18
@@ -402,6 +468,44 @@
 #define GPIO_MODE_6358_SERIAL_LED       (1 << 10)
 #define GPIO_MODE_6358_UTOPIA           (1 << 12)
 
+#define GPIO_MODE_6368_ANALOG_AFE_0     (1 << 0)
+#define GPIO_MODE_6368_ANALOG_AFE_1     (1 << 1)
+#define GPIO_MODE_6368_SYS_IRQ          (1 << 2)
+#define GPIO_MODE_6368_SERIAL_LED_DATA  (1 << 3)
+#define GPIO_MODE_6368_SERIAL_LED_CLK   (1 << 4)
+#define GPIO_MODE_6368_INET_LED         (1 << 5)
+#define GPIO_MODE_6368_EPHY0_LED        (1 << 6)
+#define GPIO_MODE_6368_EPHY1_LED        (1 << 7)
+#define GPIO_MODE_6368_EPHY2_LED        (1 << 8)
+#define GPIO_MODE_6368_EPHY3_LED        (1 << 9)
+#define GPIO_MODE_6368_ROBOSW_LED_DAT   (1 << 10)
+#define GPIO_MODE_6368_ROBOSW_LED_CLK   (1 << 11)
+#define GPIO_MODE_6368_ROBOSW_LED0      (1 << 12)
+#define GPIO_MODE_6368_ROBOSW_LED1      (1 << 13)
+#define GPIO_MODE_6368_USBD_LED         (1 << 14)
+#define GPIO_MODE_6368_NTR_PULSE        (1 << 15)
+#define GPIO_MODE_6368_PCI_REQ1         (1 << 16)
+#define GPIO_MODE_6368_PCI_GNT1         (1 << 17)
+#define GPIO_MODE_6368_PCI_INTB         (1 << 18)
+#define GPIO_MODE_6368_PCI_REQ0         (1 << 19)
+#define GPIO_MODE_6368_PCI_GNT0         (1 << 20)
+#define GPIO_MODE_6368_PCMCIA_CD1       (1 << 22)
+#define GPIO_MODE_6368_PCMCIA_CD2       (1 << 23)
+#define GPIO_MODE_6368_PCMCIA_VS1       (1 << 24)
+#define GPIO_MODE_6368_PCMCIA_VS2       (1 << 25)
+#define GPIO_MODE_6368_EBI_CS2          (1 << 26)
+#define GPIO_MODE_6368_EBI_CS3          (1 << 27)
+#define GPIO_MODE_6368_SPI_SSN2         (1 << 28)
+#define GPIO_MODE_6368_SPI_SSN3         (1 << 29)
+#define GPIO_MODE_6368_SPI_SSN4         (1 << 30)
+#define GPIO_MODE_6368_SPI_SSN5         (1 << 31)
+
+
+#define GPIO_BASEMODE_6368_REG          0x38
+#define GPIO_BASEMODE_6368_UART2        0x1
+#define GPIO_BASEMODE_6368_GPIO         0x0
+#define GPIO_BASEMODE_6368_MASK         0x7
+/* those bits must be kept as read in gpio basemode register*/
 
 /*************************************************************************
  * _REG relative to RSET_ENET
@@ -548,6 +652,56 @@
 
 
 /*************************************************************************
+ * _REG relative to RSET_ENETDMAC
+ *************************************************************************/
+
+/* Channel Configuration register */
+#define ENETDMAC_CHANCFG_REG(x)         ((x) * 0x10)
+#define ENETDMAC_CHANCFG_EN_SHIFT       0
+#define ENETDMAC_CHANCFG_EN_MASK        (1 << ENETDMA_CHANCFG_EN_SHIFT)
+#define ENETDMAC_CHANCFG_PKTHALT_SHIFT  1
+#define ENETDMAC_CHANCFG_PKTHALT_MASK   (1 << ENETDMA_CHANCFG_PKTHALT_SHIFT)
+
+/* Interrupt Control/Status register */
+#define ENETDMAC_IR_REG(x)              (0x4 + (x) * 0x10)
+#define ENETDMAC_IR_BUFDONE_MASK        (1 << 0)
+#define ENETDMAC_IR_PKTDONE_MASK        (1 << 1)
+#define ENETDMAC_IR_NOTOWNER_MASK       (1 << 2)
+
+/* Interrupt Mask register */
+#define ENETDMAC_IRMASK_REG(x)          (0x8 + (x) * 0x10)
+
+/* Maximum Burst Length */
+#define ENETDMAC_MAXBURST_REG(x)        (0xc + (x) * 0x10)
+
+
+/*************************************************************************
+ * _REG relative to RSET_ENETDMAS
+ *************************************************************************/
+
+/* Ring Start Address register */
+#define ENETDMAS_RSTART_REG(x)          ((x) * 0x10)
+
+/* State Ram Word 2 */
+#define ENETDMAS_SRAM2_REG(x)           (0x4 + (x) * 0x10)
+
+/* State Ram Word 3 */
+#define ENETDMAS_SRAM3_REG(x)           (0x8 + (x) * 0x10)
+
+/* State Ram Word 4 */
+#define ENETDMAS_SRAM4_REG(x)           (0xc + (x) * 0x10)
+
+
+/*************************************************************************
+ * _REG relative to RSET_ENETSW
+ *************************************************************************/
+
+/* MIB register */
+#define ENETSW_MIB_REG(x)               (0x2800 + (x) * 4)
+#define ENETSW_MIB_REG_COUNT            47
+
+
+/*************************************************************************
  * _REG relative to RSET_OHCI_PRIV
  *************************************************************************/
 
@@ -562,7 +716,9 @@
  * _REG relative to RSET_USBH_PRIV
  *************************************************************************/
 
-#define USBH_PRIV_SWAP_REG              0x0
+#define USBH_PRIV_SWAP_6358_REG         0x0
+#define USBH_PRIV_SWAP_6368_REG         0x1c
+
 #define USBH_PRIV_SWAP_EHCI_ENDN_SHIFT  4
 #define USBH_PRIV_SWAP_EHCI_ENDN_MASK   (1 << USBH_PRIV_SWAP_EHCI_ENDN_SHIFT)
 #define USBH_PRIV_SWAP_EHCI_DATA_SHIFT  3
@@ -572,7 +728,13 @@
 #define USBH_PRIV_SWAP_OHCI_DATA_SHIFT  0
 #define USBH_PRIV_SWAP_OHCI_DATA_MASK   (1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT)
 
-#define USBH_PRIV_TEST_REG              0x24
+#define USBH_PRIV_TEST_6358_REG         0x24
+#define USBH_PRIV_TEST_6368_REG         0x14
+
+#define USBH_PRIV_SETUP_6368_REG        0x28
+#define USBH_PRIV_SETUP_IOC_SHIFT       4
+#define USBH_PRIV_SETUP_IOC_MASK        (1 << USBH_PRIV_SETUP_IOC_SHIFT)
+
 
 
 /*************************************************************************
@@ -734,6 +896,8 @@
 #define SDRAM_CFG_BANK_SHIFT            13
 #define SDRAM_CFG_BANK_MASK             (1 << SDRAM_CFG_BANK_SHIFT)
 
+#define SDRAM_MBASE_REG                 0xc
+
 #define SDRAM_PRIO_REG                  0x2C
 #define SDRAM_PRIO_MIPS_SHIFT           29
 #define SDRAM_PRIO_MIPS_MASK            (1 << SDRAM_PRIO_MIPS_SHIFT)
@@ -768,4 +932,45 @@
 #define DMIPSPLLCFG_N2_SHIFT            29
 #define DMIPSPLLCFG_N2_MASK             (0x7 << DMIPSPLLCFG_N2_SHIFT)
 
+#define DDR_DMIPSPLLCFG_6368_REG        0x20
+#define DMIPSPLLCFG_6368_P1_SHIFT       0
+#define DMIPSPLLCFG_6368_P1_MASK        (0xf << DMIPSPLLCFG_6368_P1_SHIFT)
+#define DMIPSPLLCFG_6368_P2_SHIFT       4
+#define DMIPSPLLCFG_6368_P2_MASK        (0xf << DMIPSPLLCFG_6368_P2_SHIFT)
+#define DMIPSPLLCFG_6368_NDIV_SHIFT     16
+#define DMIPSPLLCFG_6368_NDIV_MASK      (0x1ff << DMIPSPLLCFG_6368_NDIV_SHIFT)
+
+#define DDR_DMIPSPLLDIV_6368_REG        0x24
+#define DMIPSPLLDIV_6368_MDIV_SHIFT     0
+#define DMIPSPLLDIV_6368_MDIV_MASK      (0xff << DMIPSPLLDIV_6368_MDIV_SHIFT)
+
+
+/*************************************************************************
+ * _REG relative to RSET_M2M
+ *************************************************************************/
+
+#define M2M_RX                          0
+#define M2M_TX                          1
+
+#define M2M_SRC_REG(x)                  ((x) * 0x40 + 0x00)
+#define M2M_DST_REG(x)                  ((x) * 0x40 + 0x04)
+#define M2M_SIZE_REG(x)                 ((x) * 0x40 + 0x08)
+
+#define M2M_CTRL_REG(x)                 ((x) * 0x40 + 0x0c)
+#define M2M_CTRL_ENABLE_MASK            (1 << 0)
+#define M2M_CTRL_IRQEN_MASK             (1 << 1)
+#define M2M_CTRL_ERROR_CLR_MASK         (1 << 6)
+#define M2M_CTRL_DONE_CLR_MASK          (1 << 7)
+#define M2M_CTRL_NOINC_MASK             (1 << 8)
+#define M2M_CTRL_PCMCIASWAP_MASK        (1 << 9)
+#define M2M_CTRL_SWAPBYTE_MASK          (1 << 10)
+#define M2M_CTRL_ENDIAN_MASK            (1 << 11)
+
+#define M2M_STAT_REG(x)                 ((x) * 0x40 + 0x10)
+#define M2M_STAT_DONE                   (1 << 0)
+#define M2M_STAT_ERROR                  (1 << 1)
+
+#define M2M_SRCID_REG(x)                ((x) * 0x40 + 0x14)
+#define M2M_DSTID_REG(x)                ((x) * 0x40 + 0x18)
+
 #endif /* BCM63XX_REGS_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/ioremap.h b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
new file mode 100644
index 00000000000..ef94ba73646
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
@@ -0,0 +1,42 @@
+#ifndef BCM63XX_IOREMAP_H_
+#define BCM63XX_IOREMAP_H_
+
+#include <bcm63xx_cpu.h>
+
+static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
+{
+        return phys_addr;
+}
+
+static inline int is_bcm63xx_internal_registers(phys_t offset)
+{
+        switch (bcm63xx_get_cpu_id()) {
+        case BCM6338_CPU_ID:
+        case BCM6345_CPU_ID:
+        case BCM6348_CPU_ID:
+        case BCM6358_CPU_ID:
+                if (offset >= 0xfff00000)
+                        return 1;
+                break;
+        case BCM6368_CPU_ID:
+                if (offset >= 0xb0000000 && offset < 0xb1000000)
+                        return 1;
+                break;
+        }
+        return 0;
+}
+
+static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size,
+                                         unsigned long flags)
+{
+        if (is_bcm63xx_internal_registers(offset))
+                return (void __iomem *)offset;
+        return NULL;
+}
+
+static inline int plat_iounmap(const volatile void __iomem *addr)
+{
+        return is_bcm63xx_internal_registers((unsigned long)addr);
+}
+
+#endif /* BCM63XX_IOREMAP_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/irq.h b/arch/mips/include/asm/mach-bcm63xx/irq.h
new file mode 100644
index 00000000000..9332e788a5c
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/irq.h
@@ -0,0 +1,7 @@
+#ifndef __ASM_MACH_BCM63XX_IRQ_H
+#define __ASM_MACH_BCM63XX_IRQ_H
+
+#define NR_IRQS 128
+#define MIPS_CPU_IRQ_BASE 0
+
+#endif
diff --git a/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h b/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
index 3b728275b9b..d193fb68cf2 100644
--- a/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
@@ -24,24 +24,33 @@
 
 #define cpu_has_llsc            1
 #define cpu_has_vtag_icache     0
-#define cpu_has_dc_aliases      0
-#define cpu_has_ic_fills_f_dc   0
+#define cpu_has_ic_fills_f_dc   1
 #define cpu_has_dsp             0
 #define cpu_has_mipsmt          0
-#define cpu_has_userlocal       0
-#define cpu_icache_snoops_remote_store  0
+#define cpu_icache_snoops_remote_store  1
 
-#define cpu_has_nofpuex         0
 #define cpu_has_64bits          1
 
 #define cpu_has_mips32r1        1
-#define cpu_has_mips32r2        0
 #define cpu_has_mips64r1        1
-#define cpu_has_mips64r2        0
 
 #define cpu_has_inclusive_pcaches       0
 
 #define cpu_dcache_line_size()  32
 #define cpu_icache_line_size()  32
 
+#if defined(CONFIG_CPU_XLR)
+#define cpu_has_userlocal       0
+#define cpu_has_dc_aliases      0
+#define cpu_has_mips32r2        0
+#define cpu_has_mips64r2        0
+#elif defined(CONFIG_CPU_XLP)
+#define cpu_has_userlocal       1
+#define cpu_has_mips32r2        1
+#define cpu_has_mips64r2        1
+#define cpu_has_dc_aliases      1
+#else
+#error "Unknown Netlogic CPU"
+#endif
+
 #endif /* __ASM_MACH_NETLOGIC_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 2ea7b817feb..7f87d824eeb 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -1106,7 +1106,7 @@ do {									\
 #define read_c0_brcm_reset()            __read_32bit_c0_register($22, 5)
 #define write_c0_brcm_reset(val)        __write_32bit_c0_register($22, 5, val)
 
-/* BMIPS4380 */
+/* BMIPS43xx */
 #define read_c0_brcm_cmt_intr()         __read_32bit_c0_register($22, 1)
 #define write_c0_brcm_cmt_intr(val)     __write_32bit_c0_register($22, 1, val)
 
@@ -1667,6 +1667,13 @@ __BUILD_SET_C0(config)
 __BUILD_SET_C0(intcontrol)
 __BUILD_SET_C0(intctl)
 __BUILD_SET_C0(srsmap)
+__BUILD_SET_C0(brcm_config_0)
+__BUILD_SET_C0(brcm_bus_pll)
+__BUILD_SET_C0(brcm_reset)
+__BUILD_SET_C0(brcm_cmt_intr)
+__BUILD_SET_C0(brcm_cmt_ctrl)
+__BUILD_SET_C0(brcm_config)
+__BUILD_SET_C0(brcm_mode)
 
 #endif /* !__ASSEMBLY__ */
 
diff --git a/arch/mips/include/asm/module.h b/arch/mips/include/asm/module.h
index bc01a02cacd..7467d1d933d 100644
--- a/arch/mips/include/asm/module.h
+++ b/arch/mips/include/asm/module.h
@@ -74,7 +74,9 @@ search_module_dbetables(unsigned long addr)
 }
 #endif
 
-#ifdef CONFIG_CPU_MIPS32_R1
+#ifdef CONFIG_CPU_BMIPS
+#define MODULE_PROC_FAMILY "BMIPS "
+#elif defined CONFIG_CPU_MIPS32_R1
 #define MODULE_PROC_FAMILY "MIPS32_R1 "
 #elif defined CONFIG_CPU_MIPS32_R2
 #define MODULE_PROC_FAMILY "MIPS32_R2 "
@@ -120,6 +122,8 @@ search_module_dbetables(unsigned long addr)
 #define MODULE_PROC_FAMILY "OCTEON "
 #elif defined CONFIG_CPU_XLR
 #define MODULE_PROC_FAMILY "XLR "
+#elif defined CONFIG_CPU_XLP
+#define MODULE_PROC_FAMILY "XLP "
 #else
 #error MODULE_PROC_FAMILY undefined for your processor configuration
 #endif
diff --git a/arch/mips/include/asm/netlogic/common.h b/arch/mips/include/asm/netlogic/common.h
new file mode 100644
index 00000000000..fdd2f44c7b5
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/common.h
@@ -0,0 +1,76 @@
+/*
+ * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
+ * reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the NetLogic
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _NETLOGIC_COMMON_H_
+#define _NETLOGIC_COMMON_H_
+
+/*
+ * Common SMP definitions
+ */
+#define RESET_VEC_PHYS          0x1fc00000
+#define RESET_DATA_PHYS         (RESET_VEC_PHYS + (1<<10))
+#define BOOT_THREAD_MODE        0
+#define BOOT_NMI_LOCK           4
+#define BOOT_NMI_HANDLER        8
+
+#ifndef __ASSEMBLY__
+struct irq_desc;
+extern struct plat_smp_ops nlm_smp_ops;
+extern char nlm_reset_entry[], nlm_reset_entry_end[];
+void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc);
+void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc);
+void nlm_smp_irq_init(void);
+void nlm_boot_secondary_cpus(void);
+int nlm_wakeup_secondary_cpus(u32 wakeup_mask);
+void nlm_rmiboot_preboot(void);
+
+static inline void
+nlm_set_nmi_handler(void *handler)
+{
+        char *reset_data;
+
+        reset_data = (char *)CKSEG1ADDR(RESET_DATA_PHYS);
+        *(int64_t *)(reset_data + BOOT_NMI_HANDLER) = (long)handler;
+}
+
+/*
+ * Misc.
+ */
+unsigned int nlm_get_cpu_frequency(void);
+
+extern unsigned long nlm_common_ebase;
+extern int nlm_threads_per_core;
+extern uint32_t nlm_cpumask, nlm_coremask;
+#endif
+#endif /* _NETLOGIC_COMMON_H_ */
diff --git a/arch/mips/include/asm/netlogic/haldefs.h b/arch/mips/include/asm/netlogic/haldefs.h
new file mode 100644
index 00000000000..72a0c788b47
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/haldefs.h
@@ -0,0 +1,163 @@
+/*
+ * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
+ * reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the NetLogic
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __NLM_HAL_HALDEFS_H__
+#define __NLM_HAL_HALDEFS_H__
+
+/*
+ * This file contains platform specific memory mapped IO implementation
+ * and will provide a way to read 32/64 bit memory mapped registers in
+ * all ABIs
+ */
+#if !defined(CONFIG_64BIT) && defined(CONFIG_CPU_XLP)
+#error "o32 compile not supported on XLP yet"
+#endif
+/*
+ * For o32 compilation, we have to disable interrupts and enable KX bit to
+ * access 64 bit addresses or data.
+ *
+ * We need to disable interrupts because we save just the lower 32 bits of
+ * registers in  interrupt handling. So if we get hit by an interrupt while
+ * using the upper 32 bits of a register, we lose.
+ */
+static inline uint32_t nlm_save_flags_kx(void)
+{
+        return change_c0_status(ST0_KX | ST0_IE, ST0_KX);
+}
+
+static inline uint32_t nlm_save_flags_cop2(void)
+{
+        return change_c0_status(ST0_CU2 | ST0_IE, ST0_CU2);
+}
+
+static inline void nlm_restore_flags(uint32_t sr)
+{
+        write_c0_status(sr);
+}
+
+/*
+ * The n64 implementations are simple, the o32 implementations when they
+ * are added, will have to disable interrupts and enable KX before doing
+ * 64 bit ops.
+ */
+static inline uint32_t
+nlm_read_reg(uint64_t base, uint32_t reg)
+{
+        volatile uint32_t *addr = (volatile uint32_t *)(long)base + reg;
+
+        return *addr;
+}
+
+static inline void
+nlm_write_reg(uint64_t base, uint32_t reg, uint32_t val)
+{
+        volatile uint32_t *addr = (volatile uint32_t *)(long)base + reg;
+
+        *addr = val;
+}
+
+static inline uint64_t
+nlm_read_reg64(uint64_t base, uint32_t reg)
+{
+        uint64_t addr = base + (reg >> 1) * sizeof(uint64_t);
+        volatile uint64_t *ptr = (volatile uint64_t *)(long)addr;
+
+        return *ptr;
+}
+
+static inline void
+nlm_write_reg64(uint64_t base, uint32_t reg, uint64_t val)
+{
+        uint64_t addr = base + (reg >> 1) * sizeof(uint64_t);
+        volatile uint64_t *ptr = (volatile uint64_t *)(long)addr;
+
+        *ptr = val;
+}
+
+/*
+ * Routines to store 32/64 bit values to 64 bit addresses,
+ * used when going thru XKPHYS to access registers
+ */
+static inline uint32_t
+nlm_read_reg_xkphys(uint64_t base, uint32_t reg)
+{
+        return nlm_read_reg(base, reg);
+}
+
+static inline void
+nlm_write_reg_xkphys(uint64_t base, uint32_t reg, uint32_t val)
+{
+        nlm_write_reg(base, reg, val);
+}
+
+static inline uint64_t
+nlm_read_reg64_xkphys(uint64_t base, uint32_t reg)
+{
+        return nlm_read_reg64(base, reg);
+}
+
+static inline void
+nlm_write_reg64_xkphys(uint64_t base, uint32_t reg, uint64_t val)
+{
+        nlm_write_reg64(base, reg, val);
+}
+
+/* Location where IO base is mapped */
+extern uint64_t nlm_io_base;
+
+#if defined(CONFIG_CPU_XLP)
+static inline uint64_t
+nlm_pcicfg_base(uint32_t devoffset)
+{
+        return nlm_io_base + devoffset;
+}
+
+static inline uint64_t
+nlm_xkphys_map_pcibar0(uint64_t pcibase)
+{
+        uint64_t paddr;
+
+        paddr = nlm_read_reg(pcibase, 0x4) & ~0xfu;
+        return (uint64_t)0x9000000000000000 | paddr;
+}
+#elif defined(CONFIG_CPU_XLR)
+
+static inline uint64_t
+nlm_mmio_base(uint32_t devoffset)
+{
+        return nlm_io_base + devoffset;
+}
+#endif
+
+#endif
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/bridge.h b/arch/mips/include/asm/netlogic/xlp-hal/bridge.h
new file mode 100644
index 00000000000..ca95133f1ad
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlp-hal/bridge.h
@@ -0,0 +1,187 @@
+/*
+ * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
+ * reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the NetLogic
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __NLM_HAL_BRIDGE_H__
+#define __NLM_HAL_BRIDGE_H__
+
+/**
+* @file_name mio.h
+* @author Netlogic Microsystems
+* @brief Basic definitions of XLP memory and io subsystem
+*/
+
+/*
+ * BRIDGE specific registers
+ *
+ * These registers start after the PCIe header, which has 0x40
+ * standard entries
+ */
+#define BRIDGE_MODE                     0x00
+#define BRIDGE_PCI_CFG_BASE             0x01
+#define BRIDGE_PCI_CFG_LIMIT            0x02
+#define BRIDGE_PCIE_CFG_BASE            0x03
+#define BRIDGE_PCIE_CFG_LIMIT           0x04
+#define BRIDGE_BUSNUM_BAR0              0x05
+#define BRIDGE_BUSNUM_BAR1              0x06
+#define BRIDGE_BUSNUM_BAR2              0x07
+#define BRIDGE_BUSNUM_BAR3              0x08
+#define BRIDGE_BUSNUM_BAR4              0x09
+#define BRIDGE_BUSNUM_BAR5              0x0a
+#define BRIDGE_BUSNUM_BAR6              0x0b
+#define BRIDGE_FLASH_BAR0               0x0c
+#define BRIDGE_FLASH_BAR1               0x0d
+#define BRIDGE_FLASH_BAR2               0x0e
+#define BRIDGE_FLASH_BAR3               0x0f
+#define BRIDGE_FLASH_LIMIT0             0x10
+#define BRIDGE_FLASH_LIMIT1             0x11
+#define BRIDGE_FLASH_LIMIT2             0x12
+#define BRIDGE_FLASH_LIMIT3             0x13
+
+#define BRIDGE_DRAM_BAR(i)              (0x14 + (i))
+#define BRIDGE_DRAM_BAR0                0x14
+#define BRIDGE_DRAM_BAR1                0x15
+#define BRIDGE_DRAM_BAR2                0x16
+#define BRIDGE_DRAM_BAR3                0x17
+#define BRIDGE_DRAM_BAR4                0x18
+#define BRIDGE_DRAM_BAR5                0x19
+#define BRIDGE_DRAM_BAR6                0x1a
+#define BRIDGE_DRAM_BAR7                0x1b
+
+#define BRIDGE_DRAM_LIMIT(i)            (0x1c + (i))
+#define BRIDGE_DRAM_LIMIT0              0x1c
+#define BRIDGE_DRAM_LIMIT1              0x1d
+#define BRIDGE_DRAM_LIMIT2              0x1e
+#define BRIDGE_DRAM_LIMIT3              0x1f
+#define BRIDGE_DRAM_LIMIT4              0x20
+#define BRIDGE_DRAM_LIMIT5              0x21
+#define BRIDGE_DRAM_LIMIT6              0x22
+#define BRIDGE_DRAM_LIMIT7              0x23
+
+#define BRIDGE_DRAM_NODE_TRANSLN0       0x24
+#define BRIDGE_DRAM_NODE_TRANSLN1       0x25
+#define BRIDGE_DRAM_NODE_TRANSLN2       0x26
+#define BRIDGE_DRAM_NODE_TRANSLN3       0x27
+#define BRIDGE_DRAM_NODE_TRANSLN4       0x28
+#define BRIDGE_DRAM_NODE_TRANSLN5       0x29
+#define BRIDGE_DRAM_NODE_TRANSLN6       0x2a
+#define BRIDGE_DRAM_NODE_TRANSLN7       0x2b
+#define BRIDGE_DRAM_CHNL_TRANSLN0       0x2c
+#define BRIDGE_DRAM_CHNL_TRANSLN1       0x2d
+#define BRIDGE_DRAM_CHNL_TRANSLN2       0x2e
+#define BRIDGE_DRAM_CHNL_TRANSLN3       0x2f
+#define BRIDGE_DRAM_CHNL_TRANSLN4       0x30
+#define BRIDGE_DRAM_CHNL_TRANSLN5       0x31
+#define BRIDGE_DRAM_CHNL_TRANSLN6       0x32
+#define BRIDGE_DRAM_CHNL_TRANSLN7       0x33
+#define BRIDGE_PCIEMEM_BASE0            0x34
+#define BRIDGE_PCIEMEM_BASE1            0x35
+#define BRIDGE_PCIEMEM_BASE2            0x36
+#define BRIDGE_PCIEMEM_BASE3            0x37
+#define BRIDGE_PCIEMEM_LIMIT0           0x38
+#define BRIDGE_PCIEMEM_LIMIT1           0x39
+#define BRIDGE_PCIEMEM_LIMIT2           0x3a
+#define BRIDGE_PCIEMEM_LIMIT3           0x3b
+#define BRIDGE_PCIEIO_BASE0             0x3c
+#define BRIDGE_PCIEIO_BASE1             0x3d
+#define BRIDGE_PCIEIO_BASE2             0x3e
+#define BRIDGE_PCIEIO_BASE3             0x3f
+#define BRIDGE_PCIEIO_LIMIT0            0x40
+#define BRIDGE_PCIEIO_LIMIT1            0x41
+#define BRIDGE_PCIEIO_LIMIT2            0x42
+#define BRIDGE_PCIEIO_LIMIT3            0x43
+#define BRIDGE_PCIEMEM_BASE4            0x44
+#define BRIDGE_PCIEMEM_BASE5            0x45
+#define BRIDGE_PCIEMEM_BASE6            0x46
+#define BRIDGE_PCIEMEM_LIMIT4           0x47
+#define BRIDGE_PCIEMEM_LIMIT5           0x48
+#define BRIDGE_PCIEMEM_LIMIT6           0x49
+#define BRIDGE_PCIEIO_BASE4             0x4a
+#define BRIDGE_PCIEIO_BASE5             0x4b
+#define BRIDGE_PCIEIO_BASE6             0x4c
+#define BRIDGE_PCIEIO_LIMIT4            0x4d
+#define BRIDGE_PCIEIO_LIMIT5            0x4e
+#define BRIDGE_PCIEIO_LIMIT6            0x4f
+#define BRIDGE_NBU_EVENT_CNT_CTL        0x50
+#define BRIDGE_EVNTCTR1_LOW             0x51
+#define BRIDGE_EVNTCTR1_HI              0x52
+#define BRIDGE_EVNT_CNT_CTL2            0x53
+#define BRIDGE_EVNTCTR2_LOW             0x54
+#define BRIDGE_EVNTCTR2_HI              0x55
+#define BRIDGE_TRACEBUF_MATCH0          0x56
+#define BRIDGE_TRACEBUF_MATCH1          0x57
+#define BRIDGE_TRACEBUF_MATCH_LOW       0x58
+#define BRIDGE_TRACEBUF_MATCH_HI        0x59
+#define BRIDGE_TRACEBUF_CTRL            0x5a
+#define BRIDGE_TRACEBUF_INIT            0x5b
+#define BRIDGE_TRACEBUF_ACCESS          0x5c
+#define BRIDGE_TRACEBUF_READ_DATA0      0x5d
+#define BRIDGE_TRACEBUF_READ_DATA1      0x5d
+#define BRIDGE_TRACEBUF_READ_DATA2      0x5f
+#define BRIDGE_TRACEBUF_READ_DATA3      0x60
+#define BRIDGE_TRACEBUF_STATUS          0x61
+#define BRIDGE_ADDRESS_ERROR0           0x62
+#define BRIDGE_ADDRESS_ERROR1           0x63
+#define BRIDGE_ADDRESS_ERROR2           0x64
+#define BRIDGE_TAG_ECC_ADDR_ERROR0      0x65
+#define BRIDGE_TAG_ECC_ADDR_ERROR1      0x66
+#define BRIDGE_TAG_ECC_ADDR_ERROR2      0x67
+#define BRIDGE_LINE_FLUSH0              0x68
+#define BRIDGE_LINE_FLUSH1              0x69
+#define BRIDGE_NODE_ID                  0x6a
+#define BRIDGE_ERROR_INTERRUPT_EN       0x6b
+#define BRIDGE_PCIE0_WEIGHT             0x2c0
+#define BRIDGE_PCIE1_WEIGHT             0x2c1
+#define BRIDGE_PCIE2_WEIGHT             0x2c2
+#define BRIDGE_PCIE3_WEIGHT             0x2c3
+#define BRIDGE_USB_WEIGHT               0x2c4
+#define BRIDGE_NET_WEIGHT               0x2c5
+#define BRIDGE_POE_WEIGHT               0x2c6
+#define BRIDGE_CMS_WEIGHT               0x2c7
+#define BRIDGE_DMAENG_WEIGHT            0x2c8
+#define BRIDGE_SEC_WEIGHT               0x2c9
+#define BRIDGE_COMP_WEIGHT              0x2ca
+#define BRIDGE_GIO_WEIGHT               0x2cb
+#define BRIDGE_FLASH_WEIGHT             0x2cc
+
+#ifndef __ASSEMBLY__
+
+#define nlm_read_bridge_reg(b, r)       nlm_read_reg(b, r)
+#define nlm_write_bridge_reg(b, r, v)   nlm_write_reg(b, r, v)
+#define nlm_get_bridge_pcibase(node)    \
+                        nlm_pcicfg_base(XLP_IO_BRIDGE_OFFSET(node))
+#define nlm_get_bridge_regbase(node)    \
+                        (nlm_get_bridge_pcibase(node) + XLP_IO_PCI_HDRSZ)
+
+#endif /* __ASSEMBLY__ */
+#endif /* __NLM_HAL_BRIDGE_H__ */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h b/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h
new file mode 100644
index 00000000000..bf7d41deb9b
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
+ * reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the NetLogic
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __NLM_HAL_CPUCONTROL_H__
+#define __NLM_HAL_CPUCONTROL_H__
+
+#define CPU_BLOCKID_IFU         0
+#define CPU_BLOCKID_ICU         1
+#define CPU_BLOCKID_IEU         2
+#define CPU_BLOCKID_LSU         3
+#define CPU_BLOCKID_MMU         4
+#define CPU_BLOCKID_PRF         5
+#define CPU_BLOCKID_SCH         7
+#define CPU_BLOCKID_SCU         8
+#define CPU_BLOCKID_FPU         9
+#define CPU_BLOCKID_MAP         10
+
+#define LSU_DEFEATURE           0x304
+#define LSU_CERRLOG_REGID       0x09
+#define SCHED_DEFEATURE         0x700
+
+/* Offsets of interest from the 'MAP' Block */
+#define MAP_THREADMODE                  0x00
+#define MAP_EXT_EBASE_ENABLE            0x04
+#define MAP_CCDI_CONFIG                 0x08
+#define MAP_THRD0_CCDI_STATUS           0x0c
+#define MAP_THRD1_CCDI_STATUS           0x10
+#define MAP_THRD2_CCDI_STATUS           0x14
+#define MAP_THRD3_CCDI_STATUS           0x18
+#define MAP_THRD0_DEBUG_MODE            0x1c
+#define MAP_THRD1_DEBUG_MODE            0x20
+#define MAP_THRD2_DEBUG_MODE            0x24
+#define MAP_THRD3_DEBUG_MODE            0x28
+#define MAP_MISC_STATE                  0x60
+#define MAP_DEBUG_READ_CTL              0x64
+#define MAP_DEBUG_READ_REG0             0x68
+#define MAP_DEBUG_READ_REG1             0x6c
+
+#define MMU_SETUP               0x400
+#define MMU_LFSRSEED            0x401
+#define MMU_HPW_NUM_PAGE_LVL    0x410
+#define MMU_PGWKR_PGDBASE       0x411
+#define MMU_PGWKR_PGDSHFT       0x412
+#define MMU_PGWKR_PGDMASK       0x413
+#define MMU_PGWKR_PUDSHFT       0x414
+#define MMU_PGWKR_PUDMASK       0x415
+#define MMU_PGWKR_PMDSHFT       0x416
+#define MMU_PGWKR_PMDMASK       0x417
+#define MMU_PGWKR_PTESHFT       0x418
+#define MMU_PGWKR_PTEMASK       0x419
+
+#endif /* __NLM_CPUCONTROL_H__ */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/iomap.h b/arch/mips/include/asm/netlogic/xlp-hal/iomap.h
new file mode 100644
index 00000000000..86cc3391e50
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlp-hal/iomap.h
@@ -0,0 +1,153 @@
+/*
+ * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
+ * reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the NetLogic
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __NLM_HAL_IOMAP_H__
+#define __NLM_HAL_IOMAP_H__
+
+#define XLP_DEFAULT_IO_BASE             0x18000000
+#define NMI_BASE                        0xbfc00000
+#define XLP_IO_CLK                      133333333
+
+#define XLP_PCIE_CFG_SIZE               0x1000          /* 4K */
+#define XLP_PCIE_DEV_BLK_SIZE           (8 * XLP_PCIE_CFG_SIZE)
+#define XLP_PCIE_BUS_BLK_SIZE           (256 * XLP_PCIE_DEV_BLK_SIZE)
+#define XLP_IO_SIZE                     (64 << 20)      /* ECFG space size */
+#define XLP_IO_PCI_HDRSZ                0x100
+#define XLP_IO_DEV(node, dev)           ((dev) + (node) * 8)
+#define XLP_HDR_OFFSET(node, bus, dev, fn)      (((bus) << 20) | \
+                                ((XLP_IO_DEV(node, dev)) << 15) | ((fn) << 12))
+
+#define XLP_IO_BRIDGE_OFFSET(node)      XLP_HDR_OFFSET(node, 0, 0, 0)
+/* coherent inter chip */
+#define XLP_IO_CIC0_OFFSET(node)        XLP_HDR_OFFSET(node, 0, 0, 1)
+#define XLP_IO_CIC1_OFFSET(node)        XLP_HDR_OFFSET(node, 0, 0, 2)
+#define XLP_IO_CIC2_OFFSET(node)        XLP_HDR_OFFSET(node, 0, 0, 3)
+#define XLP_IO_PIC_OFFSET(node)         XLP_HDR_OFFSET(node, 0, 0, 4)
+
+#define XLP_IO_PCIE_OFFSET(node, i)     XLP_HDR_OFFSET(node, 0, 1, i)
+#define XLP_IO_PCIE0_OFFSET(node)       XLP_HDR_OFFSET(node, 0, 1, 0)
+#define XLP_IO_PCIE1_OFFSET(node)       XLP_HDR_OFFSET(node, 0, 1, 1)
+#define XLP_IO_PCIE2_OFFSET(node)       XLP_HDR_OFFSET(node, 0, 1, 2)
+#define XLP_IO_PCIE3_OFFSET(node)       XLP_HDR_OFFSET(node, 0, 1, 3)
+
+#define XLP_IO_USB_OFFSET(node, i)      XLP_HDR_OFFSET(node, 0, 2, i)
+#define XLP_IO_USB_EHCI0_OFFSET(node)   XLP_HDR_OFFSET(node, 0, 2, 0)
+#define XLP_IO_USB_OHCI0_OFFSET(node)   XLP_HDR_OFFSET(node, 0, 2, 1)
+#define XLP_IO_USB_OHCI1_OFFSET(node)   XLP_HDR_OFFSET(node, 0, 2, 2)
+#define XLP_IO_USB_EHCI1_OFFSET(node)   XLP_HDR_OFFSET(node, 0, 2, 3)
+#define XLP_IO_USB_OHCI2_OFFSET(node)   XLP_HDR_OFFSET(node, 0, 2, 4)
+#define XLP_IO_USB_OHCI3_OFFSET(node)   XLP_HDR_OFFSET(node, 0, 2, 5)
+
+#define XLP_IO_NAE_OFFSET(node)         XLP_HDR_OFFSET(node, 0, 3, 0)
+#define XLP_IO_POE_OFFSET(node)         XLP_HDR_OFFSET(node, 0, 3, 1)
+
+#define XLP_IO_CMS_OFFSET(node)         XLP_HDR_OFFSET(node, 0, 4, 0)
+
+#define XLP_IO_DMA_OFFSET(node)         XLP_HDR_OFFSET(node, 0, 5, 1)
+#define XLP_IO_SEC_OFFSET(node)         XLP_HDR_OFFSET(node, 0, 5, 2)
+#define XLP_IO_CMP_OFFSET(node)         XLP_HDR_OFFSET(node, 0, 5, 3)
+
+#define XLP_IO_UART_OFFSET(node, i)     XLP_HDR_OFFSET(node, 0, 6, i)
+#define XLP_IO_UART0_OFFSET(node)       XLP_HDR_OFFSET(node, 0, 6, 0)
+#define XLP_IO_UART1_OFFSET(node)       XLP_HDR_OFFSET(node, 0, 6, 1)
+#define XLP_IO_I2C_OFFSET(node, i)      XLP_HDR_OFFSET(node, 0, 6, 2 + i)
+#define XLP_IO_I2C0_OFFSET(node)        XLP_HDR_OFFSET(node, 0, 6, 2)
+#define XLP_IO_I2C1_OFFSET(node)        XLP_HDR_OFFSET(node, 0, 6, 3)
+#define XLP_IO_GPIO_OFFSET(node)        XLP_HDR_OFFSET(node, 0, 6, 4)
+/* system management */
+#define XLP_IO_SYS_OFFSET(node)         XLP_HDR_OFFSET(node, 0, 6, 5)
+#define XLP_IO_JTAG_OFFSET(node)        XLP_HDR_OFFSET(node, 0, 6, 6)
+
+#define XLP_IO_NOR_OFFSET(node)         XLP_HDR_OFFSET(node, 0, 7, 0)
+#define XLP_IO_NAND_OFFSET(node)        XLP_HDR_OFFSET(node, 0, 7, 1)
+#define XLP_IO_SPI_OFFSET(node)         XLP_HDR_OFFSET(node, 0, 7, 2)
+/* SD flash */
+#define XLP_IO_SD_OFFSET(node)          XLP_HDR_OFFSET(node, 0, 7, 3)
+#define XLP_IO_MMC_OFFSET(node, slot)   \
+                ((XLP_IO_SD_OFFSET(node))+(slot*0x100)+XLP_IO_PCI_HDRSZ)
+
+/* PCI config header register id's */
+#define XLP_PCI_CFGREG0                 0x00
+#define XLP_PCI_CFGREG1                 0x01
+#define XLP_PCI_CFGREG2                 0x02
+#define XLP_PCI_CFGREG3                 0x03
+#define XLP_PCI_CFGREG4                 0x04
+#define XLP_PCI_CFGREG5                 0x05
+#define XLP_PCI_DEVINFO_REG0            0x30
+#define XLP_PCI_DEVINFO_REG1            0x31
+#define XLP_PCI_DEVINFO_REG2            0x32
+#define XLP_PCI_DEVINFO_REG3            0x33
+#define XLP_PCI_DEVINFO_REG4            0x34
+#define XLP_PCI_DEVINFO_REG5            0x35
+#define XLP_PCI_DEVINFO_REG6            0x36
+#define XLP_PCI_DEVINFO_REG7            0x37
+#define XLP_PCI_DEVSCRATCH_REG0         0x38
+#define XLP_PCI_DEVSCRATCH_REG1         0x39
+#define XLP_PCI_DEVSCRATCH_REG2         0x3a
+#define XLP_PCI_DEVSCRATCH_REG3         0x3b
+#define XLP_PCI_MSGSTN_REG              0x3c
+#define XLP_PCI_IRTINFO_REG             0x3d
+#define XLP_PCI_UCODEINFO_REG           0x3e
+#define XLP_PCI_SBB_WT_REG              0x3f
+
+/* PCI IDs for SoC device */
+#define PCI_VENDOR_NETLOGIC             0x184e
+
+#define PCI_DEVICE_ID_NLM_ROOT          0x1001
+#define PCI_DEVICE_ID_NLM_ICI           0x1002
+#define PCI_DEVICE_ID_NLM_PIC           0x1003
+#define PCI_DEVICE_ID_NLM_PCIE          0x1004
+#define PCI_DEVICE_ID_NLM_EHCI          0x1007
+#define PCI_DEVICE_ID_NLM_ILK           0x1008
+#define PCI_DEVICE_ID_NLM_NAE           0x1009
+#define PCI_DEVICE_ID_NLM_POE           0x100A
+#define PCI_DEVICE_ID_NLM_FMN           0x100B
+#define PCI_DEVICE_ID_NLM_RAID          0x100D
+#define PCI_DEVICE_ID_NLM_SAE           0x100D
+#define PCI_DEVICE_ID_NLM_RSA           0x100E
+#define PCI_DEVICE_ID_NLM_CMP           0x100F
+#define PCI_DEVICE_ID_NLM_UART          0x1010
+#define PCI_DEVICE_ID_NLM_I2C           0x1011
+#define PCI_DEVICE_ID_NLM_NOR           0x1015
+#define PCI_DEVICE_ID_NLM_NAND          0x1016
+#define PCI_DEVICE_ID_NLM_MMC           0x1018
+
+#ifndef __ASSEMBLY__
+
+#define nlm_read_pci_reg(b, r)          nlm_read_reg(b, r)
+#define nlm_write_pci_reg(b, r, v)      nlm_write_reg(b, r, v)
+
+#endif /* !__ASSEMBLY */
+
+#endif /* __NLM_HAL_IOMAP_H__ */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/pic.h b/arch/mips/include/asm/netlogic/xlp-hal/pic.h
new file mode 100644
index 00000000000..b6628f7ccf7
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlp-hal/pic.h
@@ -0,0 +1,411 @@
+/*
+ * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
+ * reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the NetLogic
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _NLM_HAL_PIC_H
+#define _NLM_HAL_PIC_H
+
+/* PIC Specific registers */
+#define PIC_CTRL                0x00
+
+/* PIC control register defines */
+#define PIC_CTRL_ITV            32 /* interrupt timeout value */
+#define PIC_CTRL_ICI            19 /* ICI interrupt timeout enable */
+#define PIC_CTRL_ITE            18 /* interrupt timeout enable */
+#define PIC_CTRL_STE            10 /* system timer interrupt enable */
+#define PIC_CTRL_WWR1           8  /* watchdog 1 wraparound count for reset */
+#define PIC_CTRL_WWR0           6  /* watchdog 0 wraparound count for reset */
+#define PIC_CTRL_WWN1           4  /* watchdog 1 wraparound count for NMI */
+#define PIC_CTRL_WWN0           2  /* watchdog 0 wraparound count for NMI */
+#define PIC_CTRL_WTE            0  /* watchdog timer enable */
+
+/* PIC Status register defines */
+#define PIC_ICI_STATUS          33 /* ICI interrupt timeout status */
+#define PIC_ITE_STATUS          32 /* interrupt timeout status */
+#define PIC_STS_STATUS          4  /* System timer interrupt status */
+#define PIC_WNS_STATUS          2  /* NMI status for watchdog timers */
+#define PIC_WIS_STATUS          0  /* Interrupt status for watchdog timers */
+
+/* PIC IPI control register offsets */
+#define PIC_IPICTRL_NMI         32
+#define PIC_IPICTRL_RIV         20 /* received interrupt vector */
+#define PIC_IPICTRL_IDB         16 /* interrupt destination base */
+#define PIC_IPICTRL_DTE          0 /* interrupt destination thread enables */
+
+/* PIC IRT register offsets */
+#define PIC_IRT_ENABLE          31
+#define PIC_IRT_NMI             29
+#define PIC_IRT_SCH             28 /* Scheduling scheme */
+#define PIC_IRT_RVEC            20 /* Interrupt receive vectors */
+#define PIC_IRT_DT              19 /* Destination type */
+#define PIC_IRT_DB              16 /* Destination base */
+#define PIC_IRT_DTE             0  /* Destination thread enables */
+
+#define PIC_BYTESWAP            0x02
+#define PIC_STATUS              0x04
+#define PIC_INTR_TIMEOUT        0x06
+#define PIC_ICI0_INTR_TIMEOUT   0x08
+#define PIC_ICI1_INTR_TIMEOUT   0x0a
+#define PIC_ICI2_INTR_TIMEOUT   0x0c
+#define PIC_IPI_CTL             0x0e
+#define PIC_INT_ACK             0x10
+#define PIC_INT_PENDING0        0x12
+#define PIC_INT_PENDING1        0x14
+#define PIC_INT_PENDING2        0x16
+
+#define PIC_WDOG0_MAXVAL        0x18
+#define PIC_WDOG0_COUNT         0x1a
+#define PIC_WDOG0_ENABLE0       0x1c
+#define PIC_WDOG0_ENABLE1       0x1e
+#define PIC_WDOG0_BEATCMD       0x20
+#define PIC_WDOG0_BEAT0         0x22
+#define PIC_WDOG0_BEAT1         0x24
+
+#define PIC_WDOG1_MAXVAL        0x26
+#define PIC_WDOG1_COUNT         0x28
+#define PIC_WDOG1_ENABLE0       0x2a
+#define PIC_WDOG1_ENABLE1       0x2c
+#define PIC_WDOG1_BEATCMD       0x2e
+#define PIC_WDOG1_BEAT0         0x30
+#define PIC_WDOG1_BEAT1         0x32
+
+#define PIC_WDOG_MAXVAL(i)      (PIC_WDOG0_MAXVAL + ((i) ? 7 : 0))
+#define PIC_WDOG_COUNT(i)       (PIC_WDOG0_COUNT + ((i) ? 7 : 0))
+#define PIC_WDOG_ENABLE0(i)     (PIC_WDOG0_ENABLE0 + ((i) ? 7 : 0))
+#define PIC_WDOG_ENABLE1(i)     (PIC_WDOG0_ENABLE1 + ((i) ? 7 : 0))
+#define PIC_WDOG_BEATCMD(i)     (PIC_WDOG0_BEATCMD + ((i) ? 7 : 0))
+#define PIC_WDOG_BEAT0(i)       (PIC_WDOG0_BEAT0 + ((i) ? 7 : 0))
+#define PIC_WDOG_BEAT1(i)       (PIC_WDOG0_BEAT1 + ((i) ? 7 : 0))
+
+#define PIC_TIMER0_MAXVAL    0x34
+#define PIC_TIMER1_MAXVAL    0x36
+#define PIC_TIMER2_MAXVAL    0x38
+#define PIC_TIMER3_MAXVAL    0x3a
+#define PIC_TIMER4_MAXVAL    0x3c
+#define PIC_TIMER5_MAXVAL    0x3e
+#define PIC_TIMER6_MAXVAL    0x40
+#define PIC_TIMER7_MAXVAL    0x42
+#define PIC_TIMER_MAXVAL(i)  (PIC_TIMER0_MAXVAL + ((i) * 2))
+
+#define PIC_TIMER0_COUNT     0x44
+#define PIC_TIMER1_COUNT     0x46
+#define PIC_TIMER2_COUNT     0x48
+#define PIC_TIMER3_COUNT     0x4a
+#define PIC_TIMER4_COUNT     0x4c
+#define PIC_TIMER5_COUNT     0x4e
+#define PIC_TIMER6_COUNT     0x50
+#define PIC_TIMER7_COUNT     0x52
+#define PIC_TIMER_COUNT(i)   (PIC_TIMER0_COUNT + ((i) * 2))
+
+#define PIC_ITE0_N0_N1          0x54
+#define PIC_ITE1_N0_N1          0x58
+#define PIC_ITE2_N0_N1          0x5c
+#define PIC_ITE3_N0_N1          0x60
+#define PIC_ITE4_N0_N1          0x64
+#define PIC_ITE5_N0_N1          0x68
+#define PIC_ITE6_N0_N1          0x6c
+#define PIC_ITE7_N0_N1          0x70
+#define PIC_ITE_N0_N1(i)        (PIC_ITE0_N0_N1 + ((i) * 4))
+
+#define PIC_ITE0_N2_N3          0x56
+#define PIC_ITE1_N2_N3          0x5a
+#define PIC_ITE2_N2_N3          0x5e
+#define PIC_ITE3_N2_N3          0x62
+#define PIC_ITE4_N2_N3          0x66
+#define PIC_ITE5_N2_N3          0x6a
+#define PIC_ITE6_N2_N3          0x6e
+#define PIC_ITE7_N2_N3          0x72
+#define PIC_ITE_N2_N3(i)        (PIC_ITE0_N2_N3 + ((i) * 4))
+
+#define PIC_IRT0                0x74
+#define PIC_IRT(i)              (PIC_IRT0 + ((i) * 2))
+
+#define TIMER_CYCLES_MAXVAL     0xffffffffffffffffULL
+
+/*
+ *    IRT Map
+ */
+#define PIC_NUM_IRTS            160
+
+#define PIC_IRT_WD_0_INDEX      0
+#define PIC_IRT_WD_1_INDEX      1
+#define PIC_IRT_WD_NMI_0_INDEX  2
+#define PIC_IRT_WD_NMI_1_INDEX  3
+#define PIC_IRT_TIMER_0_INDEX   4
+#define PIC_IRT_TIMER_1_INDEX   5
+#define PIC_IRT_TIMER_2_INDEX   6
+#define PIC_IRT_TIMER_3_INDEX   7
+#define PIC_IRT_TIMER_4_INDEX   8
+#define PIC_IRT_TIMER_5_INDEX   9
+#define PIC_IRT_TIMER_6_INDEX   10
+#define PIC_IRT_TIMER_7_INDEX   11
+#define PIC_IRT_CLOCK_INDEX     PIC_IRT_TIMER_7_INDEX
+#define PIC_IRT_TIMER_INDEX(num)        ((num) + PIC_IRT_TIMER_0_INDEX)
+
+
+/* 11 and 12 */
+#define PIC_NUM_MSG_Q_IRTS      32
+#define PIC_IRT_MSG_Q0_INDEX    12
+#define PIC_IRT_MSG_Q_INDEX(qid)        ((qid) + PIC_IRT_MSG_Q0_INDEX)
+/* 12 to 43 */
+#define PIC_IRT_MSG_0_INDEX     44
+#define PIC_IRT_MSG_1_INDEX     45
+/* 44 and 45 */
+#define PIC_NUM_PCIE_MSIX_IRTS  32
+#define PIC_IRT_PCIE_MSIX_0_INDEX       46
+#define PIC_IRT_PCIE_MSIX_INDEX(num)    ((num) + PIC_IRT_PCIE_MSIX_0_INDEX)
+/* 46 to 77 */
+#define PIC_NUM_PCIE_LINK_IRTS          4
+#define PIC_IRT_PCIE_LINK_0_INDEX       78
+#define PIC_IRT_PCIE_LINK_1_INDEX       79
+#define PIC_IRT_PCIE_LINK_2_INDEX       80
+#define PIC_IRT_PCIE_LINK_3_INDEX       81
+#define PIC_IRT_PCIE_LINK_INDEX(num)    ((num) + PIC_IRT_PCIE_LINK_0_INDEX)
+/* 78 to 81 */
+#define PIC_NUM_NA_IRTS                 32
+/* 82 to 113 */
+#define PIC_IRT_NA_0_INDEX              82
+#define PIC_IRT_NA_INDEX(num)           ((num) + PIC_IRT_NA_0_INDEX)
+#define PIC_IRT_POE_INDEX               114
+
+#define PIC_NUM_USB_IRTS                6
+#define PIC_IRT_USB_0_INDEX             115
+#define PIC_IRT_EHCI_0_INDEX            115
+#define PIC_IRT_EHCI_1_INDEX            118
+#define PIC_IRT_USB_INDEX(num)          ((num) + PIC_IRT_USB_0_INDEX)
+/* 115 to 120 */
+#define PIC_IRT_GDX_INDEX               121
+#define PIC_IRT_SEC_INDEX               122
+#define PIC_IRT_RSA_INDEX               123
+
+#define PIC_NUM_COMP_IRTS               4
+#define PIC_IRT_COMP_0_INDEX            124
+#define PIC_IRT_COMP_INDEX(num)         ((num) + PIC_IRT_COMP_0_INDEX)
+/* 124 to 127 */
+#define PIC_IRT_GBU_INDEX               128
+#define PIC_IRT_ICC_0_INDEX             129 /* ICC - Inter Chip Coherency */
+#define PIC_IRT_ICC_1_INDEX             130
+#define PIC_IRT_ICC_2_INDEX             131
+#define PIC_IRT_CAM_INDEX               132
+#define PIC_IRT_UART_0_INDEX            133
+#define PIC_IRT_UART_1_INDEX            134
+#define PIC_IRT_I2C_0_INDEX             135
+#define PIC_IRT_I2C_1_INDEX             136
+#define PIC_IRT_SYS_0_INDEX             137
+#define PIC_IRT_SYS_1_INDEX             138
+#define PIC_IRT_JTAG_INDEX              139
+#define PIC_IRT_PIC_INDEX               140
+#define PIC_IRT_NBU_INDEX               141
+#define PIC_IRT_TCU_INDEX               142
+#define PIC_IRT_GCU_INDEX               143 /* GBC - Global Coherency */
+#define PIC_IRT_DMC_0_INDEX             144
+#define PIC_IRT_DMC_1_INDEX             145
+
+#define PIC_NUM_GPIO_IRTS               4
+#define PIC_IRT_GPIO_0_INDEX            146
+#define PIC_IRT_GPIO_INDEX(num)         ((num) + PIC_IRT_GPIO_0_INDEX)
+
+/* 146 to 149 */
+#define PIC_IRT_NOR_INDEX               150
+#define PIC_IRT_NAND_INDEX              151
+#define PIC_IRT_SPI_INDEX               152
+#define PIC_IRT_MMC_INDEX               153
+
+#define PIC_CLOCK_TIMER                 7
+#define PIC_IRQ_BASE                    8
+
+#if !defined(LOCORE) && !defined(__ASSEMBLY__)
+
+#define PIC_IRT_FIRST_IRQ               (PIC_IRQ_BASE)
+#define PIC_IRT_LAST_IRQ                63
+#define PIC_IRQ_IS_IRT(irq)             ((irq) >= PIC_IRT_FIRST_IRQ)
+
+/*
+ *   Misc
+ */
+#define PIC_IRT_VALID                   1
+#define PIC_LOCAL_SCHEDULING            1
+#define PIC_GLOBAL_SCHEDULING           0
+
+#define nlm_read_pic_reg(b, r)  nlm_read_reg64(b, r)
+#define nlm_write_pic_reg(b, r, v) nlm_write_reg64(b, r, v)
+#define nlm_get_pic_pcibase(node) nlm_pcicfg_base(XLP_IO_PIC_OFFSET(node))
+#define nlm_get_pic_regbase(node) (nlm_get_pic_pcibase(node) + XLP_IO_PCI_HDRSZ)
+
+/* IRT and h/w interrupt routines */
+static inline int
+nlm_pic_read_irt(uint64_t base, int irt_index)
+{
+        return nlm_read_pic_reg(base, PIC_IRT(irt_index));
+}
+
+static inline uint64_t
+nlm_pic_read_control(uint64_t base)
+{
+        return nlm_read_pic_reg(base, PIC_CTRL);
+}
+
+static inline void
+nlm_pic_write_control(uint64_t base, uint64_t control)
+{
+        nlm_write_pic_reg(base, PIC_CTRL, control);
+}
+
+static inline void
+nlm_pic_update_control(uint64_t base, uint64_t control)
+{
+        uint64_t val;
+
+        val = nlm_read_pic_reg(base, PIC_CTRL);
+        nlm_write_pic_reg(base, PIC_CTRL, control | val);
+}
+
+static inline void
+nlm_set_irt_to_cpu(uint64_t base, int irt, int cpu)
+{
+        uint64_t val;
+
+        val = nlm_read_pic_reg(base, PIC_IRT(irt));
+        val |= cpu & 0xf;
+        if (cpu > 15)
+                val |= 1 << 16;
+        nlm_write_pic_reg(base, PIC_IRT(irt), val);
+}
+
+static inline void
+nlm_pic_write_irt(uint64_t base, int irt_num, int en, int nmi,
+        int sch, int vec, int dt, int db, int dte)
+{
+        uint64_t val;
+
+        val = (((uint64_t)en & 0x1) << 31) | ((nmi & 0x1) << 29) |
+                        ((sch & 0x1) << 28) | ((vec & 0x3f) << 20) |
+                        ((dt & 0x1) << 19) | ((db & 0x7) << 16) |
+                        (dte & 0xffff);
+
+        nlm_write_pic_reg(base, PIC_IRT(irt_num), val);
+}
+
+static inline void
+nlm_pic_write_irt_direct(uint64_t base, int irt_num, int en, int nmi,
+        int sch, int vec, int cpu)
+{
+        nlm_pic_write_irt(base, irt_num, en, nmi, sch, vec, 1,
+                (cpu >> 4),             /* thread group */
+                1 << (cpu & 0xf));      /* thread mask */
+}
+
+static inline uint64_t
+nlm_pic_read_timer(uint64_t base, int timer)
+{
+        return nlm_read_pic_reg(base, PIC_TIMER_COUNT(timer));
+}
+
+static inline void
+nlm_pic_write_timer(uint64_t base, int timer, uint64_t value)
+{
+        nlm_write_pic_reg(base, PIC_TIMER_COUNT(timer), value);
+}
+
+static inline void
+nlm_pic_set_timer(uint64_t base, int timer, uint64_t value, int irq, int cpu)
+{
+        uint64_t pic_ctrl = nlm_read_pic_reg(base, PIC_CTRL);
+        int en;
+
+        en = (irq > 0);
+        nlm_write_pic_reg(base, PIC_TIMER_MAXVAL(timer), value);
+        nlm_pic_write_irt_direct(base, PIC_IRT_TIMER_INDEX(timer),
+                en, 0, 0, irq, cpu);
+
+        /* enable the timer */
+        pic_ctrl |= (1 << (PIC_CTRL_STE + timer));
+        nlm_write_pic_reg(base, PIC_CTRL, pic_ctrl);
+}
+
+static inline void
+nlm_pic_enable_irt(uint64_t base, int irt)
+{
+        uint64_t reg;
+
+        reg = nlm_read_pic_reg(base, PIC_IRT(irt));
+        nlm_write_pic_reg(base, PIC_IRT(irt), reg | (1u << 31));
+}
+
+static inline void
+nlm_pic_disable_irt(uint64_t base, int irt)
+{
+        uint32_t reg;
+
+        reg = nlm_read_pic_reg(base, PIC_IRT(irt));
+        nlm_write_pic_reg(base, PIC_IRT(irt), reg & ~((uint64_t)1 << 31));
+}
+
+static inline void
+nlm_pic_send_ipi(uint64_t base, int hwt, int irq, int nmi)
+{
+        uint64_t ipi;
+        int     node, ncpu;
+
+        node = hwt / 32;
+        ncpu = hwt & 0x1f;
+        ipi = ((uint64_t)nmi << 31) | (irq << 20) | (node << 17) |
+                (1 << (ncpu & 0xf));
+        if (ncpu > 15)
+                ipi |= 0x10000; /* Setting bit 16 to select cpus 16-31 */
+
+        nlm_write_pic_reg(base, PIC_IPI_CTL, ipi);
+}
+
+static inline void
+nlm_pic_ack(uint64_t base, int irt_num)
+{
+        nlm_write_pic_reg(base, PIC_INT_ACK, irt_num);
+
+        /* Ack the Status register for Watchdog & System timers */
+        if (irt_num < 12)
+                nlm_write_pic_reg(base, PIC_STATUS, (1 << irt_num));
+}
+
+static inline void
+nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt)
+{
+        nlm_pic_write_irt_direct(base, irt, 0, 0, 0, irq, 0);
+}
+
+extern uint64_t nlm_pic_base;
+int nlm_irq_to_irt(int irq);
+int nlm_irt_to_irq(int irt);
+
+#endif /* __ASSEMBLY__ */
+#endif /* _NLM_HAL_PIC_H */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/sys.h b/arch/mips/include/asm/netlogic/xlp-hal/sys.h
new file mode 100644
index 00000000000..21432f7d89b
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlp-hal/sys.h
@@ -0,0 +1,129 @@
+/*
+ * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
+ * reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the NetLogic
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __NLM_HAL_SYS_H__
+#define __NLM_HAL_SYS_H__
+
+/**
+* @file_name sys.h
+* @author Netlogic Microsystems
+* @brief HAL for System configuration registers
+*/
+#define SYS_CHIP_RESET                          0x00
+#define SYS_POWER_ON_RESET_CFG                  0x01
+#define SYS_EFUSE_DEVICE_CFG_STATUS0            0x02
+#define SYS_EFUSE_DEVICE_CFG_STATUS1            0x03
+#define SYS_EFUSE_DEVICE_CFG_STATUS2            0x04
+#define SYS_EFUSE_DEVICE_CFG3                   0x05
+#define SYS_EFUSE_DEVICE_CFG4                   0x06
+#define SYS_EFUSE_DEVICE_CFG5                   0x07
+#define SYS_EFUSE_DEVICE_CFG6                   0x08
+#define SYS_EFUSE_DEVICE_CFG7                   0x09
+#define SYS_PLL_CTRL                            0x0a
+#define SYS_CPU_RESET                           0x0b
+#define SYS_CPU_NONCOHERENT_MODE                0x0d
+#define SYS_CORE_DFS_DIS_CTRL                   0x0e
+#define SYS_CORE_DFS_RST_CTRL                   0x0f
+#define SYS_CORE_DFS_BYP_CTRL                   0x10
+#define SYS_CORE_DFS_PHA_CTRL                   0x11
+#define SYS_CORE_DFS_DIV_INC_CTRL               0x12
+#define SYS_CORE_DFS_DIV_DEC_CTRL               0x13
+#define SYS_CORE_DFS_DIV_VALUE                  0x14
+#define SYS_RESET                               0x15
+#define SYS_DFS_DIS_CTRL                        0x16
+#define SYS_DFS_RST_CTRL                        0x17
+#define SYS_DFS_BYP_CTRL                        0x18
+#define SYS_DFS_DIV_INC_CTRL                    0x19
+#define SYS_DFS_DIV_DEC_CTRL                    0x1a
+#define SYS_DFS_DIV_VALUE0                      0x1b
+#define SYS_DFS_DIV_VALUE1                      0x1c
+#define SYS_SENSE_AMP_DLY                       0x1d
+#define SYS_SOC_SENSE_AMP_DLY                   0x1e
+#define SYS_CTRL0                               0x1f
+#define SYS_CTRL1                               0x20
+#define SYS_TIMEOUT_BS1                         0x21
+#define SYS_BYTE_SWAP                           0x22
+#define SYS_VRM_VID                             0x23
+#define SYS_PWR_RAM_CMD                         0x24
+#define SYS_PWR_RAM_ADDR                        0x25
+#define SYS_PWR_RAM_DATA0                       0x26
+#define SYS_PWR_RAM_DATA1                       0x27
+#define SYS_PWR_RAM_DATA2                       0x28
+#define SYS_PWR_UCODE                           0x29
+#define SYS_CPU0_PWR_STATUS                     0x2a
+#define SYS_CPU1_PWR_STATUS                     0x2b
+#define SYS_CPU2_PWR_STATUS                     0x2c
+#define SYS_CPU3_PWR_STATUS                     0x2d
+#define SYS_CPU4_PWR_STATUS                     0x2e
+#define SYS_CPU5_PWR_STATUS                     0x2f
+#define SYS_CPU6_PWR_STATUS                     0x30
+#define SYS_CPU7_PWR_STATUS                     0x31
+#define SYS_STATUS                              0x32
+#define SYS_INT_POL                             0x33
+#define SYS_INT_TYPE                            0x34
+#define SYS_INT_STATUS                          0x35
+#define SYS_INT_MASK0                           0x36
+#define SYS_INT_MASK1                           0x37
+#define SYS_UCO_S_ECC                           0x38
+#define SYS_UCO_M_ECC                           0x39
+#define SYS_UCO_ADDR                            0x3a
+#define SYS_UCO_INSTR                           0x3b
+#define SYS_MEM_BIST0                           0x3c
+#define SYS_MEM_BIST1                           0x3d
+#define SYS_MEM_BIST2                           0x3e
+#define SYS_MEM_BIST3                           0x3f
+#define SYS_MEM_BIST4                           0x40
+#define SYS_MEM_BIST5                           0x41
+#define SYS_MEM_BIST6                           0x42
+#define SYS_MEM_BIST7                           0x43
+#define SYS_MEM_BIST8                           0x44
+#define SYS_MEM_BIST9                           0x45
+#define SYS_MEM_BIST10                          0x46
+#define SYS_MEM_BIST11                          0x47
+#define SYS_MEM_BIST12                          0x48
+#define SYS_SCRTCH0                             0x49
+#define SYS_SCRTCH1                             0x4a
+#define SYS_SCRTCH2                             0x4b
+#define SYS_SCRTCH3                             0x4c
+
+#ifndef __ASSEMBLY__
+
+#define nlm_read_sys_reg(b, r)          nlm_read_reg(b, r)
+#define nlm_write_sys_reg(b, r, v)      nlm_write_reg(b, r, v)
+#define nlm_get_sys_pcibase(node) nlm_pcicfg_base(XLP_IO_SYS_OFFSET(node))
+#define nlm_get_sys_regbase(node) (nlm_get_sys_pcibase(node) + XLP_IO_PCI_HDRSZ)
+
+extern uint64_t nlm_sys_base;
+#endif
+#endif
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/uart.h b/arch/mips/include/asm/netlogic/xlp-hal/uart.h
new file mode 100644
index 00000000000..6a7046ca094
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlp-hal/uart.h
@@ -0,0 +1,191 @@
+/*
+ * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
+ * reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the NetLogic
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __XLP_HAL_UART_H__
+#define __XLP_HAL_UART_H__
+
+/* UART Specific registers */
+#define UART_RX_DATA            0x00
+#define UART_TX_DATA            0x00
+
+#define UART_INT_EN             0x01
+#define UART_INT_ID             0x02
+#define UART_FIFO_CTL           0x02
+#define UART_LINE_CTL           0x03
+#define UART_MODEM_CTL          0x04
+#define UART_LINE_STS           0x05
+#define UART_MODEM_STS          0x06
+
+#define UART_DIVISOR0           0x00
+#define UART_DIVISOR1           0x01
+
+#define BASE_BAUD               (XLP_IO_CLK/16)
+#define BAUD_DIVISOR(baud)      (BASE_BAUD / baud)
+
+/* LCR mask values */
+#define LCR_5BITS               0x00
+#define LCR_6BITS               0x01
+#define LCR_7BITS               0x02
+#define LCR_8BITS               0x03
+#define LCR_STOPB               0x04
+#define LCR_PENAB               0x08
+#define LCR_PODD                0x00
+#define LCR_PEVEN               0x10
+#define LCR_PONE                0x20
+#define LCR_PZERO               0x30
+#define LCR_SBREAK              0x40
+#define LCR_EFR_ENABLE          0xbf
+#define LCR_DLAB                0x80
+
+/* MCR mask values */
+#define MCR_DTR                 0x01
+#define MCR_RTS                 0x02
+#define MCR_DRS                 0x04
+#define MCR_IE                  0x08
+#define MCR_LOOPBACK            0x10
+
+/* FCR mask values */
+#define FCR_RCV_RST             0x02
+#define FCR_XMT_RST             0x04
+#define FCR_RX_LOW              0x00
+#define FCR_RX_MEDL             0x40
+#define FCR_RX_MEDH             0x80
+#define FCR_RX_HIGH             0xc0
+
+/* IER mask values */
+#define IER_ERXRDY              0x1
+#define IER_ETXRDY              0x2
+#define IER_ERLS                0x4
+#define IER_EMSC                0x8
+
+#if !defined(LOCORE) && !defined(__ASSEMBLY__)
+
+#define nlm_read_uart_reg(b, r)         nlm_read_reg(b, r)
+#define nlm_write_uart_reg(b, r, v)     nlm_write_reg(b, r, v)
+#define nlm_get_uart_pcibase(node, inst)        \
+                nlm_pcicfg_base(XLP_IO_UART_OFFSET(node, inst))
+#define nlm_get_uart_regbase(node, inst)        \
+                        (nlm_get_uart_pcibase(node, inst) + XLP_IO_PCI_HDRSZ)
+
+static inline void
+nlm_uart_set_baudrate(uint64_t base, int baud)
+{
+        uint32_t lcr;
+
+        lcr = nlm_read_uart_reg(base, UART_LINE_CTL);
+
+        /* enable divisor register, and write baud values */
+        nlm_write_uart_reg(base, UART_LINE_CTL, lcr | (1 << 7));
+        nlm_write_uart_reg(base, UART_DIVISOR0,
+                        (BAUD_DIVISOR(baud) & 0xff));
+        nlm_write_uart_reg(base, UART_DIVISOR1,
+                        ((BAUD_DIVISOR(baud) >> 8) & 0xff));
+
+        /* restore default lcr */
+        nlm_write_uart_reg(base, UART_LINE_CTL, lcr);
+}
+
+static inline void
+nlm_uart_outbyte(uint64_t base, char c)
+{
+        uint32_t lsr;
+
+        for (;;) {
+                lsr = nlm_read_uart_reg(base, UART_LINE_STS);
+                if (lsr & 0x20)
+                        break;
+        }
+
+        nlm_write_uart_reg(base, UART_TX_DATA, (int)c);
+}
+
+static inline char
+nlm_uart_inbyte(uint64_t base)
+{
+        int data, lsr;
+
+        for (;;) {
+                lsr = nlm_read_uart_reg(base, UART_LINE_STS);
+                if (lsr & 0x80) { /* parity/frame/break-error - push a zero */
+                        data = 0;
+                        break;
+                }
+                if (lsr & 0x01) {       /* Rx data */
+                        data = nlm_read_uart_reg(base, UART_RX_DATA);
+                        break;
+                }
+        }
+
+        return (char)data;
+}
+
+static inline int
+nlm_uart_init(uint64_t base, int baud, int databits, int stopbits,
+        int parity, int int_en, int loopback)
+{
+        uint32_t lcr;
+
+        lcr = 0;
+        if (databits >= 8)
+                lcr |= LCR_8BITS;
+        else if (databits == 7)
+                lcr |= LCR_7BITS;
+        else if (databits == 6)
+                lcr |= LCR_6BITS;
+        else
+                lcr |= LCR_5BITS;
+
+        if (stopbits > 1)
+                lcr |= LCR_STOPB;
+
+        lcr |= parity << 3;
+
+        /* setup default lcr */
+        nlm_write_uart_reg(base, UART_LINE_CTL, lcr);
+
+        /* Reset the FIFOs */
+        nlm_write_uart_reg(base, UART_LINE_CTL, FCR_RCV_RST | FCR_XMT_RST);
+
+        nlm_uart_set_baudrate(base, baud);
+
+        if (loopback)
+                nlm_write_uart_reg(base, UART_MODEM_CTL, 0x1f);
+
+        if (int_en)
+                nlm_write_uart_reg(base, UART_INT_EN, IER_ERXRDY | IER_ETXRDY);
+
+        return 0;
+}
+#endif /* !LOCORE && !__ASSEMBLY__ */
+#endif /* __XLP_HAL_UART_H__ */
diff --git a/arch/mips/netlogic/xlr/xlr_console.c b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
index 759df069220..1540588e396 100644
--- a/arch/mips/netlogic/xlr/xlr_console.c
+++ b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
@@ -32,15 +32,20 @@
  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include <linux/types.h>
-#include <asm/netlogic/xlr/iomap.h>
+#ifndef _NLM_HAL_XLP_H
+#define _NLM_HAL_XLP_H
 
-void prom_putchar(char c)
-{
-        nlm_reg_t *mmio;
+#define PIC_UART_0_IRQ           17
+#define PIC_UART_1_IRQ           18
 
-        mmio = netlogic_io_mmio(NETLOGIC_IO_UART_0_OFFSET);
-        while (netlogic_read_reg(mmio, 0x5) == 0)
-                ;
-        netlogic_write_reg(mmio, 0x0, c);
-}
+#ifndef __ASSEMBLY__
+
+/* SMP support functions */
+void xlp_boot_core0_siblings(void);
+void xlp_wakeup_secondary_cpus(void);
+
+void xlp_mmu_init(void);
+void nlm_hal_init(void);
+
+#endif /* !__ASSEMBLY__ */
+#endif /* _ASM_NLM_XLP_H */
diff --git a/arch/mips/include/asm/netlogic/xlr/iomap.h b/arch/mips/include/asm/netlogic/xlr/iomap.h
index 2e3a4dd5304..2e768f032e8 100644
--- a/arch/mips/include/asm/netlogic/xlr/iomap.h
+++ b/arch/mips/include/asm/netlogic/xlr/iomap.h
@@ -106,26 +106,4 @@
 #define DEFAULT_HT_TYPE0_CFG_BASE       0x16000000
 #define DEFAULT_HT_TYPE1_CFG_BASE       0x17000000
 
-#ifndef __ASSEMBLY__
-#include <linux/types.h>
-#include <asm/byteorder.h>
-
-typedef volatile __u32 nlm_reg_t;
-extern unsigned long netlogic_io_base;
-
-/* FIXME read once in write_reg */
-#ifdef CONFIG_CPU_LITTLE_ENDIAN
-#define netlogic_read_reg(base, offset)         ((base)[(offset)])
-#define netlogic_write_reg(base, offset, value) ((base)[(offset)] = (value))
-#else
-#define netlogic_read_reg(base, offset)         (be32_to_cpu((base)[(offset)]))
-#define netlogic_write_reg(base, offset, value) \
-                                ((base)[(offset)] = cpu_to_be32((value)))
-#endif
-
-#define netlogic_read_reg_le32(base, offset) (le32_to_cpu((base)[(offset)]))
-#define netlogic_write_reg_le32(base, offset, value) \
-                                ((base)[(offset)] = cpu_to_le32((value)))
-#define netlogic_io_mmio(offset) ((nlm_reg_t *)(netlogic_io_base+(offset)))
-#endif /* __ASSEMBLY__ */
 #endif
diff --git a/arch/mips/include/asm/netlogic/xlr/msidef.h b/arch/mips/include/asm/netlogic/xlr/msidef.h
new file mode 100644
index 00000000000..7e39d40be4f
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlr/msidef.h
@@ -0,0 +1,84 @@
+/*
+ * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
+ * reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the NetLogic
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef ASM_RMI_MSIDEF_H
+#define ASM_RMI_MSIDEF_H
+
+/*
+ * Constants for Intel APIC based MSI messages.
+ * Adapted for the RMI XLR using identical defines
+ */
+
+/*
+ * Shifts for MSI data
+ */
+
+#define MSI_DATA_VECTOR_SHIFT           0
+#define  MSI_DATA_VECTOR_MASK           0x000000ff
+#define  MSI_DATA_VECTOR(v)             (((v) << MSI_DATA_VECTOR_SHIFT) & \
+                                                MSI_DATA_VECTOR_MASK)
+
+#define MSI_DATA_DELIVERY_MODE_SHIFT    8
+#define  MSI_DATA_DELIVERY_FIXED        (0 << MSI_DATA_DELIVERY_MODE_SHIFT)
+#define  MSI_DATA_DELIVERY_LOWPRI       (1 << MSI_DATA_DELIVERY_MODE_SHIFT)
+
+#define MSI_DATA_LEVEL_SHIFT            14
+#define  MSI_DATA_LEVEL_DEASSERT        (0 << MSI_DATA_LEVEL_SHIFT)
+#define  MSI_DATA_LEVEL_ASSERT          (1 << MSI_DATA_LEVEL_SHIFT)
+
+#define MSI_DATA_TRIGGER_SHIFT          15
+#define  MSI_DATA_TRIGGER_EDGE          (0 << MSI_DATA_TRIGGER_SHIFT)
+#define  MSI_DATA_TRIGGER_LEVEL         (1 << MSI_DATA_TRIGGER_SHIFT)
+
+/*
+ * Shift/mask fields for msi address
+ */
+
+#define MSI_ADDR_BASE_HI                0
+#define MSI_ADDR_BASE_LO                0xfee00000
+
+#define MSI_ADDR_DEST_MODE_SHIFT        2
+#define  MSI_ADDR_DEST_MODE_PHYSICAL    (0 << MSI_ADDR_DEST_MODE_SHIFT)
+#define  MSI_ADDR_DEST_MODE_LOGICAL     (1 << MSI_ADDR_DEST_MODE_SHIFT)
+
+#define MSI_ADDR_REDIRECTION_SHIFT      3
+#define  MSI_ADDR_REDIRECTION_CPU       (0 << MSI_ADDR_REDIRECTION_SHIFT)
+#define  MSI_ADDR_REDIRECTION_LOWPRI    (1 << MSI_ADDR_REDIRECTION_SHIFT)
+
+#define MSI_ADDR_DEST_ID_SHIFT          12
+#define  MSI_ADDR_DEST_ID_MASK          0x00ffff0
+#define  MSI_ADDR_DEST_ID(dest)         (((dest) << MSI_ADDR_DEST_ID_SHIFT) & \
+                                                 MSI_ADDR_DEST_ID_MASK)
+
+#endif /* ASM_RMI_MSIDEF_H */
diff --git a/arch/mips/include/asm/netlogic/xlr/pic.h b/arch/mips/include/asm/netlogic/xlr/pic.h
index 5cceb746f08..868013e62f3 100644
--- a/arch/mips/include/asm/netlogic/xlr/pic.h
+++ b/arch/mips/include/asm/netlogic/xlr/pic.h
@@ -193,39 +193,72 @@
 /* end XLS */
 
 #ifndef __ASSEMBLY__
-static inline void pic_send_ipi(u32 ipi)
+
+#define PIC_IRQ_IS_EDGE_TRIGGERED(irq)  (((irq) >= PIC_TIMER_0_IRQ) && \
+                                        ((irq) <= PIC_TIMER_7_IRQ))
+#define PIC_IRQ_IS_IRT(irq)             (((irq) >= PIC_IRT_FIRST_IRQ) && \
+                                        ((irq) <= PIC_IRT_LAST_IRQ))
+
+static inline int
+nlm_irq_to_irt(int irq)
 {
-        nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
+        if (PIC_IRQ_IS_IRT(irq) == 0)
+                return -1;
 
-        netlogic_write_reg(mmio, PIC_IPI, ipi);
+        return PIC_IRQ_TO_INTR(irq);
 }
 
-static inline u32 pic_read_control(void)
+static inline int
+nlm_irt_to_irq(int irt)
 {
-        nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
 
-        return netlogic_read_reg(mmio, PIC_CTRL);
+        return PIC_INTR_TO_IRQ(irt);
 }
 
-static inline void pic_write_control(u32 control)
+static inline void
+nlm_pic_enable_irt(uint64_t base, int irt)
 {
-        nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
+        uint32_t reg;
 
-        netlogic_write_reg(mmio, PIC_CTRL, control);
+        reg = nlm_read_reg(base, PIC_IRT_1(irt));
+        nlm_write_reg(base, PIC_IRT_1(irt), reg | (1u << 31));
 }
 
-static inline void pic_update_control(u32 control)
+static inline void
+nlm_pic_disable_irt(uint64_t base, int irt)
 {
-        nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
+        uint32_t reg;
 
-        netlogic_write_reg(mmio, PIC_CTRL,
-                (control | netlogic_read_reg(mmio, PIC_CTRL)));
+        reg = nlm_read_reg(base, PIC_IRT_1(irt));
+        nlm_write_reg(base, PIC_IRT_1(irt), reg & ~(1u << 31));
 }
 
-#define PIC_IRQ_IS_EDGE_TRIGGERED(irq)  (((irq) >= PIC_TIMER_0_IRQ) && \
-                                        ((irq) <= PIC_TIMER_7_IRQ))
-#define PIC_IRQ_IS_IRT(irq)             (((irq) >= PIC_IRT_FIRST_IRQ) && \
-                                        ((irq) <= PIC_IRT_LAST_IRQ))
-#endif
+static inline void
+nlm_pic_send_ipi(uint64_t base, int hwt, int irq, int nmi)
+{
+        unsigned int tid, pid;
+
+        tid = hwt & 0x3;
+        pid = (hwt >> 2) & 0x07;
+        nlm_write_reg(base, PIC_IPI,
+                (pid << 20) | (tid << 16) | (nmi << 8) | irq);
+}
+
+static inline void
+nlm_pic_ack(uint64_t base, int irt)
+{
+        nlm_write_reg(base, PIC_INT_ACK, 1u << irt);
+}
 
+static inline void
+nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt)
+{
+        nlm_write_reg(base, PIC_IRT_0(irt), (1u << hwt));
+        /* local scheduling, invalid, level by default */
+        nlm_write_reg(base, PIC_IRT_1(irt),
+                (1 << 30) | (1 << 6) | irq);
+}
+
+extern uint64_t nlm_pic_base;
+#endif
 #endif /* _ASM_NLM_XLR_PIC_H */
diff --git a/arch/mips/include/asm/netlogic/xlr/xlr.h b/arch/mips/include/asm/netlogic/xlr/xlr.h
index 3e6372692a0..ff4a17b0bf7 100644
--- a/arch/mips/include/asm/netlogic/xlr/xlr.h
+++ b/arch/mips/include/asm/netlogic/xlr/xlr.h
@@ -40,17 +40,8 @@ struct uart_port;
 unsigned int nlm_xlr_uart_in(struct uart_port *, int);
 void nlm_xlr_uart_out(struct uart_port *, int, int);
 
-/* SMP support functions */
-struct irq_desc;
-void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc);
-void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc);
-int nlm_wakeup_secondary_cpus(u32 wakeup_mask);
-void nlm_smp_irq_init(void);
-void nlm_boot_smp_nmi(void);
-void prom_pre_boot_secondary_cpus(void);
-
-extern struct plat_smp_ops nlm_smp_ops;
-extern unsigned long nlm_common_ebase;
+/* SMP helpers */
+void xlr_wakeup_secondary_cpus(void);
 
 /* XLS B silicon "Rook" */
 static inline unsigned int nlm_chip_is_xls_b(void)
diff --git a/drivers/staging/octeon/cvmx-address.h b/arch/mips/include/asm/octeon/cvmx-address.h
index 3c74d826e2e..3c74d826e2e 100644
--- a/drivers/staging/octeon/cvmx-address.h
+++ b/arch/mips/include/asm/octeon/cvmx-address.h
diff --git a/drivers/staging/octeon/cvmx-asxx-defs.h b/arch/mips/include/asm/octeon/cvmx-asxx-defs.h
index 91415a85e8d..91415a85e8d 100644
--- a/drivers/staging/octeon/cvmx-asxx-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-asxx-defs.h
diff --git a/arch/mips/include/asm/octeon/cvmx-bootinfo.h b/arch/mips/include/asm/octeon/cvmx-bootinfo.h
index 4e4c3a8282d..1db1dc2724c 100644
--- a/arch/mips/include/asm/octeon/cvmx-bootinfo.h
+++ b/arch/mips/include/asm/octeon/cvmx-bootinfo.h
@@ -39,7 +39,7 @@
  * versions.
  */
 #define CVMX_BOOTINFO_MAJ_VER 1
-#define CVMX_BOOTINFO_MIN_VER 2
+#define CVMX_BOOTINFO_MIN_VER 3
 
 #if (CVMX_BOOTINFO_MAJ_VER == 1)
 #define CVMX_BOOTINFO_OCTEON_SERIAL_LEN 20
@@ -116,7 +116,13 @@ struct cvmx_bootinfo {
          */
         uint32_t config_flags;
 #endif
-
+#if (CVMX_BOOTINFO_MIN_VER >= 3)
+        /*
+         * Address of the OF Flattened Device Tree structure
+         * describing the board.
+         */
+        uint64_t fdt_addr;
+#endif
 };
 
 #define CVMX_BOOTINFO_CFG_FLAG_PCI_HOST                 (1ull << 0)
@@ -164,6 +170,22 @@ enum cvmx_board_types_enum {
         /* Special 'generic' board type, supports many boards */
         CVMX_BOARD_TYPE_GENERIC = 28,
         CVMX_BOARD_TYPE_EBH5610 = 29,
+        CVMX_BOARD_TYPE_LANAI2_A = 30,
+        CVMX_BOARD_TYPE_LANAI2_U = 31,
+        CVMX_BOARD_TYPE_EBB5600 = 32,
+        CVMX_BOARD_TYPE_EBB6300 = 33,
+        CVMX_BOARD_TYPE_NIC_XLE_10G = 34,
+        CVMX_BOARD_TYPE_LANAI2_G = 35,
+        CVMX_BOARD_TYPE_EBT5810 = 36,
+        CVMX_BOARD_TYPE_NIC10E = 37,
+        CVMX_BOARD_TYPE_EP6300C = 38,
+        CVMX_BOARD_TYPE_EBB6800 = 39,
+        CVMX_BOARD_TYPE_NIC4E = 40,
+        CVMX_BOARD_TYPE_NIC2E = 41,
+        CVMX_BOARD_TYPE_EBB6600 = 42,
+        CVMX_BOARD_TYPE_REDWING = 43,
+        CVMX_BOARD_TYPE_NIC68_4 = 44,
+        CVMX_BOARD_TYPE_NIC10E_66 = 45,
         CVMX_BOARD_TYPE_MAX,
 
         /*
@@ -181,6 +203,23 @@ enum cvmx_board_types_enum {
         CVMX_BOARD_TYPE_CUST_NS0216 = 10002,
         CVMX_BOARD_TYPE_CUST_NB5 = 10003,
         CVMX_BOARD_TYPE_CUST_WMR500 = 10004,
+        CVMX_BOARD_TYPE_CUST_ITB101 = 10005,
+        CVMX_BOARD_TYPE_CUST_NTE102 = 10006,
+        CVMX_BOARD_TYPE_CUST_AGS103 = 10007,
+        CVMX_BOARD_TYPE_CUST_GST104 = 10008,
+        CVMX_BOARD_TYPE_CUST_GCT105 = 10009,
+        CVMX_BOARD_TYPE_CUST_AGS106 = 10010,
+        CVMX_BOARD_TYPE_CUST_SGM107 = 10011,
+        CVMX_BOARD_TYPE_CUST_GCT108 = 10012,
+        CVMX_BOARD_TYPE_CUST_AGS109 = 10013,
+        CVMX_BOARD_TYPE_CUST_GCT110 = 10014,
+        CVMX_BOARD_TYPE_CUST_L2_AIR_SENDER = 10015,
+        CVMX_BOARD_TYPE_CUST_L2_AIR_RECEIVER = 10016,
+        CVMX_BOARD_TYPE_CUST_L2_ACCTON2_TX = 10017,
+        CVMX_BOARD_TYPE_CUST_L2_ACCTON2_RX = 10018,
+        CVMX_BOARD_TYPE_CUST_L2_WSTRNSNIC_TX = 10019,
+        CVMX_BOARD_TYPE_CUST_L2_WSTRNSNIC_RX = 10020,
+        CVMX_BOARD_TYPE_CUST_L2_ZINWELL = 10021,
         CVMX_BOARD_TYPE_CUST_DEFINED_MAX = 20000,
 
         /*
@@ -241,6 +280,22 @@ static inline const char *cvmx_board_type_to_string(enum
                 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CB5200)
                 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_GENERIC)
                 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5610)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_LANAI2_A)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_LANAI2_U)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBB5600)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBB6300)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC_XLE_10G)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_LANAI2_G)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT5810)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC10E)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EP6300C)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBB6800)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC4E)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC2E)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBB6600)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_REDWING)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC68_4)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC10E_66)
                 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_MAX)
 
                         /* Customer boards listed here */
@@ -249,6 +304,23 @@ static inline const char *cvmx_board_type_to_string(enum
                 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_NS0216)
                 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_NB5)
                 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_WMR500)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_ITB101)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_NTE102)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_AGS103)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_GST104)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_GCT105)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_AGS106)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_SGM107)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_GCT108)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_AGS109)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_GCT110)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_AIR_SENDER)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_AIR_RECEIVER)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_ACCTON2_TX)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_ACCTON2_RX)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_WSTRNSNIC_TX)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_WSTRNSNIC_RX)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_ZINWELL)
                 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_DEFINED_MAX)
 
                     /* Customer private range */
@@ -265,9 +337,9 @@ static inline const char *cvmx_chip_type_to_string(enum
 {
         switch (type) {
                 ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_NULL)
-                    ENUM_CHIP_TYPE_CASE(CVMX_CHIP_SIM_TYPE_DEPRECATED)
-                    ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_OCTEON_SAMPLE)
-                    ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_MAX)
+                ENUM_CHIP_TYPE_CASE(CVMX_CHIP_SIM_TYPE_DEPRECATED)
+                ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_OCTEON_SAMPLE)
+                ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_MAX)
         }
         return "Unsupported Chip";
 }
diff --git a/drivers/staging/octeon/cvmx-cmd-queue.h b/arch/mips/include/asm/octeon/cvmx-cmd-queue.h
index 614653b686a..614653b686a 100644
--- a/drivers/staging/octeon/cvmx-cmd-queue.h
+++ b/arch/mips/include/asm/octeon/cvmx-cmd-queue.h
diff --git a/drivers/staging/octeon/cvmx-config.h b/arch/mips/include/asm/octeon/cvmx-config.h
index 078a520481c..26835d1b43b 100644
--- a/drivers/staging/octeon/cvmx-config.h
+++ b/arch/mips/include/asm/octeon/cvmx-config.h
@@ -166,4 +166,3 @@ typedef enum {
 #define CVMX_HELPER_DISABLE_RGMII_BACKPRESSURE 0
 
 #endif /* __CVMX_CONFIG_H__ */
-
diff --git a/drivers/staging/octeon/cvmx-dbg-defs.h b/arch/mips/include/asm/octeon/cvmx-dbg-defs.h
index abbf42d05e5..abbf42d05e5 100644
--- a/drivers/staging/octeon/cvmx-dbg-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-dbg-defs.h
diff --git a/arch/mips/include/asm/octeon/cvmx-dpi-defs.h b/arch/mips/include/asm/octeon/cvmx-dpi-defs.h
new file mode 100644
index 00000000000..c34ad04789c
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-dpi-defs.h
@@ -0,0 +1,643 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2011 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_DPI_DEFS_H__
+#define __CVMX_DPI_DEFS_H__
+
+#define CVMX_DPI_BIST_STATUS (CVMX_ADD_IO_SEG(0x0001DF0000000000ull))
+#define CVMX_DPI_CTL (CVMX_ADD_IO_SEG(0x0001DF0000000040ull))
+#define CVMX_DPI_DMAX_COUNTS(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000300ull) + ((offset) & 7) * 8)
+#define CVMX_DPI_DMAX_DBELL(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000200ull) + ((offset) & 7) * 8)
+#define CVMX_DPI_DMAX_ERR_RSP_STATUS(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000A80ull) + ((offset) & 7) * 8)
+#define CVMX_DPI_DMAX_IBUFF_SADDR(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000280ull) + ((offset) & 7) * 8)
+#define CVMX_DPI_DMAX_IFLIGHT(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000A00ull) + ((offset) & 7) * 8)
+#define CVMX_DPI_DMAX_NADDR(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000380ull) + ((offset) & 7) * 8)
+#define CVMX_DPI_DMAX_REQBNK0(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000400ull) + ((offset) & 7) * 8)
+#define CVMX_DPI_DMAX_REQBNK1(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000480ull) + ((offset) & 7) * 8)
+#define CVMX_DPI_DMA_CONTROL (CVMX_ADD_IO_SEG(0x0001DF0000000048ull))
+#define CVMX_DPI_DMA_ENGX_EN(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000080ull) + ((offset) & 7) * 8)
+#define CVMX_DPI_DMA_PPX_CNT(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000B00ull) + ((offset) & 31) * 8)
+#define CVMX_DPI_ENGX_BUF(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000880ull) + ((offset) & 7) * 8)
+#define CVMX_DPI_INFO_REG (CVMX_ADD_IO_SEG(0x0001DF0000000980ull))
+#define CVMX_DPI_INT_EN (CVMX_ADD_IO_SEG(0x0001DF0000000010ull))
+#define CVMX_DPI_INT_REG (CVMX_ADD_IO_SEG(0x0001DF0000000008ull))
+#define CVMX_DPI_NCBX_CFG(block_id) (CVMX_ADD_IO_SEG(0x0001DF0000000800ull))
+#define CVMX_DPI_PINT_INFO (CVMX_ADD_IO_SEG(0x0001DF0000000830ull))
+#define CVMX_DPI_PKT_ERR_RSP (CVMX_ADD_IO_SEG(0x0001DF0000000078ull))
+#define CVMX_DPI_REQ_ERR_RSP (CVMX_ADD_IO_SEG(0x0001DF0000000058ull))
+#define CVMX_DPI_REQ_ERR_RSP_EN (CVMX_ADD_IO_SEG(0x0001DF0000000068ull))
+#define CVMX_DPI_REQ_ERR_RST (CVMX_ADD_IO_SEG(0x0001DF0000000060ull))
+#define CVMX_DPI_REQ_ERR_RST_EN (CVMX_ADD_IO_SEG(0x0001DF0000000070ull))
+#define CVMX_DPI_REQ_ERR_SKIP_COMP (CVMX_ADD_IO_SEG(0x0001DF0000000838ull))
+#define CVMX_DPI_REQ_GBL_EN (CVMX_ADD_IO_SEG(0x0001DF0000000050ull))
+#define CVMX_DPI_SLI_PRTX_CFG(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000900ull) + ((offset) & 3) * 8)
+#define CVMX_DPI_SLI_PRTX_ERR_INFO(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000940ull) + ((offset) & 3) * 8)
+
+union cvmx_dpi_bist_status {
+        uint64_t u64;
+        struct cvmx_dpi_bist_status_s {
+                uint64_t reserved_47_63:17;
+                uint64_t bist:47;
+        } s;
+        struct cvmx_dpi_bist_status_s cn61xx;
+        struct cvmx_dpi_bist_status_cn63xx {
+                uint64_t reserved_45_63:19;
+                uint64_t bist:45;
+        } cn63xx;
+        struct cvmx_dpi_bist_status_cn63xxp1 {
+                uint64_t reserved_37_63:27;
+                uint64_t bist:37;
+        } cn63xxp1;
+        struct cvmx_dpi_bist_status_s cn66xx;
+        struct cvmx_dpi_bist_status_cn63xx cn68xx;
+        struct cvmx_dpi_bist_status_cn63xx cn68xxp1;
+};
+
+union cvmx_dpi_ctl {
+        uint64_t u64;
+        struct cvmx_dpi_ctl_s {
+                uint64_t reserved_2_63:62;
+                uint64_t clk:1;
+                uint64_t en:1;
+        } s;
+        struct cvmx_dpi_ctl_cn61xx {
+                uint64_t reserved_1_63:63;
+                uint64_t en:1;
+        } cn61xx;
+        struct cvmx_dpi_ctl_s cn63xx;
+        struct cvmx_dpi_ctl_s cn63xxp1;
+        struct cvmx_dpi_ctl_s cn66xx;
+        struct cvmx_dpi_ctl_s cn68xx;
+        struct cvmx_dpi_ctl_s cn68xxp1;
+};
+
+union cvmx_dpi_dmax_counts {
+        uint64_t u64;
+        struct cvmx_dpi_dmax_counts_s {
+                uint64_t reserved_39_63:25;
+                uint64_t fcnt:7;
+                uint64_t dbell:32;
+        } s;
+        struct cvmx_dpi_dmax_counts_s cn61xx;
+        struct cvmx_dpi_dmax_counts_s cn63xx;
+        struct cvmx_dpi_dmax_counts_s cn63xxp1;
+        struct cvmx_dpi_dmax_counts_s cn66xx;
+        struct cvmx_dpi_dmax_counts_s cn68xx;
+        struct cvmx_dpi_dmax_counts_s cn68xxp1;
+};
+
+union cvmx_dpi_dmax_dbell {
+        uint64_t u64;
+        struct cvmx_dpi_dmax_dbell_s {
+                uint64_t reserved_16_63:48;
+                uint64_t dbell:16;
+        } s;
+        struct cvmx_dpi_dmax_dbell_s cn61xx;
+        struct cvmx_dpi_dmax_dbell_s cn63xx;
+        struct cvmx_dpi_dmax_dbell_s cn63xxp1;
+        struct cvmx_dpi_dmax_dbell_s cn66xx;
+        struct cvmx_dpi_dmax_dbell_s cn68xx;
+        struct cvmx_dpi_dmax_dbell_s cn68xxp1;
+};
+
+union cvmx_dpi_dmax_err_rsp_status {
+        uint64_t u64;
+        struct cvmx_dpi_dmax_err_rsp_status_s {
+                uint64_t reserved_6_63:58;
+                uint64_t status:6;
+        } s;
+        struct cvmx_dpi_dmax_err_rsp_status_s cn61xx;
+        struct cvmx_dpi_dmax_err_rsp_status_s cn66xx;
+        struct cvmx_dpi_dmax_err_rsp_status_s cn68xx;
+        struct cvmx_dpi_dmax_err_rsp_status_s cn68xxp1;
+};
+
+union cvmx_dpi_dmax_ibuff_saddr {
+        uint64_t u64;
+        struct cvmx_dpi_dmax_ibuff_saddr_s {
+                uint64_t reserved_62_63:2;
+                uint64_t csize:14;
+                uint64_t reserved_41_47:7;
+                uint64_t idle:1;
+                uint64_t saddr:33;
+                uint64_t reserved_0_6:7;
+        } s;
+        struct cvmx_dpi_dmax_ibuff_saddr_cn61xx {
+                uint64_t reserved_62_63:2;
+                uint64_t csize:14;
+                uint64_t reserved_41_47:7;
+                uint64_t idle:1;
+                uint64_t reserved_36_39:4;
+                uint64_t saddr:29;
+                uint64_t reserved_0_6:7;
+        } cn61xx;
+        struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn63xx;
+        struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn63xxp1;
+        struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn66xx;
+        struct cvmx_dpi_dmax_ibuff_saddr_s cn68xx;
+        struct cvmx_dpi_dmax_ibuff_saddr_s cn68xxp1;
+};
+
+union cvmx_dpi_dmax_iflight {
+        uint64_t u64;
+        struct cvmx_dpi_dmax_iflight_s {
+                uint64_t reserved_3_63:61;
+                uint64_t cnt:3;
+        } s;
+        struct cvmx_dpi_dmax_iflight_s cn61xx;
+        struct cvmx_dpi_dmax_iflight_s cn66xx;
+        struct cvmx_dpi_dmax_iflight_s cn68xx;
+        struct cvmx_dpi_dmax_iflight_s cn68xxp1;
+};
+
+union cvmx_dpi_dmax_naddr {
+        uint64_t u64;
+        struct cvmx_dpi_dmax_naddr_s {
+                uint64_t reserved_40_63:24;
+                uint64_t addr:40;
+        } s;
+        struct cvmx_dpi_dmax_naddr_cn61xx {
+                uint64_t reserved_36_63:28;
+                uint64_t addr:36;
+        } cn61xx;
+        struct cvmx_dpi_dmax_naddr_cn61xx cn63xx;
+        struct cvmx_dpi_dmax_naddr_cn61xx cn63xxp1;
+        struct cvmx_dpi_dmax_naddr_cn61xx cn66xx;
+        struct cvmx_dpi_dmax_naddr_s cn68xx;
+        struct cvmx_dpi_dmax_naddr_s cn68xxp1;
+};
+
+union cvmx_dpi_dmax_reqbnk0 {
+        uint64_t u64;
+        struct cvmx_dpi_dmax_reqbnk0_s {
+                uint64_t state:64;
+        } s;
+        struct cvmx_dpi_dmax_reqbnk0_s cn61xx;
+        struct cvmx_dpi_dmax_reqbnk0_s cn63xx;
+        struct cvmx_dpi_dmax_reqbnk0_s cn63xxp1;
+        struct cvmx_dpi_dmax_reqbnk0_s cn66xx;
+        struct cvmx_dpi_dmax_reqbnk0_s cn68xx;
+        struct cvmx_dpi_dmax_reqbnk0_s cn68xxp1;
+};
+
+union cvmx_dpi_dmax_reqbnk1 {
+        uint64_t u64;
+        struct cvmx_dpi_dmax_reqbnk1_s {
+                uint64_t state:64;
+        } s;
+        struct cvmx_dpi_dmax_reqbnk1_s cn61xx;
+        struct cvmx_dpi_dmax_reqbnk1_s cn63xx;
+        struct cvmx_dpi_dmax_reqbnk1_s cn63xxp1;
+        struct cvmx_dpi_dmax_reqbnk1_s cn66xx;
+        struct cvmx_dpi_dmax_reqbnk1_s cn68xx;
+        struct cvmx_dpi_dmax_reqbnk1_s cn68xxp1;
+};
+
+union cvmx_dpi_dma_control {
+        uint64_t u64;
+        struct cvmx_dpi_dma_control_s {
+                uint64_t reserved_62_63:2;
+                uint64_t dici_mode:1;
+                uint64_t pkt_en1:1;
+                uint64_t ffp_dis:1;
+                uint64_t commit_mode:1;
+                uint64_t pkt_hp:1;
+                uint64_t pkt_en:1;
+                uint64_t reserved_54_55:2;
+                uint64_t dma_enb:6;
+                uint64_t reserved_34_47:14;
+                uint64_t b0_lend:1;
+                uint64_t dwb_denb:1;
+                uint64_t dwb_ichk:9;
+                uint64_t fpa_que:3;
+                uint64_t o_add1:1;
+                uint64_t o_ro:1;
+                uint64_t o_ns:1;
+                uint64_t o_es:2;
+                uint64_t o_mode:1;
+                uint64_t reserved_0_13:14;
+        } s;
+        struct cvmx_dpi_dma_control_s cn61xx;
+        struct cvmx_dpi_dma_control_cn63xx {
+                uint64_t reserved_61_63:3;
+                uint64_t pkt_en1:1;
+                uint64_t ffp_dis:1;
+                uint64_t commit_mode:1;
+                uint64_t pkt_hp:1;
+                uint64_t pkt_en:1;
+                uint64_t reserved_54_55:2;
+                uint64_t dma_enb:6;
+                uint64_t reserved_34_47:14;
+                uint64_t b0_lend:1;
+                uint64_t dwb_denb:1;
+                uint64_t dwb_ichk:9;
+                uint64_t fpa_que:3;
+                uint64_t o_add1:1;
+                uint64_t o_ro:1;
+                uint64_t o_ns:1;
+                uint64_t o_es:2;
+                uint64_t o_mode:1;
+                uint64_t reserved_0_13:14;
+        } cn63xx;
+        struct cvmx_dpi_dma_control_cn63xxp1 {
+                uint64_t reserved_59_63:5;
+                uint64_t commit_mode:1;
+                uint64_t pkt_hp:1;
+                uint64_t pkt_en:1;
+                uint64_t reserved_54_55:2;
+                uint64_t dma_enb:6;
+                uint64_t reserved_34_47:14;
+                uint64_t b0_lend:1;
+                uint64_t dwb_denb:1;
+                uint64_t dwb_ichk:9;
+                uint64_t fpa_que:3;
+                uint64_t o_add1:1;
+                uint64_t o_ro:1;
+                uint64_t o_ns:1;
+                uint64_t o_es:2;
+                uint64_t o_mode:1;
+                uint64_t reserved_0_13:14;
+        } cn63xxp1;
+        struct cvmx_dpi_dma_control_cn63xx cn66xx;
+        struct cvmx_dpi_dma_control_s cn68xx;
+        struct cvmx_dpi_dma_control_cn63xx cn68xxp1;
+};
+
+union cvmx_dpi_dma_engx_en {
+        uint64_t u64;
+        struct cvmx_dpi_dma_engx_en_s {
+                uint64_t reserved_8_63:56;
+                uint64_t qen:8;
+        } s;
+        struct cvmx_dpi_dma_engx_en_s cn61xx;
+        struct cvmx_dpi_dma_engx_en_s cn63xx;
+        struct cvmx_dpi_dma_engx_en_s cn63xxp1;
+        struct cvmx_dpi_dma_engx_en_s cn66xx;
+        struct cvmx_dpi_dma_engx_en_s cn68xx;
+        struct cvmx_dpi_dma_engx_en_s cn68xxp1;
+};
+
+union cvmx_dpi_dma_ppx_cnt {
+        uint64_t u64;
+        struct cvmx_dpi_dma_ppx_cnt_s {
+                uint64_t reserved_16_63:48;
+                uint64_t cnt:16;
+        } s;
+        struct cvmx_dpi_dma_ppx_cnt_s cn61xx;
+        struct cvmx_dpi_dma_ppx_cnt_s cn68xx;
+};
+
+union cvmx_dpi_engx_buf {
+        uint64_t u64;
+        struct cvmx_dpi_engx_buf_s {
+                uint64_t reserved_37_63:27;
+                uint64_t compblks:5;
+                uint64_t reserved_9_31:23;
+                uint64_t base:5;
+                uint64_t blks:4;
+        } s;
+        struct cvmx_dpi_engx_buf_s cn61xx;
+        struct cvmx_dpi_engx_buf_cn63xx {
+                uint64_t reserved_8_63:56;
+                uint64_t base:4;
+                uint64_t blks:4;
+        } cn63xx;
+        struct cvmx_dpi_engx_buf_cn63xx cn63xxp1;
+        struct cvmx_dpi_engx_buf_s cn66xx;
+        struct cvmx_dpi_engx_buf_s cn68xx;
+        struct cvmx_dpi_engx_buf_s cn68xxp1;
+};
+
+union cvmx_dpi_info_reg {
+        uint64_t u64;
+        struct cvmx_dpi_info_reg_s {
+                uint64_t reserved_8_63:56;
+                uint64_t ffp:4;
+                uint64_t reserved_2_3:2;
+                uint64_t ncb:1;
+                uint64_t rsl:1;
+        } s;
+        struct cvmx_dpi_info_reg_s cn61xx;
+        struct cvmx_dpi_info_reg_s cn63xx;
+        struct cvmx_dpi_info_reg_cn63xxp1 {
+                uint64_t reserved_2_63:62;
+                uint64_t ncb:1;
+                uint64_t rsl:1;
+        } cn63xxp1;
+        struct cvmx_dpi_info_reg_s cn66xx;
+        struct cvmx_dpi_info_reg_s cn68xx;
+        struct cvmx_dpi_info_reg_s cn68xxp1;
+};
+
+union cvmx_dpi_int_en {
+        uint64_t u64;
+        struct cvmx_dpi_int_en_s {
+                uint64_t reserved_28_63:36;
+                uint64_t sprt3_rst:1;
+                uint64_t sprt2_rst:1;
+                uint64_t sprt1_rst:1;
+                uint64_t sprt0_rst:1;
+                uint64_t reserved_23_23:1;
+                uint64_t req_badfil:1;
+                uint64_t req_inull:1;
+                uint64_t req_anull:1;
+                uint64_t req_undflw:1;
+                uint64_t req_ovrflw:1;
+                uint64_t req_badlen:1;
+                uint64_t req_badadr:1;
+                uint64_t dmadbo:8;
+                uint64_t reserved_2_7:6;
+                uint64_t nfovr:1;
+                uint64_t nderr:1;
+        } s;
+        struct cvmx_dpi_int_en_s cn61xx;
+        struct cvmx_dpi_int_en_cn63xx {
+                uint64_t reserved_26_63:38;
+                uint64_t sprt1_rst:1;
+                uint64_t sprt0_rst:1;
+                uint64_t reserved_23_23:1;
+                uint64_t req_badfil:1;
+                uint64_t req_inull:1;
+                uint64_t req_anull:1;
+                uint64_t req_undflw:1;
+                uint64_t req_ovrflw:1;
+                uint64_t req_badlen:1;
+                uint64_t req_badadr:1;
+                uint64_t dmadbo:8;
+                uint64_t reserved_2_7:6;
+                uint64_t nfovr:1;
+                uint64_t nderr:1;
+        } cn63xx;
+        struct cvmx_dpi_int_en_cn63xx cn63xxp1;
+        struct cvmx_dpi_int_en_s cn66xx;
+        struct cvmx_dpi_int_en_cn63xx cn68xx;
+        struct cvmx_dpi_int_en_cn63xx cn68xxp1;
+};
+
+union cvmx_dpi_int_reg {
+        uint64_t u64;
+        struct cvmx_dpi_int_reg_s {
+                uint64_t reserved_28_63:36;
+                uint64_t sprt3_rst:1;
+                uint64_t sprt2_rst:1;
+                uint64_t sprt1_rst:1;
+                uint64_t sprt0_rst:1;
+                uint64_t reserved_23_23:1;
+                uint64_t req_badfil:1;
+                uint64_t req_inull:1;
+                uint64_t req_anull:1;
+                uint64_t req_undflw:1;
+                uint64_t req_ovrflw:1;
+                uint64_t req_badlen:1;
+                uint64_t req_badadr:1;
+                uint64_t dmadbo:8;
+                uint64_t reserved_2_7:6;
+                uint64_t nfovr:1;
+                uint64_t nderr:1;
+        } s;
+        struct cvmx_dpi_int_reg_s cn61xx;
+        struct cvmx_dpi_int_reg_cn63xx {
+                uint64_t reserved_26_63:38;
+                uint64_t sprt1_rst:1;
+                uint64_t sprt0_rst:1;
+                uint64_t reserved_23_23:1;
+                uint64_t req_badfil:1;
+                uint64_t req_inull:1;
+                uint64_t req_anull:1;
+                uint64_t req_undflw:1;
+                uint64_t req_ovrflw:1;
+                uint64_t req_badlen:1;
+                uint64_t req_badadr:1;
+                uint64_t dmadbo:8;
+                uint64_t reserved_2_7:6;
+                uint64_t nfovr:1;
+                uint64_t nderr:1;
+        } cn63xx;
+        struct cvmx_dpi_int_reg_cn63xx cn63xxp1;
+        struct cvmx_dpi_int_reg_s cn66xx;
+        struct cvmx_dpi_int_reg_cn63xx cn68xx;
+        struct cvmx_dpi_int_reg_cn63xx cn68xxp1;
+};
+
+union cvmx_dpi_ncbx_cfg {
+        uint64_t u64;
+        struct cvmx_dpi_ncbx_cfg_s {
+                uint64_t reserved_6_63:58;
+                uint64_t molr:6;
+        } s;
+        struct cvmx_dpi_ncbx_cfg_s cn61xx;
+        struct cvmx_dpi_ncbx_cfg_s cn66xx;
+        struct cvmx_dpi_ncbx_cfg_s cn68xx;
+};
+
+union cvmx_dpi_pint_info {
+        uint64_t u64;
+        struct cvmx_dpi_pint_info_s {
+                uint64_t reserved_14_63:50;
+                uint64_t iinfo:6;
+                uint64_t reserved_6_7:2;
+                uint64_t sinfo:6;
+        } s;
+        struct cvmx_dpi_pint_info_s cn61xx;
+        struct cvmx_dpi_pint_info_s cn63xx;
+        struct cvmx_dpi_pint_info_s cn63xxp1;
+        struct cvmx_dpi_pint_info_s cn66xx;
+        struct cvmx_dpi_pint_info_s cn68xx;
+        struct cvmx_dpi_pint_info_s cn68xxp1;
+};
+
+union cvmx_dpi_pkt_err_rsp {
+        uint64_t u64;
+        struct cvmx_dpi_pkt_err_rsp_s {
+                uint64_t reserved_1_63:63;
+                uint64_t pkterr:1;
+        } s;
+        struct cvmx_dpi_pkt_err_rsp_s cn61xx;
+        struct cvmx_dpi_pkt_err_rsp_s cn63xx;
+        struct cvmx_dpi_pkt_err_rsp_s cn63xxp1;
+        struct cvmx_dpi_pkt_err_rsp_s cn66xx;
+        struct cvmx_dpi_pkt_err_rsp_s cn68xx;
+        struct cvmx_dpi_pkt_err_rsp_s cn68xxp1;
+};
+
+union cvmx_dpi_req_err_rsp {
+        uint64_t u64;
+        struct cvmx_dpi_req_err_rsp_s {
+                uint64_t reserved_8_63:56;
+                uint64_t qerr:8;
+        } s;
+        struct cvmx_dpi_req_err_rsp_s cn61xx;
+        struct cvmx_dpi_req_err_rsp_s cn63xx;
+        struct cvmx_dpi_req_err_rsp_s cn63xxp1;
+        struct cvmx_dpi_req_err_rsp_s cn66xx;
+        struct cvmx_dpi_req_err_rsp_s cn68xx;
+        struct cvmx_dpi_req_err_rsp_s cn68xxp1;
+};
+
+union cvmx_dpi_req_err_rsp_en {
+        uint64_t u64;
+        struct cvmx_dpi_req_err_rsp_en_s {
+                uint64_t reserved_8_63:56;
+                uint64_t en:8;
+        } s;
+        struct cvmx_dpi_req_err_rsp_en_s cn61xx;
+        struct cvmx_dpi_req_err_rsp_en_s cn63xx;
+        struct cvmx_dpi_req_err_rsp_en_s cn63xxp1;
+        struct cvmx_dpi_req_err_rsp_en_s cn66xx;
+        struct cvmx_dpi_req_err_rsp_en_s cn68xx;
+        struct cvmx_dpi_req_err_rsp_en_s cn68xxp1;
+};
+
+union cvmx_dpi_req_err_rst {
+        uint64_t u64;
+        struct cvmx_dpi_req_err_rst_s {
+                uint64_t reserved_8_63:56;
+                uint64_t qerr:8;
+        } s;
+        struct cvmx_dpi_req_err_rst_s cn61xx;
+        struct cvmx_dpi_req_err_rst_s cn63xx;
+        struct cvmx_dpi_req_err_rst_s cn63xxp1;
+        struct cvmx_dpi_req_err_rst_s cn66xx;
+        struct cvmx_dpi_req_err_rst_s cn68xx;
+        struct cvmx_dpi_req_err_rst_s cn68xxp1;
+};
+
+union cvmx_dpi_req_err_rst_en {
+        uint64_t u64;
+        struct cvmx_dpi_req_err_rst_en_s {
+                uint64_t reserved_8_63:56;
+                uint64_t en:8;
+        } s;
+        struct cvmx_dpi_req_err_rst_en_s cn61xx;
+        struct cvmx_dpi_req_err_rst_en_s cn63xx;
+        struct cvmx_dpi_req_err_rst_en_s cn63xxp1;
+        struct cvmx_dpi_req_err_rst_en_s cn66xx;
+        struct cvmx_dpi_req_err_rst_en_s cn68xx;
+        struct cvmx_dpi_req_err_rst_en_s cn68xxp1;
+};
+
+union cvmx_dpi_req_err_skip_comp {
+        uint64_t u64;
+        struct cvmx_dpi_req_err_skip_comp_s {
+                uint64_t reserved_24_63:40;
+                uint64_t en_rst:8;
+                uint64_t reserved_8_15:8;
+                uint64_t en_rsp:8;
+        } s;
+        struct cvmx_dpi_req_err_skip_comp_s cn61xx;
+        struct cvmx_dpi_req_err_skip_comp_s cn66xx;
+        struct cvmx_dpi_req_err_skip_comp_s cn68xx;
+        struct cvmx_dpi_req_err_skip_comp_s cn68xxp1;
+};
+
+union cvmx_dpi_req_gbl_en {
+        uint64_t u64;
+        struct cvmx_dpi_req_gbl_en_s {
+                uint64_t reserved_8_63:56;
+                uint64_t qen:8;
+        } s;
+        struct cvmx_dpi_req_gbl_en_s cn61xx;
+        struct cvmx_dpi_req_gbl_en_s cn63xx;
+        struct cvmx_dpi_req_gbl_en_s cn63xxp1;
+        struct cvmx_dpi_req_gbl_en_s cn66xx;
+        struct cvmx_dpi_req_gbl_en_s cn68xx;
+        struct cvmx_dpi_req_gbl_en_s cn68xxp1;
+};
+
+union cvmx_dpi_sli_prtx_cfg {
+        uint64_t u64;
+        struct cvmx_dpi_sli_prtx_cfg_s {
+                uint64_t reserved_25_63:39;
+                uint64_t halt:1;
+                uint64_t qlm_cfg:4;
+                uint64_t reserved_17_19:3;
+                uint64_t rd_mode:1;
+                uint64_t reserved_14_15:2;
+                uint64_t molr:6;
+                uint64_t mps_lim:1;
+                uint64_t reserved_5_6:2;
+                uint64_t mps:1;
+                uint64_t mrrs_lim:1;
+                uint64_t reserved_2_2:1;
+                uint64_t mrrs:2;
+        } s;
+        struct cvmx_dpi_sli_prtx_cfg_s cn61xx;
+        struct cvmx_dpi_sli_prtx_cfg_cn63xx {
+                uint64_t reserved_25_63:39;
+                uint64_t halt:1;
+                uint64_t reserved_21_23:3;
+                uint64_t qlm_cfg:1;
+                uint64_t reserved_17_19:3;
+                uint64_t rd_mode:1;
+                uint64_t reserved_14_15:2;
+                uint64_t molr:6;
+                uint64_t mps_lim:1;
+                uint64_t reserved_5_6:2;
+                uint64_t mps:1;
+                uint64_t mrrs_lim:1;
+                uint64_t reserved_2_2:1;
+                uint64_t mrrs:2;
+        } cn63xx;
+        struct cvmx_dpi_sli_prtx_cfg_cn63xx cn63xxp1;
+        struct cvmx_dpi_sli_prtx_cfg_s cn66xx;
+        struct cvmx_dpi_sli_prtx_cfg_cn63xx cn68xx;
+        struct cvmx_dpi_sli_prtx_cfg_cn63xx cn68xxp1;
+};
+
+union cvmx_dpi_sli_prtx_err {
+        uint64_t u64;
+        struct cvmx_dpi_sli_prtx_err_s {
+                uint64_t addr:61;
+                uint64_t reserved_0_2:3;
+        } s;
+        struct cvmx_dpi_sli_prtx_err_s cn61xx;
+        struct cvmx_dpi_sli_prtx_err_s cn63xx;
+        struct cvmx_dpi_sli_prtx_err_s cn63xxp1;
+        struct cvmx_dpi_sli_prtx_err_s cn66xx;
+        struct cvmx_dpi_sli_prtx_err_s cn68xx;
+        struct cvmx_dpi_sli_prtx_err_s cn68xxp1;
+};
+
+union cvmx_dpi_sli_prtx_err_info {
+        uint64_t u64;
+        struct cvmx_dpi_sli_prtx_err_info_s {
+                uint64_t reserved_9_63:55;
+                uint64_t lock:1;
+                uint64_t reserved_5_7:3;
+                uint64_t type:1;
+                uint64_t reserved_3_3:1;
+                uint64_t reqq:3;
+        } s;
+        struct cvmx_dpi_sli_prtx_err_info_s cn61xx;
+        struct cvmx_dpi_sli_prtx_err_info_s cn63xx;
+        struct cvmx_dpi_sli_prtx_err_info_s cn63xxp1;
+        struct cvmx_dpi_sli_prtx_err_info_s cn66xx;
+        struct cvmx_dpi_sli_prtx_err_info_s cn68xx;
+        struct cvmx_dpi_sli_prtx_err_info_s cn68xxp1;
+};
+
+#endif
diff --git a/drivers/staging/octeon/cvmx-fau.h b/arch/mips/include/asm/octeon/cvmx-fau.h
index a6939fc8ba1..a6939fc8ba1 100644
--- a/drivers/staging/octeon/cvmx-fau.h
+++ b/arch/mips/include/asm/octeon/cvmx-fau.h
diff --git a/drivers/staging/octeon/cvmx-fpa-defs.h b/arch/mips/include/asm/octeon/cvmx-fpa-defs.h
index bf5546b9011..bf5546b9011 100644
--- a/drivers/staging/octeon/cvmx-fpa-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-fpa-defs.h
diff --git a/drivers/staging/octeon/cvmx-fpa.h b/arch/mips/include/asm/octeon/cvmx-fpa.h
index 1f04f965873..1f04f965873 100644
--- a/drivers/staging/octeon/cvmx-fpa.h
+++ b/arch/mips/include/asm/octeon/cvmx-fpa.h
diff --git a/drivers/staging/octeon/cvmx-gmxx-defs.h b/arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
index 946a43a73fd..946a43a73fd 100644
--- a/drivers/staging/octeon/cvmx-gmxx-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
diff --git a/drivers/staging/octeon/cvmx-helper-board.h b/arch/mips/include/asm/octeon/cvmx-helper-board.h
index b465bec4355..88527fa835c 100644
--- a/drivers/staging/octeon/cvmx-helper-board.h
+++ b/arch/mips/include/asm/octeon/cvmx-helper-board.h
@@ -44,6 +44,12 @@ typedef enum {
         set_phy_link_flags_flow_control_mask = 0x3 << 1,        /* Mask for 2 bit wide flow control field */
 } cvmx_helper_board_set_phy_link_flags_types_t;
 
+/*
+ * Fake IPD port, the RGMII/MII interface may use different PHY, use
+ * this macro to return appropriate MIX address to read the PHY.
+ */
+#define CVMX_HELPER_BOARD_MGMT_IPD_PORT     -10
+
 /**
  * cvmx_override_board_link_get(int ipd_port) is a function
  * pointer. It is meant to allow customization of the process of
diff --git a/drivers/staging/octeon/cvmx-helper-fpa.h b/arch/mips/include/asm/octeon/cvmx-helper-fpa.h
index 5ff8c93198d..5ff8c93198d 100644
--- a/drivers/staging/octeon/cvmx-helper-fpa.h
+++ b/arch/mips/include/asm/octeon/cvmx-helper-fpa.h
diff --git a/drivers/staging/octeon/cvmx-helper-loop.h b/arch/mips/include/asm/octeon/cvmx-helper-loop.h
index e646a6ccce7..077f0e9d3b2 100644
--- a/drivers/staging/octeon/cvmx-helper-loop.h
+++ b/arch/mips/include/asm/octeon/cvmx-helper-loop.h
@@ -44,6 +44,7 @@
  * Returns Number of ports on the interface. Zero to disable.
  */
 extern int __cvmx_helper_loop_probe(int interface);
+static inline int __cvmx_helper_loop_enumerate(int interface) {return 4; }
 
 /**
  * Bringup and enable a LOOP interface. After this call packet
diff --git a/drivers/staging/octeon/cvmx-helper-npi.h b/arch/mips/include/asm/octeon/cvmx-helper-npi.h
index 908e7b08c21..8df4c7fafdb 100644
--- a/drivers/staging/octeon/cvmx-helper-npi.h
+++ b/arch/mips/include/asm/octeon/cvmx-helper-npi.h
@@ -45,6 +45,7 @@
  * Returns Number of ports on the interface. Zero to disable.
  */
 extern int __cvmx_helper_npi_probe(int interface);
+#define __cvmx_helper_npi_enumerate __cvmx_helper_npi_probe
 
 /**
  * Bringup and enable a NPI interface. After this call packet
diff --git a/drivers/staging/octeon/cvmx-helper-rgmii.h b/arch/mips/include/asm/octeon/cvmx-helper-rgmii.h
index ea2652604a5..78295ba0050 100644
--- a/drivers/staging/octeon/cvmx-helper-rgmii.h
+++ b/arch/mips/include/asm/octeon/cvmx-helper-rgmii.h
@@ -43,6 +43,7 @@
  * Returns Number of RGMII/GMII/MII ports (0-4).
  */
 extern int __cvmx_helper_rgmii_probe(int interface);
+#define __cvmx_helper_rgmii_enumerate __cvmx_helper_rgmii_probe
 
 /**
  * Put an RGMII interface in loopback mode. Internal packets sent
diff --git a/drivers/staging/octeon/cvmx-helper-sgmii.h b/arch/mips/include/asm/octeon/cvmx-helper-sgmii.h
index 19b48d60857..9a9b6c103ed 100644
--- a/drivers/staging/octeon/cvmx-helper-sgmii.h
+++ b/arch/mips/include/asm/octeon/cvmx-helper-sgmii.h
@@ -45,6 +45,7 @@
  * Returns Number of ports on the interface. Zero to disable.
  */
 extern int __cvmx_helper_sgmii_probe(int interface);
+extern int __cvmx_helper_sgmii_enumerate(int interface);
 
 /**
  * Bringup and enable a SGMII interface. After this call packet
diff --git a/drivers/staging/octeon/cvmx-helper-spi.h b/arch/mips/include/asm/octeon/cvmx-helper-spi.h
index 69bac036d10..9f1c6b968f9 100644
--- a/drivers/staging/octeon/cvmx-helper-spi.h
+++ b/arch/mips/include/asm/octeon/cvmx-helper-spi.h
@@ -42,6 +42,7 @@
  * Returns Number of ports on the interface. Zero to disable.
  */
 extern int __cvmx_helper_spi_probe(int interface);
+extern int __cvmx_helper_spi_enumerate(int interface);
 
 /**
  * Bringup and enable a SPI interface. After this call packet I/O
diff --git a/drivers/staging/octeon/cvmx-helper-util.h b/arch/mips/include/asm/octeon/cvmx-helper-util.h
index 6a6e52fc22c..6a6e52fc22c 100644
--- a/drivers/staging/octeon/cvmx-helper-util.h
+++ b/arch/mips/include/asm/octeon/cvmx-helper-util.h
diff --git a/drivers/staging/octeon/cvmx-helper-xaui.h b/arch/mips/include/asm/octeon/cvmx-helper-xaui.h
index 4b4db2f93cd..f6fbc4f45b5 100644
--- a/drivers/staging/octeon/cvmx-helper-xaui.h
+++ b/arch/mips/include/asm/octeon/cvmx-helper-xaui.h
@@ -45,6 +45,7 @@
  * Returns Number of ports on the interface. Zero to disable.
  */
 extern int __cvmx_helper_xaui_probe(int interface);
+extern int __cvmx_helper_xaui_enumerate(int interface);
 
 /**
  * Bringup and enable a XAUI interface. After this call packet
diff --git a/drivers/staging/octeon/cvmx-helper.h b/arch/mips/include/asm/octeon/cvmx-helper.h
index 51916f3cc40..3169cd79f2a 100644
--- a/drivers/staging/octeon/cvmx-helper.h
+++ b/arch/mips/include/asm/octeon/cvmx-helper.h
@@ -207,6 +207,7 @@ extern int cvmx_helper_link_set(int ipd_port,
  * Returns Zero on success, negative on failure
  */
 extern int cvmx_helper_interface_probe(int interface);
+extern int cvmx_helper_interface_enumerate(int interface);
 
 /**
  * Configure a port for internal and/or external loopback. Internal loopback
diff --git a/drivers/staging/octeon/cvmx-ipd.h b/arch/mips/include/asm/octeon/cvmx-ipd.h
index 115a552c5c7..115a552c5c7 100644
--- a/drivers/staging/octeon/cvmx-ipd.h
+++ b/arch/mips/include/asm/octeon/cvmx-ipd.h
diff --git a/drivers/staging/octeon/cvmx-mdio.h b/arch/mips/include/asm/octeon/cvmx-mdio.h
index d88ab8d8e37..d88ab8d8e37 100644
--- a/drivers/staging/octeon/cvmx-mdio.h
+++ b/arch/mips/include/asm/octeon/cvmx-mdio.h
diff --git a/arch/mips/include/asm/octeon/cvmx-mio-defs.h b/arch/mips/include/asm/octeon/cvmx-mio-defs.h
index 52b14a333ad..b1774126736 100644
--- a/arch/mips/include/asm/octeon/cvmx-mio-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-mio-defs.h
@@ -43,6 +43,22 @@
 #define CVMX_MIO_BOOT_REG_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001180000000000ull) + ((offset) & 7) * 8)
 #define CVMX_MIO_BOOT_REG_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001180000000040ull) + ((offset) & 7) * 8)
 #define CVMX_MIO_BOOT_THR (CVMX_ADD_IO_SEG(0x00011800000000B0ull))
+#define CVMX_MIO_EMM_BUF_DAT (CVMX_ADD_IO_SEG(0x00011800000020E8ull))
+#define CVMX_MIO_EMM_BUF_IDX (CVMX_ADD_IO_SEG(0x00011800000020E0ull))
+#define CVMX_MIO_EMM_CFG (CVMX_ADD_IO_SEG(0x0001180000002000ull))
+#define CVMX_MIO_EMM_CMD (CVMX_ADD_IO_SEG(0x0001180000002058ull))
+#define CVMX_MIO_EMM_DMA (CVMX_ADD_IO_SEG(0x0001180000002050ull))
+#define CVMX_MIO_EMM_INT (CVMX_ADD_IO_SEG(0x0001180000002078ull))
+#define CVMX_MIO_EMM_INT_EN (CVMX_ADD_IO_SEG(0x0001180000002080ull))
+#define CVMX_MIO_EMM_MODEX(offset) (CVMX_ADD_IO_SEG(0x0001180000002008ull) + ((offset) & 3) * 8)
+#define CVMX_MIO_EMM_RCA (CVMX_ADD_IO_SEG(0x00011800000020A0ull))
+#define CVMX_MIO_EMM_RSP_HI (CVMX_ADD_IO_SEG(0x0001180000002070ull))
+#define CVMX_MIO_EMM_RSP_LO (CVMX_ADD_IO_SEG(0x0001180000002068ull))
+#define CVMX_MIO_EMM_RSP_STS (CVMX_ADD_IO_SEG(0x0001180000002060ull))
+#define CVMX_MIO_EMM_SAMPLE (CVMX_ADD_IO_SEG(0x0001180000002090ull))
+#define CVMX_MIO_EMM_STS_MASK (CVMX_ADD_IO_SEG(0x0001180000002098ull))
+#define CVMX_MIO_EMM_SWITCH (CVMX_ADD_IO_SEG(0x0001180000002048ull))
+#define CVMX_MIO_EMM_WDOG (CVMX_ADD_IO_SEG(0x0001180000002088ull))
 #define CVMX_MIO_FUS_BNK_DATX(offset) (CVMX_ADD_IO_SEG(0x0001180000001520ull) + ((offset) & 3) * 8)
 #define CVMX_MIO_FUS_DAT0 (CVMX_ADD_IO_SEG(0x0001180000001400ull))
 #define CVMX_MIO_FUS_DAT1 (CVMX_ADD_IO_SEG(0x0001180000001408ull))
@@ -60,6 +76,7 @@
 #define CVMX_MIO_FUS_REPAIR_RES2 (CVMX_ADD_IO_SEG(0x0001180000001568ull))
 #define CVMX_MIO_FUS_SPR_REPAIR_RES (CVMX_ADD_IO_SEG(0x0001180000001548ull))
 #define CVMX_MIO_FUS_SPR_REPAIR_SUM (CVMX_ADD_IO_SEG(0x0001180000001540ull))
+#define CVMX_MIO_FUS_TGG (CVMX_ADD_IO_SEG(0x0001180000001428ull))
 #define CVMX_MIO_FUS_UNLOCK (CVMX_ADD_IO_SEG(0x0001180000001578ull))
 #define CVMX_MIO_FUS_WADR (CVMX_ADD_IO_SEG(0x0001180000001508ull))
 #define CVMX_MIO_GPIO_COMP (CVMX_ADD_IO_SEG(0x00011800000000C8ull))
@@ -68,14 +85,25 @@
 #define CVMX_MIO_NDF_DMA_INT_EN (CVMX_ADD_IO_SEG(0x0001180000000178ull))
 #define CVMX_MIO_PLL_CTL (CVMX_ADD_IO_SEG(0x0001180000001448ull))
 #define CVMX_MIO_PLL_SETTING (CVMX_ADD_IO_SEG(0x0001180000001440ull))
+#define CVMX_MIO_PTP_CKOUT_HI_INCR (CVMX_ADD_IO_SEG(0x0001070000000F40ull))
+#define CVMX_MIO_PTP_CKOUT_LO_INCR (CVMX_ADD_IO_SEG(0x0001070000000F48ull))
+#define CVMX_MIO_PTP_CKOUT_THRESH_HI (CVMX_ADD_IO_SEG(0x0001070000000F38ull))
+#define CVMX_MIO_PTP_CKOUT_THRESH_LO (CVMX_ADD_IO_SEG(0x0001070000000F30ull))
 #define CVMX_MIO_PTP_CLOCK_CFG (CVMX_ADD_IO_SEG(0x0001070000000F00ull))
 #define CVMX_MIO_PTP_CLOCK_COMP (CVMX_ADD_IO_SEG(0x0001070000000F18ull))
 #define CVMX_MIO_PTP_CLOCK_HI (CVMX_ADD_IO_SEG(0x0001070000000F10ull))
 #define CVMX_MIO_PTP_CLOCK_LO (CVMX_ADD_IO_SEG(0x0001070000000F08ull))
 #define CVMX_MIO_PTP_EVT_CNT (CVMX_ADD_IO_SEG(0x0001070000000F28ull))
+#define CVMX_MIO_PTP_PPS_HI_INCR (CVMX_ADD_IO_SEG(0x0001070000000F60ull))
+#define CVMX_MIO_PTP_PPS_LO_INCR (CVMX_ADD_IO_SEG(0x0001070000000F68ull))
+#define CVMX_MIO_PTP_PPS_THRESH_HI (CVMX_ADD_IO_SEG(0x0001070000000F58ull))
+#define CVMX_MIO_PTP_PPS_THRESH_LO (CVMX_ADD_IO_SEG(0x0001070000000F50ull))
 #define CVMX_MIO_PTP_TIMESTAMP (CVMX_ADD_IO_SEG(0x0001070000000F20ull))
+#define CVMX_MIO_QLMX_CFG(offset) (CVMX_ADD_IO_SEG(0x0001180000001590ull) + ((offset) & 7) * 8)
 #define CVMX_MIO_RST_BOOT (CVMX_ADD_IO_SEG(0x0001180000001600ull))
 #define CVMX_MIO_RST_CFG (CVMX_ADD_IO_SEG(0x0001180000001610ull))
+#define CVMX_MIO_RST_CKILL (CVMX_ADD_IO_SEG(0x0001180000001638ull))
+#define CVMX_MIO_RST_CNTLX(offset) (CVMX_ADD_IO_SEG(0x0001180000001648ull) + ((offset) & 3) * 8)
 #define CVMX_MIO_RST_CTLX(offset) (CVMX_ADD_IO_SEG(0x0001180000001618ull) + ((offset) & 1) * 8)
 #define CVMX_MIO_RST_DELAY (CVMX_ADD_IO_SEG(0x0001180000001608ull))
 #define CVMX_MIO_RST_INT (CVMX_ADD_IO_SEG(0x0001180000001628ull))
@@ -183,11 +211,21 @@ union cvmx_mio_boot_bist_stat {
         struct cvmx_mio_boot_bist_stat_cn52xxp1 cn56xxp1;
         struct cvmx_mio_boot_bist_stat_cn38xx cn58xx;
         struct cvmx_mio_boot_bist_stat_cn38xx cn58xxp1;
+        struct cvmx_mio_boot_bist_stat_cn61xx {
+                uint64_t reserved_12_63:52;
+                uint64_t stat:12;
+        } cn61xx;
         struct cvmx_mio_boot_bist_stat_cn63xx {
                 uint64_t reserved_9_63:55;
                 uint64_t stat:9;
         } cn63xx;
         struct cvmx_mio_boot_bist_stat_cn63xx cn63xxp1;
+        struct cvmx_mio_boot_bist_stat_cn66xx {
+                uint64_t reserved_10_63:54;
+                uint64_t stat:10;
+        } cn66xx;
+        struct cvmx_mio_boot_bist_stat_cn66xx cn68xx;
+        struct cvmx_mio_boot_bist_stat_cn66xx cn68xxp1;
 };
 
 union cvmx_mio_boot_comp {
@@ -204,12 +242,16 @@ union cvmx_mio_boot_comp {
         struct cvmx_mio_boot_comp_cn50xx cn52xxp1;
         struct cvmx_mio_boot_comp_cn50xx cn56xx;
         struct cvmx_mio_boot_comp_cn50xx cn56xxp1;
-        struct cvmx_mio_boot_comp_cn63xx {
+        struct cvmx_mio_boot_comp_cn61xx {
                 uint64_t reserved_12_63:52;
                 uint64_t pctl:6;
                 uint64_t nctl:6;
-        } cn63xx;
-        struct cvmx_mio_boot_comp_cn63xx cn63xxp1;
+        } cn61xx;
+        struct cvmx_mio_boot_comp_cn61xx cn63xx;
+        struct cvmx_mio_boot_comp_cn61xx cn63xxp1;
+        struct cvmx_mio_boot_comp_cn61xx cn66xx;
+        struct cvmx_mio_boot_comp_cn61xx cn68xx;
+        struct cvmx_mio_boot_comp_cn61xx cn68xxp1;
 };
 
 union cvmx_mio_boot_dma_cfgx {
@@ -230,8 +272,12 @@ union cvmx_mio_boot_dma_cfgx {
         struct cvmx_mio_boot_dma_cfgx_s cn52xxp1;
         struct cvmx_mio_boot_dma_cfgx_s cn56xx;
         struct cvmx_mio_boot_dma_cfgx_s cn56xxp1;
+        struct cvmx_mio_boot_dma_cfgx_s cn61xx;
         struct cvmx_mio_boot_dma_cfgx_s cn63xx;
         struct cvmx_mio_boot_dma_cfgx_s cn63xxp1;
+        struct cvmx_mio_boot_dma_cfgx_s cn66xx;
+        struct cvmx_mio_boot_dma_cfgx_s cn68xx;
+        struct cvmx_mio_boot_dma_cfgx_s cn68xxp1;
 };
 
 union cvmx_mio_boot_dma_intx {
@@ -245,8 +291,12 @@ union cvmx_mio_boot_dma_intx {
         struct cvmx_mio_boot_dma_intx_s cn52xxp1;
         struct cvmx_mio_boot_dma_intx_s cn56xx;
         struct cvmx_mio_boot_dma_intx_s cn56xxp1;
+        struct cvmx_mio_boot_dma_intx_s cn61xx;
         struct cvmx_mio_boot_dma_intx_s cn63xx;
         struct cvmx_mio_boot_dma_intx_s cn63xxp1;
+        struct cvmx_mio_boot_dma_intx_s cn66xx;
+        struct cvmx_mio_boot_dma_intx_s cn68xx;
+        struct cvmx_mio_boot_dma_intx_s cn68xxp1;
 };
 
 union cvmx_mio_boot_dma_int_enx {
@@ -260,8 +310,12 @@ union cvmx_mio_boot_dma_int_enx {
         struct cvmx_mio_boot_dma_int_enx_s cn52xxp1;
         struct cvmx_mio_boot_dma_int_enx_s cn56xx;
         struct cvmx_mio_boot_dma_int_enx_s cn56xxp1;
+        struct cvmx_mio_boot_dma_int_enx_s cn61xx;
         struct cvmx_mio_boot_dma_int_enx_s cn63xx;
         struct cvmx_mio_boot_dma_int_enx_s cn63xxp1;
+        struct cvmx_mio_boot_dma_int_enx_s cn66xx;
+        struct cvmx_mio_boot_dma_int_enx_s cn68xx;
+        struct cvmx_mio_boot_dma_int_enx_s cn68xxp1;
 };
 
 union cvmx_mio_boot_dma_timx {
@@ -287,8 +341,12 @@ union cvmx_mio_boot_dma_timx {
         struct cvmx_mio_boot_dma_timx_s cn52xxp1;
         struct cvmx_mio_boot_dma_timx_s cn56xx;
         struct cvmx_mio_boot_dma_timx_s cn56xxp1;
+        struct cvmx_mio_boot_dma_timx_s cn61xx;
         struct cvmx_mio_boot_dma_timx_s cn63xx;
         struct cvmx_mio_boot_dma_timx_s cn63xxp1;
+        struct cvmx_mio_boot_dma_timx_s cn66xx;
+        struct cvmx_mio_boot_dma_timx_s cn68xx;
+        struct cvmx_mio_boot_dma_timx_s cn68xxp1;
 };
 
 union cvmx_mio_boot_err {
@@ -309,8 +367,12 @@ union cvmx_mio_boot_err {
         struct cvmx_mio_boot_err_s cn56xxp1;
         struct cvmx_mio_boot_err_s cn58xx;
         struct cvmx_mio_boot_err_s cn58xxp1;
+        struct cvmx_mio_boot_err_s cn61xx;
         struct cvmx_mio_boot_err_s cn63xx;
         struct cvmx_mio_boot_err_s cn63xxp1;
+        struct cvmx_mio_boot_err_s cn66xx;
+        struct cvmx_mio_boot_err_s cn68xx;
+        struct cvmx_mio_boot_err_s cn68xxp1;
 };
 
 union cvmx_mio_boot_int {
@@ -331,8 +393,12 @@ union cvmx_mio_boot_int {
         struct cvmx_mio_boot_int_s cn56xxp1;
         struct cvmx_mio_boot_int_s cn58xx;
         struct cvmx_mio_boot_int_s cn58xxp1;
+        struct cvmx_mio_boot_int_s cn61xx;
         struct cvmx_mio_boot_int_s cn63xx;
         struct cvmx_mio_boot_int_s cn63xxp1;
+        struct cvmx_mio_boot_int_s cn66xx;
+        struct cvmx_mio_boot_int_s cn68xx;
+        struct cvmx_mio_boot_int_s cn68xxp1;
 };
 
 union cvmx_mio_boot_loc_adr {
@@ -353,8 +419,12 @@ union cvmx_mio_boot_loc_adr {
         struct cvmx_mio_boot_loc_adr_s cn56xxp1;
         struct cvmx_mio_boot_loc_adr_s cn58xx;
         struct cvmx_mio_boot_loc_adr_s cn58xxp1;
+        struct cvmx_mio_boot_loc_adr_s cn61xx;
         struct cvmx_mio_boot_loc_adr_s cn63xx;
         struct cvmx_mio_boot_loc_adr_s cn63xxp1;
+        struct cvmx_mio_boot_loc_adr_s cn66xx;
+        struct cvmx_mio_boot_loc_adr_s cn68xx;
+        struct cvmx_mio_boot_loc_adr_s cn68xxp1;
 };
 
 union cvmx_mio_boot_loc_cfgx {
@@ -377,8 +447,12 @@ union cvmx_mio_boot_loc_cfgx {
         struct cvmx_mio_boot_loc_cfgx_s cn56xxp1;
         struct cvmx_mio_boot_loc_cfgx_s cn58xx;
         struct cvmx_mio_boot_loc_cfgx_s cn58xxp1;
+        struct cvmx_mio_boot_loc_cfgx_s cn61xx;
         struct cvmx_mio_boot_loc_cfgx_s cn63xx;
         struct cvmx_mio_boot_loc_cfgx_s cn63xxp1;
+        struct cvmx_mio_boot_loc_cfgx_s cn66xx;
+        struct cvmx_mio_boot_loc_cfgx_s cn68xx;
+        struct cvmx_mio_boot_loc_cfgx_s cn68xxp1;
 };
 
 union cvmx_mio_boot_loc_dat {
@@ -397,14 +471,19 @@ union cvmx_mio_boot_loc_dat {
         struct cvmx_mio_boot_loc_dat_s cn56xxp1;
         struct cvmx_mio_boot_loc_dat_s cn58xx;
         struct cvmx_mio_boot_loc_dat_s cn58xxp1;
+        struct cvmx_mio_boot_loc_dat_s cn61xx;
         struct cvmx_mio_boot_loc_dat_s cn63xx;
         struct cvmx_mio_boot_loc_dat_s cn63xxp1;
+        struct cvmx_mio_boot_loc_dat_s cn66xx;
+        struct cvmx_mio_boot_loc_dat_s cn68xx;
+        struct cvmx_mio_boot_loc_dat_s cn68xxp1;
 };
 
 union cvmx_mio_boot_pin_defs {
         uint64_t u64;
         struct cvmx_mio_boot_pin_defs_s {
-                uint64_t reserved_16_63:48;
+                uint64_t reserved_32_63:32;
+                uint64_t user1:16;
                 uint64_t ale:1;
                 uint64_t width:1;
                 uint64_t dmack_p2:1;
@@ -412,7 +491,7 @@ union cvmx_mio_boot_pin_defs {
                 uint64_t dmack_p0:1;
                 uint64_t term:2;
                 uint64_t nand:1;
-                uint64_t reserved_0_7:8;
+                uint64_t user0:8;
         } s;
         struct cvmx_mio_boot_pin_defs_cn52xx {
                 uint64_t reserved_16_63:48;
@@ -435,8 +514,23 @@ union cvmx_mio_boot_pin_defs {
                 uint64_t term:2;
                 uint64_t reserved_0_8:9;
         } cn56xx;
+        struct cvmx_mio_boot_pin_defs_cn61xx {
+                uint64_t reserved_32_63:32;
+                uint64_t user1:16;
+                uint64_t ale:1;
+                uint64_t width:1;
+                uint64_t reserved_13_13:1;
+                uint64_t dmack_p1:1;
+                uint64_t dmack_p0:1;
+                uint64_t term:2;
+                uint64_t nand:1;
+                uint64_t user0:8;
+        } cn61xx;
         struct cvmx_mio_boot_pin_defs_cn52xx cn63xx;
         struct cvmx_mio_boot_pin_defs_cn52xx cn63xxp1;
+        struct cvmx_mio_boot_pin_defs_cn52xx cn66xx;
+        struct cvmx_mio_boot_pin_defs_cn52xx cn68xx;
+        struct cvmx_mio_boot_pin_defs_cn52xx cn68xxp1;
 };
 
 union cvmx_mio_boot_reg_cfgx {
@@ -498,8 +592,12 @@ union cvmx_mio_boot_reg_cfgx {
         struct cvmx_mio_boot_reg_cfgx_s cn56xxp1;
         struct cvmx_mio_boot_reg_cfgx_cn30xx cn58xx;
         struct cvmx_mio_boot_reg_cfgx_cn30xx cn58xxp1;
+        struct cvmx_mio_boot_reg_cfgx_s cn61xx;
         struct cvmx_mio_boot_reg_cfgx_s cn63xx;
         struct cvmx_mio_boot_reg_cfgx_s cn63xxp1;
+        struct cvmx_mio_boot_reg_cfgx_s cn66xx;
+        struct cvmx_mio_boot_reg_cfgx_s cn68xx;
+        struct cvmx_mio_boot_reg_cfgx_s cn68xxp1;
 };
 
 union cvmx_mio_boot_reg_timx {
@@ -544,8 +642,12 @@ union cvmx_mio_boot_reg_timx {
         struct cvmx_mio_boot_reg_timx_s cn56xxp1;
         struct cvmx_mio_boot_reg_timx_s cn58xx;
         struct cvmx_mio_boot_reg_timx_s cn58xxp1;
+        struct cvmx_mio_boot_reg_timx_s cn61xx;
         struct cvmx_mio_boot_reg_timx_s cn63xx;
         struct cvmx_mio_boot_reg_timx_s cn63xxp1;
+        struct cvmx_mio_boot_reg_timx_s cn66xx;
+        struct cvmx_mio_boot_reg_timx_s cn68xx;
+        struct cvmx_mio_boot_reg_timx_s cn68xxp1;
 };
 
 union cvmx_mio_boot_thr {
@@ -574,8 +676,231 @@ union cvmx_mio_boot_thr {
         struct cvmx_mio_boot_thr_s cn56xxp1;
         struct cvmx_mio_boot_thr_cn30xx cn58xx;
         struct cvmx_mio_boot_thr_cn30xx cn58xxp1;
+        struct cvmx_mio_boot_thr_s cn61xx;
         struct cvmx_mio_boot_thr_s cn63xx;
         struct cvmx_mio_boot_thr_s cn63xxp1;
+        struct cvmx_mio_boot_thr_s cn66xx;
+        struct cvmx_mio_boot_thr_s cn68xx;
+        struct cvmx_mio_boot_thr_s cn68xxp1;
+};
+
+union cvmx_mio_emm_buf_dat {
+        uint64_t u64;
+        struct cvmx_mio_emm_buf_dat_s {
+                uint64_t dat:64;
+        } s;
+        struct cvmx_mio_emm_buf_dat_s cn61xx;
+};
+
+union cvmx_mio_emm_buf_idx {
+        uint64_t u64;
+        struct cvmx_mio_emm_buf_idx_s {
+                uint64_t reserved_17_63:47;
+                uint64_t inc:1;
+                uint64_t reserved_7_15:9;
+                uint64_t buf_num:1;
+                uint64_t offset:6;
+        } s;
+        struct cvmx_mio_emm_buf_idx_s cn61xx;
+};
+
+union cvmx_mio_emm_cfg {
+        uint64_t u64;
+        struct cvmx_mio_emm_cfg_s {
+                uint64_t reserved_17_63:47;
+                uint64_t boot_fail:1;
+                uint64_t reserved_4_15:12;
+                uint64_t bus_ena:4;
+        } s;
+        struct cvmx_mio_emm_cfg_s cn61xx;
+};
+
+union cvmx_mio_emm_cmd {
+        uint64_t u64;
+        struct cvmx_mio_emm_cmd_s {
+                uint64_t reserved_62_63:2;
+                uint64_t bus_id:2;
+                uint64_t cmd_val:1;
+                uint64_t reserved_56_58:3;
+                uint64_t dbuf:1;
+                uint64_t offset:6;
+                uint64_t reserved_43_48:6;
+                uint64_t ctype_xor:2;
+                uint64_t rtype_xor:3;
+                uint64_t cmd_idx:6;
+                uint64_t arg:32;
+        } s;
+        struct cvmx_mio_emm_cmd_s cn61xx;
+};
+
+union cvmx_mio_emm_dma {
+        uint64_t u64;
+        struct cvmx_mio_emm_dma_s {
+                uint64_t reserved_62_63:2;
+                uint64_t bus_id:2;
+                uint64_t dma_val:1;
+                uint64_t sector:1;
+                uint64_t dat_null:1;
+                uint64_t thres:6;
+                uint64_t rel_wr:1;
+                uint64_t rw:1;
+                uint64_t multi:1;
+                uint64_t block_cnt:16;
+                uint64_t card_addr:32;
+        } s;
+        struct cvmx_mio_emm_dma_s cn61xx;
+};
+
+union cvmx_mio_emm_int {
+        uint64_t u64;
+        struct cvmx_mio_emm_int_s {
+                uint64_t reserved_7_63:57;
+                uint64_t switch_err:1;
+                uint64_t switch_done:1;
+                uint64_t dma_err:1;
+                uint64_t cmd_err:1;
+                uint64_t dma_done:1;
+                uint64_t cmd_done:1;
+                uint64_t buf_done:1;
+        } s;
+        struct cvmx_mio_emm_int_s cn61xx;
+};
+
+union cvmx_mio_emm_int_en {
+        uint64_t u64;
+        struct cvmx_mio_emm_int_en_s {
+                uint64_t reserved_7_63:57;
+                uint64_t switch_err:1;
+                uint64_t switch_done:1;
+                uint64_t dma_err:1;
+                uint64_t cmd_err:1;
+                uint64_t dma_done:1;
+                uint64_t cmd_done:1;
+                uint64_t buf_done:1;
+        } s;
+        struct cvmx_mio_emm_int_en_s cn61xx;
+};
+
+union cvmx_mio_emm_modex {
+        uint64_t u64;
+        struct cvmx_mio_emm_modex_s {
+                uint64_t reserved_49_63:15;
+                uint64_t hs_timing:1;
+                uint64_t reserved_43_47:5;
+                uint64_t bus_width:3;
+                uint64_t reserved_36_39:4;
+                uint64_t power_class:4;
+                uint64_t clk_hi:16;
+                uint64_t clk_lo:16;
+        } s;
+        struct cvmx_mio_emm_modex_s cn61xx;
+};
+
+union cvmx_mio_emm_rca {
+        uint64_t u64;
+        struct cvmx_mio_emm_rca_s {
+                uint64_t reserved_16_63:48;
+                uint64_t card_rca:16;
+        } s;
+        struct cvmx_mio_emm_rca_s cn61xx;
+};
+
+union cvmx_mio_emm_rsp_hi {
+        uint64_t u64;
+        struct cvmx_mio_emm_rsp_hi_s {
+                uint64_t dat:64;
+        } s;
+        struct cvmx_mio_emm_rsp_hi_s cn61xx;
+};
+
+union cvmx_mio_emm_rsp_lo {
+        uint64_t u64;
+        struct cvmx_mio_emm_rsp_lo_s {
+                uint64_t dat:64;
+        } s;
+        struct cvmx_mio_emm_rsp_lo_s cn61xx;
+};
+
+union cvmx_mio_emm_rsp_sts {
+        uint64_t u64;
+        struct cvmx_mio_emm_rsp_sts_s {
+                uint64_t reserved_62_63:2;
+                uint64_t bus_id:2;
+                uint64_t cmd_val:1;
+                uint64_t switch_val:1;
+                uint64_t dma_val:1;
+                uint64_t dma_pend:1;
+                uint64_t reserved_29_55:27;
+                uint64_t dbuf_err:1;
+                uint64_t reserved_24_27:4;
+                uint64_t dbuf:1;
+                uint64_t blk_timeout:1;
+                uint64_t blk_crc_err:1;
+                uint64_t rsp_busybit:1;
+                uint64_t stp_timeout:1;
+                uint64_t stp_crc_err:1;
+                uint64_t stp_bad_sts:1;
+                uint64_t stp_val:1;
+                uint64_t rsp_timeout:1;
+                uint64_t rsp_crc_err:1;
+                uint64_t rsp_bad_sts:1;
+                uint64_t rsp_val:1;
+                uint64_t rsp_type:3;
+                uint64_t cmd_type:2;
+                uint64_t cmd_idx:6;
+                uint64_t cmd_done:1;
+        } s;
+        struct cvmx_mio_emm_rsp_sts_s cn61xx;
+};
+
+union cvmx_mio_emm_sample {
+        uint64_t u64;
+        struct cvmx_mio_emm_sample_s {
+                uint64_t reserved_26_63:38;
+                uint64_t cmd_cnt:10;
+                uint64_t reserved_10_15:6;
+                uint64_t dat_cnt:10;
+        } s;
+        struct cvmx_mio_emm_sample_s cn61xx;
+};
+
+union cvmx_mio_emm_sts_mask {
+        uint64_t u64;
+        struct cvmx_mio_emm_sts_mask_s {
+                uint64_t reserved_32_63:32;
+                uint64_t sts_msk:32;
+        } s;
+        struct cvmx_mio_emm_sts_mask_s cn61xx;
+};
+
+union cvmx_mio_emm_switch {
+        uint64_t u64;
+        struct cvmx_mio_emm_switch_s {
+                uint64_t reserved_62_63:2;
+                uint64_t bus_id:2;
+                uint64_t switch_exe:1;
+                uint64_t switch_err0:1;
+                uint64_t switch_err1:1;
+                uint64_t switch_err2:1;
+                uint64_t reserved_49_55:7;
+                uint64_t hs_timing:1;
+                uint64_t reserved_43_47:5;
+                uint64_t bus_width:3;
+                uint64_t reserved_36_39:4;
+                uint64_t power_class:4;
+                uint64_t clk_hi:16;
+                uint64_t clk_lo:16;
+        } s;
+        struct cvmx_mio_emm_switch_s cn61xx;
+};
+
+union cvmx_mio_emm_wdog {
+        uint64_t u64;
+        struct cvmx_mio_emm_wdog_s {
+                uint64_t reserved_26_63:38;
+                uint64_t clk_cnt:26;
+        } s;
+        struct cvmx_mio_emm_wdog_s cn61xx;
 };
 
 union cvmx_mio_fus_bnk_datx {
@@ -590,8 +915,12 @@ union cvmx_mio_fus_bnk_datx {
         struct cvmx_mio_fus_bnk_datx_s cn56xxp1;
         struct cvmx_mio_fus_bnk_datx_s cn58xx;
         struct cvmx_mio_fus_bnk_datx_s cn58xxp1;
+        struct cvmx_mio_fus_bnk_datx_s cn61xx;
         struct cvmx_mio_fus_bnk_datx_s cn63xx;
         struct cvmx_mio_fus_bnk_datx_s cn63xxp1;
+        struct cvmx_mio_fus_bnk_datx_s cn66xx;
+        struct cvmx_mio_fus_bnk_datx_s cn68xx;
+        struct cvmx_mio_fus_bnk_datx_s cn68xxp1;
 };
 
 union cvmx_mio_fus_dat0 {
@@ -611,8 +940,12 @@ union cvmx_mio_fus_dat0 {
         struct cvmx_mio_fus_dat0_s cn56xxp1;
         struct cvmx_mio_fus_dat0_s cn58xx;
         struct cvmx_mio_fus_dat0_s cn58xxp1;
+        struct cvmx_mio_fus_dat0_s cn61xx;
         struct cvmx_mio_fus_dat0_s cn63xx;
         struct cvmx_mio_fus_dat0_s cn63xxp1;
+        struct cvmx_mio_fus_dat0_s cn66xx;
+        struct cvmx_mio_fus_dat0_s cn68xx;
+        struct cvmx_mio_fus_dat0_s cn68xxp1;
 };
 
 union cvmx_mio_fus_dat1 {
@@ -632,14 +965,21 @@ union cvmx_mio_fus_dat1 {
         struct cvmx_mio_fus_dat1_s cn56xxp1;
         struct cvmx_mio_fus_dat1_s cn58xx;
         struct cvmx_mio_fus_dat1_s cn58xxp1;
+        struct cvmx_mio_fus_dat1_s cn61xx;
         struct cvmx_mio_fus_dat1_s cn63xx;
         struct cvmx_mio_fus_dat1_s cn63xxp1;
+        struct cvmx_mio_fus_dat1_s cn66xx;
+        struct cvmx_mio_fus_dat1_s cn68xx;
+        struct cvmx_mio_fus_dat1_s cn68xxp1;
 };
 
 union cvmx_mio_fus_dat2 {
         uint64_t u64;
         struct cvmx_mio_fus_dat2_s {
-                uint64_t reserved_35_63:29;
+                uint64_t reserved_48_63:16;
+                uint64_t fus118:1;
+                uint64_t rom_info:10;
+                uint64_t power_limit:2;
                 uint64_t dorm_crypto:1;
                 uint64_t fus318:1;
                 uint64_t raid_en:1;
@@ -747,6 +1087,23 @@ union cvmx_mio_fus_dat2 {
                 uint64_t pp_dis:16;
         } cn58xx;
         struct cvmx_mio_fus_dat2_cn58xx cn58xxp1;
+        struct cvmx_mio_fus_dat2_cn61xx {
+                uint64_t reserved_48_63:16;
+                uint64_t fus118:1;
+                uint64_t rom_info:10;
+                uint64_t power_limit:2;
+                uint64_t dorm_crypto:1;
+                uint64_t fus318:1;
+                uint64_t raid_en:1;
+                uint64_t reserved_29_31:3;
+                uint64_t nodfa_cp2:1;
+                uint64_t nomul:1;
+                uint64_t nocrypto:1;
+                uint64_t reserved_24_25:2;
+                uint64_t chip_id:8;
+                uint64_t reserved_4_15:12;
+                uint64_t pp_dis:4;
+        } cn61xx;
         struct cvmx_mio_fus_dat2_cn63xx {
                 uint64_t reserved_35_63:29;
                 uint64_t dorm_crypto:1;
@@ -762,6 +1119,38 @@ union cvmx_mio_fus_dat2 {
                 uint64_t pp_dis:6;
         } cn63xx;
         struct cvmx_mio_fus_dat2_cn63xx cn63xxp1;
+        struct cvmx_mio_fus_dat2_cn66xx {
+                uint64_t reserved_48_63:16;
+                uint64_t fus118:1;
+                uint64_t rom_info:10;
+                uint64_t power_limit:2;
+                uint64_t dorm_crypto:1;
+                uint64_t fus318:1;
+                uint64_t raid_en:1;
+                uint64_t reserved_29_31:3;
+                uint64_t nodfa_cp2:1;
+                uint64_t nomul:1;
+                uint64_t nocrypto:1;
+                uint64_t reserved_24_25:2;
+                uint64_t chip_id:8;
+                uint64_t reserved_10_15:6;
+                uint64_t pp_dis:10;
+        } cn66xx;
+        struct cvmx_mio_fus_dat2_cn68xx {
+                uint64_t reserved_37_63:27;
+                uint64_t power_limit:2;
+                uint64_t dorm_crypto:1;
+                uint64_t fus318:1;
+                uint64_t raid_en:1;
+                uint64_t reserved_29_31:3;
+                uint64_t nodfa_cp2:1;
+                uint64_t nomul:1;
+                uint64_t nocrypto:1;
+                uint64_t reserved_24_25:2;
+                uint64_t chip_id:8;
+                uint64_t reserved_0_15:16;
+        } cn68xx;
+        struct cvmx_mio_fus_dat2_cn68xx cn68xxp1;
 };
 
 union cvmx_mio_fus_dat3 {
@@ -834,7 +1223,7 @@ union cvmx_mio_fus_dat3 {
         struct cvmx_mio_fus_dat3_cn38xx cn56xxp1;
         struct cvmx_mio_fus_dat3_cn38xx cn58xx;
         struct cvmx_mio_fus_dat3_cn38xx cn58xxp1;
-        struct cvmx_mio_fus_dat3_cn63xx {
+        struct cvmx_mio_fus_dat3_cn61xx {
                 uint64_t reserved_58_63:6;
                 uint64_t pll_ctl:10;
                 uint64_t dfa_info_dte:3;
@@ -853,8 +1242,12 @@ union cvmx_mio_fus_dat3 {
                 uint64_t nozip:1;
                 uint64_t nodfa_dte:1;
                 uint64_t reserved_0_23:24;
-        } cn63xx;
-        struct cvmx_mio_fus_dat3_cn63xx cn63xxp1;
+        } cn61xx;
+        struct cvmx_mio_fus_dat3_cn61xx cn63xx;
+        struct cvmx_mio_fus_dat3_cn61xx cn63xxp1;
+        struct cvmx_mio_fus_dat3_cn61xx cn66xx;
+        struct cvmx_mio_fus_dat3_cn61xx cn68xx;
+        struct cvmx_mio_fus_dat3_cn61xx cn68xxp1;
 };
 
 union cvmx_mio_fus_ema {
@@ -875,8 +1268,12 @@ union cvmx_mio_fus_ema {
                 uint64_t ema:2;
         } cn58xx;
         struct cvmx_mio_fus_ema_cn58xx cn58xxp1;
+        struct cvmx_mio_fus_ema_s cn61xx;
         struct cvmx_mio_fus_ema_s cn63xx;
         struct cvmx_mio_fus_ema_s cn63xxp1;
+        struct cvmx_mio_fus_ema_s cn66xx;
+        struct cvmx_mio_fus_ema_s cn68xx;
+        struct cvmx_mio_fus_ema_s cn68xxp1;
 };
 
 union cvmx_mio_fus_pdf {
@@ -890,14 +1287,21 @@ union cvmx_mio_fus_pdf {
         struct cvmx_mio_fus_pdf_s cn56xx;
         struct cvmx_mio_fus_pdf_s cn56xxp1;
         struct cvmx_mio_fus_pdf_s cn58xx;
+        struct cvmx_mio_fus_pdf_s cn61xx;
         struct cvmx_mio_fus_pdf_s cn63xx;
         struct cvmx_mio_fus_pdf_s cn63xxp1;
+        struct cvmx_mio_fus_pdf_s cn66xx;
+        struct cvmx_mio_fus_pdf_s cn68xx;
+        struct cvmx_mio_fus_pdf_s cn68xxp1;
 };
 
 union cvmx_mio_fus_pll {
         uint64_t u64;
         struct cvmx_mio_fus_pll_s {
-                uint64_t reserved_8_63:56;
+                uint64_t reserved_48_63:16;
+                uint64_t rclk_align_r:8;
+                uint64_t rclk_align_l:8;
+                uint64_t reserved_8_31:24;
                 uint64_t c_cout_rst:1;
                 uint64_t c_cout_sel:2;
                 uint64_t pnr_cout_rst:1;
@@ -916,8 +1320,20 @@ union cvmx_mio_fus_pll {
         struct cvmx_mio_fus_pll_cn50xx cn56xxp1;
         struct cvmx_mio_fus_pll_cn50xx cn58xx;
         struct cvmx_mio_fus_pll_cn50xx cn58xxp1;
-        struct cvmx_mio_fus_pll_s cn63xx;
-        struct cvmx_mio_fus_pll_s cn63xxp1;
+        struct cvmx_mio_fus_pll_cn61xx {
+                uint64_t reserved_8_63:56;
+                uint64_t c_cout_rst:1;
+                uint64_t c_cout_sel:2;
+                uint64_t pnr_cout_rst:1;
+                uint64_t pnr_cout_sel:2;
+                uint64_t rfslip:1;
+                uint64_t fbslip:1;
+        } cn61xx;
+        struct cvmx_mio_fus_pll_cn61xx cn63xx;
+        struct cvmx_mio_fus_pll_cn61xx cn63xxp1;
+        struct cvmx_mio_fus_pll_cn61xx cn66xx;
+        struct cvmx_mio_fus_pll_s cn68xx;
+        struct cvmx_mio_fus_pll_s cn68xxp1;
 };
 
 union cvmx_mio_fus_prog {
@@ -941,8 +1357,12 @@ union cvmx_mio_fus_prog {
         struct cvmx_mio_fus_prog_cn30xx cn56xxp1;
         struct cvmx_mio_fus_prog_cn30xx cn58xx;
         struct cvmx_mio_fus_prog_cn30xx cn58xxp1;
+        struct cvmx_mio_fus_prog_s cn61xx;
         struct cvmx_mio_fus_prog_s cn63xx;
         struct cvmx_mio_fus_prog_s cn63xxp1;
+        struct cvmx_mio_fus_prog_s cn66xx;
+        struct cvmx_mio_fus_prog_s cn68xx;
+        struct cvmx_mio_fus_prog_s cn68xxp1;
 };
 
 union cvmx_mio_fus_prog_times {
@@ -969,7 +1389,7 @@ union cvmx_mio_fus_prog_times {
         struct cvmx_mio_fus_prog_times_cn50xx cn56xxp1;
         struct cvmx_mio_fus_prog_times_cn50xx cn58xx;
         struct cvmx_mio_fus_prog_times_cn50xx cn58xxp1;
-        struct cvmx_mio_fus_prog_times_cn63xx {
+        struct cvmx_mio_fus_prog_times_cn61xx {
                 uint64_t reserved_35_63:29;
                 uint64_t vgate_pin:1;
                 uint64_t fsrc_pin:1;
@@ -978,8 +1398,12 @@ union cvmx_mio_fus_prog_times {
                 uint64_t sclk_lo:4;
                 uint64_t sclk_hi:15;
                 uint64_t setup:6;
-        } cn63xx;
-        struct cvmx_mio_fus_prog_times_cn63xx cn63xxp1;
+        } cn61xx;
+        struct cvmx_mio_fus_prog_times_cn61xx cn63xx;
+        struct cvmx_mio_fus_prog_times_cn61xx cn63xxp1;
+        struct cvmx_mio_fus_prog_times_cn61xx cn66xx;
+        struct cvmx_mio_fus_prog_times_cn61xx cn68xx;
+        struct cvmx_mio_fus_prog_times_cn61xx cn68xxp1;
 };
 
 union cvmx_mio_fus_rcmd {
@@ -1013,8 +1437,12 @@ union cvmx_mio_fus_rcmd {
         struct cvmx_mio_fus_rcmd_s cn56xxp1;
         struct cvmx_mio_fus_rcmd_cn30xx cn58xx;
         struct cvmx_mio_fus_rcmd_cn30xx cn58xxp1;
+        struct cvmx_mio_fus_rcmd_s cn61xx;
         struct cvmx_mio_fus_rcmd_s cn63xx;
         struct cvmx_mio_fus_rcmd_s cn63xxp1;
+        struct cvmx_mio_fus_rcmd_s cn66xx;
+        struct cvmx_mio_fus_rcmd_s cn68xx;
+        struct cvmx_mio_fus_rcmd_s cn68xxp1;
 };
 
 union cvmx_mio_fus_read_times {
@@ -1027,8 +1455,12 @@ union cvmx_mio_fus_read_times {
                 uint64_t sdh:4;
                 uint64_t setup:10;
         } s;
+        struct cvmx_mio_fus_read_times_s cn61xx;
         struct cvmx_mio_fus_read_times_s cn63xx;
         struct cvmx_mio_fus_read_times_s cn63xxp1;
+        struct cvmx_mio_fus_read_times_s cn66xx;
+        struct cvmx_mio_fus_read_times_s cn68xx;
+        struct cvmx_mio_fus_read_times_s cn68xxp1;
 };
 
 union cvmx_mio_fus_repair_res0 {
@@ -1040,8 +1472,12 @@ union cvmx_mio_fus_repair_res0 {
                 uint64_t repair1:18;
                 uint64_t repair0:18;
         } s;
+        struct cvmx_mio_fus_repair_res0_s cn61xx;
         struct cvmx_mio_fus_repair_res0_s cn63xx;
         struct cvmx_mio_fus_repair_res0_s cn63xxp1;
+        struct cvmx_mio_fus_repair_res0_s cn66xx;
+        struct cvmx_mio_fus_repair_res0_s cn68xx;
+        struct cvmx_mio_fus_repair_res0_s cn68xxp1;
 };
 
 union cvmx_mio_fus_repair_res1 {
@@ -1052,8 +1488,12 @@ union cvmx_mio_fus_repair_res1 {
                 uint64_t repair4:18;
                 uint64_t repair3:18;
         } s;
+        struct cvmx_mio_fus_repair_res1_s cn61xx;
         struct cvmx_mio_fus_repair_res1_s cn63xx;
         struct cvmx_mio_fus_repair_res1_s cn63xxp1;
+        struct cvmx_mio_fus_repair_res1_s cn66xx;
+        struct cvmx_mio_fus_repair_res1_s cn68xx;
+        struct cvmx_mio_fus_repair_res1_s cn68xxp1;
 };
 
 union cvmx_mio_fus_repair_res2 {
@@ -1062,8 +1502,12 @@ union cvmx_mio_fus_repair_res2 {
                 uint64_t reserved_18_63:46;
                 uint64_t repair6:18;
         } s;
+        struct cvmx_mio_fus_repair_res2_s cn61xx;
         struct cvmx_mio_fus_repair_res2_s cn63xx;
         struct cvmx_mio_fus_repair_res2_s cn63xxp1;
+        struct cvmx_mio_fus_repair_res2_s cn66xx;
+        struct cvmx_mio_fus_repair_res2_s cn68xx;
+        struct cvmx_mio_fus_repair_res2_s cn68xxp1;
 };
 
 union cvmx_mio_fus_spr_repair_res {
@@ -1084,8 +1528,12 @@ union cvmx_mio_fus_spr_repair_res {
         struct cvmx_mio_fus_spr_repair_res_s cn56xxp1;
         struct cvmx_mio_fus_spr_repair_res_s cn58xx;
         struct cvmx_mio_fus_spr_repair_res_s cn58xxp1;
+        struct cvmx_mio_fus_spr_repair_res_s cn61xx;
         struct cvmx_mio_fus_spr_repair_res_s cn63xx;
         struct cvmx_mio_fus_spr_repair_res_s cn63xxp1;
+        struct cvmx_mio_fus_spr_repair_res_s cn66xx;
+        struct cvmx_mio_fus_spr_repair_res_s cn68xx;
+        struct cvmx_mio_fus_spr_repair_res_s cn68xxp1;
 };
 
 union cvmx_mio_fus_spr_repair_sum {
@@ -1104,8 +1552,22 @@ union cvmx_mio_fus_spr_repair_sum {
         struct cvmx_mio_fus_spr_repair_sum_s cn56xxp1;
         struct cvmx_mio_fus_spr_repair_sum_s cn58xx;
         struct cvmx_mio_fus_spr_repair_sum_s cn58xxp1;
+        struct cvmx_mio_fus_spr_repair_sum_s cn61xx;
         struct cvmx_mio_fus_spr_repair_sum_s cn63xx;
         struct cvmx_mio_fus_spr_repair_sum_s cn63xxp1;
+        struct cvmx_mio_fus_spr_repair_sum_s cn66xx;
+        struct cvmx_mio_fus_spr_repair_sum_s cn68xx;
+        struct cvmx_mio_fus_spr_repair_sum_s cn68xxp1;
+};
+
+union cvmx_mio_fus_tgg {
+        uint64_t u64;
+        struct cvmx_mio_fus_tgg_s {
+                uint64_t val:1;
+                uint64_t dat:63;
+        } s;
+        struct cvmx_mio_fus_tgg_s cn61xx;
+        struct cvmx_mio_fus_tgg_s cn66xx;
 };
 
 union cvmx_mio_fus_unlock {
@@ -1141,11 +1603,15 @@ union cvmx_mio_fus_wadr {
         struct cvmx_mio_fus_wadr_cn52xx cn56xxp1;
         struct cvmx_mio_fus_wadr_cn50xx cn58xx;
         struct cvmx_mio_fus_wadr_cn50xx cn58xxp1;
-        struct cvmx_mio_fus_wadr_cn63xx {
+        struct cvmx_mio_fus_wadr_cn61xx {
                 uint64_t reserved_4_63:60;
                 uint64_t addr:4;
-        } cn63xx;
-        struct cvmx_mio_fus_wadr_cn63xx cn63xxp1;
+        } cn61xx;
+        struct cvmx_mio_fus_wadr_cn61xx cn63xx;
+        struct cvmx_mio_fus_wadr_cn61xx cn63xxp1;
+        struct cvmx_mio_fus_wadr_cn61xx cn66xx;
+        struct cvmx_mio_fus_wadr_cn61xx cn68xx;
+        struct cvmx_mio_fus_wadr_cn61xx cn68xxp1;
 };
 
 union cvmx_mio_gpio_comp {
@@ -1155,8 +1621,12 @@ union cvmx_mio_gpio_comp {
                 uint64_t pctl:6;
                 uint64_t nctl:6;
         } s;
+        struct cvmx_mio_gpio_comp_s cn61xx;
         struct cvmx_mio_gpio_comp_s cn63xx;
         struct cvmx_mio_gpio_comp_s cn63xxp1;
+        struct cvmx_mio_gpio_comp_s cn66xx;
+        struct cvmx_mio_gpio_comp_s cn68xx;
+        struct cvmx_mio_gpio_comp_s cn68xxp1;
 };
 
 union cvmx_mio_ndf_dma_cfg {
@@ -1174,8 +1644,12 @@ union cvmx_mio_ndf_dma_cfg {
                 uint64_t adr:36;
         } s;
         struct cvmx_mio_ndf_dma_cfg_s cn52xx;
+        struct cvmx_mio_ndf_dma_cfg_s cn61xx;
         struct cvmx_mio_ndf_dma_cfg_s cn63xx;
         struct cvmx_mio_ndf_dma_cfg_s cn63xxp1;
+        struct cvmx_mio_ndf_dma_cfg_s cn66xx;
+        struct cvmx_mio_ndf_dma_cfg_s cn68xx;
+        struct cvmx_mio_ndf_dma_cfg_s cn68xxp1;
 };
 
 union cvmx_mio_ndf_dma_int {
@@ -1185,8 +1659,12 @@ union cvmx_mio_ndf_dma_int {
                 uint64_t done:1;
         } s;
         struct cvmx_mio_ndf_dma_int_s cn52xx;
+        struct cvmx_mio_ndf_dma_int_s cn61xx;
         struct cvmx_mio_ndf_dma_int_s cn63xx;
         struct cvmx_mio_ndf_dma_int_s cn63xxp1;
+        struct cvmx_mio_ndf_dma_int_s cn66xx;
+        struct cvmx_mio_ndf_dma_int_s cn68xx;
+        struct cvmx_mio_ndf_dma_int_s cn68xxp1;
 };
 
 union cvmx_mio_ndf_dma_int_en {
@@ -1196,8 +1674,12 @@ union cvmx_mio_ndf_dma_int_en {
                 uint64_t done:1;
         } s;
         struct cvmx_mio_ndf_dma_int_en_s cn52xx;
+        struct cvmx_mio_ndf_dma_int_en_s cn61xx;
         struct cvmx_mio_ndf_dma_int_en_s cn63xx;
         struct cvmx_mio_ndf_dma_int_en_s cn63xxp1;
+        struct cvmx_mio_ndf_dma_int_en_s cn66xx;
+        struct cvmx_mio_ndf_dma_int_en_s cn68xx;
+        struct cvmx_mio_ndf_dma_int_en_s cn68xxp1;
 };
 
 union cvmx_mio_pll_ctl {
@@ -1220,10 +1702,63 @@ union cvmx_mio_pll_setting {
         struct cvmx_mio_pll_setting_s cn31xx;
 };
 
+union cvmx_mio_ptp_ckout_hi_incr {
+        uint64_t u64;
+        struct cvmx_mio_ptp_ckout_hi_incr_s {
+                uint64_t nanosec:32;
+                uint64_t frnanosec:32;
+        } s;
+        struct cvmx_mio_ptp_ckout_hi_incr_s cn61xx;
+        struct cvmx_mio_ptp_ckout_hi_incr_s cn66xx;
+        struct cvmx_mio_ptp_ckout_hi_incr_s cn68xx;
+};
+
+union cvmx_mio_ptp_ckout_lo_incr {
+        uint64_t u64;
+        struct cvmx_mio_ptp_ckout_lo_incr_s {
+                uint64_t nanosec:32;
+                uint64_t frnanosec:32;
+        } s;
+        struct cvmx_mio_ptp_ckout_lo_incr_s cn61xx;
+        struct cvmx_mio_ptp_ckout_lo_incr_s cn66xx;
+        struct cvmx_mio_ptp_ckout_lo_incr_s cn68xx;
+};
+
+union cvmx_mio_ptp_ckout_thresh_hi {
+        uint64_t u64;
+        struct cvmx_mio_ptp_ckout_thresh_hi_s {
+                uint64_t nanosec:64;
+        } s;
+        struct cvmx_mio_ptp_ckout_thresh_hi_s cn61xx;
+        struct cvmx_mio_ptp_ckout_thresh_hi_s cn66xx;
+        struct cvmx_mio_ptp_ckout_thresh_hi_s cn68xx;
+};
+
+union cvmx_mio_ptp_ckout_thresh_lo {
+        uint64_t u64;
+        struct cvmx_mio_ptp_ckout_thresh_lo_s {
+                uint64_t reserved_32_63:32;
+                uint64_t frnanosec:32;
+        } s;
+        struct cvmx_mio_ptp_ckout_thresh_lo_s cn61xx;
+        struct cvmx_mio_ptp_ckout_thresh_lo_s cn66xx;
+        struct cvmx_mio_ptp_ckout_thresh_lo_s cn68xx;
+};
+
 union cvmx_mio_ptp_clock_cfg {
         uint64_t u64;
         struct cvmx_mio_ptp_clock_cfg_s {
-                uint64_t reserved_24_63:40;
+                uint64_t reserved_42_63:22;
+                uint64_t pps:1;
+                uint64_t ckout:1;
+                uint64_t ext_clk_edge:2;
+                uint64_t ckout_out4:1;
+                uint64_t pps_out:5;
+                uint64_t pps_inv:1;
+                uint64_t pps_en:1;
+                uint64_t ckout_out:4;
+                uint64_t ckout_inv:1;
+                uint64_t ckout_en:1;
                 uint64_t evcnt_in:6;
                 uint64_t evcnt_edge:1;
                 uint64_t evcnt_en:1;
@@ -1234,8 +1769,42 @@ union cvmx_mio_ptp_clock_cfg {
                 uint64_t ext_clk_en:1;
                 uint64_t ptp_en:1;
         } s;
-        struct cvmx_mio_ptp_clock_cfg_s cn63xx;
-        struct cvmx_mio_ptp_clock_cfg_s cn63xxp1;
+        struct cvmx_mio_ptp_clock_cfg_s cn61xx;
+        struct cvmx_mio_ptp_clock_cfg_cn63xx {
+                uint64_t reserved_24_63:40;
+                uint64_t evcnt_in:6;
+                uint64_t evcnt_edge:1;
+                uint64_t evcnt_en:1;
+                uint64_t tstmp_in:6;
+                uint64_t tstmp_edge:1;
+                uint64_t tstmp_en:1;
+                uint64_t ext_clk_in:6;
+                uint64_t ext_clk_en:1;
+                uint64_t ptp_en:1;
+        } cn63xx;
+        struct cvmx_mio_ptp_clock_cfg_cn63xx cn63xxp1;
+        struct cvmx_mio_ptp_clock_cfg_cn66xx {
+                uint64_t reserved_40_63:24;
+                uint64_t ext_clk_edge:2;
+                uint64_t ckout_out4:1;
+                uint64_t pps_out:5;
+                uint64_t pps_inv:1;
+                uint64_t pps_en:1;
+                uint64_t ckout_out:4;
+                uint64_t ckout_inv:1;
+                uint64_t ckout_en:1;
+                uint64_t evcnt_in:6;
+                uint64_t evcnt_edge:1;
+                uint64_t evcnt_en:1;
+                uint64_t tstmp_in:6;
+                uint64_t tstmp_edge:1;
+                uint64_t tstmp_en:1;
+                uint64_t ext_clk_in:6;
+                uint64_t ext_clk_en:1;
+                uint64_t ptp_en:1;
+        } cn66xx;
+        struct cvmx_mio_ptp_clock_cfg_s cn68xx;
+        struct cvmx_mio_ptp_clock_cfg_cn63xx cn68xxp1;
 };
 
 union cvmx_mio_ptp_clock_comp {
@@ -1244,8 +1813,12 @@ union cvmx_mio_ptp_clock_comp {
                 uint64_t nanosec:32;
                 uint64_t frnanosec:32;
         } s;
+        struct cvmx_mio_ptp_clock_comp_s cn61xx;
         struct cvmx_mio_ptp_clock_comp_s cn63xx;
         struct cvmx_mio_ptp_clock_comp_s cn63xxp1;
+        struct cvmx_mio_ptp_clock_comp_s cn66xx;
+        struct cvmx_mio_ptp_clock_comp_s cn68xx;
+        struct cvmx_mio_ptp_clock_comp_s cn68xxp1;
 };
 
 union cvmx_mio_ptp_clock_hi {
@@ -1253,8 +1826,12 @@ union cvmx_mio_ptp_clock_hi {
         struct cvmx_mio_ptp_clock_hi_s {
                 uint64_t nanosec:64;
         } s;
+        struct cvmx_mio_ptp_clock_hi_s cn61xx;
         struct cvmx_mio_ptp_clock_hi_s cn63xx;
         struct cvmx_mio_ptp_clock_hi_s cn63xxp1;
+        struct cvmx_mio_ptp_clock_hi_s cn66xx;
+        struct cvmx_mio_ptp_clock_hi_s cn68xx;
+        struct cvmx_mio_ptp_clock_hi_s cn68xxp1;
 };
 
 union cvmx_mio_ptp_clock_lo {
@@ -1263,8 +1840,12 @@ union cvmx_mio_ptp_clock_lo {
                 uint64_t reserved_32_63:32;
                 uint64_t frnanosec:32;
         } s;
+        struct cvmx_mio_ptp_clock_lo_s cn61xx;
         struct cvmx_mio_ptp_clock_lo_s cn63xx;
         struct cvmx_mio_ptp_clock_lo_s cn63xxp1;
+        struct cvmx_mio_ptp_clock_lo_s cn66xx;
+        struct cvmx_mio_ptp_clock_lo_s cn68xx;
+        struct cvmx_mio_ptp_clock_lo_s cn68xxp1;
 };
 
 union cvmx_mio_ptp_evt_cnt {
@@ -1272,8 +1853,55 @@ union cvmx_mio_ptp_evt_cnt {
         struct cvmx_mio_ptp_evt_cnt_s {
                 uint64_t cntr:64;
         } s;
+        struct cvmx_mio_ptp_evt_cnt_s cn61xx;
         struct cvmx_mio_ptp_evt_cnt_s cn63xx;
         struct cvmx_mio_ptp_evt_cnt_s cn63xxp1;
+        struct cvmx_mio_ptp_evt_cnt_s cn66xx;
+        struct cvmx_mio_ptp_evt_cnt_s cn68xx;
+        struct cvmx_mio_ptp_evt_cnt_s cn68xxp1;
+};
+
+union cvmx_mio_ptp_pps_hi_incr {
+        uint64_t u64;
+        struct cvmx_mio_ptp_pps_hi_incr_s {
+                uint64_t nanosec:32;
+                uint64_t frnanosec:32;
+        } s;
+        struct cvmx_mio_ptp_pps_hi_incr_s cn61xx;
+        struct cvmx_mio_ptp_pps_hi_incr_s cn66xx;
+        struct cvmx_mio_ptp_pps_hi_incr_s cn68xx;
+};
+
+union cvmx_mio_ptp_pps_lo_incr {
+        uint64_t u64;
+        struct cvmx_mio_ptp_pps_lo_incr_s {
+                uint64_t nanosec:32;
+                uint64_t frnanosec:32;
+        } s;
+        struct cvmx_mio_ptp_pps_lo_incr_s cn61xx;
+        struct cvmx_mio_ptp_pps_lo_incr_s cn66xx;
+        struct cvmx_mio_ptp_pps_lo_incr_s cn68xx;
+};
+
+union cvmx_mio_ptp_pps_thresh_hi {
+        uint64_t u64;
+        struct cvmx_mio_ptp_pps_thresh_hi_s {
+                uint64_t nanosec:64;
+        } s;
+        struct cvmx_mio_ptp_pps_thresh_hi_s cn61xx;
+        struct cvmx_mio_ptp_pps_thresh_hi_s cn66xx;
+        struct cvmx_mio_ptp_pps_thresh_hi_s cn68xx;
+};
+
+union cvmx_mio_ptp_pps_thresh_lo {
+        uint64_t u64;
+        struct cvmx_mio_ptp_pps_thresh_lo_s {
+                uint64_t reserved_32_63:32;
+                uint64_t frnanosec:32;
+        } s;
+        struct cvmx_mio_ptp_pps_thresh_lo_s cn61xx;
+        struct cvmx_mio_ptp_pps_thresh_lo_s cn66xx;
+        struct cvmx_mio_ptp_pps_thresh_lo_s cn68xx;
 };
 
 union cvmx_mio_ptp_timestamp {
@@ -1281,14 +1909,52 @@ union cvmx_mio_ptp_timestamp {
         struct cvmx_mio_ptp_timestamp_s {
                 uint64_t nanosec:64;
         } s;
+        struct cvmx_mio_ptp_timestamp_s cn61xx;
         struct cvmx_mio_ptp_timestamp_s cn63xx;
         struct cvmx_mio_ptp_timestamp_s cn63xxp1;
+        struct cvmx_mio_ptp_timestamp_s cn66xx;
+        struct cvmx_mio_ptp_timestamp_s cn68xx;
+        struct cvmx_mio_ptp_timestamp_s cn68xxp1;
+};
+
+union cvmx_mio_qlmx_cfg {
+        uint64_t u64;
+        struct cvmx_mio_qlmx_cfg_s {
+                uint64_t reserved_12_63:52;
+                uint64_t qlm_spd:4;
+                uint64_t reserved_4_7:4;
+                uint64_t qlm_cfg:4;
+        } s;
+        struct cvmx_mio_qlmx_cfg_cn61xx {
+                uint64_t reserved_12_63:52;
+                uint64_t qlm_spd:4;
+                uint64_t reserved_2_7:6;
+                uint64_t qlm_cfg:2;
+        } cn61xx;
+        struct cvmx_mio_qlmx_cfg_s cn66xx;
+        struct cvmx_mio_qlmx_cfg_cn68xx {
+                uint64_t reserved_12_63:52;
+                uint64_t qlm_spd:4;
+                uint64_t reserved_3_7:5;
+                uint64_t qlm_cfg:3;
+        } cn68xx;
+        struct cvmx_mio_qlmx_cfg_cn68xx cn68xxp1;
 };
 
 union cvmx_mio_rst_boot {
         uint64_t u64;
         struct cvmx_mio_rst_boot_s {
-                uint64_t reserved_36_63:28;
+                uint64_t chipkill:1;
+                uint64_t jtcsrdis:1;
+                uint64_t ejtagdis:1;
+                uint64_t romen:1;
+                uint64_t ckill_ppdis:1;
+                uint64_t jt_tstmode:1;
+                uint64_t reserved_50_57:8;
+                uint64_t lboot_ext:2;
+                uint64_t reserved_44_47:4;
+                uint64_t qlm4_spd:4;
+                uint64_t qlm3_spd:4;
                 uint64_t c_mul:6;
                 uint64_t pnr_mul:6;
                 uint64_t qlm2_spd:4;
@@ -1298,32 +1964,168 @@ union cvmx_mio_rst_boot {
                 uint64_t rboot:1;
                 uint64_t rboot_pin:1;
         } s;
-        struct cvmx_mio_rst_boot_s cn63xx;
-        struct cvmx_mio_rst_boot_s cn63xxp1;
+        struct cvmx_mio_rst_boot_cn61xx {
+                uint64_t chipkill:1;
+                uint64_t jtcsrdis:1;
+                uint64_t ejtagdis:1;
+                uint64_t romen:1;
+                uint64_t ckill_ppdis:1;
+                uint64_t jt_tstmode:1;
+                uint64_t reserved_50_57:8;
+                uint64_t lboot_ext:2;
+                uint64_t reserved_36_47:12;
+                uint64_t c_mul:6;
+                uint64_t pnr_mul:6;
+                uint64_t qlm2_spd:4;
+                uint64_t qlm1_spd:4;
+                uint64_t qlm0_spd:4;
+                uint64_t lboot:10;
+                uint64_t rboot:1;
+                uint64_t rboot_pin:1;
+        } cn61xx;
+        struct cvmx_mio_rst_boot_cn63xx {
+                uint64_t reserved_36_63:28;
+                uint64_t c_mul:6;
+                uint64_t pnr_mul:6;
+                uint64_t qlm2_spd:4;
+                uint64_t qlm1_spd:4;
+                uint64_t qlm0_spd:4;
+                uint64_t lboot:10;
+                uint64_t rboot:1;
+                uint64_t rboot_pin:1;
+        } cn63xx;
+        struct cvmx_mio_rst_boot_cn63xx cn63xxp1;
+        struct cvmx_mio_rst_boot_cn66xx {
+                uint64_t chipkill:1;
+                uint64_t jtcsrdis:1;
+                uint64_t ejtagdis:1;
+                uint64_t romen:1;
+                uint64_t ckill_ppdis:1;
+                uint64_t reserved_50_58:9;
+                uint64_t lboot_ext:2;
+                uint64_t reserved_36_47:12;
+                uint64_t c_mul:6;
+                uint64_t pnr_mul:6;
+                uint64_t qlm2_spd:4;
+                uint64_t qlm1_spd:4;
+                uint64_t qlm0_spd:4;
+                uint64_t lboot:10;
+                uint64_t rboot:1;
+                uint64_t rboot_pin:1;
+        } cn66xx;
+        struct cvmx_mio_rst_boot_cn68xx {
+                uint64_t reserved_59_63:5;
+                uint64_t jt_tstmode:1;
+                uint64_t reserved_44_57:14;
+                uint64_t qlm4_spd:4;
+                uint64_t qlm3_spd:4;
+                uint64_t c_mul:6;
+                uint64_t pnr_mul:6;
+                uint64_t qlm2_spd:4;
+                uint64_t qlm1_spd:4;
+                uint64_t qlm0_spd:4;
+                uint64_t lboot:10;
+                uint64_t rboot:1;
+                uint64_t rboot_pin:1;
+        } cn68xx;
+        struct cvmx_mio_rst_boot_cn68xxp1 {
+                uint64_t reserved_44_63:20;
+                uint64_t qlm4_spd:4;
+                uint64_t qlm3_spd:4;
+                uint64_t c_mul:6;
+                uint64_t pnr_mul:6;
+                uint64_t qlm2_spd:4;
+                uint64_t qlm1_spd:4;
+                uint64_t qlm0_spd:4;
+                uint64_t lboot:10;
+                uint64_t rboot:1;
+                uint64_t rboot_pin:1;
+        } cn68xxp1;
 };
 
 union cvmx_mio_rst_cfg {
         uint64_t u64;
         struct cvmx_mio_rst_cfg_s {
+                uint64_t reserved_3_63:61;
+                uint64_t cntl_clr_bist:1;
+                uint64_t warm_clr_bist:1;
+                uint64_t soft_clr_bist:1;
+        } s;
+        struct cvmx_mio_rst_cfg_cn61xx {
                 uint64_t bist_delay:58;
                 uint64_t reserved_3_5:3;
                 uint64_t cntl_clr_bist:1;
                 uint64_t warm_clr_bist:1;
                 uint64_t soft_clr_bist:1;
-        } s;
-        struct cvmx_mio_rst_cfg_s cn63xx;
+        } cn61xx;
+        struct cvmx_mio_rst_cfg_cn61xx cn63xx;
         struct cvmx_mio_rst_cfg_cn63xxp1 {
                 uint64_t bist_delay:58;
                 uint64_t reserved_2_5:4;
                 uint64_t warm_clr_bist:1;
                 uint64_t soft_clr_bist:1;
         } cn63xxp1;
+        struct cvmx_mio_rst_cfg_cn61xx cn66xx;
+        struct cvmx_mio_rst_cfg_cn68xx {
+                uint64_t bist_delay:56;
+                uint64_t reserved_3_7:5;
+                uint64_t cntl_clr_bist:1;
+                uint64_t warm_clr_bist:1;
+                uint64_t soft_clr_bist:1;
+        } cn68xx;
+        struct cvmx_mio_rst_cfg_cn68xx cn68xxp1;
+};
+
+union cvmx_mio_rst_ckill {
+        uint64_t u64;
+        struct cvmx_mio_rst_ckill_s {
+                uint64_t reserved_47_63:17;
+                uint64_t timer:47;
+        } s;
+        struct cvmx_mio_rst_ckill_s cn61xx;
+        struct cvmx_mio_rst_ckill_s cn66xx;
+};
+
+union cvmx_mio_rst_cntlx {
+        uint64_t u64;
+        struct cvmx_mio_rst_cntlx_s {
+                uint64_t reserved_13_63:51;
+                uint64_t in_rev_ln:1;
+                uint64_t rev_lanes:1;
+                uint64_t gen1_only:1;
+                uint64_t prst_link:1;
+                uint64_t rst_done:1;
+                uint64_t rst_link:1;
+                uint64_t host_mode:1;
+                uint64_t prtmode:2;
+                uint64_t rst_drv:1;
+                uint64_t rst_rcv:1;
+                uint64_t rst_chip:1;
+                uint64_t rst_val:1;
+        } s;
+        struct cvmx_mio_rst_cntlx_s cn61xx;
+        struct cvmx_mio_rst_cntlx_cn66xx {
+                uint64_t reserved_10_63:54;
+                uint64_t prst_link:1;
+                uint64_t rst_done:1;
+                uint64_t rst_link:1;
+                uint64_t host_mode:1;
+                uint64_t prtmode:2;
+                uint64_t rst_drv:1;
+                uint64_t rst_rcv:1;
+                uint64_t rst_chip:1;
+                uint64_t rst_val:1;
+        } cn66xx;
+        struct cvmx_mio_rst_cntlx_cn66xx cn68xx;
 };
 
 union cvmx_mio_rst_ctlx {
         uint64_t u64;
         struct cvmx_mio_rst_ctlx_s {
-                uint64_t reserved_10_63:54;
+                uint64_t reserved_13_63:51;
+                uint64_t in_rev_ln:1;
+                uint64_t rev_lanes:1;
+                uint64_t gen1_only:1;
                 uint64_t prst_link:1;
                 uint64_t rst_done:1;
                 uint64_t rst_link:1;
@@ -1334,7 +2136,19 @@ union cvmx_mio_rst_ctlx {
                 uint64_t rst_chip:1;
                 uint64_t rst_val:1;
         } s;
-        struct cvmx_mio_rst_ctlx_s cn63xx;
+        struct cvmx_mio_rst_ctlx_s cn61xx;
+        struct cvmx_mio_rst_ctlx_cn63xx {
+                uint64_t reserved_10_63:54;
+                uint64_t prst_link:1;
+                uint64_t rst_done:1;
+                uint64_t rst_link:1;
+                uint64_t host_mode:1;
+                uint64_t prtmode:2;
+                uint64_t rst_drv:1;
+                uint64_t rst_rcv:1;
+                uint64_t rst_chip:1;
+                uint64_t rst_val:1;
+        } cn63xx;
         struct cvmx_mio_rst_ctlx_cn63xxp1 {
                 uint64_t reserved_9_63:55;
                 uint64_t rst_done:1;
@@ -1346,17 +2160,24 @@ union cvmx_mio_rst_ctlx {
                 uint64_t rst_chip:1;
                 uint64_t rst_val:1;
         } cn63xxp1;
+        struct cvmx_mio_rst_ctlx_cn63xx cn66xx;
+        struct cvmx_mio_rst_ctlx_cn63xx cn68xx;
+        struct cvmx_mio_rst_ctlx_cn63xx cn68xxp1;
 };
 
 union cvmx_mio_rst_delay {
         uint64_t u64;
         struct cvmx_mio_rst_delay_s {
                 uint64_t reserved_32_63:32;
-                uint64_t soft_rst_dly:16;
                 uint64_t warm_rst_dly:16;
+                uint64_t soft_rst_dly:16;
         } s;
+        struct cvmx_mio_rst_delay_s cn61xx;
         struct cvmx_mio_rst_delay_s cn63xx;
         struct cvmx_mio_rst_delay_s cn63xxp1;
+        struct cvmx_mio_rst_delay_s cn66xx;
+        struct cvmx_mio_rst_delay_s cn68xx;
+        struct cvmx_mio_rst_delay_s cn68xxp1;
 };
 
 union cvmx_mio_rst_int {
@@ -1365,12 +2186,25 @@ union cvmx_mio_rst_int {
                 uint64_t reserved_10_63:54;
                 uint64_t perst1:1;
                 uint64_t perst0:1;
-                uint64_t reserved_2_7:6;
+                uint64_t reserved_4_7:4;
+                uint64_t rst_link3:1;
+                uint64_t rst_link2:1;
                 uint64_t rst_link1:1;
                 uint64_t rst_link0:1;
         } s;
-        struct cvmx_mio_rst_int_s cn63xx;
-        struct cvmx_mio_rst_int_s cn63xxp1;
+        struct cvmx_mio_rst_int_cn61xx {
+                uint64_t reserved_10_63:54;
+                uint64_t perst1:1;
+                uint64_t perst0:1;
+                uint64_t reserved_2_7:6;
+                uint64_t rst_link1:1;
+                uint64_t rst_link0:1;
+        } cn61xx;
+        struct cvmx_mio_rst_int_cn61xx cn63xx;
+        struct cvmx_mio_rst_int_cn61xx cn63xxp1;
+        struct cvmx_mio_rst_int_s cn66xx;
+        struct cvmx_mio_rst_int_cn61xx cn68xx;
+        struct cvmx_mio_rst_int_cn61xx cn68xxp1;
 };
 
 union cvmx_mio_rst_int_en {
@@ -1379,12 +2213,25 @@ union cvmx_mio_rst_int_en {
                 uint64_t reserved_10_63:54;
                 uint64_t perst1:1;
                 uint64_t perst0:1;
-                uint64_t reserved_2_7:6;
+                uint64_t reserved_4_7:4;
+                uint64_t rst_link3:1;
+                uint64_t rst_link2:1;
                 uint64_t rst_link1:1;
                 uint64_t rst_link0:1;
         } s;
-        struct cvmx_mio_rst_int_en_s cn63xx;
-        struct cvmx_mio_rst_int_en_s cn63xxp1;
+        struct cvmx_mio_rst_int_en_cn61xx {
+                uint64_t reserved_10_63:54;
+                uint64_t perst1:1;
+                uint64_t perst0:1;
+                uint64_t reserved_2_7:6;
+                uint64_t rst_link1:1;
+                uint64_t rst_link0:1;
+        } cn61xx;
+        struct cvmx_mio_rst_int_en_cn61xx cn63xx;
+        struct cvmx_mio_rst_int_en_cn61xx cn63xxp1;
+        struct cvmx_mio_rst_int_en_s cn66xx;
+        struct cvmx_mio_rst_int_en_cn61xx cn68xx;
+        struct cvmx_mio_rst_int_en_cn61xx cn68xxp1;
 };
 
 union cvmx_mio_twsx_int {
@@ -1424,8 +2271,12 @@ union cvmx_mio_twsx_int {
         struct cvmx_mio_twsx_int_s cn56xxp1;
         struct cvmx_mio_twsx_int_s cn58xx;
         struct cvmx_mio_twsx_int_s cn58xxp1;
+        struct cvmx_mio_twsx_int_s cn61xx;
         struct cvmx_mio_twsx_int_s cn63xx;
         struct cvmx_mio_twsx_int_s cn63xxp1;
+        struct cvmx_mio_twsx_int_s cn66xx;
+        struct cvmx_mio_twsx_int_s cn68xx;
+        struct cvmx_mio_twsx_int_s cn68xxp1;
 };
 
 union cvmx_mio_twsx_sw_twsi {
@@ -1455,8 +2306,12 @@ union cvmx_mio_twsx_sw_twsi {
         struct cvmx_mio_twsx_sw_twsi_s cn56xxp1;
         struct cvmx_mio_twsx_sw_twsi_s cn58xx;
         struct cvmx_mio_twsx_sw_twsi_s cn58xxp1;
+        struct cvmx_mio_twsx_sw_twsi_s cn61xx;
         struct cvmx_mio_twsx_sw_twsi_s cn63xx;
         struct cvmx_mio_twsx_sw_twsi_s cn63xxp1;
+        struct cvmx_mio_twsx_sw_twsi_s cn66xx;
+        struct cvmx_mio_twsx_sw_twsi_s cn68xx;
+        struct cvmx_mio_twsx_sw_twsi_s cn68xxp1;
 };
 
 union cvmx_mio_twsx_sw_twsi_ext {
@@ -1477,8 +2332,12 @@ union cvmx_mio_twsx_sw_twsi_ext {
         struct cvmx_mio_twsx_sw_twsi_ext_s cn56xxp1;
         struct cvmx_mio_twsx_sw_twsi_ext_s cn58xx;
         struct cvmx_mio_twsx_sw_twsi_ext_s cn58xxp1;
+        struct cvmx_mio_twsx_sw_twsi_ext_s cn61xx;
         struct cvmx_mio_twsx_sw_twsi_ext_s cn63xx;
         struct cvmx_mio_twsx_sw_twsi_ext_s cn63xxp1;
+        struct cvmx_mio_twsx_sw_twsi_ext_s cn66xx;
+        struct cvmx_mio_twsx_sw_twsi_ext_s cn68xx;
+        struct cvmx_mio_twsx_sw_twsi_ext_s cn68xxp1;
 };
 
 union cvmx_mio_twsx_twsi_sw {
@@ -1499,8 +2358,12 @@ union cvmx_mio_twsx_twsi_sw {
         struct cvmx_mio_twsx_twsi_sw_s cn56xxp1;
         struct cvmx_mio_twsx_twsi_sw_s cn58xx;
         struct cvmx_mio_twsx_twsi_sw_s cn58xxp1;
+        struct cvmx_mio_twsx_twsi_sw_s cn61xx;
         struct cvmx_mio_twsx_twsi_sw_s cn63xx;
         struct cvmx_mio_twsx_twsi_sw_s cn63xxp1;
+        struct cvmx_mio_twsx_twsi_sw_s cn66xx;
+        struct cvmx_mio_twsx_twsi_sw_s cn68xx;
+        struct cvmx_mio_twsx_twsi_sw_s cn68xxp1;
 };
 
 union cvmx_mio_uartx_dlh {
@@ -1520,8 +2383,12 @@ union cvmx_mio_uartx_dlh {
         struct cvmx_mio_uartx_dlh_s cn56xxp1;
         struct cvmx_mio_uartx_dlh_s cn58xx;
         struct cvmx_mio_uartx_dlh_s cn58xxp1;
+        struct cvmx_mio_uartx_dlh_s cn61xx;
         struct cvmx_mio_uartx_dlh_s cn63xx;
         struct cvmx_mio_uartx_dlh_s cn63xxp1;
+        struct cvmx_mio_uartx_dlh_s cn66xx;
+        struct cvmx_mio_uartx_dlh_s cn68xx;
+        struct cvmx_mio_uartx_dlh_s cn68xxp1;
 };
 
 union cvmx_mio_uartx_dll {
@@ -1541,8 +2408,12 @@ union cvmx_mio_uartx_dll {
         struct cvmx_mio_uartx_dll_s cn56xxp1;
         struct cvmx_mio_uartx_dll_s cn58xx;
         struct cvmx_mio_uartx_dll_s cn58xxp1;
+        struct cvmx_mio_uartx_dll_s cn61xx;
         struct cvmx_mio_uartx_dll_s cn63xx;
         struct cvmx_mio_uartx_dll_s cn63xxp1;
+        struct cvmx_mio_uartx_dll_s cn66xx;
+        struct cvmx_mio_uartx_dll_s cn68xx;
+        struct cvmx_mio_uartx_dll_s cn68xxp1;
 };
 
 union cvmx_mio_uartx_far {
@@ -1562,8 +2433,12 @@ union cvmx_mio_uartx_far {
         struct cvmx_mio_uartx_far_s cn56xxp1;
         struct cvmx_mio_uartx_far_s cn58xx;
         struct cvmx_mio_uartx_far_s cn58xxp1;
+        struct cvmx_mio_uartx_far_s cn61xx;
         struct cvmx_mio_uartx_far_s cn63xx;
         struct cvmx_mio_uartx_far_s cn63xxp1;
+        struct cvmx_mio_uartx_far_s cn66xx;
+        struct cvmx_mio_uartx_far_s cn68xx;
+        struct cvmx_mio_uartx_far_s cn68xxp1;
 };
 
 union cvmx_mio_uartx_fcr {
@@ -1588,8 +2463,12 @@ union cvmx_mio_uartx_fcr {
         struct cvmx_mio_uartx_fcr_s cn56xxp1;
         struct cvmx_mio_uartx_fcr_s cn58xx;
         struct cvmx_mio_uartx_fcr_s cn58xxp1;
+        struct cvmx_mio_uartx_fcr_s cn61xx;
         struct cvmx_mio_uartx_fcr_s cn63xx;
         struct cvmx_mio_uartx_fcr_s cn63xxp1;
+        struct cvmx_mio_uartx_fcr_s cn66xx;
+        struct cvmx_mio_uartx_fcr_s cn68xx;
+        struct cvmx_mio_uartx_fcr_s cn68xxp1;
 };
 
 union cvmx_mio_uartx_htx {
@@ -1609,8 +2488,12 @@ union cvmx_mio_uartx_htx {
         struct cvmx_mio_uartx_htx_s cn56xxp1;
         struct cvmx_mio_uartx_htx_s cn58xx;
         struct cvmx_mio_uartx_htx_s cn58xxp1;
+        struct cvmx_mio_uartx_htx_s cn61xx;
         struct cvmx_mio_uartx_htx_s cn63xx;
         struct cvmx_mio_uartx_htx_s cn63xxp1;
+        struct cvmx_mio_uartx_htx_s cn66xx;
+        struct cvmx_mio_uartx_htx_s cn68xx;
+        struct cvmx_mio_uartx_htx_s cn68xxp1;
 };
 
 union cvmx_mio_uartx_ier {
@@ -1635,8 +2518,12 @@ union cvmx_mio_uartx_ier {
         struct cvmx_mio_uartx_ier_s cn56xxp1;
         struct cvmx_mio_uartx_ier_s cn58xx;
         struct cvmx_mio_uartx_ier_s cn58xxp1;
+        struct cvmx_mio_uartx_ier_s cn61xx;
         struct cvmx_mio_uartx_ier_s cn63xx;
         struct cvmx_mio_uartx_ier_s cn63xxp1;
+        struct cvmx_mio_uartx_ier_s cn66xx;
+        struct cvmx_mio_uartx_ier_s cn68xx;
+        struct cvmx_mio_uartx_ier_s cn68xxp1;
 };
 
 union cvmx_mio_uartx_iir {
@@ -1658,8 +2545,12 @@ union cvmx_mio_uartx_iir {
         struct cvmx_mio_uartx_iir_s cn56xxp1;
         struct cvmx_mio_uartx_iir_s cn58xx;
         struct cvmx_mio_uartx_iir_s cn58xxp1;
+        struct cvmx_mio_uartx_iir_s cn61xx;
         struct cvmx_mio_uartx_iir_s cn63xx;
         struct cvmx_mio_uartx_iir_s cn63xxp1;
+        struct cvmx_mio_uartx_iir_s cn66xx;
+        struct cvmx_mio_uartx_iir_s cn68xx;
+        struct cvmx_mio_uartx_iir_s cn68xxp1;
 };
 
 union cvmx_mio_uartx_lcr {
@@ -1685,8 +2576,12 @@ union cvmx_mio_uartx_lcr {
         struct cvmx_mio_uartx_lcr_s cn56xxp1;
         struct cvmx_mio_uartx_lcr_s cn58xx;
         struct cvmx_mio_uartx_lcr_s cn58xxp1;
+        struct cvmx_mio_uartx_lcr_s cn61xx;
         struct cvmx_mio_uartx_lcr_s cn63xx;
         struct cvmx_mio_uartx_lcr_s cn63xxp1;
+        struct cvmx_mio_uartx_lcr_s cn66xx;
+        struct cvmx_mio_uartx_lcr_s cn68xx;
+        struct cvmx_mio_uartx_lcr_s cn68xxp1;
 };
 
 union cvmx_mio_uartx_lsr {
@@ -1713,8 +2608,12 @@ union cvmx_mio_uartx_lsr {
         struct cvmx_mio_uartx_lsr_s cn56xxp1;
         struct cvmx_mio_uartx_lsr_s cn58xx;
         struct cvmx_mio_uartx_lsr_s cn58xxp1;
+        struct cvmx_mio_uartx_lsr_s cn61xx;
         struct cvmx_mio_uartx_lsr_s cn63xx;
         struct cvmx_mio_uartx_lsr_s cn63xxp1;
+        struct cvmx_mio_uartx_lsr_s cn66xx;
+        struct cvmx_mio_uartx_lsr_s cn68xx;
+        struct cvmx_mio_uartx_lsr_s cn68xxp1;
 };
 
 union cvmx_mio_uartx_mcr {
@@ -1739,8 +2638,12 @@ union cvmx_mio_uartx_mcr {
         struct cvmx_mio_uartx_mcr_s cn56xxp1;
         struct cvmx_mio_uartx_mcr_s cn58xx;
         struct cvmx_mio_uartx_mcr_s cn58xxp1;
+        struct cvmx_mio_uartx_mcr_s cn61xx;
         struct cvmx_mio_uartx_mcr_s cn63xx;
         struct cvmx_mio_uartx_mcr_s cn63xxp1;
+        struct cvmx_mio_uartx_mcr_s cn66xx;
+        struct cvmx_mio_uartx_mcr_s cn68xx;
+        struct cvmx_mio_uartx_mcr_s cn68xxp1;
 };
 
 union cvmx_mio_uartx_msr {
@@ -1767,8 +2670,12 @@ union cvmx_mio_uartx_msr {
         struct cvmx_mio_uartx_msr_s cn56xxp1;
         struct cvmx_mio_uartx_msr_s cn58xx;
         struct cvmx_mio_uartx_msr_s cn58xxp1;
+        struct cvmx_mio_uartx_msr_s cn61xx;
         struct cvmx_mio_uartx_msr_s cn63xx;
         struct cvmx_mio_uartx_msr_s cn63xxp1;
+        struct cvmx_mio_uartx_msr_s cn66xx;
+        struct cvmx_mio_uartx_msr_s cn68xx;
+        struct cvmx_mio_uartx_msr_s cn68xxp1;
 };
 
 union cvmx_mio_uartx_rbr {
@@ -1788,8 +2695,12 @@ union cvmx_mio_uartx_rbr {
         struct cvmx_mio_uartx_rbr_s cn56xxp1;
         struct cvmx_mio_uartx_rbr_s cn58xx;
         struct cvmx_mio_uartx_rbr_s cn58xxp1;
+        struct cvmx_mio_uartx_rbr_s cn61xx;
         struct cvmx_mio_uartx_rbr_s cn63xx;
         struct cvmx_mio_uartx_rbr_s cn63xxp1;
+        struct cvmx_mio_uartx_rbr_s cn66xx;
+        struct cvmx_mio_uartx_rbr_s cn68xx;
+        struct cvmx_mio_uartx_rbr_s cn68xxp1;
 };
 
 union cvmx_mio_uartx_rfl {
@@ -1809,8 +2720,12 @@ union cvmx_mio_uartx_rfl {
         struct cvmx_mio_uartx_rfl_s cn56xxp1;
         struct cvmx_mio_uartx_rfl_s cn58xx;
         struct cvmx_mio_uartx_rfl_s cn58xxp1;
+        struct cvmx_mio_uartx_rfl_s cn61xx;
         struct cvmx_mio_uartx_rfl_s cn63xx;
         struct cvmx_mio_uartx_rfl_s cn63xxp1;
+        struct cvmx_mio_uartx_rfl_s cn66xx;
+        struct cvmx_mio_uartx_rfl_s cn68xx;
+        struct cvmx_mio_uartx_rfl_s cn68xxp1;
 };
 
 union cvmx_mio_uartx_rfw {
@@ -1832,8 +2747,12 @@ union cvmx_mio_uartx_rfw {
         struct cvmx_mio_uartx_rfw_s cn56xxp1;
         struct cvmx_mio_uartx_rfw_s cn58xx;
         struct cvmx_mio_uartx_rfw_s cn58xxp1;
+        struct cvmx_mio_uartx_rfw_s cn61xx;
         struct cvmx_mio_uartx_rfw_s cn63xx;
         struct cvmx_mio_uartx_rfw_s cn63xxp1;
+        struct cvmx_mio_uartx_rfw_s cn66xx;
+        struct cvmx_mio_uartx_rfw_s cn68xx;
+        struct cvmx_mio_uartx_rfw_s cn68xxp1;
 };
 
 union cvmx_mio_uartx_sbcr {
@@ -1853,8 +2772,12 @@ union cvmx_mio_uartx_sbcr {
         struct cvmx_mio_uartx_sbcr_s cn56xxp1;
         struct cvmx_mio_uartx_sbcr_s cn58xx;
         struct cvmx_mio_uartx_sbcr_s cn58xxp1;
+        struct cvmx_mio_uartx_sbcr_s cn61xx;
         struct cvmx_mio_uartx_sbcr_s cn63xx;
         struct cvmx_mio_uartx_sbcr_s cn63xxp1;
+        struct cvmx_mio_uartx_sbcr_s cn66xx;
+        struct cvmx_mio_uartx_sbcr_s cn68xx;
+        struct cvmx_mio_uartx_sbcr_s cn68xxp1;
 };
 
 union cvmx_mio_uartx_scr {
@@ -1874,8 +2797,12 @@ union cvmx_mio_uartx_scr {
         struct cvmx_mio_uartx_scr_s cn56xxp1;
         struct cvmx_mio_uartx_scr_s cn58xx;
         struct cvmx_mio_uartx_scr_s cn58xxp1;
+        struct cvmx_mio_uartx_scr_s cn61xx;
         struct cvmx_mio_uartx_scr_s cn63xx;
         struct cvmx_mio_uartx_scr_s cn63xxp1;
+        struct cvmx_mio_uartx_scr_s cn66xx;
+        struct cvmx_mio_uartx_scr_s cn68xx;
+        struct cvmx_mio_uartx_scr_s cn68xxp1;
 };
 
 union cvmx_mio_uartx_sfe {
@@ -1895,8 +2822,12 @@ union cvmx_mio_uartx_sfe {
         struct cvmx_mio_uartx_sfe_s cn56xxp1;
         struct cvmx_mio_uartx_sfe_s cn58xx;
         struct cvmx_mio_uartx_sfe_s cn58xxp1;
+        struct cvmx_mio_uartx_sfe_s cn61xx;
         struct cvmx_mio_uartx_sfe_s cn63xx;
         struct cvmx_mio_uartx_sfe_s cn63xxp1;
+        struct cvmx_mio_uartx_sfe_s cn66xx;
+        struct cvmx_mio_uartx_sfe_s cn68xx;
+        struct cvmx_mio_uartx_sfe_s cn68xxp1;
 };
 
 union cvmx_mio_uartx_srr {
@@ -1918,8 +2849,12 @@ union cvmx_mio_uartx_srr {
         struct cvmx_mio_uartx_srr_s cn56xxp1;
         struct cvmx_mio_uartx_srr_s cn58xx;
         struct cvmx_mio_uartx_srr_s cn58xxp1;
+        struct cvmx_mio_uartx_srr_s cn61xx;
         struct cvmx_mio_uartx_srr_s cn63xx;
         struct cvmx_mio_uartx_srr_s cn63xxp1;
+        struct cvmx_mio_uartx_srr_s cn66xx;
+        struct cvmx_mio_uartx_srr_s cn68xx;
+        struct cvmx_mio_uartx_srr_s cn68xxp1;
 };
 
 union cvmx_mio_uartx_srt {
@@ -1939,8 +2874,12 @@ union cvmx_mio_uartx_srt {
         struct cvmx_mio_uartx_srt_s cn56xxp1;
         struct cvmx_mio_uartx_srt_s cn58xx;
         struct cvmx_mio_uartx_srt_s cn58xxp1;
+        struct cvmx_mio_uartx_srt_s cn61xx;
         struct cvmx_mio_uartx_srt_s cn63xx;
         struct cvmx_mio_uartx_srt_s cn63xxp1;
+        struct cvmx_mio_uartx_srt_s cn66xx;
+        struct cvmx_mio_uartx_srt_s cn68xx;
+        struct cvmx_mio_uartx_srt_s cn68xxp1;
 };
 
 union cvmx_mio_uartx_srts {
@@ -1960,8 +2899,12 @@ union cvmx_mio_uartx_srts {
         struct cvmx_mio_uartx_srts_s cn56xxp1;
         struct cvmx_mio_uartx_srts_s cn58xx;
         struct cvmx_mio_uartx_srts_s cn58xxp1;
+        struct cvmx_mio_uartx_srts_s cn61xx;
         struct cvmx_mio_uartx_srts_s cn63xx;
         struct cvmx_mio_uartx_srts_s cn63xxp1;
+        struct cvmx_mio_uartx_srts_s cn66xx;
+        struct cvmx_mio_uartx_srts_s cn68xx;
+        struct cvmx_mio_uartx_srts_s cn68xxp1;
 };
 
 union cvmx_mio_uartx_stt {
@@ -1981,8 +2924,12 @@ union cvmx_mio_uartx_stt {
         struct cvmx_mio_uartx_stt_s cn56xxp1;
         struct cvmx_mio_uartx_stt_s cn58xx;
         struct cvmx_mio_uartx_stt_s cn58xxp1;
+        struct cvmx_mio_uartx_stt_s cn61xx;
         struct cvmx_mio_uartx_stt_s cn63xx;
         struct cvmx_mio_uartx_stt_s cn63xxp1;
+        struct cvmx_mio_uartx_stt_s cn66xx;
+        struct cvmx_mio_uartx_stt_s cn68xx;
+        struct cvmx_mio_uartx_stt_s cn68xxp1;
 };
 
 union cvmx_mio_uartx_tfl {
@@ -2002,8 +2949,12 @@ union cvmx_mio_uartx_tfl {
         struct cvmx_mio_uartx_tfl_s cn56xxp1;
         struct cvmx_mio_uartx_tfl_s cn58xx;
         struct cvmx_mio_uartx_tfl_s cn58xxp1;
+        struct cvmx_mio_uartx_tfl_s cn61xx;
         struct cvmx_mio_uartx_tfl_s cn63xx;
         struct cvmx_mio_uartx_tfl_s cn63xxp1;
+        struct cvmx_mio_uartx_tfl_s cn66xx;
+        struct cvmx_mio_uartx_tfl_s cn68xx;
+        struct cvmx_mio_uartx_tfl_s cn68xxp1;
 };
 
 union cvmx_mio_uartx_tfr {
@@ -2023,8 +2974,12 @@ union cvmx_mio_uartx_tfr {
         struct cvmx_mio_uartx_tfr_s cn56xxp1;
         struct cvmx_mio_uartx_tfr_s cn58xx;
         struct cvmx_mio_uartx_tfr_s cn58xxp1;
+        struct cvmx_mio_uartx_tfr_s cn61xx;
         struct cvmx_mio_uartx_tfr_s cn63xx;
         struct cvmx_mio_uartx_tfr_s cn63xxp1;
+        struct cvmx_mio_uartx_tfr_s cn66xx;
+        struct cvmx_mio_uartx_tfr_s cn68xx;
+        struct cvmx_mio_uartx_tfr_s cn68xxp1;
 };
 
 union cvmx_mio_uartx_thr {
@@ -2044,8 +2999,12 @@ union cvmx_mio_uartx_thr {
         struct cvmx_mio_uartx_thr_s cn56xxp1;
         struct cvmx_mio_uartx_thr_s cn58xx;
         struct cvmx_mio_uartx_thr_s cn58xxp1;
+        struct cvmx_mio_uartx_thr_s cn61xx;
         struct cvmx_mio_uartx_thr_s cn63xx;
         struct cvmx_mio_uartx_thr_s cn63xxp1;
+        struct cvmx_mio_uartx_thr_s cn66xx;
+        struct cvmx_mio_uartx_thr_s cn68xx;
+        struct cvmx_mio_uartx_thr_s cn68xxp1;
 };
 
 union cvmx_mio_uartx_usr {
@@ -2069,8 +3028,12 @@ union cvmx_mio_uartx_usr {
         struct cvmx_mio_uartx_usr_s cn56xxp1;
         struct cvmx_mio_uartx_usr_s cn58xx;
         struct cvmx_mio_uartx_usr_s cn58xxp1;
+        struct cvmx_mio_uartx_usr_s cn61xx;
         struct cvmx_mio_uartx_usr_s cn63xx;
         struct cvmx_mio_uartx_usr_s cn63xxp1;
+        struct cvmx_mio_uartx_usr_s cn66xx;
+        struct cvmx_mio_uartx_usr_s cn68xx;
+        struct cvmx_mio_uartx_usr_s cn68xxp1;
 };
 
 union cvmx_mio_uart2_dlh {
diff --git a/arch/mips/include/asm/octeon/cvmx-npei-defs.h b/arch/mips/include/asm/octeon/cvmx-npei-defs.h
index 9899a9d2ba7..a3075f733ca 100644
--- a/arch/mips/include/asm/octeon/cvmx-npei-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-npei-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2010 Cavium Networks
+ * Copyright (c) 2003-2011 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -65,7 +65,7 @@
 #define CVMX_NPEI_LAST_WIN_RDATA0 (0x0000000000000600ull)
 #define CVMX_NPEI_LAST_WIN_RDATA1 (0x0000000000000610ull)
 #define CVMX_NPEI_MEM_ACCESS_CTL (0x00000000000004F0ull)
-#define CVMX_NPEI_MEM_ACCESS_SUBIDX(offset) (0x0000000000000340ull + ((offset) & 31) * 16 - 16*12)
+#define CVMX_NPEI_MEM_ACCESS_SUBIDX(offset) (0x0000000000000280ull + ((offset) & 31) * 16 - 16*12)
 #define CVMX_NPEI_MSI_ENB0 (0x0000000000003C50ull)
 #define CVMX_NPEI_MSI_ENB1 (0x0000000000003C60ull)
 #define CVMX_NPEI_MSI_ENB2 (0x0000000000003C70ull)
diff --git a/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h b/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h
index f8cb88902ef..7b1dc8b74e5 100644
--- a/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2010 Cavium Networks
+ * Copyright (c) 2003-2011 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -116,8 +116,12 @@ union cvmx_pciercx_cfg000 {
         struct cvmx_pciercx_cfg000_s cn52xxp1;
         struct cvmx_pciercx_cfg000_s cn56xx;
         struct cvmx_pciercx_cfg000_s cn56xxp1;
+        struct cvmx_pciercx_cfg000_s cn61xx;
         struct cvmx_pciercx_cfg000_s cn63xx;
         struct cvmx_pciercx_cfg000_s cn63xxp1;
+        struct cvmx_pciercx_cfg000_s cn66xx;
+        struct cvmx_pciercx_cfg000_s cn68xx;
+        struct cvmx_pciercx_cfg000_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg001 {
@@ -152,8 +156,12 @@ union cvmx_pciercx_cfg001 {
         struct cvmx_pciercx_cfg001_s cn52xxp1;
         struct cvmx_pciercx_cfg001_s cn56xx;
         struct cvmx_pciercx_cfg001_s cn56xxp1;
+        struct cvmx_pciercx_cfg001_s cn61xx;
         struct cvmx_pciercx_cfg001_s cn63xx;
         struct cvmx_pciercx_cfg001_s cn63xxp1;
+        struct cvmx_pciercx_cfg001_s cn66xx;
+        struct cvmx_pciercx_cfg001_s cn68xx;
+        struct cvmx_pciercx_cfg001_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg002 {
@@ -168,8 +176,12 @@ union cvmx_pciercx_cfg002 {
         struct cvmx_pciercx_cfg002_s cn52xxp1;
         struct cvmx_pciercx_cfg002_s cn56xx;
         struct cvmx_pciercx_cfg002_s cn56xxp1;
+        struct cvmx_pciercx_cfg002_s cn61xx;
         struct cvmx_pciercx_cfg002_s cn63xx;
         struct cvmx_pciercx_cfg002_s cn63xxp1;
+        struct cvmx_pciercx_cfg002_s cn66xx;
+        struct cvmx_pciercx_cfg002_s cn68xx;
+        struct cvmx_pciercx_cfg002_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg003 {
@@ -185,8 +197,12 @@ union cvmx_pciercx_cfg003 {
         struct cvmx_pciercx_cfg003_s cn52xxp1;
         struct cvmx_pciercx_cfg003_s cn56xx;
         struct cvmx_pciercx_cfg003_s cn56xxp1;
+        struct cvmx_pciercx_cfg003_s cn61xx;
         struct cvmx_pciercx_cfg003_s cn63xx;
         struct cvmx_pciercx_cfg003_s cn63xxp1;
+        struct cvmx_pciercx_cfg003_s cn66xx;
+        struct cvmx_pciercx_cfg003_s cn68xx;
+        struct cvmx_pciercx_cfg003_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg004 {
@@ -198,8 +214,12 @@ union cvmx_pciercx_cfg004 {
         struct cvmx_pciercx_cfg004_s cn52xxp1;
         struct cvmx_pciercx_cfg004_s cn56xx;
         struct cvmx_pciercx_cfg004_s cn56xxp1;
+        struct cvmx_pciercx_cfg004_s cn61xx;
         struct cvmx_pciercx_cfg004_s cn63xx;
         struct cvmx_pciercx_cfg004_s cn63xxp1;
+        struct cvmx_pciercx_cfg004_s cn66xx;
+        struct cvmx_pciercx_cfg004_s cn68xx;
+        struct cvmx_pciercx_cfg004_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg005 {
@@ -211,8 +231,12 @@ union cvmx_pciercx_cfg005 {
         struct cvmx_pciercx_cfg005_s cn52xxp1;
         struct cvmx_pciercx_cfg005_s cn56xx;
         struct cvmx_pciercx_cfg005_s cn56xxp1;
+        struct cvmx_pciercx_cfg005_s cn61xx;
         struct cvmx_pciercx_cfg005_s cn63xx;
         struct cvmx_pciercx_cfg005_s cn63xxp1;
+        struct cvmx_pciercx_cfg005_s cn66xx;
+        struct cvmx_pciercx_cfg005_s cn68xx;
+        struct cvmx_pciercx_cfg005_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg006 {
@@ -227,8 +251,12 @@ union cvmx_pciercx_cfg006 {
         struct cvmx_pciercx_cfg006_s cn52xxp1;
         struct cvmx_pciercx_cfg006_s cn56xx;
         struct cvmx_pciercx_cfg006_s cn56xxp1;
+        struct cvmx_pciercx_cfg006_s cn61xx;
         struct cvmx_pciercx_cfg006_s cn63xx;
         struct cvmx_pciercx_cfg006_s cn63xxp1;
+        struct cvmx_pciercx_cfg006_s cn66xx;
+        struct cvmx_pciercx_cfg006_s cn68xx;
+        struct cvmx_pciercx_cfg006_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg007 {
@@ -256,8 +284,12 @@ union cvmx_pciercx_cfg007 {
         struct cvmx_pciercx_cfg007_s cn52xxp1;
         struct cvmx_pciercx_cfg007_s cn56xx;
         struct cvmx_pciercx_cfg007_s cn56xxp1;
+        struct cvmx_pciercx_cfg007_s cn61xx;
         struct cvmx_pciercx_cfg007_s cn63xx;
         struct cvmx_pciercx_cfg007_s cn63xxp1;
+        struct cvmx_pciercx_cfg007_s cn66xx;
+        struct cvmx_pciercx_cfg007_s cn68xx;
+        struct cvmx_pciercx_cfg007_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg008 {
@@ -272,8 +304,12 @@ union cvmx_pciercx_cfg008 {
         struct cvmx_pciercx_cfg008_s cn52xxp1;
         struct cvmx_pciercx_cfg008_s cn56xx;
         struct cvmx_pciercx_cfg008_s cn56xxp1;
+        struct cvmx_pciercx_cfg008_s cn61xx;
         struct cvmx_pciercx_cfg008_s cn63xx;
         struct cvmx_pciercx_cfg008_s cn63xxp1;
+        struct cvmx_pciercx_cfg008_s cn66xx;
+        struct cvmx_pciercx_cfg008_s cn68xx;
+        struct cvmx_pciercx_cfg008_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg009 {
@@ -290,8 +326,12 @@ union cvmx_pciercx_cfg009 {
         struct cvmx_pciercx_cfg009_s cn52xxp1;
         struct cvmx_pciercx_cfg009_s cn56xx;
         struct cvmx_pciercx_cfg009_s cn56xxp1;
+        struct cvmx_pciercx_cfg009_s cn61xx;
         struct cvmx_pciercx_cfg009_s cn63xx;
         struct cvmx_pciercx_cfg009_s cn63xxp1;
+        struct cvmx_pciercx_cfg009_s cn66xx;
+        struct cvmx_pciercx_cfg009_s cn68xx;
+        struct cvmx_pciercx_cfg009_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg010 {
@@ -303,8 +343,12 @@ union cvmx_pciercx_cfg010 {
         struct cvmx_pciercx_cfg010_s cn52xxp1;
         struct cvmx_pciercx_cfg010_s cn56xx;
         struct cvmx_pciercx_cfg010_s cn56xxp1;
+        struct cvmx_pciercx_cfg010_s cn61xx;
         struct cvmx_pciercx_cfg010_s cn63xx;
         struct cvmx_pciercx_cfg010_s cn63xxp1;
+        struct cvmx_pciercx_cfg010_s cn66xx;
+        struct cvmx_pciercx_cfg010_s cn68xx;
+        struct cvmx_pciercx_cfg010_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg011 {
@@ -316,8 +360,12 @@ union cvmx_pciercx_cfg011 {
         struct cvmx_pciercx_cfg011_s cn52xxp1;
         struct cvmx_pciercx_cfg011_s cn56xx;
         struct cvmx_pciercx_cfg011_s cn56xxp1;
+        struct cvmx_pciercx_cfg011_s cn61xx;
         struct cvmx_pciercx_cfg011_s cn63xx;
         struct cvmx_pciercx_cfg011_s cn63xxp1;
+        struct cvmx_pciercx_cfg011_s cn66xx;
+        struct cvmx_pciercx_cfg011_s cn68xx;
+        struct cvmx_pciercx_cfg011_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg012 {
@@ -330,8 +378,12 @@ union cvmx_pciercx_cfg012 {
         struct cvmx_pciercx_cfg012_s cn52xxp1;
         struct cvmx_pciercx_cfg012_s cn56xx;
         struct cvmx_pciercx_cfg012_s cn56xxp1;
+        struct cvmx_pciercx_cfg012_s cn61xx;
         struct cvmx_pciercx_cfg012_s cn63xx;
         struct cvmx_pciercx_cfg012_s cn63xxp1;
+        struct cvmx_pciercx_cfg012_s cn66xx;
+        struct cvmx_pciercx_cfg012_s cn68xx;
+        struct cvmx_pciercx_cfg012_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg013 {
@@ -344,8 +396,12 @@ union cvmx_pciercx_cfg013 {
         struct cvmx_pciercx_cfg013_s cn52xxp1;
         struct cvmx_pciercx_cfg013_s cn56xx;
         struct cvmx_pciercx_cfg013_s cn56xxp1;
+        struct cvmx_pciercx_cfg013_s cn61xx;
         struct cvmx_pciercx_cfg013_s cn63xx;
         struct cvmx_pciercx_cfg013_s cn63xxp1;
+        struct cvmx_pciercx_cfg013_s cn66xx;
+        struct cvmx_pciercx_cfg013_s cn68xx;
+        struct cvmx_pciercx_cfg013_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg014 {
@@ -357,8 +413,12 @@ union cvmx_pciercx_cfg014 {
         struct cvmx_pciercx_cfg014_s cn52xxp1;
         struct cvmx_pciercx_cfg014_s cn56xx;
         struct cvmx_pciercx_cfg014_s cn56xxp1;
+        struct cvmx_pciercx_cfg014_s cn61xx;
         struct cvmx_pciercx_cfg014_s cn63xx;
         struct cvmx_pciercx_cfg014_s cn63xxp1;
+        struct cvmx_pciercx_cfg014_s cn66xx;
+        struct cvmx_pciercx_cfg014_s cn68xx;
+        struct cvmx_pciercx_cfg014_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg015 {
@@ -384,8 +444,12 @@ union cvmx_pciercx_cfg015 {
         struct cvmx_pciercx_cfg015_s cn52xxp1;
         struct cvmx_pciercx_cfg015_s cn56xx;
         struct cvmx_pciercx_cfg015_s cn56xxp1;
+        struct cvmx_pciercx_cfg015_s cn61xx;
         struct cvmx_pciercx_cfg015_s cn63xx;
         struct cvmx_pciercx_cfg015_s cn63xxp1;
+        struct cvmx_pciercx_cfg015_s cn66xx;
+        struct cvmx_pciercx_cfg015_s cn68xx;
+        struct cvmx_pciercx_cfg015_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg016 {
@@ -406,8 +470,12 @@ union cvmx_pciercx_cfg016 {
         struct cvmx_pciercx_cfg016_s cn52xxp1;
         struct cvmx_pciercx_cfg016_s cn56xx;
         struct cvmx_pciercx_cfg016_s cn56xxp1;
+        struct cvmx_pciercx_cfg016_s cn61xx;
         struct cvmx_pciercx_cfg016_s cn63xx;
         struct cvmx_pciercx_cfg016_s cn63xxp1;
+        struct cvmx_pciercx_cfg016_s cn66xx;
+        struct cvmx_pciercx_cfg016_s cn68xx;
+        struct cvmx_pciercx_cfg016_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg017 {
@@ -430,14 +498,19 @@ union cvmx_pciercx_cfg017 {
         struct cvmx_pciercx_cfg017_s cn52xxp1;
         struct cvmx_pciercx_cfg017_s cn56xx;
         struct cvmx_pciercx_cfg017_s cn56xxp1;
+        struct cvmx_pciercx_cfg017_s cn61xx;
         struct cvmx_pciercx_cfg017_s cn63xx;
         struct cvmx_pciercx_cfg017_s cn63xxp1;
+        struct cvmx_pciercx_cfg017_s cn66xx;
+        struct cvmx_pciercx_cfg017_s cn68xx;
+        struct cvmx_pciercx_cfg017_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg020 {
         uint32_t u32;
         struct cvmx_pciercx_cfg020_s {
-                uint32_t reserved_24_31:8;
+                uint32_t reserved_25_31:7;
+                uint32_t pvm:1;
                 uint32_t m64:1;
                 uint32_t mme:3;
                 uint32_t mmc:3;
@@ -445,12 +518,24 @@ union cvmx_pciercx_cfg020 {
                 uint32_t ncp:8;
                 uint32_t msicid:8;
         } s;
-        struct cvmx_pciercx_cfg020_s cn52xx;
-        struct cvmx_pciercx_cfg020_s cn52xxp1;
-        struct cvmx_pciercx_cfg020_s cn56xx;
-        struct cvmx_pciercx_cfg020_s cn56xxp1;
-        struct cvmx_pciercx_cfg020_s cn63xx;
-        struct cvmx_pciercx_cfg020_s cn63xxp1;
+        struct cvmx_pciercx_cfg020_cn52xx {
+                uint32_t reserved_24_31:8;
+                uint32_t m64:1;
+                uint32_t mme:3;
+                uint32_t mmc:3;
+                uint32_t msien:1;
+                uint32_t ncp:8;
+                uint32_t msicid:8;
+        } cn52xx;
+        struct cvmx_pciercx_cfg020_cn52xx cn52xxp1;
+        struct cvmx_pciercx_cfg020_cn52xx cn56xx;
+        struct cvmx_pciercx_cfg020_cn52xx cn56xxp1;
+        struct cvmx_pciercx_cfg020_s cn61xx;
+        struct cvmx_pciercx_cfg020_cn52xx cn63xx;
+        struct cvmx_pciercx_cfg020_cn52xx cn63xxp1;
+        struct cvmx_pciercx_cfg020_cn52xx cn66xx;
+        struct cvmx_pciercx_cfg020_cn52xx cn68xx;
+        struct cvmx_pciercx_cfg020_cn52xx cn68xxp1;
 };
 
 union cvmx_pciercx_cfg021 {
@@ -463,8 +548,12 @@ union cvmx_pciercx_cfg021 {
         struct cvmx_pciercx_cfg021_s cn52xxp1;
         struct cvmx_pciercx_cfg021_s cn56xx;
         struct cvmx_pciercx_cfg021_s cn56xxp1;
+        struct cvmx_pciercx_cfg021_s cn61xx;
         struct cvmx_pciercx_cfg021_s cn63xx;
         struct cvmx_pciercx_cfg021_s cn63xxp1;
+        struct cvmx_pciercx_cfg021_s cn66xx;
+        struct cvmx_pciercx_cfg021_s cn68xx;
+        struct cvmx_pciercx_cfg021_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg022 {
@@ -476,8 +565,12 @@ union cvmx_pciercx_cfg022 {
         struct cvmx_pciercx_cfg022_s cn52xxp1;
         struct cvmx_pciercx_cfg022_s cn56xx;
         struct cvmx_pciercx_cfg022_s cn56xxp1;
+        struct cvmx_pciercx_cfg022_s cn61xx;
         struct cvmx_pciercx_cfg022_s cn63xx;
         struct cvmx_pciercx_cfg022_s cn63xxp1;
+        struct cvmx_pciercx_cfg022_s cn66xx;
+        struct cvmx_pciercx_cfg022_s cn68xx;
+        struct cvmx_pciercx_cfg022_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg023 {
@@ -490,8 +583,12 @@ union cvmx_pciercx_cfg023 {
         struct cvmx_pciercx_cfg023_s cn52xxp1;
         struct cvmx_pciercx_cfg023_s cn56xx;
         struct cvmx_pciercx_cfg023_s cn56xxp1;
+        struct cvmx_pciercx_cfg023_s cn61xx;
         struct cvmx_pciercx_cfg023_s cn63xx;
         struct cvmx_pciercx_cfg023_s cn63xxp1;
+        struct cvmx_pciercx_cfg023_s cn66xx;
+        struct cvmx_pciercx_cfg023_s cn68xx;
+        struct cvmx_pciercx_cfg023_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg028 {
@@ -509,8 +606,12 @@ union cvmx_pciercx_cfg028 {
         struct cvmx_pciercx_cfg028_s cn52xxp1;
         struct cvmx_pciercx_cfg028_s cn56xx;
         struct cvmx_pciercx_cfg028_s cn56xxp1;
+        struct cvmx_pciercx_cfg028_s cn61xx;
         struct cvmx_pciercx_cfg028_s cn63xx;
         struct cvmx_pciercx_cfg028_s cn63xxp1;
+        struct cvmx_pciercx_cfg028_s cn66xx;
+        struct cvmx_pciercx_cfg028_s cn68xx;
+        struct cvmx_pciercx_cfg028_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg029 {
@@ -532,8 +633,12 @@ union cvmx_pciercx_cfg029 {
         struct cvmx_pciercx_cfg029_s cn52xxp1;
         struct cvmx_pciercx_cfg029_s cn56xx;
         struct cvmx_pciercx_cfg029_s cn56xxp1;
+        struct cvmx_pciercx_cfg029_s cn61xx;
         struct cvmx_pciercx_cfg029_s cn63xx;
         struct cvmx_pciercx_cfg029_s cn63xxp1;
+        struct cvmx_pciercx_cfg029_s cn66xx;
+        struct cvmx_pciercx_cfg029_s cn68xx;
+        struct cvmx_pciercx_cfg029_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg030 {
@@ -563,15 +668,20 @@ union cvmx_pciercx_cfg030 {
         struct cvmx_pciercx_cfg030_s cn52xxp1;
         struct cvmx_pciercx_cfg030_s cn56xx;
         struct cvmx_pciercx_cfg030_s cn56xxp1;
+        struct cvmx_pciercx_cfg030_s cn61xx;
         struct cvmx_pciercx_cfg030_s cn63xx;
         struct cvmx_pciercx_cfg030_s cn63xxp1;
+        struct cvmx_pciercx_cfg030_s cn66xx;
+        struct cvmx_pciercx_cfg030_s cn68xx;
+        struct cvmx_pciercx_cfg030_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg031 {
         uint32_t u32;
         struct cvmx_pciercx_cfg031_s {
                 uint32_t pnum:8;
-                uint32_t reserved_22_23:2;
+                uint32_t reserved_23_23:1;
+                uint32_t aspm:1;
                 uint32_t lbnc:1;
                 uint32_t dllarc:1;
                 uint32_t sderc:1;
@@ -582,12 +692,28 @@ union cvmx_pciercx_cfg031 {
                 uint32_t mlw:6;
                 uint32_t mls:4;
         } s;
-        struct cvmx_pciercx_cfg031_s cn52xx;
-        struct cvmx_pciercx_cfg031_s cn52xxp1;
-        struct cvmx_pciercx_cfg031_s cn56xx;
-        struct cvmx_pciercx_cfg031_s cn56xxp1;
-        struct cvmx_pciercx_cfg031_s cn63xx;
-        struct cvmx_pciercx_cfg031_s cn63xxp1;
+        struct cvmx_pciercx_cfg031_cn52xx {
+                uint32_t pnum:8;
+                uint32_t reserved_22_23:2;
+                uint32_t lbnc:1;
+                uint32_t dllarc:1;
+                uint32_t sderc:1;
+                uint32_t cpm:1;
+                uint32_t l1el:3;
+                uint32_t l0el:3;
+                uint32_t aslpms:2;
+                uint32_t mlw:6;
+                uint32_t mls:4;
+        } cn52xx;
+        struct cvmx_pciercx_cfg031_cn52xx cn52xxp1;
+        struct cvmx_pciercx_cfg031_cn52xx cn56xx;
+        struct cvmx_pciercx_cfg031_cn52xx cn56xxp1;
+        struct cvmx_pciercx_cfg031_s cn61xx;
+        struct cvmx_pciercx_cfg031_cn52xx cn63xx;
+        struct cvmx_pciercx_cfg031_cn52xx cn63xxp1;
+        struct cvmx_pciercx_cfg031_s cn66xx;
+        struct cvmx_pciercx_cfg031_s cn68xx;
+        struct cvmx_pciercx_cfg031_cn52xx cn68xxp1;
 };
 
 union cvmx_pciercx_cfg032 {
@@ -618,8 +744,12 @@ union cvmx_pciercx_cfg032 {
         struct cvmx_pciercx_cfg032_s cn52xxp1;
         struct cvmx_pciercx_cfg032_s cn56xx;
         struct cvmx_pciercx_cfg032_s cn56xxp1;
+        struct cvmx_pciercx_cfg032_s cn61xx;
         struct cvmx_pciercx_cfg032_s cn63xx;
         struct cvmx_pciercx_cfg032_s cn63xxp1;
+        struct cvmx_pciercx_cfg032_s cn66xx;
+        struct cvmx_pciercx_cfg032_s cn68xx;
+        struct cvmx_pciercx_cfg032_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg033 {
@@ -642,8 +772,12 @@ union cvmx_pciercx_cfg033 {
         struct cvmx_pciercx_cfg033_s cn52xxp1;
         struct cvmx_pciercx_cfg033_s cn56xx;
         struct cvmx_pciercx_cfg033_s cn56xxp1;
+        struct cvmx_pciercx_cfg033_s cn61xx;
         struct cvmx_pciercx_cfg033_s cn63xx;
         struct cvmx_pciercx_cfg033_s cn63xxp1;
+        struct cvmx_pciercx_cfg033_s cn66xx;
+        struct cvmx_pciercx_cfg033_s cn68xx;
+        struct cvmx_pciercx_cfg033_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg034 {
@@ -676,8 +810,12 @@ union cvmx_pciercx_cfg034 {
         struct cvmx_pciercx_cfg034_s cn52xxp1;
         struct cvmx_pciercx_cfg034_s cn56xx;
         struct cvmx_pciercx_cfg034_s cn56xxp1;
+        struct cvmx_pciercx_cfg034_s cn61xx;
         struct cvmx_pciercx_cfg034_s cn63xx;
         struct cvmx_pciercx_cfg034_s cn63xxp1;
+        struct cvmx_pciercx_cfg034_s cn66xx;
+        struct cvmx_pciercx_cfg034_s cn68xx;
+        struct cvmx_pciercx_cfg034_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg035 {
@@ -696,8 +834,12 @@ union cvmx_pciercx_cfg035 {
         struct cvmx_pciercx_cfg035_s cn52xxp1;
         struct cvmx_pciercx_cfg035_s cn56xx;
         struct cvmx_pciercx_cfg035_s cn56xxp1;
+        struct cvmx_pciercx_cfg035_s cn61xx;
         struct cvmx_pciercx_cfg035_s cn63xx;
         struct cvmx_pciercx_cfg035_s cn63xxp1;
+        struct cvmx_pciercx_cfg035_s cn66xx;
+        struct cvmx_pciercx_cfg035_s cn68xx;
+        struct cvmx_pciercx_cfg035_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg036 {
@@ -712,38 +854,95 @@ union cvmx_pciercx_cfg036 {
         struct cvmx_pciercx_cfg036_s cn52xxp1;
         struct cvmx_pciercx_cfg036_s cn56xx;
         struct cvmx_pciercx_cfg036_s cn56xxp1;
+        struct cvmx_pciercx_cfg036_s cn61xx;
         struct cvmx_pciercx_cfg036_s cn63xx;
         struct cvmx_pciercx_cfg036_s cn63xxp1;
+        struct cvmx_pciercx_cfg036_s cn66xx;
+        struct cvmx_pciercx_cfg036_s cn68xx;
+        struct cvmx_pciercx_cfg036_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg037 {
         uint32_t u32;
         struct cvmx_pciercx_cfg037_s {
-                uint32_t reserved_5_31:27;
+                uint32_t reserved_14_31:18;
+                uint32_t tph:2;
+                uint32_t reserved_11_11:1;
+                uint32_t noroprpr:1;
+                uint32_t atom128s:1;
+                uint32_t atom64s:1;
+                uint32_t atom32s:1;
+                uint32_t atom_ops:1;
+                uint32_t reserved_5_5:1;
                 uint32_t ctds:1;
                 uint32_t ctrs:4;
         } s;
-        struct cvmx_pciercx_cfg037_s cn52xx;
-        struct cvmx_pciercx_cfg037_s cn52xxp1;
-        struct cvmx_pciercx_cfg037_s cn56xx;
-        struct cvmx_pciercx_cfg037_s cn56xxp1;
-        struct cvmx_pciercx_cfg037_s cn63xx;
-        struct cvmx_pciercx_cfg037_s cn63xxp1;
+        struct cvmx_pciercx_cfg037_cn52xx {
+                uint32_t reserved_5_31:27;
+                uint32_t ctds:1;
+                uint32_t ctrs:4;
+        } cn52xx;
+        struct cvmx_pciercx_cfg037_cn52xx cn52xxp1;
+        struct cvmx_pciercx_cfg037_cn52xx cn56xx;
+        struct cvmx_pciercx_cfg037_cn52xx cn56xxp1;
+        struct cvmx_pciercx_cfg037_cn61xx {
+                uint32_t reserved_14_31:18;
+                uint32_t tph:2;
+                uint32_t reserved_11_11:1;
+                uint32_t noroprpr:1;
+                uint32_t atom128s:1;
+                uint32_t atom64s:1;
+                uint32_t atom32s:1;
+                uint32_t atom_ops:1;
+                uint32_t ari_fw:1;
+                uint32_t ctds:1;
+                uint32_t ctrs:4;
+        } cn61xx;
+        struct cvmx_pciercx_cfg037_cn52xx cn63xx;
+        struct cvmx_pciercx_cfg037_cn52xx cn63xxp1;
+        struct cvmx_pciercx_cfg037_cn66xx {
+                uint32_t reserved_14_31:18;
+                uint32_t tph:2;
+                uint32_t reserved_11_11:1;
+                uint32_t noroprpr:1;
+                uint32_t atom128s:1;
+                uint32_t atom64s:1;
+                uint32_t atom32s:1;
+                uint32_t atom_ops:1;
+                uint32_t ari:1;
+                uint32_t ctds:1;
+                uint32_t ctrs:4;
+        } cn66xx;
+        struct cvmx_pciercx_cfg037_cn66xx cn68xx;
+        struct cvmx_pciercx_cfg037_cn66xx cn68xxp1;
 };
 
 union cvmx_pciercx_cfg038 {
         uint32_t u32;
         struct cvmx_pciercx_cfg038_s {
-                uint32_t reserved_5_31:27;
+                uint32_t reserved_10_31:22;
+                uint32_t id0_cp:1;
+                uint32_t id0_rq:1;
+                uint32_t atom_op_eb:1;
+                uint32_t atom_op:1;
+                uint32_t ari:1;
                 uint32_t ctd:1;
                 uint32_t ctv:4;
         } s;
-        struct cvmx_pciercx_cfg038_s cn52xx;
-        struct cvmx_pciercx_cfg038_s cn52xxp1;
-        struct cvmx_pciercx_cfg038_s cn56xx;
-        struct cvmx_pciercx_cfg038_s cn56xxp1;
-        struct cvmx_pciercx_cfg038_s cn63xx;
-        struct cvmx_pciercx_cfg038_s cn63xxp1;
+        struct cvmx_pciercx_cfg038_cn52xx {
+                uint32_t reserved_5_31:27;
+                uint32_t ctd:1;
+                uint32_t ctv:4;
+        } cn52xx;
+        struct cvmx_pciercx_cfg038_cn52xx cn52xxp1;
+        struct cvmx_pciercx_cfg038_cn52xx cn56xx;
+        struct cvmx_pciercx_cfg038_cn52xx cn56xxp1;
+        struct cvmx_pciercx_cfg038_s cn61xx;
+        struct cvmx_pciercx_cfg038_cn52xx cn63xx;
+        struct cvmx_pciercx_cfg038_cn52xx cn63xxp1;
+        struct cvmx_pciercx_cfg038_s cn66xx;
+        struct cvmx_pciercx_cfg038_s cn68xx;
+        struct cvmx_pciercx_cfg038_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg039 {
@@ -760,8 +959,12 @@ union cvmx_pciercx_cfg039 {
         struct cvmx_pciercx_cfg039_cn52xx cn52xxp1;
         struct cvmx_pciercx_cfg039_cn52xx cn56xx;
         struct cvmx_pciercx_cfg039_cn52xx cn56xxp1;
+        struct cvmx_pciercx_cfg039_s cn61xx;
         struct cvmx_pciercx_cfg039_s cn63xx;
         struct cvmx_pciercx_cfg039_cn52xx cn63xxp1;
+        struct cvmx_pciercx_cfg039_s cn66xx;
+        struct cvmx_pciercx_cfg039_s cn68xx;
+        struct cvmx_pciercx_cfg039_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg040 {
@@ -785,8 +988,12 @@ union cvmx_pciercx_cfg040 {
         struct cvmx_pciercx_cfg040_cn52xx cn52xxp1;
         struct cvmx_pciercx_cfg040_cn52xx cn56xx;
         struct cvmx_pciercx_cfg040_cn52xx cn56xxp1;
+        struct cvmx_pciercx_cfg040_s cn61xx;
         struct cvmx_pciercx_cfg040_s cn63xx;
         struct cvmx_pciercx_cfg040_s cn63xxp1;
+        struct cvmx_pciercx_cfg040_s cn66xx;
+        struct cvmx_pciercx_cfg040_s cn68xx;
+        struct cvmx_pciercx_cfg040_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg041 {
@@ -798,8 +1005,12 @@ union cvmx_pciercx_cfg041 {
         struct cvmx_pciercx_cfg041_s cn52xxp1;
         struct cvmx_pciercx_cfg041_s cn56xx;
         struct cvmx_pciercx_cfg041_s cn56xxp1;
+        struct cvmx_pciercx_cfg041_s cn61xx;
         struct cvmx_pciercx_cfg041_s cn63xx;
         struct cvmx_pciercx_cfg041_s cn63xxp1;
+        struct cvmx_pciercx_cfg041_s cn66xx;
+        struct cvmx_pciercx_cfg041_s cn68xx;
+        struct cvmx_pciercx_cfg041_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg042 {
@@ -811,8 +1022,12 @@ union cvmx_pciercx_cfg042 {
         struct cvmx_pciercx_cfg042_s cn52xxp1;
         struct cvmx_pciercx_cfg042_s cn56xx;
         struct cvmx_pciercx_cfg042_s cn56xxp1;
+        struct cvmx_pciercx_cfg042_s cn61xx;
         struct cvmx_pciercx_cfg042_s cn63xx;
         struct cvmx_pciercx_cfg042_s cn63xxp1;
+        struct cvmx_pciercx_cfg042_s cn66xx;
+        struct cvmx_pciercx_cfg042_s cn68xx;
+        struct cvmx_pciercx_cfg042_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg064 {
@@ -826,14 +1041,20 @@ union cvmx_pciercx_cfg064 {
         struct cvmx_pciercx_cfg064_s cn52xxp1;
         struct cvmx_pciercx_cfg064_s cn56xx;
         struct cvmx_pciercx_cfg064_s cn56xxp1;
+        struct cvmx_pciercx_cfg064_s cn61xx;
         struct cvmx_pciercx_cfg064_s cn63xx;
         struct cvmx_pciercx_cfg064_s cn63xxp1;
+        struct cvmx_pciercx_cfg064_s cn66xx;
+        struct cvmx_pciercx_cfg064_s cn68xx;
+        struct cvmx_pciercx_cfg064_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg065 {
         uint32_t u32;
         struct cvmx_pciercx_cfg065_s {
-                uint32_t reserved_21_31:11;
+                uint32_t reserved_25_31:7;
+                uint32_t uatombs:1;
+                uint32_t reserved_21_23:3;
                 uint32_t ures:1;
                 uint32_t ecrces:1;
                 uint32_t mtlps:1;
@@ -848,18 +1069,39 @@ union cvmx_pciercx_cfg065 {
                 uint32_t dlpes:1;
                 uint32_t reserved_0_3:4;
         } s;
-        struct cvmx_pciercx_cfg065_s cn52xx;
-        struct cvmx_pciercx_cfg065_s cn52xxp1;
-        struct cvmx_pciercx_cfg065_s cn56xx;
-        struct cvmx_pciercx_cfg065_s cn56xxp1;
-        struct cvmx_pciercx_cfg065_s cn63xx;
-        struct cvmx_pciercx_cfg065_s cn63xxp1;
+        struct cvmx_pciercx_cfg065_cn52xx {
+                uint32_t reserved_21_31:11;
+                uint32_t ures:1;
+                uint32_t ecrces:1;
+                uint32_t mtlps:1;
+                uint32_t ros:1;
+                uint32_t ucs:1;
+                uint32_t cas:1;
+                uint32_t cts:1;
+                uint32_t fcpes:1;
+                uint32_t ptlps:1;
+                uint32_t reserved_6_11:6;
+                uint32_t sdes:1;
+                uint32_t dlpes:1;
+                uint32_t reserved_0_3:4;
+        } cn52xx;
+        struct cvmx_pciercx_cfg065_cn52xx cn52xxp1;
+        struct cvmx_pciercx_cfg065_cn52xx cn56xx;
+        struct cvmx_pciercx_cfg065_cn52xx cn56xxp1;
+        struct cvmx_pciercx_cfg065_s cn61xx;
+        struct cvmx_pciercx_cfg065_cn52xx cn63xx;
+        struct cvmx_pciercx_cfg065_cn52xx cn63xxp1;
+        struct cvmx_pciercx_cfg065_s cn66xx;
+        struct cvmx_pciercx_cfg065_s cn68xx;
+        struct cvmx_pciercx_cfg065_cn52xx cn68xxp1;
 };
 
 union cvmx_pciercx_cfg066 {
         uint32_t u32;
         struct cvmx_pciercx_cfg066_s {
-                uint32_t reserved_21_31:11;
+                uint32_t reserved_25_31:7;
+                uint32_t uatombm:1;
+                uint32_t reserved_21_23:3;
                 uint32_t urem:1;
                 uint32_t ecrcem:1;
                 uint32_t mtlpm:1;
@@ -874,18 +1116,39 @@ union cvmx_pciercx_cfg066 {
                 uint32_t dlpem:1;
                 uint32_t reserved_0_3:4;
         } s;
-        struct cvmx_pciercx_cfg066_s cn52xx;
-        struct cvmx_pciercx_cfg066_s cn52xxp1;
-        struct cvmx_pciercx_cfg066_s cn56xx;
-        struct cvmx_pciercx_cfg066_s cn56xxp1;
-        struct cvmx_pciercx_cfg066_s cn63xx;
-        struct cvmx_pciercx_cfg066_s cn63xxp1;
+        struct cvmx_pciercx_cfg066_cn52xx {
+                uint32_t reserved_21_31:11;
+                uint32_t urem:1;
+                uint32_t ecrcem:1;
+                uint32_t mtlpm:1;
+                uint32_t rom:1;
+                uint32_t ucm:1;
+                uint32_t cam:1;
+                uint32_t ctm:1;
+                uint32_t fcpem:1;
+                uint32_t ptlpm:1;
+                uint32_t reserved_6_11:6;
+                uint32_t sdem:1;
+                uint32_t dlpem:1;
+                uint32_t reserved_0_3:4;
+        } cn52xx;
+        struct cvmx_pciercx_cfg066_cn52xx cn52xxp1;
+        struct cvmx_pciercx_cfg066_cn52xx cn56xx;
+        struct cvmx_pciercx_cfg066_cn52xx cn56xxp1;
+        struct cvmx_pciercx_cfg066_s cn61xx;
+        struct cvmx_pciercx_cfg066_cn52xx cn63xx;
+        struct cvmx_pciercx_cfg066_cn52xx cn63xxp1;
+        struct cvmx_pciercx_cfg066_s cn66xx;
+        struct cvmx_pciercx_cfg066_s cn68xx;
+        struct cvmx_pciercx_cfg066_cn52xx cn68xxp1;
 };
 
 union cvmx_pciercx_cfg067 {
         uint32_t u32;
         struct cvmx_pciercx_cfg067_s {
-                uint32_t reserved_21_31:11;
+                uint32_t reserved_25_31:7;
+                uint32_t uatombs:1;
+                uint32_t reserved_21_23:3;
                 uint32_t ures:1;
                 uint32_t ecrces:1;
                 uint32_t mtlps:1;
@@ -900,12 +1163,31 @@ union cvmx_pciercx_cfg067 {
                 uint32_t dlpes:1;
                 uint32_t reserved_0_3:4;
         } s;
-        struct cvmx_pciercx_cfg067_s cn52xx;
-        struct cvmx_pciercx_cfg067_s cn52xxp1;
-        struct cvmx_pciercx_cfg067_s cn56xx;
-        struct cvmx_pciercx_cfg067_s cn56xxp1;
-        struct cvmx_pciercx_cfg067_s cn63xx;
-        struct cvmx_pciercx_cfg067_s cn63xxp1;
+        struct cvmx_pciercx_cfg067_cn52xx {
+                uint32_t reserved_21_31:11;
+                uint32_t ures:1;
+                uint32_t ecrces:1;
+                uint32_t mtlps:1;
+                uint32_t ros:1;
+                uint32_t ucs:1;
+                uint32_t cas:1;
+                uint32_t cts:1;
+                uint32_t fcpes:1;
+                uint32_t ptlps:1;
+                uint32_t reserved_6_11:6;
+                uint32_t sdes:1;
+                uint32_t dlpes:1;
+                uint32_t reserved_0_3:4;
+        } cn52xx;
+        struct cvmx_pciercx_cfg067_cn52xx cn52xxp1;
+        struct cvmx_pciercx_cfg067_cn52xx cn56xx;
+        struct cvmx_pciercx_cfg067_cn52xx cn56xxp1;
+        struct cvmx_pciercx_cfg067_s cn61xx;
+        struct cvmx_pciercx_cfg067_cn52xx cn63xx;
+        struct cvmx_pciercx_cfg067_cn52xx cn63xxp1;
+        struct cvmx_pciercx_cfg067_s cn66xx;
+        struct cvmx_pciercx_cfg067_s cn68xx;
+        struct cvmx_pciercx_cfg067_cn52xx cn68xxp1;
 };
 
 union cvmx_pciercx_cfg068 {
@@ -925,8 +1207,12 @@ union cvmx_pciercx_cfg068 {
         struct cvmx_pciercx_cfg068_s cn52xxp1;
         struct cvmx_pciercx_cfg068_s cn56xx;
         struct cvmx_pciercx_cfg068_s cn56xxp1;
+        struct cvmx_pciercx_cfg068_s cn61xx;
         struct cvmx_pciercx_cfg068_s cn63xx;
         struct cvmx_pciercx_cfg068_s cn63xxp1;
+        struct cvmx_pciercx_cfg068_s cn66xx;
+        struct cvmx_pciercx_cfg068_s cn68xx;
+        struct cvmx_pciercx_cfg068_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg069 {
@@ -946,8 +1232,12 @@ union cvmx_pciercx_cfg069 {
         struct cvmx_pciercx_cfg069_s cn52xxp1;
         struct cvmx_pciercx_cfg069_s cn56xx;
         struct cvmx_pciercx_cfg069_s cn56xxp1;
+        struct cvmx_pciercx_cfg069_s cn61xx;
         struct cvmx_pciercx_cfg069_s cn63xx;
         struct cvmx_pciercx_cfg069_s cn63xxp1;
+        struct cvmx_pciercx_cfg069_s cn66xx;
+        struct cvmx_pciercx_cfg069_s cn68xx;
+        struct cvmx_pciercx_cfg069_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg070 {
@@ -964,8 +1254,12 @@ union cvmx_pciercx_cfg070 {
         struct cvmx_pciercx_cfg070_s cn52xxp1;
         struct cvmx_pciercx_cfg070_s cn56xx;
         struct cvmx_pciercx_cfg070_s cn56xxp1;
+        struct cvmx_pciercx_cfg070_s cn61xx;
         struct cvmx_pciercx_cfg070_s cn63xx;
         struct cvmx_pciercx_cfg070_s cn63xxp1;
+        struct cvmx_pciercx_cfg070_s cn66xx;
+        struct cvmx_pciercx_cfg070_s cn68xx;
+        struct cvmx_pciercx_cfg070_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg071 {
@@ -977,8 +1271,12 @@ union cvmx_pciercx_cfg071 {
         struct cvmx_pciercx_cfg071_s cn52xxp1;
         struct cvmx_pciercx_cfg071_s cn56xx;
         struct cvmx_pciercx_cfg071_s cn56xxp1;
+        struct cvmx_pciercx_cfg071_s cn61xx;
         struct cvmx_pciercx_cfg071_s cn63xx;
         struct cvmx_pciercx_cfg071_s cn63xxp1;
+        struct cvmx_pciercx_cfg071_s cn66xx;
+        struct cvmx_pciercx_cfg071_s cn68xx;
+        struct cvmx_pciercx_cfg071_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg072 {
@@ -990,8 +1288,12 @@ union cvmx_pciercx_cfg072 {
         struct cvmx_pciercx_cfg072_s cn52xxp1;
         struct cvmx_pciercx_cfg072_s cn56xx;
         struct cvmx_pciercx_cfg072_s cn56xxp1;
+        struct cvmx_pciercx_cfg072_s cn61xx;
         struct cvmx_pciercx_cfg072_s cn63xx;
         struct cvmx_pciercx_cfg072_s cn63xxp1;
+        struct cvmx_pciercx_cfg072_s cn66xx;
+        struct cvmx_pciercx_cfg072_s cn68xx;
+        struct cvmx_pciercx_cfg072_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg073 {
@@ -1003,8 +1305,12 @@ union cvmx_pciercx_cfg073 {
         struct cvmx_pciercx_cfg073_s cn52xxp1;
         struct cvmx_pciercx_cfg073_s cn56xx;
         struct cvmx_pciercx_cfg073_s cn56xxp1;
+        struct cvmx_pciercx_cfg073_s cn61xx;
         struct cvmx_pciercx_cfg073_s cn63xx;
         struct cvmx_pciercx_cfg073_s cn63xxp1;
+        struct cvmx_pciercx_cfg073_s cn66xx;
+        struct cvmx_pciercx_cfg073_s cn68xx;
+        struct cvmx_pciercx_cfg073_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg074 {
@@ -1016,8 +1322,12 @@ union cvmx_pciercx_cfg074 {
         struct cvmx_pciercx_cfg074_s cn52xxp1;
         struct cvmx_pciercx_cfg074_s cn56xx;
         struct cvmx_pciercx_cfg074_s cn56xxp1;
+        struct cvmx_pciercx_cfg074_s cn61xx;
         struct cvmx_pciercx_cfg074_s cn63xx;
         struct cvmx_pciercx_cfg074_s cn63xxp1;
+        struct cvmx_pciercx_cfg074_s cn66xx;
+        struct cvmx_pciercx_cfg074_s cn68xx;
+        struct cvmx_pciercx_cfg074_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg075 {
@@ -1032,8 +1342,12 @@ union cvmx_pciercx_cfg075 {
         struct cvmx_pciercx_cfg075_s cn52xxp1;
         struct cvmx_pciercx_cfg075_s cn56xx;
         struct cvmx_pciercx_cfg075_s cn56xxp1;
+        struct cvmx_pciercx_cfg075_s cn61xx;
         struct cvmx_pciercx_cfg075_s cn63xx;
         struct cvmx_pciercx_cfg075_s cn63xxp1;
+        struct cvmx_pciercx_cfg075_s cn66xx;
+        struct cvmx_pciercx_cfg075_s cn68xx;
+        struct cvmx_pciercx_cfg075_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg076 {
@@ -1053,8 +1367,12 @@ union cvmx_pciercx_cfg076 {
         struct cvmx_pciercx_cfg076_s cn52xxp1;
         struct cvmx_pciercx_cfg076_s cn56xx;
         struct cvmx_pciercx_cfg076_s cn56xxp1;
+        struct cvmx_pciercx_cfg076_s cn61xx;
         struct cvmx_pciercx_cfg076_s cn63xx;
         struct cvmx_pciercx_cfg076_s cn63xxp1;
+        struct cvmx_pciercx_cfg076_s cn66xx;
+        struct cvmx_pciercx_cfg076_s cn68xx;
+        struct cvmx_pciercx_cfg076_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg077 {
@@ -1067,8 +1385,12 @@ union cvmx_pciercx_cfg077 {
         struct cvmx_pciercx_cfg077_s cn52xxp1;
         struct cvmx_pciercx_cfg077_s cn56xx;
         struct cvmx_pciercx_cfg077_s cn56xxp1;
+        struct cvmx_pciercx_cfg077_s cn61xx;
         struct cvmx_pciercx_cfg077_s cn63xx;
         struct cvmx_pciercx_cfg077_s cn63xxp1;
+        struct cvmx_pciercx_cfg077_s cn66xx;
+        struct cvmx_pciercx_cfg077_s cn68xx;
+        struct cvmx_pciercx_cfg077_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg448 {
@@ -1081,8 +1403,12 @@ union cvmx_pciercx_cfg448 {
         struct cvmx_pciercx_cfg448_s cn52xxp1;
         struct cvmx_pciercx_cfg448_s cn56xx;
         struct cvmx_pciercx_cfg448_s cn56xxp1;
+        struct cvmx_pciercx_cfg448_s cn61xx;
         struct cvmx_pciercx_cfg448_s cn63xx;
         struct cvmx_pciercx_cfg448_s cn63xxp1;
+        struct cvmx_pciercx_cfg448_s cn66xx;
+        struct cvmx_pciercx_cfg448_s cn68xx;
+        struct cvmx_pciercx_cfg448_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg449 {
@@ -1094,8 +1420,12 @@ union cvmx_pciercx_cfg449 {
         struct cvmx_pciercx_cfg449_s cn52xxp1;
         struct cvmx_pciercx_cfg449_s cn56xx;
         struct cvmx_pciercx_cfg449_s cn56xxp1;
+        struct cvmx_pciercx_cfg449_s cn61xx;
         struct cvmx_pciercx_cfg449_s cn63xx;
         struct cvmx_pciercx_cfg449_s cn63xxp1;
+        struct cvmx_pciercx_cfg449_s cn66xx;
+        struct cvmx_pciercx_cfg449_s cn68xx;
+        struct cvmx_pciercx_cfg449_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg450 {
@@ -1112,26 +1442,42 @@ union cvmx_pciercx_cfg450 {
         struct cvmx_pciercx_cfg450_s cn52xxp1;
         struct cvmx_pciercx_cfg450_s cn56xx;
         struct cvmx_pciercx_cfg450_s cn56xxp1;
+        struct cvmx_pciercx_cfg450_s cn61xx;
         struct cvmx_pciercx_cfg450_s cn63xx;
         struct cvmx_pciercx_cfg450_s cn63xxp1;
+        struct cvmx_pciercx_cfg450_s cn66xx;
+        struct cvmx_pciercx_cfg450_s cn68xx;
+        struct cvmx_pciercx_cfg450_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg451 {
         uint32_t u32;
         struct cvmx_pciercx_cfg451_s {
-                uint32_t reserved_30_31:2;
+                uint32_t reserved_31_31:1;
+                uint32_t easpml1:1;
                 uint32_t l1el:3;
                 uint32_t l0el:3;
                 uint32_t n_fts_cc:8;
                 uint32_t n_fts:8;
                 uint32_t ack_freq:8;
         } s;
-        struct cvmx_pciercx_cfg451_s cn52xx;
-        struct cvmx_pciercx_cfg451_s cn52xxp1;
-        struct cvmx_pciercx_cfg451_s cn56xx;
-        struct cvmx_pciercx_cfg451_s cn56xxp1;
-        struct cvmx_pciercx_cfg451_s cn63xx;
-        struct cvmx_pciercx_cfg451_s cn63xxp1;
+        struct cvmx_pciercx_cfg451_cn52xx {
+                uint32_t reserved_30_31:2;
+                uint32_t l1el:3;
+                uint32_t l0el:3;
+                uint32_t n_fts_cc:8;
+                uint32_t n_fts:8;
+                uint32_t ack_freq:8;
+        } cn52xx;
+        struct cvmx_pciercx_cfg451_cn52xx cn52xxp1;
+        struct cvmx_pciercx_cfg451_cn52xx cn56xx;
+        struct cvmx_pciercx_cfg451_cn52xx cn56xxp1;
+        struct cvmx_pciercx_cfg451_s cn61xx;
+        struct cvmx_pciercx_cfg451_cn52xx cn63xx;
+        struct cvmx_pciercx_cfg451_cn52xx cn63xxp1;
+        struct cvmx_pciercx_cfg451_s cn66xx;
+        struct cvmx_pciercx_cfg451_s cn68xx;
+        struct cvmx_pciercx_cfg451_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg452 {
@@ -1155,8 +1501,24 @@ union cvmx_pciercx_cfg452 {
         struct cvmx_pciercx_cfg452_s cn52xxp1;
         struct cvmx_pciercx_cfg452_s cn56xx;
         struct cvmx_pciercx_cfg452_s cn56xxp1;
+        struct cvmx_pciercx_cfg452_cn61xx {
+                uint32_t reserved_22_31:10;
+                uint32_t lme:6;
+                uint32_t reserved_8_15:8;
+                uint32_t flm:1;
+                uint32_t reserved_6_6:1;
+                uint32_t dllle:1;
+                uint32_t reserved_4_4:1;
+                uint32_t ra:1;
+                uint32_t le:1;
+                uint32_t sd:1;
+                uint32_t omr:1;
+        } cn61xx;
         struct cvmx_pciercx_cfg452_s cn63xx;
         struct cvmx_pciercx_cfg452_s cn63xxp1;
+        struct cvmx_pciercx_cfg452_cn61xx cn66xx;
+        struct cvmx_pciercx_cfg452_cn61xx cn68xx;
+        struct cvmx_pciercx_cfg452_cn61xx cn68xxp1;
 };
 
 union cvmx_pciercx_cfg453 {
@@ -1172,13 +1534,26 @@ union cvmx_pciercx_cfg453 {
         struct cvmx_pciercx_cfg453_s cn52xxp1;
         struct cvmx_pciercx_cfg453_s cn56xx;
         struct cvmx_pciercx_cfg453_s cn56xxp1;
+        struct cvmx_pciercx_cfg453_s cn61xx;
         struct cvmx_pciercx_cfg453_s cn63xx;
         struct cvmx_pciercx_cfg453_s cn63xxp1;
+        struct cvmx_pciercx_cfg453_s cn66xx;
+        struct cvmx_pciercx_cfg453_s cn68xx;
+        struct cvmx_pciercx_cfg453_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg454 {
         uint32_t u32;
         struct cvmx_pciercx_cfg454_s {
+                uint32_t cx_nfunc:3;
+                uint32_t tmfcwt:5;
+                uint32_t tmanlt:5;
+                uint32_t tmrt:5;
+                uint32_t reserved_11_13:3;
+                uint32_t nskps:3;
+                uint32_t reserved_0_7:8;
+        } s;
+        struct cvmx_pciercx_cfg454_cn52xx {
                 uint32_t reserved_29_31:3;
                 uint32_t tmfcwt:5;
                 uint32_t tmanlt:5;
@@ -1187,13 +1562,23 @@ union cvmx_pciercx_cfg454 {
                 uint32_t nskps:3;
                 uint32_t reserved_4_7:4;
                 uint32_t ntss:4;
-        } s;
-        struct cvmx_pciercx_cfg454_s cn52xx;
-        struct cvmx_pciercx_cfg454_s cn52xxp1;
-        struct cvmx_pciercx_cfg454_s cn56xx;
-        struct cvmx_pciercx_cfg454_s cn56xxp1;
-        struct cvmx_pciercx_cfg454_s cn63xx;
-        struct cvmx_pciercx_cfg454_s cn63xxp1;
+        } cn52xx;
+        struct cvmx_pciercx_cfg454_cn52xx cn52xxp1;
+        struct cvmx_pciercx_cfg454_cn52xx cn56xx;
+        struct cvmx_pciercx_cfg454_cn52xx cn56xxp1;
+        struct cvmx_pciercx_cfg454_cn61xx {
+                uint32_t cx_nfunc:3;
+                uint32_t tmfcwt:5;
+                uint32_t tmanlt:5;
+                uint32_t tmrt:5;
+                uint32_t reserved_8_13:6;
+                uint32_t mfuncn:8;
+        } cn61xx;
+        struct cvmx_pciercx_cfg454_cn52xx cn63xx;
+        struct cvmx_pciercx_cfg454_cn52xx cn63xxp1;
+        struct cvmx_pciercx_cfg454_cn61xx cn66xx;
+        struct cvmx_pciercx_cfg454_cn61xx cn68xx;
+        struct cvmx_pciercx_cfg454_cn52xx cn68xxp1;
 };
 
 union cvmx_pciercx_cfg455 {
@@ -1223,23 +1608,37 @@ union cvmx_pciercx_cfg455 {
         struct cvmx_pciercx_cfg455_s cn52xxp1;
         struct cvmx_pciercx_cfg455_s cn56xx;
         struct cvmx_pciercx_cfg455_s cn56xxp1;
+        struct cvmx_pciercx_cfg455_s cn61xx;
         struct cvmx_pciercx_cfg455_s cn63xx;
         struct cvmx_pciercx_cfg455_s cn63xxp1;
+        struct cvmx_pciercx_cfg455_s cn66xx;
+        struct cvmx_pciercx_cfg455_s cn68xx;
+        struct cvmx_pciercx_cfg455_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg456 {
         uint32_t u32;
         struct cvmx_pciercx_cfg456_s {
-                uint32_t reserved_2_31:30;
+                uint32_t reserved_4_31:28;
+                uint32_t m_handle_flush:1;
+                uint32_t m_dabort_4ucpl:1;
                 uint32_t m_vend1_drp:1;
                 uint32_t m_vend0_drp:1;
         } s;
-        struct cvmx_pciercx_cfg456_s cn52xx;
-        struct cvmx_pciercx_cfg456_s cn52xxp1;
-        struct cvmx_pciercx_cfg456_s cn56xx;
-        struct cvmx_pciercx_cfg456_s cn56xxp1;
-        struct cvmx_pciercx_cfg456_s cn63xx;
-        struct cvmx_pciercx_cfg456_s cn63xxp1;
+        struct cvmx_pciercx_cfg456_cn52xx {
+                uint32_t reserved_2_31:30;
+                uint32_t m_vend1_drp:1;
+                uint32_t m_vend0_drp:1;
+        } cn52xx;
+        struct cvmx_pciercx_cfg456_cn52xx cn52xxp1;
+        struct cvmx_pciercx_cfg456_cn52xx cn56xx;
+        struct cvmx_pciercx_cfg456_cn52xx cn56xxp1;
+        struct cvmx_pciercx_cfg456_s cn61xx;
+        struct cvmx_pciercx_cfg456_cn52xx cn63xx;
+        struct cvmx_pciercx_cfg456_cn52xx cn63xxp1;
+        struct cvmx_pciercx_cfg456_s cn66xx;
+        struct cvmx_pciercx_cfg456_s cn68xx;
+        struct cvmx_pciercx_cfg456_cn52xx cn68xxp1;
 };
 
 union cvmx_pciercx_cfg458 {
@@ -1251,8 +1650,12 @@ union cvmx_pciercx_cfg458 {
         struct cvmx_pciercx_cfg458_s cn52xxp1;
         struct cvmx_pciercx_cfg458_s cn56xx;
         struct cvmx_pciercx_cfg458_s cn56xxp1;
+        struct cvmx_pciercx_cfg458_s cn61xx;
         struct cvmx_pciercx_cfg458_s cn63xx;
         struct cvmx_pciercx_cfg458_s cn63xxp1;
+        struct cvmx_pciercx_cfg458_s cn66xx;
+        struct cvmx_pciercx_cfg458_s cn68xx;
+        struct cvmx_pciercx_cfg458_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg459 {
@@ -1264,8 +1667,12 @@ union cvmx_pciercx_cfg459 {
         struct cvmx_pciercx_cfg459_s cn52xxp1;
         struct cvmx_pciercx_cfg459_s cn56xx;
         struct cvmx_pciercx_cfg459_s cn56xxp1;
+        struct cvmx_pciercx_cfg459_s cn61xx;
         struct cvmx_pciercx_cfg459_s cn63xx;
         struct cvmx_pciercx_cfg459_s cn63xxp1;
+        struct cvmx_pciercx_cfg459_s cn66xx;
+        struct cvmx_pciercx_cfg459_s cn68xx;
+        struct cvmx_pciercx_cfg459_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg460 {
@@ -1279,8 +1686,12 @@ union cvmx_pciercx_cfg460 {
         struct cvmx_pciercx_cfg460_s cn52xxp1;
         struct cvmx_pciercx_cfg460_s cn56xx;
         struct cvmx_pciercx_cfg460_s cn56xxp1;
+        struct cvmx_pciercx_cfg460_s cn61xx;
         struct cvmx_pciercx_cfg460_s cn63xx;
         struct cvmx_pciercx_cfg460_s cn63xxp1;
+        struct cvmx_pciercx_cfg460_s cn66xx;
+        struct cvmx_pciercx_cfg460_s cn68xx;
+        struct cvmx_pciercx_cfg460_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg461 {
@@ -1294,8 +1705,12 @@ union cvmx_pciercx_cfg461 {
         struct cvmx_pciercx_cfg461_s cn52xxp1;
         struct cvmx_pciercx_cfg461_s cn56xx;
         struct cvmx_pciercx_cfg461_s cn56xxp1;
+        struct cvmx_pciercx_cfg461_s cn61xx;
         struct cvmx_pciercx_cfg461_s cn63xx;
         struct cvmx_pciercx_cfg461_s cn63xxp1;
+        struct cvmx_pciercx_cfg461_s cn66xx;
+        struct cvmx_pciercx_cfg461_s cn68xx;
+        struct cvmx_pciercx_cfg461_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg462 {
@@ -1309,8 +1724,12 @@ union cvmx_pciercx_cfg462 {
         struct cvmx_pciercx_cfg462_s cn52xxp1;
         struct cvmx_pciercx_cfg462_s cn56xx;
         struct cvmx_pciercx_cfg462_s cn56xxp1;
+        struct cvmx_pciercx_cfg462_s cn61xx;
         struct cvmx_pciercx_cfg462_s cn63xx;
         struct cvmx_pciercx_cfg462_s cn63xxp1;
+        struct cvmx_pciercx_cfg462_s cn66xx;
+        struct cvmx_pciercx_cfg462_s cn68xx;
+        struct cvmx_pciercx_cfg462_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg463 {
@@ -1325,8 +1744,12 @@ union cvmx_pciercx_cfg463 {
         struct cvmx_pciercx_cfg463_s cn52xxp1;
         struct cvmx_pciercx_cfg463_s cn56xx;
         struct cvmx_pciercx_cfg463_s cn56xxp1;
+        struct cvmx_pciercx_cfg463_s cn61xx;
         struct cvmx_pciercx_cfg463_s cn63xx;
         struct cvmx_pciercx_cfg463_s cn63xxp1;
+        struct cvmx_pciercx_cfg463_s cn66xx;
+        struct cvmx_pciercx_cfg463_s cn68xx;
+        struct cvmx_pciercx_cfg463_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg464 {
@@ -1341,8 +1764,12 @@ union cvmx_pciercx_cfg464 {
         struct cvmx_pciercx_cfg464_s cn52xxp1;
         struct cvmx_pciercx_cfg464_s cn56xx;
         struct cvmx_pciercx_cfg464_s cn56xxp1;
+        struct cvmx_pciercx_cfg464_s cn61xx;
         struct cvmx_pciercx_cfg464_s cn63xx;
         struct cvmx_pciercx_cfg464_s cn63xxp1;
+        struct cvmx_pciercx_cfg464_s cn66xx;
+        struct cvmx_pciercx_cfg464_s cn68xx;
+        struct cvmx_pciercx_cfg464_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg465 {
@@ -1357,8 +1784,12 @@ union cvmx_pciercx_cfg465 {
         struct cvmx_pciercx_cfg465_s cn52xxp1;
         struct cvmx_pciercx_cfg465_s cn56xx;
         struct cvmx_pciercx_cfg465_s cn56xxp1;
+        struct cvmx_pciercx_cfg465_s cn61xx;
         struct cvmx_pciercx_cfg465_s cn63xx;
         struct cvmx_pciercx_cfg465_s cn63xxp1;
+        struct cvmx_pciercx_cfg465_s cn66xx;
+        struct cvmx_pciercx_cfg465_s cn68xx;
+        struct cvmx_pciercx_cfg465_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg466 {
@@ -1376,8 +1807,12 @@ union cvmx_pciercx_cfg466 {
         struct cvmx_pciercx_cfg466_s cn52xxp1;
         struct cvmx_pciercx_cfg466_s cn56xx;
         struct cvmx_pciercx_cfg466_s cn56xxp1;
+        struct cvmx_pciercx_cfg466_s cn61xx;
         struct cvmx_pciercx_cfg466_s cn63xx;
         struct cvmx_pciercx_cfg466_s cn63xxp1;
+        struct cvmx_pciercx_cfg466_s cn66xx;
+        struct cvmx_pciercx_cfg466_s cn68xx;
+        struct cvmx_pciercx_cfg466_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg467 {
@@ -1393,8 +1828,12 @@ union cvmx_pciercx_cfg467 {
         struct cvmx_pciercx_cfg467_s cn52xxp1;
         struct cvmx_pciercx_cfg467_s cn56xx;
         struct cvmx_pciercx_cfg467_s cn56xxp1;
+        struct cvmx_pciercx_cfg467_s cn61xx;
         struct cvmx_pciercx_cfg467_s cn63xx;
         struct cvmx_pciercx_cfg467_s cn63xxp1;
+        struct cvmx_pciercx_cfg467_s cn66xx;
+        struct cvmx_pciercx_cfg467_s cn68xx;
+        struct cvmx_pciercx_cfg467_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg468 {
@@ -1410,8 +1849,12 @@ union cvmx_pciercx_cfg468 {
         struct cvmx_pciercx_cfg468_s cn52xxp1;
         struct cvmx_pciercx_cfg468_s cn56xx;
         struct cvmx_pciercx_cfg468_s cn56xxp1;
+        struct cvmx_pciercx_cfg468_s cn61xx;
         struct cvmx_pciercx_cfg468_s cn63xx;
         struct cvmx_pciercx_cfg468_s cn63xxp1;
+        struct cvmx_pciercx_cfg468_s cn66xx;
+        struct cvmx_pciercx_cfg468_s cn68xx;
+        struct cvmx_pciercx_cfg468_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg490 {
@@ -1426,8 +1869,12 @@ union cvmx_pciercx_cfg490 {
         struct cvmx_pciercx_cfg490_s cn52xxp1;
         struct cvmx_pciercx_cfg490_s cn56xx;
         struct cvmx_pciercx_cfg490_s cn56xxp1;
+        struct cvmx_pciercx_cfg490_s cn61xx;
         struct cvmx_pciercx_cfg490_s cn63xx;
         struct cvmx_pciercx_cfg490_s cn63xxp1;
+        struct cvmx_pciercx_cfg490_s cn66xx;
+        struct cvmx_pciercx_cfg490_s cn68xx;
+        struct cvmx_pciercx_cfg490_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg491 {
@@ -1442,8 +1889,12 @@ union cvmx_pciercx_cfg491 {
         struct cvmx_pciercx_cfg491_s cn52xxp1;
         struct cvmx_pciercx_cfg491_s cn56xx;
         struct cvmx_pciercx_cfg491_s cn56xxp1;
+        struct cvmx_pciercx_cfg491_s cn61xx;
         struct cvmx_pciercx_cfg491_s cn63xx;
         struct cvmx_pciercx_cfg491_s cn63xxp1;
+        struct cvmx_pciercx_cfg491_s cn66xx;
+        struct cvmx_pciercx_cfg491_s cn68xx;
+        struct cvmx_pciercx_cfg491_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg492 {
@@ -1458,8 +1909,12 @@ union cvmx_pciercx_cfg492 {
         struct cvmx_pciercx_cfg492_s cn52xxp1;
         struct cvmx_pciercx_cfg492_s cn56xx;
         struct cvmx_pciercx_cfg492_s cn56xxp1;
+        struct cvmx_pciercx_cfg492_s cn61xx;
         struct cvmx_pciercx_cfg492_s cn63xx;
         struct cvmx_pciercx_cfg492_s cn63xxp1;
+        struct cvmx_pciercx_cfg492_s cn66xx;
+        struct cvmx_pciercx_cfg492_s cn68xx;
+        struct cvmx_pciercx_cfg492_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg515 {
@@ -1473,8 +1928,12 @@ union cvmx_pciercx_cfg515 {
                 uint32_t le:9;
                 uint32_t n_fts:8;
         } s;
+        struct cvmx_pciercx_cfg515_s cn61xx;
         struct cvmx_pciercx_cfg515_s cn63xx;
         struct cvmx_pciercx_cfg515_s cn63xxp1;
+        struct cvmx_pciercx_cfg515_s cn66xx;
+        struct cvmx_pciercx_cfg515_s cn68xx;
+        struct cvmx_pciercx_cfg515_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg516 {
@@ -1486,8 +1945,12 @@ union cvmx_pciercx_cfg516 {
         struct cvmx_pciercx_cfg516_s cn52xxp1;
         struct cvmx_pciercx_cfg516_s cn56xx;
         struct cvmx_pciercx_cfg516_s cn56xxp1;
+        struct cvmx_pciercx_cfg516_s cn61xx;
         struct cvmx_pciercx_cfg516_s cn63xx;
         struct cvmx_pciercx_cfg516_s cn63xxp1;
+        struct cvmx_pciercx_cfg516_s cn66xx;
+        struct cvmx_pciercx_cfg516_s cn68xx;
+        struct cvmx_pciercx_cfg516_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg517 {
@@ -1499,8 +1962,12 @@ union cvmx_pciercx_cfg517 {
         struct cvmx_pciercx_cfg517_s cn52xxp1;
         struct cvmx_pciercx_cfg517_s cn56xx;
         struct cvmx_pciercx_cfg517_s cn56xxp1;
+        struct cvmx_pciercx_cfg517_s cn61xx;
         struct cvmx_pciercx_cfg517_s cn63xx;
         struct cvmx_pciercx_cfg517_s cn63xxp1;
+        struct cvmx_pciercx_cfg517_s cn66xx;
+        struct cvmx_pciercx_cfg517_s cn68xx;
+        struct cvmx_pciercx_cfg517_s cn68xxp1;
 };
 
 #endif
diff --git a/drivers/staging/octeon/cvmx-pcsx-defs.h b/arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
index d45952df5f5..d45952df5f5 100644
--- a/drivers/staging/octeon/cvmx-pcsx-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
diff --git a/drivers/staging/octeon/cvmx-pcsxx-defs.h b/arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
index 55d120fe8ae..55d120fe8ae 100644
--- a/drivers/staging/octeon/cvmx-pcsxx-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
diff --git a/arch/mips/include/asm/octeon/cvmx-pemx-defs.h b/arch/mips/include/asm/octeon/cvmx-pemx-defs.h
new file mode 100644
index 00000000000..be189a2585e
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-pemx-defs.h
@@ -0,0 +1,509 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2011 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_PEMX_DEFS_H__
+#define __CVMX_PEMX_DEFS_H__
+
+#define CVMX_PEMX_BAR1_INDEXX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C00000A8ull) + (((offset) & 15) + ((block_id) & 1) * 0x200000ull) * 8)
+#define CVMX_PEMX_BAR2_MASK(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000130ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_BAR_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000128ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000018ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_BIST_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000420ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_CFG_RD(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000030ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_CFG_WR(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000028ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_CPL_LUT_VALID(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000098ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000000ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_DBG_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000008ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_DBG_INFO_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800C00000A0ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_DIAG_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000020ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_INB_READ_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000138ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_INT_ENB(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000410ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_INT_ENB_INT(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000418ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_INT_SUM(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000408ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_P2N_BAR0_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000080ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_P2N_BAR1_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000088ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_P2N_BAR2_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000090ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_P2P_BARX_END(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C0000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x100000ull) * 16)
+#define CVMX_PEMX_P2P_BARX_START(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C0000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x100000ull) * 16)
+#define CVMX_PEMX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000038ull) + ((block_id) & 1) * 0x1000000ull)
+
+union cvmx_pemx_bar1_indexx {
+        uint64_t u64;
+        struct cvmx_pemx_bar1_indexx_s {
+                uint64_t reserved_20_63:44;
+                uint64_t addr_idx:16;
+                uint64_t ca:1;
+                uint64_t end_swp:2;
+                uint64_t addr_v:1;
+        } s;
+        struct cvmx_pemx_bar1_indexx_s cn61xx;
+        struct cvmx_pemx_bar1_indexx_s cn63xx;
+        struct cvmx_pemx_bar1_indexx_s cn63xxp1;
+        struct cvmx_pemx_bar1_indexx_s cn66xx;
+        struct cvmx_pemx_bar1_indexx_s cn68xx;
+        struct cvmx_pemx_bar1_indexx_s cn68xxp1;
+};
+
+union cvmx_pemx_bar2_mask {
+        uint64_t u64;
+        struct cvmx_pemx_bar2_mask_s {
+                uint64_t reserved_38_63:26;
+                uint64_t mask:35;
+                uint64_t reserved_0_2:3;
+        } s;
+        struct cvmx_pemx_bar2_mask_s cn61xx;
+        struct cvmx_pemx_bar2_mask_s cn66xx;
+        struct cvmx_pemx_bar2_mask_s cn68xx;
+        struct cvmx_pemx_bar2_mask_s cn68xxp1;
+};
+
+union cvmx_pemx_bar_ctl {
+        uint64_t u64;
+        struct cvmx_pemx_bar_ctl_s {
+                uint64_t reserved_7_63:57;
+                uint64_t bar1_siz:3;
+                uint64_t bar2_enb:1;
+                uint64_t bar2_esx:2;
+                uint64_t bar2_cax:1;
+        } s;
+        struct cvmx_pemx_bar_ctl_s cn61xx;
+        struct cvmx_pemx_bar_ctl_s cn63xx;
+        struct cvmx_pemx_bar_ctl_s cn63xxp1;
+        struct cvmx_pemx_bar_ctl_s cn66xx;
+        struct cvmx_pemx_bar_ctl_s cn68xx;
+        struct cvmx_pemx_bar_ctl_s cn68xxp1;
+};
+
+union cvmx_pemx_bist_status {
+        uint64_t u64;
+        struct cvmx_pemx_bist_status_s {
+                uint64_t reserved_8_63:56;
+                uint64_t retry:1;
+                uint64_t rqdata0:1;
+                uint64_t rqdata1:1;
+                uint64_t rqdata2:1;
+                uint64_t rqdata3:1;
+                uint64_t rqhdr1:1;
+                uint64_t rqhdr0:1;
+                uint64_t sot:1;
+        } s;
+        struct cvmx_pemx_bist_status_s cn61xx;
+        struct cvmx_pemx_bist_status_s cn63xx;
+        struct cvmx_pemx_bist_status_s cn63xxp1;
+        struct cvmx_pemx_bist_status_s cn66xx;
+        struct cvmx_pemx_bist_status_s cn68xx;
+        struct cvmx_pemx_bist_status_s cn68xxp1;
+};
+
+union cvmx_pemx_bist_status2 {
+        uint64_t u64;
+        struct cvmx_pemx_bist_status2_s {
+                uint64_t reserved_10_63:54;
+                uint64_t e2p_cpl:1;
+                uint64_t e2p_n:1;
+                uint64_t e2p_p:1;
+                uint64_t peai_p2e:1;
+                uint64_t pef_tpf1:1;
+                uint64_t pef_tpf0:1;
+                uint64_t pef_tnf:1;
+                uint64_t pef_tcf1:1;
+                uint64_t pef_tc0:1;
+                uint64_t ppf:1;
+        } s;
+        struct cvmx_pemx_bist_status2_s cn61xx;
+        struct cvmx_pemx_bist_status2_s cn63xx;
+        struct cvmx_pemx_bist_status2_s cn63xxp1;
+        struct cvmx_pemx_bist_status2_s cn66xx;
+        struct cvmx_pemx_bist_status2_s cn68xx;
+        struct cvmx_pemx_bist_status2_s cn68xxp1;
+};
+
+union cvmx_pemx_cfg_rd {
+        uint64_t u64;
+        struct cvmx_pemx_cfg_rd_s {
+                uint64_t data:32;
+                uint64_t addr:32;
+        } s;
+        struct cvmx_pemx_cfg_rd_s cn61xx;
+        struct cvmx_pemx_cfg_rd_s cn63xx;
+        struct cvmx_pemx_cfg_rd_s cn63xxp1;
+        struct cvmx_pemx_cfg_rd_s cn66xx;
+        struct cvmx_pemx_cfg_rd_s cn68xx;
+        struct cvmx_pemx_cfg_rd_s cn68xxp1;
+};
+
+union cvmx_pemx_cfg_wr {
+        uint64_t u64;
+        struct cvmx_pemx_cfg_wr_s {
+                uint64_t data:32;
+                uint64_t addr:32;
+        } s;
+        struct cvmx_pemx_cfg_wr_s cn61xx;
+        struct cvmx_pemx_cfg_wr_s cn63xx;
+        struct cvmx_pemx_cfg_wr_s cn63xxp1;
+        struct cvmx_pemx_cfg_wr_s cn66xx;
+        struct cvmx_pemx_cfg_wr_s cn68xx;
+        struct cvmx_pemx_cfg_wr_s cn68xxp1;
+};
+
+union cvmx_pemx_cpl_lut_valid {
+        uint64_t u64;
+        struct cvmx_pemx_cpl_lut_valid_s {
+                uint64_t reserved_32_63:32;
+                uint64_t tag:32;
+        } s;
+        struct cvmx_pemx_cpl_lut_valid_s cn61xx;
+        struct cvmx_pemx_cpl_lut_valid_s cn63xx;
+        struct cvmx_pemx_cpl_lut_valid_s cn63xxp1;
+        struct cvmx_pemx_cpl_lut_valid_s cn66xx;
+        struct cvmx_pemx_cpl_lut_valid_s cn68xx;
+        struct cvmx_pemx_cpl_lut_valid_s cn68xxp1;
+};
+
+union cvmx_pemx_ctl_status {
+        uint64_t u64;
+        struct cvmx_pemx_ctl_status_s {
+                uint64_t reserved_48_63:16;
+                uint64_t auto_sd:1;
+                uint64_t dnum:5;
+                uint64_t pbus:8;
+                uint64_t reserved_32_33:2;
+                uint64_t cfg_rtry:16;
+                uint64_t reserved_12_15:4;
+                uint64_t pm_xtoff:1;
+                uint64_t pm_xpme:1;
+                uint64_t ob_p_cmd:1;
+                uint64_t reserved_7_8:2;
+                uint64_t nf_ecrc:1;
+                uint64_t dly_one:1;
+                uint64_t lnk_enb:1;
+                uint64_t ro_ctlp:1;
+                uint64_t fast_lm:1;
+                uint64_t inv_ecrc:1;
+                uint64_t inv_lcrc:1;
+        } s;
+        struct cvmx_pemx_ctl_status_s cn61xx;
+        struct cvmx_pemx_ctl_status_s cn63xx;
+        struct cvmx_pemx_ctl_status_s cn63xxp1;
+        struct cvmx_pemx_ctl_status_s cn66xx;
+        struct cvmx_pemx_ctl_status_s cn68xx;
+        struct cvmx_pemx_ctl_status_s cn68xxp1;
+};
+
+union cvmx_pemx_dbg_info {
+        uint64_t u64;
+        struct cvmx_pemx_dbg_info_s {
+                uint64_t reserved_31_63:33;
+                uint64_t ecrc_e:1;
+                uint64_t rawwpp:1;
+                uint64_t racpp:1;
+                uint64_t ramtlp:1;
+                uint64_t rarwdns:1;
+                uint64_t caar:1;
+                uint64_t racca:1;
+                uint64_t racur:1;
+                uint64_t rauc:1;
+                uint64_t rqo:1;
+                uint64_t fcuv:1;
+                uint64_t rpe:1;
+                uint64_t fcpvwt:1;
+                uint64_t dpeoosd:1;
+                uint64_t rtwdle:1;
+                uint64_t rdwdle:1;
+                uint64_t mre:1;
+                uint64_t rte:1;
+                uint64_t acto:1;
+                uint64_t rvdm:1;
+                uint64_t rumep:1;
+                uint64_t rptamrc:1;
+                uint64_t rpmerc:1;
+                uint64_t rfemrc:1;
+                uint64_t rnfemrc:1;
+                uint64_t rcemrc:1;
+                uint64_t rpoison:1;
+                uint64_t recrce:1;
+                uint64_t rtlplle:1;
+                uint64_t rtlpmal:1;
+                uint64_t spoison:1;
+        } s;
+        struct cvmx_pemx_dbg_info_s cn61xx;
+        struct cvmx_pemx_dbg_info_s cn63xx;
+        struct cvmx_pemx_dbg_info_s cn63xxp1;
+        struct cvmx_pemx_dbg_info_s cn66xx;
+        struct cvmx_pemx_dbg_info_s cn68xx;
+        struct cvmx_pemx_dbg_info_s cn68xxp1;
+};
+
+union cvmx_pemx_dbg_info_en {
+        uint64_t u64;
+        struct cvmx_pemx_dbg_info_en_s {
+                uint64_t reserved_31_63:33;
+                uint64_t ecrc_e:1;
+                uint64_t rawwpp:1;
+                uint64_t racpp:1;
+                uint64_t ramtlp:1;
+                uint64_t rarwdns:1;
+                uint64_t caar:1;
+                uint64_t racca:1;
+                uint64_t racur:1;
+                uint64_t rauc:1;
+                uint64_t rqo:1;
+                uint64_t fcuv:1;
+                uint64_t rpe:1;
+                uint64_t fcpvwt:1;
+                uint64_t dpeoosd:1;
+                uint64_t rtwdle:1;
+                uint64_t rdwdle:1;
+                uint64_t mre:1;
+                uint64_t rte:1;
+                uint64_t acto:1;
+                uint64_t rvdm:1;
+                uint64_t rumep:1;
+                uint64_t rptamrc:1;
+                uint64_t rpmerc:1;
+                uint64_t rfemrc:1;
+                uint64_t rnfemrc:1;
+                uint64_t rcemrc:1;
+                uint64_t rpoison:1;
+                uint64_t recrce:1;
+                uint64_t rtlplle:1;
+                uint64_t rtlpmal:1;
+                uint64_t spoison:1;
+        } s;
+        struct cvmx_pemx_dbg_info_en_s cn61xx;
+        struct cvmx_pemx_dbg_info_en_s cn63xx;
+        struct cvmx_pemx_dbg_info_en_s cn63xxp1;
+        struct cvmx_pemx_dbg_info_en_s cn66xx;
+        struct cvmx_pemx_dbg_info_en_s cn68xx;
+        struct cvmx_pemx_dbg_info_en_s cn68xxp1;
+};
+
+union cvmx_pemx_diag_status {
+        uint64_t u64;
+        struct cvmx_pemx_diag_status_s {
+                uint64_t reserved_4_63:60;
+                uint64_t pm_dst:1;
+                uint64_t pm_stat:1;
+                uint64_t pm_en:1;
+                uint64_t aux_en:1;
+        } s;
+        struct cvmx_pemx_diag_status_s cn61xx;
+        struct cvmx_pemx_diag_status_s cn63xx;
+        struct cvmx_pemx_diag_status_s cn63xxp1;
+        struct cvmx_pemx_diag_status_s cn66xx;
+        struct cvmx_pemx_diag_status_s cn68xx;
+        struct cvmx_pemx_diag_status_s cn68xxp1;
+};
+
+union cvmx_pemx_inb_read_credits {
+        uint64_t u64;
+        struct cvmx_pemx_inb_read_credits_s {
+                uint64_t reserved_6_63:58;
+                uint64_t num:6;
+        } s;
+        struct cvmx_pemx_inb_read_credits_s cn61xx;
+        struct cvmx_pemx_inb_read_credits_s cn66xx;
+        struct cvmx_pemx_inb_read_credits_s cn68xx;
+};
+
+union cvmx_pemx_int_enb {
+        uint64_t u64;
+        struct cvmx_pemx_int_enb_s {
+                uint64_t reserved_14_63:50;
+                uint64_t crs_dr:1;
+                uint64_t crs_er:1;
+                uint64_t rdlk:1;
+                uint64_t exc:1;
+                uint64_t un_bx:1;
+                uint64_t un_b2:1;
+                uint64_t un_b1:1;
+                uint64_t up_bx:1;
+                uint64_t up_b2:1;
+                uint64_t up_b1:1;
+                uint64_t pmem:1;
+                uint64_t pmei:1;
+                uint64_t se:1;
+                uint64_t aeri:1;
+        } s;
+        struct cvmx_pemx_int_enb_s cn61xx;
+        struct cvmx_pemx_int_enb_s cn63xx;
+        struct cvmx_pemx_int_enb_s cn63xxp1;
+        struct cvmx_pemx_int_enb_s cn66xx;
+        struct cvmx_pemx_int_enb_s cn68xx;
+        struct cvmx_pemx_int_enb_s cn68xxp1;
+};
+
+union cvmx_pemx_int_enb_int {
+        uint64_t u64;
+        struct cvmx_pemx_int_enb_int_s {
+                uint64_t reserved_14_63:50;
+                uint64_t crs_dr:1;
+                uint64_t crs_er:1;
+                uint64_t rdlk:1;
+                uint64_t exc:1;
+                uint64_t un_bx:1;
+                uint64_t un_b2:1;
+                uint64_t un_b1:1;
+                uint64_t up_bx:1;
+                uint64_t up_b2:1;
+                uint64_t up_b1:1;
+                uint64_t pmem:1;
+                uint64_t pmei:1;
+                uint64_t se:1;
+                uint64_t aeri:1;
+        } s;
+        struct cvmx_pemx_int_enb_int_s cn61xx;
+        struct cvmx_pemx_int_enb_int_s cn63xx;
+        struct cvmx_pemx_int_enb_int_s cn63xxp1;
+        struct cvmx_pemx_int_enb_int_s cn66xx;
+        struct cvmx_pemx_int_enb_int_s cn68xx;
+        struct cvmx_pemx_int_enb_int_s cn68xxp1;
+};
+
+union cvmx_pemx_int_sum {
+        uint64_t u64;
+        struct cvmx_pemx_int_sum_s {
+                uint64_t reserved_14_63:50;
+                uint64_t crs_dr:1;
+                uint64_t crs_er:1;
+                uint64_t rdlk:1;
+                uint64_t exc:1;
+                uint64_t un_bx:1;
+                uint64_t un_b2:1;
+                uint64_t un_b1:1;
+                uint64_t up_bx:1;
+                uint64_t up_b2:1;
+                uint64_t up_b1:1;
+                uint64_t pmem:1;
+                uint64_t pmei:1;
+                uint64_t se:1;
+                uint64_t aeri:1;
+        } s;
+        struct cvmx_pemx_int_sum_s cn61xx;
+        struct cvmx_pemx_int_sum_s cn63xx;
+        struct cvmx_pemx_int_sum_s cn63xxp1;
+        struct cvmx_pemx_int_sum_s cn66xx;
+        struct cvmx_pemx_int_sum_s cn68xx;
+        struct cvmx_pemx_int_sum_s cn68xxp1;
+};
+
+union cvmx_pemx_p2n_bar0_start {
+        uint64_t u64;
+        struct cvmx_pemx_p2n_bar0_start_s {
+                uint64_t addr:50;
+                uint64_t reserved_0_13:14;
+        } s;
+        struct cvmx_pemx_p2n_bar0_start_s cn61xx;
+        struct cvmx_pemx_p2n_bar0_start_s cn63xx;
+        struct cvmx_pemx_p2n_bar0_start_s cn63xxp1;
+        struct cvmx_pemx_p2n_bar0_start_s cn66xx;
+        struct cvmx_pemx_p2n_bar0_start_s cn68xx;
+        struct cvmx_pemx_p2n_bar0_start_s cn68xxp1;
+};
+
+union cvmx_pemx_p2n_bar1_start {
+        uint64_t u64;
+        struct cvmx_pemx_p2n_bar1_start_s {
+                uint64_t addr:38;
+                uint64_t reserved_0_25:26;
+        } s;
+        struct cvmx_pemx_p2n_bar1_start_s cn61xx;
+        struct cvmx_pemx_p2n_bar1_start_s cn63xx;
+        struct cvmx_pemx_p2n_bar1_start_s cn63xxp1;
+        struct cvmx_pemx_p2n_bar1_start_s cn66xx;
+        struct cvmx_pemx_p2n_bar1_start_s cn68xx;
+        struct cvmx_pemx_p2n_bar1_start_s cn68xxp1;
+};
+
+union cvmx_pemx_p2n_bar2_start {
+        uint64_t u64;
+        struct cvmx_pemx_p2n_bar2_start_s {
+                uint64_t addr:23;
+                uint64_t reserved_0_40:41;
+        } s;
+        struct cvmx_pemx_p2n_bar2_start_s cn61xx;
+        struct cvmx_pemx_p2n_bar2_start_s cn63xx;
+        struct cvmx_pemx_p2n_bar2_start_s cn63xxp1;
+        struct cvmx_pemx_p2n_bar2_start_s cn66xx;
+        struct cvmx_pemx_p2n_bar2_start_s cn68xx;
+        struct cvmx_pemx_p2n_bar2_start_s cn68xxp1;
+};
+
+union cvmx_pemx_p2p_barx_end {
+        uint64_t u64;
+        struct cvmx_pemx_p2p_barx_end_s {
+                uint64_t addr:52;
+                uint64_t reserved_0_11:12;
+        } s;
+        struct cvmx_pemx_p2p_barx_end_s cn63xx;
+        struct cvmx_pemx_p2p_barx_end_s cn63xxp1;
+        struct cvmx_pemx_p2p_barx_end_s cn66xx;
+        struct cvmx_pemx_p2p_barx_end_s cn68xx;
+        struct cvmx_pemx_p2p_barx_end_s cn68xxp1;
+};
+
+union cvmx_pemx_p2p_barx_start {
+        uint64_t u64;
+        struct cvmx_pemx_p2p_barx_start_s {
+                uint64_t addr:52;
+                uint64_t reserved_0_11:12;
+        } s;
+        struct cvmx_pemx_p2p_barx_start_s cn63xx;
+        struct cvmx_pemx_p2p_barx_start_s cn63xxp1;
+        struct cvmx_pemx_p2p_barx_start_s cn66xx;
+        struct cvmx_pemx_p2p_barx_start_s cn68xx;
+        struct cvmx_pemx_p2p_barx_start_s cn68xxp1;
+};
+
+union cvmx_pemx_tlp_credits {
+        uint64_t u64;
+        struct cvmx_pemx_tlp_credits_s {
+                uint64_t reserved_56_63:8;
+                uint64_t peai_ppf:8;
+                uint64_t pem_cpl:8;
+                uint64_t pem_np:8;
+                uint64_t pem_p:8;
+                uint64_t sli_cpl:8;
+                uint64_t sli_np:8;
+                uint64_t sli_p:8;
+        } s;
+        struct cvmx_pemx_tlp_credits_cn61xx {
+                uint64_t reserved_56_63:8;
+                uint64_t peai_ppf:8;
+                uint64_t reserved_24_47:24;
+                uint64_t sli_cpl:8;
+                uint64_t sli_np:8;
+                uint64_t sli_p:8;
+        } cn61xx;
+        struct cvmx_pemx_tlp_credits_s cn63xx;
+        struct cvmx_pemx_tlp_credits_s cn63xxp1;
+        struct cvmx_pemx_tlp_credits_s cn66xx;
+        struct cvmx_pemx_tlp_credits_s cn68xx;
+        struct cvmx_pemx_tlp_credits_s cn68xxp1;
+};
+
+#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pexp-defs.h b/arch/mips/include/asm/octeon/cvmx-pexp-defs.h
index 5ab8679d89a..4438d211988 100644
--- a/arch/mips/include/asm/octeon/cvmx-pexp-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-pexp-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2010 Cavium Networks
+ * Copyright (c) 2003-2011 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -25,13 +25,6 @@
  * Contact Cavium Networks for more information
  ***********************license end**************************************/
 
-/**
- * cvmx-pexp-defs.h
- *
- * Configuration and status register (CSR) definitions for
- * OCTEON PEXP.
- *
- */
 #ifndef __CVMX_PEXP_DEFS_H__
 #define __CVMX_PEXP_DEFS_H__
 
@@ -139,7 +132,7 @@
 #define CVMX_PEXP_NPEI_STATE3 (CVMX_ADD_IO_SEG(0x00011F0000008640ull))
 #define CVMX_PEXP_NPEI_WINDOW_CTL (CVMX_ADD_IO_SEG(0x00011F0000008380ull))
 #define CVMX_PEXP_SLI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F0000010580ull))
-#define CVMX_PEXP_SLI_CTL_PORTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000010050ull) + ((offset) & 1) * 16)
+#define CVMX_PEXP_SLI_CTL_PORTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000010050ull) + ((offset) & 3) * 16)
 #define CVMX_PEXP_SLI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000010570ull))
 #define CVMX_PEXP_SLI_DATA_OUT_CNT (CVMX_ADD_IO_SEG(0x00011F00000105F0ull))
 #define CVMX_PEXP_SLI_DBG_DATA (CVMX_ADD_IO_SEG(0x00011F0000010310ull))
@@ -152,7 +145,10 @@
 #define CVMX_PEXP_SLI_INT_SUM (CVMX_ADD_IO_SEG(0x00011F0000010330ull))
 #define CVMX_PEXP_SLI_LAST_WIN_RDATA0 (CVMX_ADD_IO_SEG(0x00011F0000010600ull))
 #define CVMX_PEXP_SLI_LAST_WIN_RDATA1 (CVMX_ADD_IO_SEG(0x00011F0000010610ull))
+#define CVMX_PEXP_SLI_LAST_WIN_RDATA2 (CVMX_ADD_IO_SEG(0x00011F00000106C0ull))
+#define CVMX_PEXP_SLI_LAST_WIN_RDATA3 (CVMX_ADD_IO_SEG(0x00011F00000106D0ull))
 #define CVMX_PEXP_SLI_MAC_CREDIT_CNT (CVMX_ADD_IO_SEG(0x00011F0000013D70ull))
+#define CVMX_PEXP_SLI_MAC_CREDIT_CNT2 (CVMX_ADD_IO_SEG(0x00011F0000013E10ull))
 #define CVMX_PEXP_SLI_MEM_ACCESS_CTL (CVMX_ADD_IO_SEG(0x00011F00000102F0ull))
 #define CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F00000100E0ull) + ((offset) & 31) * 16 - 16*12)
 #define CVMX_PEXP_SLI_MSI_ENB0 (CVMX_ADD_IO_SEG(0x00011F0000013C50ull))
@@ -206,6 +202,7 @@
 #define CVMX_PEXP_SLI_PKT_IPTR (CVMX_ADD_IO_SEG(0x00011F0000011070ull))
 #define CVMX_PEXP_SLI_PKT_OUTPUT_WMARK (CVMX_ADD_IO_SEG(0x00011F0000011180ull))
 #define CVMX_PEXP_SLI_PKT_OUT_BMODE (CVMX_ADD_IO_SEG(0x00011F00000110D0ull))
+#define CVMX_PEXP_SLI_PKT_OUT_BP_EN (CVMX_ADD_IO_SEG(0x00011F0000011240ull))
 #define CVMX_PEXP_SLI_PKT_OUT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011010ull))
 #define CVMX_PEXP_SLI_PKT_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000110E0ull))
 #define CVMX_PEXP_SLI_PKT_PORT_IN_RST (CVMX_ADD_IO_SEG(0x00011F00000111F0ull))
@@ -214,12 +211,14 @@
 #define CVMX_PEXP_SLI_PKT_SLIST_ROR (CVMX_ADD_IO_SEG(0x00011F0000011030ull))
 #define CVMX_PEXP_SLI_PKT_TIME_INT (CVMX_ADD_IO_SEG(0x00011F0000011140ull))
 #define CVMX_PEXP_SLI_PKT_TIME_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011160ull))
-#define CVMX_PEXP_SLI_S2M_PORTX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011F0000013D80ull) + ((offset) & 1) * 16)
+#define CVMX_PEXP_SLI_PORTX_PKIND(offset) (CVMX_ADD_IO_SEG(0x00011F0000010800ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_SLI_S2M_PORTX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011F0000013D80ull) + ((offset) & 3) * 16)
 #define CVMX_PEXP_SLI_SCRATCH_1 (CVMX_ADD_IO_SEG(0x00011F00000103C0ull))
 #define CVMX_PEXP_SLI_SCRATCH_2 (CVMX_ADD_IO_SEG(0x00011F00000103D0ull))
 #define CVMX_PEXP_SLI_STATE1 (CVMX_ADD_IO_SEG(0x00011F0000010620ull))
 #define CVMX_PEXP_SLI_STATE2 (CVMX_ADD_IO_SEG(0x00011F0000010630ull))
 #define CVMX_PEXP_SLI_STATE3 (CVMX_ADD_IO_SEG(0x00011F0000010640ull))
+#define CVMX_PEXP_SLI_TX_PIPE (CVMX_ADD_IO_SEG(0x00011F0000011230ull))
 #define CVMX_PEXP_SLI_WINDOW_CTL (CVMX_ADD_IO_SEG(0x00011F00000102E0ull))
 
 #endif
diff --git a/drivers/staging/octeon/cvmx-pip-defs.h b/arch/mips/include/asm/octeon/cvmx-pip-defs.h
index 5a369100ca6..5a369100ca6 100644
--- a/drivers/staging/octeon/cvmx-pip-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-pip-defs.h
diff --git a/drivers/staging/octeon/cvmx-pip.h b/arch/mips/include/asm/octeon/cvmx-pip.h
index 78dbce8f2c5..78dbce8f2c5 100644
--- a/drivers/staging/octeon/cvmx-pip.h
+++ b/arch/mips/include/asm/octeon/cvmx-pip.h
diff --git a/drivers/staging/octeon/cvmx-pko-defs.h b/arch/mips/include/asm/octeon/cvmx-pko-defs.h
index 50e779cf1ad..50e779cf1ad 100644
--- a/drivers/staging/octeon/cvmx-pko-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-pko-defs.h
diff --git a/drivers/staging/octeon/cvmx-pko.h b/arch/mips/include/asm/octeon/cvmx-pko.h
index de3412aada5..de3412aada5 100644
--- a/drivers/staging/octeon/cvmx-pko.h
+++ b/arch/mips/include/asm/octeon/cvmx-pko.h
diff --git a/drivers/staging/octeon/cvmx-pow.h b/arch/mips/include/asm/octeon/cvmx-pow.h
index 999aefe3274..999aefe3274 100644
--- a/drivers/staging/octeon/cvmx-pow.h
+++ b/arch/mips/include/asm/octeon/cvmx-pow.h
diff --git a/drivers/staging/octeon/cvmx-scratch.h b/arch/mips/include/asm/octeon/cvmx-scratch.h
index 96b70cfd624..96b70cfd624 100644
--- a/drivers/staging/octeon/cvmx-scratch.h
+++ b/arch/mips/include/asm/octeon/cvmx-scratch.h
diff --git a/arch/mips/include/asm/octeon/cvmx-sli-defs.h b/arch/mips/include/asm/octeon/cvmx-sli-defs.h
new file mode 100644
index 00000000000..7c6c901d3d2
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-sli-defs.h
@@ -0,0 +1,2172 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2011 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_SLI_DEFS_H__
+#define __CVMX_SLI_DEFS_H__
+
+#define CVMX_SLI_BIST_STATUS (0x0000000000000580ull)
+#define CVMX_SLI_CTL_PORTX(offset) (0x0000000000000050ull + ((offset) & 3) * 16)
+#define CVMX_SLI_CTL_STATUS (0x0000000000000570ull)
+#define CVMX_SLI_DATA_OUT_CNT (0x00000000000005F0ull)
+#define CVMX_SLI_DBG_DATA (0x0000000000000310ull)
+#define CVMX_SLI_DBG_SELECT (0x0000000000000300ull)
+#define CVMX_SLI_DMAX_CNT(offset) (0x0000000000000400ull + ((offset) & 1) * 16)
+#define CVMX_SLI_DMAX_INT_LEVEL(offset) (0x00000000000003E0ull + ((offset) & 1) * 16)
+#define CVMX_SLI_DMAX_TIM(offset) (0x0000000000000420ull + ((offset) & 1) * 16)
+#define CVMX_SLI_INT_ENB_CIU (0x0000000000003CD0ull)
+#define CVMX_SLI_INT_ENB_PORTX(offset) (0x0000000000000340ull + ((offset) & 1) * 16)
+#define CVMX_SLI_INT_SUM (0x0000000000000330ull)
+#define CVMX_SLI_LAST_WIN_RDATA0 (0x0000000000000600ull)
+#define CVMX_SLI_LAST_WIN_RDATA1 (0x0000000000000610ull)
+#define CVMX_SLI_LAST_WIN_RDATA2 (0x00000000000006C0ull)
+#define CVMX_SLI_LAST_WIN_RDATA3 (0x00000000000006D0ull)
+#define CVMX_SLI_MAC_CREDIT_CNT (0x0000000000003D70ull)
+#define CVMX_SLI_MAC_CREDIT_CNT2 (0x0000000000003E10ull)
+#define CVMX_SLI_MAC_NUMBER (0x0000000000003E00ull)
+#define CVMX_SLI_MEM_ACCESS_CTL (0x00000000000002F0ull)
+#define CVMX_SLI_MEM_ACCESS_SUBIDX(offset) (0x00000000000000E0ull + ((offset) & 31) * 16 - 16*12)
+#define CVMX_SLI_MSI_ENB0 (0x0000000000003C50ull)
+#define CVMX_SLI_MSI_ENB1 (0x0000000000003C60ull)
+#define CVMX_SLI_MSI_ENB2 (0x0000000000003C70ull)
+#define CVMX_SLI_MSI_ENB3 (0x0000000000003C80ull)
+#define CVMX_SLI_MSI_RCV0 (0x0000000000003C10ull)
+#define CVMX_SLI_MSI_RCV1 (0x0000000000003C20ull)
+#define CVMX_SLI_MSI_RCV2 (0x0000000000003C30ull)
+#define CVMX_SLI_MSI_RCV3 (0x0000000000003C40ull)
+#define CVMX_SLI_MSI_RD_MAP (0x0000000000003CA0ull)
+#define CVMX_SLI_MSI_W1C_ENB0 (0x0000000000003CF0ull)
+#define CVMX_SLI_MSI_W1C_ENB1 (0x0000000000003D00ull)
+#define CVMX_SLI_MSI_W1C_ENB2 (0x0000000000003D10ull)
+#define CVMX_SLI_MSI_W1C_ENB3 (0x0000000000003D20ull)
+#define CVMX_SLI_MSI_W1S_ENB0 (0x0000000000003D30ull)
+#define CVMX_SLI_MSI_W1S_ENB1 (0x0000000000003D40ull)
+#define CVMX_SLI_MSI_W1S_ENB2 (0x0000000000003D50ull)
+#define CVMX_SLI_MSI_W1S_ENB3 (0x0000000000003D60ull)
+#define CVMX_SLI_MSI_WR_MAP (0x0000000000003C90ull)
+#define CVMX_SLI_PCIE_MSI_RCV (0x0000000000003CB0ull)
+#define CVMX_SLI_PCIE_MSI_RCV_B1 (0x0000000000000650ull)
+#define CVMX_SLI_PCIE_MSI_RCV_B2 (0x0000000000000660ull)
+#define CVMX_SLI_PCIE_MSI_RCV_B3 (0x0000000000000670ull)
+#define CVMX_SLI_PKTX_CNTS(offset) (0x0000000000002400ull + ((offset) & 31) * 16)
+#define CVMX_SLI_PKTX_INSTR_BADDR(offset) (0x0000000000002800ull + ((offset) & 31) * 16)
+#define CVMX_SLI_PKTX_INSTR_BAOFF_DBELL(offset) (0x0000000000002C00ull + ((offset) & 31) * 16)
+#define CVMX_SLI_PKTX_INSTR_FIFO_RSIZE(offset) (0x0000000000003000ull + ((offset) & 31) * 16)
+#define CVMX_SLI_PKTX_INSTR_HEADER(offset) (0x0000000000003400ull + ((offset) & 31) * 16)
+#define CVMX_SLI_PKTX_IN_BP(offset) (0x0000000000003800ull + ((offset) & 31) * 16)
+#define CVMX_SLI_PKTX_OUT_SIZE(offset) (0x0000000000000C00ull + ((offset) & 31) * 16)
+#define CVMX_SLI_PKTX_SLIST_BADDR(offset) (0x0000000000001400ull + ((offset) & 31) * 16)
+#define CVMX_SLI_PKTX_SLIST_BAOFF_DBELL(offset) (0x0000000000001800ull + ((offset) & 31) * 16)
+#define CVMX_SLI_PKTX_SLIST_FIFO_RSIZE(offset) (0x0000000000001C00ull + ((offset) & 31) * 16)
+#define CVMX_SLI_PKT_CNT_INT (0x0000000000001130ull)
+#define CVMX_SLI_PKT_CNT_INT_ENB (0x0000000000001150ull)
+#define CVMX_SLI_PKT_CTL (0x0000000000001220ull)
+#define CVMX_SLI_PKT_DATA_OUT_ES (0x00000000000010B0ull)
+#define CVMX_SLI_PKT_DATA_OUT_NS (0x00000000000010A0ull)
+#define CVMX_SLI_PKT_DATA_OUT_ROR (0x0000000000001090ull)
+#define CVMX_SLI_PKT_DPADDR (0x0000000000001080ull)
+#define CVMX_SLI_PKT_INPUT_CONTROL (0x0000000000001170ull)
+#define CVMX_SLI_PKT_INSTR_ENB (0x0000000000001000ull)
+#define CVMX_SLI_PKT_INSTR_RD_SIZE (0x00000000000011A0ull)
+#define CVMX_SLI_PKT_INSTR_SIZE (0x0000000000001020ull)
+#define CVMX_SLI_PKT_INT_LEVELS (0x0000000000001120ull)
+#define CVMX_SLI_PKT_IN_BP (0x0000000000001210ull)
+#define CVMX_SLI_PKT_IN_DONEX_CNTS(offset) (0x0000000000002000ull + ((offset) & 31) * 16)
+#define CVMX_SLI_PKT_IN_INSTR_COUNTS (0x0000000000001200ull)
+#define CVMX_SLI_PKT_IN_PCIE_PORT (0x00000000000011B0ull)
+#define CVMX_SLI_PKT_IPTR (0x0000000000001070ull)
+#define CVMX_SLI_PKT_OUTPUT_WMARK (0x0000000000001180ull)
+#define CVMX_SLI_PKT_OUT_BMODE (0x00000000000010D0ull)
+#define CVMX_SLI_PKT_OUT_BP_EN (0x0000000000001240ull)
+#define CVMX_SLI_PKT_OUT_ENB (0x0000000000001010ull)
+#define CVMX_SLI_PKT_PCIE_PORT (0x00000000000010E0ull)
+#define CVMX_SLI_PKT_PORT_IN_RST (0x00000000000011F0ull)
+#define CVMX_SLI_PKT_SLIST_ES (0x0000000000001050ull)
+#define CVMX_SLI_PKT_SLIST_NS (0x0000000000001040ull)
+#define CVMX_SLI_PKT_SLIST_ROR (0x0000000000001030ull)
+#define CVMX_SLI_PKT_TIME_INT (0x0000000000001140ull)
+#define CVMX_SLI_PKT_TIME_INT_ENB (0x0000000000001160ull)
+#define CVMX_SLI_PORTX_PKIND(offset) (0x0000000000000800ull + ((offset) & 31) * 16)
+#define CVMX_SLI_S2M_PORTX_CTL(offset) (0x0000000000003D80ull + ((offset) & 3) * 16)
+#define CVMX_SLI_SCRATCH_1 (0x00000000000003C0ull)
+#define CVMX_SLI_SCRATCH_2 (0x00000000000003D0ull)
+#define CVMX_SLI_STATE1 (0x0000000000000620ull)
+#define CVMX_SLI_STATE2 (0x0000000000000630ull)
+#define CVMX_SLI_STATE3 (0x0000000000000640ull)
+#define CVMX_SLI_TX_PIPE (0x0000000000001230ull)
+#define CVMX_SLI_WINDOW_CTL (0x00000000000002E0ull)
+#define CVMX_SLI_WIN_RD_ADDR (0x0000000000000010ull)
+#define CVMX_SLI_WIN_RD_DATA (0x0000000000000040ull)
+#define CVMX_SLI_WIN_WR_ADDR (0x0000000000000000ull)
+#define CVMX_SLI_WIN_WR_DATA (0x0000000000000020ull)
+#define CVMX_SLI_WIN_WR_MASK (0x0000000000000030ull)
+
+union cvmx_sli_bist_status {
+        uint64_t u64;
+        struct cvmx_sli_bist_status_s {
+                uint64_t reserved_32_63:32;
+                uint64_t ncb_req:1;
+                uint64_t n2p0_c:1;
+                uint64_t n2p0_o:1;
+                uint64_t n2p1_c:1;
+                uint64_t n2p1_o:1;
+                uint64_t cpl_p0:1;
+                uint64_t cpl_p1:1;
+                uint64_t reserved_19_24:6;
+                uint64_t p2n0_c0:1;
+                uint64_t p2n0_c1:1;
+                uint64_t p2n0_n:1;
+                uint64_t p2n0_p0:1;
+                uint64_t p2n0_p1:1;
+                uint64_t p2n1_c0:1;
+                uint64_t p2n1_c1:1;
+                uint64_t p2n1_n:1;
+                uint64_t p2n1_p0:1;
+                uint64_t p2n1_p1:1;
+                uint64_t reserved_6_8:3;
+                uint64_t dsi1_1:1;
+                uint64_t dsi1_0:1;
+                uint64_t dsi0_1:1;
+                uint64_t dsi0_0:1;
+                uint64_t msi:1;
+                uint64_t ncb_cmd:1;
+        } s;
+        struct cvmx_sli_bist_status_cn61xx {
+                uint64_t reserved_31_63:33;
+                uint64_t n2p0_c:1;
+                uint64_t n2p0_o:1;
+                uint64_t reserved_27_28:2;
+                uint64_t cpl_p0:1;
+                uint64_t cpl_p1:1;
+                uint64_t reserved_19_24:6;
+                uint64_t p2n0_c0:1;
+                uint64_t p2n0_c1:1;
+                uint64_t p2n0_n:1;
+                uint64_t p2n0_p0:1;
+                uint64_t p2n0_p1:1;
+                uint64_t p2n1_c0:1;
+                uint64_t p2n1_c1:1;
+                uint64_t p2n1_n:1;
+                uint64_t p2n1_p0:1;
+                uint64_t p2n1_p1:1;
+                uint64_t reserved_6_8:3;
+                uint64_t dsi1_1:1;
+                uint64_t dsi1_0:1;
+                uint64_t dsi0_1:1;
+                uint64_t dsi0_0:1;
+                uint64_t msi:1;
+                uint64_t ncb_cmd:1;
+        } cn61xx;
+        struct cvmx_sli_bist_status_cn63xx {
+                uint64_t reserved_31_63:33;
+                uint64_t n2p0_c:1;
+                uint64_t n2p0_o:1;
+                uint64_t n2p1_c:1;
+                uint64_t n2p1_o:1;
+                uint64_t cpl_p0:1;
+                uint64_t cpl_p1:1;
+                uint64_t reserved_19_24:6;
+                uint64_t p2n0_c0:1;
+                uint64_t p2n0_c1:1;
+                uint64_t p2n0_n:1;
+                uint64_t p2n0_p0:1;
+                uint64_t p2n0_p1:1;
+                uint64_t p2n1_c0:1;
+                uint64_t p2n1_c1:1;
+                uint64_t p2n1_n:1;
+                uint64_t p2n1_p0:1;
+                uint64_t p2n1_p1:1;
+                uint64_t reserved_6_8:3;
+                uint64_t dsi1_1:1;
+                uint64_t dsi1_0:1;
+                uint64_t dsi0_1:1;
+                uint64_t dsi0_0:1;
+                uint64_t msi:1;
+                uint64_t ncb_cmd:1;
+        } cn63xx;
+        struct cvmx_sli_bist_status_cn63xx cn63xxp1;
+        struct cvmx_sli_bist_status_cn61xx cn66xx;
+        struct cvmx_sli_bist_status_s cn68xx;
+        struct cvmx_sli_bist_status_s cn68xxp1;
+};
+
+union cvmx_sli_ctl_portx {
+        uint64_t u64;
+        struct cvmx_sli_ctl_portx_s {
+                uint64_t reserved_22_63:42;
+                uint64_t intd:1;
+                uint64_t intc:1;
+                uint64_t intb:1;
+                uint64_t inta:1;
+                uint64_t dis_port:1;
+                uint64_t waitl_com:1;
+                uint64_t intd_map:2;
+                uint64_t intc_map:2;
+                uint64_t intb_map:2;
+                uint64_t inta_map:2;
+                uint64_t ctlp_ro:1;
+                uint64_t reserved_6_6:1;
+                uint64_t ptlp_ro:1;
+                uint64_t reserved_1_4:4;
+                uint64_t wait_com:1;
+        } s;
+        struct cvmx_sli_ctl_portx_s cn61xx;
+        struct cvmx_sli_ctl_portx_s cn63xx;
+        struct cvmx_sli_ctl_portx_s cn63xxp1;
+        struct cvmx_sli_ctl_portx_s cn66xx;
+        struct cvmx_sli_ctl_portx_s cn68xx;
+        struct cvmx_sli_ctl_portx_s cn68xxp1;
+};
+
+union cvmx_sli_ctl_status {
+        uint64_t u64;
+        struct cvmx_sli_ctl_status_s {
+                uint64_t reserved_20_63:44;
+                uint64_t p1_ntags:6;
+                uint64_t p0_ntags:6;
+                uint64_t chip_rev:8;
+        } s;
+        struct cvmx_sli_ctl_status_cn61xx {
+                uint64_t reserved_14_63:50;
+                uint64_t p0_ntags:6;
+                uint64_t chip_rev:8;
+        } cn61xx;
+        struct cvmx_sli_ctl_status_s cn63xx;
+        struct cvmx_sli_ctl_status_s cn63xxp1;
+        struct cvmx_sli_ctl_status_cn61xx cn66xx;
+        struct cvmx_sli_ctl_status_s cn68xx;
+        struct cvmx_sli_ctl_status_s cn68xxp1;
+};
+
+union cvmx_sli_data_out_cnt {
+        uint64_t u64;
+        struct cvmx_sli_data_out_cnt_s {
+                uint64_t reserved_44_63:20;
+                uint64_t p1_ucnt:16;
+                uint64_t p1_fcnt:6;
+                uint64_t p0_ucnt:16;
+                uint64_t p0_fcnt:6;
+        } s;
+        struct cvmx_sli_data_out_cnt_s cn61xx;
+        struct cvmx_sli_data_out_cnt_s cn63xx;
+        struct cvmx_sli_data_out_cnt_s cn63xxp1;
+        struct cvmx_sli_data_out_cnt_s cn66xx;
+        struct cvmx_sli_data_out_cnt_s cn68xx;
+        struct cvmx_sli_data_out_cnt_s cn68xxp1;
+};
+
+union cvmx_sli_dbg_data {
+        uint64_t u64;
+        struct cvmx_sli_dbg_data_s {
+                uint64_t reserved_18_63:46;
+                uint64_t dsel_ext:1;
+                uint64_t data:17;
+        } s;
+        struct cvmx_sli_dbg_data_s cn61xx;
+        struct cvmx_sli_dbg_data_s cn63xx;
+        struct cvmx_sli_dbg_data_s cn63xxp1;
+        struct cvmx_sli_dbg_data_s cn66xx;
+        struct cvmx_sli_dbg_data_s cn68xx;
+        struct cvmx_sli_dbg_data_s cn68xxp1;
+};
+
+union cvmx_sli_dbg_select {
+        uint64_t u64;
+        struct cvmx_sli_dbg_select_s {
+                uint64_t reserved_33_63:31;
+                uint64_t adbg_sel:1;
+                uint64_t dbg_sel:32;
+        } s;
+        struct cvmx_sli_dbg_select_s cn61xx;
+        struct cvmx_sli_dbg_select_s cn63xx;
+        struct cvmx_sli_dbg_select_s cn63xxp1;
+        struct cvmx_sli_dbg_select_s cn66xx;
+        struct cvmx_sli_dbg_select_s cn68xx;
+        struct cvmx_sli_dbg_select_s cn68xxp1;
+};
+
+union cvmx_sli_dmax_cnt {
+        uint64_t u64;
+        struct cvmx_sli_dmax_cnt_s {
+                uint64_t reserved_32_63:32;
+                uint64_t cnt:32;
+        } s;
+        struct cvmx_sli_dmax_cnt_s cn61xx;
+        struct cvmx_sli_dmax_cnt_s cn63xx;
+        struct cvmx_sli_dmax_cnt_s cn63xxp1;
+        struct cvmx_sli_dmax_cnt_s cn66xx;
+        struct cvmx_sli_dmax_cnt_s cn68xx;
+        struct cvmx_sli_dmax_cnt_s cn68xxp1;
+};
+
+union cvmx_sli_dmax_int_level {
+        uint64_t u64;
+        struct cvmx_sli_dmax_int_level_s {
+                uint64_t time:32;
+                uint64_t cnt:32;
+        } s;
+        struct cvmx_sli_dmax_int_level_s cn61xx;
+        struct cvmx_sli_dmax_int_level_s cn63xx;
+        struct cvmx_sli_dmax_int_level_s cn63xxp1;
+        struct cvmx_sli_dmax_int_level_s cn66xx;
+        struct cvmx_sli_dmax_int_level_s cn68xx;
+        struct cvmx_sli_dmax_int_level_s cn68xxp1;
+};
+
+union cvmx_sli_dmax_tim {
+        uint64_t u64;
+        struct cvmx_sli_dmax_tim_s {
+                uint64_t reserved_32_63:32;
+                uint64_t tim:32;
+        } s;
+        struct cvmx_sli_dmax_tim_s cn61xx;
+        struct cvmx_sli_dmax_tim_s cn63xx;
+        struct cvmx_sli_dmax_tim_s cn63xxp1;
+        struct cvmx_sli_dmax_tim_s cn66xx;
+        struct cvmx_sli_dmax_tim_s cn68xx;
+        struct cvmx_sli_dmax_tim_s cn68xxp1;
+};
+
+union cvmx_sli_int_enb_ciu {
+        uint64_t u64;
+        struct cvmx_sli_int_enb_ciu_s {
+                uint64_t reserved_62_63:2;
+                uint64_t pipe_err:1;
+                uint64_t ill_pad:1;
+                uint64_t sprt3_err:1;
+                uint64_t sprt2_err:1;
+                uint64_t sprt1_err:1;
+                uint64_t sprt0_err:1;
+                uint64_t pins_err:1;
+                uint64_t pop_err:1;
+                uint64_t pdi_err:1;
+                uint64_t pgl_err:1;
+                uint64_t pin_bp:1;
+                uint64_t pout_err:1;
+                uint64_t psldbof:1;
+                uint64_t pidbof:1;
+                uint64_t reserved_38_47:10;
+                uint64_t dtime:2;
+                uint64_t dcnt:2;
+                uint64_t dmafi:2;
+                uint64_t reserved_28_31:4;
+                uint64_t m3_un_wi:1;
+                uint64_t m3_un_b0:1;
+                uint64_t m3_up_wi:1;
+                uint64_t m3_up_b0:1;
+                uint64_t m2_un_wi:1;
+                uint64_t m2_un_b0:1;
+                uint64_t m2_up_wi:1;
+                uint64_t m2_up_b0:1;
+                uint64_t reserved_18_19:2;
+                uint64_t mio_int1:1;
+                uint64_t mio_int0:1;
+                uint64_t m1_un_wi:1;
+                uint64_t m1_un_b0:1;
+                uint64_t m1_up_wi:1;
+                uint64_t m1_up_b0:1;
+                uint64_t m0_un_wi:1;
+                uint64_t m0_un_b0:1;
+                uint64_t m0_up_wi:1;
+                uint64_t m0_up_b0:1;
+                uint64_t reserved_6_7:2;
+                uint64_t ptime:1;
+                uint64_t pcnt:1;
+                uint64_t iob2big:1;
+                uint64_t bar0_to:1;
+                uint64_t reserved_1_1:1;
+                uint64_t rml_to:1;
+        } s;
+        struct cvmx_sli_int_enb_ciu_cn61xx {
+                uint64_t reserved_61_63:3;
+                uint64_t ill_pad:1;
+                uint64_t sprt3_err:1;
+                uint64_t sprt2_err:1;
+                uint64_t sprt1_err:1;
+                uint64_t sprt0_err:1;
+                uint64_t pins_err:1;
+                uint64_t pop_err:1;
+                uint64_t pdi_err:1;
+                uint64_t pgl_err:1;
+                uint64_t pin_bp:1;
+                uint64_t pout_err:1;
+                uint64_t psldbof:1;
+                uint64_t pidbof:1;
+                uint64_t reserved_38_47:10;
+                uint64_t dtime:2;
+                uint64_t dcnt:2;
+                uint64_t dmafi:2;
+                uint64_t reserved_28_31:4;
+                uint64_t m3_un_wi:1;
+                uint64_t m3_un_b0:1;
+                uint64_t m3_up_wi:1;
+                uint64_t m3_up_b0:1;
+                uint64_t m2_un_wi:1;
+                uint64_t m2_un_b0:1;
+                uint64_t m2_up_wi:1;
+                uint64_t m2_up_b0:1;
+                uint64_t reserved_18_19:2;
+                uint64_t mio_int1:1;
+                uint64_t mio_int0:1;
+                uint64_t m1_un_wi:1;
+                uint64_t m1_un_b0:1;
+                uint64_t m1_up_wi:1;
+                uint64_t m1_up_b0:1;
+                uint64_t m0_un_wi:1;
+                uint64_t m0_un_b0:1;
+                uint64_t m0_up_wi:1;
+                uint64_t m0_up_b0:1;
+                uint64_t reserved_6_7:2;
+                uint64_t ptime:1;
+                uint64_t pcnt:1;
+                uint64_t iob2big:1;
+                uint64_t bar0_to:1;
+                uint64_t reserved_1_1:1;
+                uint64_t rml_to:1;
+        } cn61xx;
+        struct cvmx_sli_int_enb_ciu_cn63xx {
+                uint64_t reserved_61_63:3;
+                uint64_t ill_pad:1;
+                uint64_t reserved_58_59:2;
+                uint64_t sprt1_err:1;
+                uint64_t sprt0_err:1;
+                uint64_t pins_err:1;
+                uint64_t pop_err:1;
+                uint64_t pdi_err:1;
+                uint64_t pgl_err:1;
+                uint64_t pin_bp:1;
+                uint64_t pout_err:1;
+                uint64_t psldbof:1;
+                uint64_t pidbof:1;
+                uint64_t reserved_38_47:10;
+                uint64_t dtime:2;
+                uint64_t dcnt:2;
+                uint64_t dmafi:2;
+                uint64_t reserved_18_31:14;
+                uint64_t mio_int1:1;
+                uint64_t mio_int0:1;
+                uint64_t m1_un_wi:1;
+                uint64_t m1_un_b0:1;
+                uint64_t m1_up_wi:1;
+                uint64_t m1_up_b0:1;
+                uint64_t m0_un_wi:1;
+                uint64_t m0_un_b0:1;
+                uint64_t m0_up_wi:1;
+                uint64_t m0_up_b0:1;
+                uint64_t reserved_6_7:2;
+                uint64_t ptime:1;
+                uint64_t pcnt:1;
+                uint64_t iob2big:1;
+                uint64_t bar0_to:1;
+                uint64_t reserved_1_1:1;
+                uint64_t rml_to:1;
+        } cn63xx;
+        struct cvmx_sli_int_enb_ciu_cn63xx cn63xxp1;
+        struct cvmx_sli_int_enb_ciu_cn61xx cn66xx;
+        struct cvmx_sli_int_enb_ciu_cn68xx {
+                uint64_t reserved_62_63:2;
+                uint64_t pipe_err:1;
+                uint64_t ill_pad:1;
+                uint64_t reserved_58_59:2;
+                uint64_t sprt1_err:1;
+                uint64_t sprt0_err:1;
+                uint64_t pins_err:1;
+                uint64_t pop_err:1;
+                uint64_t pdi_err:1;
+                uint64_t pgl_err:1;
+                uint64_t reserved_51_51:1;
+                uint64_t pout_err:1;
+                uint64_t psldbof:1;
+                uint64_t pidbof:1;
+                uint64_t reserved_38_47:10;
+                uint64_t dtime:2;
+                uint64_t dcnt:2;
+                uint64_t dmafi:2;
+                uint64_t reserved_18_31:14;
+                uint64_t mio_int1:1;
+                uint64_t mio_int0:1;
+                uint64_t m1_un_wi:1;
+                uint64_t m1_un_b0:1;
+                uint64_t m1_up_wi:1;
+                uint64_t m1_up_b0:1;
+                uint64_t m0_un_wi:1;
+                uint64_t m0_un_b0:1;
+                uint64_t m0_up_wi:1;
+                uint64_t m0_up_b0:1;
+                uint64_t reserved_6_7:2;
+                uint64_t ptime:1;
+                uint64_t pcnt:1;
+                uint64_t iob2big:1;
+                uint64_t bar0_to:1;
+                uint64_t reserved_1_1:1;
+                uint64_t rml_to:1;
+        } cn68xx;
+        struct cvmx_sli_int_enb_ciu_cn68xx cn68xxp1;
+};
+
+union cvmx_sli_int_enb_portx {
+        uint64_t u64;
+        struct cvmx_sli_int_enb_portx_s {
+                uint64_t reserved_62_63:2;
+                uint64_t pipe_err:1;
+                uint64_t ill_pad:1;
+                uint64_t sprt3_err:1;
+                uint64_t sprt2_err:1;
+                uint64_t sprt1_err:1;
+                uint64_t sprt0_err:1;
+                uint64_t pins_err:1;
+                uint64_t pop_err:1;
+                uint64_t pdi_err:1;
+                uint64_t pgl_err:1;
+                uint64_t pin_bp:1;
+                uint64_t pout_err:1;
+                uint64_t psldbof:1;
+                uint64_t pidbof:1;
+                uint64_t reserved_38_47:10;
+                uint64_t dtime:2;
+                uint64_t dcnt:2;
+                uint64_t dmafi:2;
+                uint64_t reserved_28_31:4;
+                uint64_t m3_un_wi:1;
+                uint64_t m3_un_b0:1;
+                uint64_t m3_up_wi:1;
+                uint64_t m3_up_b0:1;
+                uint64_t m2_un_wi:1;
+                uint64_t m2_un_b0:1;
+                uint64_t m2_up_wi:1;
+                uint64_t m2_up_b0:1;
+                uint64_t mac1_int:1;
+                uint64_t mac0_int:1;
+                uint64_t mio_int1:1;
+                uint64_t mio_int0:1;
+                uint64_t m1_un_wi:1;
+                uint64_t m1_un_b0:1;
+                uint64_t m1_up_wi:1;
+                uint64_t m1_up_b0:1;
+                uint64_t m0_un_wi:1;
+                uint64_t m0_un_b0:1;
+                uint64_t m0_up_wi:1;
+                uint64_t m0_up_b0:1;
+                uint64_t reserved_6_7:2;
+                uint64_t ptime:1;
+                uint64_t pcnt:1;
+                uint64_t iob2big:1;
+                uint64_t bar0_to:1;
+                uint64_t reserved_1_1:1;
+                uint64_t rml_to:1;
+        } s;
+        struct cvmx_sli_int_enb_portx_cn61xx {
+                uint64_t reserved_61_63:3;
+                uint64_t ill_pad:1;
+                uint64_t sprt3_err:1;
+                uint64_t sprt2_err:1;
+                uint64_t sprt1_err:1;
+                uint64_t sprt0_err:1;
+                uint64_t pins_err:1;
+                uint64_t pop_err:1;
+                uint64_t pdi_err:1;
+                uint64_t pgl_err:1;
+                uint64_t pin_bp:1;
+                uint64_t pout_err:1;
+                uint64_t psldbof:1;
+                uint64_t pidbof:1;
+                uint64_t reserved_38_47:10;
+                uint64_t dtime:2;
+                uint64_t dcnt:2;
+                uint64_t dmafi:2;
+                uint64_t reserved_28_31:4;
+                uint64_t m3_un_wi:1;
+                uint64_t m3_un_b0:1;
+                uint64_t m3_up_wi:1;
+                uint64_t m3_up_b0:1;
+                uint64_t m2_un_wi:1;
+                uint64_t m2_un_b0:1;
+                uint64_t m2_up_wi:1;
+                uint64_t m2_up_b0:1;
+                uint64_t mac1_int:1;
+                uint64_t mac0_int:1;
+                uint64_t mio_int1:1;
+                uint64_t mio_int0:1;
+                uint64_t m1_un_wi:1;
+                uint64_t m1_un_b0:1;
+                uint64_t m1_up_wi:1;
+                uint64_t m1_up_b0:1;
+                uint64_t m0_un_wi:1;
+                uint64_t m0_un_b0:1;
+                uint64_t m0_up_wi:1;
+                uint64_t m0_up_b0:1;
+                uint64_t reserved_6_7:2;
+                uint64_t ptime:1;
+                uint64_t pcnt:1;
+                uint64_t iob2big:1;
+                uint64_t bar0_to:1;
+                uint64_t reserved_1_1:1;
+                uint64_t rml_to:1;
+        } cn61xx;
+        struct cvmx_sli_int_enb_portx_cn63xx {
+                uint64_t reserved_61_63:3;
+                uint64_t ill_pad:1;
+                uint64_t reserved_58_59:2;
+                uint64_t sprt1_err:1;
+                uint64_t sprt0_err:1;
+                uint64_t pins_err:1;
+                uint64_t pop_err:1;
+                uint64_t pdi_err:1;
+                uint64_t pgl_err:1;
+                uint64_t pin_bp:1;
+                uint64_t pout_err:1;
+                uint64_t psldbof:1;
+                uint64_t pidbof:1;
+                uint64_t reserved_38_47:10;
+                uint64_t dtime:2;
+                uint64_t dcnt:2;
+                uint64_t dmafi:2;
+                uint64_t reserved_20_31:12;
+                uint64_t mac1_int:1;
+                uint64_t mac0_int:1;
+                uint64_t mio_int1:1;
+                uint64_t mio_int0:1;
+                uint64_t m1_un_wi:1;
+                uint64_t m1_un_b0:1;
+                uint64_t m1_up_wi:1;
+                uint64_t m1_up_b0:1;
+                uint64_t m0_un_wi:1;
+                uint64_t m0_un_b0:1;
+                uint64_t m0_up_wi:1;
+                uint64_t m0_up_b0:1;
+                uint64_t reserved_6_7:2;
+                uint64_t ptime:1;
+                uint64_t pcnt:1;
+                uint64_t iob2big:1;
+                uint64_t bar0_to:1;
+                uint64_t reserved_1_1:1;
+                uint64_t rml_to:1;
+        } cn63xx;
+        struct cvmx_sli_int_enb_portx_cn63xx cn63xxp1;
+        struct cvmx_sli_int_enb_portx_cn61xx cn66xx;
+        struct cvmx_sli_int_enb_portx_cn68xx {
+                uint64_t reserved_62_63:2;
+                uint64_t pipe_err:1;
+                uint64_t ill_pad:1;
+                uint64_t reserved_58_59:2;
+                uint64_t sprt1_err:1;
+                uint64_t sprt0_err:1;
+                uint64_t pins_err:1;
+                uint64_t pop_err:1;
+                uint64_t pdi_err:1;
+                uint64_t pgl_err:1;
+                uint64_t reserved_51_51:1;
+                uint64_t pout_err:1;
+                uint64_t psldbof:1;
+                uint64_t pidbof:1;
+                uint64_t reserved_38_47:10;
+                uint64_t dtime:2;
+                uint64_t dcnt:2;
+                uint64_t dmafi:2;
+                uint64_t reserved_20_31:12;
+                uint64_t mac1_int:1;
+                uint64_t mac0_int:1;
+                uint64_t mio_int1:1;
+                uint64_t mio_int0:1;
+                uint64_t m1_un_wi:1;
+                uint64_t m1_un_b0:1;
+                uint64_t m1_up_wi:1;
+                uint64_t m1_up_b0:1;
+                uint64_t m0_un_wi:1;
+                uint64_t m0_un_b0:1;
+                uint64_t m0_up_wi:1;
+                uint64_t m0_up_b0:1;
+                uint64_t reserved_6_7:2;
+                uint64_t ptime:1;
+                uint64_t pcnt:1;
+                uint64_t iob2big:1;
+                uint64_t bar0_to:1;
+                uint64_t reserved_1_1:1;
+                uint64_t rml_to:1;
+        } cn68xx;
+        struct cvmx_sli_int_enb_portx_cn68xx cn68xxp1;
+};
+
+union cvmx_sli_int_sum {
+        uint64_t u64;
+        struct cvmx_sli_int_sum_s {
+                uint64_t reserved_62_63:2;
+                uint64_t pipe_err:1;
+                uint64_t ill_pad:1;
+                uint64_t sprt3_err:1;
+                uint64_t sprt2_err:1;
+                uint64_t sprt1_err:1;
+                uint64_t sprt0_err:1;
+                uint64_t pins_err:1;
+                uint64_t pop_err:1;
+                uint64_t pdi_err:1;
+                uint64_t pgl_err:1;
+                uint64_t pin_bp:1;
+                uint64_t pout_err:1;
+                uint64_t psldbof:1;
+                uint64_t pidbof:1;
+                uint64_t reserved_38_47:10;
+                uint64_t dtime:2;
+                uint64_t dcnt:2;
+                uint64_t dmafi:2;
+                uint64_t reserved_28_31:4;
+                uint64_t m3_un_wi:1;
+                uint64_t m3_un_b0:1;
+                uint64_t m3_up_wi:1;
+                uint64_t m3_up_b0:1;
+                uint64_t m2_un_wi:1;
+                uint64_t m2_un_b0:1;
+                uint64_t m2_up_wi:1;
+                uint64_t m2_up_b0:1;
+                uint64_t mac1_int:1;
+                uint64_t mac0_int:1;
+                uint64_t mio_int1:1;
+                uint64_t mio_int0:1;
+                uint64_t m1_un_wi:1;
+                uint64_t m1_un_b0:1;
+                uint64_t m1_up_wi:1;
+                uint64_t m1_up_b0:1;
+                uint64_t m0_un_wi:1;
+                uint64_t m0_un_b0:1;
+                uint64_t m0_up_wi:1;
+                uint64_t m0_up_b0:1;
+                uint64_t reserved_6_7:2;
+                uint64_t ptime:1;
+                uint64_t pcnt:1;
+                uint64_t iob2big:1;
+                uint64_t bar0_to:1;
+                uint64_t reserved_1_1:1;
+                uint64_t rml_to:1;
+        } s;
+        struct cvmx_sli_int_sum_cn61xx {
+                uint64_t reserved_61_63:3;
+                uint64_t ill_pad:1;
+                uint64_t sprt3_err:1;
+                uint64_t sprt2_err:1;
+                uint64_t sprt1_err:1;
+                uint64_t sprt0_err:1;
+                uint64_t pins_err:1;
+                uint64_t pop_err:1;
+                uint64_t pdi_err:1;
+                uint64_t pgl_err:1;
+                uint64_t pin_bp:1;
+                uint64_t pout_err:1;
+                uint64_t psldbof:1;
+                uint64_t pidbof:1;
+                uint64_t reserved_38_47:10;
+                uint64_t dtime:2;
+                uint64_t dcnt:2;
+                uint64_t dmafi:2;
+                uint64_t reserved_28_31:4;
+                uint64_t m3_un_wi:1;
+                uint64_t m3_un_b0:1;
+                uint64_t m3_up_wi:1;
+                uint64_t m3_up_b0:1;
+                uint64_t m2_un_wi:1;
+                uint64_t m2_un_b0:1;
+                uint64_t m2_up_wi:1;
+                uint64_t m2_up_b0:1;
+                uint64_t mac1_int:1;
+                uint64_t mac0_int:1;
+                uint64_t mio_int1:1;
+                uint64_t mio_int0:1;
+                uint64_t m1_un_wi:1;
+                uint64_t m1_un_b0:1;
+                uint64_t m1_up_wi:1;
+                uint64_t m1_up_b0:1;
+                uint64_t m0_un_wi:1;
+                uint64_t m0_un_b0:1;
+                uint64_t m0_up_wi:1;
+                uint64_t m0_up_b0:1;
+                uint64_t reserved_6_7:2;
+                uint64_t ptime:1;
+                uint64_t pcnt:1;
+                uint64_t iob2big:1;
+                uint64_t bar0_to:1;
+                uint64_t reserved_1_1:1;
+                uint64_t rml_to:1;
+        } cn61xx;
+        struct cvmx_sli_int_sum_cn63xx {
+                uint64_t reserved_61_63:3;
+                uint64_t ill_pad:1;
+                uint64_t reserved_58_59:2;
+                uint64_t sprt1_err:1;
+                uint64_t sprt0_err:1;
+                uint64_t pins_err:1;
+                uint64_t pop_err:1;
+                uint64_t pdi_err:1;
+                uint64_t pgl_err:1;
+                uint64_t pin_bp:1;
+                uint64_t pout_err:1;
+                uint64_t psldbof:1;
+                uint64_t pidbof:1;
+                uint64_t reserved_38_47:10;
+                uint64_t dtime:2;
+                uint64_t dcnt:2;
+                uint64_t dmafi:2;
+                uint64_t reserved_20_31:12;
+                uint64_t mac1_int:1;
+                uint64_t mac0_int:1;
+                uint64_t mio_int1:1;
+                uint64_t mio_int0:1;
+                uint64_t m1_un_wi:1;
+                uint64_t m1_un_b0:1;
+                uint64_t m1_up_wi:1;
+                uint64_t m1_up_b0:1;
+                uint64_t m0_un_wi:1;
+                uint64_t m0_un_b0:1;
+                uint64_t m0_up_wi:1;
+                uint64_t m0_up_b0:1;
+                uint64_t reserved_6_7:2;
+                uint64_t ptime:1;
+                uint64_t pcnt:1;
+                uint64_t iob2big:1;
+                uint64_t bar0_to:1;
+                uint64_t reserved_1_1:1;
+                uint64_t rml_to:1;
+        } cn63xx;
+        struct cvmx_sli_int_sum_cn63xx cn63xxp1;
+        struct cvmx_sli_int_sum_cn61xx cn66xx;
+        struct cvmx_sli_int_sum_cn68xx {
+                uint64_t reserved_62_63:2;
+                uint64_t pipe_err:1;
+                uint64_t ill_pad:1;
+                uint64_t reserved_58_59:2;
+                uint64_t sprt1_err:1;
+                uint64_t sprt0_err:1;
+                uint64_t pins_err:1;
+                uint64_t pop_err:1;
+                uint64_t pdi_err:1;
+                uint64_t pgl_err:1;
+                uint64_t reserved_51_51:1;
+                uint64_t pout_err:1;
+                uint64_t psldbof:1;
+                uint64_t pidbof:1;
+                uint64_t reserved_38_47:10;
+                uint64_t dtime:2;
+                uint64_t dcnt:2;
+                uint64_t dmafi:2;
+                uint64_t reserved_20_31:12;
+                uint64_t mac1_int:1;
+                uint64_t mac0_int:1;
+                uint64_t mio_int1:1;
+                uint64_t mio_int0:1;
+                uint64_t m1_un_wi:1;
+                uint64_t m1_un_b0:1;
+                uint64_t m1_up_wi:1;
+                uint64_t m1_up_b0:1;
+                uint64_t m0_un_wi:1;
+                uint64_t m0_un_b0:1;
+                uint64_t m0_up_wi:1;
+                uint64_t m0_up_b0:1;
+                uint64_t reserved_6_7:2;
+                uint64_t ptime:1;
+                uint64_t pcnt:1;
+                uint64_t iob2big:1;
+                uint64_t bar0_to:1;
+                uint64_t reserved_1_1:1;
+                uint64_t rml_to:1;
+        } cn68xx;
+        struct cvmx_sli_int_sum_cn68xx cn68xxp1;
+};
+
+union cvmx_sli_last_win_rdata0 {
+        uint64_t u64;
+        struct cvmx_sli_last_win_rdata0_s {
+                uint64_t data:64;
+        } s;
+        struct cvmx_sli_last_win_rdata0_s cn61xx;
+        struct cvmx_sli_last_win_rdata0_s cn63xx;
+        struct cvmx_sli_last_win_rdata0_s cn63xxp1;
+        struct cvmx_sli_last_win_rdata0_s cn66xx;
+        struct cvmx_sli_last_win_rdata0_s cn68xx;
+        struct cvmx_sli_last_win_rdata0_s cn68xxp1;
+};
+
+union cvmx_sli_last_win_rdata1 {
+        uint64_t u64;
+        struct cvmx_sli_last_win_rdata1_s {
+                uint64_t data:64;
+        } s;
+        struct cvmx_sli_last_win_rdata1_s cn61xx;
+        struct cvmx_sli_last_win_rdata1_s cn63xx;
+        struct cvmx_sli_last_win_rdata1_s cn63xxp1;
+        struct cvmx_sli_last_win_rdata1_s cn66xx;
+        struct cvmx_sli_last_win_rdata1_s cn68xx;
+        struct cvmx_sli_last_win_rdata1_s cn68xxp1;
+};
+
+union cvmx_sli_last_win_rdata2 {
+        uint64_t u64;
+        struct cvmx_sli_last_win_rdata2_s {
+                uint64_t data:64;
+        } s;
+        struct cvmx_sli_last_win_rdata2_s cn61xx;
+        struct cvmx_sli_last_win_rdata2_s cn66xx;
+};
+
+union cvmx_sli_last_win_rdata3 {
+        uint64_t u64;
+        struct cvmx_sli_last_win_rdata3_s {
+                uint64_t data:64;
+        } s;
+        struct cvmx_sli_last_win_rdata3_s cn61xx;
+        struct cvmx_sli_last_win_rdata3_s cn66xx;
+};
+
+union cvmx_sli_mac_credit_cnt {
+        uint64_t u64;
+        struct cvmx_sli_mac_credit_cnt_s {
+                uint64_t reserved_54_63:10;
+                uint64_t p1_c_d:1;
+                uint64_t p1_n_d:1;
+                uint64_t p1_p_d:1;
+                uint64_t p0_c_d:1;
+                uint64_t p0_n_d:1;
+                uint64_t p0_p_d:1;
+                uint64_t p1_ccnt:8;
+                uint64_t p1_ncnt:8;
+                uint64_t p1_pcnt:8;
+                uint64_t p0_ccnt:8;
+                uint64_t p0_ncnt:8;
+                uint64_t p0_pcnt:8;
+        } s;
+        struct cvmx_sli_mac_credit_cnt_s cn61xx;
+        struct cvmx_sli_mac_credit_cnt_s cn63xx;
+        struct cvmx_sli_mac_credit_cnt_cn63xxp1 {
+                uint64_t reserved_48_63:16;
+                uint64_t p1_ccnt:8;
+                uint64_t p1_ncnt:8;
+                uint64_t p1_pcnt:8;
+                uint64_t p0_ccnt:8;
+                uint64_t p0_ncnt:8;
+                uint64_t p0_pcnt:8;
+        } cn63xxp1;
+        struct cvmx_sli_mac_credit_cnt_s cn66xx;
+        struct cvmx_sli_mac_credit_cnt_s cn68xx;
+        struct cvmx_sli_mac_credit_cnt_s cn68xxp1;
+};
+
+union cvmx_sli_mac_credit_cnt2 {
+        uint64_t u64;
+        struct cvmx_sli_mac_credit_cnt2_s {
+                uint64_t reserved_54_63:10;
+                uint64_t p3_c_d:1;
+                uint64_t p3_n_d:1;
+                uint64_t p3_p_d:1;
+                uint64_t p2_c_d:1;
+                uint64_t p2_n_d:1;
+                uint64_t p2_p_d:1;
+                uint64_t p3_ccnt:8;
+                uint64_t p3_ncnt:8;
+                uint64_t p3_pcnt:8;
+                uint64_t p2_ccnt:8;
+                uint64_t p2_ncnt:8;
+                uint64_t p2_pcnt:8;
+        } s;
+        struct cvmx_sli_mac_credit_cnt2_s cn61xx;
+        struct cvmx_sli_mac_credit_cnt2_s cn66xx;
+};
+
+union cvmx_sli_mac_number {
+        uint64_t u64;
+        struct cvmx_sli_mac_number_s {
+                uint64_t reserved_9_63:55;
+                uint64_t a_mode:1;
+                uint64_t num:8;
+        } s;
+        struct cvmx_sli_mac_number_s cn61xx;
+        struct cvmx_sli_mac_number_cn63xx {
+                uint64_t reserved_8_63:56;
+                uint64_t num:8;
+        } cn63xx;
+        struct cvmx_sli_mac_number_s cn66xx;
+        struct cvmx_sli_mac_number_cn63xx cn68xx;
+        struct cvmx_sli_mac_number_cn63xx cn68xxp1;
+};
+
+union cvmx_sli_mem_access_ctl {
+        uint64_t u64;
+        struct cvmx_sli_mem_access_ctl_s {
+                uint64_t reserved_14_63:50;
+                uint64_t max_word:4;
+                uint64_t timer:10;
+        } s;
+        struct cvmx_sli_mem_access_ctl_s cn61xx;
+        struct cvmx_sli_mem_access_ctl_s cn63xx;
+        struct cvmx_sli_mem_access_ctl_s cn63xxp1;
+        struct cvmx_sli_mem_access_ctl_s cn66xx;
+        struct cvmx_sli_mem_access_ctl_s cn68xx;
+        struct cvmx_sli_mem_access_ctl_s cn68xxp1;
+};
+
+union cvmx_sli_mem_access_subidx {
+        uint64_t u64;
+        struct cvmx_sli_mem_access_subidx_s {
+                uint64_t reserved_43_63:21;
+                uint64_t zero:1;
+                uint64_t port:3;
+                uint64_t nmerge:1;
+                uint64_t esr:2;
+                uint64_t esw:2;
+                uint64_t wtype:2;
+                uint64_t rtype:2;
+                uint64_t reserved_0_29:30;
+        } s;
+        struct cvmx_sli_mem_access_subidx_cn61xx {
+                uint64_t reserved_43_63:21;
+                uint64_t zero:1;
+                uint64_t port:3;
+                uint64_t nmerge:1;
+                uint64_t esr:2;
+                uint64_t esw:2;
+                uint64_t wtype:2;
+                uint64_t rtype:2;
+                uint64_t ba:30;
+        } cn61xx;
+        struct cvmx_sli_mem_access_subidx_cn61xx cn63xx;
+        struct cvmx_sli_mem_access_subidx_cn61xx cn63xxp1;
+        struct cvmx_sli_mem_access_subidx_cn61xx cn66xx;
+        struct cvmx_sli_mem_access_subidx_cn68xx {
+                uint64_t reserved_43_63:21;
+                uint64_t zero:1;
+                uint64_t port:3;
+                uint64_t nmerge:1;
+                uint64_t esr:2;
+                uint64_t esw:2;
+                uint64_t wtype:2;
+                uint64_t rtype:2;
+                uint64_t ba:28;
+                uint64_t reserved_0_1:2;
+        } cn68xx;
+        struct cvmx_sli_mem_access_subidx_cn68xx cn68xxp1;
+};
+
+union cvmx_sli_msi_enb0 {
+        uint64_t u64;
+        struct cvmx_sli_msi_enb0_s {
+                uint64_t enb:64;
+        } s;
+        struct cvmx_sli_msi_enb0_s cn61xx;
+        struct cvmx_sli_msi_enb0_s cn63xx;
+        struct cvmx_sli_msi_enb0_s cn63xxp1;
+        struct cvmx_sli_msi_enb0_s cn66xx;
+        struct cvmx_sli_msi_enb0_s cn68xx;
+        struct cvmx_sli_msi_enb0_s cn68xxp1;
+};
+
+union cvmx_sli_msi_enb1 {
+        uint64_t u64;
+        struct cvmx_sli_msi_enb1_s {
+                uint64_t enb:64;
+        } s;
+        struct cvmx_sli_msi_enb1_s cn61xx;
+        struct cvmx_sli_msi_enb1_s cn63xx;
+        struct cvmx_sli_msi_enb1_s cn63xxp1;
+        struct cvmx_sli_msi_enb1_s cn66xx;
+        struct cvmx_sli_msi_enb1_s cn68xx;
+        struct cvmx_sli_msi_enb1_s cn68xxp1;
+};
+
+union cvmx_sli_msi_enb2 {
+        uint64_t u64;
+        struct cvmx_sli_msi_enb2_s {
+                uint64_t enb:64;
+        } s;
+        struct cvmx_sli_msi_enb2_s cn61xx;
+        struct cvmx_sli_msi_enb2_s cn63xx;
+        struct cvmx_sli_msi_enb2_s cn63xxp1;
+        struct cvmx_sli_msi_enb2_s cn66xx;
+        struct cvmx_sli_msi_enb2_s cn68xx;
+        struct cvmx_sli_msi_enb2_s cn68xxp1;
+};
+
+union cvmx_sli_msi_enb3 {
+        uint64_t u64;
+        struct cvmx_sli_msi_enb3_s {
+                uint64_t enb:64;
+        } s;
+        struct cvmx_sli_msi_enb3_s cn61xx;
+        struct cvmx_sli_msi_enb3_s cn63xx;
+        struct cvmx_sli_msi_enb3_s cn63xxp1;
+        struct cvmx_sli_msi_enb3_s cn66xx;
+        struct cvmx_sli_msi_enb3_s cn68xx;
+        struct cvmx_sli_msi_enb3_s cn68xxp1;
+};
+
+union cvmx_sli_msi_rcv0 {
+        uint64_t u64;
+        struct cvmx_sli_msi_rcv0_s {
+                uint64_t intr:64;
+        } s;
+        struct cvmx_sli_msi_rcv0_s cn61xx;
+        struct cvmx_sli_msi_rcv0_s cn63xx;
+        struct cvmx_sli_msi_rcv0_s cn63xxp1;
+        struct cvmx_sli_msi_rcv0_s cn66xx;
+        struct cvmx_sli_msi_rcv0_s cn68xx;
+        struct cvmx_sli_msi_rcv0_s cn68xxp1;
+};
+
+union cvmx_sli_msi_rcv1 {
+        uint64_t u64;
+        struct cvmx_sli_msi_rcv1_s {
+                uint64_t intr:64;
+        } s;
+        struct cvmx_sli_msi_rcv1_s cn61xx;
+        struct cvmx_sli_msi_rcv1_s cn63xx;
+        struct cvmx_sli_msi_rcv1_s cn63xxp1;
+        struct cvmx_sli_msi_rcv1_s cn66xx;
+        struct cvmx_sli_msi_rcv1_s cn68xx;
+        struct cvmx_sli_msi_rcv1_s cn68xxp1;
+};
+
+union cvmx_sli_msi_rcv2 {
+        uint64_t u64;
+        struct cvmx_sli_msi_rcv2_s {
+                uint64_t intr:64;
+        } s;
+        struct cvmx_sli_msi_rcv2_s cn61xx;
+        struct cvmx_sli_msi_rcv2_s cn63xx;
+        struct cvmx_sli_msi_rcv2_s cn63xxp1;
+        struct cvmx_sli_msi_rcv2_s cn66xx;
+        struct cvmx_sli_msi_rcv2_s cn68xx;
+        struct cvmx_sli_msi_rcv2_s cn68xxp1;
+};
+
+union cvmx_sli_msi_rcv3 {
+        uint64_t u64;
+        struct cvmx_sli_msi_rcv3_s {
+                uint64_t intr:64;
+        } s;
+        struct cvmx_sli_msi_rcv3_s cn61xx;
+        struct cvmx_sli_msi_rcv3_s cn63xx;
+        struct cvmx_sli_msi_rcv3_s cn63xxp1;
+        struct cvmx_sli_msi_rcv3_s cn66xx;
+        struct cvmx_sli_msi_rcv3_s cn68xx;
+        struct cvmx_sli_msi_rcv3_s cn68xxp1;
+};
+
+union cvmx_sli_msi_rd_map {
+        uint64_t u64;
+        struct cvmx_sli_msi_rd_map_s {
+                uint64_t reserved_16_63:48;
+                uint64_t rd_int:8;
+                uint64_t msi_int:8;
+        } s;
+        struct cvmx_sli_msi_rd_map_s cn61xx;
+        struct cvmx_sli_msi_rd_map_s cn63xx;
+        struct cvmx_sli_msi_rd_map_s cn63xxp1;
+        struct cvmx_sli_msi_rd_map_s cn66xx;
+        struct cvmx_sli_msi_rd_map_s cn68xx;
+        struct cvmx_sli_msi_rd_map_s cn68xxp1;
+};
+
+union cvmx_sli_msi_w1c_enb0 {
+        uint64_t u64;
+        struct cvmx_sli_msi_w1c_enb0_s {
+                uint64_t clr:64;
+        } s;
+        struct cvmx_sli_msi_w1c_enb0_s cn61xx;
+        struct cvmx_sli_msi_w1c_enb0_s cn63xx;
+        struct cvmx_sli_msi_w1c_enb0_s cn63xxp1;
+        struct cvmx_sli_msi_w1c_enb0_s cn66xx;
+        struct cvmx_sli_msi_w1c_enb0_s cn68xx;
+        struct cvmx_sli_msi_w1c_enb0_s cn68xxp1;
+};
+
+union cvmx_sli_msi_w1c_enb1 {
+        uint64_t u64;
+        struct cvmx_sli_msi_w1c_enb1_s {
+                uint64_t clr:64;
+        } s;
+        struct cvmx_sli_msi_w1c_enb1_s cn61xx;
+        struct cvmx_sli_msi_w1c_enb1_s cn63xx;
+        struct cvmx_sli_msi_w1c_enb1_s cn63xxp1;
+        struct cvmx_sli_msi_w1c_enb1_s cn66xx;
+        struct cvmx_sli_msi_w1c_enb1_s cn68xx;
+        struct cvmx_sli_msi_w1c_enb1_s cn68xxp1;
+};
+
+union cvmx_sli_msi_w1c_enb2 {
+        uint64_t u64;
+        struct cvmx_sli_msi_w1c_enb2_s {
+                uint64_t clr:64;
+        } s;
+        struct cvmx_sli_msi_w1c_enb2_s cn61xx;
+        struct cvmx_sli_msi_w1c_enb2_s cn63xx;
+        struct cvmx_sli_msi_w1c_enb2_s cn63xxp1;
+        struct cvmx_sli_msi_w1c_enb2_s cn66xx;
+        struct cvmx_sli_msi_w1c_enb2_s cn68xx;
+        struct cvmx_sli_msi_w1c_enb2_s cn68xxp1;
+};
+
+union cvmx_sli_msi_w1c_enb3 {
+        uint64_t u64;
+        struct cvmx_sli_msi_w1c_enb3_s {
+                uint64_t clr:64;
+        } s;
+        struct cvmx_sli_msi_w1c_enb3_s cn61xx;
+        struct cvmx_sli_msi_w1c_enb3_s cn63xx;
+        struct cvmx_sli_msi_w1c_enb3_s cn63xxp1;
+        struct cvmx_sli_msi_w1c_enb3_s cn66xx;
+        struct cvmx_sli_msi_w1c_enb3_s cn68xx;
+        struct cvmx_sli_msi_w1c_enb3_s cn68xxp1;
+};
+
+union cvmx_sli_msi_w1s_enb0 {
+        uint64_t u64;
+        struct cvmx_sli_msi_w1s_enb0_s {
+                uint64_t set:64;
+        } s;
+        struct cvmx_sli_msi_w1s_enb0_s cn61xx;
+        struct cvmx_sli_msi_w1s_enb0_s cn63xx;
+        struct cvmx_sli_msi_w1s_enb0_s cn63xxp1;
+        struct cvmx_sli_msi_w1s_enb0_s cn66xx;
+        struct cvmx_sli_msi_w1s_enb0_s cn68xx;
+        struct cvmx_sli_msi_w1s_enb0_s cn68xxp1;
+};
+
+union cvmx_sli_msi_w1s_enb1 {
+        uint64_t u64;
+        struct cvmx_sli_msi_w1s_enb1_s {
+                uint64_t set:64;
+        } s;
+        struct cvmx_sli_msi_w1s_enb1_s cn61xx;
+        struct cvmx_sli_msi_w1s_enb1_s cn63xx;
+        struct cvmx_sli_msi_w1s_enb1_s cn63xxp1;
+        struct cvmx_sli_msi_w1s_enb1_s cn66xx;
+        struct cvmx_sli_msi_w1s_enb1_s cn68xx;
+        struct cvmx_sli_msi_w1s_enb1_s cn68xxp1;
+};
+
+union cvmx_sli_msi_w1s_enb2 {
+        uint64_t u64;
+        struct cvmx_sli_msi_w1s_enb2_s {
+                uint64_t set:64;
+        } s;
+        struct cvmx_sli_msi_w1s_enb2_s cn61xx;
+        struct cvmx_sli_msi_w1s_enb2_s cn63xx;
+        struct cvmx_sli_msi_w1s_enb2_s cn63xxp1;
+        struct cvmx_sli_msi_w1s_enb2_s cn66xx;
+        struct cvmx_sli_msi_w1s_enb2_s cn68xx;
+        struct cvmx_sli_msi_w1s_enb2_s cn68xxp1;
+};
+
+union cvmx_sli_msi_w1s_enb3 {
+        uint64_t u64;
+        struct cvmx_sli_msi_w1s_enb3_s {
+                uint64_t set:64;
+        } s;
+        struct cvmx_sli_msi_w1s_enb3_s cn61xx;
+        struct cvmx_sli_msi_w1s_enb3_s cn63xx;
+        struct cvmx_sli_msi_w1s_enb3_s cn63xxp1;
+        struct cvmx_sli_msi_w1s_enb3_s cn66xx;
+        struct cvmx_sli_msi_w1s_enb3_s cn68xx;
+        struct cvmx_sli_msi_w1s_enb3_s cn68xxp1;
+};
+
+union cvmx_sli_msi_wr_map {
+        uint64_t u64;
+        struct cvmx_sli_msi_wr_map_s {
+                uint64_t reserved_16_63:48;
+                uint64_t ciu_int:8;
+                uint64_t msi_int:8;
+        } s;
+        struct cvmx_sli_msi_wr_map_s cn61xx;
+        struct cvmx_sli_msi_wr_map_s cn63xx;
+        struct cvmx_sli_msi_wr_map_s cn63xxp1;
+        struct cvmx_sli_msi_wr_map_s cn66xx;
+        struct cvmx_sli_msi_wr_map_s cn68xx;
+        struct cvmx_sli_msi_wr_map_s cn68xxp1;
+};
+
+union cvmx_sli_pcie_msi_rcv {
+        uint64_t u64;
+        struct cvmx_sli_pcie_msi_rcv_s {
+                uint64_t reserved_8_63:56;
+                uint64_t intr:8;
+        } s;
+        struct cvmx_sli_pcie_msi_rcv_s cn61xx;
+        struct cvmx_sli_pcie_msi_rcv_s cn63xx;
+        struct cvmx_sli_pcie_msi_rcv_s cn63xxp1;
+        struct cvmx_sli_pcie_msi_rcv_s cn66xx;
+        struct cvmx_sli_pcie_msi_rcv_s cn68xx;
+        struct cvmx_sli_pcie_msi_rcv_s cn68xxp1;
+};
+
+union cvmx_sli_pcie_msi_rcv_b1 {
+        uint64_t u64;
+        struct cvmx_sli_pcie_msi_rcv_b1_s {
+                uint64_t reserved_16_63:48;
+                uint64_t intr:8;
+                uint64_t reserved_0_7:8;
+        } s;
+        struct cvmx_sli_pcie_msi_rcv_b1_s cn61xx;
+        struct cvmx_sli_pcie_msi_rcv_b1_s cn63xx;
+        struct cvmx_sli_pcie_msi_rcv_b1_s cn63xxp1;
+        struct cvmx_sli_pcie_msi_rcv_b1_s cn66xx;
+        struct cvmx_sli_pcie_msi_rcv_b1_s cn68xx;
+        struct cvmx_sli_pcie_msi_rcv_b1_s cn68xxp1;
+};
+
+union cvmx_sli_pcie_msi_rcv_b2 {
+        uint64_t u64;
+        struct cvmx_sli_pcie_msi_rcv_b2_s {
+                uint64_t reserved_24_63:40;
+                uint64_t intr:8;
+                uint64_t reserved_0_15:16;
+        } s;
+        struct cvmx_sli_pcie_msi_rcv_b2_s cn61xx;
+        struct cvmx_sli_pcie_msi_rcv_b2_s cn63xx;
+        struct cvmx_sli_pcie_msi_rcv_b2_s cn63xxp1;
+        struct cvmx_sli_pcie_msi_rcv_b2_s cn66xx;
+        struct cvmx_sli_pcie_msi_rcv_b2_s cn68xx;
+        struct cvmx_sli_pcie_msi_rcv_b2_s cn68xxp1;
+};
+
+union cvmx_sli_pcie_msi_rcv_b3 {
+        uint64_t u64;
+        struct cvmx_sli_pcie_msi_rcv_b3_s {
+                uint64_t reserved_32_63:32;
+                uint64_t intr:8;
+                uint64_t reserved_0_23:24;
+        } s;
+        struct cvmx_sli_pcie_msi_rcv_b3_s cn61xx;
+        struct cvmx_sli_pcie_msi_rcv_b3_s cn63xx;
+        struct cvmx_sli_pcie_msi_rcv_b3_s cn63xxp1;
+        struct cvmx_sli_pcie_msi_rcv_b3_s cn66xx;
+        struct cvmx_sli_pcie_msi_rcv_b3_s cn68xx;
+        struct cvmx_sli_pcie_msi_rcv_b3_s cn68xxp1;
+};
+
+union cvmx_sli_pktx_cnts {
+        uint64_t u64;
+        struct cvmx_sli_pktx_cnts_s {
+                uint64_t reserved_54_63:10;
+                uint64_t timer:22;
+                uint64_t cnt:32;
+        } s;
+        struct cvmx_sli_pktx_cnts_s cn61xx;
+        struct cvmx_sli_pktx_cnts_s cn63xx;
+        struct cvmx_sli_pktx_cnts_s cn63xxp1;
+        struct cvmx_sli_pktx_cnts_s cn66xx;
+        struct cvmx_sli_pktx_cnts_s cn68xx;
+        struct cvmx_sli_pktx_cnts_s cn68xxp1;
+};
+
+union cvmx_sli_pktx_in_bp {
+        uint64_t u64;
+        struct cvmx_sli_pktx_in_bp_s {
+                uint64_t wmark:32;
+                uint64_t cnt:32;
+        } s;
+        struct cvmx_sli_pktx_in_bp_s cn61xx;
+        struct cvmx_sli_pktx_in_bp_s cn63xx;
+        struct cvmx_sli_pktx_in_bp_s cn63xxp1;
+        struct cvmx_sli_pktx_in_bp_s cn66xx;
+};
+
+union cvmx_sli_pktx_instr_baddr {
+        uint64_t u64;
+        struct cvmx_sli_pktx_instr_baddr_s {
+                uint64_t addr:61;
+                uint64_t reserved_0_2:3;
+        } s;
+        struct cvmx_sli_pktx_instr_baddr_s cn61xx;
+        struct cvmx_sli_pktx_instr_baddr_s cn63xx;
+        struct cvmx_sli_pktx_instr_baddr_s cn63xxp1;
+        struct cvmx_sli_pktx_instr_baddr_s cn66xx;
+        struct cvmx_sli_pktx_instr_baddr_s cn68xx;
+        struct cvmx_sli_pktx_instr_baddr_s cn68xxp1;
+};
+
+union cvmx_sli_pktx_instr_baoff_dbell {
+        uint64_t u64;
+        struct cvmx_sli_pktx_instr_baoff_dbell_s {
+                uint64_t aoff:32;
+                uint64_t dbell:32;
+        } s;
+        struct cvmx_sli_pktx_instr_baoff_dbell_s cn61xx;
+        struct cvmx_sli_pktx_instr_baoff_dbell_s cn63xx;
+        struct cvmx_sli_pktx_instr_baoff_dbell_s cn63xxp1;
+        struct cvmx_sli_pktx_instr_baoff_dbell_s cn66xx;
+        struct cvmx_sli_pktx_instr_baoff_dbell_s cn68xx;
+        struct cvmx_sli_pktx_instr_baoff_dbell_s cn68xxp1;
+};
+
+union cvmx_sli_pktx_instr_fifo_rsize {
+        uint64_t u64;
+        struct cvmx_sli_pktx_instr_fifo_rsize_s {
+                uint64_t max:9;
+                uint64_t rrp:9;
+                uint64_t wrp:9;
+                uint64_t fcnt:5;
+                uint64_t rsize:32;
+        } s;
+        struct cvmx_sli_pktx_instr_fifo_rsize_s cn61xx;
+        struct cvmx_sli_pktx_instr_fifo_rsize_s cn63xx;
+        struct cvmx_sli_pktx_instr_fifo_rsize_s cn63xxp1;
+        struct cvmx_sli_pktx_instr_fifo_rsize_s cn66xx;
+        struct cvmx_sli_pktx_instr_fifo_rsize_s cn68xx;
+        struct cvmx_sli_pktx_instr_fifo_rsize_s cn68xxp1;
+};
+
+union cvmx_sli_pktx_instr_header {
+        uint64_t u64;
+        struct cvmx_sli_pktx_instr_header_s {
+                uint64_t reserved_44_63:20;
+                uint64_t pbp:1;
+                uint64_t reserved_38_42:5;
+                uint64_t rparmode:2;
+                uint64_t reserved_35_35:1;
+                uint64_t rskp_len:7;
+                uint64_t rngrpext:2;
+                uint64_t rnqos:1;
+                uint64_t rngrp:1;
+                uint64_t rntt:1;
+                uint64_t rntag:1;
+                uint64_t use_ihdr:1;
+                uint64_t reserved_16_20:5;
+                uint64_t par_mode:2;
+                uint64_t reserved_13_13:1;
+                uint64_t skp_len:7;
+                uint64_t ngrpext:2;
+                uint64_t nqos:1;
+                uint64_t ngrp:1;
+                uint64_t ntt:1;
+                uint64_t ntag:1;
+        } s;
+        struct cvmx_sli_pktx_instr_header_cn61xx {
+                uint64_t reserved_44_63:20;
+                uint64_t pbp:1;
+                uint64_t reserved_38_42:5;
+                uint64_t rparmode:2;
+                uint64_t reserved_35_35:1;
+                uint64_t rskp_len:7;
+                uint64_t reserved_26_27:2;
+                uint64_t rnqos:1;
+                uint64_t rngrp:1;
+                uint64_t rntt:1;
+                uint64_t rntag:1;
+                uint64_t use_ihdr:1;
+                uint64_t reserved_16_20:5;
+                uint64_t par_mode:2;
+                uint64_t reserved_13_13:1;
+                uint64_t skp_len:7;
+                uint64_t reserved_4_5:2;
+                uint64_t nqos:1;
+                uint64_t ngrp:1;
+                uint64_t ntt:1;
+                uint64_t ntag:1;
+        } cn61xx;
+        struct cvmx_sli_pktx_instr_header_cn61xx cn63xx;
+        struct cvmx_sli_pktx_instr_header_cn61xx cn63xxp1;
+        struct cvmx_sli_pktx_instr_header_cn61xx cn66xx;
+        struct cvmx_sli_pktx_instr_header_s cn68xx;
+        struct cvmx_sli_pktx_instr_header_cn61xx cn68xxp1;
+};
+
+union cvmx_sli_pktx_out_size {
+        uint64_t u64;
+        struct cvmx_sli_pktx_out_size_s {
+                uint64_t reserved_23_63:41;
+                uint64_t isize:7;
+                uint64_t bsize:16;
+        } s;
+        struct cvmx_sli_pktx_out_size_s cn61xx;
+        struct cvmx_sli_pktx_out_size_s cn63xx;
+        struct cvmx_sli_pktx_out_size_s cn63xxp1;
+        struct cvmx_sli_pktx_out_size_s cn66xx;
+        struct cvmx_sli_pktx_out_size_s cn68xx;
+        struct cvmx_sli_pktx_out_size_s cn68xxp1;
+};
+
+union cvmx_sli_pktx_slist_baddr {
+        uint64_t u64;
+        struct cvmx_sli_pktx_slist_baddr_s {
+                uint64_t addr:60;
+                uint64_t reserved_0_3:4;
+        } s;
+        struct cvmx_sli_pktx_slist_baddr_s cn61xx;
+        struct cvmx_sli_pktx_slist_baddr_s cn63xx;
+        struct cvmx_sli_pktx_slist_baddr_s cn63xxp1;
+        struct cvmx_sli_pktx_slist_baddr_s cn66xx;
+        struct cvmx_sli_pktx_slist_baddr_s cn68xx;
+        struct cvmx_sli_pktx_slist_baddr_s cn68xxp1;
+};
+
+union cvmx_sli_pktx_slist_baoff_dbell {
+        uint64_t u64;
+        struct cvmx_sli_pktx_slist_baoff_dbell_s {
+                uint64_t aoff:32;
+                uint64_t dbell:32;
+        } s;
+        struct cvmx_sli_pktx_slist_baoff_dbell_s cn61xx;
+        struct cvmx_sli_pktx_slist_baoff_dbell_s cn63xx;
+        struct cvmx_sli_pktx_slist_baoff_dbell_s cn63xxp1;
+        struct cvmx_sli_pktx_slist_baoff_dbell_s cn66xx;
+        struct cvmx_sli_pktx_slist_baoff_dbell_s cn68xx;
+        struct cvmx_sli_pktx_slist_baoff_dbell_s cn68xxp1;
+};
+
+union cvmx_sli_pktx_slist_fifo_rsize {
+        uint64_t u64;
+        struct cvmx_sli_pktx_slist_fifo_rsize_s {
+                uint64_t reserved_32_63:32;
+                uint64_t rsize:32;
+        } s;
+        struct cvmx_sli_pktx_slist_fifo_rsize_s cn61xx;
+        struct cvmx_sli_pktx_slist_fifo_rsize_s cn63xx;
+        struct cvmx_sli_pktx_slist_fifo_rsize_s cn63xxp1;
+        struct cvmx_sli_pktx_slist_fifo_rsize_s cn66xx;
+        struct cvmx_sli_pktx_slist_fifo_rsize_s cn68xx;
+        struct cvmx_sli_pktx_slist_fifo_rsize_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_cnt_int {
+        uint64_t u64;
+        struct cvmx_sli_pkt_cnt_int_s {
+                uint64_t reserved_32_63:32;
+                uint64_t port:32;
+        } s;
+        struct cvmx_sli_pkt_cnt_int_s cn61xx;
+        struct cvmx_sli_pkt_cnt_int_s cn63xx;
+        struct cvmx_sli_pkt_cnt_int_s cn63xxp1;
+        struct cvmx_sli_pkt_cnt_int_s cn66xx;
+        struct cvmx_sli_pkt_cnt_int_s cn68xx;
+        struct cvmx_sli_pkt_cnt_int_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_cnt_int_enb {
+        uint64_t u64;
+        struct cvmx_sli_pkt_cnt_int_enb_s {
+                uint64_t reserved_32_63:32;
+                uint64_t port:32;
+        } s;
+        struct cvmx_sli_pkt_cnt_int_enb_s cn61xx;
+        struct cvmx_sli_pkt_cnt_int_enb_s cn63xx;
+        struct cvmx_sli_pkt_cnt_int_enb_s cn63xxp1;
+        struct cvmx_sli_pkt_cnt_int_enb_s cn66xx;
+        struct cvmx_sli_pkt_cnt_int_enb_s cn68xx;
+        struct cvmx_sli_pkt_cnt_int_enb_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_ctl {
+        uint64_t u64;
+        struct cvmx_sli_pkt_ctl_s {
+                uint64_t reserved_5_63:59;
+                uint64_t ring_en:1;
+                uint64_t pkt_bp:4;
+        } s;
+        struct cvmx_sli_pkt_ctl_s cn61xx;
+        struct cvmx_sli_pkt_ctl_s cn63xx;
+        struct cvmx_sli_pkt_ctl_s cn63xxp1;
+        struct cvmx_sli_pkt_ctl_s cn66xx;
+        struct cvmx_sli_pkt_ctl_s cn68xx;
+        struct cvmx_sli_pkt_ctl_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_data_out_es {
+        uint64_t u64;
+        struct cvmx_sli_pkt_data_out_es_s {
+                uint64_t es:64;
+        } s;
+        struct cvmx_sli_pkt_data_out_es_s cn61xx;
+        struct cvmx_sli_pkt_data_out_es_s cn63xx;
+        struct cvmx_sli_pkt_data_out_es_s cn63xxp1;
+        struct cvmx_sli_pkt_data_out_es_s cn66xx;
+        struct cvmx_sli_pkt_data_out_es_s cn68xx;
+        struct cvmx_sli_pkt_data_out_es_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_data_out_ns {
+        uint64_t u64;
+        struct cvmx_sli_pkt_data_out_ns_s {
+                uint64_t reserved_32_63:32;
+                uint64_t nsr:32;
+        } s;
+        struct cvmx_sli_pkt_data_out_ns_s cn61xx;
+        struct cvmx_sli_pkt_data_out_ns_s cn63xx;
+        struct cvmx_sli_pkt_data_out_ns_s cn63xxp1;
+        struct cvmx_sli_pkt_data_out_ns_s cn66xx;
+        struct cvmx_sli_pkt_data_out_ns_s cn68xx;
+        struct cvmx_sli_pkt_data_out_ns_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_data_out_ror {
+        uint64_t u64;
+        struct cvmx_sli_pkt_data_out_ror_s {
+                uint64_t reserved_32_63:32;
+                uint64_t ror:32;
+        } s;
+        struct cvmx_sli_pkt_data_out_ror_s cn61xx;
+        struct cvmx_sli_pkt_data_out_ror_s cn63xx;
+        struct cvmx_sli_pkt_data_out_ror_s cn63xxp1;
+        struct cvmx_sli_pkt_data_out_ror_s cn66xx;
+        struct cvmx_sli_pkt_data_out_ror_s cn68xx;
+        struct cvmx_sli_pkt_data_out_ror_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_dpaddr {
+        uint64_t u64;
+        struct cvmx_sli_pkt_dpaddr_s {
+                uint64_t reserved_32_63:32;
+                uint64_t dptr:32;
+        } s;
+        struct cvmx_sli_pkt_dpaddr_s cn61xx;
+        struct cvmx_sli_pkt_dpaddr_s cn63xx;
+        struct cvmx_sli_pkt_dpaddr_s cn63xxp1;
+        struct cvmx_sli_pkt_dpaddr_s cn66xx;
+        struct cvmx_sli_pkt_dpaddr_s cn68xx;
+        struct cvmx_sli_pkt_dpaddr_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_in_bp {
+        uint64_t u64;
+        struct cvmx_sli_pkt_in_bp_s {
+                uint64_t reserved_32_63:32;
+                uint64_t bp:32;
+        } s;
+        struct cvmx_sli_pkt_in_bp_s cn61xx;
+        struct cvmx_sli_pkt_in_bp_s cn63xx;
+        struct cvmx_sli_pkt_in_bp_s cn63xxp1;
+        struct cvmx_sli_pkt_in_bp_s cn66xx;
+};
+
+union cvmx_sli_pkt_in_donex_cnts {
+        uint64_t u64;
+        struct cvmx_sli_pkt_in_donex_cnts_s {
+                uint64_t reserved_32_63:32;
+                uint64_t cnt:32;
+        } s;
+        struct cvmx_sli_pkt_in_donex_cnts_s cn61xx;
+        struct cvmx_sli_pkt_in_donex_cnts_s cn63xx;
+        struct cvmx_sli_pkt_in_donex_cnts_s cn63xxp1;
+        struct cvmx_sli_pkt_in_donex_cnts_s cn66xx;
+        struct cvmx_sli_pkt_in_donex_cnts_s cn68xx;
+        struct cvmx_sli_pkt_in_donex_cnts_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_in_instr_counts {
+        uint64_t u64;
+        struct cvmx_sli_pkt_in_instr_counts_s {
+                uint64_t wr_cnt:32;
+                uint64_t rd_cnt:32;
+        } s;
+        struct cvmx_sli_pkt_in_instr_counts_s cn61xx;
+        struct cvmx_sli_pkt_in_instr_counts_s cn63xx;
+        struct cvmx_sli_pkt_in_instr_counts_s cn63xxp1;
+        struct cvmx_sli_pkt_in_instr_counts_s cn66xx;
+        struct cvmx_sli_pkt_in_instr_counts_s cn68xx;
+        struct cvmx_sli_pkt_in_instr_counts_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_in_pcie_port {
+        uint64_t u64;
+        struct cvmx_sli_pkt_in_pcie_port_s {
+                uint64_t pp:64;
+        } s;
+        struct cvmx_sli_pkt_in_pcie_port_s cn61xx;
+        struct cvmx_sli_pkt_in_pcie_port_s cn63xx;
+        struct cvmx_sli_pkt_in_pcie_port_s cn63xxp1;
+        struct cvmx_sli_pkt_in_pcie_port_s cn66xx;
+        struct cvmx_sli_pkt_in_pcie_port_s cn68xx;
+        struct cvmx_sli_pkt_in_pcie_port_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_input_control {
+        uint64_t u64;
+        struct cvmx_sli_pkt_input_control_s {
+                uint64_t prd_erst:1;
+                uint64_t prd_rds:7;
+                uint64_t gii_erst:1;
+                uint64_t gii_rds:7;
+                uint64_t reserved_41_47:7;
+                uint64_t prc_idle:1;
+                uint64_t reserved_24_39:16;
+                uint64_t pin_rst:1;
+                uint64_t pkt_rr:1;
+                uint64_t pbp_dhi:13;
+                uint64_t d_nsr:1;
+                uint64_t d_esr:2;
+                uint64_t d_ror:1;
+                uint64_t use_csr:1;
+                uint64_t nsr:1;
+                uint64_t esr:2;
+                uint64_t ror:1;
+        } s;
+        struct cvmx_sli_pkt_input_control_s cn61xx;
+        struct cvmx_sli_pkt_input_control_cn63xx {
+                uint64_t reserved_23_63:41;
+                uint64_t pkt_rr:1;
+                uint64_t pbp_dhi:13;
+                uint64_t d_nsr:1;
+                uint64_t d_esr:2;
+                uint64_t d_ror:1;
+                uint64_t use_csr:1;
+                uint64_t nsr:1;
+                uint64_t esr:2;
+                uint64_t ror:1;
+        } cn63xx;
+        struct cvmx_sli_pkt_input_control_cn63xx cn63xxp1;
+        struct cvmx_sli_pkt_input_control_s cn66xx;
+        struct cvmx_sli_pkt_input_control_s cn68xx;
+        struct cvmx_sli_pkt_input_control_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_instr_enb {
+        uint64_t u64;
+        struct cvmx_sli_pkt_instr_enb_s {
+                uint64_t reserved_32_63:32;
+                uint64_t enb:32;
+        } s;
+        struct cvmx_sli_pkt_instr_enb_s cn61xx;
+        struct cvmx_sli_pkt_instr_enb_s cn63xx;
+        struct cvmx_sli_pkt_instr_enb_s cn63xxp1;
+        struct cvmx_sli_pkt_instr_enb_s cn66xx;
+        struct cvmx_sli_pkt_instr_enb_s cn68xx;
+        struct cvmx_sli_pkt_instr_enb_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_instr_rd_size {
+        uint64_t u64;
+        struct cvmx_sli_pkt_instr_rd_size_s {
+                uint64_t rdsize:64;
+        } s;
+        struct cvmx_sli_pkt_instr_rd_size_s cn61xx;
+        struct cvmx_sli_pkt_instr_rd_size_s cn63xx;
+        struct cvmx_sli_pkt_instr_rd_size_s cn63xxp1;
+        struct cvmx_sli_pkt_instr_rd_size_s cn66xx;
+        struct cvmx_sli_pkt_instr_rd_size_s cn68xx;
+        struct cvmx_sli_pkt_instr_rd_size_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_instr_size {
+        uint64_t u64;
+        struct cvmx_sli_pkt_instr_size_s {
+                uint64_t reserved_32_63:32;
+                uint64_t is_64b:32;
+        } s;
+        struct cvmx_sli_pkt_instr_size_s cn61xx;
+        struct cvmx_sli_pkt_instr_size_s cn63xx;
+        struct cvmx_sli_pkt_instr_size_s cn63xxp1;
+        struct cvmx_sli_pkt_instr_size_s cn66xx;
+        struct cvmx_sli_pkt_instr_size_s cn68xx;
+        struct cvmx_sli_pkt_instr_size_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_int_levels {
+        uint64_t u64;
+        struct cvmx_sli_pkt_int_levels_s {
+                uint64_t reserved_54_63:10;
+                uint64_t time:22;
+                uint64_t cnt:32;
+        } s;
+        struct cvmx_sli_pkt_int_levels_s cn61xx;
+        struct cvmx_sli_pkt_int_levels_s cn63xx;
+        struct cvmx_sli_pkt_int_levels_s cn63xxp1;
+        struct cvmx_sli_pkt_int_levels_s cn66xx;
+        struct cvmx_sli_pkt_int_levels_s cn68xx;
+        struct cvmx_sli_pkt_int_levels_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_iptr {
+        uint64_t u64;
+        struct cvmx_sli_pkt_iptr_s {
+                uint64_t reserved_32_63:32;
+                uint64_t iptr:32;
+        } s;
+        struct cvmx_sli_pkt_iptr_s cn61xx;
+        struct cvmx_sli_pkt_iptr_s cn63xx;
+        struct cvmx_sli_pkt_iptr_s cn63xxp1;
+        struct cvmx_sli_pkt_iptr_s cn66xx;
+        struct cvmx_sli_pkt_iptr_s cn68xx;
+        struct cvmx_sli_pkt_iptr_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_out_bmode {
+        uint64_t u64;
+        struct cvmx_sli_pkt_out_bmode_s {
+                uint64_t reserved_32_63:32;
+                uint64_t bmode:32;
+        } s;
+        struct cvmx_sli_pkt_out_bmode_s cn61xx;
+        struct cvmx_sli_pkt_out_bmode_s cn63xx;
+        struct cvmx_sli_pkt_out_bmode_s cn63xxp1;
+        struct cvmx_sli_pkt_out_bmode_s cn66xx;
+        struct cvmx_sli_pkt_out_bmode_s cn68xx;
+        struct cvmx_sli_pkt_out_bmode_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_out_bp_en {
+        uint64_t u64;
+        struct cvmx_sli_pkt_out_bp_en_s {
+                uint64_t reserved_32_63:32;
+                uint64_t bp_en:32;
+        } s;
+        struct cvmx_sli_pkt_out_bp_en_s cn68xx;
+        struct cvmx_sli_pkt_out_bp_en_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_out_enb {
+        uint64_t u64;
+        struct cvmx_sli_pkt_out_enb_s {
+                uint64_t reserved_32_63:32;
+                uint64_t enb:32;
+        } s;
+        struct cvmx_sli_pkt_out_enb_s cn61xx;
+        struct cvmx_sli_pkt_out_enb_s cn63xx;
+        struct cvmx_sli_pkt_out_enb_s cn63xxp1;
+        struct cvmx_sli_pkt_out_enb_s cn66xx;
+        struct cvmx_sli_pkt_out_enb_s cn68xx;
+        struct cvmx_sli_pkt_out_enb_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_output_wmark {
+        uint64_t u64;
+        struct cvmx_sli_pkt_output_wmark_s {
+                uint64_t reserved_32_63:32;
+                uint64_t wmark:32;
+        } s;
+        struct cvmx_sli_pkt_output_wmark_s cn61xx;
+        struct cvmx_sli_pkt_output_wmark_s cn63xx;
+        struct cvmx_sli_pkt_output_wmark_s cn63xxp1;
+        struct cvmx_sli_pkt_output_wmark_s cn66xx;
+        struct cvmx_sli_pkt_output_wmark_s cn68xx;
+        struct cvmx_sli_pkt_output_wmark_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_pcie_port {
+        uint64_t u64;
+        struct cvmx_sli_pkt_pcie_port_s {
+                uint64_t pp:64;
+        } s;
+        struct cvmx_sli_pkt_pcie_port_s cn61xx;
+        struct cvmx_sli_pkt_pcie_port_s cn63xx;
+        struct cvmx_sli_pkt_pcie_port_s cn63xxp1;
+        struct cvmx_sli_pkt_pcie_port_s cn66xx;
+        struct cvmx_sli_pkt_pcie_port_s cn68xx;
+        struct cvmx_sli_pkt_pcie_port_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_port_in_rst {
+        uint64_t u64;
+        struct cvmx_sli_pkt_port_in_rst_s {
+                uint64_t in_rst:32;
+                uint64_t out_rst:32;
+        } s;
+        struct cvmx_sli_pkt_port_in_rst_s cn61xx;
+        struct cvmx_sli_pkt_port_in_rst_s cn63xx;
+        struct cvmx_sli_pkt_port_in_rst_s cn63xxp1;
+        struct cvmx_sli_pkt_port_in_rst_s cn66xx;
+        struct cvmx_sli_pkt_port_in_rst_s cn68xx;
+        struct cvmx_sli_pkt_port_in_rst_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_slist_es {
+        uint64_t u64;
+        struct cvmx_sli_pkt_slist_es_s {
+                uint64_t es:64;
+        } s;
+        struct cvmx_sli_pkt_slist_es_s cn61xx;
+        struct cvmx_sli_pkt_slist_es_s cn63xx;
+        struct cvmx_sli_pkt_slist_es_s cn63xxp1;
+        struct cvmx_sli_pkt_slist_es_s cn66xx;
+        struct cvmx_sli_pkt_slist_es_s cn68xx;
+        struct cvmx_sli_pkt_slist_es_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_slist_ns {
+        uint64_t u64;
+        struct cvmx_sli_pkt_slist_ns_s {
+                uint64_t reserved_32_63:32;
+                uint64_t nsr:32;
+        } s;
+        struct cvmx_sli_pkt_slist_ns_s cn61xx;
+        struct cvmx_sli_pkt_slist_ns_s cn63xx;
+        struct cvmx_sli_pkt_slist_ns_s cn63xxp1;
+        struct cvmx_sli_pkt_slist_ns_s cn66xx;
+        struct cvmx_sli_pkt_slist_ns_s cn68xx;
+        struct cvmx_sli_pkt_slist_ns_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_slist_ror {
+        uint64_t u64;
+        struct cvmx_sli_pkt_slist_ror_s {
+                uint64_t reserved_32_63:32;
+                uint64_t ror:32;
+        } s;
+        struct cvmx_sli_pkt_slist_ror_s cn61xx;
+        struct cvmx_sli_pkt_slist_ror_s cn63xx;
+        struct cvmx_sli_pkt_slist_ror_s cn63xxp1;
+        struct cvmx_sli_pkt_slist_ror_s cn66xx;
+        struct cvmx_sli_pkt_slist_ror_s cn68xx;
+        struct cvmx_sli_pkt_slist_ror_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_time_int {
+        uint64_t u64;
+        struct cvmx_sli_pkt_time_int_s {
+                uint64_t reserved_32_63:32;
+                uint64_t port:32;
+        } s;
+        struct cvmx_sli_pkt_time_int_s cn61xx;
+        struct cvmx_sli_pkt_time_int_s cn63xx;
+        struct cvmx_sli_pkt_time_int_s cn63xxp1;
+        struct cvmx_sli_pkt_time_int_s cn66xx;
+        struct cvmx_sli_pkt_time_int_s cn68xx;
+        struct cvmx_sli_pkt_time_int_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_time_int_enb {
+        uint64_t u64;
+        struct cvmx_sli_pkt_time_int_enb_s {
+                uint64_t reserved_32_63:32;
+                uint64_t port:32;
+        } s;
+        struct cvmx_sli_pkt_time_int_enb_s cn61xx;
+        struct cvmx_sli_pkt_time_int_enb_s cn63xx;
+        struct cvmx_sli_pkt_time_int_enb_s cn63xxp1;
+        struct cvmx_sli_pkt_time_int_enb_s cn66xx;
+        struct cvmx_sli_pkt_time_int_enb_s cn68xx;
+        struct cvmx_sli_pkt_time_int_enb_s cn68xxp1;
+};
+
+union cvmx_sli_portx_pkind {
+        uint64_t u64;
+        struct cvmx_sli_portx_pkind_s {
+                uint64_t reserved_25_63:39;
+                uint64_t rpk_enb:1;
+                uint64_t reserved_22_23:2;
+                uint64_t pkindr:6;
+                uint64_t reserved_14_15:2;
+                uint64_t bpkind:6;
+                uint64_t reserved_6_7:2;
+                uint64_t pkind:6;
+        } s;
+        struct cvmx_sli_portx_pkind_s cn68xx;
+        struct cvmx_sli_portx_pkind_cn68xxp1 {
+                uint64_t reserved_14_63:50;
+                uint64_t bpkind:6;
+                uint64_t reserved_6_7:2;
+                uint64_t pkind:6;
+        } cn68xxp1;
+};
+
+union cvmx_sli_s2m_portx_ctl {
+        uint64_t u64;
+        struct cvmx_sli_s2m_portx_ctl_s {
+                uint64_t reserved_5_63:59;
+                uint64_t wind_d:1;
+                uint64_t bar0_d:1;
+                uint64_t mrrs:3;
+        } s;
+        struct cvmx_sli_s2m_portx_ctl_s cn61xx;
+        struct cvmx_sli_s2m_portx_ctl_s cn63xx;
+        struct cvmx_sli_s2m_portx_ctl_s cn63xxp1;
+        struct cvmx_sli_s2m_portx_ctl_s cn66xx;
+        struct cvmx_sli_s2m_portx_ctl_s cn68xx;
+        struct cvmx_sli_s2m_portx_ctl_s cn68xxp1;
+};
+
+union cvmx_sli_scratch_1 {
+        uint64_t u64;
+        struct cvmx_sli_scratch_1_s {
+                uint64_t data:64;
+        } s;
+        struct cvmx_sli_scratch_1_s cn61xx;
+        struct cvmx_sli_scratch_1_s cn63xx;
+        struct cvmx_sli_scratch_1_s cn63xxp1;
+        struct cvmx_sli_scratch_1_s cn66xx;
+        struct cvmx_sli_scratch_1_s cn68xx;
+        struct cvmx_sli_scratch_1_s cn68xxp1;
+};
+
+union cvmx_sli_scratch_2 {
+        uint64_t u64;
+        struct cvmx_sli_scratch_2_s {
+                uint64_t data:64;
+        } s;
+        struct cvmx_sli_scratch_2_s cn61xx;
+        struct cvmx_sli_scratch_2_s cn63xx;
+        struct cvmx_sli_scratch_2_s cn63xxp1;
+        struct cvmx_sli_scratch_2_s cn66xx;
+        struct cvmx_sli_scratch_2_s cn68xx;
+        struct cvmx_sli_scratch_2_s cn68xxp1;
+};
+
+union cvmx_sli_state1 {
+        uint64_t u64;
+        struct cvmx_sli_state1_s {
+                uint64_t cpl1:12;
+                uint64_t cpl0:12;
+                uint64_t arb:1;
+                uint64_t csr:39;
+        } s;
+        struct cvmx_sli_state1_s cn61xx;
+        struct cvmx_sli_state1_s cn63xx;
+        struct cvmx_sli_state1_s cn63xxp1;
+        struct cvmx_sli_state1_s cn66xx;
+        struct cvmx_sli_state1_s cn68xx;
+        struct cvmx_sli_state1_s cn68xxp1;
+};
+
+union cvmx_sli_state2 {
+        uint64_t u64;
+        struct cvmx_sli_state2_s {
+                uint64_t reserved_56_63:8;
+                uint64_t nnp1:8;
+                uint64_t reserved_47_47:1;
+                uint64_t rac:1;
+                uint64_t csm1:15;
+                uint64_t csm0:15;
+                uint64_t nnp0:8;
+                uint64_t nnd:8;
+        } s;
+        struct cvmx_sli_state2_s cn61xx;
+        struct cvmx_sli_state2_s cn63xx;
+        struct cvmx_sli_state2_s cn63xxp1;
+        struct cvmx_sli_state2_s cn66xx;
+        struct cvmx_sli_state2_s cn68xx;
+        struct cvmx_sli_state2_s cn68xxp1;
+};
+
+union cvmx_sli_state3 {
+        uint64_t u64;
+        struct cvmx_sli_state3_s {
+                uint64_t reserved_56_63:8;
+                uint64_t psm1:15;
+                uint64_t psm0:15;
+                uint64_t nsm1:13;
+                uint64_t nsm0:13;
+        } s;
+        struct cvmx_sli_state3_s cn61xx;
+        struct cvmx_sli_state3_s cn63xx;
+        struct cvmx_sli_state3_s cn63xxp1;
+        struct cvmx_sli_state3_s cn66xx;
+        struct cvmx_sli_state3_s cn68xx;
+        struct cvmx_sli_state3_s cn68xxp1;
+};
+
+union cvmx_sli_tx_pipe {
+        uint64_t u64;
+        struct cvmx_sli_tx_pipe_s {
+                uint64_t reserved_24_63:40;
+                uint64_t nump:8;
+                uint64_t reserved_7_15:9;
+                uint64_t base:7;
+        } s;
+        struct cvmx_sli_tx_pipe_s cn68xx;
+        struct cvmx_sli_tx_pipe_s cn68xxp1;
+};
+
+union cvmx_sli_win_rd_addr {
+        uint64_t u64;
+        struct cvmx_sli_win_rd_addr_s {
+                uint64_t reserved_51_63:13;
+                uint64_t ld_cmd:2;
+                uint64_t iobit:1;
+                uint64_t rd_addr:48;
+        } s;
+        struct cvmx_sli_win_rd_addr_s cn61xx;
+        struct cvmx_sli_win_rd_addr_s cn63xx;
+        struct cvmx_sli_win_rd_addr_s cn63xxp1;
+        struct cvmx_sli_win_rd_addr_s cn66xx;
+        struct cvmx_sli_win_rd_addr_s cn68xx;
+        struct cvmx_sli_win_rd_addr_s cn68xxp1;
+};
+
+union cvmx_sli_win_rd_data {
+        uint64_t u64;
+        struct cvmx_sli_win_rd_data_s {
+                uint64_t rd_data:64;
+        } s;
+        struct cvmx_sli_win_rd_data_s cn61xx;
+        struct cvmx_sli_win_rd_data_s cn63xx;
+        struct cvmx_sli_win_rd_data_s cn63xxp1;
+        struct cvmx_sli_win_rd_data_s cn66xx;
+        struct cvmx_sli_win_rd_data_s cn68xx;
+        struct cvmx_sli_win_rd_data_s cn68xxp1;
+};
+
+union cvmx_sli_win_wr_addr {
+        uint64_t u64;
+        struct cvmx_sli_win_wr_addr_s {
+                uint64_t reserved_49_63:15;
+                uint64_t iobit:1;
+                uint64_t wr_addr:45;
+                uint64_t reserved_0_2:3;
+        } s;
+        struct cvmx_sli_win_wr_addr_s cn61xx;
+        struct cvmx_sli_win_wr_addr_s cn63xx;
+        struct cvmx_sli_win_wr_addr_s cn63xxp1;
+        struct cvmx_sli_win_wr_addr_s cn66xx;
+        struct cvmx_sli_win_wr_addr_s cn68xx;
+        struct cvmx_sli_win_wr_addr_s cn68xxp1;
+};
+
+union cvmx_sli_win_wr_data {
+        uint64_t u64;
+        struct cvmx_sli_win_wr_data_s {
+                uint64_t wr_data:64;
+        } s;
+        struct cvmx_sli_win_wr_data_s cn61xx;
+        struct cvmx_sli_win_wr_data_s cn63xx;
+        struct cvmx_sli_win_wr_data_s cn63xxp1;
+        struct cvmx_sli_win_wr_data_s cn66xx;
+        struct cvmx_sli_win_wr_data_s cn68xx;
+        struct cvmx_sli_win_wr_data_s cn68xxp1;
+};
+
+union cvmx_sli_win_wr_mask {
+        uint64_t u64;
+        struct cvmx_sli_win_wr_mask_s {
+                uint64_t reserved_8_63:56;
+                uint64_t wr_mask:8;
+        } s;
+        struct cvmx_sli_win_wr_mask_s cn61xx;
+        struct cvmx_sli_win_wr_mask_s cn63xx;
+        struct cvmx_sli_win_wr_mask_s cn63xxp1;
+        struct cvmx_sli_win_wr_mask_s cn66xx;
+        struct cvmx_sli_win_wr_mask_s cn68xx;
+        struct cvmx_sli_win_wr_mask_s cn68xxp1;
+};
+
+union cvmx_sli_window_ctl {
+        uint64_t u64;
+        struct cvmx_sli_window_ctl_s {
+                uint64_t reserved_32_63:32;
+                uint64_t time:32;
+        } s;
+        struct cvmx_sli_window_ctl_s cn61xx;
+        struct cvmx_sli_window_ctl_s cn63xx;
+        struct cvmx_sli_window_ctl_s cn63xxp1;
+        struct cvmx_sli_window_ctl_s cn66xx;
+        struct cvmx_sli_window_ctl_s cn68xx;
+        struct cvmx_sli_window_ctl_s cn68xxp1;
+};
+
+#endif
diff --git a/drivers/staging/octeon/cvmx-spi.h b/arch/mips/include/asm/octeon/cvmx-spi.h
index e814648953a..e814648953a 100644
--- a/drivers/staging/octeon/cvmx-spi.h
+++ b/arch/mips/include/asm/octeon/cvmx-spi.h
diff --git a/drivers/staging/octeon/cvmx-spxx-defs.h b/arch/mips/include/asm/octeon/cvmx-spxx-defs.h
index b16940e32c8..b16940e32c8 100644
--- a/drivers/staging/octeon/cvmx-spxx-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-spxx-defs.h
diff --git a/arch/mips/include/asm/octeon/cvmx-sriox-defs.h b/arch/mips/include/asm/octeon/cvmx-sriox-defs.h
new file mode 100644
index 00000000000..7be7e9ed746
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-sriox-defs.h
@@ -0,0 +1,1036 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2011 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_SRIOX_DEFS_H__
+#define __CVMX_SRIOX_DEFS_H__
+
+#define CVMX_SRIOX_ACC_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000148ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_ASMBLY_ID(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000200ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_ASMBLY_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000208ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_BELL_RESP_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000310ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000108ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_IMSG_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000508ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_IMSG_INST_HDRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000510ull) + (((offset) & 1) + ((block_id) & 3) * 0x200000ull) * 8)
+#define CVMX_SRIOX_IMSG_QOS_GRPX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000600ull) + (((offset) & 31) + ((block_id) & 3) * 0x200000ull) * 8)
+#define CVMX_SRIOX_IMSG_STATUSX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000700ull) + (((offset) & 31) + ((block_id) & 3) * 0x200000ull) * 8)
+#define CVMX_SRIOX_IMSG_VPORT_THR(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000500ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_IMSG_VPORT_THR2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000528ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_INT2_ENABLE(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003E0ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_INT2_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003E8ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_INT_ENABLE(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000110ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_INT_INFO0(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000120ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_INT_INFO1(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000128ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_INT_INFO2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000130ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_INT_INFO3(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000138ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000118ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_IP_FEATURE(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003F8ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_MAC_BUFFERS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000390ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_MAINT_OP(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000158ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_MAINT_RD_DATA(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000160ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_MCE_TX_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000240ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_MEM_OP_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000168ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_OMSG_CTRLX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000488ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
+#define CVMX_SRIOX_OMSG_DONE_COUNTSX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80004B0ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
+#define CVMX_SRIOX_OMSG_FMP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000498ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
+#define CVMX_SRIOX_OMSG_NMP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80004A0ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
+#define CVMX_SRIOX_OMSG_PORTX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000480ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
+#define CVMX_SRIOX_OMSG_SILO_THR(block_id) (CVMX_ADD_IO_SEG(0x00011800C80004F8ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_OMSG_SP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000490ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
+#define CVMX_SRIOX_PRIOX_IN_USE(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80003C0ull) + (((offset) & 3) + ((block_id) & 3) * 0x200000ull) * 8)
+#define CVMX_SRIOX_RX_BELL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000308ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_RX_BELL_SEQ(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000300ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_RX_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000380ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_S2M_TYPEX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000180ull) + (((offset) & 15) + ((block_id) & 3) * 0x200000ull) * 8)
+#define CVMX_SRIOX_SEQ(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000278ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_STATUS_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000100ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_TAG_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000178ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000150ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_TX_BELL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000280ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_TX_BELL_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000288ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_TX_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000170ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_TX_EMPHASIS(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003F0ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_TX_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000388ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_WR_DONE_COUNTS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000340ull) + ((block_id) & 3) * 0x1000000ull)
+
+union cvmx_sriox_acc_ctrl {
+        uint64_t u64;
+        struct cvmx_sriox_acc_ctrl_s {
+                uint64_t reserved_7_63:57;
+                uint64_t deny_adr2:1;
+                uint64_t deny_adr1:1;
+                uint64_t deny_adr0:1;
+                uint64_t reserved_3_3:1;
+                uint64_t deny_bar2:1;
+                uint64_t deny_bar1:1;
+                uint64_t deny_bar0:1;
+        } s;
+        struct cvmx_sriox_acc_ctrl_cn63xx {
+                uint64_t reserved_3_63:61;
+                uint64_t deny_bar2:1;
+                uint64_t deny_bar1:1;
+                uint64_t deny_bar0:1;
+        } cn63xx;
+        struct cvmx_sriox_acc_ctrl_cn63xx cn63xxp1;
+        struct cvmx_sriox_acc_ctrl_s cn66xx;
+};
+
+union cvmx_sriox_asmbly_id {
+        uint64_t u64;
+        struct cvmx_sriox_asmbly_id_s {
+                uint64_t reserved_32_63:32;
+                uint64_t assy_id:16;
+                uint64_t assy_ven:16;
+        } s;
+        struct cvmx_sriox_asmbly_id_s cn63xx;
+        struct cvmx_sriox_asmbly_id_s cn63xxp1;
+        struct cvmx_sriox_asmbly_id_s cn66xx;
+};
+
+union cvmx_sriox_asmbly_info {
+        uint64_t u64;
+        struct cvmx_sriox_asmbly_info_s {
+                uint64_t reserved_32_63:32;
+                uint64_t assy_rev:16;
+                uint64_t reserved_0_15:16;
+        } s;
+        struct cvmx_sriox_asmbly_info_s cn63xx;
+        struct cvmx_sriox_asmbly_info_s cn63xxp1;
+        struct cvmx_sriox_asmbly_info_s cn66xx;
+};
+
+union cvmx_sriox_bell_resp_ctrl {
+        uint64_t u64;
+        struct cvmx_sriox_bell_resp_ctrl_s {
+                uint64_t reserved_6_63:58;
+                uint64_t rp1_sid:1;
+                uint64_t rp0_sid:2;
+                uint64_t rp1_pid:1;
+                uint64_t rp0_pid:2;
+        } s;
+        struct cvmx_sriox_bell_resp_ctrl_s cn63xx;
+        struct cvmx_sriox_bell_resp_ctrl_s cn63xxp1;
+        struct cvmx_sriox_bell_resp_ctrl_s cn66xx;
+};
+
+union cvmx_sriox_bist_status {
+        uint64_t u64;
+        struct cvmx_sriox_bist_status_s {
+                uint64_t reserved_45_63:19;
+                uint64_t lram:1;
+                uint64_t mram:2;
+                uint64_t cram:2;
+                uint64_t bell:2;
+                uint64_t otag:2;
+                uint64_t itag:1;
+                uint64_t ofree:1;
+                uint64_t rtn:2;
+                uint64_t obulk:4;
+                uint64_t optrs:4;
+                uint64_t oarb2:2;
+                uint64_t rxbuf2:2;
+                uint64_t oarb:2;
+                uint64_t ispf:1;
+                uint64_t ospf:1;
+                uint64_t txbuf:2;
+                uint64_t rxbuf:2;
+                uint64_t imsg:5;
+                uint64_t omsg:7;
+        } s;
+        struct cvmx_sriox_bist_status_cn63xx {
+                uint64_t reserved_44_63:20;
+                uint64_t mram:2;
+                uint64_t cram:2;
+                uint64_t bell:2;
+                uint64_t otag:2;
+                uint64_t itag:1;
+                uint64_t ofree:1;
+                uint64_t rtn:2;
+                uint64_t obulk:4;
+                uint64_t optrs:4;
+                uint64_t oarb2:2;
+                uint64_t rxbuf2:2;
+                uint64_t oarb:2;
+                uint64_t ispf:1;
+                uint64_t ospf:1;
+                uint64_t txbuf:2;
+                uint64_t rxbuf:2;
+                uint64_t imsg:5;
+                uint64_t omsg:7;
+        } cn63xx;
+        struct cvmx_sriox_bist_status_cn63xxp1 {
+                uint64_t reserved_44_63:20;
+                uint64_t mram:2;
+                uint64_t cram:2;
+                uint64_t bell:2;
+                uint64_t otag:2;
+                uint64_t itag:1;
+                uint64_t ofree:1;
+                uint64_t rtn:2;
+                uint64_t obulk:4;
+                uint64_t optrs:4;
+                uint64_t reserved_20_23:4;
+                uint64_t oarb:2;
+                uint64_t ispf:1;
+                uint64_t ospf:1;
+                uint64_t txbuf:2;
+                uint64_t rxbuf:2;
+                uint64_t imsg:5;
+                uint64_t omsg:7;
+        } cn63xxp1;
+        struct cvmx_sriox_bist_status_s cn66xx;
+};
+
+union cvmx_sriox_imsg_ctrl {
+        uint64_t u64;
+        struct cvmx_sriox_imsg_ctrl_s {
+                uint64_t reserved_32_63:32;
+                uint64_t to_mode:1;
+                uint64_t reserved_30_30:1;
+                uint64_t rsp_thr:6;
+                uint64_t reserved_22_23:2;
+                uint64_t rp1_sid:1;
+                uint64_t rp0_sid:2;
+                uint64_t rp1_pid:1;
+                uint64_t rp0_pid:2;
+                uint64_t reserved_15_15:1;
+                uint64_t prt_sel:3;
+                uint64_t lttr:4;
+                uint64_t prio:4;
+                uint64_t mbox:4;
+        } s;
+        struct cvmx_sriox_imsg_ctrl_s cn63xx;
+        struct cvmx_sriox_imsg_ctrl_s cn63xxp1;
+        struct cvmx_sriox_imsg_ctrl_s cn66xx;
+};
+
+union cvmx_sriox_imsg_inst_hdrx {
+        uint64_t u64;
+        struct cvmx_sriox_imsg_inst_hdrx_s {
+                uint64_t r:1;
+                uint64_t reserved_58_62:5;
+                uint64_t pm:2;
+                uint64_t reserved_55_55:1;
+                uint64_t sl:7;
+                uint64_t reserved_46_47:2;
+                uint64_t nqos:1;
+                uint64_t ngrp:1;
+                uint64_t ntt:1;
+                uint64_t ntag:1;
+                uint64_t reserved_35_41:7;
+                uint64_t rs:1;
+                uint64_t tt:2;
+                uint64_t tag:32;
+        } s;
+        struct cvmx_sriox_imsg_inst_hdrx_s cn63xx;
+        struct cvmx_sriox_imsg_inst_hdrx_s cn63xxp1;
+        struct cvmx_sriox_imsg_inst_hdrx_s cn66xx;
+};
+
+union cvmx_sriox_imsg_qos_grpx {
+        uint64_t u64;
+        struct cvmx_sriox_imsg_qos_grpx_s {
+                uint64_t reserved_63_63:1;
+                uint64_t qos7:3;
+                uint64_t grp7:4;
+                uint64_t reserved_55_55:1;
+                uint64_t qos6:3;
+                uint64_t grp6:4;
+                uint64_t reserved_47_47:1;
+                uint64_t qos5:3;
+                uint64_t grp5:4;
+                uint64_t reserved_39_39:1;
+                uint64_t qos4:3;
+                uint64_t grp4:4;
+                uint64_t reserved_31_31:1;
+                uint64_t qos3:3;
+                uint64_t grp3:4;
+                uint64_t reserved_23_23:1;
+                uint64_t qos2:3;
+                uint64_t grp2:4;
+                uint64_t reserved_15_15:1;
+                uint64_t qos1:3;
+                uint64_t grp1:4;
+                uint64_t reserved_7_7:1;
+                uint64_t qos0:3;
+                uint64_t grp0:4;
+        } s;
+        struct cvmx_sriox_imsg_qos_grpx_s cn63xx;
+        struct cvmx_sriox_imsg_qos_grpx_s cn63xxp1;
+        struct cvmx_sriox_imsg_qos_grpx_s cn66xx;
+};
+
+union cvmx_sriox_imsg_statusx {
+        uint64_t u64;
+        struct cvmx_sriox_imsg_statusx_s {
+                uint64_t val1:1;
+                uint64_t err1:1;
+                uint64_t toe1:1;
+                uint64_t toc1:1;
+                uint64_t prt1:1;
+                uint64_t reserved_58_58:1;
+                uint64_t tt1:1;
+                uint64_t dis1:1;
+                uint64_t seg1:4;
+                uint64_t mbox1:2;
+                uint64_t lttr1:2;
+                uint64_t sid1:16;
+                uint64_t val0:1;
+                uint64_t err0:1;
+                uint64_t toe0:1;
+                uint64_t toc0:1;
+                uint64_t prt0:1;
+                uint64_t reserved_26_26:1;
+                uint64_t tt0:1;
+                uint64_t dis0:1;
+                uint64_t seg0:4;
+                uint64_t mbox0:2;
+                uint64_t lttr0:2;
+                uint64_t sid0:16;
+        } s;
+        struct cvmx_sriox_imsg_statusx_s cn63xx;
+        struct cvmx_sriox_imsg_statusx_s cn63xxp1;
+        struct cvmx_sriox_imsg_statusx_s cn66xx;
+};
+
+union cvmx_sriox_imsg_vport_thr {
+        uint64_t u64;
+        struct cvmx_sriox_imsg_vport_thr_s {
+                uint64_t reserved_54_63:10;
+                uint64_t max_tot:6;
+                uint64_t reserved_46_47:2;
+                uint64_t max_s1:6;
+                uint64_t reserved_38_39:2;
+                uint64_t max_s0:6;
+                uint64_t sp_vport:1;
+                uint64_t reserved_20_30:11;
+                uint64_t buf_thr:4;
+                uint64_t reserved_14_15:2;
+                uint64_t max_p1:6;
+                uint64_t reserved_6_7:2;
+                uint64_t max_p0:6;
+        } s;
+        struct cvmx_sriox_imsg_vport_thr_s cn63xx;
+        struct cvmx_sriox_imsg_vport_thr_s cn63xxp1;
+        struct cvmx_sriox_imsg_vport_thr_s cn66xx;
+};
+
+union cvmx_sriox_imsg_vport_thr2 {
+        uint64_t u64;
+        struct cvmx_sriox_imsg_vport_thr2_s {
+                uint64_t reserved_46_63:18;
+                uint64_t max_s3:6;
+                uint64_t reserved_38_39:2;
+                uint64_t max_s2:6;
+                uint64_t reserved_0_31:32;
+        } s;
+        struct cvmx_sriox_imsg_vport_thr2_s cn66xx;
+};
+
+union cvmx_sriox_int2_enable {
+        uint64_t u64;
+        struct cvmx_sriox_int2_enable_s {
+                uint64_t reserved_1_63:63;
+                uint64_t pko_rst:1;
+        } s;
+        struct cvmx_sriox_int2_enable_s cn63xx;
+        struct cvmx_sriox_int2_enable_s cn66xx;
+};
+
+union cvmx_sriox_int2_reg {
+        uint64_t u64;
+        struct cvmx_sriox_int2_reg_s {
+                uint64_t reserved_32_63:32;
+                uint64_t int_sum:1;
+                uint64_t reserved_1_30:30;
+                uint64_t pko_rst:1;
+        } s;
+        struct cvmx_sriox_int2_reg_s cn63xx;
+        struct cvmx_sriox_int2_reg_s cn66xx;
+};
+
+union cvmx_sriox_int_enable {
+        uint64_t u64;
+        struct cvmx_sriox_int_enable_s {
+                uint64_t reserved_27_63:37;
+                uint64_t zero_pkt:1;
+                uint64_t ttl_tout:1;
+                uint64_t fail:1;
+                uint64_t degrade:1;
+                uint64_t mac_buf:1;
+                uint64_t f_error:1;
+                uint64_t rtry_err:1;
+                uint64_t pko_err:1;
+                uint64_t omsg_err:1;
+                uint64_t omsg1:1;
+                uint64_t omsg0:1;
+                uint64_t link_up:1;
+                uint64_t link_dwn:1;
+                uint64_t phy_erb:1;
+                uint64_t log_erb:1;
+                uint64_t soft_rx:1;
+                uint64_t soft_tx:1;
+                uint64_t mce_rx:1;
+                uint64_t mce_tx:1;
+                uint64_t wr_done:1;
+                uint64_t sli_err:1;
+                uint64_t deny_wr:1;
+                uint64_t bar_err:1;
+                uint64_t maint_op:1;
+                uint64_t rxbell:1;
+                uint64_t bell_err:1;
+                uint64_t txbell:1;
+        } s;
+        struct cvmx_sriox_int_enable_s cn63xx;
+        struct cvmx_sriox_int_enable_cn63xxp1 {
+                uint64_t reserved_22_63:42;
+                uint64_t f_error:1;
+                uint64_t rtry_err:1;
+                uint64_t pko_err:1;
+                uint64_t omsg_err:1;
+                uint64_t omsg1:1;
+                uint64_t omsg0:1;
+                uint64_t link_up:1;
+                uint64_t link_dwn:1;
+                uint64_t phy_erb:1;
+                uint64_t log_erb:1;
+                uint64_t soft_rx:1;
+                uint64_t soft_tx:1;
+                uint64_t mce_rx:1;
+                uint64_t mce_tx:1;
+                uint64_t wr_done:1;
+                uint64_t sli_err:1;
+                uint64_t deny_wr:1;
+                uint64_t bar_err:1;
+                uint64_t maint_op:1;
+                uint64_t rxbell:1;
+                uint64_t bell_err:1;
+                uint64_t txbell:1;
+        } cn63xxp1;
+        struct cvmx_sriox_int_enable_s cn66xx;
+};
+
+union cvmx_sriox_int_info0 {
+        uint64_t u64;
+        struct cvmx_sriox_int_info0_s {
+                uint64_t cmd:4;
+                uint64_t type:4;
+                uint64_t tag:8;
+                uint64_t reserved_42_47:6;
+                uint64_t length:10;
+                uint64_t status:3;
+                uint64_t reserved_16_28:13;
+                uint64_t be0:8;
+                uint64_t be1:8;
+        } s;
+        struct cvmx_sriox_int_info0_s cn63xx;
+        struct cvmx_sriox_int_info0_s cn63xxp1;
+        struct cvmx_sriox_int_info0_s cn66xx;
+};
+
+union cvmx_sriox_int_info1 {
+        uint64_t u64;
+        struct cvmx_sriox_int_info1_s {
+                uint64_t info1:64;
+        } s;
+        struct cvmx_sriox_int_info1_s cn63xx;
+        struct cvmx_sriox_int_info1_s cn63xxp1;
+        struct cvmx_sriox_int_info1_s cn66xx;
+};
+
+union cvmx_sriox_int_info2 {
+        uint64_t u64;
+        struct cvmx_sriox_int_info2_s {
+                uint64_t prio:2;
+                uint64_t tt:1;
+                uint64_t sis:1;
+                uint64_t ssize:4;
+                uint64_t did:16;
+                uint64_t xmbox:4;
+                uint64_t mbox:2;
+                uint64_t letter:2;
+                uint64_t rsrvd:30;
+                uint64_t lns:1;
+                uint64_t intr:1;
+        } s;
+        struct cvmx_sriox_int_info2_s cn63xx;
+        struct cvmx_sriox_int_info2_s cn63xxp1;
+        struct cvmx_sriox_int_info2_s cn66xx;
+};
+
+union cvmx_sriox_int_info3 {
+        uint64_t u64;
+        struct cvmx_sriox_int_info3_s {
+                uint64_t prio:2;
+                uint64_t tt:2;
+                uint64_t type:4;
+                uint64_t other:48;
+                uint64_t reserved_0_7:8;
+        } s;
+        struct cvmx_sriox_int_info3_s cn63xx;
+        struct cvmx_sriox_int_info3_s cn63xxp1;
+        struct cvmx_sriox_int_info3_s cn66xx;
+};
+
+union cvmx_sriox_int_reg {
+        uint64_t u64;
+        struct cvmx_sriox_int_reg_s {
+                uint64_t reserved_32_63:32;
+                uint64_t int2_sum:1;
+                uint64_t reserved_27_30:4;
+                uint64_t zero_pkt:1;
+                uint64_t ttl_tout:1;
+                uint64_t fail:1;
+                uint64_t degrad:1;
+                uint64_t mac_buf:1;
+                uint64_t f_error:1;
+                uint64_t rtry_err:1;
+                uint64_t pko_err:1;
+                uint64_t omsg_err:1;
+                uint64_t omsg1:1;
+                uint64_t omsg0:1;
+                uint64_t link_up:1;
+                uint64_t link_dwn:1;
+                uint64_t phy_erb:1;
+                uint64_t log_erb:1;
+                uint64_t soft_rx:1;
+                uint64_t soft_tx:1;
+                uint64_t mce_rx:1;
+                uint64_t mce_tx:1;
+                uint64_t wr_done:1;
+                uint64_t sli_err:1;
+                uint64_t deny_wr:1;
+                uint64_t bar_err:1;
+                uint64_t maint_op:1;
+                uint64_t rxbell:1;
+                uint64_t bell_err:1;
+                uint64_t txbell:1;
+        } s;
+        struct cvmx_sriox_int_reg_s cn63xx;
+        struct cvmx_sriox_int_reg_cn63xxp1 {
+                uint64_t reserved_22_63:42;
+                uint64_t f_error:1;
+                uint64_t rtry_err:1;
+                uint64_t pko_err:1;
+                uint64_t omsg_err:1;
+                uint64_t omsg1:1;
+                uint64_t omsg0:1;
+                uint64_t link_up:1;
+                uint64_t link_dwn:1;
+                uint64_t phy_erb:1;
+                uint64_t log_erb:1;
+                uint64_t soft_rx:1;
+                uint64_t soft_tx:1;
+                uint64_t mce_rx:1;
+                uint64_t mce_tx:1;
+                uint64_t wr_done:1;
+                uint64_t sli_err:1;
+                uint64_t deny_wr:1;
+                uint64_t bar_err:1;
+                uint64_t maint_op:1;
+                uint64_t rxbell:1;
+                uint64_t bell_err:1;
+                uint64_t txbell:1;
+        } cn63xxp1;
+        struct cvmx_sriox_int_reg_s cn66xx;
+};
+
+union cvmx_sriox_ip_feature {
+        uint64_t u64;
+        struct cvmx_sriox_ip_feature_s {
+                uint64_t ops:32;
+                uint64_t reserved_15_31:17;
+                uint64_t no_vmin:1;
+                uint64_t a66:1;
+                uint64_t a50:1;
+                uint64_t reserved_11_11:1;
+                uint64_t tx_flow:1;
+                uint64_t pt_width:2;
+                uint64_t tx_pol:4;
+                uint64_t rx_pol:4;
+        } s;
+        struct cvmx_sriox_ip_feature_cn63xx {
+                uint64_t ops:32;
+                uint64_t reserved_14_31:18;
+                uint64_t a66:1;
+                uint64_t a50:1;
+                uint64_t reserved_11_11:1;
+                uint64_t tx_flow:1;
+                uint64_t pt_width:2;
+                uint64_t tx_pol:4;
+                uint64_t rx_pol:4;
+        } cn63xx;
+        struct cvmx_sriox_ip_feature_cn63xx cn63xxp1;
+        struct cvmx_sriox_ip_feature_s cn66xx;
+};
+
+union cvmx_sriox_mac_buffers {
+        uint64_t u64;
+        struct cvmx_sriox_mac_buffers_s {
+                uint64_t reserved_56_63:8;
+                uint64_t tx_enb:8;
+                uint64_t reserved_44_47:4;
+                uint64_t tx_inuse:4;
+                uint64_t tx_stat:8;
+                uint64_t reserved_24_31:8;
+                uint64_t rx_enb:8;
+                uint64_t reserved_12_15:4;
+                uint64_t rx_inuse:4;
+                uint64_t rx_stat:8;
+        } s;
+        struct cvmx_sriox_mac_buffers_s cn63xx;
+        struct cvmx_sriox_mac_buffers_s cn66xx;
+};
+
+union cvmx_sriox_maint_op {
+        uint64_t u64;
+        struct cvmx_sriox_maint_op_s {
+                uint64_t wr_data:32;
+                uint64_t reserved_27_31:5;
+                uint64_t fail:1;
+                uint64_t pending:1;
+                uint64_t op:1;
+                uint64_t addr:24;
+        } s;
+        struct cvmx_sriox_maint_op_s cn63xx;
+        struct cvmx_sriox_maint_op_s cn63xxp1;
+        struct cvmx_sriox_maint_op_s cn66xx;
+};
+
+union cvmx_sriox_maint_rd_data {
+        uint64_t u64;
+        struct cvmx_sriox_maint_rd_data_s {
+                uint64_t reserved_33_63:31;
+                uint64_t valid:1;
+                uint64_t rd_data:32;
+        } s;
+        struct cvmx_sriox_maint_rd_data_s cn63xx;
+        struct cvmx_sriox_maint_rd_data_s cn63xxp1;
+        struct cvmx_sriox_maint_rd_data_s cn66xx;
+};
+
+union cvmx_sriox_mce_tx_ctl {
+        uint64_t u64;
+        struct cvmx_sriox_mce_tx_ctl_s {
+                uint64_t reserved_1_63:63;
+                uint64_t mce:1;
+        } s;
+        struct cvmx_sriox_mce_tx_ctl_s cn63xx;
+        struct cvmx_sriox_mce_tx_ctl_s cn63xxp1;
+        struct cvmx_sriox_mce_tx_ctl_s cn66xx;
+};
+
+union cvmx_sriox_mem_op_ctrl {
+        uint64_t u64;
+        struct cvmx_sriox_mem_op_ctrl_s {
+                uint64_t reserved_10_63:54;
+                uint64_t rr_ro:1;
+                uint64_t w_ro:1;
+                uint64_t reserved_6_7:2;
+                uint64_t rp1_sid:1;
+                uint64_t rp0_sid:2;
+                uint64_t rp1_pid:1;
+                uint64_t rp0_pid:2;
+        } s;
+        struct cvmx_sriox_mem_op_ctrl_s cn63xx;
+        struct cvmx_sriox_mem_op_ctrl_s cn63xxp1;
+        struct cvmx_sriox_mem_op_ctrl_s cn66xx;
+};
+
+union cvmx_sriox_omsg_ctrlx {
+        uint64_t u64;
+        struct cvmx_sriox_omsg_ctrlx_s {
+                uint64_t testmode:1;
+                uint64_t reserved_37_62:26;
+                uint64_t silo_max:5;
+                uint64_t rtry_thr:16;
+                uint64_t rtry_en:1;
+                uint64_t reserved_11_14:4;
+                uint64_t idm_tt:1;
+                uint64_t idm_sis:1;
+                uint64_t idm_did:1;
+                uint64_t lttr_sp:4;
+                uint64_t lttr_mp:4;
+        } s;
+        struct cvmx_sriox_omsg_ctrlx_s cn63xx;
+        struct cvmx_sriox_omsg_ctrlx_cn63xxp1 {
+                uint64_t testmode:1;
+                uint64_t reserved_32_62:31;
+                uint64_t rtry_thr:16;
+                uint64_t rtry_en:1;
+                uint64_t reserved_11_14:4;
+                uint64_t idm_tt:1;
+                uint64_t idm_sis:1;
+                uint64_t idm_did:1;
+                uint64_t lttr_sp:4;
+                uint64_t lttr_mp:4;
+        } cn63xxp1;
+        struct cvmx_sriox_omsg_ctrlx_s cn66xx;
+};
+
+union cvmx_sriox_omsg_done_countsx {
+        uint64_t u64;
+        struct cvmx_sriox_omsg_done_countsx_s {
+                uint64_t reserved_32_63:32;
+                uint64_t bad:16;
+                uint64_t good:16;
+        } s;
+        struct cvmx_sriox_omsg_done_countsx_s cn63xx;
+        struct cvmx_sriox_omsg_done_countsx_s cn66xx;
+};
+
+union cvmx_sriox_omsg_fmp_mrx {
+        uint64_t u64;
+        struct cvmx_sriox_omsg_fmp_mrx_s {
+                uint64_t reserved_15_63:49;
+                uint64_t ctlr_sp:1;
+                uint64_t ctlr_fmp:1;
+                uint64_t ctlr_nmp:1;
+                uint64_t id_sp:1;
+                uint64_t id_fmp:1;
+                uint64_t id_nmp:1;
+                uint64_t id_psd:1;
+                uint64_t mbox_sp:1;
+                uint64_t mbox_fmp:1;
+                uint64_t mbox_nmp:1;
+                uint64_t mbox_psd:1;
+                uint64_t all_sp:1;
+                uint64_t all_fmp:1;
+                uint64_t all_nmp:1;
+                uint64_t all_psd:1;
+        } s;
+        struct cvmx_sriox_omsg_fmp_mrx_s cn63xx;
+        struct cvmx_sriox_omsg_fmp_mrx_s cn63xxp1;
+        struct cvmx_sriox_omsg_fmp_mrx_s cn66xx;
+};
+
+union cvmx_sriox_omsg_nmp_mrx {
+        uint64_t u64;
+        struct cvmx_sriox_omsg_nmp_mrx_s {
+                uint64_t reserved_15_63:49;
+                uint64_t ctlr_sp:1;
+                uint64_t ctlr_fmp:1;
+                uint64_t ctlr_nmp:1;
+                uint64_t id_sp:1;
+                uint64_t id_fmp:1;
+                uint64_t id_nmp:1;
+                uint64_t reserved_8_8:1;
+                uint64_t mbox_sp:1;
+                uint64_t mbox_fmp:1;
+                uint64_t mbox_nmp:1;
+                uint64_t reserved_4_4:1;
+                uint64_t all_sp:1;
+                uint64_t all_fmp:1;
+                uint64_t all_nmp:1;
+                uint64_t reserved_0_0:1;
+        } s;
+        struct cvmx_sriox_omsg_nmp_mrx_s cn63xx;
+        struct cvmx_sriox_omsg_nmp_mrx_s cn63xxp1;
+        struct cvmx_sriox_omsg_nmp_mrx_s cn66xx;
+};
+
+union cvmx_sriox_omsg_portx {
+        uint64_t u64;
+        struct cvmx_sriox_omsg_portx_s {
+                uint64_t reserved_32_63:32;
+                uint64_t enable:1;
+                uint64_t reserved_3_30:28;
+                uint64_t port:3;
+        } s;
+        struct cvmx_sriox_omsg_portx_cn63xx {
+                uint64_t reserved_32_63:32;
+                uint64_t enable:1;
+                uint64_t reserved_2_30:29;
+                uint64_t port:2;
+        } cn63xx;
+        struct cvmx_sriox_omsg_portx_cn63xx cn63xxp1;
+        struct cvmx_sriox_omsg_portx_s cn66xx;
+};
+
+union cvmx_sriox_omsg_silo_thr {
+        uint64_t u64;
+        struct cvmx_sriox_omsg_silo_thr_s {
+                uint64_t reserved_5_63:59;
+                uint64_t tot_silo:5;
+        } s;
+        struct cvmx_sriox_omsg_silo_thr_s cn63xx;
+        struct cvmx_sriox_omsg_silo_thr_s cn66xx;
+};
+
+union cvmx_sriox_omsg_sp_mrx {
+        uint64_t u64;
+        struct cvmx_sriox_omsg_sp_mrx_s {
+                uint64_t reserved_16_63:48;
+                uint64_t xmbox_sp:1;
+                uint64_t ctlr_sp:1;
+                uint64_t ctlr_fmp:1;
+                uint64_t ctlr_nmp:1;
+                uint64_t id_sp:1;
+                uint64_t id_fmp:1;
+                uint64_t id_nmp:1;
+                uint64_t id_psd:1;
+                uint64_t mbox_sp:1;
+                uint64_t mbox_fmp:1;
+                uint64_t mbox_nmp:1;
+                uint64_t mbox_psd:1;
+                uint64_t all_sp:1;
+                uint64_t all_fmp:1;
+                uint64_t all_nmp:1;
+                uint64_t all_psd:1;
+        } s;
+        struct cvmx_sriox_omsg_sp_mrx_s cn63xx;
+        struct cvmx_sriox_omsg_sp_mrx_s cn63xxp1;
+        struct cvmx_sriox_omsg_sp_mrx_s cn66xx;
+};
+
+union cvmx_sriox_priox_in_use {
+        uint64_t u64;
+        struct cvmx_sriox_priox_in_use_s {
+                uint64_t reserved_32_63:32;
+                uint64_t end_cnt:16;
+                uint64_t start_cnt:16;
+        } s;
+        struct cvmx_sriox_priox_in_use_s cn63xx;
+        struct cvmx_sriox_priox_in_use_s cn66xx;
+};
+
+union cvmx_sriox_rx_bell {
+        uint64_t u64;
+        struct cvmx_sriox_rx_bell_s {
+                uint64_t reserved_48_63:16;
+                uint64_t data:16;
+                uint64_t src_id:16;
+                uint64_t count:8;
+                uint64_t reserved_5_7:3;
+                uint64_t dest_id:1;
+                uint64_t id16:1;
+                uint64_t reserved_2_2:1;
+                uint64_t priority:2;
+        } s;
+        struct cvmx_sriox_rx_bell_s cn63xx;
+        struct cvmx_sriox_rx_bell_s cn63xxp1;
+        struct cvmx_sriox_rx_bell_s cn66xx;
+};
+
+union cvmx_sriox_rx_bell_seq {
+        uint64_t u64;
+        struct cvmx_sriox_rx_bell_seq_s {
+                uint64_t reserved_40_63:24;
+                uint64_t count:8;
+                uint64_t seq:32;
+        } s;
+        struct cvmx_sriox_rx_bell_seq_s cn63xx;
+        struct cvmx_sriox_rx_bell_seq_s cn63xxp1;
+        struct cvmx_sriox_rx_bell_seq_s cn66xx;
+};
+
+union cvmx_sriox_rx_status {
+        uint64_t u64;
+        struct cvmx_sriox_rx_status_s {
+                uint64_t rtn_pr3:8;
+                uint64_t rtn_pr2:8;
+                uint64_t rtn_pr1:8;
+                uint64_t reserved_28_39:12;
+                uint64_t mbox:4;
+                uint64_t comp:8;
+                uint64_t reserved_13_15:3;
+                uint64_t n_post:5;
+                uint64_t post:8;
+        } s;
+        struct cvmx_sriox_rx_status_s cn63xx;
+        struct cvmx_sriox_rx_status_s cn63xxp1;
+        struct cvmx_sriox_rx_status_s cn66xx;
+};
+
+union cvmx_sriox_s2m_typex {
+        uint64_t u64;
+        struct cvmx_sriox_s2m_typex_s {
+                uint64_t reserved_19_63:45;
+                uint64_t wr_op:3;
+                uint64_t reserved_15_15:1;
+                uint64_t rd_op:3;
+                uint64_t wr_prior:2;
+                uint64_t rd_prior:2;
+                uint64_t reserved_6_7:2;
+                uint64_t src_id:1;
+                uint64_t id16:1;
+                uint64_t reserved_2_3:2;
+                uint64_t iaow_sel:2;
+        } s;
+        struct cvmx_sriox_s2m_typex_s cn63xx;
+        struct cvmx_sriox_s2m_typex_s cn63xxp1;
+        struct cvmx_sriox_s2m_typex_s cn66xx;
+};
+
+union cvmx_sriox_seq {
+        uint64_t u64;
+        struct cvmx_sriox_seq_s {
+                uint64_t reserved_32_63:32;
+                uint64_t seq:32;
+        } s;
+        struct cvmx_sriox_seq_s cn63xx;
+        struct cvmx_sriox_seq_s cn63xxp1;
+        struct cvmx_sriox_seq_s cn66xx;
+};
+
+union cvmx_sriox_status_reg {
+        uint64_t u64;
+        struct cvmx_sriox_status_reg_s {
+                uint64_t reserved_2_63:62;
+                uint64_t access:1;
+                uint64_t srio:1;
+        } s;
+        struct cvmx_sriox_status_reg_s cn63xx;
+        struct cvmx_sriox_status_reg_s cn63xxp1;
+        struct cvmx_sriox_status_reg_s cn66xx;
+};
+
+union cvmx_sriox_tag_ctrl {
+        uint64_t u64;
+        struct cvmx_sriox_tag_ctrl_s {
+                uint64_t reserved_17_63:47;
+                uint64_t o_clr:1;
+                uint64_t reserved_13_15:3;
+                uint64_t otag:5;
+                uint64_t reserved_5_7:3;
+                uint64_t itag:5;
+        } s;
+        struct cvmx_sriox_tag_ctrl_s cn63xx;
+        struct cvmx_sriox_tag_ctrl_s cn63xxp1;
+        struct cvmx_sriox_tag_ctrl_s cn66xx;
+};
+
+union cvmx_sriox_tlp_credits {
+        uint64_t u64;
+        struct cvmx_sriox_tlp_credits_s {
+                uint64_t reserved_28_63:36;
+                uint64_t mbox:4;
+                uint64_t comp:8;
+                uint64_t reserved_13_15:3;
+                uint64_t n_post:5;
+                uint64_t post:8;
+        } s;
+        struct cvmx_sriox_tlp_credits_s cn63xx;
+        struct cvmx_sriox_tlp_credits_s cn63xxp1;
+        struct cvmx_sriox_tlp_credits_s cn66xx;
+};
+
+union cvmx_sriox_tx_bell {
+        uint64_t u64;
+        struct cvmx_sriox_tx_bell_s {
+                uint64_t reserved_48_63:16;
+                uint64_t data:16;
+                uint64_t dest_id:16;
+                uint64_t reserved_9_15:7;
+                uint64_t pending:1;
+                uint64_t reserved_5_7:3;
+                uint64_t src_id:1;
+                uint64_t id16:1;
+                uint64_t reserved_2_2:1;
+                uint64_t priority:2;
+        } s;
+        struct cvmx_sriox_tx_bell_s cn63xx;
+        struct cvmx_sriox_tx_bell_s cn63xxp1;
+        struct cvmx_sriox_tx_bell_s cn66xx;
+};
+
+union cvmx_sriox_tx_bell_info {
+        uint64_t u64;
+        struct cvmx_sriox_tx_bell_info_s {
+                uint64_t reserved_48_63:16;
+                uint64_t data:16;
+                uint64_t dest_id:16;
+                uint64_t reserved_8_15:8;
+                uint64_t timeout:1;
+                uint64_t error:1;
+                uint64_t retry:1;
+                uint64_t src_id:1;
+                uint64_t id16:1;
+                uint64_t reserved_2_2:1;
+                uint64_t priority:2;
+        } s;
+        struct cvmx_sriox_tx_bell_info_s cn63xx;
+        struct cvmx_sriox_tx_bell_info_s cn63xxp1;
+        struct cvmx_sriox_tx_bell_info_s cn66xx;
+};
+
+union cvmx_sriox_tx_ctrl {
+        uint64_t u64;
+        struct cvmx_sriox_tx_ctrl_s {
+                uint64_t reserved_53_63:11;
+                uint64_t tag_th2:5;
+                uint64_t reserved_45_47:3;
+                uint64_t tag_th1:5;
+                uint64_t reserved_37_39:3;
+                uint64_t tag_th0:5;
+                uint64_t reserved_20_31:12;
+                uint64_t tx_th2:4;
+                uint64_t reserved_12_15:4;
+                uint64_t tx_th1:4;
+                uint64_t reserved_4_7:4;
+                uint64_t tx_th0:4;
+        } s;
+        struct cvmx_sriox_tx_ctrl_s cn63xx;
+        struct cvmx_sriox_tx_ctrl_s cn63xxp1;
+        struct cvmx_sriox_tx_ctrl_s cn66xx;
+};
+
+union cvmx_sriox_tx_emphasis {
+        uint64_t u64;
+        struct cvmx_sriox_tx_emphasis_s {
+                uint64_t reserved_4_63:60;
+                uint64_t emph:4;
+        } s;
+        struct cvmx_sriox_tx_emphasis_s cn63xx;
+        struct cvmx_sriox_tx_emphasis_s cn66xx;
+};
+
+union cvmx_sriox_tx_status {
+        uint64_t u64;
+        struct cvmx_sriox_tx_status_s {
+                uint64_t reserved_32_63:32;
+                uint64_t s2m_pr3:8;
+                uint64_t s2m_pr2:8;
+                uint64_t s2m_pr1:8;
+                uint64_t s2m_pr0:8;
+        } s;
+        struct cvmx_sriox_tx_status_s cn63xx;
+        struct cvmx_sriox_tx_status_s cn63xxp1;
+        struct cvmx_sriox_tx_status_s cn66xx;
+};
+
+union cvmx_sriox_wr_done_counts {
+        uint64_t u64;
+        struct cvmx_sriox_wr_done_counts_s {
+                uint64_t reserved_32_63:32;
+                uint64_t bad:16;
+                uint64_t good:16;
+        } s;
+        struct cvmx_sriox_wr_done_counts_s cn63xx;
+        struct cvmx_sriox_wr_done_counts_s cn66xx;
+};
+
+#endif
diff --git a/drivers/staging/octeon/cvmx-srxx-defs.h b/arch/mips/include/asm/octeon/cvmx-srxx-defs.h
index d82b366c279..d82b366c279 100644
--- a/drivers/staging/octeon/cvmx-srxx-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-srxx-defs.h
diff --git a/drivers/staging/octeon/cvmx-stxx-defs.h b/arch/mips/include/asm/octeon/cvmx-stxx-defs.h
index 4f209b62cae..4f209b62cae 100644
--- a/drivers/staging/octeon/cvmx-stxx-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-stxx-defs.h
diff --git a/drivers/staging/octeon/cvmx-wqe.h b/arch/mips/include/asm/octeon/cvmx-wqe.h
index 653610953d2..653610953d2 100644
--- a/drivers/staging/octeon/cvmx-wqe.h
+++ b/arch/mips/include/asm/octeon/cvmx-wqe.h
diff --git a/arch/mips/include/asm/octeon/cvmx.h b/arch/mips/include/asm/octeon/cvmx.h
index 7e1286706d4..740be97a325 100644
--- a/arch/mips/include/asm/octeon/cvmx.h
+++ b/arch/mips/include/asm/octeon/cvmx.h
@@ -31,6 +31,27 @@
 #include <linux/kernel.h>
 #include <linux/string.h>
 
+enum cvmx_mips_space {
+        CVMX_MIPS_SPACE_XKSEG = 3LL,
+        CVMX_MIPS_SPACE_XKPHYS = 2LL,
+        CVMX_MIPS_SPACE_XSSEG = 1LL,
+        CVMX_MIPS_SPACE_XUSEG = 0LL
+};
+
+/* These macros for use when using 32 bit pointers. */
+#define CVMX_MIPS32_SPACE_KSEG0 1l
+#define CVMX_ADD_SEG32(segment, add) \
+        (((int32_t)segment << 31) | (int32_t)(add))
+
+#define CVMX_IO_SEG CVMX_MIPS_SPACE_XKPHYS
+
+/* These macros simplify the process of creating common IO addresses */
+#define CVMX_ADD_SEG(segment, add) \
+        ((((uint64_t)segment) << 62) | (add))
+#ifndef CVMX_ADD_IO_SEG
+#define CVMX_ADD_IO_SEG(add) CVMX_ADD_SEG(CVMX_IO_SEG, (add))
+#endif
+
 #include "cvmx-asm.h"
 #include "cvmx-packet.h"
 #include "cvmx-sysinfo.h"
@@ -129,27 +150,6 @@ static inline uint64_t cvmx_build_bits(uint64_t high_bit,
         return (value & cvmx_build_mask(high_bit - low_bit + 1)) << low_bit;
 }
 
-enum cvmx_mips_space {
-        CVMX_MIPS_SPACE_XKSEG = 3LL,
-        CVMX_MIPS_SPACE_XKPHYS = 2LL,
-        CVMX_MIPS_SPACE_XSSEG = 1LL,
-        CVMX_MIPS_SPACE_XUSEG = 0LL
-};
-
-/* These macros for use when using 32 bit pointers. */
-#define CVMX_MIPS32_SPACE_KSEG0 1l
-#define CVMX_ADD_SEG32(segment, add) \
-        (((int32_t)segment << 31) | (int32_t)(add))
-
-#define CVMX_IO_SEG CVMX_MIPS_SPACE_XKPHYS
-
-/* These macros simplify the process of creating common IO addresses */
-#define CVMX_ADD_SEG(segment, add) \
-        ((((uint64_t)segment) << 62) | (add))
-#ifndef CVMX_ADD_IO_SEG
-#define CVMX_ADD_IO_SEG(add) CVMX_ADD_SEG(CVMX_IO_SEG, (add))
-#endif
-
 /**
  * Convert a memory pointer (void*) into a hardware compatible
  * memory address (uint64_t). Octeon hardware widgets don't
diff --git a/arch/mips/include/asm/octeon/octeon-feature.h b/arch/mips/include/asm/octeon/octeon-feature.h
index cba6fbed9f4..8008da2f877 100644
--- a/arch/mips/include/asm/octeon/octeon-feature.h
+++ b/arch/mips/include/asm/octeon/octeon-feature.h
@@ -31,8 +31,14 @@
 
 #ifndef __OCTEON_FEATURE_H__
 #define __OCTEON_FEATURE_H__
+#include <asm/octeon/cvmx-mio-defs.h>
+#include <asm/octeon/cvmx-rnm-defs.h>
 
 enum octeon_feature {
+        /* CN68XX uses port kinds for packet interface */
+        OCTEON_FEATURE_PKND,
+        /* CN68XX has different fields in word0 - word2 */
+        OCTEON_FEATURE_CN68XX_WQE,
         /*
          * Octeon models in the CN5XXX family and higher support
          * atomic add instructions to memory (saa/saad).
@@ -42,8 +48,13 @@ enum octeon_feature {
         OCTEON_FEATURE_ZIP,
         /* Does this Octeon support crypto acceleration using COP2? */
         OCTEON_FEATURE_CRYPTO,
+        OCTEON_FEATURE_DORM_CRYPTO,
         /* Does this Octeon support PCI express? */
         OCTEON_FEATURE_PCIE,
+        /* Does this Octeon support SRIOs */
+        OCTEON_FEATURE_SRIO,
+        /*  Does this Octeon support Interlaken */
+        OCTEON_FEATURE_ILK,
         /* Some Octeon models support internal memory for storing
          * cryptographic keys */
         OCTEON_FEATURE_KEY_MEMORY,
@@ -64,6 +75,15 @@ enum octeon_feature {
         /* Octeon MDIO block supports clause 45 transactions for 10
          * Gig support */
         OCTEON_FEATURE_MDIO_CLAUSE_45,
+        /*
+         *  CN52XX and CN56XX used a block named NPEI for PCIe
+         *  access. Newer chips replaced this with SLI+DPI.
+         */
+        OCTEON_FEATURE_NPEI,
+        OCTEON_FEATURE_HFA,
+        OCTEON_FEATURE_DFM,
+        OCTEON_FEATURE_CIU2,
+        OCTEON_MAX_FEATURE
 };
 
 static inline int cvmx_fuse_read(int fuse);
@@ -96,30 +116,78 @@ static inline int octeon_has_feature(enum octeon_feature feature)
                         return !cvmx_fuse_read(121);
 
         case OCTEON_FEATURE_CRYPTO:
-                return !cvmx_fuse_read(90);
+                if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
+                        union cvmx_mio_fus_dat2 fus_2;
+                        fus_2.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT2);
+                        if (fus_2.s.nocrypto || fus_2.s.nomul) {
+                                return 0;
+                        } else if (!fus_2.s.dorm_crypto) {
+                                return 1;
+                        } else {
+                                union cvmx_rnm_ctl_status st;
+                                st.u64 = cvmx_read_csr(CVMX_RNM_CTL_STATUS);
+                                return st.s.eer_val;
+                        }
+                } else {
+                        return !cvmx_fuse_read(90);
+                }
+
+        case OCTEON_FEATURE_DORM_CRYPTO:
+                if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
+                        union cvmx_mio_fus_dat2 fus_2;
+                        fus_2.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT2);
+                        return !fus_2.s.nocrypto && !fus_2.s.nomul && fus_2.s.dorm_crypto;
+                } else {
+                        return 0;
+                }
 
         case OCTEON_FEATURE_PCIE:
-        case OCTEON_FEATURE_MGMT_PORT:
-        case OCTEON_FEATURE_RAID:
                 return OCTEON_IS_MODEL(OCTEON_CN56XX)
-                        || OCTEON_IS_MODEL(OCTEON_CN52XX);
+                        || OCTEON_IS_MODEL(OCTEON_CN52XX)
+                        || OCTEON_IS_MODEL(OCTEON_CN6XXX);
+
+        case OCTEON_FEATURE_SRIO:
+                return OCTEON_IS_MODEL(OCTEON_CN63XX)
+                        || OCTEON_IS_MODEL(OCTEON_CN66XX);
+
+        case OCTEON_FEATURE_ILK:
+                return (OCTEON_IS_MODEL(OCTEON_CN68XX));
 
         case OCTEON_FEATURE_KEY_MEMORY:
+                return OCTEON_IS_MODEL(OCTEON_CN38XX)
+                        || OCTEON_IS_MODEL(OCTEON_CN58XX)
+                        || OCTEON_IS_MODEL(OCTEON_CN56XX)
+                        || OCTEON_IS_MODEL(OCTEON_CN6XXX);
+
         case OCTEON_FEATURE_LED_CONTROLLER:
                 return OCTEON_IS_MODEL(OCTEON_CN38XX)
                         || OCTEON_IS_MODEL(OCTEON_CN58XX)
                         || OCTEON_IS_MODEL(OCTEON_CN56XX);
+
         case OCTEON_FEATURE_TRA:
                 return !(OCTEON_IS_MODEL(OCTEON_CN30XX)
                          || OCTEON_IS_MODEL(OCTEON_CN50XX));
+        case OCTEON_FEATURE_MGMT_PORT:
+                return OCTEON_IS_MODEL(OCTEON_CN56XX)
+                        || OCTEON_IS_MODEL(OCTEON_CN52XX)
+                        || OCTEON_IS_MODEL(OCTEON_CN6XXX);
+
+        case OCTEON_FEATURE_RAID:
+                return OCTEON_IS_MODEL(OCTEON_CN56XX)
+                        || OCTEON_IS_MODEL(OCTEON_CN52XX)
+                        || OCTEON_IS_MODEL(OCTEON_CN6XXX);
+
         case OCTEON_FEATURE_USB:
                 return !(OCTEON_IS_MODEL(OCTEON_CN38XX)
                          || OCTEON_IS_MODEL(OCTEON_CN58XX));
+
         case OCTEON_FEATURE_NO_WPTR:
                 return (OCTEON_IS_MODEL(OCTEON_CN56XX)
-                         || OCTEON_IS_MODEL(OCTEON_CN52XX))
-                        && !OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)
-                        && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X);
+                        || OCTEON_IS_MODEL(OCTEON_CN52XX)
+                        || OCTEON_IS_MODEL(OCTEON_CN6XXX))
+                          && !OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)
+                          && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X);
+
         case OCTEON_FEATURE_DFA:
                 if (!OCTEON_IS_MODEL(OCTEON_CN38XX)
                     && !OCTEON_IS_MODEL(OCTEON_CN31XX)
@@ -127,14 +195,42 @@ static inline int octeon_has_feature(enum octeon_feature feature)
                         return 0;
                 else if (OCTEON_IS_MODEL(OCTEON_CN3020))
                         return 0;
-                else if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1))
-                        return 1;
                 else
                         return !cvmx_fuse_read(120);
+
+        case OCTEON_FEATURE_HFA:
+                if (!OCTEON_IS_MODEL(OCTEON_CN6XXX))
+                        return 0;
+                else
+                        return !cvmx_fuse_read(90);
+
+        case OCTEON_FEATURE_DFM:
+                if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)
+                      || OCTEON_IS_MODEL(OCTEON_CN66XX)))
+                        return 0;
+                else
+                        return !cvmx_fuse_read(90);
+
         case OCTEON_FEATURE_MDIO_CLAUSE_45:
                 return !(OCTEON_IS_MODEL(OCTEON_CN3XXX)
                          || OCTEON_IS_MODEL(OCTEON_CN58XX)
                          || OCTEON_IS_MODEL(OCTEON_CN50XX));
+
+        case OCTEON_FEATURE_NPEI:
+                return OCTEON_IS_MODEL(OCTEON_CN56XX)
+                        || OCTEON_IS_MODEL(OCTEON_CN52XX);
+
+        case OCTEON_FEATURE_PKND:
+                return OCTEON_IS_MODEL(OCTEON_CN68XX);
+
+        case OCTEON_FEATURE_CN68XX_WQE:
+                return OCTEON_IS_MODEL(OCTEON_CN68XX);
+
+        case OCTEON_FEATURE_CIU2:
+                return OCTEON_IS_MODEL(OCTEON_CN68XX);
+
+        default:
+                break;
         }
         return 0;
 }
diff --git a/arch/mips/include/asm/octeon/octeon-model.h b/arch/mips/include/asm/octeon/octeon-model.h
index 700f88e31ca..4e338a4d942 100644
--- a/arch/mips/include/asm/octeon/octeon-model.h
+++ b/arch/mips/include/asm/octeon/octeon-model.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -24,14 +24,6 @@
  * This file may also be available under a different license from Cavium.
  * Contact Cavium Networks for more information
  ***********************license end**************************************/
-
-/*
- *
- * File defining different Octeon model IDs and macros to
- * compare them.
- *
- */
-
 #ifndef __OCTEON_MODEL_H__
 #define __OCTEON_MODEL_H__
 
@@ -52,6 +44,8 @@
  * for internal use only, and may change without notice.
  */
 
+#define OCTEON_FAMILY_MASK      0x00ffff00
+
 /* Flag bits in top byte */
 /* Ignores revision in model checks */
 #define OM_IGNORE_REVISION        0x01000000
@@ -63,21 +57,48 @@
 #define OM_IGNORE_MINOR_REVISION  0x08000000
 #define OM_FLAG_MASK              0xff000000
 
-#define OM_MATCH_5XXX_FAMILY_MODELS     0x20000000 /* Match all cn5XXX Octeon models. */
-#define OM_MATCH_6XXX_FAMILY_MODELS     0x40000000 /* Match all cn6XXX Octeon models. */
+/* Match all cn5XXX Octeon models. */
+#define OM_MATCH_5XXX_FAMILY_MODELS     0x20000000
+/* Match all cn6XXX Octeon models. */
+#define OM_MATCH_6XXX_FAMILY_MODELS     0x40000000
 
 /*
  * CN6XXX models with new revision encoding
  */
+#define OCTEON_CN68XX_PASS1_0   0x000d9100
+#define OCTEON_CN68XX_PASS1_1   0x000d9101
+#define OCTEON_CN68XX_PASS1_2   0x000d9102
+#define OCTEON_CN68XX_PASS2_0   0x000d9108
+
+#define OCTEON_CN68XX           (OCTEON_CN68XX_PASS2_0 | OM_IGNORE_REVISION)
+#define OCTEON_CN68XX_PASS1_X   (OCTEON_CN68XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
+#define OCTEON_CN68XX_PASS2_X   (OCTEON_CN68XX_PASS2_0 | OM_IGNORE_MINOR_REVISION)
+
+#define OCTEON_CN68XX_PASS1     OCTEON_CN68XX_PASS1_X
+#define OCTEON_CN68XX_PASS2     OCTEON_CN68XX_PASS2_X
+
+#define OCTEON_CN66XX_PASS1_0   0x000d9200
+#define OCTEON_CN66XX_PASS1_2   0x000d9202
+
+#define OCTEON_CN66XX           (OCTEON_CN66XX_PASS1_0 | OM_IGNORE_REVISION)
+#define OCTEON_CN66XX_PASS1_X   (OCTEON_CN66XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
+
 #define OCTEON_CN63XX_PASS1_0   0x000d9000
 #define OCTEON_CN63XX_PASS1_1   0x000d9001
 #define OCTEON_CN63XX_PASS1_2   0x000d9002
 #define OCTEON_CN63XX_PASS2_0   0x000d9008
+#define OCTEON_CN63XX_PASS2_1   0x000d9009
+#define OCTEON_CN63XX_PASS2_2   0x000d900a
 
 #define OCTEON_CN63XX           (OCTEON_CN63XX_PASS2_0 | OM_IGNORE_REVISION)
 #define OCTEON_CN63XX_PASS1_X   (OCTEON_CN63XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
 #define OCTEON_CN63XX_PASS2_X   (OCTEON_CN63XX_PASS2_0 | OM_IGNORE_MINOR_REVISION)
 
+#define OCTEON_CN61XX_PASS1_0   0x000d9300
+
+#define OCTEON_CN61XX           (OCTEON_CN61XX_PASS1_0 | OM_IGNORE_REVISION)
+#define OCTEON_CN61XX_PASS1_X   (OCTEON_CN61XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
+
 /*
  * CN5XXX models with new revision encoding
  */
@@ -90,10 +111,8 @@
 #define OCTEON_CN58XX_PASS2_3   0x000d030b
 
 #define OCTEON_CN58XX           (OCTEON_CN58XX_PASS1_0 | OM_IGNORE_REVISION)
-#define OCTEON_CN58XX_PASS1_X   (OCTEON_CN58XX_PASS1_0 \
-                                 | OM_IGNORE_MINOR_REVISION)
-#define OCTEON_CN58XX_PASS2_X   (OCTEON_CN58XX_PASS2_0 \
-                                 | OM_IGNORE_MINOR_REVISION)
+#define OCTEON_CN58XX_PASS1_X   (OCTEON_CN58XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
+#define OCTEON_CN58XX_PASS2_X   (OCTEON_CN58XX_PASS2_0 | OM_IGNORE_MINOR_REVISION)
 #define OCTEON_CN58XX_PASS1     OCTEON_CN58XX_PASS1_X
 #define OCTEON_CN58XX_PASS2     OCTEON_CN58XX_PASS2_X
 
@@ -103,10 +122,8 @@
 #define OCTEON_CN56XX_PASS2_1   0x000d0409
 
 #define OCTEON_CN56XX           (OCTEON_CN56XX_PASS2_0 | OM_IGNORE_REVISION)
-#define OCTEON_CN56XX_PASS1_X   (OCTEON_CN56XX_PASS1_0 \
-                                 | OM_IGNORE_MINOR_REVISION)
-#define OCTEON_CN56XX_PASS2_X   (OCTEON_CN56XX_PASS2_0 \
-                                 | OM_IGNORE_MINOR_REVISION)
+#define OCTEON_CN56XX_PASS1_X   (OCTEON_CN56XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
+#define OCTEON_CN56XX_PASS2_X   (OCTEON_CN56XX_PASS2_0 | OM_IGNORE_MINOR_REVISION)
 #define OCTEON_CN56XX_PASS1     OCTEON_CN56XX_PASS1_X
 #define OCTEON_CN56XX_PASS2     OCTEON_CN56XX_PASS2_X
 
@@ -125,8 +142,7 @@
 #define OCTEON_CN50XX_PASS1_0   0x000d0600
 
 #define OCTEON_CN50XX           (OCTEON_CN50XX_PASS1_0 | OM_IGNORE_REVISION)
-#define OCTEON_CN50XX_PASS1_X   (OCTEON_CN50XX_PASS1_0 \
-                                 | OM_IGNORE_MINOR_REVISION)
+#define OCTEON_CN50XX_PASS1_X   (OCTEON_CN50XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
 #define OCTEON_CN50XX_PASS1     OCTEON_CN50XX_PASS1_X
 
 /*
@@ -138,10 +154,8 @@
 #define OCTEON_CN52XX_PASS2_0   0x000d0708
 
 #define OCTEON_CN52XX           (OCTEON_CN52XX_PASS2_0 | OM_IGNORE_REVISION)
-#define OCTEON_CN52XX_PASS1_X   (OCTEON_CN52XX_PASS1_0 \
-                                 | OM_IGNORE_MINOR_REVISION)
-#define OCTEON_CN52XX_PASS2_X   (OCTEON_CN52XX_PASS2_0 \
-                                 | OM_IGNORE_MINOR_REVISION)
+#define OCTEON_CN52XX_PASS1_X   (OCTEON_CN52XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
+#define OCTEON_CN52XX_PASS2_X   (OCTEON_CN52XX_PASS2_0 | OM_IGNORE_MINOR_REVISION)
 #define OCTEON_CN52XX_PASS1     OCTEON_CN52XX_PASS1_X
 #define OCTEON_CN52XX_PASS2     OCTEON_CN52XX_PASS2_X
 
@@ -174,28 +188,23 @@
 #define OCTEON_CN3005_PASS1     (0x000d0210 | OM_CHECK_SUBMODEL)
 #define OCTEON_CN3005_PASS1_0   (0x000d0210 | OM_CHECK_SUBMODEL)
 #define OCTEON_CN3005_PASS1_1   (0x000d0212 | OM_CHECK_SUBMODEL)
-#define OCTEON_CN3005           (OCTEON_CN3005_PASS1 | OM_IGNORE_REVISION \
-                                 | OM_CHECK_SUBMODEL)
+#define OCTEON_CN3005           (OCTEON_CN3005_PASS1 | OM_IGNORE_REVISION | OM_CHECK_SUBMODEL)
 
 #define OCTEON_CN3010_PASS1     (0x000d0200 | OM_CHECK_SUBMODEL)
 #define OCTEON_CN3010_PASS1_0   (0x000d0200 | OM_CHECK_SUBMODEL)
 #define OCTEON_CN3010_PASS1_1   (0x000d0202 | OM_CHECK_SUBMODEL)
-#define OCTEON_CN3010           (OCTEON_CN3010_PASS1 | OM_IGNORE_REVISION \
-                                 | OM_CHECK_SUBMODEL)
+#define OCTEON_CN3010           (OCTEON_CN3010_PASS1 | OM_IGNORE_REVISION | OM_CHECK_SUBMODEL)
 
 #define OCTEON_CN3020_PASS1     (0x000d0110 | OM_CHECK_SUBMODEL)
 #define OCTEON_CN3020_PASS1_0   (0x000d0110 | OM_CHECK_SUBMODEL)
 #define OCTEON_CN3020_PASS1_1   (0x000d0112 | OM_CHECK_SUBMODEL)
-#define OCTEON_CN3020           (OCTEON_CN3020_PASS1 | OM_IGNORE_REVISION \
-                                 | OM_CHECK_SUBMODEL)
-
-
-
-/* This matches the complete family of CN3xxx CPUs, and not subsequent models */
-#define OCTEON_CN3XXX           (OCTEON_CN58XX_PASS1_0 \
-                                 | OM_MATCH_PREVIOUS_MODELS \
-                                 | OM_IGNORE_REVISION)
+#define OCTEON_CN3020           (OCTEON_CN3020_PASS1 | OM_IGNORE_REVISION | OM_CHECK_SUBMODEL)
 
+/*
+ * This matches the complete family of CN3xxx CPUs, and not subsequent
+ * models
+ */
+#define OCTEON_CN3XXX           (OCTEON_CN58XX_PASS1_0 | OM_MATCH_PREVIOUS_MODELS | OM_IGNORE_REVISION)
 #define OCTEON_CN5XXX           (OCTEON_CN58XX_PASS1_0 | OM_MATCH_5XXX_FAMILY_MODELS)
 #define OCTEON_CN6XXX           (OCTEON_CN63XX_PASS1_0 | OM_MATCH_6XXX_FAMILY_MODELS)
 
@@ -221,90 +230,55 @@
 #define OCTEON_38XX_FAMILY_MASK      0x00ffff00
 #define OCTEON_38XX_FAMILY_REV_MASK  0x00ffff0f
 #define OCTEON_38XX_MODEL_MASK       0x00ffff10
-#define OCTEON_38XX_MODEL_REV_MASK   (OCTEON_38XX_FAMILY_REV_MASK \
-                                      | OCTEON_38XX_MODEL_MASK)
+#define OCTEON_38XX_MODEL_REV_MASK   (OCTEON_38XX_FAMILY_REV_MASK | OCTEON_38XX_MODEL_MASK)
 
 /* CN5XXX and later use different layout of bits in the revision ID field */
 #define OCTEON_58XX_FAMILY_MASK      OCTEON_38XX_FAMILY_MASK
 #define OCTEON_58XX_FAMILY_REV_MASK  0x00ffff3f
 #define OCTEON_58XX_MODEL_MASK       0x00ffffc0
-#define OCTEON_58XX_MODEL_REV_MASK   (OCTEON_58XX_FAMILY_REV_MASK \
-                                      | OCTEON_58XX_MODEL_MASK)
-#define OCTEON_58XX_MODEL_MINOR_REV_MASK (OCTEON_58XX_MODEL_REV_MASK \
-                                          & 0x00fffff8)
+#define OCTEON_58XX_MODEL_REV_MASK   (OCTEON_58XX_FAMILY_REV_MASK | OCTEON_58XX_MODEL_MASK)
+#define OCTEON_58XX_MODEL_MINOR_REV_MASK (OCTEON_58XX_MODEL_REV_MASK & 0x00fffff8)
 #define OCTEON_5XXX_MODEL_MASK       0x00ff0fc0
 
-#define __OCTEON_MATCH_MASK__(x, y, z) (((x) & (z)) == ((y) & (z)))
-
-/* NOTE: This is for internal (to this file) use only. */
-static inline int __OCTEON_IS_MODEL_COMPILE__(uint32_t arg_model,
-                                              uint32_t chip_model)
-{
-        uint32_t rev_and_sub = OM_IGNORE_REVISION | OM_CHECK_SUBMODEL;
-
-        if ((arg_model & OCTEON_38XX_FAMILY_MASK) < OCTEON_CN58XX_PASS1_0) {
-                if (((arg_model & OM_FLAG_MASK) == rev_and_sub) &&
-                    __OCTEON_MATCH_MASK__(chip_model, arg_model,
-                                          OCTEON_38XX_MODEL_MASK))
-                        return 1;
-                if (((arg_model & OM_FLAG_MASK) == 0) &&
-                    __OCTEON_MATCH_MASK__(chip_model, arg_model,
-                                          OCTEON_38XX_FAMILY_REV_MASK))
-                        return 1;
-                if (((arg_model & OM_FLAG_MASK) == OM_IGNORE_REVISION) &&
-                    __OCTEON_MATCH_MASK__(chip_model, arg_model,
-                                          OCTEON_38XX_FAMILY_MASK))
-                        return 1;
-                if (((arg_model & OM_FLAG_MASK) == OM_CHECK_SUBMODEL) &&
-                    __OCTEON_MATCH_MASK__((chip_model), (arg_model),
-                                          OCTEON_38XX_MODEL_REV_MASK))
-                        return 1;
-                if ((arg_model & OM_MATCH_PREVIOUS_MODELS) &&
-                    ((chip_model & OCTEON_38XX_MODEL_MASK) <
-                            (arg_model & OCTEON_38XX_MODEL_MASK)))
-                        return 1;
-        } else {
-                if (((arg_model & OM_FLAG_MASK) == rev_and_sub) &&
-                    __OCTEON_MATCH_MASK__((chip_model), (arg_model),
-                                          OCTEON_58XX_MODEL_MASK))
-                        return 1;
-                if (((arg_model & OM_FLAG_MASK) == 0) &&
-                    __OCTEON_MATCH_MASK__((chip_model), (arg_model),
-                                          OCTEON_58XX_FAMILY_REV_MASK))
-                        return 1;
-                if (((arg_model & OM_FLAG_MASK) == OM_IGNORE_MINOR_REVISION) &&
-                    __OCTEON_MATCH_MASK__((chip_model), (arg_model),
-                                          OCTEON_58XX_MODEL_MINOR_REV_MASK))
-                        return 1;
-                if (((arg_model & OM_FLAG_MASK) == OM_IGNORE_REVISION) &&
-                    __OCTEON_MATCH_MASK__((chip_model), (arg_model),
-                                          OCTEON_58XX_FAMILY_MASK))
-                        return 1;
-                if (((arg_model & OM_FLAG_MASK) == OM_CHECK_SUBMODEL) &&
-                    __OCTEON_MATCH_MASK__((chip_model), (arg_model),
-                                          OCTEON_58XX_MODEL_REV_MASK))
-                        return 1;
-
-                if (((arg_model & OM_MATCH_5XXX_FAMILY_MODELS) == OM_MATCH_5XXX_FAMILY_MODELS) &&
-                    ((chip_model) >= OCTEON_CN58XX_PASS1_0) && ((chip_model) < OCTEON_CN63XX_PASS1_0))
-                        return 1;
-
-                if (((arg_model & OM_MATCH_6XXX_FAMILY_MODELS) == OM_MATCH_6XXX_FAMILY_MODELS) &&
-                    ((chip_model) >= OCTEON_CN63XX_PASS1_0))
-                        return 1;
-
-                if ((arg_model & OM_MATCH_PREVIOUS_MODELS) &&
-                    ((chip_model & OCTEON_58XX_MODEL_MASK) <
-                            (arg_model & OCTEON_58XX_MODEL_MASK)))
-                        return 1;
-        }
-        return 0;
-}
-
 /* forward declarations */
 static inline uint32_t cvmx_get_proc_id(void) __attribute__ ((pure));
 static inline uint64_t cvmx_read_csr(uint64_t csr_addr);
 
+#define __OCTEON_MATCH_MASK__(x, y, z) (((x) & (z)) == ((y) & (z)))
+
+/* NOTE: This for internal use only! */
+#define __OCTEON_IS_MODEL_COMPILE__(arg_model, chip_model)              \
+((((arg_model & OCTEON_38XX_FAMILY_MASK) < OCTEON_CN58XX_PASS1_0)  && ( \
+                ((((arg_model) & (OM_FLAG_MASK)) == (OM_IGNORE_REVISION | OM_CHECK_SUBMODEL)) \
+                        && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_38XX_MODEL_MASK)) || \
+                ((((arg_model) & (OM_FLAG_MASK)) == 0)                  \
+                        && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_38XX_FAMILY_REV_MASK)) || \
+                ((((arg_model) & (OM_FLAG_MASK)) == OM_IGNORE_REVISION) \
+                        && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_38XX_FAMILY_MASK)) || \
+                ((((arg_model) & (OM_FLAG_MASK)) == OM_CHECK_SUBMODEL)  \
+                        && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_38XX_MODEL_REV_MASK)) || \
+                ((((arg_model) & (OM_MATCH_PREVIOUS_MODELS)) == OM_MATCH_PREVIOUS_MODELS) \
+                        && (((chip_model) & OCTEON_38XX_MODEL_MASK) < ((arg_model) & OCTEON_38XX_MODEL_MASK))) \
+                )) ||                                                   \
+        (((arg_model & OCTEON_38XX_FAMILY_MASK) >= OCTEON_CN58XX_PASS1_0)  && ( \
+                ((((arg_model) & (OM_FLAG_MASK)) == (OM_IGNORE_REVISION | OM_CHECK_SUBMODEL)) \
+                        && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_MODEL_MASK)) || \
+                ((((arg_model) & (OM_FLAG_MASK)) == 0)                  \
+                        && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_FAMILY_REV_MASK)) || \
+                ((((arg_model) & (OM_FLAG_MASK)) == OM_IGNORE_MINOR_REVISION) \
+                        && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_MODEL_MINOR_REV_MASK)) || \
+                ((((arg_model) & (OM_FLAG_MASK)) == OM_IGNORE_REVISION) \
+                        && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_FAMILY_MASK)) || \
+                ((((arg_model) & (OM_FLAG_MASK)) == OM_CHECK_SUBMODEL)  \
+                        && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_MODEL_REV_MASK)) || \
+                ((((arg_model) & (OM_MATCH_5XXX_FAMILY_MODELS)) == OM_MATCH_5XXX_FAMILY_MODELS) \
+                        && ((chip_model) >= OCTEON_CN58XX_PASS1_0) && ((chip_model) < OCTEON_CN63XX_PASS1_0)) || \
+                ((((arg_model) & (OM_MATCH_6XXX_FAMILY_MODELS)) == OM_MATCH_6XXX_FAMILY_MODELS) \
+                        && ((chip_model) >= OCTEON_CN63XX_PASS1_0)) ||  \
+                ((((arg_model) & (OM_MATCH_PREVIOUS_MODELS)) == OM_MATCH_PREVIOUS_MODELS) \
+                        && (((chip_model) & OCTEON_58XX_MODEL_MASK) < ((arg_model) & OCTEON_58XX_MODEL_MASK))) \
+                )))
+
 /* NOTE: This for internal use only!!!!! */
 static inline int __octeon_is_model_runtime__(uint32_t model)
 {
@@ -312,22 +286,25 @@ static inline int __octeon_is_model_runtime__(uint32_t model)
 
         /*
          * Check for special case of mismarked 3005 samples. We only
-         * need to check if the sub model isn't being ignored.
+         * need to check if the sub model isn't being ignored
          */
         if ((model & OM_CHECK_SUBMODEL) == OM_CHECK_SUBMODEL) {
-                if (cpuid == OCTEON_CN3010_PASS1 \
-                    && (cvmx_read_csr(0x80011800800007B8ull) & (1ull << 34)))
+                if (cpuid == OCTEON_CN3010_PASS1 && (cvmx_read_csr(0x80011800800007B8ull) & (1ull << 34)))
                         cpuid |= 0x10;
         }
         return __OCTEON_IS_MODEL_COMPILE__(model, cpuid);
 }
 
 /*
- * The OCTEON_IS_MODEL macro should be used for all Octeon model
- * checking done in a program.  This should be kept runtime if at all
- * possible.  Any compile time (#if OCTEON_IS_MODEL) usage must be
- * condtionalized with OCTEON_IS_COMMON_BINARY() if runtime checking
- * support is required.
+ * The OCTEON_IS_MODEL macro should be used for all Octeon model checking done
+ * in a program.
+ * This should be kept runtime if at all possible  and must be conditionalized
+ * with OCTEON_IS_COMMON_BINARY() if runtime checking support is required.
+ *
+ * Use of the macro in preprocessor directives ( #if OCTEON_IS_MODEL(...) )
+ * is NOT SUPPORTED, and should be replaced with CVMX_COMPILED_FOR()
+ * I.e.:
+ *  #if OCTEON_IS_MODEL(OCTEON_CN56XX)  ->  #if CVMX_COMPILED_FOR(OCTEON_CN56XX)
  */
 #define OCTEON_IS_MODEL(x) __octeon_is_model_runtime__(x)
 #define OCTEON_IS_COMMON_BINARY() 1
diff --git a/arch/mips/include/asm/octeon/pci-octeon.h b/arch/mips/include/asm/octeon/pci-octeon.h
index fba2ba200f5..c66734bd338 100644
--- a/arch/mips/include/asm/octeon/pci-octeon.h
+++ b/arch/mips/include/asm/octeon/pci-octeon.h
@@ -56,7 +56,8 @@ enum octeon_dma_bar_type {
         OCTEON_DMA_BAR_TYPE_INVALID,
         OCTEON_DMA_BAR_TYPE_SMALL,
         OCTEON_DMA_BAR_TYPE_BIG,
-        OCTEON_DMA_BAR_TYPE_PCIE
+        OCTEON_DMA_BAR_TYPE_PCIE,
+        OCTEON_DMA_BAR_TYPE_PCIE2
 };
 
 /*
diff --git a/arch/mips/include/asm/traps.h b/arch/mips/include/asm/traps.h
index 90ff2f497c5..ff74aec3561 100644
--- a/arch/mips/include/asm/traps.h
+++ b/arch/mips/include/asm/traps.h
@@ -24,5 +24,18 @@ extern int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
 extern void (*board_nmi_handler_setup)(void);
 extern void (*board_ejtag_handler_setup)(void);
 extern void (*board_bind_eic_interrupt)(int irq, int regset);
+extern void (*board_ebase_setup)(void);
+
+extern int register_nmi_notifier(struct notifier_block *nb);
+
+#define nmi_notifier(fn, pri)                                           \
+({                                                                      \
+        static struct notifier_block fn##_nb = {                        \
+                .notifier_call = fn,                                    \
+                .priority = pri                                         \
+        };                                                              \
+                                                                        \
+        register_nmi_notifier(&fn##_nb);                                \
+})
 
 #endif /* _ASM_TRAPS_H */
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index 1a966183e35..0c6877ea900 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -55,9 +55,11 @@ obj-$(CONFIG_CPU_TX49XX)	+= r4k_fpu.o r4k_switch.o
 obj-$(CONFIG_CPU_VR41XX)        += r4k_fpu.o r4k_switch.o
 obj-$(CONFIG_CPU_CAVIUM_OCTEON) += octeon_switch.o
 obj-$(CONFIG_CPU_XLR)           += r4k_fpu.o r4k_switch.o
+obj-$(CONFIG_CPU_XLP)           += r4k_fpu.o r4k_switch.o
 
 obj-$(CONFIG_SMP)               += smp.o
 obj-$(CONFIG_SMP_UP)            += smp-up.o
+obj-$(CONFIG_CPU_BMIPS)         += smp-bmips.o bmips_vec.o
 
 obj-$(CONFIG_MIPS_MT)           += mips-mt.o
 obj-$(CONFIG_MIPS_MT_FPAFF)     += mips-mt-fpaff.o
diff --git a/arch/mips/kernel/bmips_vec.S b/arch/mips/kernel/bmips_vec.S
new file mode 100644
index 00000000000..e908e81330b
--- /dev/null
+++ b/arch/mips/kernel/bmips_vec.S
@@ -0,0 +1,255 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2011 by Kevin Cernekee (cernekee@gmail.com)
+ *
+ * Reset/NMI/re-entry vectors for BMIPS processors
+ */
+
+#include <linux/init.h>
+
+#include <asm/asm.h>
+#include <asm/asmmacro.h>
+#include <asm/cacheops.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/stackframe.h>
+#include <asm/addrspace.h>
+#include <asm/hazards.h>
+#include <asm/bmips.h>
+
+        .macro  BARRIER
+        .set    mips32
+        _ssnop
+        _ssnop
+        _ssnop
+        .set    mips0
+        .endm
+
+        __CPUINIT
+
+/***********************************************************************
+ * Alternate CPU1 startup vector for BMIPS4350
+ *
+ * On some systems the bootloader has already started CPU1 and configured
+ * it to resume execution at 0x8000_0200 (!BEV IV vector) when it is
+ * triggered by the SW1 interrupt.  If that is the case we try to move
+ * it to a more convenient place: BMIPS_WARM_RESTART_VEC @ 0x8000_0380.
+ ***********************************************************************/
+
+LEAF(bmips_smp_movevec)
+        la      k0, 1f
+        li      k1, CKSEG1
+        or      k0, k1
+        jr      k0
+
+1:
+        /* clear IV, pending IPIs */
+        mtc0    zero, CP0_CAUSE
+
+        /* re-enable IRQs to wait for SW1 */
+        li      k0, ST0_IE | ST0_BEV | STATUSF_IP1
+        mtc0    k0, CP0_STATUS
+
+        /* set up CPU1 CBR; move BASE to 0xa000_0000 */
+        li      k0, 0xff400000
+        mtc0    k0, $22, 6
+        li      k1, CKSEG1 | BMIPS_RELO_VECTOR_CONTROL_1
+        or      k0, k1
+        li      k1, 0xa0080000
+        sw      k1, 0(k0)
+
+        /* wait here for SW1 interrupt from bmips_boot_secondary() */
+        wait
+
+        la      k0, bmips_reset_nmi_vec
+        li      k1, CKSEG1
+        or      k0, k1
+        jr      k0
+END(bmips_smp_movevec)
+
+/***********************************************************************
+ * Reset/NMI vector
+ * For BMIPS processors that can relocate their exception vectors, this
+ * entire function gets copied to 0x8000_0000.
+ ***********************************************************************/
+
+NESTED(bmips_reset_nmi_vec, PT_SIZE, sp)
+        .set    push
+        .set    noat
+        .align  4
+
+#ifdef CONFIG_SMP
+        /* if the NMI bit is clear, assume this is a CPU1 reset instead */
+        li      k1, (1 << 19)
+        mfc0    k0, CP0_STATUS
+        and     k0, k1
+        beqz    k0, bmips_smp_entry
+
+#if defined(CONFIG_CPU_BMIPS5000)
+        /* if we're not on core 0, this must be the SMP boot signal */
+        li      k1, (3 << 25)
+        mfc0    k0, $22
+        and     k0, k1
+        bnez    k0, bmips_smp_entry
+#endif
+#endif /* CONFIG_SMP */
+
+        /* nope, it's just a regular NMI */
+        SAVE_ALL
+        move    a0, sp
+
+        /* clear EXL, ERL, BEV so that TLB refills still work */
+        mfc0    k0, CP0_STATUS
+        li      k1, ST0_ERL | ST0_EXL | ST0_BEV | ST0_IE
+        or      k0, k1
+        xor     k0, k1
+        mtc0    k0, CP0_STATUS
+        BARRIER
+
+        /* jump to the NMI handler function */
+        la      k0, nmi_handler
+        jr      k0
+
+        RESTORE_ALL
+        .set    mips3
+        eret
+
+/***********************************************************************
+ * CPU1 reset vector (used for the initial boot only)
+ * This is still part of bmips_reset_nmi_vec().
+ ***********************************************************************/
+
+#ifdef CONFIG_SMP
+
+bmips_smp_entry:
+
+        /* set up CP0 STATUS; enable FPU */
+        li      k0, 0x30000000
+        mtc0    k0, CP0_STATUS
+        BARRIER
+
+        /* set local CP0 CONFIG to make kseg0 cacheable, write-back */
+        mfc0    k0, CP0_CONFIG
+        ori     k0, 0x07
+        xori    k0, 0x04
+        mtc0    k0, CP0_CONFIG
+
+#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
+        /* initialize CPU1's local I-cache */
+        li      k0, 0x80000000
+        li      k1, 0x80010000
+        mtc0    zero, $28
+        mtc0    zero, $28, 1
+        BARRIER
+
+1:      cache   Index_Store_Tag_I, 0(k0)
+        addiu   k0, 16
+        bne     k0, k1, 1b
+#elif defined(CONFIG_CPU_BMIPS5000)
+        /* set exception vector base */
+        la      k0, ebase
+        lw      k0, 0(k0)
+        mtc0    k0, $15, 1
+        BARRIER
+#endif
+
+        /* jump back to kseg0 in case we need to remap the kseg1 area */
+        la      k0, 1f
+        jr      k0
+1:
+        la      k0, bmips_enable_xks01
+        jalr    k0
+
+        /* use temporary stack to set up upper memory TLB */
+        li      sp, BMIPS_WARM_RESTART_VEC
+        la      k0, plat_wired_tlb_setup
+        jalr    k0
+
+        /* switch to permanent stack and continue booting */
+
+        .global bmips_secondary_reentry
+bmips_secondary_reentry:
+        la      k0, bmips_smp_boot_sp
+        lw      sp, 0(k0)
+        la      k0, bmips_smp_boot_gp
+        lw      gp, 0(k0)
+        la      k0, start_secondary
+        jr      k0
+
+#endif /* CONFIG_SMP */
+
+        .align  4
+        .global bmips_reset_nmi_vec_end
+bmips_reset_nmi_vec_end:
+
+END(bmips_reset_nmi_vec)
+
+        .set    pop
+        .previous
+
+/***********************************************************************
+ * CPU1 warm restart vector (used for second and subsequent boots).
+ * Also used for S2 standby recovery (PM).
+ * This entire function gets copied to (BMIPS_WARM_RESTART_VEC)
+ ***********************************************************************/
+
+LEAF(bmips_smp_int_vec)
+
+        .align  4
+        mfc0    k0, CP0_STATUS
+        ori     k0, 0x01
+        xori    k0, 0x01
+        mtc0    k0, CP0_STATUS
+        eret
+
+        .align  4
+        .global bmips_smp_int_vec_end
+bmips_smp_int_vec_end:
+
+END(bmips_smp_int_vec)
+
+/***********************************************************************
+ * XKS01 support
+ * Certain CPUs support extending kseg0 to 1024MB.
+ ***********************************************************************/
+
+        __CPUINIT
+
+LEAF(bmips_enable_xks01)
+
+#if defined(CONFIG_XKS01)
+
+#if defined(CONFIG_CPU_BMIPS4380)
+        mfc0    t0, $22, 3
+        li      t1, 0x1ff0
+        li      t2, (1 << 12) | (1 << 9)
+        or      t0, t1
+        xor     t0, t1
+        or      t0, t2
+        mtc0    t0, $22, 3
+        BARRIER
+#elif defined(CONFIG_CPU_BMIPS5000)
+        mfc0    t0, $22, 5
+        li      t1, 0x01ff
+        li      t2, (1 << 8) | (1 << 5)
+        or      t0, t1
+        xor     t0, t1
+        or      t0, t2
+        mtc0    t0, $22, 5
+        BARRIER
+#else
+
+#error Missing XKS01 setup
+
+#endif
+
+#endif /* defined(CONFIG_XKS01) */
+
+        jr      ra
+
+END(bmips_enable_xks01)
+
+        .previous
diff --git a/arch/mips/kernel/branch.c b/arch/mips/kernel/branch.c
index 32103cc2a25..4d735d0e58f 100644
--- a/arch/mips/kernel/branch.c
+++ b/arch/mips/kernel/branch.c
@@ -9,6 +9,7 @@
 #include <linux/kernel.h>
 #include <linux/sched.h>
 #include <linux/signal.h>
+#include <linux/module.h>
 #include <asm/branch.h>
 #include <asm/cpu.h>
 #include <asm/cpu-features.h>
@@ -17,28 +18,22 @@
 #include <asm/ptrace.h>
 #include <asm/uaccess.h>
 
-/*
- * Compute the return address and do emulate branch simulation, if required.
+/**
+ * __compute_return_epc_for_insn - Computes the return address and do emulate
+ *                                  branch simulation, if required.
+ *
+ * @regs:       Pointer to pt_regs
+ * @insn:       branch instruction to decode
+ * @returns:    -EFAULT on error and forces SIGBUS, and on success
+ *              returns 0 or BRANCH_LIKELY_TAKEN as appropriate after
+ *              evaluating the branch.
  */
-int __compute_return_epc(struct pt_regs *regs)
+int __compute_return_epc_for_insn(struct pt_regs *regs,
+                                   union mips_instruction insn)
 {
-        unsigned int __user *addr;
         unsigned int bit, fcr31, dspcontrol;
-        long epc;
-        union mips_instruction insn;
-
-        epc = regs->cp0_epc;
-        if (epc & 3)
-                goto unaligned;
-
-        /*
-         * Read the instruction
-         */
-        addr = (unsigned int __user *) epc;
-        if (__get_user(insn.word, addr)) {
-                force_sig(SIGSEGV, current);
-                return -EFAULT;
-        }
+        long epc = regs->cp0_epc;
+        int ret = 0;
 
         switch (insn.i_format.opcode) {
         /*
@@ -64,18 +59,22 @@ int __compute_return_epc(struct pt_regs *regs)
                 switch (insn.i_format.rt) {
                 case bltz_op:
                 case bltzl_op:
-                        if ((long)regs->regs[insn.i_format.rs] < 0)
+                        if ((long)regs->regs[insn.i_format.rs] < 0) {
                                 epc = epc + 4 + (insn.i_format.simmediate << 2);
-                        else
+                                if (insn.i_format.rt == bltzl_op)
+                                        ret = BRANCH_LIKELY_TAKEN;
+                        } else
                                 epc += 8;
                         regs->cp0_epc = epc;
                         break;
 
                 case bgez_op:
                 case bgezl_op:
-                        if ((long)regs->regs[insn.i_format.rs] >= 0)
+                        if ((long)regs->regs[insn.i_format.rs] >= 0) {
                                 epc = epc + 4 + (insn.i_format.simmediate << 2);
-                        else
+                                if (insn.i_format.rt == bgezl_op)
+                                        ret = BRANCH_LIKELY_TAKEN;
+                        } else
                                 epc += 8;
                         regs->cp0_epc = epc;
                         break;
@@ -83,9 +82,11 @@ int __compute_return_epc(struct pt_regs *regs)
                 case bltzal_op:
                 case bltzall_op:
                         regs->regs[31] = epc + 8;
-                        if ((long)regs->regs[insn.i_format.rs] < 0)
+                        if ((long)regs->regs[insn.i_format.rs] < 0) {
                                 epc = epc + 4 + (insn.i_format.simmediate << 2);
-                        else
+                                if (insn.i_format.rt == bltzall_op)
+                                        ret = BRANCH_LIKELY_TAKEN;
+                        } else
                                 epc += 8;
                         regs->cp0_epc = epc;
                         break;
@@ -93,12 +94,15 @@ int __compute_return_epc(struct pt_regs *regs)
                 case bgezal_op:
                 case bgezall_op:
                         regs->regs[31] = epc + 8;
-                        if ((long)regs->regs[insn.i_format.rs] >= 0)
+                        if ((long)regs->regs[insn.i_format.rs] >= 0) {
                                 epc = epc + 4 + (insn.i_format.simmediate << 2);
-                        else
+                                if (insn.i_format.rt == bgezall_op)
+                                        ret = BRANCH_LIKELY_TAKEN;
+                        } else
                                 epc += 8;
                         regs->cp0_epc = epc;
                         break;
+
                 case bposge32_op:
                         if (!cpu_has_dsp)
                                 goto sigill;
@@ -133,9 +137,11 @@ int __compute_return_epc(struct pt_regs *regs)
         case beq_op:
         case beql_op:
                 if (regs->regs[insn.i_format.rs] ==
-                    regs->regs[insn.i_format.rt])
+                    regs->regs[insn.i_format.rt]) {
                         epc = epc + 4 + (insn.i_format.simmediate << 2);
-                else
+                        if (insn.i_format.rt == beql_op)
+                                ret = BRANCH_LIKELY_TAKEN;
+                } else
                         epc += 8;
                 regs->cp0_epc = epc;
                 break;
@@ -143,9 +149,11 @@ int __compute_return_epc(struct pt_regs *regs)
         case bne_op:
         case bnel_op:
                 if (regs->regs[insn.i_format.rs] !=
-                    regs->regs[insn.i_format.rt])
+                    regs->regs[insn.i_format.rt]) {
                         epc = epc + 4 + (insn.i_format.simmediate << 2);
-                else
+                        if (insn.i_format.rt == bnel_op)
+                                ret = BRANCH_LIKELY_TAKEN;
+                } else
                         epc += 8;
                 regs->cp0_epc = epc;
                 break;
@@ -153,9 +161,11 @@ int __compute_return_epc(struct pt_regs *regs)
         case blez_op: /* not really i_format */
         case blezl_op:
                 /* rt field assumed to be zero */
-                if ((long)regs->regs[insn.i_format.rs] <= 0)
+                if ((long)regs->regs[insn.i_format.rs] <= 0) {
                         epc = epc + 4 + (insn.i_format.simmediate << 2);
-                else
+                        if (insn.i_format.rt == bnel_op)
+                                ret = BRANCH_LIKELY_TAKEN;
+                } else
                         epc += 8;
                 regs->cp0_epc = epc;
                 break;
@@ -163,9 +173,11 @@ int __compute_return_epc(struct pt_regs *regs)
         case bgtz_op:
         case bgtzl_op:
                 /* rt field assumed to be zero */
-                if ((long)regs->regs[insn.i_format.rs] > 0)
+                if ((long)regs->regs[insn.i_format.rs] > 0) {
                         epc = epc + 4 + (insn.i_format.simmediate << 2);
-                else
+                        if (insn.i_format.rt == bnel_op)
+                                ret = BRANCH_LIKELY_TAKEN;
+                } else
                         epc += 8;
                 regs->cp0_epc = epc;
                 break;
@@ -187,18 +199,22 @@ int __compute_return_epc(struct pt_regs *regs)
                 switch (insn.i_format.rt & 3) {
                 case 0: /* bc1f */
                 case 2: /* bc1fl */
-                        if (~fcr31 & (1 << bit))
+                        if (~fcr31 & (1 << bit)) {
                                 epc = epc + 4 + (insn.i_format.simmediate << 2);
-                        else
+                                if (insn.i_format.rt == 2)
+                                        ret = BRANCH_LIKELY_TAKEN;
+                        } else
                                 epc += 8;
                         regs->cp0_epc = epc;
                         break;
 
                 case 1: /* bc1t */
                 case 3: /* bc1tl */
-                        if (fcr31 & (1 << bit))
+                        if (fcr31 & (1 << bit)) {
                                 epc = epc + 4 + (insn.i_format.simmediate << 2);
-                        else
+                                if (insn.i_format.rt == 3)
+                                        ret = BRANCH_LIKELY_TAKEN;
+                        } else
                                 epc += 8;
                         regs->cp0_epc = epc;
                         break;
@@ -239,15 +255,39 @@ int __compute_return_epc(struct pt_regs *regs)
 #endif
         }
 
-        return 0;
+        return ret;
 
-unaligned:
-        printk("%s: unaligned epc - sending SIGBUS.\n", current->comm);
+sigill:
+        printk("%s: DSP branch but not DSP ASE - sending SIGBUS.\n", current->comm);
         force_sig(SIGBUS, current);
         return -EFAULT;
+}
+EXPORT_SYMBOL_GPL(__compute_return_epc_for_insn);
 
-sigill:
-        printk("%s: DSP branch but not DSP ASE - sending SIGBUS.\n", current->comm);
+int __compute_return_epc(struct pt_regs *regs)
+{
+        unsigned int __user *addr;
+        long epc;
+        union mips_instruction insn;
+
+        epc = regs->cp0_epc;
+        if (epc & 3)
+                goto unaligned;
+
+        /*
+         * Read the instruction
+         */
+        addr = (unsigned int __user *) epc;
+        if (__get_user(insn.word, addr)) {
+                force_sig(SIGSEGV, current);
+                return -EFAULT;
+        }
+
+        return __compute_return_epc_for_insn(regs, insn);
+
+unaligned:
+        printk("%s: unaligned epc - sending SIGBUS.\n", current->comm);
         force_sig(SIGBUS, current);
         return -EFAULT;
+
 }
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 98383995e6a..0bab464b8e3 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -191,6 +191,8 @@ void __init check_wait(void)
         case CPU_CAVIUM_OCTEON_PLUS:
         case CPU_CAVIUM_OCTEON2:
         case CPU_JZRISC:
+        case CPU_XLR:
+        case CPU_XLP:
                 cpu_wait = r4k_wait;
                 break;
 
@@ -1030,6 +1032,12 @@ static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
                         MIPS_CPU_LLSC);
 
         switch (c->processor_id & 0xff00) {
+        case PRID_IMP_NETLOGIC_XLP8XX:
+        case PRID_IMP_NETLOGIC_XLP3XX:
+                c->cputype = CPU_XLP;
+                __cpu_name[cpu] = "Netlogic XLP";
+                break;
+
         case PRID_IMP_NETLOGIC_XLR732:
         case PRID_IMP_NETLOGIC_XLR716:
         case PRID_IMP_NETLOGIC_XLR532:
@@ -1060,14 +1068,21 @@ static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
                 break;
 
         default:
-                printk(KERN_INFO "Unknown Netlogic chip id [%02x]!\n",
+                pr_info("Unknown Netlogic chip id [%02x]!\n",
                        c->processor_id);
                 c->cputype = CPU_XLR;
                 break;
         }
 
-        c->isa_level = MIPS_CPU_ISA_M64R1;
-        c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
+        if (c->cputype == CPU_XLP) {
+                c->isa_level = MIPS_CPU_ISA_M64R2;
+                c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
+                /* This will be updated again after all threads are woken up */
+                c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
+        } else {
+                c->isa_level = MIPS_CPU_ISA_M64R1;
+                c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
+        }
 }
 
 #ifdef CONFIG_64BIT
diff --git a/arch/mips/kernel/kprobes.c b/arch/mips/kernel/kprobes.c
index ee28683fc2a..158467da9bc 100644
--- a/arch/mips/kernel/kprobes.c
+++ b/arch/mips/kernel/kprobes.c
@@ -25,10 +25,12 @@
 
 #include <linux/kprobes.h>
 #include <linux/preempt.h>
+#include <linux/uaccess.h>
 #include <linux/kdebug.h>
 #include <linux/slab.h>
 
 #include <asm/ptrace.h>
+#include <asm/branch.h>
 #include <asm/break.h>
 #include <asm/inst.h>
 
@@ -112,17 +114,49 @@ insn_ok:
         return 0;
 }
 
+/*
+ * insn_has_ll_or_sc function checks whether instruction is ll or sc
+ * one; putting breakpoint on top of atomic ll/sc pair is bad idea;
+ * so we need to prevent it and refuse kprobes insertion for such
+ * instructions; cannot do much about breakpoint in the middle of
+ * ll/sc pair; it is upto user to avoid those places
+ */
+static int __kprobes insn_has_ll_or_sc(union mips_instruction insn)
+{
+        int ret = 0;
+
+        switch (insn.i_format.opcode) {
+        case ll_op:
+        case lld_op:
+        case sc_op:
+        case scd_op:
+                ret = 1;
+                break;
+        default:
+                break;
+        }
+        return ret;
+}
+
 int __kprobes arch_prepare_kprobe(struct kprobe *p)
 {
         union mips_instruction insn;
         union mips_instruction prev_insn;
         int ret = 0;
 
-        prev_insn = p->addr[-1];
         insn = p->addr[0];
 
-        if (insn_has_delayslot(insn) || insn_has_delayslot(prev_insn)) {
-                pr_notice("Kprobes for branch and jump instructions are not supported\n");
+        if (insn_has_ll_or_sc(insn)) {
+                pr_notice("Kprobes for ll and sc instructions are not"
+                          "supported\n");
+                ret = -EINVAL;
+                goto out;
+        }
+
+        if ((probe_kernel_read(&prev_insn, p->addr - 1,
+                                sizeof(mips_instruction)) == 0) &&
+                                insn_has_delayslot(prev_insn)) {
+                pr_notice("Kprobes for branch delayslot are not supported\n");
                 ret = -EINVAL;
                 goto out;
         }
@@ -138,9 +172,20 @@ int __kprobes arch_prepare_kprobe(struct kprobe *p)
          * In the kprobe->ainsn.insn[] array we store the original
          * instruction at index zero and a break trap instruction at
          * index one.
+         *
+         * On MIPS arch if the instruction at probed address is a
+         * branch instruction, we need to execute the instruction at
+         * Branch Delayslot (BD) at the time of probe hit. As MIPS also
+         * doesn't have single stepping support, the BD instruction can
+         * not be executed in-line and it would be executed on SSOL slot
+         * using a normal breakpoint instruction in the next slot.
+         * So, read the instruction and save it for later execution.
          */
+        if (insn_has_delayslot(insn))
+                memcpy(&p->ainsn.insn[0], p->addr + 1, sizeof(kprobe_opcode_t));
+        else
+                memcpy(&p->ainsn.insn[0], p->addr, sizeof(kprobe_opcode_t));
 
-        memcpy(&p->ainsn.insn[0], p->addr, sizeof(kprobe_opcode_t));
         p->ainsn.insn[1] = breakpoint2_insn;
         p->opcode = *p->addr;
 
@@ -191,16 +236,96 @@ static void set_current_kprobe(struct kprobe *p, struct pt_regs *regs,
         kcb->kprobe_saved_epc = regs->cp0_epc;
 }
 
-static void prepare_singlestep(struct kprobe *p, struct pt_regs *regs)
+/**
+ * evaluate_branch_instrucion -
+ *
+ * Evaluate the branch instruction at probed address during probe hit. The
+ * result of evaluation would be the updated epc. The insturction in delayslot
+ * would actually be single stepped using a normal breakpoint) on SSOL slot.
+ *
+ * The result is also saved in the kprobe control block for later use,
+ * in case we need to execute the delayslot instruction. The latter will be
+ * false for NOP instruction in dealyslot and the branch-likely instructions
+ * when the branch is taken. And for those cases we set a flag as
+ * SKIP_DELAYSLOT in the kprobe control block
+ */
+static int evaluate_branch_instruction(struct kprobe *p, struct pt_regs *regs,
+                                        struct kprobe_ctlblk *kcb)
 {
+        union mips_instruction insn = p->opcode;
+        long epc;
+        int ret = 0;
+
+        epc = regs->cp0_epc;
+        if (epc & 3)
+                goto unaligned;
+
+        if (p->ainsn.insn->word == 0)
+                kcb->flags |= SKIP_DELAYSLOT;
+        else
+                kcb->flags &= ~SKIP_DELAYSLOT;
+
+        ret = __compute_return_epc_for_insn(regs, insn);
+        if (ret < 0)
+                return ret;
+
+        if (ret == BRANCH_LIKELY_TAKEN)
+                kcb->flags |= SKIP_DELAYSLOT;
+
+        kcb->target_epc = regs->cp0_epc;
+
+        return 0;
+
+unaligned:
+        pr_notice("%s: unaligned epc - sending SIGBUS.\n", current->comm);
+        force_sig(SIGBUS, current);
+        return -EFAULT;
+
+}
+
+static void prepare_singlestep(struct kprobe *p, struct pt_regs *regs,
+                                                struct kprobe_ctlblk *kcb)
+{
+        int ret = 0;
+
         regs->cp0_status &= ~ST0_IE;
 
         /* single step inline if the instruction is a break */
         if (p->opcode.word == breakpoint_insn.word ||
             p->opcode.word == breakpoint2_insn.word)
                 regs->cp0_epc = (unsigned long)p->addr;
-        else
-                regs->cp0_epc = (unsigned long)&p->ainsn.insn[0];
+        else if (insn_has_delayslot(p->opcode)) {
+                ret = evaluate_branch_instruction(p, regs, kcb);
+                if (ret < 0) {
+                        pr_notice("Kprobes: Error in evaluating branch\n");
+                        return;
+                }
+        }
+        regs->cp0_epc = (unsigned long)&p->ainsn.insn[0];
+}
+
+/*
+ * Called after single-stepping.  p->addr is the address of the
+ * instruction whose first byte has been replaced by the "break 0"
+ * instruction.  To avoid the SMP problems that can occur when we
+ * temporarily put back the original opcode to single-step, we
+ * single-stepped a copy of the instruction.  The address of this
+ * copy is p->ainsn.insn.
+ *
+ * This function prepares to return from the post-single-step
+ * breakpoint trap. In case of branch instructions, the target
+ * epc to be restored.
+ */
+static void __kprobes resume_execution(struct kprobe *p,
+                                       struct pt_regs *regs,
+                                       struct kprobe_ctlblk *kcb)
+{
+        if (insn_has_delayslot(p->opcode))
+                regs->cp0_epc = kcb->target_epc;
+        else {
+                unsigned long orig_epc = kcb->kprobe_saved_epc;
+                regs->cp0_epc = orig_epc + 4;
+        }
 }
 
 static int __kprobes kprobe_handler(struct pt_regs *regs)
@@ -239,8 +364,13 @@ static int __kprobes kprobe_handler(struct pt_regs *regs)
                         save_previous_kprobe(kcb);
                         set_current_kprobe(p, regs, kcb);
                         kprobes_inc_nmissed_count(p);
-                        prepare_singlestep(p, regs);
+                        prepare_singlestep(p, regs, kcb);
                         kcb->kprobe_status = KPROBE_REENTER;
+                        if (kcb->flags & SKIP_DELAYSLOT) {
+                                resume_execution(p, regs, kcb);
+                                restore_previous_kprobe(kcb);
+                                preempt_enable_no_resched();
+                        }
                         return 1;
                 } else {
                         if (addr->word != breakpoint_insn.word) {
@@ -284,8 +414,16 @@ static int __kprobes kprobe_handler(struct pt_regs *regs)
         }
 
 ss_probe:
-        prepare_singlestep(p, regs);
-        kcb->kprobe_status = KPROBE_HIT_SS;
+        prepare_singlestep(p, regs, kcb);
+        if (kcb->flags & SKIP_DELAYSLOT) {
+                kcb->kprobe_status = KPROBE_HIT_SSDONE;
+                if (p->post_handler)
+                        p->post_handler(p, regs, 0);
+                resume_execution(p, regs, kcb);
+                preempt_enable_no_resched();
+        } else
+                kcb->kprobe_status = KPROBE_HIT_SS;
+
         return 1;
 
 no_kprobe:
@@ -294,25 +432,6 @@ no_kprobe:
 
 }
 
-/*
- * Called after single-stepping.  p->addr is the address of the
- * instruction whose first byte has been replaced by the "break 0"
- * instruction.  To avoid the SMP problems that can occur when we
- * temporarily put back the original opcode to single-step, we
- * single-stepped a copy of the instruction.  The address of this
- * copy is p->ainsn.insn.
- *
- * This function prepares to return from the post-single-step
- * breakpoint trap.
- */
-static void __kprobes resume_execution(struct kprobe *p,
-                                       struct pt_regs *regs,
-                                       struct kprobe_ctlblk *kcb)
-{
-        unsigned long orig_epc = kcb->kprobe_saved_epc;
-        regs->cp0_epc = orig_epc + 4;
-}
-
 static inline int post_kprobe_handler(struct pt_regs *regs)
 {
         struct kprobe *cur = kprobe_running();
diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c
index 4f2971bcf8e..bda4bc9e698 100644
--- a/arch/mips/kernel/perf_event_mipsxx.c
+++ b/arch/mips/kernel/perf_event_mipsxx.c
@@ -621,11 +621,6 @@ static int mipspmu_event_init(struct perf_event *event)
                 return -ENODEV;
 
         if (!atomic_inc_not_zero(&active_events)) {
-                if (atomic_read(&active_events) > MIPS_MAX_HWEVENTS) {
-                        atomic_dec(&active_events);
-                        return -ENOSPC;
-                }
-
                 mutex_lock(&pmu_reserve_mutex);
                 if (atomic_read(&active_events) == 0)
                         err = mipspmu_get_irq();
@@ -638,11 +633,7 @@ static int mipspmu_event_init(struct perf_event *event)
         if (err)
                 return err;
 
-        err = __hw_perf_event_init(event);
-        if (err)
-                hw_perf_event_destroy(event);
-
-        return err;
+        return __hw_perf_event_init(event);
 }
 
 static struct pmu pmu = {
@@ -712,18 +703,6 @@ static const struct mips_perf_event *mipspmu_map_cache_event(u64 config)
 
 }
 
-static int validate_event(struct cpu_hw_events *cpuc,
-               struct perf_event *event)
-{
-        struct hw_perf_event fake_hwc = event->hw;
-
-        /* Allow mixed event group. So return 1 to pass validation. */
-        if (event->pmu != &pmu || event->state <= PERF_EVENT_STATE_OFF)
-                return 1;
-
-        return mipsxx_pmu_alloc_counter(cpuc, &fake_hwc) >= 0;
-}
-
 static int validate_group(struct perf_event *event)
 {
         struct perf_event *sibling, *leader = event->group_leader;
@@ -731,15 +710,15 @@ static int validate_group(struct perf_event *event)
 
         memset(&fake_cpuc, 0, sizeof(fake_cpuc));
 
-        if (!validate_event(&fake_cpuc, leader))
+        if (mipsxx_pmu_alloc_counter(&fake_cpuc, &leader->hw) < 0)
                 return -ENOSPC;
 
         list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
-                if (!validate_event(&fake_cpuc, sibling))
+                if (mipsxx_pmu_alloc_counter(&fake_cpuc, &sibling->hw) < 0)
                         return -ENOSPC;
         }
 
-        if (!validate_event(&fake_cpuc, event))
+        if (mipsxx_pmu_alloc_counter(&fake_cpuc, &event->hw) < 0)
                 return -ENOSPC;
 
         return 0;
@@ -1279,13 +1258,14 @@ static int __hw_perf_event_init(struct perf_event *event)
         }
 
         err = 0;
-        if (event->group_leader != event) {
+        if (event->group_leader != event)
                 err = validate_group(event);
-                if (err)
-                        return -EINVAL;
-        }
 
         event->destroy = hw_perf_event_destroy;
+
+        if (err)
+                event->destroy(event);
+
         return err;
 }
 
@@ -1380,20 +1360,10 @@ static irqreturn_t mipsxx_pmu_handle_irq(int irq, void *dev)
 }
 
 /* 24K */
-#define IS_UNSUPPORTED_24K_EVENT(r, b)                                  \
-        ((b) == 12 || (r) == 151 || (r) == 152 || (b) == 26 ||          \
-         (b) == 27 || (r) == 28 || (r) == 158 || (b) == 31 ||           \
-         (b) == 32 || (b) == 34 || (b) == 36 || (r) == 168 ||           \
-         (r) == 172 || (b) == 47 || ((b) >= 56 && (b) <= 63) ||         \
-         ((b) >= 68 && (b) <= 127))
 #define IS_BOTH_COUNTERS_24K_EVENT(b)                                   \
         ((b) == 0 || (b) == 1 || (b) == 11)
 
 /* 34K */
-#define IS_UNSUPPORTED_34K_EVENT(r, b)                                  \
-        ((b) == 12 || (r) == 27 || (r) == 158 || (b) == 36 ||           \
-         (b) == 38 || (r) == 175 || ((b) >= 56 && (b) <= 63) ||         \
-         ((b) >= 68 && (b) <= 127))
 #define IS_BOTH_COUNTERS_34K_EVENT(b)                                   \
         ((b) == 0 || (b) == 1 || (b) == 11)
 #ifdef CONFIG_MIPS_MT_SMP
@@ -1406,20 +1376,10 @@ static irqreturn_t mipsxx_pmu_handle_irq(int irq, void *dev)
 #endif
 
 /* 74K */
-#define IS_UNSUPPORTED_74K_EVENT(r, b)                                  \
-        ((r) == 5 || ((r) >= 135 && (r) <= 137) ||                      \
-         ((b) >= 10 && (b) <= 12) || (b) == 22 || (b) == 27 ||          \
-         (b) == 33 || (b) == 34 || ((b) >= 47 && (b) <= 49) ||          \
-         (r) == 178 || (b) == 55 || (b) == 57 || (b) == 60 ||           \
-         (b) == 61 || (r) == 62 || (r) == 191 ||                        \
-         ((b) >= 64 && (b) <= 127))
 #define IS_BOTH_COUNTERS_74K_EVENT(b)                                   \
         ((b) == 0 || (b) == 1)
 
 /* 1004K */
-#define IS_UNSUPPORTED_1004K_EVENT(r, b)                                \
-        ((b) == 12 || (r) == 27 || (r) == 158 || (b) == 38 ||           \
-         (r) == 175 || (b) == 63 || ((b) >= 68 && (b) <= 127))
 #define IS_BOTH_COUNTERS_1004K_EVENT(b)                                 \
         ((b) == 0 || (b) == 1 || (b) == 11)
 #ifdef CONFIG_MIPS_MT_SMP
@@ -1445,11 +1405,10 @@ static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config)
         unsigned int raw_id = config & 0xff;
         unsigned int base_id = raw_id & 0x7f;
 
+        raw_event.event_id = base_id;
+
         switch (current_cpu_type()) {
         case CPU_24K:
-                if (IS_UNSUPPORTED_24K_EVENT(raw_id, base_id))
-                        return ERR_PTR(-EOPNOTSUPP);
-                raw_event.event_id = base_id;
                 if (IS_BOTH_COUNTERS_24K_EVENT(base_id))
                         raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
                 else
@@ -1464,9 +1423,6 @@ static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config)
 #endif
                 break;
         case CPU_34K:
-                if (IS_UNSUPPORTED_34K_EVENT(raw_id, base_id))
-                        return ERR_PTR(-EOPNOTSUPP);
-                raw_event.event_id = base_id;
                 if (IS_BOTH_COUNTERS_34K_EVENT(base_id))
                         raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
                 else
@@ -1482,9 +1438,6 @@ static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config)
 #endif
                 break;
         case CPU_74K:
-                if (IS_UNSUPPORTED_74K_EVENT(raw_id, base_id))
-                        return ERR_PTR(-EOPNOTSUPP);
-                raw_event.event_id = base_id;
                 if (IS_BOTH_COUNTERS_74K_EVENT(base_id))
                         raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
                 else
@@ -1495,9 +1448,6 @@ static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config)
 #endif
                 break;
         case CPU_1004K:
-                if (IS_UNSUPPORTED_1004K_EVENT(raw_id, base_id))
-                        return ERR_PTR(-EOPNOTSUPP);
-                raw_event.event_id = base_id;
                 if (IS_BOTH_COUNTERS_1004K_EVENT(base_id))
                         raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
                 else
diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c
new file mode 100644
index 00000000000..58fe71afd87
--- /dev/null
+++ b/arch/mips/kernel/smp-bmips.c
@@ -0,0 +1,458 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2011 by Kevin Cernekee (cernekee@gmail.com)
+ *
+ * SMP support for BMIPS
+ */
+
+#include <linux/version.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <linux/delay.h>
+#include <linux/smp.h>
+#include <linux/interrupt.h>
+#include <linux/spinlock.h>
+#include <linux/init.h>
+#include <linux/cpu.h>
+#include <linux/cpumask.h>
+#include <linux/reboot.h>
+#include <linux/io.h>
+#include <linux/compiler.h>
+#include <linux/linkage.h>
+#include <linux/bug.h>
+#include <linux/kernel.h>
+
+#include <asm/time.h>
+#include <asm/pgtable.h>
+#include <asm/processor.h>
+#include <asm/system.h>
+#include <asm/bootinfo.h>
+#include <asm/pmon.h>
+#include <asm/cacheflush.h>
+#include <asm/tlbflush.h>
+#include <asm/mipsregs.h>
+#include <asm/bmips.h>
+#include <asm/traps.h>
+#include <asm/barrier.h>
+
+static int __maybe_unused max_cpus = 1;
+
+/* these may be configured by the platform code */
+int bmips_smp_enabled = 1;
+int bmips_cpu_offset;
+cpumask_t bmips_booted_mask;
+
+#ifdef CONFIG_SMP
+
+/* initial $sp, $gp - used by arch/mips/kernel/bmips_vec.S */
+unsigned long bmips_smp_boot_sp;
+unsigned long bmips_smp_boot_gp;
+
+static void bmips_send_ipi_single(int cpu, unsigned int action);
+static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id);
+
+/* SW interrupts 0,1 are used for interprocessor signaling */
+#define IPI0_IRQ                        (MIPS_CPU_IRQ_BASE + 0)
+#define IPI1_IRQ                        (MIPS_CPU_IRQ_BASE + 1)
+
+#define CPUNUM(cpu, shift)              (((cpu) + bmips_cpu_offset) << (shift))
+#define ACTION_CLR_IPI(cpu, ipi)        (0x2000 | CPUNUM(cpu, 9) | ((ipi) << 8))
+#define ACTION_SET_IPI(cpu, ipi)        (0x3000 | CPUNUM(cpu, 9) | ((ipi) << 8))
+#define ACTION_BOOT_THREAD(cpu)         (0x08 | CPUNUM(cpu, 0))
+
+static void __init bmips_smp_setup(void)
+{
+        int i;
+
+#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
+        /* arbitration priority */
+        clear_c0_brcm_cmt_ctrl(0x30);
+
+        /* NBK and weak order flags */
+        set_c0_brcm_config_0(0x30000);
+
+        /*
+         * MIPS interrupts 0,1 (SW INT 0,1) cross over to the other thread
+         * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output
+         * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output
+         */
+        change_c0_brcm_cmt_intr(0xf8018000,
+                (0x02 << 27) | (0x03 << 15));
+
+        /* single core, 2 threads (2 pipelines) */
+        max_cpus = 2;
+#elif defined(CONFIG_CPU_BMIPS5000)
+        /* enable raceless SW interrupts */
+        set_c0_brcm_config(0x03 << 22);
+
+        /* route HW interrupt 0 to CPU0, HW interrupt 1 to CPU1 */
+        change_c0_brcm_mode(0x1f << 27, 0x02 << 27);
+
+        /* N cores, 2 threads per core */
+        max_cpus = (((read_c0_brcm_config() >> 6) & 0x03) + 1) << 1;
+
+        /* clear any pending SW interrupts */
+        for (i = 0; i < max_cpus; i++) {
+                write_c0_brcm_action(ACTION_CLR_IPI(i, 0));
+                write_c0_brcm_action(ACTION_CLR_IPI(i, 1));
+        }
+#endif
+
+        if (!bmips_smp_enabled)
+                max_cpus = 1;
+
+        /* this can be overridden by the BSP */
+        if (!board_ebase_setup)
+                board_ebase_setup = &bmips_ebase_setup;
+
+        for (i = 0; i < max_cpus; i++) {
+                __cpu_number_map[i] = 1;
+                __cpu_logical_map[i] = 1;
+                set_cpu_possible(i, 1);
+                set_cpu_present(i, 1);
+        }
+}
+
+/*
+ * IPI IRQ setup - runs on CPU0
+ */
+static void bmips_prepare_cpus(unsigned int max_cpus)
+{
+        if (request_irq(IPI0_IRQ, bmips_ipi_interrupt, IRQF_PERCPU,
+                        "smp_ipi0", NULL))
+                panic("Can't request IPI0 interrupt\n");
+        if (request_irq(IPI1_IRQ, bmips_ipi_interrupt, IRQF_PERCPU,
+                        "smp_ipi1", NULL))
+                panic("Can't request IPI1 interrupt\n");
+}
+
+/*
+ * Tell the hardware to boot CPUx - runs on CPU0
+ */
+static void bmips_boot_secondary(int cpu, struct task_struct *idle)
+{
+        bmips_smp_boot_sp = __KSTK_TOS(idle);
+        bmips_smp_boot_gp = (unsigned long)task_thread_info(idle);
+        mb();
+
+        /*
+         * Initial boot sequence for secondary CPU:
+         *   bmips_reset_nmi_vec @ a000_0000 ->
+         *   bmips_smp_entry ->
+         *   plat_wired_tlb_setup (cached function call; optional) ->
+         *   start_secondary (cached jump)
+         *
+         * Warm restart sequence:
+         *   play_dead WAIT loop ->
+         *   bmips_smp_int_vec @ BMIPS_WARM_RESTART_VEC ->
+         *   eret to play_dead ->
+         *   bmips_secondary_reentry ->
+         *   start_secondary
+         */
+
+        pr_info("SMP: Booting CPU%d...\n", cpu);
+
+        if (cpumask_test_cpu(cpu, &bmips_booted_mask))
+                bmips_send_ipi_single(cpu, 0);
+        else {
+#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
+                set_c0_brcm_cmt_ctrl(0x01);
+#elif defined(CONFIG_CPU_BMIPS5000)
+                if (cpu & 0x01)
+                        write_c0_brcm_action(ACTION_BOOT_THREAD(cpu));
+                else {
+                        /*
+                         * core N thread 0 was already booted; just
+                         * pulse the NMI line
+                         */
+                        bmips_write_zscm_reg(0x210, 0xc0000000);
+                        udelay(10);
+                        bmips_write_zscm_reg(0x210, 0x00);
+                }
+#endif
+                cpumask_set_cpu(cpu, &bmips_booted_mask);
+        }
+}
+
+/*
+ * Early setup - runs on secondary CPU after cache probe
+ */
+static void bmips_init_secondary(void)
+{
+        /* move NMI vector to kseg0, in case XKS01 is enabled */
+
+#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
+        void __iomem *cbr = BMIPS_GET_CBR();
+        unsigned long old_vec;
+
+        old_vec = __raw_readl(cbr + BMIPS_RELO_VECTOR_CONTROL_1);
+        __raw_writel(old_vec & ~0x20000000, cbr + BMIPS_RELO_VECTOR_CONTROL_1);
+
+        clear_c0_cause(smp_processor_id() ? C_SW1 : C_SW0);
+#elif defined(CONFIG_CPU_BMIPS5000)
+        write_c0_brcm_bootvec(read_c0_brcm_bootvec() &
+                (smp_processor_id() & 0x01 ? ~0x20000000 : ~0x2000));
+
+        write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0));
+#endif
+
+        /* make sure there won't be a timer interrupt for a little while */
+        write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
+
+        irq_enable_hazard();
+        set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ1 | IE_IRQ5 | ST0_IE);
+        irq_enable_hazard();
+}
+
+/*
+ * Late setup - runs on secondary CPU before entering the idle loop
+ */
+static void bmips_smp_finish(void)
+{
+        pr_info("SMP: CPU%d is running\n", smp_processor_id());
+}
+
+/*
+ * Runs on CPU0 after all CPUs have been booted
+ */
+static void bmips_cpus_done(void)
+{
+}
+
+#if defined(CONFIG_CPU_BMIPS5000)
+
+/*
+ * BMIPS5000 raceless IPIs
+ *
+ * Each CPU has two inbound SW IRQs which are independent of all other CPUs.
+ * IPI0 is used for SMP_RESCHEDULE_YOURSELF
+ * IPI1 is used for SMP_CALL_FUNCTION
+ */
+
+static void bmips_send_ipi_single(int cpu, unsigned int action)
+{
+        write_c0_brcm_action(ACTION_SET_IPI(cpu, action == SMP_CALL_FUNCTION));
+}
+
+static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id)
+{
+        int action = irq - IPI0_IRQ;
+
+        write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), action));
+
+        if (action == 0)
+                scheduler_ipi();
+        else
+                smp_call_function_interrupt();
+
+        return IRQ_HANDLED;
+}
+
+#else
+
+/*
+ * BMIPS43xx racey IPIs
+ *
+ * We use one inbound SW IRQ for each CPU.
+ *
+ * A spinlock must be held in order to keep CPUx from accidentally clearing
+ * an incoming IPI when it writes CP0 CAUSE to raise an IPI on CPUy.  The
+ * same spinlock is used to protect the action masks.
+ */
+
+static DEFINE_SPINLOCK(ipi_lock);
+static DEFINE_PER_CPU(int, ipi_action_mask);
+
+static void bmips_send_ipi_single(int cpu, unsigned int action)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&ipi_lock, flags);
+        set_c0_cause(cpu ? C_SW1 : C_SW0);
+        per_cpu(ipi_action_mask, cpu) |= action;
+        irq_enable_hazard();
+        spin_unlock_irqrestore(&ipi_lock, flags);
+}
+
+static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id)
+{
+        unsigned long flags;
+        int action, cpu = irq - IPI0_IRQ;
+
+        spin_lock_irqsave(&ipi_lock, flags);
+        action = __get_cpu_var(ipi_action_mask);
+        per_cpu(ipi_action_mask, cpu) = 0;
+        clear_c0_cause(cpu ? C_SW1 : C_SW0);
+        spin_unlock_irqrestore(&ipi_lock, flags);
+
+        if (action & SMP_RESCHEDULE_YOURSELF)
+                scheduler_ipi();
+        if (action & SMP_CALL_FUNCTION)
+                smp_call_function_interrupt();
+
+        return IRQ_HANDLED;
+}
+
+#endif /* BMIPS type */
+
+static void bmips_send_ipi_mask(const struct cpumask *mask,
+        unsigned int action)
+{
+        unsigned int i;
+
+        for_each_cpu(i, mask)
+                bmips_send_ipi_single(i, action);
+}
+
+#ifdef CONFIG_HOTPLUG_CPU
+
+static int bmips_cpu_disable(void)
+{
+        unsigned int cpu = smp_processor_id();
+
+        if (cpu == 0)
+                return -EBUSY;
+
+        pr_info("SMP: CPU%d is offline\n", cpu);
+
+        cpu_clear(cpu, cpu_online_map);
+        cpu_clear(cpu, cpu_callin_map);
+
+        local_flush_tlb_all();
+        local_flush_icache_range(0, ~0);
+
+        return 0;
+}
+
+static void bmips_cpu_die(unsigned int cpu)
+{
+}
+
+void __ref play_dead(void)
+{
+        idle_task_exit();
+
+        /* flush data cache */
+        _dma_cache_wback_inv(0, ~0);
+
+        /*
+         * Wakeup is on SW0 or SW1; disable everything else
+         * Use BEV !IV (BMIPS_WARM_RESTART_VEC) to avoid the regular Linux
+         * IRQ handlers; this clears ST0_IE and returns immediately.
+         */
+        clear_c0_cause(CAUSEF_IV | C_SW0 | C_SW1);
+        change_c0_status(IE_IRQ5 | IE_IRQ1 | IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV,
+                IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV);
+        irq_disable_hazard();
+
+        /*
+         * wait for SW interrupt from bmips_boot_secondary(), then jump
+         * back to start_secondary()
+         */
+        __asm__ __volatile__(
+        "       wait\n"
+        "       j       bmips_secondary_reentry\n"
+        : : : "memory");
+}
+
+#endif /* CONFIG_HOTPLUG_CPU */
+
+struct plat_smp_ops bmips_smp_ops = {
+        .smp_setup              = bmips_smp_setup,
+        .prepare_cpus           = bmips_prepare_cpus,
+        .boot_secondary         = bmips_boot_secondary,
+        .smp_finish             = bmips_smp_finish,
+        .init_secondary         = bmips_init_secondary,
+        .cpus_done              = bmips_cpus_done,
+        .send_ipi_single        = bmips_send_ipi_single,
+        .send_ipi_mask          = bmips_send_ipi_mask,
+#ifdef CONFIG_HOTPLUG_CPU
+        .cpu_disable            = bmips_cpu_disable,
+        .cpu_die                = bmips_cpu_die,
+#endif
+};
+
+#endif /* CONFIG_SMP */
+
+/***********************************************************************
+ * BMIPS vector relocation
+ * This is primarily used for SMP boot, but it is applicable to some
+ * UP BMIPS systems as well.
+ ***********************************************************************/
+
+static void __cpuinit bmips_wr_vec(unsigned long dst, char *start, char *end)
+{
+        memcpy((void *)dst, start, end - start);
+        dma_cache_wback((unsigned long)start, end - start);
+        local_flush_icache_range(dst, dst + (end - start));
+        instruction_hazard();
+}
+
+static inline void __cpuinit bmips_nmi_handler_setup(void)
+{
+        bmips_wr_vec(BMIPS_NMI_RESET_VEC, &bmips_reset_nmi_vec,
+                &bmips_reset_nmi_vec_end);
+        bmips_wr_vec(BMIPS_WARM_RESTART_VEC, &bmips_smp_int_vec,
+                &bmips_smp_int_vec_end);
+}
+
+void __cpuinit bmips_ebase_setup(void)
+{
+        unsigned long new_ebase = ebase;
+        void __iomem __maybe_unused *cbr;
+
+        BUG_ON(ebase != CKSEG0);
+
+#if defined(CONFIG_CPU_BMIPS4350)
+        /*
+         * BMIPS4350 cannot relocate the normal vectors, but it
+         * can relocate the BEV=1 vectors.  So CPU1 starts up at
+         * the relocated BEV=1, IV=0 general exception vector @
+         * 0xa000_0380.
+         *
+         * set_uncached_handler() is used here because:
+         *  - CPU1 will run this from uncached space
+         *  - None of the cacheflush functions are set up yet
+         */
+        set_uncached_handler(BMIPS_WARM_RESTART_VEC - CKSEG0,
+                &bmips_smp_int_vec, 0x80);
+        __sync();
+        return;
+#elif defined(CONFIG_CPU_BMIPS4380)
+        /*
+         * 0x8000_0000: reset/NMI (initially in kseg1)
+         * 0x8000_0400: normal vectors
+         */
+        new_ebase = 0x80000400;
+        cbr = BMIPS_GET_CBR();
+        __raw_writel(0x80080800, cbr + BMIPS_RELO_VECTOR_CONTROL_0);
+        __raw_writel(0xa0080800, cbr + BMIPS_RELO_VECTOR_CONTROL_1);
+#elif defined(CONFIG_CPU_BMIPS5000)
+        /*
+         * 0x8000_0000: reset/NMI (initially in kseg1)
+         * 0x8000_1000: normal vectors
+         */
+        new_ebase = 0x80001000;
+        write_c0_brcm_bootvec(0xa0088008);
+        write_c0_ebase(new_ebase);
+        if (max_cpus > 2)
+                bmips_write_zscm_reg(0xa0, 0xa008a008);
+#else
+        return;
+#endif
+        board_nmi_handler_setup = &bmips_nmi_handler_setup;
+        ebase = new_ebase;
+}
+
+asmlinkage void __weak plat_wired_tlb_setup(void)
+{
+        /*
+         * Called when starting/restarting a secondary CPU.
+         * Kernel stacks and other important data might only be accessible
+         * once the wired entries are present.
+         */
+}
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 363c4764b81..48240fd8c29 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -91,6 +91,7 @@ int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
 void (*board_nmi_handler_setup)(void);
 void (*board_ejtag_handler_setup)(void);
 void (*board_bind_eic_interrupt)(int irq, int regset);
+void (*board_ebase_setup)(void);
 
 
 static void show_raw_backtrace(unsigned long reg29)
@@ -1339,9 +1340,18 @@ void ejtag_exception_handler(struct pt_regs *regs)
 
 /*
  * NMI exception handler.
+ * No lock; only written during early bootup by CPU 0.
  */
+static RAW_NOTIFIER_HEAD(nmi_chain);
+
+int register_nmi_notifier(struct notifier_block *nb)
+{
+        return raw_notifier_chain_register(&nmi_chain, nb);
+}
+
 NORET_TYPE void ATTRIB_NORET nmi_exception_handler(struct pt_regs *regs)
 {
+        raw_notifier_call_chain(&nmi_chain, 0, regs);
         bust_spinlocks(1);
         printk("NMI taken!!!!\n");
         die("NMI", regs);
@@ -1682,6 +1692,8 @@ void __init trap_init(void)
                         ebase += (read_c0_ebase() & 0x3ffff000);
         }
 
+        if (board_ebase_setup)
+                board_ebase_setup();
         per_cpu_trap_init();
 
         /*
diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile
index b2cad4fd5fc..2a7c74fc15f 100644
--- a/arch/mips/lib/Makefile
+++ b/arch/mips/lib/Makefile
@@ -29,6 +29,7 @@ obj-$(CONFIG_CPU_TX49XX)	+= dump_tlb.o
 obj-$(CONFIG_CPU_VR41XX)        += dump_tlb.o
 obj-$(CONFIG_CPU_CAVIUM_OCTEON) += dump_tlb.o
 obj-$(CONFIG_CPU_XLR)           += dump_tlb.o
+obj-$(CONFIG_CPU_XLP)           += dump_tlb.o
 
 # libgcc-style stuff needed in the kernel
 obj-y += ashldi3.o ashrdi3.o cmpdi2.o lshrdi3.o ucmpdi2.o
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index dbf2f93a509..a03bf00a1a9 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -245,7 +245,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
                  */
                 emulpc = xcp->cp0_epc + 4;      /* Snapshot emulation target */
 
-                if (__compute_return_epc(xcp)) {
+                if (__compute_return_epc(xcp) < 0) {
 #ifdef CP1DBG
                         printk("failed to emulate branch at %p\n",
                                 (void *) (xcp->cp0_epc));
diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile
index 3ca2a065cf7..4aa20280613 100644
--- a/arch/mips/mm/Makefile
+++ b/arch/mips/mm/Makefile
@@ -31,6 +31,7 @@ obj-$(CONFIG_CPU_TX49XX)	+= c-r4k.o cex-gen.o tlb-r4k.o
 obj-$(CONFIG_CPU_VR41XX)        += c-r4k.o cex-gen.o tlb-r4k.o
 obj-$(CONFIG_CPU_CAVIUM_OCTEON) += c-octeon.o cex-oct.o tlb-r4k.o
 obj-$(CONFIG_CPU_XLR)           += c-r4k.o tlb-r4k.o cex-gen.o
+obj-$(CONFIG_CPU_XLP)           += c-r4k.o tlb-r4k.o cex-gen.o
 
 obj-$(CONFIG_IP22_CPU_SCACHE)   += sc-ip22.o
 obj-$(CONFIG_R5000_CPU_SCACHE)  += sc-r5k.o
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index a79fe9aa772..4f9eb0b2303 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1235,6 +1235,9 @@ static void __cpuinit setup_scache(void)
                 loongson2_sc_init();
                 return;
 #endif
+        case CPU_XLP:
+                /* don't need to worry about L2, fully coherent */
+                return;
 
         default:
                 if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
diff --git a/arch/mips/netlogic/Kconfig b/arch/mips/netlogic/Kconfig
index a5ca743613f..75bec44b585 100644
--- a/arch/mips/netlogic/Kconfig
+++ b/arch/mips/netlogic/Kconfig
@@ -1,5 +1,2 @@
 config NLM_COMMON
         bool
-
-config NLM_XLR
-        bool
diff --git a/arch/mips/netlogic/Makefile b/arch/mips/netlogic/Makefile
new file mode 100644
index 00000000000..36d169b2ca6
--- /dev/null
+++ b/arch/mips/netlogic/Makefile
@@ -0,0 +1,3 @@
+obj-$(CONFIG_NLM_COMMON)        +=      common/
+obj-$(CONFIG_CPU_XLR)           +=      xlr/
+obj-$(CONFIG_CPU_XLP)           +=      xlp/
diff --git a/arch/mips/netlogic/Platform b/arch/mips/netlogic/Platform
index b648b487fd6..cdfc9abbbb7 100644
--- a/arch/mips/netlogic/Platform
+++ b/arch/mips/netlogic/Platform
@@ -1,16 +1,17 @@
 #
 # NETLOGIC includes
 #
-cflags-$(CONFIG_NLM_COMMON)  += -I$(srctree)/arch/mips/include/asm/mach-netlogic
-cflags-$(CONFIG_NLM_COMMON)  += -I$(srctree)/arch/mips/include/asm/netlogic
+cflags-$(CONFIG_NLM_COMMON)     += -I$(srctree)/arch/mips/include/asm/mach-netlogic
+cflags-$(CONFIG_NLM_COMMON)     += -I$(srctree)/arch/mips/include/asm/netlogic
 
 #
 # use mips64 if xlr is not available
 #
-cflags-$(CONFIG_NLM_XLR)        += $(call cc-option,-march=xlr,-march=mips64)
+cflags-$(CONFIG_CPU_XLR)        += $(call cc-option,-march=xlr,-march=mips64)
+cflags-$(CONFIG_CPU_XLP)        += $(call cc-option,-march=xlp,-march=mips64r2)
 
 #
-# NETLOGIC XLR/XLS SoC, Simulator and boards
+# NETLOGIC processor support
 #
-core-$(CONFIG_NLM_XLR)        += arch/mips/netlogic/xlr/
-load-$(CONFIG_NLM_XLR_BOARD)  += 0xffffffff84000000
+platform-$(CONFIG_NLM_COMMON)   += netlogic/
+load-$(CONFIG_NLM_COMMON)       += 0xffffffff80100000
diff --git a/arch/mips/netlogic/common/Makefile b/arch/mips/netlogic/common/Makefile
new file mode 100644
index 00000000000..291372a086f
--- /dev/null
+++ b/arch/mips/netlogic/common/Makefile
@@ -0,0 +1,3 @@
+obj-y                           += irq.o time.o
+obj-$(CONFIG_SMP)               += smp.o smpboot.o
+obj-$(CONFIG_EARLY_PRINTK)      += earlycons.o
diff --git a/arch/mips/netlogic/common/earlycons.c b/arch/mips/netlogic/common/earlycons.c
new file mode 100644
index 00000000000..f193f7b3bd8
--- /dev/null
+++ b/arch/mips/netlogic/common/earlycons.c
@@ -0,0 +1,60 @@
+/*
+ * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
+ * reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the NetLogic
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <linux/types.h>
+#include <linux/serial_reg.h>
+
+#include <asm/mipsregs.h>
+#include <asm/netlogic/haldefs.h>
+
+#if defined(CONFIG_CPU_XLP)
+#include <asm/netlogic/xlp-hal/iomap.h>
+#include <asm/netlogic/xlp-hal/uart.h>
+#elif defined(CONFIG_CPU_XLR)
+#include <asm/netlogic/xlr/iomap.h>
+#endif
+
+void prom_putchar(char c)
+{
+        uint64_t uartbase;
+
+#if defined(CONFIG_CPU_XLP)
+        uartbase = nlm_get_uart_regbase(0, 0);
+#elif defined(CONFIG_CPU_XLR)
+        uartbase = nlm_mmio_base(NETLOGIC_IO_UART_0_OFFSET);
+#endif
+        while (nlm_read_reg(uartbase, UART_LSR) == 0)
+                ;
+        nlm_write_reg(uartbase, UART_TX, c);
+}
diff --git a/arch/mips/netlogic/common/irq.c b/arch/mips/netlogic/common/irq.c
new file mode 100644
index 00000000000..49a4f6cf71e
--- /dev/null
+++ b/arch/mips/netlogic/common/irq.c
@@ -0,0 +1,238 @@
+/*
+ * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
+ * reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the NetLogic
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/linkage.h>
+#include <linux/interrupt.h>
+#include <linux/spinlock.h>
+#include <linux/mm.h>
+#include <linux/slab.h>
+#include <linux/irq.h>
+
+#include <asm/errno.h>
+#include <asm/signal.h>
+#include <asm/system.h>
+#include <asm/ptrace.h>
+#include <asm/mipsregs.h>
+#include <asm/thread_info.h>
+
+#include <asm/netlogic/mips-extns.h>
+#include <asm/netlogic/interrupt.h>
+#include <asm/netlogic/haldefs.h>
+#include <asm/netlogic/common.h>
+
+#if defined(CONFIG_CPU_XLP)
+#include <asm/netlogic/xlp-hal/iomap.h>
+#include <asm/netlogic/xlp-hal/xlp.h>
+#include <asm/netlogic/xlp-hal/pic.h>
+#elif defined(CONFIG_CPU_XLR)
+#include <asm/netlogic/xlr/iomap.h>
+#include <asm/netlogic/xlr/pic.h>
+#else
+#error "Unknown CPU"
+#endif
+/*
+ * These are the routines that handle all the low level interrupt stuff.
+ * Actions handled here are: initialization of the interrupt map, requesting of
+ * interrupt lines by handlers, dispatching if interrupts to handlers, probing
+ * for interrupt lines
+ */
+
+/* Globals */
+static uint64_t nlm_irq_mask;
+static DEFINE_SPINLOCK(nlm_pic_lock);
+
+static void xlp_pic_enable(struct irq_data *d)
+{
+        unsigned long flags;
+        int irt;
+
+        irt = nlm_irq_to_irt(d->irq);
+        if (irt == -1)
+                return;
+        spin_lock_irqsave(&nlm_pic_lock, flags);
+        nlm_pic_enable_irt(nlm_pic_base, irt);
+        spin_unlock_irqrestore(&nlm_pic_lock, flags);
+}
+
+static void xlp_pic_disable(struct irq_data *d)
+{
+        unsigned long flags;
+        int irt;
+
+        irt = nlm_irq_to_irt(d->irq);
+        if (irt == -1)
+                return;
+        spin_lock_irqsave(&nlm_pic_lock, flags);
+        nlm_pic_disable_irt(nlm_pic_base, irt);
+        spin_unlock_irqrestore(&nlm_pic_lock, flags);
+}
+
+static void xlp_pic_mask_ack(struct irq_data *d)
+{
+        uint64_t mask = 1ull << d->irq;
+
+        write_c0_eirr(mask);            /* ack by writing EIRR */
+}
+
+static void xlp_pic_unmask(struct irq_data *d)
+{
+        void *hd = irq_data_get_irq_handler_data(d);
+        int irt;
+
+        irt = nlm_irq_to_irt(d->irq);
+        if (irt == -1)
+                return;
+
+        if (hd) {
+                void (*extra_ack)(void *) = hd;
+                extra_ack(d);
+        }
+        /* Ack is a single write, no need to lock */
+        nlm_pic_ack(nlm_pic_base, irt);
+}
+
+static struct irq_chip xlp_pic = {
+        .name           = "XLP-PIC",
+        .irq_enable     = xlp_pic_enable,
+        .irq_disable    = xlp_pic_disable,
+        .irq_mask_ack   = xlp_pic_mask_ack,
+        .irq_unmask     = xlp_pic_unmask,
+};
+
+static void cpuintr_disable(struct irq_data *d)
+{
+        uint64_t eimr;
+        uint64_t mask = 1ull << d->irq;
+
+        eimr = read_c0_eimr();
+        write_c0_eimr(eimr & ~mask);
+}
+
+static void cpuintr_enable(struct irq_data *d)
+{
+        uint64_t eimr;
+        uint64_t mask = 1ull << d->irq;
+
+        eimr = read_c0_eimr();
+        write_c0_eimr(eimr | mask);
+}
+
+static void cpuintr_ack(struct irq_data *d)
+{
+        uint64_t mask = 1ull << d->irq;
+
+        write_c0_eirr(mask);
+}
+
+static void cpuintr_nop(struct irq_data *d)
+{
+        WARN(d->irq >= PIC_IRQ_BASE, "Bad irq %d", d->irq);
+}
+
+/*
+ * Chip definition for CPU originated interrupts(timer, msg) and
+ * IPIs
+ */
+struct irq_chip nlm_cpu_intr = {
+        .name           = "XLP-CPU-INTR",
+        .irq_enable     = cpuintr_enable,
+        .irq_disable    = cpuintr_disable,
+        .irq_mask       = cpuintr_nop,
+        .irq_ack        = cpuintr_nop,
+        .irq_eoi        = cpuintr_ack,
+};
+
+void __init init_nlm_common_irqs(void)
+{
+        int i, irq, irt;
+
+        for (i = 0; i < PIC_IRT_FIRST_IRQ; i++)
+                irq_set_chip_and_handler(i, &nlm_cpu_intr, handle_percpu_irq);
+
+        for (i = PIC_IRT_FIRST_IRQ; i <= PIC_IRT_LAST_IRQ ; i++)
+                irq_set_chip_and_handler(i, &xlp_pic, handle_level_irq);
+
+#ifdef CONFIG_SMP
+        irq_set_chip_and_handler(IRQ_IPI_SMP_FUNCTION, &nlm_cpu_intr,
+                         nlm_smp_function_ipi_handler);
+        irq_set_chip_and_handler(IRQ_IPI_SMP_RESCHEDULE, &nlm_cpu_intr,
+                         nlm_smp_resched_ipi_handler);
+        nlm_irq_mask |=
+            ((1ULL << IRQ_IPI_SMP_FUNCTION) | (1ULL << IRQ_IPI_SMP_RESCHEDULE));
+#endif
+
+        for (irq = PIC_IRT_FIRST_IRQ; irq <= PIC_IRT_LAST_IRQ; irq++) {
+                irt = nlm_irq_to_irt(irq);
+                if (irt == -1)
+                        continue;
+                nlm_irq_mask |= (1ULL << irq);
+                nlm_pic_init_irt(nlm_pic_base, irt, irq, 0);
+        }
+
+        nlm_irq_mask |= (1ULL << IRQ_TIMER);
+}
+
+void __init arch_init_irq(void)
+{
+        /* Initialize the irq descriptors */
+        init_nlm_common_irqs();
+
+        write_c0_eimr(nlm_irq_mask);
+}
+
+void __cpuinit nlm_smp_irq_init(void)
+{
+        /* set interrupt mask for non-zero cpus */
+        write_c0_eimr(nlm_irq_mask);
+}
+
+asmlinkage void plat_irq_dispatch(void)
+{
+        uint64_t eirr;
+        int i;
+
+        eirr = read_c0_eirr() & read_c0_eimr();
+        if (eirr & (1 << IRQ_TIMER)) {
+                do_IRQ(IRQ_TIMER);
+                return;
+        }
+
+        i = __ilog2_u64(eirr);
+        if (i == -1)
+                return;
+
+        do_IRQ(i);
+}
diff --git a/arch/mips/netlogic/xlr/smp.c b/arch/mips/netlogic/common/smp.c
index 080284ded50..db17f49886c 100644
--- a/arch/mips/netlogic/xlr/smp.c
+++ b/arch/mips/netlogic/common/smp.c
@@ -42,31 +42,29 @@
 
 #include <asm/netlogic/interrupt.h>
 #include <asm/netlogic/mips-extns.h>
-
+#include <asm/netlogic/haldefs.h>
+#include <asm/netlogic/common.h>
+
+#if defined(CONFIG_CPU_XLP)
+#include <asm/netlogic/xlp-hal/iomap.h>
+#include <asm/netlogic/xlp-hal/xlp.h>
+#include <asm/netlogic/xlp-hal/pic.h>
+#elif defined(CONFIG_CPU_XLR)
 #include <asm/netlogic/xlr/iomap.h>
 #include <asm/netlogic/xlr/pic.h>
 #include <asm/netlogic/xlr/xlr.h>
+#else
+#error "Unknown CPU"
+#endif
 
-void core_send_ipi(int logical_cpu, unsigned int action)
+void nlm_send_ipi_single(int logical_cpu, unsigned int action)
 {
         int cpu = cpu_logical_map(logical_cpu);
-        u32 tid = cpu & 0x3;
-        u32 pid = (cpu >> 2) & 0x07;
-        u32 ipi = (tid << 16) | (pid << 20);
 
         if (action & SMP_CALL_FUNCTION)
-                ipi |= IRQ_IPI_SMP_FUNCTION;
-        else if (action & SMP_RESCHEDULE_YOURSELF)
-                ipi |= IRQ_IPI_SMP_RESCHEDULE;
-        else
-                return;
-
-        pic_send_ipi(ipi);
-}
-
-void nlm_send_ipi_single(int cpu, unsigned int action)
-{
-        core_send_ipi(cpu, action);
+                nlm_pic_send_ipi(nlm_pic_base, cpu, IRQ_IPI_SMP_FUNCTION, 0);
+        if (action & SMP_RESCHEDULE_YOURSELF)
+                nlm_pic_send_ipi(nlm_pic_base, cpu, IRQ_IPI_SMP_RESCHEDULE, 0);
 }
 
 void nlm_send_ipi_mask(const struct cpumask *mask, unsigned int action)
@@ -74,29 +72,35 @@ void nlm_send_ipi_mask(const struct cpumask *mask, unsigned int action)
         int cpu;
 
         for_each_cpu(cpu, mask) {
-                core_send_ipi(cpu, action);
+                nlm_send_ipi_single(cpu, action);
         }
 }
 
 /* IRQ_IPI_SMP_FUNCTION Handler */
 void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc)
 {
+        write_c0_eirr(1ull << irq);
         smp_call_function_interrupt();
 }
 
 /* IRQ_IPI_SMP_RESCHEDULE  handler */
 void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc)
 {
+        write_c0_eirr(1ull << irq);
         scheduler_ipi();
 }
 
 /*
  * Called before going into mips code, early cpu init
  */
-void nlm_early_init_secondary(void)
+void nlm_early_init_secondary(int cpu)
 {
+        change_c0_config(CONF_CM_CMASK, 0x3);
         write_c0_ebase((uint32_t)nlm_common_ebase);
-        /* TLB partition here later */
+#ifdef CONFIG_CPU_XLP
+        if (hard_smp_processor_id() % 4 == 0)
+                xlp_mmu_init();
+#endif
 }
 
 /*
@@ -104,9 +108,16 @@ void nlm_early_init_secondary(void)
  */
 static void __cpuinit nlm_init_secondary(void)
 {
+        current_cpu_data.core = hard_smp_processor_id() / 4;
         nlm_smp_irq_init();
 }
 
+void nlm_prepare_cpus(unsigned int max_cpus)
+{
+        /* declare we are SMT capable */
+        smp_num_siblings = nlm_threads_per_core;
+}
+
 void nlm_smp_finish(void)
 {
 #ifdef notyet
@@ -123,10 +134,10 @@ void nlm_cpus_done(void)
  * Boot all other cpus in the system, initialize them, and bring them into
  * the boot function
  */
-int nlm_cpu_unblock[NR_CPUS];
 int nlm_cpu_ready[NR_CPUS];
 unsigned long nlm_next_gp;
 unsigned long nlm_next_sp;
+
 cpumask_t phys_cpu_present_map;
 
 void nlm_boot_secondary(int logical_cpu, struct task_struct *idle)
@@ -140,7 +151,7 @@ void nlm_boot_secondary(int logical_cpu, struct task_struct *idle)
 
         /* barrier */
         __sync();
-        nlm_cpu_unblock[cpu] = 1;
+        nlm_pic_send_ipi(nlm_pic_base, cpu, 1, 1);
 }
 
 void __init nlm_smp_setup(void)
@@ -159,8 +170,8 @@ void __init nlm_smp_setup(void)
         num_cpus = 1;
         for (i = 0; i < NR_CPUS; i++) {
                 /*
-                 * BSP is not set in nlm_cpu_ready array, it is only for
-                 * ASPs (goto see smpboot.S)
+                 * nlm_cpu_ready array is not set for the boot_cpu,
+                 * it is only set for ASPs (see smpboot.S)
                  */
                 if (nlm_cpu_ready[i]) {
                         cpu_set(i, phys_cpu_present_map);
@@ -176,10 +187,75 @@ void __init nlm_smp_setup(void)
                 (unsigned long)cpu_possible_map.bits[0]);
 
         pr_info("Detected %i Slave CPU(s)\n", num_cpus);
+        nlm_set_nmi_handler(nlm_boot_secondary_cpus);
 }
 
-void nlm_prepare_cpus(unsigned int max_cpus)
+static int nlm_parse_cpumask(u32 cpu_mask)
+{
+        uint32_t core0_thr_mask, core_thr_mask;
+        int threadmode, i;
+
+        core0_thr_mask = cpu_mask & 0xf;
+        switch (core0_thr_mask) {
+        case 1:
+                nlm_threads_per_core = 1;
+                threadmode = 0;
+                break;
+        case 3:
+                nlm_threads_per_core = 2;
+                threadmode = 2;
+                break;
+        case 0xf:
+                nlm_threads_per_core = 4;
+                threadmode = 3;
+                break;
+        default:
+                goto unsupp;
+        }
+
+        /* Verify other cores CPU masks */
+        nlm_coremask = 1;
+        nlm_cpumask = core0_thr_mask;
+        for (i = 1; i < 8; i++) {
+                core_thr_mask = (cpu_mask >> (i * 4)) & 0xf;
+                if (core_thr_mask) {
+                        if (core_thr_mask != core0_thr_mask)
+                                goto unsupp;
+                        nlm_coremask |= 1 << i;
+                        nlm_cpumask |= core0_thr_mask << (4 * i);
+                }
+        }
+        return threadmode;
+
+unsupp:
+        panic("Unsupported CPU mask %x\n", cpu_mask);
+        return 0;
+}
+
+int __cpuinit nlm_wakeup_secondary_cpus(u32 wakeup_mask)
 {
+        unsigned long reset_vec;
+        char *reset_data;
+        int threadmode;
+
+        /* Update reset entry point with CPU init code */
+        reset_vec = CKSEG1ADDR(RESET_VEC_PHYS);
+        memcpy((void *)reset_vec, (void *)nlm_reset_entry,
+                        (nlm_reset_entry_end - nlm_reset_entry));
+
+        /* verify the mask and setup core config variables */
+        threadmode = nlm_parse_cpumask(wakeup_mask);
+
+        /* Setup CPU init parameters */
+        reset_data = (char *)CKSEG1ADDR(RESET_DATA_PHYS);
+        *(int *)(reset_data + BOOT_THREAD_MODE) = threadmode;
+
+#ifdef CONFIG_CPU_XLP
+        xlp_wakeup_secondary_cpus();
+#else
+        xlr_wakeup_secondary_cpus();
+#endif
+        return 0;
 }
 
 struct plat_smp_ops nlm_smp_ops = {
@@ -192,29 +268,3 @@ struct plat_smp_ops nlm_smp_ops = {
         .smp_setup              = nlm_smp_setup,
         .prepare_cpus           = nlm_prepare_cpus,
 };
-
-unsigned long secondary_entry_point;
-
-int __cpuinit nlm_wakeup_secondary_cpus(u32 wakeup_mask)
-{
-        unsigned int tid, pid, ipi, i, boot_cpu;
-        void *reset_vec;
-
-        secondary_entry_point = (unsigned long)prom_pre_boot_secondary_cpus;
-        reset_vec = (void *)CKSEG1ADDR(0x1fc00000);
-        memcpy(reset_vec, nlm_boot_smp_nmi, 0x80);
-        boot_cpu = hard_smp_processor_id();
-
-        for (i = 0; i < NR_CPUS; i++) {
-                if (i == boot_cpu)
-                        continue;
-                if (wakeup_mask & (1u << i)) {
-                        tid = i & 0x3;
-                        pid = (i >> 2) & 0x7;
-                        ipi = (tid << 16) | (pid << 20) | (1 << 8);
-                        pic_send_ipi(ipi);
-                }
-        }
-
-        return 0;
-}
diff --git a/arch/mips/netlogic/common/smpboot.S b/arch/mips/netlogic/common/smpboot.S
new file mode 100644
index 00000000000..c138b1a6dec
--- /dev/null
+++ b/arch/mips/netlogic/common/smpboot.S
@@ -0,0 +1,272 @@
+/*
+ * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
+ * reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the NetLogic
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <linux/init.h>
+
+#include <asm/asm.h>
+#include <asm/asm-offsets.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/stackframe.h>
+#include <asm/asmmacro.h>
+#include <asm/addrspace.h>
+
+#include <asm/netlogic/common.h>
+
+#include <asm/netlogic/xlp-hal/iomap.h>
+#include <asm/netlogic/xlp-hal/xlp.h>
+#include <asm/netlogic/xlp-hal/sys.h>
+#include <asm/netlogic/xlp-hal/cpucontrol.h>
+
+#define CP0_EBASE       $15
+#define SYS_CPU_COHERENT_BASE(node)     CKSEG1ADDR(XLP_DEFAULT_IO_BASE) + \
+                        XLP_IO_SYS_OFFSET(node) + XLP_IO_PCI_HDRSZ + \
+                        SYS_CPU_NONCOHERENT_MODE * 4
+
+.macro __config_lsu
+        li      t0, LSU_DEFEATURE
+        mfcr    t1, t0
+
+        lui     t2, 0x4080  /* Enable Unaligned Access, L2HPE */
+        or      t1, t1, t2
+        li      t2, ~0xe    /* S1RCM */
+        and     t1, t1, t2
+        mtcr    t1, t0
+
+        li      t0, SCHED_DEFEATURE
+        lui     t1, 0x0100  /* Experimental: Disable BRU accepting ALU ops */
+        mtcr    t1, t0
+.endm
+
+/*
+ * The cores can come start when they are woken up. This is also the NMI
+ * entry, so check that first.
+ *
+ * The data corresponding to reset is stored at RESET_DATA_PHYS location,
+ * this will have the thread mask (used when core is woken up) and the
+ * current NMI handler in case we reached here for an NMI.
+ *
+ * When a core or thread is newly woken up, it loops in a 'wait'. When
+ * the CPU really needs waking up, we send an NMI to it, with the NMI
+ * handler set to prom_boot_secondary_cpus
+ */
+
+        .set    noreorder
+        .set    noat
+        .set    arch=xlr        /* for mfcr/mtcr, XLR is sufficient */
+
+FEXPORT(nlm_reset_entry)
+        dmtc0   k0, $22, 6
+        dmtc0   k1, $22, 7
+        mfc0    k0, CP0_STATUS
+        li      k1, 0x80000
+        and     k1, k0, k1
+        beqz    k1, 1f         /* go to real reset entry */
+        nop
+        li      k1, CKSEG1ADDR(RESET_DATA_PHYS)   /* NMI */
+        ld      k0, BOOT_NMI_HANDLER(k1)
+        jr      k0
+        nop
+
+1:      /* Entry point on core wakeup */
+        mfc0    t0, CP0_EBASE, 1
+        mfc0    t1, CP0_EBASE, 1
+        srl     t1, 5
+        andi    t1, 0x3                 /* t1 <- node */
+        li      t2, 0x40000
+        mul     t3, t2, t1              /* t3 = node * 0x40000 */
+        srl     t0, t0, 2
+        and     t0, t0, 0x7             /* t0 <- core */
+        li      t1, 0x1
+        sll     t0, t1, t0
+        nor     t0, t0, zero            /* t0 <- ~(1 << core) */
+        li      t2, SYS_CPU_COHERENT_BASE(0)
+        add     t2, t2, t3              /* t2 <- SYS offset for node */
+        lw      t1, 0(t2)
+        and     t1, t1, t0
+        sw      t1, 0(t2)
+
+        /* read back to ensure complete */
+        lw      t1, 0(t2)
+        sync
+
+        /* Configure LSU on Non-0 Cores. */
+        __config_lsu
+
+/*
+ * Wake up sibling threads from the initial thread in
+ * a core.
+ */
+EXPORT(nlm_boot_siblings)
+        li      t0, CKSEG1ADDR(RESET_DATA_PHYS)
+        lw      t1, BOOT_THREAD_MODE(t0)        /* t1 <- thread mode */
+        li      t0, ((CPU_BLOCKID_MAP << 8) | MAP_THREADMODE)
+        mfcr    t2, t0
+        or      t2, t2, t1
+        mtcr    t2, t0
+
+        /*
+         * The new hardware thread starts at the next instruction
+         * For all the cases other than core 0 thread 0, we will
+         * jump to the secondary wait function.
+         */
+        mfc0    v0, CP0_EBASE, 1
+        andi    v0, 0x7f                /* v0 <- node/core */
+
+#if 1
+        /* A0 errata - Write MMU_SETUP after changing thread mode register. */
+        andi    v1, v0, 0x3             /* v1 <- thread id */
+        bnez    v1, 2f
+        nop
+
+        li      t0, MMU_SETUP
+        li      t1, 0
+        mtcr    t1, t0
+        ehb
+#endif
+
+2:      beqz    v0, 4f
+        nop
+
+        /* setup status reg */
+        mfc0    t1, CP0_STATUS
+        li      t0, ST0_BEV
+        or      t1, t0
+        xor     t1, t0
+#ifdef CONFIG_64BIT
+        ori     t1, ST0_KX
+#endif
+        mtc0    t1, CP0_STATUS
+        /* mark CPU ready */
+        PTR_LA  t1, nlm_cpu_ready
+        sll     v1, v0, 2
+        PTR_ADDU t1, v1
+        li      t2, 1
+        sw      t2, 0(t1)
+        /* Wait until NMI hits */
+3:      wait
+        j       3b
+        nop
+
+        /*
+         * For the boot CPU, we have to restore registers and
+         * return
+         */
+4:      dmfc0   t0, $4, 2       /* restore SP from UserLocal */
+        li      t1, 0xfadebeef
+        dmtc0   t1, $4, 2       /* restore SP from UserLocal */
+        PTR_SUBU sp, t0, PT_SIZE
+        RESTORE_ALL
+        jr   ra
+        nop
+EXPORT(nlm_reset_entry_end)
+
+FEXPORT(xlp_boot_core0_siblings)        /* "Master" cpu starts from here */
+        __config_lsu
+        dmtc0   sp, $4, 2               /* SP saved in UserLocal */
+        SAVE_ALL
+        sync
+        /* find the location to which nlm_boot_siblings was relocated */
+        li      t0, CKSEG1ADDR(RESET_VEC_PHYS)
+        dla     t1, nlm_reset_entry
+        dla     t2, nlm_boot_siblings
+        dsubu   t2, t1
+        daddu   t2, t0
+        /* call it */
+        jr      t2
+        nop
+        /* not reached */
+
+        __CPUINIT
+NESTED(nlm_boot_secondary_cpus, 16, sp)
+        PTR_LA  t1, nlm_next_sp
+        PTR_L   sp, 0(t1)
+        PTR_LA  t1, nlm_next_gp
+        PTR_L   gp, 0(t1)
+
+        /* a0 has the processor id */
+        PTR_LA  t0, nlm_early_init_secondary
+        jalr    t0
+        nop
+
+        PTR_LA  t0, smp_bootstrap
+        jr      t0
+        nop
+END(nlm_boot_secondary_cpus)
+        __FINIT
+
+/*
+ * In case of RMIboot bootloader which is used on XLR boards, the CPUs
+ * be already woken up and waiting in bootloader code.
+ * This will get them out of the bootloader code and into linux. Needed
+ *  because the bootloader area will be taken and initialized by linux.
+ */
+        __CPUINIT
+NESTED(nlm_rmiboot_preboot, 16, sp)
+        mfc0    t0, $15, 1      # read ebase
+        andi    t0, 0x1f        # t0 has the processor_id()
+        andi    t2, t0, 0x3     # thread no
+        sll     t0, 2           # offset in cpu array
+
+        PTR_LA  t1, nlm_cpu_ready # mark CPU ready
+        PTR_ADDU t1, t0
+        li      t3, 1
+        sw      t3, 0(t1)
+
+        bnez    t2, 1f          # skip thread programming
+        nop                     # for non zero hw threads
+
+        /*
+         * MMU setup only for first thread in core
+         */
+        li      t0, 0x400
+        mfcr    t1, t0
+        li      t2, 6           # XLR thread mode mask
+        nor     t3, t2, zero
+        and     t2, t1, t2      # t2 - current thread mode
+        li      v0, CKSEG1ADDR(RESET_DATA_PHYS)
+        lw      v1, BOOT_THREAD_MODE(v0) # v1 - new thread mode
+        sll     v1, 1
+        beq     v1, t2, 1f      # same as request value
+        nop                     # nothing to do */
+
+        and     t2, t1, t3      # mask out old thread mode
+        or      t1, t2, v1      # put in new value
+        mtcr    t1, t0          # update core control
+
+1:      wait
+        j       1b
+        nop
+END(nlm_rmiboot_preboot)
+        __FINIT
diff --git a/arch/mips/netlogic/xlr/time.c b/arch/mips/netlogic/common/time.c
index 0d81b262593..bd3e498157f 100644
--- a/arch/mips/netlogic/xlr/time.c
+++ b/arch/mips/netlogic/common/time.c
@@ -36,7 +36,7 @@
 
 #include <asm/time.h>
 #include <asm/netlogic/interrupt.h>
-#include <asm/netlogic/psb-bootinfo.h>
+#include <asm/netlogic/common.h>
 
 unsigned int __cpuinit get_c0_compare_int(void)
 {
@@ -45,7 +45,7 @@ unsigned int __cpuinit get_c0_compare_int(void)
 
 void __init plat_time_init(void)
 {
-        mips_hpt_frequency = nlm_prom_info.cpu_frequency;
+        mips_hpt_frequency = nlm_get_cpu_frequency();
         pr_info("MIPS counter frequency [%ld]\n",
-                (unsigned long)mips_hpt_frequency);
+                        (unsigned long)mips_hpt_frequency);
 }
diff --git a/arch/mips/netlogic/xlp/Makefile b/arch/mips/netlogic/xlp/Makefile
new file mode 100644
index 00000000000..b93ed83474e
--- /dev/null
+++ b/arch/mips/netlogic/xlp/Makefile
@@ -0,0 +1,2 @@
+obj-y                           += setup.o platform.o nlm_hal.o
+obj-$(CONFIG_SMP)               += wakeup.o
diff --git a/arch/mips/netlogic/xlp/nlm_hal.c b/arch/mips/netlogic/xlp/nlm_hal.c
new file mode 100644
index 00000000000..9428e7125fe
--- /dev/null
+++ b/arch/mips/netlogic/xlp/nlm_hal.c
@@ -0,0 +1,111 @@
+/*
+ * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
+ * reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the NetLogic
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/mm.h>
+#include <linux/delay.h>
+
+#include <asm/mipsregs.h>
+#include <asm/time.h>
+
+#include <asm/netlogic/haldefs.h>
+#include <asm/netlogic/xlp-hal/iomap.h>
+#include <asm/netlogic/xlp-hal/xlp.h>
+#include <asm/netlogic/xlp-hal/pic.h>
+#include <asm/netlogic/xlp-hal/sys.h>
+
+/* These addresses are computed by the nlm_hal_init() */
+uint64_t nlm_io_base;
+uint64_t nlm_sys_base;
+uint64_t nlm_pic_base;
+
+/* Main initialization */
+void nlm_hal_init(void)
+{
+        nlm_io_base = CKSEG1ADDR(XLP_DEFAULT_IO_BASE);
+        nlm_sys_base = nlm_get_sys_regbase(0);  /* node 0 */
+        nlm_pic_base = nlm_get_pic_regbase(0);  /* node 0 */
+}
+
+int nlm_irq_to_irt(int irq)
+{
+        if (!PIC_IRQ_IS_IRT(irq))
+                return -1;
+
+        switch (irq) {
+        case PIC_UART_0_IRQ:
+                return PIC_IRT_UART_0_INDEX;
+        case PIC_UART_1_IRQ:
+                return PIC_IRT_UART_1_INDEX;
+        default:
+                return -1;
+        }
+}
+
+int nlm_irt_to_irq(int irt)
+{
+        switch (irt) {
+        case PIC_IRT_UART_0_INDEX:
+                return PIC_UART_0_IRQ;
+        case PIC_IRT_UART_1_INDEX:
+                return PIC_UART_1_IRQ;
+        default:
+                return -1;
+        }
+}
+
+unsigned int nlm_get_core_frequency(int core)
+{
+        unsigned int pll_divf, pll_divr, dfs_div, ext_div;
+        unsigned int rstval, dfsval, denom;
+        uint64_t num;
+
+        rstval = nlm_read_sys_reg(nlm_sys_base, SYS_POWER_ON_RESET_CFG);
+        dfsval = nlm_read_sys_reg(nlm_sys_base, SYS_CORE_DFS_DIV_VALUE);
+        pll_divf = ((rstval >> 10) & 0x7f) + 1;
+        pll_divr = ((rstval >> 8)  & 0x3) + 1;
+        ext_div  = ((rstval >> 30) & 0x3) + 1;
+        dfs_div  = ((dfsval >> (core * 4)) & 0xf) + 1;
+
+        num = 800000000ULL * pll_divf;
+        denom = 3 * pll_divr * ext_div * dfs_div;
+        do_div(num, denom);
+        return (unsigned int)num;
+}
+
+unsigned int nlm_get_cpu_frequency(void)
+{
+        return nlm_get_core_frequency(0);
+}
diff --git a/arch/mips/netlogic/xlp/platform.c b/arch/mips/netlogic/xlp/platform.c
new file mode 100644
index 00000000000..1f5e4cba891
--- /dev/null
+++ b/arch/mips/netlogic/xlp/platform.c
@@ -0,0 +1,108 @@
+/*
+ * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
+ * reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the NetLogic
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <linux/dma-mapping.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/serial.h>
+#include <linux/serial_8250.h>
+#include <linux/pci.h>
+#include <linux/serial_reg.h>
+#include <linux/spinlock.h>
+
+#include <asm/time.h>
+#include <asm/addrspace.h>
+#include <asm/netlogic/haldefs.h>
+#include <asm/netlogic/xlp-hal/iomap.h>
+#include <asm/netlogic/xlp-hal/xlp.h>
+#include <asm/netlogic/xlp-hal/pic.h>
+#include <asm/netlogic/xlp-hal/uart.h>
+
+static unsigned int nlm_xlp_uart_in(struct uart_port *p, int offset)
+{
+         return nlm_read_reg(p->iobase, offset);
+}
+
+static void nlm_xlp_uart_out(struct uart_port *p, int offset, int value)
+{
+        nlm_write_reg(p->iobase, offset, value);
+}
+
+#define PORT(_irq)                                      \
+        {                                               \
+                .irq            = _irq,                 \
+                .regshift       = 2,                    \
+                .iotype         = UPIO_MEM32,           \
+                .flags          = (UPF_SKIP_TEST|UPF_FIXED_TYPE|\
+                                        UPF_BOOT_AUTOCONF),     \
+                .uartclk        = XLP_IO_CLK,           \
+                .type           = PORT_16550A,          \
+                .serial_in      = nlm_xlp_uart_in,      \
+                .serial_out     = nlm_xlp_uart_out,     \
+        }
+
+static struct plat_serial8250_port xlp_uart_data[] = {
+        PORT(PIC_UART_0_IRQ),
+        PORT(PIC_UART_1_IRQ),
+        {},
+};
+
+static struct platform_device uart_device = {
+        .name           = "serial8250",
+        .id             = PLAT8250_DEV_PLATFORM,
+        .dev = {
+                .platform_data = xlp_uart_data,
+        },
+};
+
+static int __init nlm_platform_uart_init(void)
+{
+        unsigned long mmio;
+
+        mmio = (unsigned long)nlm_get_uart_regbase(0, 0);
+        xlp_uart_data[0].iobase = mmio;
+        xlp_uart_data[0].membase = (void __iomem *)mmio;
+        xlp_uart_data[0].mapbase = mmio;
+
+        mmio = (unsigned long)nlm_get_uart_regbase(0, 1);
+        xlp_uart_data[1].iobase = mmio;
+        xlp_uart_data[1].membase = (void __iomem *)mmio;
+        xlp_uart_data[1].mapbase = mmio;
+
+        return platform_device_register(&uart_device);
+}
+
+arch_initcall(nlm_platform_uart_init);
diff --git a/arch/mips/netlogic/xlp/setup.c b/arch/mips/netlogic/xlp/setup.c
new file mode 100644
index 00000000000..acb677a1227
--- /dev/null
+++ b/arch/mips/netlogic/xlp/setup.c
@@ -0,0 +1,105 @@
+/*
+ * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
+ * reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the NetLogic
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <linux/kernel.h>
+#include <linux/serial_8250.h>
+#include <linux/pm.h>
+
+#include <asm/reboot.h>
+#include <asm/time.h>
+#include <asm/bootinfo.h>
+
+#include <linux/of_fdt.h>
+
+#include <asm/netlogic/haldefs.h>
+#include <asm/netlogic/common.h>
+
+#include <asm/netlogic/xlp-hal/iomap.h>
+#include <asm/netlogic/xlp-hal/xlp.h>
+#include <asm/netlogic/xlp-hal/sys.h>
+
+unsigned long nlm_common_ebase = 0x0;
+
+/* default to uniprocessor */
+uint32_t nlm_coremask = 1, nlm_cpumask  = 1;
+int  nlm_threads_per_core = 1;
+
+static void nlm_linux_exit(void)
+{
+        nlm_write_sys_reg(nlm_sys_base, SYS_CHIP_RESET, 1);
+        for ( ; ; )
+                cpu_wait();
+}
+
+void __init plat_mem_setup(void)
+{
+        panic_timeout   = 5;
+        _machine_restart = (void (*)(char *))nlm_linux_exit;
+        _machine_halt   = nlm_linux_exit;
+        pm_power_off    = nlm_linux_exit;
+}
+
+const char *get_system_type(void)
+{
+        return "Netlogic XLP Series";
+}
+
+void __init prom_free_prom_memory(void)
+{
+        /* Nothing yet */
+}
+
+void xlp_mmu_init(void)
+{
+        write_c0_config6(read_c0_config6() | 0x24);
+        current_cpu_data.tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
+        write_c0_config7(PM_DEFAULT_MASK >>
+                (13 + (ffz(PM_DEFAULT_MASK >> 13) / 2)));
+}
+
+void __init prom_init(void)
+{
+        void *fdtp;
+
+        fdtp = (void *)(long)fw_arg0;
+        xlp_mmu_init();
+        nlm_hal_init();
+        early_init_devtree(fdtp);
+
+        nlm_common_ebase = read_c0_ebase() & (~((1 << 12) - 1));
+#ifdef CONFIG_SMP
+        nlm_wakeup_secondary_cpus(0xffffffff);
+        register_smp_ops(&nlm_smp_ops);
+#endif
+}
diff --git a/arch/mips/netlogic/xlp/wakeup.c b/arch/mips/netlogic/xlp/wakeup.c
new file mode 100644
index 00000000000..44d923ff384
--- /dev/null
+++ b/arch/mips/netlogic/xlp/wakeup.c
@@ -0,0 +1,102 @@
+/*
+ * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
+ * reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the NetLogic
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/threads.h>
+
+#include <asm/asm.h>
+#include <asm/asm-offsets.h>
+#include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+#include <asm/string.h>
+
+#include <asm/netlogic/haldefs.h>
+#include <asm/netlogic/common.h>
+#include <asm/netlogic/mips-extns.h>
+
+#include <asm/netlogic/xlp-hal/iomap.h>
+#include <asm/netlogic/xlp-hal/pic.h>
+#include <asm/netlogic/xlp-hal/xlp.h>
+#include <asm/netlogic/xlp-hal/sys.h>
+
+static void xlp_enable_secondary_cores(void)
+{
+        uint32_t core, value, coremask, syscoremask;
+        int count;
+
+        /* read cores in reset from SYS block */
+        syscoremask = nlm_read_sys_reg(nlm_sys_base, SYS_CPU_RESET);
+
+        /* update user specified */
+        nlm_coremask = nlm_coremask & (syscoremask | 1);
+
+        for (core = 1; core < 8; core++) {
+                coremask = 1 << core;
+                if ((nlm_coremask & coremask) == 0)
+                        continue;
+
+                /* Enable CPU clock */
+                value = nlm_read_sys_reg(nlm_sys_base, SYS_CORE_DFS_DIS_CTRL);
+                value &= ~coremask;
+                nlm_write_sys_reg(nlm_sys_base, SYS_CORE_DFS_DIS_CTRL, value);
+
+                /* Remove CPU Reset */
+                value = nlm_read_sys_reg(nlm_sys_base, SYS_CPU_RESET);
+                value &= ~coremask;
+                nlm_write_sys_reg(nlm_sys_base, SYS_CPU_RESET, value);
+
+                /* Poll for CPU to mark itself coherent */
+                count = 100000;
+                do {
+                        value = nlm_read_sys_reg(nlm_sys_base,
+                            SYS_CPU_NONCOHERENT_MODE);
+                } while ((value & coremask) != 0 && count-- > 0);
+
+                if (count == 0)
+                        pr_err("Failed to enable core %d\n", core);
+        }
+}
+
+void xlp_wakeup_secondary_cpus(void)
+{
+        /*
+         * In case of u-boot, the secondaries are in reset
+         * first wakeup core 0 threads
+         */
+        xlp_boot_core0_siblings();
+
+        /* now get other cores out of reset */
+        xlp_enable_secondary_cores();
+}
diff --git a/arch/mips/netlogic/xlr/Makefile b/arch/mips/netlogic/xlr/Makefile
index 2dca585dd2f..f01e4d7a060 100644
--- a/arch/mips/netlogic/xlr/Makefile
+++ b/arch/mips/netlogic/xlr/Makefile
@@ -1,5 +1,2 @@
-obj-y                           += setup.o platform.o irq.o setup.o time.o
-obj-$(CONFIG_SMP)               += smp.o smpboot.o
-obj-$(CONFIG_EARLY_PRINTK)      += xlr_console.o
-
-ccflags-y                       += -Werror
+obj-y                           += setup.o platform.o
+obj-$(CONFIG_SMP)               += wakeup.o
diff --git a/arch/mips/netlogic/xlr/irq.c b/arch/mips/netlogic/xlr/irq.c
deleted file mode 100644
index 521bb7377eb..00000000000
--- a/arch/mips/netlogic/xlr/irq.c
+++ /dev/null
@@ -1,300 +0,0 @@
-/*
- * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
- * reserved.
- *
- * This software is available to you under a choice of one of two
- * licenses.  You may choose to be licensed under the terms of the GNU
- * General Public License (GPL) Version 2, available from the file
- * COPYING in the main directory of this source tree, or the NetLogic
- * license below:
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/linkage.h>
-#include <linux/interrupt.h>
-#include <linux/spinlock.h>
-#include <linux/mm.h>
-
-#include <asm/mipsregs.h>
-
-#include <asm/netlogic/xlr/iomap.h>
-#include <asm/netlogic/xlr/pic.h>
-#include <asm/netlogic/xlr/xlr.h>
-
-#include <asm/netlogic/interrupt.h>
-#include <asm/netlogic/mips-extns.h>
-
-static u64 nlm_irq_mask;
-static DEFINE_SPINLOCK(nlm_pic_lock);
-
-static void xlr_pic_enable(struct irq_data *d)
-{
-        nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
-        unsigned long flags;
-        nlm_reg_t reg;
-        int irq = d->irq;
-
-        WARN(!PIC_IRQ_IS_IRT(irq), "Bad irq %d", irq);
-
-        spin_lock_irqsave(&nlm_pic_lock, flags);
-        reg = netlogic_read_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE);
-        netlogic_write_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE,
-                          reg | (1 << 6) | (1 << 30) | (1 << 31));
-        spin_unlock_irqrestore(&nlm_pic_lock, flags);
-}
-
-static void xlr_pic_mask(struct irq_data *d)
-{
-        nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
-        unsigned long flags;
-        nlm_reg_t reg;
-        int irq = d->irq;
-
-        WARN(!PIC_IRQ_IS_IRT(irq), "Bad irq %d", irq);
-
-        spin_lock_irqsave(&nlm_pic_lock, flags);
-        reg = netlogic_read_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE);
-        netlogic_write_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE,
-                          reg | (1 << 6) | (1 << 30) | (0 << 31));
-        spin_unlock_irqrestore(&nlm_pic_lock, flags);
-}
-
-#ifdef CONFIG_PCI
-/* Extra ACK needed for XLR on chip PCI controller */
-static void xlr_pci_ack(struct irq_data *d)
-{
-        nlm_reg_t *pci_mmio = netlogic_io_mmio(NETLOGIC_IO_PCIX_OFFSET);
-
-        netlogic_read_reg(pci_mmio, (0x140 >> 2));
-}
-
-/* Extra ACK needed for XLS on chip PCIe controller */
-static void xls_pcie_ack(struct irq_data *d)
-{
-        nlm_reg_t *pcie_mmio_le = netlogic_io_mmio(NETLOGIC_IO_PCIE_1_OFFSET);
-
-        switch (d->irq) {
-        case PIC_PCIE_LINK0_IRQ:
-                netlogic_write_reg(pcie_mmio_le, (0x90 >> 2), 0xffffffff);
-                break;
-        case PIC_PCIE_LINK1_IRQ:
-                netlogic_write_reg(pcie_mmio_le, (0x94 >> 2), 0xffffffff);
-                break;
-        case PIC_PCIE_LINK2_IRQ:
-                netlogic_write_reg(pcie_mmio_le, (0x190 >> 2), 0xffffffff);
-                break;
-        case PIC_PCIE_LINK3_IRQ:
-                netlogic_write_reg(pcie_mmio_le, (0x194 >> 2), 0xffffffff);
-                break;
-        }
-}
-
-/* For XLS B silicon, the 3,4 PCI interrupts are different */
-static void xls_pcie_ack_b(struct irq_data *d)
-{
-        nlm_reg_t *pcie_mmio_le = netlogic_io_mmio(NETLOGIC_IO_PCIE_1_OFFSET);
-
-        switch (d->irq) {
-        case PIC_PCIE_LINK0_IRQ:
-                netlogic_write_reg(pcie_mmio_le, (0x90 >> 2), 0xffffffff);
-                break;
-        case PIC_PCIE_LINK1_IRQ:
-                netlogic_write_reg(pcie_mmio_le, (0x94 >> 2), 0xffffffff);
-                break;
-        case PIC_PCIE_XLSB0_LINK2_IRQ:
-                netlogic_write_reg(pcie_mmio_le, (0x190 >> 2), 0xffffffff);
-                break;
-        case PIC_PCIE_XLSB0_LINK3_IRQ:
-                netlogic_write_reg(pcie_mmio_le, (0x194 >> 2), 0xffffffff);
-                break;
-        }
-}
-#endif
-
-static void xlr_pic_ack(struct irq_data *d)
-{
-        unsigned long flags;
-        nlm_reg_t *mmio;
-        int irq = d->irq;
-        void *hd = irq_data_get_irq_handler_data(d);
-
-        WARN(!PIC_IRQ_IS_IRT(irq), "Bad irq %d", irq);
-
-        if (hd) {
-                void (*extra_ack)(void *) = hd;
-                extra_ack(d);
-        }
-        mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
-        spin_lock_irqsave(&nlm_pic_lock, flags);
-        netlogic_write_reg(mmio, PIC_INT_ACK, (1 << (irq - PIC_IRQ_BASE)));
-        spin_unlock_irqrestore(&nlm_pic_lock, flags);
-}
-
-/*
- * This chip definition handles interrupts routed thru the XLR
- * hardware PIC, currently IRQs 8-39 are mapped to hardware intr
- * 0-31 wired the XLR PIC
- */
-static struct irq_chip xlr_pic = {
-        .name           = "XLR-PIC",
-        .irq_enable     = xlr_pic_enable,
-        .irq_mask       = xlr_pic_mask,
-        .irq_ack        = xlr_pic_ack,
-};
-
-static void rsvd_irq_handler(struct irq_data *d)
-{
-        WARN(d->irq >= PIC_IRQ_BASE, "Bad irq %d", d->irq);
-}
-
-/*
- * Chip definition for CPU originated interrupts(timer, msg) and
- * IPIs
- */
-struct irq_chip nlm_cpu_intr = {
-        .name           = "XLR-CPU-INTR",
-        .irq_enable     = rsvd_irq_handler,
-        .irq_mask       = rsvd_irq_handler,
-        .irq_ack        = rsvd_irq_handler,
-};
-
-void __init init_xlr_irqs(void)
-{
-        nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
-        uint32_t thread_mask = 1;
-        int level, i;
-
-        pr_info("Interrupt thread mask [%x]\n", thread_mask);
-        for (i = 0; i < PIC_NUM_IRTS; i++) {
-                level = PIC_IRQ_IS_EDGE_TRIGGERED(i);
-
-                /* Bind all PIC irqs to boot cpu */
-                netlogic_write_reg(mmio, PIC_IRT_0_BASE + i, thread_mask);
-
-                /*
-                 * Use local scheduling and high polarity for all IRTs
-                 * Invalidate all IRTs, by default
-                 */
-                netlogic_write_reg(mmio, PIC_IRT_1_BASE + i,
-                                (level << 30) | (1 << 6) | (PIC_IRQ_BASE + i));
-        }
-
-        /* Make all IRQs as level triggered by default */
-        for (i = 0; i < NR_IRQS; i++) {
-                if (PIC_IRQ_IS_IRT(i))
-                        irq_set_chip_and_handler(i, &xlr_pic, handle_level_irq);
-                else
-                        irq_set_chip_and_handler(i, &nlm_cpu_intr,
-                                                handle_percpu_irq);
-        }
-#ifdef CONFIG_SMP
-        irq_set_chip_and_handler(IRQ_IPI_SMP_FUNCTION, &nlm_cpu_intr,
-                         nlm_smp_function_ipi_handler);
-        irq_set_chip_and_handler(IRQ_IPI_SMP_RESCHEDULE, &nlm_cpu_intr,
-                         nlm_smp_resched_ipi_handler);
-        nlm_irq_mask |=
-            ((1ULL << IRQ_IPI_SMP_FUNCTION) | (1ULL << IRQ_IPI_SMP_RESCHEDULE));
-#endif
-
-#ifdef CONFIG_PCI
-        /*
-         * For PCI interrupts, we need to ack the PIC controller too, overload
-         * irq handler data to do this
-         */
-        if (nlm_chip_is_xls()) {
-                if (nlm_chip_is_xls_b()) {
-                        irq_set_handler_data(PIC_PCIE_LINK0_IRQ,
-                                                        xls_pcie_ack_b);
-                        irq_set_handler_data(PIC_PCIE_LINK1_IRQ,
-                                                        xls_pcie_ack_b);
-                        irq_set_handler_data(PIC_PCIE_XLSB0_LINK2_IRQ,
-                                                        xls_pcie_ack_b);
-                        irq_set_handler_data(PIC_PCIE_XLSB0_LINK3_IRQ,
-                                                        xls_pcie_ack_b);
-                } else {
-                        irq_set_handler_data(PIC_PCIE_LINK0_IRQ, xls_pcie_ack);
-                        irq_set_handler_data(PIC_PCIE_LINK1_IRQ, xls_pcie_ack);
-                        irq_set_handler_data(PIC_PCIE_LINK2_IRQ, xls_pcie_ack);
-                        irq_set_handler_data(PIC_PCIE_LINK3_IRQ, xls_pcie_ack);
-                }
-        } else {
-                /* XLR PCI controller ACK */
-                irq_set_handler_data(PIC_PCIE_XLSB0_LINK3_IRQ, xlr_pci_ack);
-        }
-#endif
-        /* unmask all PIC related interrupts. If no handler is installed by the
-         * drivers, it'll just ack the interrupt and return
-         */
-        for (i = PIC_IRT_FIRST_IRQ; i <= PIC_IRT_LAST_IRQ; i++)
-                nlm_irq_mask |= (1ULL << i);
-
-        nlm_irq_mask |= (1ULL << IRQ_TIMER);
-}
-
-void __init arch_init_irq(void)
-{
-        /* Initialize the irq descriptors */
-        init_xlr_irqs();
-        write_c0_eimr(nlm_irq_mask);
-}
-
-void __cpuinit nlm_smp_irq_init(void)
-{
-        /* set interrupt mask for non-zero cpus */
-        write_c0_eimr(nlm_irq_mask);
-}
-
-asmlinkage void plat_irq_dispatch(void)
-{
-        uint64_t eirr;
-        int i;
-
-        eirr = read_c0_eirr() & read_c0_eimr();
-        if (!eirr)
-                return;
-
-        /* no need of EIRR here, writing compare clears interrupt */
-        if (eirr & (1 << IRQ_TIMER)) {
-                do_IRQ(IRQ_TIMER);
-                return;
-        }
-
-        /* use dcltz: optimize below code */
-        for (i = 63; i != -1; i--) {
-                if (eirr & (1ULL << i))
-                        break;
-        }
-        if (i == -1) {
-                pr_err("no interrupt !!\n");
-                return;
-        }
-
-        /* Ack eirr */
-        write_c0_eirr(1ULL << i);
-
-        do_IRQ(i);
-}
diff --git a/arch/mips/netlogic/xlr/platform.c b/arch/mips/netlogic/xlr/platform.c
index 609ec253464..eab64b45dff 100644
--- a/arch/mips/netlogic/xlr/platform.c
+++ b/arch/mips/netlogic/xlr/platform.c
@@ -15,18 +15,19 @@
 #include <linux/serial_8250.h>
 #include <linux/serial_reg.h>
 
+#include <asm/netlogic/haldefs.h>
 #include <asm/netlogic/xlr/iomap.h>
 #include <asm/netlogic/xlr/pic.h>
 #include <asm/netlogic/xlr/xlr.h>
 
 unsigned int nlm_xlr_uart_in(struct uart_port *p, int offset)
 {
-        nlm_reg_t *mmio;
+        uint64_t uartbase;
         unsigned int value;
 
-        /* XLR uart does not need any mapping of regs */
-        mmio = (nlm_reg_t *)(p->membase + (offset << p->regshift));
-        value = netlogic_read_reg(mmio, 0);
+        /* sign extend to 64 bits, if needed */
+        uartbase = (uint64_t)(long)p->membase;
+        value = nlm_read_reg(uartbase, offset);
 
         /* See XLR/XLS errata */
         if (offset == UART_MSR)
@@ -39,10 +40,10 @@ unsigned int nlm_xlr_uart_in(struct uart_port *p, int offset)
 
 void nlm_xlr_uart_out(struct uart_port *p, int offset, int value)
 {
-        nlm_reg_t *mmio;
+        uint64_t uartbase;
 
-        /* XLR uart does not need any mapping of regs */
-        mmio = (nlm_reg_t *)(p->membase + (offset << p->regshift));
+        /* sign extend to 64 bits, if needed */
+        uartbase = (uint64_t)(long)p->membase;
 
         /* See XLR/XLS errata */
         if (offset == UART_MSR)
@@ -50,7 +51,7 @@ void nlm_xlr_uart_out(struct uart_port *p, int offset, int value)
         else if (offset == UART_MCR)
                 value ^= 0x3;
 
-        netlogic_write_reg(mmio, 0, value);
+        nlm_write_reg(uartbase, offset, value);
 }
 
 #define PORT(_irq)                                      \
@@ -82,15 +83,15 @@ static struct platform_device uart_device = {
 
 static int __init nlm_uart_init(void)
 {
-        nlm_reg_t *mmio;
+        unsigned long uartbase;
 
-        mmio = netlogic_io_mmio(NETLOGIC_IO_UART_0_OFFSET);
-        xlr_uart_data[0].membase = (void __iomem *)mmio;
-        xlr_uart_data[0].mapbase = CPHYSADDR((unsigned long)mmio);
+        uartbase = (unsigned long)nlm_mmio_base(NETLOGIC_IO_UART_0_OFFSET);
+        xlr_uart_data[0].membase = (void __iomem *)uartbase;
+        xlr_uart_data[0].mapbase = CPHYSADDR(uartbase);
 
-        mmio = netlogic_io_mmio(NETLOGIC_IO_UART_1_OFFSET);
-        xlr_uart_data[1].membase = (void __iomem *)mmio;
-        xlr_uart_data[1].mapbase = CPHYSADDR((unsigned long)mmio);
+        uartbase = (unsigned long)nlm_mmio_base(NETLOGIC_IO_UART_1_OFFSET);
+        xlr_uart_data[1].membase = (void __iomem *)uartbase;
+        xlr_uart_data[1].mapbase = CPHYSADDR(uartbase);
 
         return platform_device_register(&uart_device);
 }
diff --git a/arch/mips/netlogic/xlr/setup.c b/arch/mips/netlogic/xlr/setup.c
index cee25ddd088..c9d066dedc4 100644
--- a/arch/mips/netlogic/xlr/setup.c
+++ b/arch/mips/netlogic/xlr/setup.c
@@ -39,26 +39,33 @@
 #include <asm/reboot.h>
 #include <asm/time.h>
 #include <asm/bootinfo.h>
-#include <asm/smp-ops.h>
 
 #include <asm/netlogic/interrupt.h>
 #include <asm/netlogic/psb-bootinfo.h>
+#include <asm/netlogic/haldefs.h>
+#include <asm/netlogic/common.h>
 
 #include <asm/netlogic/xlr/xlr.h>
 #include <asm/netlogic/xlr/iomap.h>
 #include <asm/netlogic/xlr/pic.h>
 #include <asm/netlogic/xlr/gpio.h>
 
-unsigned long netlogic_io_base = (unsigned long)(DEFAULT_NETLOGIC_IO_BASE);
-unsigned long nlm_common_ebase = 0x0;
+uint64_t nlm_io_base = DEFAULT_NETLOGIC_IO_BASE;
+uint64_t nlm_pic_base;
 struct psb_info nlm_prom_info;
 
+unsigned long nlm_common_ebase = 0x0;
+
+/* default to uniprocessor */
+uint32_t nlm_coremask = 1, nlm_cpumask  = 1;
+int  nlm_threads_per_core = 1;
+
 static void __init nlm_early_serial_setup(void)
 {
         struct uart_port s;
-        nlm_reg_t *uart_base;
+        unsigned long uart_base;
 
-        uart_base = netlogic_io_mmio(NETLOGIC_IO_UART_0_OFFSET);
+        uart_base = (unsigned long)nlm_mmio_base(NETLOGIC_IO_UART_0_OFFSET);
         memset(&s, 0, sizeof(s));
         s.flags         = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
         s.iotype        = UPIO_MEM32;
@@ -67,18 +74,18 @@ static void __init nlm_early_serial_setup(void)
         s.uartclk       = PIC_CLKS_PER_SEC;
         s.serial_in     = nlm_xlr_uart_in;
         s.serial_out    = nlm_xlr_uart_out;
-        s.mapbase       = (unsigned long)uart_base;
+        s.mapbase       = uart_base;
         s.membase       = (unsigned char __iomem *)uart_base;
         early_serial_setup(&s);
 }
 
 static void nlm_linux_exit(void)
 {
-        nlm_reg_t *mmio;
+        uint64_t gpiobase;
 
-        mmio = netlogic_io_mmio(NETLOGIC_IO_GPIO_OFFSET);
+        gpiobase = nlm_mmio_base(NETLOGIC_IO_GPIO_OFFSET);
         /* trigger a chip reset by writing 1 to GPIO_SWRESET_REG */
-        netlogic_write_reg(mmio, NETLOGIC_GPIO_SWRESET_REG, 1);
+        nlm_write_reg(gpiobase, NETLOGIC_GPIO_SWRESET_REG, 1);
         for ( ; ; )
                 cpu_wait();
 }
@@ -96,6 +103,11 @@ const char *get_system_type(void)
         return "Netlogic XLR/XLS Series";
 }
 
+unsigned int nlm_get_cpu_frequency(void)
+{
+        return (unsigned int)nlm_prom_info.cpu_frequency;
+}
+
 void __init prom_free_prom_memory(void)
 {
         /* Nothing yet */
@@ -175,6 +187,7 @@ void __init prom_init(void)
         prom_infop = (struct psb_info *)(long)(int)fw_arg3;
 
         nlm_prom_info = *prom_infop;
+        nlm_pic_base = nlm_mmio_base(NETLOGIC_IO_PIC_OFFSET);
 
         nlm_early_serial_setup();
         build_arcs_cmdline(argv);
diff --git a/arch/mips/netlogic/xlr/smpboot.S b/arch/mips/netlogic/xlr/wakeup.c
index 8cb7889ce0c..db5d987d488 100644
--- a/arch/mips/netlogic/xlr/smpboot.S
+++ b/arch/mips/netlogic/xlr/wakeup.c
@@ -33,68 +33,36 @@
  */
 
 #include <linux/init.h>
+#include <linux/threads.h>
 
 #include <asm/asm.h>
 #include <asm/asm-offsets.h>
-#include <asm/regdef.h>
 #include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+#include <asm/string.h>
 
-/*
- * Early code for secondary CPUs. This will get them out of the bootloader
- * code and into linux. Needed because the bootloader area will be taken
- * and initialized by linux.
- */
-        __CPUINIT
-NESTED(prom_pre_boot_secondary_cpus, 16, sp)
-        .set    mips64
-        mfc0    t0, $15, 1      # read ebase
-        andi    t0, 0x1f        # t0 has the processor_id()
-        sll     t0, 2           # offset in cpu array
-
-        PTR_LA  t1, nlm_cpu_ready # mark CPU ready
-        PTR_ADDU t1, t0
-        li      t2, 1
-        sw      t2, 0(t1)
-
-        PTR_LA  t1, nlm_cpu_unblock
-        PTR_ADDU t1, t0
-1:      lw      t2, 0(t1)       # wait till unblocked
-        beqz    t2, 1b
-        nop
+#include <asm/netlogic/haldefs.h>
+#include <asm/netlogic/common.h>
+#include <asm/netlogic/mips-extns.h>
 
-        PTR_LA  t1, nlm_next_sp
-        PTR_L   sp, 0(t1)
-        PTR_LA  t1, nlm_next_gp
-        PTR_L   gp, 0(t1)
+#include <asm/netlogic/xlr/iomap.h>
+#include <asm/netlogic/xlr/pic.h>
 
-        PTR_LA  t0, nlm_early_init_secondary
-        jalr    t0
-        nop
-
-        PTR_LA  t0, smp_bootstrap
-        jr      t0
-        nop
-END(prom_pre_boot_secondary_cpus)
-        __FINIT
-
-/*
- * NMI code, used for CPU wakeup, copied to reset entry
- */
-NESTED(nlm_boot_smp_nmi, 0, sp)
-        .set push
-        .set noat
-        .set mips64
-        .set noreorder
+int __cpuinit xlr_wakeup_secondary_cpus(void)
+{
+        unsigned int i, boot_cpu;
 
-        /* Clear the  NMI and BEV bits */
-        MFC0    k0, CP0_STATUS
-        li      k1, 0xffb7ffff
-        and     k0, k0, k1
-        MTC0    k0, CP0_STATUS
+        /*
+         *  In case of RMI boot, hit with NMI to get the cores
+         *  from bootloader to linux code.
+         */
+        boot_cpu = hard_smp_processor_id();
+        nlm_set_nmi_handler(nlm_rmiboot_preboot);
+        for (i = 0; i < NR_CPUS; i++) {
+                if (i == boot_cpu || (nlm_cpumask & (1u << i)) == 0)
+                        continue;
+                nlm_pic_send_ipi(nlm_pic_base, i, 1, 1); /* send NMI */
+        }
 
-        PTR_LA  k1, secondary_entry_point
-        PTR_L   k0, 0(k1)
-        jr      k0
-        nop
-        .set pop
-END(nlm_boot_smp_nmi)
+        return 0;
+}
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index bb82cbdbc62..c3ac4b086eb 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_BCM47XX)		+= pci-bcm47xx.o
 obj-$(CONFIG_BCM63XX)           += pci-bcm63xx.o fixup-bcm63xx.o \
                                         ops-bcm63xx.o
 obj-$(CONFIG_MIPS_ALCHEMY)      += pci-alchemy.o
+obj-$(CONFIG_SOC_AR724X)        += pci-ath724x.o
 
 #
 # These are still pretty much in the old state, watch, go blind.
@@ -55,7 +56,7 @@ obj-$(CONFIG_ZAO_CAPCELLA)	+= fixup-capcella.o
 obj-$(CONFIG_WR_PPMC)           += fixup-wrppmc.o
 obj-$(CONFIG_MIKROTIK_RB532)    += pci-rc32434.o ops-rc32434.o fixup-rc32434.o
 obj-$(CONFIG_CPU_CAVIUM_OCTEON) += pci-octeon.o pcie-octeon.o
-obj-$(CONFIG_NLM_XLR)           += pci-xlr.o
+obj-$(CONFIG_CPU_XLR)           += pci-xlr.o
 
 ifdef CONFIG_PCI_MSI
 obj-$(CONFIG_CPU_CAVIUM_OCTEON) += msi-octeon.o
diff --git a/arch/mips/pci/pci-ath724x.c b/arch/mips/pci/pci-ath724x.c
new file mode 100644
index 00000000000..a4dd24a4130
--- /dev/null
+++ b/arch/mips/pci/pci-ath724x.c
@@ -0,0 +1,174 @@
+/*
+ *  Atheros 724x PCI support
+ *
+ *  Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#include <linux/pci.h>
+#include <asm/mach-ath79/pci-ath724x.h>
+
+#define reg_read(_phys)         (*(unsigned int *) KSEG1ADDR(_phys))
+#define reg_write(_phys, _val)  ((*(unsigned int *) KSEG1ADDR(_phys)) = (_val))
+
+#define ATH724X_PCI_DEV_BASE    0x14000000
+#define ATH724X_PCI_MEM_BASE    0x10000000
+#define ATH724X_PCI_MEM_SIZE    0x08000000
+
+static DEFINE_SPINLOCK(ath724x_pci_lock);
+static struct ath724x_pci_data *pci_data;
+static int pci_data_size;
+
+static int ath724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
+                            int size, uint32_t *value)
+{
+        unsigned long flags, addr, tval, mask;
+
+        if (devfn)
+                return PCIBIOS_DEVICE_NOT_FOUND;
+
+        if (where & (size - 1))
+                return PCIBIOS_BAD_REGISTER_NUMBER;
+
+        spin_lock_irqsave(&ath724x_pci_lock, flags);
+
+        switch (size) {
+        case 1:
+                addr = where & ~3;
+                mask = 0xff000000 >> ((where % 4) * 8);
+                tval = reg_read(ATH724X_PCI_DEV_BASE + addr);
+                tval = tval & ~mask;
+                *value = (tval >> ((4 - (where % 4))*8));
+                break;
+        case 2:
+                addr = where & ~3;
+                mask = 0xffff0000 >> ((where % 4)*8);
+                tval = reg_read(ATH724X_PCI_DEV_BASE + addr);
+                tval = tval & ~mask;
+                *value = (tval >> ((4 - (where % 4))*8));
+                break;
+        case 4:
+                *value = reg_read(ATH724X_PCI_DEV_BASE + where);
+                break;
+        default:
+                spin_unlock_irqrestore(&ath724x_pci_lock, flags);
+
+                return PCIBIOS_BAD_REGISTER_NUMBER;
+        }
+
+        spin_unlock_irqrestore(&ath724x_pci_lock, flags);
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+static int ath724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
+                             int size, uint32_t value)
+{
+        unsigned long flags, tval, addr, mask;
+
+        if (devfn)
+                return PCIBIOS_DEVICE_NOT_FOUND;
+
+        if (where & (size - 1))
+                return PCIBIOS_BAD_REGISTER_NUMBER;
+
+        spin_lock_irqsave(&ath724x_pci_lock, flags);
+
+        switch (size) {
+        case 1:
+                addr = (ATH724X_PCI_DEV_BASE + where) & ~3;
+                mask = 0xff000000 >> ((where % 4)*8);
+                tval = reg_read(addr);
+                tval = tval & ~mask;
+                tval |= (value << ((4 - (where % 4))*8)) & mask;
+                reg_write(addr, tval);
+                break;
+        case 2:
+                addr = (ATH724X_PCI_DEV_BASE + where) & ~3;
+                mask = 0xffff0000 >> ((where % 4)*8);
+                tval = reg_read(addr);
+                tval = tval & ~mask;
+                tval |= (value << ((4 - (where % 4))*8)) & mask;
+                reg_write(addr, tval);
+                break;
+        case 4:
+                reg_write((ATH724X_PCI_DEV_BASE + where), value);
+                break;
+        default:
+                spin_unlock_irqrestore(&ath724x_pci_lock, flags);
+
+                return PCIBIOS_BAD_REGISTER_NUMBER;
+        }
+
+        spin_unlock_irqrestore(&ath724x_pci_lock, flags);
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+static struct pci_ops ath724x_pci_ops = {
+        .read   = ath724x_pci_read,
+        .write  = ath724x_pci_write,
+};
+
+static struct resource ath724x_io_resource = {
+        .name   = "PCI IO space",
+        .start  = 0,
+        .end    = 0,
+        .flags  = IORESOURCE_IO,
+};
+
+static struct resource ath724x_mem_resource = {
+        .name   = "PCI memory space",
+        .start  = ATH724X_PCI_MEM_BASE,
+        .end    = ATH724X_PCI_MEM_BASE + ATH724X_PCI_MEM_SIZE - 1,
+        .flags  = IORESOURCE_MEM,
+};
+
+static struct pci_controller ath724x_pci_controller = {
+        .pci_ops        = &ath724x_pci_ops,
+        .io_resource    = &ath724x_io_resource,
+        .mem_resource   = &ath724x_mem_resource,
+};
+
+void ath724x_pci_add_data(struct ath724x_pci_data *data, int size)
+{
+        pci_data        = data;
+        pci_data_size   = size;
+}
+
+int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
+{
+        unsigned int devfn = dev->devfn;
+        int irq = -1;
+
+        if (devfn > pci_data_size - 1)
+                return irq;
+
+        irq = pci_data[devfn].irq;
+
+        return irq;
+}
+
+int pcibios_plat_dev_init(struct pci_dev *dev)
+{
+        unsigned int devfn = dev->devfn;
+
+        if (devfn > pci_data_size - 1)
+                return PCIBIOS_DEVICE_NOT_FOUND;
+
+        dev->dev.platform_data = pci_data[devfn].pdata;
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+static int __init ath724x_pcibios_init(void)
+{
+        register_pci_controller(&ath724x_pci_controller);
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+arch_initcall(ath724x_pcibios_init);
diff --git a/arch/mips/pci/pci-bcm63xx.c b/arch/mips/pci/pci-bcm63xx.c
index 82e0fde1dba..39eb7c417e2 100644
--- a/arch/mips/pci/pci-bcm63xx.c
+++ b/arch/mips/pci/pci-bcm63xx.c
@@ -99,7 +99,7 @@ static int __init bcm63xx_pci_init(void)
         unsigned int mem_size;
         u32 val;
 
-        if (!BCMCPU_IS_6348() && !BCMCPU_IS_6358())
+        if (!BCMCPU_IS_6348() && !BCMCPU_IS_6358() && !BCMCPU_IS_6368())
                 return -ENODEV;
 
         if (!bcm63xx_pci_enabled)
@@ -159,7 +159,7 @@ static int __init bcm63xx_pci_init(void)
         /* setup PCI to local bus access, used by PCI device to target
          * local RAM while bus mastering */
         bcm63xx_int_cfg_writel(0, PCI_BASE_ADDRESS_3);
-        if (BCMCPU_IS_6358())
+        if (BCMCPU_IS_6358() || BCMCPU_IS_6368())
                 val = MPI_SP0_REMAP_ENABLE_MASK;
         else
                 val = 0;
diff --git a/arch/mips/pci/pci-octeon.c b/arch/mips/pci/pci-octeon.c
index ed1c54284b8..52a1ba70b3b 100644
--- a/arch/mips/pci/pci-octeon.c
+++ b/arch/mips/pci/pci-octeon.c
@@ -99,7 +99,7 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
          */
         pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 64 / 4);
         /* Set latency timers for all devices */
-        pci_write_config_byte(dev, PCI_LATENCY_TIMER, 48);
+        pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
 
         /* Enable reporting System errors and parity errors on all devices */
         /* Enable parity checking and error reporting */
@@ -109,7 +109,7 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
 
         if (dev->subordinate) {
                 /* Set latency timers on sub bridges */
-                pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 48);
+                pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 64);
                 /* More bridge error detection */
                 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &config);
                 config |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR;
@@ -121,14 +121,10 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
         if (pos) {
                 /* Update Device Control */
                 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &config);
-                /* Correctable Error Reporting */
-                config |= PCI_EXP_DEVCTL_CERE;
-                /* Non-Fatal Error Reporting */
-                config |= PCI_EXP_DEVCTL_NFERE;
-                /* Fatal Error Reporting */
-                config |= PCI_EXP_DEVCTL_FERE;
-                /* Unsupported Request */
-                config |= PCI_EXP_DEVCTL_URRE;
+                config |= PCI_EXP_DEVCTL_CERE; /* Correctable Error Reporting */
+                config |= PCI_EXP_DEVCTL_NFERE; /* Non-Fatal Error Reporting */
+                config |= PCI_EXP_DEVCTL_FERE;  /* Fatal Error Reporting */
+                config |= PCI_EXP_DEVCTL_URRE;  /* Unsupported Request */
                 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, config);
         }
 
diff --git a/arch/mips/pci/pci-xlr.c b/arch/mips/pci/pci-xlr.c
index 38fece16c43..3d701a962ef 100644
--- a/arch/mips/pci/pci-xlr.c
+++ b/arch/mips/pci/pci-xlr.c
@@ -36,12 +36,18 @@
 #include <linux/pci.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/msi.h>
 #include <linux/mm.h>
+#include <linux/irq.h>
+#include <linux/irqdesc.h>
 #include <linux/console.h>
 
 #include <asm/io.h>
 
 #include <asm/netlogic/interrupt.h>
+#include <asm/netlogic/haldefs.h>
+
+#include <asm/netlogic/xlr/msidef.h>
 #include <asm/netlogic/xlr/iomap.h>
 #include <asm/netlogic/xlr/pic.h>
 #include <asm/netlogic/xlr/xlr.h>
@@ -150,7 +156,7 @@ struct pci_controller nlm_pci_controller = {
         .io_offset      = 0x00000000UL,
 };
 
-int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+static int get_irq_vector(const struct pci_dev *dev)
 {
         if (!nlm_chip_is_xls())
                 return  PIC_PCIX_IRQ;   /* for XLR just one IRQ*/
@@ -182,6 +188,101 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
         return 0;
 }
 
+#ifdef CONFIG_PCI_MSI
+void destroy_irq(unsigned int irq)
+{
+            /* nothing to do yet */
+}
+
+void arch_teardown_msi_irq(unsigned int irq)
+{
+        destroy_irq(irq);
+}
+
+int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
+{
+        struct msi_msg msg;
+        int irq, ret;
+
+        irq = get_irq_vector(dev);
+        if (irq <= 0)
+                return 1;
+
+        msg.address_hi = MSI_ADDR_BASE_HI;
+        msg.address_lo = MSI_ADDR_BASE_LO   |
+                MSI_ADDR_DEST_MODE_PHYSICAL |
+                MSI_ADDR_REDIRECTION_CPU;
+
+        msg.data = MSI_DATA_TRIGGER_EDGE |
+                MSI_DATA_LEVEL_ASSERT    |
+                MSI_DATA_DELIVERY_FIXED;
+
+        ret = irq_set_msi_desc(irq, desc);
+        if (ret < 0) {
+                destroy_irq(irq);
+                return ret;
+        }
+
+        write_msi_msg(irq, &msg);
+        return 0;
+}
+#endif
+
+/* Extra ACK needed for XLR on chip PCI controller */
+static void xlr_pci_ack(struct irq_data *d)
+{
+        uint64_t pcibase = nlm_mmio_base(NETLOGIC_IO_PCIX_OFFSET);
+
+        nlm_read_reg(pcibase, (0x140 >> 2));
+}
+
+/* Extra ACK needed for XLS on chip PCIe controller */
+static void xls_pcie_ack(struct irq_data *d)
+{
+        uint64_t pciebase_le = nlm_mmio_base(NETLOGIC_IO_PCIE_1_OFFSET);
+
+        switch (d->irq) {
+        case PIC_PCIE_LINK0_IRQ:
+                nlm_write_reg(pciebase_le, (0x90 >> 2), 0xffffffff);
+                break;
+        case PIC_PCIE_LINK1_IRQ:
+                nlm_write_reg(pciebase_le, (0x94 >> 2), 0xffffffff);
+                break;
+        case PIC_PCIE_LINK2_IRQ:
+                nlm_write_reg(pciebase_le, (0x190 >> 2), 0xffffffff);
+                break;
+        case PIC_PCIE_LINK3_IRQ:
+                nlm_write_reg(pciebase_le, (0x194 >> 2), 0xffffffff);
+                break;
+        }
+}
+
+/* For XLS B silicon, the 3,4 PCI interrupts are different */
+static void xls_pcie_ack_b(struct irq_data *d)
+{
+        uint64_t pciebase_le = nlm_mmio_base(NETLOGIC_IO_PCIE_1_OFFSET);
+
+        switch (d->irq) {
+        case PIC_PCIE_LINK0_IRQ:
+                nlm_write_reg(pciebase_le, (0x90 >> 2), 0xffffffff);
+                break;
+        case PIC_PCIE_LINK1_IRQ:
+                nlm_write_reg(pciebase_le, (0x94 >> 2), 0xffffffff);
+                break;
+        case PIC_PCIE_XLSB0_LINK2_IRQ:
+                nlm_write_reg(pciebase_le, (0x190 >> 2), 0xffffffff);
+                break;
+        case PIC_PCIE_XLSB0_LINK3_IRQ:
+                nlm_write_reg(pciebase_le, (0x194 >> 2), 0xffffffff);
+                break;
+        }
+}
+
+int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+{
+        return get_irq_vector(dev);
+}
+
 /* Do platform specific device initialization at pci_enable_device() time */
 int pcibios_plat_dev_init(struct pci_dev *dev)
 {
@@ -204,6 +305,31 @@ static int __init pcibios_init(void)
         pr_info("Registering XLR/XLS PCIX/PCIE Controller.\n");
         register_pci_controller(&nlm_pci_controller);
 
+        /*
+         * For PCI interrupts, we need to ack the PCI controller too, overload
+         * irq handler data to do this
+         */
+        if (nlm_chip_is_xls()) {
+                if (nlm_chip_is_xls_b()) {
+                        irq_set_handler_data(PIC_PCIE_LINK0_IRQ,
+                                                        xls_pcie_ack_b);
+                        irq_set_handler_data(PIC_PCIE_LINK1_IRQ,
+                                                        xls_pcie_ack_b);
+                        irq_set_handler_data(PIC_PCIE_XLSB0_LINK2_IRQ,
+                                                        xls_pcie_ack_b);
+                        irq_set_handler_data(PIC_PCIE_XLSB0_LINK3_IRQ,
+                                                        xls_pcie_ack_b);
+                } else {
+                        irq_set_handler_data(PIC_PCIE_LINK0_IRQ, xls_pcie_ack);
+                        irq_set_handler_data(PIC_PCIE_LINK1_IRQ, xls_pcie_ack);
+                        irq_set_handler_data(PIC_PCIE_LINK2_IRQ, xls_pcie_ack);
+                        irq_set_handler_data(PIC_PCIE_LINK3_IRQ, xls_pcie_ack);
+                }
+        } else {
+                /* XLR PCI controller ACK */
+                irq_set_handler_data(PIC_PCIE_XLSB0_LINK3_IRQ, xlr_pci_ack);
+        }
+
         return 0;
 }
 
diff --git a/arch/mips/pci/pcie-octeon.c b/arch/mips/pci/pcie-octeon.c
index 0583c463e5f..fdb4d558c0c 100644
--- a/arch/mips/pci/pcie-octeon.c
+++ b/arch/mips/pci/pcie-octeon.c
@@ -3,7 +3,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 2007, 2008 Cavium Networks
+ * Copyright (C) 2007, 2008, 2009, 2010, 2011 Cavium Networks
  */
 #include <linux/kernel.h>
 #include <linux/init.h>
@@ -11,15 +11,32 @@
 #include <linux/interrupt.h>
 #include <linux/time.h>
 #include <linux/delay.h>
+#include <linux/module.h>
 
 #include <asm/octeon/octeon.h>
 #include <asm/octeon/cvmx-npei-defs.h>
 #include <asm/octeon/cvmx-pciercx-defs.h>
 #include <asm/octeon/cvmx-pescx-defs.h>
 #include <asm/octeon/cvmx-pexp-defs.h>
+#include <asm/octeon/cvmx-pemx-defs.h>
+#include <asm/octeon/cvmx-dpi-defs.h>
+#include <asm/octeon/cvmx-sli-defs.h>
+#include <asm/octeon/cvmx-sriox-defs.h>
 #include <asm/octeon/cvmx-helper-errata.h>
 #include <asm/octeon/pci-octeon.h>
 
+#define MRRS_CN5XXX 0 /* 128 byte Max Read Request Size */
+#define MPS_CN5XXX  0 /* 128 byte Max Packet Size (Limit of most PCs) */
+#define MRRS_CN6XXX 3 /* 1024 byte Max Read Request Size */
+#define MPS_CN6XXX  0 /* 128 byte Max Packet Size (Limit of most PCs) */
+
+/* Module parameter to disable PCI probing */
+static int pcie_disable;
+module_param(pcie_disable, int, S_IRUGO);
+
+static int enable_pcie_14459_war;
+static int enable_pcie_bus_num_war[2];
+
 union cvmx_pcie_address {
         uint64_t u64;
         struct {
@@ -75,6 +92,8 @@ union cvmx_pcie_address {
         } mem;
 };
 
+static int cvmx_pcie_rc_initialize(int pcie_port);
+
 #include <dma-coherence.h>
 
 /**
@@ -154,12 +173,21 @@ static inline uint64_t cvmx_pcie_get_mem_size(int pcie_port)
  */
 static uint32_t cvmx_pcie_cfgx_read(int pcie_port, uint32_t cfg_offset)
 {
-        union cvmx_pescx_cfg_rd pescx_cfg_rd;
-        pescx_cfg_rd.u64 = 0;
-        pescx_cfg_rd.s.addr = cfg_offset;
-        cvmx_write_csr(CVMX_PESCX_CFG_RD(pcie_port), pescx_cfg_rd.u64);
-        pescx_cfg_rd.u64 = cvmx_read_csr(CVMX_PESCX_CFG_RD(pcie_port));
-        return pescx_cfg_rd.s.data;
+        if (octeon_has_feature(OCTEON_FEATURE_NPEI)) {
+                union cvmx_pescx_cfg_rd pescx_cfg_rd;
+                pescx_cfg_rd.u64 = 0;
+                pescx_cfg_rd.s.addr = cfg_offset;
+                cvmx_write_csr(CVMX_PESCX_CFG_RD(pcie_port), pescx_cfg_rd.u64);
+                pescx_cfg_rd.u64 = cvmx_read_csr(CVMX_PESCX_CFG_RD(pcie_port));
+                return pescx_cfg_rd.s.data;
+        } else {
+                union cvmx_pemx_cfg_rd pemx_cfg_rd;
+                pemx_cfg_rd.u64 = 0;
+                pemx_cfg_rd.s.addr = cfg_offset;
+                cvmx_write_csr(CVMX_PEMX_CFG_RD(pcie_port), pemx_cfg_rd.u64);
+                pemx_cfg_rd.u64 = cvmx_read_csr(CVMX_PEMX_CFG_RD(pcie_port));
+                return pemx_cfg_rd.s.data;
+        }
 }
 
 /**
@@ -173,11 +201,19 @@ static uint32_t cvmx_pcie_cfgx_read(int pcie_port, uint32_t cfg_offset)
 static void cvmx_pcie_cfgx_write(int pcie_port, uint32_t cfg_offset,
                                  uint32_t val)
 {
-        union cvmx_pescx_cfg_wr pescx_cfg_wr;
-        pescx_cfg_wr.u64 = 0;
-        pescx_cfg_wr.s.addr = cfg_offset;
-        pescx_cfg_wr.s.data = val;
-        cvmx_write_csr(CVMX_PESCX_CFG_WR(pcie_port), pescx_cfg_wr.u64);
+        if (octeon_has_feature(OCTEON_FEATURE_NPEI)) {
+                union cvmx_pescx_cfg_wr pescx_cfg_wr;
+                pescx_cfg_wr.u64 = 0;
+                pescx_cfg_wr.s.addr = cfg_offset;
+                pescx_cfg_wr.s.data = val;
+                cvmx_write_csr(CVMX_PESCX_CFG_WR(pcie_port), pescx_cfg_wr.u64);
+        } else {
+                union cvmx_pemx_cfg_wr pemx_cfg_wr;
+                pemx_cfg_wr.u64 = 0;
+                pemx_cfg_wr.s.addr = cfg_offset;
+                pemx_cfg_wr.s.data = val;
+                cvmx_write_csr(CVMX_PEMX_CFG_WR(pcie_port), pemx_cfg_wr.u64);
+        }
 }
 
 /**
@@ -348,7 +384,6 @@ static void cvmx_pcie_config_write32(int pcie_port, int bus, int dev, int fn,
 static void __cvmx_pcie_rc_initialize_config_space(int pcie_port)
 {
         union cvmx_pciercx_cfg030 pciercx_cfg030;
-        union cvmx_npei_ctl_status2 npei_ctl_status2;
         union cvmx_pciercx_cfg070 pciercx_cfg070;
         union cvmx_pciercx_cfg001 pciercx_cfg001;
         union cvmx_pciercx_cfg032 pciercx_cfg032;
@@ -365,21 +400,21 @@ static void __cvmx_pcie_rc_initialize_config_space(int pcie_port)
         /* Max Read Request Size (PCIE*_CFG030[MRRS]) */
         /* Relaxed-order, no-snoop enables (PCIE*_CFG030[RO_EN,NS_EN] */
         /* Error Message Enables (PCIE*_CFG030[CE_EN,NFE_EN,FE_EN,UR_EN]) */
-        pciercx_cfg030.u32 =
-                cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG030(pcie_port));
-        /*
-         * Max payload size = 128 bytes for best Octeon DMA
-         * performance.
-         */
-        pciercx_cfg030.s.mps = 0;
+
+        pciercx_cfg030.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG030(pcie_port));
+        if (OCTEON_IS_MODEL(OCTEON_CN5XXX)) {
+                pciercx_cfg030.s.mps = MPS_CN5XXX;
+                pciercx_cfg030.s.mrrs = MRRS_CN5XXX;
+        } else {
+                pciercx_cfg030.s.mps = MPS_CN6XXX;
+                pciercx_cfg030.s.mrrs = MRRS_CN6XXX;
+        }
         /*
-         * Max read request size = 128 bytes for best Octeon DMA
-         * performance.
+         * Enable relaxed order processing. This will allow devices to
+         * affect read response ordering.
          */
-        pciercx_cfg030.s.mrrs = 0;
-        /* Enable relaxed ordering. */
         pciercx_cfg030.s.ro_en = 1;
-        /* Enable no snoop. */
+        /* Enable no snoop processing. Not used by Octeon */
         pciercx_cfg030.s.ns_en = 1;
         /* Correctable error reporting enable. */
         pciercx_cfg030.s.ce_en = 1;
@@ -389,50 +424,67 @@ static void __cvmx_pcie_rc_initialize_config_space(int pcie_port)
         pciercx_cfg030.s.fe_en = 1;
         /* Unsupported request reporting enable. */
         pciercx_cfg030.s.ur_en = 1;
-        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG030(pcie_port),
-                             pciercx_cfg030.u32);
+        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG030(pcie_port), pciercx_cfg030.u32);
 
-        /*
-         * Max Payload Size (NPEI_CTL_STATUS2[MPS]) must match
-         * PCIE*_CFG030[MPS]
-         *
-         * Max Read Request Size (NPEI_CTL_STATUS2[MRRS]) must not
-         * exceed PCIE*_CFG030[MRRS].
-         */
-        npei_ctl_status2.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS2);
-        /* Max payload size = 128 bytes for best Octeon DMA performance */
-        npei_ctl_status2.s.mps = 0;
-        /* Max read request size = 128 bytes for best Octeon DMA performance */
-        npei_ctl_status2.s.mrrs = 0;
-        if (pcie_port)
-                npei_ctl_status2.s.c1_b1_s = 3; /* Port1 BAR1 Size 256MB */
-        else
-                npei_ctl_status2.s.c0_b1_s = 3; /* Port0 BAR1 Size 256MB */
-        cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS2, npei_ctl_status2.u64);
+
+        if (octeon_has_feature(OCTEON_FEATURE_NPEI)) {
+                union cvmx_npei_ctl_status2 npei_ctl_status2;
+                /*
+                 * Max Payload Size (NPEI_CTL_STATUS2[MPS]) must match
+                 * PCIE*_CFG030[MPS].  Max Read Request Size
+                 * (NPEI_CTL_STATUS2[MRRS]) must not exceed
+                 * PCIE*_CFG030[MRRS]
+                 */
+                npei_ctl_status2.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS2);
+                /* Max payload size = 128 bytes for best Octeon DMA performance */
+                npei_ctl_status2.s.mps = MPS_CN5XXX;
+                /* Max read request size = 128 bytes for best Octeon DMA performance */
+                npei_ctl_status2.s.mrrs = MRRS_CN5XXX;
+                if (pcie_port)
+                        npei_ctl_status2.s.c1_b1_s = 3; /* Port1 BAR1 Size 256MB */
+                else
+                        npei_ctl_status2.s.c0_b1_s = 3; /* Port0 BAR1 Size 256MB */
+
+                cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS2, npei_ctl_status2.u64);
+        } else {
+                /*
+                 * Max Payload Size (DPI_SLI_PRTX_CFG[MPS]) must match
+                 * PCIE*_CFG030[MPS].  Max Read Request Size
+                 * (DPI_SLI_PRTX_CFG[MRRS]) must not exceed
+                 * PCIE*_CFG030[MRRS].
+                 */
+                union cvmx_dpi_sli_prtx_cfg prt_cfg;
+                union cvmx_sli_s2m_portx_ctl sli_s2m_portx_ctl;
+                prt_cfg.u64 = cvmx_read_csr(CVMX_DPI_SLI_PRTX_CFG(pcie_port));
+                prt_cfg.s.mps = MPS_CN6XXX;
+                prt_cfg.s.mrrs = MRRS_CN6XXX;
+                /* Max outstanding load request. */
+                prt_cfg.s.molr = 32;
+                cvmx_write_csr(CVMX_DPI_SLI_PRTX_CFG(pcie_port), prt_cfg.u64);
+
+                sli_s2m_portx_ctl.u64 = cvmx_read_csr(CVMX_PEXP_SLI_S2M_PORTX_CTL(pcie_port));
+                sli_s2m_portx_ctl.s.mrrs = MRRS_CN6XXX;
+                cvmx_write_csr(CVMX_PEXP_SLI_S2M_PORTX_CTL(pcie_port), sli_s2m_portx_ctl.u64);
+        }
 
         /* ECRC Generation (PCIE*_CFG070[GE,CE]) */
-        pciercx_cfg070.u32 =
-                cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG070(pcie_port));
+        pciercx_cfg070.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG070(pcie_port));
         pciercx_cfg070.s.ge = 1;        /* ECRC generation enable. */
         pciercx_cfg070.s.ce = 1;        /* ECRC check enable. */
-        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG070(pcie_port),
-                             pciercx_cfg070.u32);
+        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG070(pcie_port), pciercx_cfg070.u32);
 
         /*
-         * Access Enables (PCIE*_CFG001[MSAE,ME]) ME and MSAE should
-         * always be set.
-         *
-         * Interrupt Disable (PCIE*_CFG001[I_DIS]) System Error
-         * Message Enable (PCIE*_CFG001[SEE])
+         * Access Enables (PCIE*_CFG001[MSAE,ME])
+         * ME and MSAE should always be set.
+         * Interrupt Disable (PCIE*_CFG001[I_DIS])
+         * System Error Message Enable (PCIE*_CFG001[SEE])
          */
-        pciercx_cfg001.u32 =
-                cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG001(pcie_port));
+        pciercx_cfg001.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG001(pcie_port));
         pciercx_cfg001.s.msae = 1;      /* Memory space enable. */
         pciercx_cfg001.s.me = 1;        /* Bus master enable. */
         pciercx_cfg001.s.i_dis = 1;     /* INTx assertion disable. */
         pciercx_cfg001.s.see = 1;       /* SERR# enable */
-        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG001(pcie_port),
-                        pciercx_cfg001.u32);
+        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG001(pcie_port), pciercx_cfg001.u32);
 
         /* Advanced Error Recovery Message Enables */
         /* (PCIE*_CFG066,PCIE*_CFG067,PCIE*_CFG069) */
@@ -440,14 +492,11 @@ static void __cvmx_pcie_rc_initialize_config_space(int pcie_port)
         /* Use CVMX_PCIERCX_CFG067 hardware default */
         cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG069(pcie_port), 0);
 
-        /* Active State Power Management (PCIE*_CFG032[ASLPC]) */
-        pciercx_cfg032.u32 =
-                cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
-        pciercx_cfg032.s.aslpc = 0;     /* Active state Link PM control. */
-        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG032(pcie_port),
-                             pciercx_cfg032.u32);
 
-        /* Entrance Latencies (PCIE*_CFG451[L0EL,L1EL]) */
+        /* Active State Power Management (PCIE*_CFG032[ASLPC]) */
+        pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
+        pciercx_cfg032.s.aslpc = 0; /* Active state Link PM control. */
+        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG032(pcie_port), pciercx_cfg032.u32);
 
         /*
          * Link Width Mode (PCIERCn_CFG452[LME]) - Set during
@@ -462,8 +511,8 @@ static void __cvmx_pcie_rc_initialize_config_space(int pcie_port)
         pciercx_cfg006.s.pbnum = 1;
         pciercx_cfg006.s.sbnum = 1;
         pciercx_cfg006.s.subbnum = 1;
-        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG006(pcie_port),
-                             pciercx_cfg006.u32);
+        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG006(pcie_port), pciercx_cfg006.u32);
+
 
         /*
          * Memory-mapped I/O BAR (PCIERCn_CFG008)
@@ -473,8 +522,8 @@ static void __cvmx_pcie_rc_initialize_config_space(int pcie_port)
         pciercx_cfg008.u32 = 0;
         pciercx_cfg008.s.mb_addr = 0x100;
         pciercx_cfg008.s.ml_addr = 0;
-        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG008(pcie_port),
-                             pciercx_cfg008.u32);
+        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG008(pcie_port), pciercx_cfg008.u32);
+
 
         /*
          * Prefetchable BAR (PCIERCn_CFG009,PCIERCn_CFG010,PCIERCn_CFG011)
@@ -482,72 +531,51 @@ static void __cvmx_pcie_rc_initialize_config_space(int pcie_port)
          * PCIERCn_CFG011[UMEM_LIMIT],PCIERCn_CFG009[LMEM_LIMIT] <
          * PCIERCn_CFG010[UMEM_BASE],PCIERCn_CFG009[LMEM_BASE]
          */
-        pciercx_cfg009.u32 =
-                cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG009(pcie_port));
-        pciercx_cfg010.u32 =
-                cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG010(pcie_port));
-        pciercx_cfg011.u32 =
-                cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG011(pcie_port));
+        pciercx_cfg009.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG009(pcie_port));
+        pciercx_cfg010.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG010(pcie_port));
+        pciercx_cfg011.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG011(pcie_port));
         pciercx_cfg009.s.lmem_base = 0x100;
         pciercx_cfg009.s.lmem_limit = 0;
         pciercx_cfg010.s.umem_base = 0x100;
         pciercx_cfg011.s.umem_limit = 0;
-        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG009(pcie_port),
-                             pciercx_cfg009.u32);
-        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG010(pcie_port),
-                             pciercx_cfg010.u32);
-        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG011(pcie_port),
-                             pciercx_cfg011.u32);
+        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG009(pcie_port), pciercx_cfg009.u32);
+        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG010(pcie_port), pciercx_cfg010.u32);
+        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG011(pcie_port), pciercx_cfg011.u32);
 
         /*
          * System Error Interrupt Enables (PCIERCn_CFG035[SECEE,SEFEE,SENFEE])
          * PME Interrupt Enables (PCIERCn_CFG035[PMEIE])
-         */
-        pciercx_cfg035.u32 =
-                cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG035(pcie_port));
-        /* System error on correctable error enable. */
-        pciercx_cfg035.s.secee = 1;
-        /* System error on fatal error enable. */
-        pciercx_cfg035.s.sefee = 1;
-        /* System error on non-fatal error enable. */
-        pciercx_cfg035.s.senfee = 1;
-        /* PME interrupt enable. */
-        pciercx_cfg035.s.pmeie = 1;
-        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG035(pcie_port),
-                             pciercx_cfg035.u32);
+        */
+        pciercx_cfg035.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG035(pcie_port));
+        pciercx_cfg035.s.secee = 1; /* System error on correctable error enable. */
+        pciercx_cfg035.s.sefee = 1; /* System error on fatal error enable. */
+        pciercx_cfg035.s.senfee = 1; /* System error on non-fatal error enable. */
+        pciercx_cfg035.s.pmeie = 1; /* PME interrupt enable. */
+        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG035(pcie_port), pciercx_cfg035.u32);
 
         /*
          * Advanced Error Recovery Interrupt Enables
          * (PCIERCn_CFG075[CERE,NFERE,FERE])
          */
-        pciercx_cfg075.u32 =
-                cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG075(pcie_port));
-        /* Correctable error reporting enable. */
-        pciercx_cfg075.s.cere = 1;
-        /* Non-fatal error reporting enable. */
-        pciercx_cfg075.s.nfere = 1;
-        /* Fatal error reporting enable. */
-        pciercx_cfg075.s.fere = 1;
-        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG075(pcie_port),
-                             pciercx_cfg075.u32);
+        pciercx_cfg075.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG075(pcie_port));
+        pciercx_cfg075.s.cere = 1; /* Correctable error reporting enable. */
+        pciercx_cfg075.s.nfere = 1; /* Non-fatal error reporting enable. */
+        pciercx_cfg075.s.fere = 1; /* Fatal error reporting enable. */
+        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG075(pcie_port), pciercx_cfg075.u32);
 
-        /* HP Interrupt Enables (PCIERCn_CFG034[HPINT_EN],
+        /*
+         * HP Interrupt Enables (PCIERCn_CFG034[HPINT_EN],
          * PCIERCn_CFG034[DLLS_EN,CCINT_EN])
          */
-        pciercx_cfg034.u32 =
-                cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG034(pcie_port));
-        /* Hot-plug interrupt enable. */
-        pciercx_cfg034.s.hpint_en = 1;
-        /* Data Link Layer state changed enable */
-        pciercx_cfg034.s.dlls_en = 1;
-        /* Command completed interrupt enable. */
-        pciercx_cfg034.s.ccint_en = 1;
-        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG034(pcie_port),
-                             pciercx_cfg034.u32);
+        pciercx_cfg034.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG034(pcie_port));
+        pciercx_cfg034.s.hpint_en = 1; /* Hot-plug interrupt enable. */
+        pciercx_cfg034.s.dlls_en = 1; /* Data Link Layer state changed enable */
+        pciercx_cfg034.s.ccint_en = 1; /* Command completed interrupt enable. */
+        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG034(pcie_port), pciercx_cfg034.u32);
 }
 
 /**
- * Initialize a host mode PCIe link. This function takes a PCIe
+ * Initialize a host mode PCIe gen 1 link. This function takes a PCIe
  * port from reset to a link up state. Software can then begin
  * configuring the rest of the link.
  *
@@ -555,7 +583,7 @@ static void __cvmx_pcie_rc_initialize_config_space(int pcie_port)
  *
  * Returns Zero on success
  */
-static int __cvmx_pcie_rc_initialize_link(int pcie_port)
+static int __cvmx_pcie_rc_initialize_link_gen1(int pcie_port)
 {
         uint64_t start_cycle;
         union cvmx_pescx_ctl_status pescx_ctl_status;
@@ -564,18 +592,15 @@ static int __cvmx_pcie_rc_initialize_link(int pcie_port)
         union cvmx_pciercx_cfg448 pciercx_cfg448;
 
         /* Set the lane width */
-        pciercx_cfg452.u32 =
-            cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG452(pcie_port));
+        pciercx_cfg452.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG452(pcie_port));
         pescx_ctl_status.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS(pcie_port));
-        if (pescx_ctl_status.s.qlm_cfg == 0) {
+        if (pescx_ctl_status.s.qlm_cfg == 0)
                 /* We're in 8 lane (56XX) or 4 lane (54XX) mode */
                 pciercx_cfg452.s.lme = 0xf;
-        } else {
+        else
                 /* We're in 4 lane (56XX) or 2 lane (52XX) mode */
                 pciercx_cfg452.s.lme = 0x7;
-        }
-        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG452(pcie_port),
-                             pciercx_cfg452.u32);
+        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG452(pcie_port), pciercx_cfg452.u32);
 
         /*
          * CN52XX pass 1.x has an errata where length mismatches on UR
@@ -584,19 +609,15 @@ static int __cvmx_pcie_rc_initialize_link(int pcie_port)
          */
         if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
                 union cvmx_pciercx_cfg455 pciercx_cfg455;
-                pciercx_cfg455.u32 =
-                    cvmx_pcie_cfgx_read(pcie_port,
-                                        CVMX_PCIERCX_CFG455(pcie_port));
+                pciercx_cfg455.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG455(pcie_port));
                 pciercx_cfg455.s.m_cpl_len_err = 1;
-                cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG455(pcie_port),
-                                     pciercx_cfg455.u32);
+                cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG455(pcie_port), pciercx_cfg455.u32);
         }
 
         /* Lane swap needs to be manually enabled for CN52XX */
         if (OCTEON_IS_MODEL(OCTEON_CN52XX) && (pcie_port == 1)) {
                 pescx_ctl_status.s.lane_swp = 1;
-                cvmx_write_csr(CVMX_PESCX_CTL_STATUS(pcie_port),
-                               pescx_ctl_status.u64);
+                cvmx_write_csr(CVMX_PESCX_CTL_STATUS(pcie_port), pescx_ctl_status.u64);
         }
 
         /* Bring up the link */
@@ -612,24 +633,18 @@ static int __cvmx_pcie_rc_initialize_link(int pcie_port)
                 __cvmx_helper_errata_qlm_disable_2nd_order_cdr(0);
 
         /* Wait for the link to come up */
-        cvmx_dprintf("PCIe: Waiting for port %d link\n", pcie_port);
         start_cycle = cvmx_get_cycle();
         do {
-                if (cvmx_get_cycle() - start_cycle >
-                    2 * cvmx_sysinfo_get()->cpu_clock_hz) {
-                        cvmx_dprintf("PCIe: Port %d link timeout\n",
-                                     pcie_port);
+                if (cvmx_get_cycle() - start_cycle > 2 * octeon_get_clock_rate()) {
+                        cvmx_dprintf("PCIe: Port %d link timeout\n", pcie_port);
                         return -1;
                 }
                 cvmx_wait(10000);
-                pciercx_cfg032.u32 =
-                    cvmx_pcie_cfgx_read(pcie_port,
-                                        CVMX_PCIERCX_CFG032(pcie_port));
+                pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
         } while (pciercx_cfg032.s.dlla == 0);
 
-        /* Display the link status */
-        cvmx_dprintf("PCIe: Port %d link active, %d lanes\n", pcie_port,
-                     pciercx_cfg032.s.nlw);
+        /* Clear all pending errors */
+        cvmx_write_csr(CVMX_PEXP_NPEI_INT_SUM, cvmx_read_csr(CVMX_PEXP_NPEI_INT_SUM));
 
         /*
          * Update the Replay Time Limit. Empirically, some PCIe
@@ -639,8 +654,7 @@ static int __cvmx_pcie_rc_initialize_link(int pcie_port)
          * our actual 256 byte MPS. The numbers below are directly
          * from the PCIe spec table 3-4.
          */
-        pciercx_cfg448.u32 =
-            cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG448(pcie_port));
+        pciercx_cfg448.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG448(pcie_port));
         switch (pciercx_cfg032.s.nlw) {
         case 1:         /* 1 lane */
                 pciercx_cfg448.s.rtl = 1677;
@@ -655,21 +669,28 @@ static int __cvmx_pcie_rc_initialize_link(int pcie_port)
                 pciercx_cfg448.s.rtl = 258;
                 break;
         }
-        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG448(pcie_port),
-                             pciercx_cfg448.u32);
+        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG448(pcie_port), pciercx_cfg448.u32);
 
         return 0;
 }
 
+static void __cvmx_increment_ba(union cvmx_sli_mem_access_subidx *pmas)
+{
+        if (OCTEON_IS_MODEL(OCTEON_CN68XX))
+                pmas->cn68xx.ba++;
+        else
+                pmas->cn63xx.ba++;
+}
+
 /**
- * Initialize a PCIe port for use in host(RC) mode. It doesn't
+ * Initialize a PCIe gen 1 port for use in host(RC) mode. It doesn't
  * enumerate the bus.
  *
  * @pcie_port: PCIe port to initialize
  *
  * Returns Zero on success
  */
-static int cvmx_pcie_rc_initialize(int pcie_port)
+static int __cvmx_pcie_rc_initialize_gen1(int pcie_port)
 {
         int i;
         int base;
@@ -682,16 +703,17 @@ static int cvmx_pcie_rc_initialize(int pcie_port)
         union cvmx_npei_mem_access_subidx mem_access_subid;
         union cvmx_npei_dbg_data npei_dbg_data;
         union cvmx_pescx_ctl_status2 pescx_ctl_status2;
+        union cvmx_pciercx_cfg032 pciercx_cfg032;
         union cvmx_npei_bar1_indexx bar1_index;
 
+retry:
         /*
          * Make sure we aren't trying to setup a target mode interface
          * in host mode.
          */
         npei_ctl_status.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS);
         if ((pcie_port == 0) && !npei_ctl_status.s.host_mode) {
-                cvmx_dprintf("PCIe: ERROR: cvmx_pcie_rc_initialize() called "
-                             "on port0, but port0 is not in host mode\n");
+                cvmx_dprintf("PCIe: Port %d in endpoint mode\n", pcie_port);
                 return -1;
         }
 
@@ -702,9 +724,7 @@ static int cvmx_pcie_rc_initialize(int pcie_port)
         if (OCTEON_IS_MODEL(OCTEON_CN52XX)) {
                 npei_dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
                 if ((pcie_port == 1) && npei_dbg_data.cn52xx.qlm0_link_width) {
-                        cvmx_dprintf("PCIe: ERROR: cvmx_pcie_rc_initialize() "
-                                     "called on port1, but port1 is "
-                                     "disabled\n");
+                        cvmx_dprintf("PCIe: ERROR: cvmx_pcie_rc_initialize() called on port1, but port1 is disabled\n");
                         return -1;
                 }
         }
@@ -733,7 +753,7 @@ static int cvmx_pcie_rc_initialize(int pcie_port)
                  * the board. As a workaround for this bug, we bring
                  * both PCIe ports out of reset at the same time
                  * instead of on separate calls. So for port 0, we
-                 * bring both out of reset and do nothing on port 1.
+                 * bring both out of reset and do nothing on port 1
                  */
                 if (pcie_port == 0) {
                         ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
@@ -746,13 +766,10 @@ static int cvmx_pcie_rc_initialize(int pcie_port)
                         if (ciu_soft_prst.s.soft_prst == 0) {
                                 /* Reset the ports */
                                 ciu_soft_prst.s.soft_prst = 1;
-                                cvmx_write_csr(CVMX_CIU_SOFT_PRST,
-                                               ciu_soft_prst.u64);
-                                ciu_soft_prst.u64 =
-                                    cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
+                                cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
+                                ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
                                 ciu_soft_prst.s.soft_prst = 1;
-                                cvmx_write_csr(CVMX_CIU_SOFT_PRST1,
-                                               ciu_soft_prst.u64);
+                                cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
                                 /* Wait until pcie resets the ports. */
                                 udelay(2000);
                         }
@@ -782,11 +799,9 @@ static int cvmx_pcie_rc_initialize(int pcie_port)
                         /* Reset the port */
                         ciu_soft_prst.s.soft_prst = 1;
                         if (pcie_port)
-                                cvmx_write_csr(CVMX_CIU_SOFT_PRST1,
-                                               ciu_soft_prst.u64);
+                                cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
                         else
-                                cvmx_write_csr(CVMX_CIU_SOFT_PRST,
-                                               ciu_soft_prst.u64);
+                                cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
                         /* Wait until pcie resets the ports. */
                         udelay(2000);
                 }
@@ -808,25 +823,21 @@ static int cvmx_pcie_rc_initialize(int pcie_port)
          */
         cvmx_wait(400000);
 
-        /* PESCX_BIST_STATUS2[PCLK_RUN] was missing on pass 1 of CN56XX and
-           CN52XX, so we only probe it on newer chips */
-        if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)
-            && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
+        /*
+         * PESCX_BIST_STATUS2[PCLK_RUN] was missing on pass 1 of
+         * CN56XX and CN52XX, so we only probe it on newer chips
+         */
+        if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X) && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
                 /* Clear PCLK_RUN so we can check if the clock is running */
-                pescx_ctl_status2.u64 =
-                    cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(pcie_port));
+                pescx_ctl_status2.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(pcie_port));
                 pescx_ctl_status2.s.pclk_run = 1;
-                cvmx_write_csr(CVMX_PESCX_CTL_STATUS2(pcie_port),
-                               pescx_ctl_status2.u64);
-                /*
-                 * Now that we cleared PCLK_RUN, wait for it to be set
-                 * again telling us the clock is running.
+                cvmx_write_csr(CVMX_PESCX_CTL_STATUS2(pcie_port), pescx_ctl_status2.u64);
+                /* Now that we cleared PCLK_RUN, wait for it to be set
+                 * again telling us the clock is running
                  */
                 if (CVMX_WAIT_FOR_FIELD64(CVMX_PESCX_CTL_STATUS2(pcie_port),
-                                          union cvmx_pescx_ctl_status2,
-                                          pclk_run, ==, 1, 10000)) {
-                        cvmx_dprintf("PCIe: Port %d isn't clocked, skipping.\n",
-                                     pcie_port);
+                                          union cvmx_pescx_ctl_status2, pclk_run, ==, 1, 10000)) {
+                        cvmx_dprintf("PCIe: Port %d isn't clocked, skipping.\n", pcie_port);
                         return -1;
                 }
         }
@@ -836,30 +847,26 @@ static int cvmx_pcie_rc_initialize(int pcie_port)
          * the board probably hasn't wired the clocks up and the
          * interface should be skipped.
          */
-        pescx_ctl_status2.u64 =
-            cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(pcie_port));
+        pescx_ctl_status2.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(pcie_port));
         if (pescx_ctl_status2.s.pcierst) {
-                cvmx_dprintf("PCIe: Port %d stuck in reset, skipping.\n",
-                             pcie_port);
+                cvmx_dprintf("PCIe: Port %d stuck in reset, skipping.\n", pcie_port);
                 return -1;
         }
 
         /*
-         * Check BIST2 status. If any bits are set skip this interface. This
-         * is an attempt to catch PCIE-813 on pass 1 parts.
+         * Check BIST2 status. If any bits are set skip this
+         * interface. This is an attempt to catch PCIE-813 on pass 1
+         * parts.
          */
-        pescx_bist_status2.u64 =
-            cvmx_read_csr(CVMX_PESCX_BIST_STATUS2(pcie_port));
+        pescx_bist_status2.u64 = cvmx_read_csr(CVMX_PESCX_BIST_STATUS2(pcie_port));
         if (pescx_bist_status2.u64) {
-                cvmx_dprintf("PCIe: Port %d BIST2 failed. Most likely this "
-                             "port isn't hooked up, skipping.\n",
+                cvmx_dprintf("PCIe: Port %d BIST2 failed. Most likely this port isn't hooked up, skipping.\n",
                              pcie_port);
                 return -1;
         }
 
         /* Check BIST status */
-        pescx_bist_status.u64 =
-            cvmx_read_csr(CVMX_PESCX_BIST_STATUS(pcie_port));
+        pescx_bist_status.u64 = cvmx_read_csr(CVMX_PESCX_BIST_STATUS(pcie_port));
         if (pescx_bist_status.u64)
                 cvmx_dprintf("PCIe: BIST FAILED for port %d (0x%016llx)\n",
                              pcie_port, CAST64(pescx_bist_status.u64));
@@ -868,50 +875,37 @@ static int cvmx_pcie_rc_initialize(int pcie_port)
         __cvmx_pcie_rc_initialize_config_space(pcie_port);
 
         /* Bring the link up */
-        if (__cvmx_pcie_rc_initialize_link(pcie_port)) {
-                cvmx_dprintf
-                    ("PCIe: ERROR: cvmx_pcie_rc_initialize_link() failed\n");
+        if (__cvmx_pcie_rc_initialize_link_gen1(pcie_port)) {
+                cvmx_dprintf("PCIe: Failed to initialize port %d, probably the slot is empty\n",
+                             pcie_port);
                 return -1;
         }
 
         /* Store merge control (NPEI_MEM_ACCESS_CTL[TIMER,MAX_WORD]) */
         npei_mem_access_ctl.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL);
-        /* Allow 16 words to combine */
-        npei_mem_access_ctl.s.max_word = 0;
-        /* Wait up to 127 cycles for more data */
-        npei_mem_access_ctl.s.timer = 127;
+        npei_mem_access_ctl.s.max_word = 0;     /* Allow 16 words to combine */
+        npei_mem_access_ctl.s.timer = 127;      /* Wait up to 127 cycles for more data */
         cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL, npei_mem_access_ctl.u64);
 
         /* Setup Mem access SubDIDs */
         mem_access_subid.u64 = 0;
-        /* Port the request is sent to. */
-        mem_access_subid.s.port = pcie_port;
-        /* Due to an errata on pass 1 chips, no merging is allowed. */
-        mem_access_subid.s.nmerge = 1;
-        /* Endian-swap for Reads. */
-        mem_access_subid.s.esr = 1;
-        /* Endian-swap for Writes. */
-        mem_access_subid.s.esw = 1;
-        /* No Snoop for Reads. */
-        mem_access_subid.s.nsr = 1;
-        /* No Snoop for Writes. */
-        mem_access_subid.s.nsw = 1;
-        /* Disable Relaxed Ordering for Reads. */
-        mem_access_subid.s.ror = 0;
-        /* Disable Relaxed Ordering for Writes. */
-        mem_access_subid.s.row = 0;
-        /* PCIe Address Bits <63:34>. */
-        mem_access_subid.s.ba = 0;
+        mem_access_subid.s.port = pcie_port; /* Port the request is sent to. */
+        mem_access_subid.s.nmerge = 1;  /* Due to an errata on pass 1 chips, no merging is allowed. */
+        mem_access_subid.s.esr = 1;     /* Endian-swap for Reads. */
+        mem_access_subid.s.esw = 1;     /* Endian-swap for Writes. */
+        mem_access_subid.s.nsr = 0;     /* Enable Snooping for Reads. Octeon doesn't care, but devices might want this more conservative setting */
+        mem_access_subid.s.nsw = 0;     /* Enable Snoop for Writes. */
+        mem_access_subid.s.ror = 0;     /* Disable Relaxed Ordering for Reads. */
+        mem_access_subid.s.row = 0;     /* Disable Relaxed Ordering for Writes. */
+        mem_access_subid.s.ba = 0;      /* PCIe Adddress Bits <63:34>. */
 
         /*
          * Setup mem access 12-15 for port 0, 16-19 for port 1,
          * supplying 36 bits of address space.
          */
         for (i = 12 + pcie_port * 4; i < 16 + pcie_port * 4; i++) {
-                cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(i),
-                               mem_access_subid.u64);
-                /* Set each SUBID to extend the addressable range */
-                mem_access_subid.s.ba += 1;
+                cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(i), mem_access_subid.u64);
+                mem_access_subid.s.ba += 1; /* Set each SUBID to extend the addressable range */
         }
 
         /*
@@ -927,7 +921,7 @@ static int cvmx_pcie_rc_initialize(int pcie_port)
         /* Set Octeon's BAR0 to decode 0-16KB. It overlaps with Bar2 */
         cvmx_write_csr(CVMX_PESCX_P2N_BAR0_START(pcie_port), 0);
 
-        /* BAR1 follows BAR2 with a gap. */
+        /* BAR1 follows BAR2 with a gap so it has the same address as for gen2. */
         cvmx_write_csr(CVMX_PESCX_P2N_BAR1_START(pcie_port), CVMX_PCIE_BAR1_RC_BASE);
 
         bar1_index.u32 = 0;
@@ -992,14 +986,474 @@ static int cvmx_pcie_rc_initialize(int pcie_port)
                 npei_ctl_port.s.waitl_com = 0;
                 cvmx_write_csr(CVMX_PEXP_NPEI_CTL_PORT0, npei_ctl_port.u64);
         }
+
+        /*
+         * Both pass 1 and pass 2 of CN52XX and CN56XX have an errata
+         * that causes TLP ordering to not be preserved after multiple
+         * PCIe port resets. This code detects this fault and corrects
+         * it by aligning the TLP counters properly. Another link
+         * reset is then performed. See PCIE-13340
+         */
+        if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS2_X) ||
+            OCTEON_IS_MODEL(OCTEON_CN52XX_PASS2_X) ||
+            OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X) ||
+            OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
+                union cvmx_npei_dbg_data dbg_data;
+                int old_in_fif_p_count;
+                int in_fif_p_count;
+                int out_p_count;
+                int in_p_offset = (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)) ? 4 : 1;
+                int i;
+
+                /*
+                 * Choose a write address of 1MB. It should be
+                 * harmless as all bars haven't been setup.
+                 */
+                uint64_t write_address = (cvmx_pcie_get_mem_base_address(pcie_port) + 0x100000) | (1ull<<63);
+
+                /*
+                 * Make sure at least in_p_offset have been executed before we try and
+                 * read in_fif_p_count
+                 */
+                i = in_p_offset;
+                while (i--) {
+                        cvmx_write64_uint32(write_address, 0);
+                        cvmx_wait(10000);
+                }
+
+                /*
+                 * Read the IN_FIF_P_COUNT from the debug
+                 * select. IN_FIF_P_COUNT can be unstable sometimes so
+                 * read it twice with a write between the reads.  This
+                 * way we can tell the value is good as it will
+                 * increment by one due to the write
+                 */
+                cvmx_write_csr(CVMX_PEXP_NPEI_DBG_SELECT, (pcie_port) ? 0xd7fc : 0xcffc);
+                cvmx_read_csr(CVMX_PEXP_NPEI_DBG_SELECT);
+                do {
+                        dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
+                        old_in_fif_p_count = dbg_data.s.data & 0xff;
+                        cvmx_write64_uint32(write_address, 0);
+                        cvmx_wait(10000);
+                        dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
+                        in_fif_p_count = dbg_data.s.data & 0xff;
+                } while (in_fif_p_count != ((old_in_fif_p_count+1) & 0xff));
+
+                /* Update in_fif_p_count for it's offset with respect to out_p_count */
+                in_fif_p_count = (in_fif_p_count + in_p_offset) & 0xff;
+
+                /* Read the OUT_P_COUNT from the debug select */
+                cvmx_write_csr(CVMX_PEXP_NPEI_DBG_SELECT, (pcie_port) ? 0xd00f : 0xc80f);
+                cvmx_read_csr(CVMX_PEXP_NPEI_DBG_SELECT);
+                dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
+                out_p_count = (dbg_data.s.data>>1) & 0xff;
+
+                /* Check that the two counters are aligned */
+                if (out_p_count != in_fif_p_count) {
+                        cvmx_dprintf("PCIe: Port %d aligning TLP counters as workaround to maintain ordering\n", pcie_port);
+                        while (in_fif_p_count != 0) {
+                                cvmx_write64_uint32(write_address, 0);
+                                cvmx_wait(10000);
+                                in_fif_p_count = (in_fif_p_count + 1) & 0xff;
+                        }
+                        /*
+                         * The EBH5200 board swapped the PCIe reset
+                         * lines on the board. This means we must
+                         * bring both links down and up, which will
+                         * cause the PCIe0 to need alignment
+                         * again. Lots of messages will be displayed,
+                         * but everything should work
+                         */
+                        if ((cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_EBH5200) &&
+                                (pcie_port == 1))
+                                cvmx_pcie_rc_initialize(0);
+                        /* Rety bringing this port up */
+                        goto retry;
+                }
+        }
+
+        /* Display the link status */
+        pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
+        cvmx_dprintf("PCIe: Port %d link active, %d lanes\n", pcie_port, pciercx_cfg032.s.nlw);
+
         return 0;
 }
 
+/**
+  * Initialize a host mode PCIe gen 2 link. This function takes a PCIe
+ * port from reset to a link up state. Software can then begin
+ * configuring the rest of the link.
+ *
+ * @pcie_port: PCIe port to initialize
+ *
+ * Return Zero on success.
+ */
+static int __cvmx_pcie_rc_initialize_link_gen2(int pcie_port)
+{
+        uint64_t start_cycle;
+        union cvmx_pemx_ctl_status pem_ctl_status;
+        union cvmx_pciercx_cfg032 pciercx_cfg032;
+        union cvmx_pciercx_cfg448 pciercx_cfg448;
 
-/* Above was cvmx-pcie.c, below original pcie.c */
+        /* Bring up the link */
+        pem_ctl_status.u64 = cvmx_read_csr(CVMX_PEMX_CTL_STATUS(pcie_port));
+        pem_ctl_status.s.lnk_enb = 1;
+        cvmx_write_csr(CVMX_PEMX_CTL_STATUS(pcie_port), pem_ctl_status.u64);
+
+        /* Wait for the link to come up */
+        start_cycle = cvmx_get_cycle();
+        do {
+                if (cvmx_get_cycle() - start_cycle >  octeon_get_clock_rate())
+                        return -1;
+                cvmx_wait(10000);
+                pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
+        } while ((pciercx_cfg032.s.dlla == 0) || (pciercx_cfg032.s.lt == 1));
+
+        /*
+         * Update the Replay Time Limit. Empirically, some PCIe
+         * devices take a little longer to respond than expected under
+         * load. As a workaround for this we configure the Replay Time
+         * Limit to the value expected for a 512 byte MPS instead of
+         * our actual 256 byte MPS. The numbers below are directly
+         * from the PCIe spec table 3-4
+         */
+        pciercx_cfg448.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG448(pcie_port));
+        switch (pciercx_cfg032.s.nlw) {
+        case 1: /* 1 lane */
+                pciercx_cfg448.s.rtl = 1677;
+                break;
+        case 2: /* 2 lanes */
+                pciercx_cfg448.s.rtl = 867;
+                break;
+        case 4: /* 4 lanes */
+                pciercx_cfg448.s.rtl = 462;
+                break;
+        case 8: /* 8 lanes */
+                pciercx_cfg448.s.rtl = 258;
+                break;
+        }
+        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG448(pcie_port), pciercx_cfg448.u32);
+
+        return 0;
+}
 
 
 /**
+ * Initialize a PCIe gen 2 port for use in host(RC) mode. It doesn't enumerate
+ * the bus.
+ *
+ * @pcie_port: PCIe port to initialize
+ *
+ * Returns Zero on success.
+ */
+static int __cvmx_pcie_rc_initialize_gen2(int pcie_port)
+{
+        int i;
+        union cvmx_ciu_soft_prst ciu_soft_prst;
+        union cvmx_mio_rst_ctlx mio_rst_ctl;
+        union cvmx_pemx_bar_ctl pemx_bar_ctl;
+        union cvmx_pemx_ctl_status pemx_ctl_status;
+        union cvmx_pemx_bist_status pemx_bist_status;
+        union cvmx_pemx_bist_status2 pemx_bist_status2;
+        union cvmx_pciercx_cfg032 pciercx_cfg032;
+        union cvmx_pciercx_cfg515 pciercx_cfg515;
+        union cvmx_sli_ctl_portx sli_ctl_portx;
+        union cvmx_sli_mem_access_ctl sli_mem_access_ctl;
+        union cvmx_sli_mem_access_subidx mem_access_subid;
+        union cvmx_sriox_status_reg sriox_status_reg;
+        union cvmx_pemx_bar1_indexx bar1_index;
+
+        if (octeon_has_feature(OCTEON_FEATURE_SRIO)) {
+                /* Make sure this interface isn't SRIO */
+                if (OCTEON_IS_MODEL(OCTEON_CN66XX)) {
+                        /*
+                         * The CN66XX requires reading the
+                         * MIO_QLMX_CFG register to figure out the
+                         * port type.
+                         */
+                        union cvmx_mio_qlmx_cfg qlmx_cfg;
+                        qlmx_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(pcie_port));
+
+                        if (qlmx_cfg.s.qlm_spd == 15) {
+                                pr_notice("PCIe: Port %d is disabled, skipping.\n", pcie_port);
+                                return -1;
+                        }
+
+                        switch (qlmx_cfg.s.qlm_spd) {
+                        case 0x1: /* SRIO 1x4 short */
+                        case 0x3: /* SRIO 1x4 long */
+                        case 0x4: /* SRIO 2x2 short */
+                        case 0x6: /* SRIO 2x2 long */
+                                pr_notice("PCIe: Port %d is SRIO, skipping.\n", pcie_port);
+                                return -1;
+                        case 0x9: /* SGMII */
+                                pr_notice("PCIe: Port %d is SGMII, skipping.\n", pcie_port);
+                                return -1;
+                        case 0xb: /* XAUI */
+                                pr_notice("PCIe: Port %d is XAUI, skipping.\n", pcie_port);
+                                return -1;
+                        case 0x0: /* PCIE gen2 */
+                        case 0x8: /* PCIE gen2 (alias) */
+                        case 0x2: /* PCIE gen1 */
+                        case 0xa: /* PCIE gen1 (alias) */
+                                break;
+                        default:
+                                pr_notice("PCIe: Port %d is unknown, skipping.\n", pcie_port);
+                                return -1;
+                        }
+                } else {
+                        sriox_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(pcie_port));
+                        if (sriox_status_reg.s.srio) {
+                                pr_notice("PCIe: Port %d is SRIO, skipping.\n", pcie_port);
+                                return -1;
+                        }
+                }
+        }
+
+#if 0
+    /* This code is so that the PCIe analyzer is able to see 63XX traffic */
+        pr_notice("PCIE : init for pcie analyzer.\n");
+        cvmx_helper_qlm_jtag_init();
+        cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 85);
+        cvmx_helper_qlm_jtag_shift(pcie_port, 1, 1);
+        cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 300-86);
+        cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 85);
+        cvmx_helper_qlm_jtag_shift(pcie_port, 1, 1);
+        cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 300-86);
+        cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 85);
+        cvmx_helper_qlm_jtag_shift(pcie_port, 1, 1);
+        cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 300-86);
+        cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 85);
+        cvmx_helper_qlm_jtag_shift(pcie_port, 1, 1);
+        cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 300-86);
+        cvmx_helper_qlm_jtag_update(pcie_port);
+#endif
+
+        /* Make sure we aren't trying to setup a target mode interface in host mode */
+        mio_rst_ctl.u64 = cvmx_read_csr(CVMX_MIO_RST_CTLX(pcie_port));
+        if (!mio_rst_ctl.s.host_mode) {
+                pr_notice("PCIe: Port %d in endpoint mode.\n", pcie_port);
+                return -1;
+        }
+
+        /* CN63XX Pass 1.0 errata G-14395 requires the QLM De-emphasis be programmed */
+        if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_0)) {
+                if (pcie_port) {
+                        union cvmx_ciu_qlm1 ciu_qlm;
+                        ciu_qlm.u64 = cvmx_read_csr(CVMX_CIU_QLM1);
+                        ciu_qlm.s.txbypass = 1;
+                        ciu_qlm.s.txdeemph = 5;
+                        ciu_qlm.s.txmargin = 0x17;
+                        cvmx_write_csr(CVMX_CIU_QLM1, ciu_qlm.u64);
+                } else {
+                        union cvmx_ciu_qlm0 ciu_qlm;
+                        ciu_qlm.u64 = cvmx_read_csr(CVMX_CIU_QLM0);
+                        ciu_qlm.s.txbypass = 1;
+                        ciu_qlm.s.txdeemph = 5;
+                        ciu_qlm.s.txmargin = 0x17;
+                        cvmx_write_csr(CVMX_CIU_QLM0, ciu_qlm.u64);
+                }
+        }
+        /* Bring the PCIe out of reset */
+        if (pcie_port)
+                ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
+        else
+                ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
+        /*
+         * After a chip reset the PCIe will also be in reset. If it
+         * isn't, most likely someone is trying to init it again
+         * without a proper PCIe reset
+         */
+        if (ciu_soft_prst.s.soft_prst == 0) {
+                /* Reset the port */
+                ciu_soft_prst.s.soft_prst = 1;
+                if (pcie_port)
+                        cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
+                else
+                        cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
+                /* Wait until pcie resets the ports. */
+                udelay(2000);
+        }
+        if (pcie_port) {
+                ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
+                ciu_soft_prst.s.soft_prst = 0;
+                cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
+        } else {
+                ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
+                ciu_soft_prst.s.soft_prst = 0;
+                cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
+        }
+
+        /* Wait for PCIe reset to complete */
+        udelay(1000);
+
+        /*
+         * Check and make sure PCIe came out of reset. If it doesn't
+         * the board probably hasn't wired the clocks up and the
+         * interface should be skipped.
+         */
+        if (CVMX_WAIT_FOR_FIELD64(CVMX_MIO_RST_CTLX(pcie_port), union cvmx_mio_rst_ctlx, rst_done, ==, 1, 10000)) {
+                pr_notice("PCIe: Port %d stuck in reset, skipping.\n", pcie_port);
+                return -1;
+        }
+
+        /* Check BIST status */
+        pemx_bist_status.u64 = cvmx_read_csr(CVMX_PEMX_BIST_STATUS(pcie_port));
+        if (pemx_bist_status.u64)
+                pr_notice("PCIe: BIST FAILED for port %d (0x%016llx)\n", pcie_port, CAST64(pemx_bist_status.u64));
+        pemx_bist_status2.u64 = cvmx_read_csr(CVMX_PEMX_BIST_STATUS2(pcie_port));
+        /* Errata PCIE-14766 may cause the lower 6 bits to be randomly set on CN63XXp1 */
+        if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X))
+                pemx_bist_status2.u64 &= ~0x3full;
+        if (pemx_bist_status2.u64)
+                pr_notice("PCIe: BIST2 FAILED for port %d (0x%016llx)\n", pcie_port, CAST64(pemx_bist_status2.u64));
+
+        /* Initialize the config space CSRs */
+        __cvmx_pcie_rc_initialize_config_space(pcie_port);
+
+        /* Enable gen2 speed selection */
+        pciercx_cfg515.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG515(pcie_port));
+        pciercx_cfg515.s.dsc = 1;
+        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG515(pcie_port), pciercx_cfg515.u32);
+
+        /* Bring the link up */
+        if (__cvmx_pcie_rc_initialize_link_gen2(pcie_port)) {
+                /*
+                 * Some gen1 devices don't handle the gen 2 training
+                 * correctly. Disable gen2 and try again with only
+                 * gen1
+                 */
+                union cvmx_pciercx_cfg031 pciercx_cfg031;
+                pciercx_cfg031.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG031(pcie_port));
+                pciercx_cfg031.s.mls = 1;
+                cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG031(pcie_port), pciercx_cfg031.u32);
+                if (__cvmx_pcie_rc_initialize_link_gen2(pcie_port)) {
+                        pr_notice("PCIe: Link timeout on port %d, probably the slot is empty\n", pcie_port);
+                        return -1;
+                }
+        }
+
+        /* Store merge control (SLI_MEM_ACCESS_CTL[TIMER,MAX_WORD]) */
+        sli_mem_access_ctl.u64 = cvmx_read_csr(CVMX_PEXP_SLI_MEM_ACCESS_CTL);
+        sli_mem_access_ctl.s.max_word = 0;      /* Allow 16 words to combine */
+        sli_mem_access_ctl.s.timer = 127;       /* Wait up to 127 cycles for more data */
+        cvmx_write_csr(CVMX_PEXP_SLI_MEM_ACCESS_CTL, sli_mem_access_ctl.u64);
+
+        /* Setup Mem access SubDIDs */
+        mem_access_subid.u64 = 0;
+        mem_access_subid.s.port = pcie_port; /* Port the request is sent to. */
+        mem_access_subid.s.nmerge = 0;  /* Allow merging as it works on CN6XXX. */
+        mem_access_subid.s.esr = 1;     /* Endian-swap for Reads. */
+        mem_access_subid.s.esw = 1;     /* Endian-swap for Writes. */
+        mem_access_subid.s.wtype = 0;   /* "No snoop" and "Relaxed ordering" are not set */
+        mem_access_subid.s.rtype = 0;   /* "No snoop" and "Relaxed ordering" are not set */
+        /* PCIe Adddress Bits <63:34>. */
+        if (OCTEON_IS_MODEL(OCTEON_CN68XX))
+                mem_access_subid.cn68xx.ba = 0;
+        else
+                mem_access_subid.cn63xx.ba = 0;
+
+        /*
+         * Setup mem access 12-15 for port 0, 16-19 for port 1,
+         * supplying 36 bits of address space.
+         */
+        for (i = 12 + pcie_port * 4; i < 16 + pcie_port * 4; i++) {
+                cvmx_write_csr(CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(i), mem_access_subid.u64);
+                /* Set each SUBID to extend the addressable range */
+                __cvmx_increment_ba(&mem_access_subid);
+        }
+
+        /*
+         * Disable the peer to peer forwarding register. This must be
+         * setup by the OS after it enumerates the bus and assigns
+         * addresses to the PCIe busses.
+         */
+        for (i = 0; i < 4; i++) {
+                cvmx_write_csr(CVMX_PEMX_P2P_BARX_START(i, pcie_port), -1);
+                cvmx_write_csr(CVMX_PEMX_P2P_BARX_END(i, pcie_port), -1);
+        }
+
+        /* Set Octeon's BAR0 to decode 0-16KB. It overlaps with Bar2 */
+        cvmx_write_csr(CVMX_PEMX_P2N_BAR0_START(pcie_port), 0);
+
+        /*
+         * Set Octeon's BAR2 to decode 0-2^41. Bar0 and Bar1 take
+         * precedence where they overlap. It also overlaps with the
+         * device addresses, so make sure the peer to peer forwarding
+         * is set right.
+         */
+        cvmx_write_csr(CVMX_PEMX_P2N_BAR2_START(pcie_port), 0);
+
+        /*
+         * Setup BAR2 attributes
+         * Relaxed Ordering (NPEI_CTL_PORTn[PTLP_RO,CTLP_RO, WAIT_COM])
+         * - PTLP_RO,CTLP_RO should normally be set (except for debug).
+         * - WAIT_COM=0 will likely work for all applications.
+         * Load completion relaxed ordering (NPEI_CTL_PORTn[WAITL_COM])
+         */
+        pemx_bar_ctl.u64 = cvmx_read_csr(CVMX_PEMX_BAR_CTL(pcie_port));
+        pemx_bar_ctl.s.bar1_siz = 3;  /* 256MB BAR1*/
+        pemx_bar_ctl.s.bar2_enb = 1;
+        pemx_bar_ctl.s.bar2_esx = 1;
+        pemx_bar_ctl.s.bar2_cax = 0;
+        cvmx_write_csr(CVMX_PEMX_BAR_CTL(pcie_port), pemx_bar_ctl.u64);
+        sli_ctl_portx.u64 = cvmx_read_csr(CVMX_PEXP_SLI_CTL_PORTX(pcie_port));
+        sli_ctl_portx.s.ptlp_ro = 1;
+        sli_ctl_portx.s.ctlp_ro = 1;
+        sli_ctl_portx.s.wait_com = 0;
+        sli_ctl_portx.s.waitl_com = 0;
+        cvmx_write_csr(CVMX_PEXP_SLI_CTL_PORTX(pcie_port), sli_ctl_portx.u64);
+
+        /* BAR1 follows BAR2 */
+        cvmx_write_csr(CVMX_PEMX_P2N_BAR1_START(pcie_port), CVMX_PCIE_BAR1_RC_BASE);
+
+        bar1_index.u64 = 0;
+        bar1_index.s.addr_idx = (CVMX_PCIE_BAR1_PHYS_BASE >> 22);
+        bar1_index.s.ca = 1;       /* Not Cached */
+        bar1_index.s.end_swp = 1;  /* Endian Swap mode */
+        bar1_index.s.addr_v = 1;   /* Valid entry */
+
+        for (i = 0; i < 16; i++) {
+                cvmx_write_csr(CVMX_PEMX_BAR1_INDEXX(i, pcie_port), bar1_index.u64);
+                /* 256MB / 16 >> 22 == 4 */
+                bar1_index.s.addr_idx += (((1ull << 28) / 16ull) >> 22);
+        }
+
+        /*
+         * Allow config retries for 250ms. Count is based off the 5Ghz
+         * SERDES clock.
+         */
+        pemx_ctl_status.u64 = cvmx_read_csr(CVMX_PEMX_CTL_STATUS(pcie_port));
+        pemx_ctl_status.s.cfg_rtry = 250 * 5000000 / 0x10000;
+        cvmx_write_csr(CVMX_PEMX_CTL_STATUS(pcie_port), pemx_ctl_status.u64);
+
+        /* Display the link status */
+        pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
+        pr_notice("PCIe: Port %d link active, %d lanes, speed gen%d\n", pcie_port, pciercx_cfg032.s.nlw, pciercx_cfg032.s.ls);
+
+        return 0;
+}
+
+/**
+ * Initialize a PCIe port for use in host(RC) mode. It doesn't enumerate the bus.
+ *
+ * @pcie_port: PCIe port to initialize
+ *
+ * Returns Zero on success
+ */
+static int cvmx_pcie_rc_initialize(int pcie_port)
+{
+        int result;
+        if (octeon_has_feature(OCTEON_FEATURE_NPEI))
+                result = __cvmx_pcie_rc_initialize_gen1(pcie_port);
+        else
+                result = __cvmx_pcie_rc_initialize_gen2(pcie_port);
+        return result;
+}
+
+/* Above was cvmx-pcie.c, below original pcie.c */
+
+/**
  * Map a PCI device to the appropriate interrupt line
  *
  * @dev:    The Linux PCI device structure for the device to map
@@ -1027,11 +1481,12 @@ int __init octeon_pcie_pcibios_map_irq(const struct pci_dev *dev,
                  */
                 while (dev->bus && dev->bus->parent)
                         dev = to_pci_dev(dev->bus->bridge);
-                /* If the root bus is number 0 and the PEX 8114 is the
+                /*
+                 * If the root bus is number 0 and the PEX 8114 is the
                  * root, assume we are behind the miswired bus. We
                  * need to correct the swizzle level by two. Yuck.
                  */
-                if ((dev->bus->number == 0) &&
+                if ((dev->bus->number == 1) &&
                     (dev->vendor == 0x10b5) && (dev->device == 0x8114)) {
                         /*
                          * The pin field is one based, not zero. We
@@ -1048,39 +1503,73 @@ int __init octeon_pcie_pcibios_map_irq(const struct pci_dev *dev,
         return pin - 1 + OCTEON_IRQ_PCI_INT0;
 }
 
-/**
+static  void set_cfg_read_retry(u32 retry_cnt)
+{
+        union cvmx_pemx_ctl_status pemx_ctl;
+        pemx_ctl.u64 = cvmx_read_csr(CVMX_PEMX_CTL_STATUS(1));
+        pemx_ctl.s.cfg_rtry = retry_cnt;
+        cvmx_write_csr(CVMX_PEMX_CTL_STATUS(1), pemx_ctl.u64);
+}
+
+
+static u32 disable_cfg_read_retry(void)
+{
+        u32 retry_cnt;
+
+        union cvmx_pemx_ctl_status pemx_ctl;
+        pemx_ctl.u64 = cvmx_read_csr(CVMX_PEMX_CTL_STATUS(1));
+        retry_cnt =  pemx_ctl.s.cfg_rtry;
+        pemx_ctl.s.cfg_rtry = 0;
+        cvmx_write_csr(CVMX_PEMX_CTL_STATUS(1), pemx_ctl.u64);
+        return retry_cnt;
+}
+
+static int is_cfg_retry(void)
+{
+        union cvmx_pemx_int_sum pemx_int_sum;
+        pemx_int_sum.u64 = cvmx_read_csr(CVMX_PEMX_INT_SUM(1));
+        if (pemx_int_sum.s.crs_dr)
+                return 1;
+        return 0;
+}
+
+/*
  * Read a value from configuration space
  *
- * @bus:
- * @devfn:
- * @reg:
- * @size:
- * @val:
- * Returns
  */
-static inline int octeon_pcie_read_config(int pcie_port, struct pci_bus *bus,
-                                          unsigned int devfn, int reg, int size,
-                                          u32 *val)
+static int octeon_pcie_read_config(unsigned int pcie_port, struct pci_bus *bus,
+                                   unsigned int devfn, int reg, int size,
+                                   u32 *val)
 {
         union octeon_cvmemctl cvmmemctl;
         union octeon_cvmemctl cvmmemctl_save;
         int bus_number = bus->number;
+        int cfg_retry = 0;
+        int retry_cnt = 0;
+        int max_retry_cnt = 10;
+        u32 cfg_retry_cnt = 0;
 
+        cvmmemctl_save.u64 = 0;
+        BUG_ON(pcie_port >= ARRAY_SIZE(enable_pcie_bus_num_war));
         /*
          * For the top level bus make sure our hardware bus number
-         * matches the software one.
+         * matches the software one
          */
         if (bus->parent == NULL) {
-                union cvmx_pciercx_cfg006 pciercx_cfg006;
-                pciercx_cfg006.u32 = cvmx_pcie_cfgx_read(pcie_port,
-                        CVMX_PCIERCX_CFG006(pcie_port));
-                if (pciercx_cfg006.s.pbnum != bus_number) {
-                        pciercx_cfg006.s.pbnum = bus_number;
-                        pciercx_cfg006.s.sbnum = bus_number;
-                        pciercx_cfg006.s.subbnum = bus_number;
-                        cvmx_pcie_cfgx_write(pcie_port,
-                                CVMX_PCIERCX_CFG006(pcie_port),
-                                pciercx_cfg006.u32);
+                if (enable_pcie_bus_num_war[pcie_port])
+                        bus_number = 0;
+                else {
+                        union cvmx_pciercx_cfg006 pciercx_cfg006;
+                        pciercx_cfg006.u32 = cvmx_pcie_cfgx_read(pcie_port,
+                                             CVMX_PCIERCX_CFG006(pcie_port));
+                        if (pciercx_cfg006.s.pbnum != bus_number) {
+                                pciercx_cfg006.s.pbnum = bus_number;
+                                pciercx_cfg006.s.sbnum = bus_number;
+                                pciercx_cfg006.s.subbnum = bus_number;
+                                cvmx_pcie_cfgx_write(pcie_port,
+                                            CVMX_PCIERCX_CFG006(pcie_port),
+                                            pciercx_cfg006.u32);
+                        }
                 }
         }
 
@@ -1116,29 +1605,52 @@ static inline int octeon_pcie_read_config(int pcie_port, struct pci_bus *bus,
                  */
 #if 1
                 /* Use this option if you aren't using either slot */
-                if (bus_number == 1)
+                if (bus_number == 2)
                         return PCIBIOS_FUNC_NOT_SUPPORTED;
 #elif 0
                 /*
                  * Use this option if you are using the first slot but
                  * not the second.
                  */
-                if ((bus_number == 1) && (devfn >> 3 != 2))
+                if ((bus_number == 2) && (devfn >> 3 != 2))
                         return PCIBIOS_FUNC_NOT_SUPPORTED;
 #elif 0
                 /*
                  * Use this option if you are using the second slot
                  * but not the first.
                  */
-                if ((bus_number == 1) && (devfn >> 3 != 3))
+                if ((bus_number == 2) && (devfn >> 3 != 3))
                         return PCIBIOS_FUNC_NOT_SUPPORTED;
 #elif 0
                 /* Use this opion if you are using both slots */
-                if ((bus_number == 1) &&
+                if ((bus_number == 2) &&
                     !((devfn == (2 << 3)) || (devfn == (3 << 3))))
                         return PCIBIOS_FUNC_NOT_SUPPORTED;
 #endif
 
+                /* The following #if gives a more complicated example. This is
+                   the required checks for running a Nitrox CN16XX-NHBX in the
+                   slot of the EBH5600. This card has a PLX PCIe bridge with
+                   four Nitrox PLX parts behind it */
+#if 0
+                /* PLX bridge with 4 ports */
+                if ((bus_number == 4) &&
+                    !((devfn >> 3 >= 1) && (devfn >> 3 <= 4)))
+                        return PCIBIOS_FUNC_NOT_SUPPORTED;
+                /* Nitrox behind PLX 1 */
+                if ((bus_number == 5) && (devfn >> 3 != 0))
+                        return PCIBIOS_FUNC_NOT_SUPPORTED;
+                /* Nitrox behind PLX 2 */
+                if ((bus_number == 6) && (devfn >> 3 != 0))
+                        return PCIBIOS_FUNC_NOT_SUPPORTED;
+                /* Nitrox behind PLX 3 */
+                if ((bus_number == 7) && (devfn >> 3 != 0))
+                        return PCIBIOS_FUNC_NOT_SUPPORTED;
+                /* Nitrox behind PLX 4 */
+                if ((bus_number == 8) && (devfn >> 3 != 0))
+                        return PCIBIOS_FUNC_NOT_SUPPORTED;
+#endif
+
                 /*
                  * Shorten the DID timeout so bus errors for PCIe
                  * config reads from non existent devices happen
@@ -1152,26 +1664,48 @@ static inline int octeon_pcie_read_config(int pcie_port, struct pci_bus *bus,
                 __write_64bit_c0_register($11, 7, cvmmemctl.u64);
         }
 
-        switch (size) {
-        case 4:
-                *val = cvmx_pcie_config_read32(pcie_port, bus_number,
-                                               devfn >> 3, devfn & 0x7, reg);
+        if ((OCTEON_IS_MODEL(OCTEON_CN63XX)) && (enable_pcie_14459_war))
+                cfg_retry_cnt = disable_cfg_read_retry();
+
+        pr_debug("pcie_cfg_rd port=%d b=%d devfn=0x%03x reg=0x%03x"
+                 " size=%d ", pcie_port, bus_number, devfn, reg, size);
+        do {
+                switch (size) {
+                case 4:
+                        *val = cvmx_pcie_config_read32(pcie_port, bus_number,
+                                devfn >> 3, devfn & 0x7, reg);
                 break;
-        case 2:
-                *val = cvmx_pcie_config_read16(pcie_port, bus_number,
-                                               devfn >> 3, devfn & 0x7, reg);
+                case 2:
+                        *val = cvmx_pcie_config_read16(pcie_port, bus_number,
+                                devfn >> 3, devfn & 0x7, reg);
                 break;
-        case 1:
-                *val = cvmx_pcie_config_read8(pcie_port, bus_number, devfn >> 3,
-                                              devfn & 0x7, reg);
+                case 1:
+                        *val = cvmx_pcie_config_read8(pcie_port, bus_number,
+                                devfn >> 3, devfn & 0x7, reg);
                 break;
-        default:
-                return PCIBIOS_FUNC_NOT_SUPPORTED;
-        }
+                default:
+                        if (OCTEON_IS_MODEL(OCTEON_CN63XX))
+                                set_cfg_read_retry(cfg_retry_cnt);
+                        return PCIBIOS_FUNC_NOT_SUPPORTED;
+                }
+                if ((OCTEON_IS_MODEL(OCTEON_CN63XX)) &&
+                        (enable_pcie_14459_war)) {
+                        cfg_retry = is_cfg_retry();
+                        retry_cnt++;
+                        if (retry_cnt > max_retry_cnt) {
+                                pr_err(" pcie cfg_read retries failed. retry_cnt=%d\n",
+                                       retry_cnt);
+                                cfg_retry = 0;
+                        }
+                }
+        } while (cfg_retry);
 
+        if ((OCTEON_IS_MODEL(OCTEON_CN63XX)) && (enable_pcie_14459_war))
+                set_cfg_read_retry(cfg_retry_cnt);
+        pr_debug("val=%08x  : tries=%02d\n", *val, retry_cnt);
         if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1) ||
             OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_1))
-                __write_64bit_c0_register($11, 7, cvmmemctl_save.u64);
+                write_c0_cvmmemctl(cvmmemctl_save.u64);
         return PCIBIOS_SUCCESSFUL;
 }
 
@@ -1187,42 +1721,56 @@ static int octeon_pcie1_read_config(struct pci_bus *bus, unsigned int devfn,
         return octeon_pcie_read_config(1, bus, devfn, reg, size, val);
 }
 
+static int octeon_dummy_read_config(struct pci_bus *bus, unsigned int devfn,
+                                    int reg, int size, u32 *val)
+{
+        return PCIBIOS_FUNC_NOT_SUPPORTED;
+}
 
-
-/**
+/*
  * Write a value to PCI configuration space
- *
- * @bus:
- * @devfn:
- * @reg:
- * @size:
- * @val:
- * Returns
  */
-static inline int octeon_pcie_write_config(int pcie_port, struct pci_bus *bus,
-                                           unsigned int devfn, int reg,
-                                           int size, u32 val)
+static int octeon_pcie_write_config(unsigned int pcie_port, struct pci_bus *bus,
+                                    unsigned int devfn, int reg,
+                                    int size, u32 val)
 {
         int bus_number = bus->number;
 
+        BUG_ON(pcie_port >= ARRAY_SIZE(enable_pcie_bus_num_war));
+
+        if ((bus->parent == NULL) && (enable_pcie_bus_num_war[pcie_port]))
+                bus_number = 0;
+
+        pr_debug("pcie_cfg_wr port=%d b=%d devfn=0x%03x"
+                 " reg=0x%03x size=%d val=%08x\n", pcie_port, bus_number, devfn,
+                 reg, size, val);
+
+
         switch (size) {
         case 4:
                 cvmx_pcie_config_write32(pcie_port, bus_number, devfn >> 3,
                                          devfn & 0x7, reg, val);
-                return PCIBIOS_SUCCESSFUL;
+                break;
         case 2:
                 cvmx_pcie_config_write16(pcie_port, bus_number, devfn >> 3,
                                          devfn & 0x7, reg, val);
-                return PCIBIOS_SUCCESSFUL;
+                break;
         case 1:
                 cvmx_pcie_config_write8(pcie_port, bus_number, devfn >> 3,
                                         devfn & 0x7, reg, val);
-                return PCIBIOS_SUCCESSFUL;
+                break;
+        default:
+                return PCIBIOS_FUNC_NOT_SUPPORTED;
         }
 #if PCI_CONFIG_SPACE_DELAY
+        /*
+         * Delay on writes so that devices have time to come up. Some
+         * bridges need this to allow time for the secondary busses to
+         * work
+         */
         udelay(PCI_CONFIG_SPACE_DELAY);
 #endif
-        return PCIBIOS_FUNC_NOT_SUPPORTED;
+        return PCIBIOS_SUCCESSFUL;
 }
 
 static int octeon_pcie0_write_config(struct pci_bus *bus, unsigned int devfn,
@@ -1237,6 +1785,12 @@ static int octeon_pcie1_write_config(struct pci_bus *bus, unsigned int devfn,
         return octeon_pcie_write_config(1, bus, devfn, reg, size, val);
 }
 
+static int octeon_dummy_write_config(struct pci_bus *bus, unsigned int devfn,
+                                     int reg, int size, u32 val)
+{
+        return PCIBIOS_FUNC_NOT_SUPPORTED;
+}
+
 static struct pci_ops octeon_pcie0_ops = {
         octeon_pcie0_read_config,
         octeon_pcie0_write_config,
@@ -1279,6 +1833,35 @@ static struct pci_controller octeon_pcie1_controller = {
         .io_resource = &octeon_pcie1_io_resource,
 };
 
+static struct pci_ops octeon_dummy_ops = {
+        octeon_dummy_read_config,
+        octeon_dummy_write_config,
+};
+
+static struct resource octeon_dummy_mem_resource = {
+        .name = "Virtual PCIe MEM",
+        .flags = IORESOURCE_MEM,
+};
+
+static struct resource octeon_dummy_io_resource = {
+        .name = "Virtual PCIe IO",
+        .flags = IORESOURCE_IO,
+};
+
+static struct pci_controller octeon_dummy_controller = {
+        .pci_ops = &octeon_dummy_ops,
+        .mem_resource = &octeon_dummy_mem_resource,
+        .io_resource = &octeon_dummy_io_resource,
+};
+
+static int device_needs_bus_num_war(uint32_t deviceid)
+{
+#define IDT_VENDOR_ID 0x111d
+
+        if ((deviceid  & 0xffff) == IDT_VENDOR_ID)
+                return 1;
+        return 0;
+}
 
 /**
  * Initialize the Octeon PCIe controllers
@@ -1287,19 +1870,27 @@ static struct pci_controller octeon_pcie1_controller = {
  */
 static int __init octeon_pcie_setup(void)
 {
-        union cvmx_npei_ctl_status npei_ctl_status;
         int result;
+        int host_mode;
+        int srio_war15205 = 0, port;
+        union cvmx_sli_ctl_portx sli_ctl_portx;
+        union cvmx_sriox_status_reg sriox_status_reg;
 
         /* These chips don't have PCIe */
         if (!octeon_has_feature(OCTEON_FEATURE_PCIE))
                 return 0;
 
+        /* No PCIe simulation */
+        if (octeon_is_simulation())
+                return 0;
+
+        /* Disable PCI if instructed on the command line */
+        if (pcie_disable)
+                return 0;
+
         /* Point pcibios_map_irq() to the PCIe version of it */
         octeon_pcibios_map_irq = octeon_pcie_pcibios_map_irq;
 
-        /* Use the PCIe based DMA mappings */
-        octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_PCIE;
-
         /*
          * PCIe I/O range. It is based on port 0 but includes up until
          * port 1's end.
@@ -1310,11 +1901,43 @@ static int __init octeon_pcie_setup(void)
                 cvmx_pcie_get_io_base_address(1) -
                 cvmx_pcie_get_io_base_address(0) + cvmx_pcie_get_io_size(1) - 1;
 
-        npei_ctl_status.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS);
-        if (npei_ctl_status.s.host_mode) {
+        /*
+         * Create a dummy PCIe controller to swallow up bus 0. IDT bridges
+         * don't work if the primary bus number is zero. Here we add a fake
+         * PCIe controller that the kernel will give bus 0. This allows
+         * us to not change the normal kernel bus enumeration
+         */
+        octeon_dummy_controller.io_map_base = -1;
+        octeon_dummy_controller.mem_resource->start = (1ull<<48);
+        octeon_dummy_controller.mem_resource->end = (1ull<<48);
+        register_pci_controller(&octeon_dummy_controller);
+
+        if (octeon_has_feature(OCTEON_FEATURE_NPEI)) {
+                union cvmx_npei_ctl_status npei_ctl_status;
+                npei_ctl_status.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS);
+                host_mode = npei_ctl_status.s.host_mode;
+                octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_PCIE;
+        } else {
+                union cvmx_mio_rst_ctlx mio_rst_ctl;
+                mio_rst_ctl.u64 = cvmx_read_csr(CVMX_MIO_RST_CTLX(0));
+                host_mode = mio_rst_ctl.s.host_mode;
+                octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_PCIE2;
+        }
+
+        if (host_mode) {
                 pr_notice("PCIe: Initializing port 0\n");
+                /* CN63XX pass 1_x/2.0 errata PCIe-15205 */
+                if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) ||
+                        OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0)) {
+                        sriox_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(0));
+                        if (sriox_status_reg.s.srio) {
+                                srio_war15205 += 1;      /* Port is SRIO */
+                                port = 0;
+                        }
+                }
                 result = cvmx_pcie_rc_initialize(0);
                 if (result == 0) {
+                        uint32_t device0;
                         /* Memory offsets are physical addresses */
                         octeon_pcie0_controller.mem_offset =
                                 cvmx_pcie_get_mem_base_address(0);
@@ -1343,60 +1966,134 @@ static int __init octeon_pcie_setup(void)
                         octeon_pcie0_controller.io_resource->start = 4 << 10;
                         octeon_pcie0_controller.io_resource->end =
                                 cvmx_pcie_get_io_size(0) - 1;
+                        msleep(100); /* Some devices need extra time */
                         register_pci_controller(&octeon_pcie0_controller);
+                        device0 = cvmx_pcie_config_read32(0, 0, 0, 0, 0);
+                        enable_pcie_bus_num_war[0] =
+                                device_needs_bus_num_war(device0);
                 }
         } else {
                 pr_notice("PCIe: Port 0 in endpoint mode, skipping.\n");
+                /* CN63XX pass 1_x/2.0 errata PCIe-15205 */
+                if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) ||
+                        OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0)) {
+                        srio_war15205 += 1;
+                        port = 0;
+                }
         }
 
-        /* Skip the 2nd port on CN52XX if port 0 is in 4 lane mode */
-        if (OCTEON_IS_MODEL(OCTEON_CN52XX)) {
-                union cvmx_npei_dbg_data npei_dbg_data;
-                npei_dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
-                if (npei_dbg_data.cn52xx.qlm0_link_width)
-                        return 0;
+        if (octeon_has_feature(OCTEON_FEATURE_NPEI)) {
+                host_mode = 1;
+                /* Skip the 2nd port on CN52XX if port 0 is in 4 lane mode */
+                if (OCTEON_IS_MODEL(OCTEON_CN52XX)) {
+                        union cvmx_npei_dbg_data dbg_data;
+                        dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
+                        if (dbg_data.cn52xx.qlm0_link_width)
+                                host_mode = 0;
+                }
+        } else {
+                union cvmx_mio_rst_ctlx mio_rst_ctl;
+                mio_rst_ctl.u64 = cvmx_read_csr(CVMX_MIO_RST_CTLX(1));
+                host_mode = mio_rst_ctl.s.host_mode;
         }
 
-        pr_notice("PCIe: Initializing port 1\n");
-        result = cvmx_pcie_rc_initialize(1);
-        if (result == 0) {
-                /* Memory offsets are physical addresses */
-                octeon_pcie1_controller.mem_offset =
-                        cvmx_pcie_get_mem_base_address(1);
-                /* IO offsets are Mips virtual addresses */
-                octeon_pcie1_controller.io_map_base =
-                        CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address(1));
-                octeon_pcie1_controller.io_offset =
-                        cvmx_pcie_get_io_base_address(1) -
-                        cvmx_pcie_get_io_base_address(0);
-                /*
-                 * To keep things similar to PCI, we start device
-                 * addresses at the same place as PCI uisng big bar
-                 * support. This normally translates to 4GB-256MB,
-                 * which is the same as most x86 PCs.
-                 */
-                octeon_pcie1_controller.mem_resource->start =
-                        cvmx_pcie_get_mem_base_address(1) + (4ul << 30) -
-                        (OCTEON_PCI_BAR1_HOLE_SIZE << 20);
-                octeon_pcie1_controller.mem_resource->end =
-                        cvmx_pcie_get_mem_base_address(1) +
-                        cvmx_pcie_get_mem_size(1) - 1;
-                /*
-                 * Ports must be above 16KB for the ISA bus filtering
-                 * in the PCI-X to PCI bridge.
-                 */
-                octeon_pcie1_controller.io_resource->start =
-                        cvmx_pcie_get_io_base_address(1) -
-                        cvmx_pcie_get_io_base_address(0);
-                octeon_pcie1_controller.io_resource->end =
-                        octeon_pcie1_controller.io_resource->start +
-                        cvmx_pcie_get_io_size(1) - 1;
-                register_pci_controller(&octeon_pcie1_controller);
+        if (host_mode) {
+                pr_notice("PCIe: Initializing port 1\n");
+                /* CN63XX pass 1_x/2.0 errata PCIe-15205 */
+                if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) ||
+                        OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0)) {
+                        sriox_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(1));
+                        if (sriox_status_reg.s.srio) {
+                                srio_war15205 += 1;      /* Port is SRIO */
+                                port = 1;
+                        }
+                }
+                result = cvmx_pcie_rc_initialize(1);
+                if (result == 0) {
+                        uint32_t device0;
+                        /* Memory offsets are physical addresses */
+                        octeon_pcie1_controller.mem_offset =
+                                cvmx_pcie_get_mem_base_address(1);
+                        /*
+                         * To calculate the address for accessing the 2nd PCIe device,
+                         * either 'io_map_base' (pci_iomap()), or 'mips_io_port_base'
+                         * (ioport_map()) value is added to
+                         * pci_resource_start(dev,bar)). The 'mips_io_port_base' is set
+                         * only once based on first PCIe. Also changing 'io_map_base'
+                         * based on first slot's value so that both the routines will
+                         * work properly.
+                         */
+                        octeon_pcie1_controller.io_map_base =
+                                CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address(0));
+                        /* IO offsets are Mips virtual addresses */
+                        octeon_pcie1_controller.io_offset =
+                                cvmx_pcie_get_io_base_address(1) -
+                                cvmx_pcie_get_io_base_address(0);
+                        /*
+                         * To keep things similar to PCI, we start device
+                         * addresses at the same place as PCI uisng big bar
+                         * support. This normally translates to 4GB-256MB,
+                         * which is the same as most x86 PCs.
+                         */
+                        octeon_pcie1_controller.mem_resource->start =
+                                cvmx_pcie_get_mem_base_address(1) + (4ul << 30) -
+                                (OCTEON_PCI_BAR1_HOLE_SIZE << 20);
+                        octeon_pcie1_controller.mem_resource->end =
+                                cvmx_pcie_get_mem_base_address(1) +
+                                cvmx_pcie_get_mem_size(1) - 1;
+                        /*
+                         * Ports must be above 16KB for the ISA bus filtering
+                         * in the PCI-X to PCI bridge.
+                         */
+                        octeon_pcie1_controller.io_resource->start =
+                                cvmx_pcie_get_io_base_address(1) -
+                                cvmx_pcie_get_io_base_address(0);
+                        octeon_pcie1_controller.io_resource->end =
+                                octeon_pcie1_controller.io_resource->start +
+                                cvmx_pcie_get_io_size(1) - 1;
+                        msleep(100); /* Some devices need extra time */
+                        register_pci_controller(&octeon_pcie1_controller);
+                        device0 = cvmx_pcie_config_read32(1, 0, 0, 0, 0);
+                        enable_pcie_bus_num_war[1] =
+                                device_needs_bus_num_war(device0);
+                }
+        } else {
+                pr_notice("PCIe: Port 1 not in root complex mode, skipping.\n");
+                /* CN63XX pass 1_x/2.0 errata PCIe-15205  */
+                if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) ||
+                        OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0)) {
+                        srio_war15205 += 1;
+                        port = 1;
+                }
+        }
+
+        /*
+         * CN63XX pass 1_x/2.0 errata PCIe-15205 requires setting all
+         * of SRIO MACs SLI_CTL_PORT*[INT*_MAP] to similar value and
+         * all of PCIe Macs SLI_CTL_PORT*[INT*_MAP] to different value
+         * from the previous set values
+         */
+        if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) ||
+                OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0)) {
+                if (srio_war15205 == 1) {
+                        sli_ctl_portx.u64 = cvmx_read_csr(CVMX_PEXP_SLI_CTL_PORTX(port));
+                        sli_ctl_portx.s.inta_map = 1;
+                        sli_ctl_portx.s.intb_map = 1;
+                        sli_ctl_portx.s.intc_map = 1;
+                        sli_ctl_portx.s.intd_map = 1;
+                        cvmx_write_csr(CVMX_PEXP_SLI_CTL_PORTX(port), sli_ctl_portx.u64);
+
+                        sli_ctl_portx.u64 = cvmx_read_csr(CVMX_PEXP_SLI_CTL_PORTX(!port));
+                        sli_ctl_portx.s.inta_map = 0;
+                        sli_ctl_portx.s.intb_map = 0;
+                        sli_ctl_portx.s.intc_map = 0;
+                        sli_ctl_portx.s.intd_map = 0;
+                        cvmx_write_csr(CVMX_PEXP_SLI_CTL_PORTX(!port), sli_ctl_portx.u64);
+                }
         }
 
         octeon_pci_dma_init();
 
         return 0;
 }
-
 arch_initcall(octeon_pcie_setup);
diff --git a/drivers/staging/octeon/Makefile b/drivers/staging/octeon/Makefile
index fc850bac88c..9012dee0c34 100644
--- a/drivers/staging/octeon/Makefile
+++ b/drivers/staging/octeon/Makefile
@@ -20,9 +20,4 @@ octeon-ethernet-y += ethernet-sgmii.o
 octeon-ethernet-y += ethernet-spi.o
 octeon-ethernet-y += ethernet-tx.o
 octeon-ethernet-y += ethernet-xaui.o
-octeon-ethernet-y += cvmx-pko.o cvmx-spi.o cvmx-cmd-queue.o \
-        cvmx-helper-board.o cvmx-helper.o cvmx-helper-xaui.o \
-        cvmx-helper-rgmii.o cvmx-helper-sgmii.o cvmx-helper-npi.o \
-        cvmx-helper-loop.o cvmx-helper-spi.o cvmx-helper-util.o \
-        cvmx-interrupt-decodes.o cvmx-interrupt-rsl.o
 
diff --git a/drivers/staging/octeon/cvmx-packet.h b/drivers/staging/octeon/cvmx-packet.h
deleted file mode 100644
index 62ffe78a8c8..00000000000
--- a/drivers/staging/octeon/cvmx-packet.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/***********************license start***************
- * Author: Cavium Networks
- *
- * Contact: support@caviumnetworks.com
- * This file is part of the OCTEON SDK
- *
- * Copyright (c) 2003-2008 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful, but
- * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
- * NONINFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this file; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- * or visit http://www.gnu.org/licenses/.
- *
- * This file may also be available under a different license from Cavium.
- * Contact Cavium Networks for more information
- ***********************license end**************************************/
-
-/**
- *
- * Packet buffer defines.
- */
-
-#ifndef __CVMX_PACKET_H__
-#define __CVMX_PACKET_H__
-
-/**
- * This structure defines a buffer pointer on Octeon
- */
-union cvmx_buf_ptr {
-        void *ptr;
-        uint64_t u64;
-        struct {
-                /*
-                 * if set, invert the "free" pick of the overall
-                 * packet. HW always sets this bit to 0 on inbound
-                 * packet
-                 */
-                uint64_t i:1;
-                /*
-                 * Indicates the amount to back up to get to the
-                 * buffer start in cache lines. In most cases this is
-                 * less than one complete cache line, so the value is
-                 * zero.
-                 */
-                uint64_t back:4;
-                /* The pool that the buffer came from / goes to */
-                uint64_t pool:3;
-                /* The size of the segment pointed to by addr (in bytes) */
-                uint64_t size:16;
-                /* Pointer to the first byte of the data, NOT buffer */
-                uint64_t addr:40;
-        } s;
-};
-
-#endif /*  __CVMX_PACKET_H__ */
diff --git a/drivers/staging/octeon/cvmx-smix-defs.h b/drivers/staging/octeon/cvmx-smix-defs.h
deleted file mode 100644
index 9ae45fcbe3e..00000000000
--- a/drivers/staging/octeon/cvmx-smix-defs.h
+++ /dev/null
@@ -1,178 +0,0 @@
-/***********************license start***************
- * Author: Cavium Networks
- *
- * Contact: support@caviumnetworks.com
- * This file is part of the OCTEON SDK
- *
- * Copyright (c) 2003-2008 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful, but
- * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
- * NONINFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this file; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- * or visit http://www.gnu.org/licenses/.
- *
- * This file may also be available under a different license from Cavium.
- * Contact Cavium Networks for more information
- ***********************license end**************************************/
-
-#ifndef __CVMX_SMIX_DEFS_H__
-#define __CVMX_SMIX_DEFS_H__
-
-#define CVMX_SMIX_CLK(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000001818ull + (((offset) & 1) * 256))
-#define CVMX_SMIX_CMD(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000001800ull + (((offset) & 1) * 256))
-#define CVMX_SMIX_EN(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000001820ull + (((offset) & 1) * 256))
-#define CVMX_SMIX_RD_DAT(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000001810ull + (((offset) & 1) * 256))
-#define CVMX_SMIX_WR_DAT(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000001808ull + (((offset) & 1) * 256))
-
-union cvmx_smix_clk {
-        uint64_t u64;
-        struct cvmx_smix_clk_s {
-                uint64_t reserved_25_63:39;
-                uint64_t mode:1;
-                uint64_t reserved_21_23:3;
-                uint64_t sample_hi:5;
-                uint64_t sample_mode:1;
-                uint64_t reserved_14_14:1;
-                uint64_t clk_idle:1;
-                uint64_t preamble:1;
-                uint64_t sample:4;
-                uint64_t phase:8;
-        } s;
-        struct cvmx_smix_clk_cn30xx {
-                uint64_t reserved_21_63:43;
-                uint64_t sample_hi:5;
-                uint64_t reserved_14_15:2;
-                uint64_t clk_idle:1;
-                uint64_t preamble:1;
-                uint64_t sample:4;
-                uint64_t phase:8;
-        } cn30xx;
-        struct cvmx_smix_clk_cn30xx cn31xx;
-        struct cvmx_smix_clk_cn30xx cn38xx;
-        struct cvmx_smix_clk_cn30xx cn38xxp2;
-        struct cvmx_smix_clk_cn50xx {
-                uint64_t reserved_25_63:39;
-                uint64_t mode:1;
-                uint64_t reserved_21_23:3;
-                uint64_t sample_hi:5;
-                uint64_t reserved_14_15:2;
-                uint64_t clk_idle:1;
-                uint64_t preamble:1;
-                uint64_t sample:4;
-                uint64_t phase:8;
-        } cn50xx;
-        struct cvmx_smix_clk_s cn52xx;
-        struct cvmx_smix_clk_cn50xx cn52xxp1;
-        struct cvmx_smix_clk_s cn56xx;
-        struct cvmx_smix_clk_cn50xx cn56xxp1;
-        struct cvmx_smix_clk_cn30xx cn58xx;
-        struct cvmx_smix_clk_cn30xx cn58xxp1;
-};
-
-union cvmx_smix_cmd {
-        uint64_t u64;
-        struct cvmx_smix_cmd_s {
-                uint64_t reserved_18_63:46;
-                uint64_t phy_op:2;
-                uint64_t reserved_13_15:3;
-                uint64_t phy_adr:5;
-                uint64_t reserved_5_7:3;
-                uint64_t reg_adr:5;
-        } s;
-        struct cvmx_smix_cmd_cn30xx {
-                uint64_t reserved_17_63:47;
-                uint64_t phy_op:1;
-                uint64_t reserved_13_15:3;
-                uint64_t phy_adr:5;
-                uint64_t reserved_5_7:3;
-                uint64_t reg_adr:5;
-        } cn30xx;
-        struct cvmx_smix_cmd_cn30xx cn31xx;
-        struct cvmx_smix_cmd_cn30xx cn38xx;
-        struct cvmx_smix_cmd_cn30xx cn38xxp2;
-        struct cvmx_smix_cmd_s cn50xx;
-        struct cvmx_smix_cmd_s cn52xx;
-        struct cvmx_smix_cmd_s cn52xxp1;
-        struct cvmx_smix_cmd_s cn56xx;
-        struct cvmx_smix_cmd_s cn56xxp1;
-        struct cvmx_smix_cmd_cn30xx cn58xx;
-        struct cvmx_smix_cmd_cn30xx cn58xxp1;
-};
-
-union cvmx_smix_en {
-        uint64_t u64;
-        struct cvmx_smix_en_s {
-                uint64_t reserved_1_63:63;
-                uint64_t en:1;
-        } s;
-        struct cvmx_smix_en_s cn30xx;
-        struct cvmx_smix_en_s cn31xx;
-        struct cvmx_smix_en_s cn38xx;
-        struct cvmx_smix_en_s cn38xxp2;
-        struct cvmx_smix_en_s cn50xx;
-        struct cvmx_smix_en_s cn52xx;
-        struct cvmx_smix_en_s cn52xxp1;
-        struct cvmx_smix_en_s cn56xx;
-        struct cvmx_smix_en_s cn56xxp1;
-        struct cvmx_smix_en_s cn58xx;
-        struct cvmx_smix_en_s cn58xxp1;
-};
-
-union cvmx_smix_rd_dat {
-        uint64_t u64;
-        struct cvmx_smix_rd_dat_s {
-                uint64_t reserved_18_63:46;
-                uint64_t pending:1;
-                uint64_t val:1;
-                uint64_t dat:16;
-        } s;
-        struct cvmx_smix_rd_dat_s cn30xx;
-        struct cvmx_smix_rd_dat_s cn31xx;
-        struct cvmx_smix_rd_dat_s cn38xx;
-        struct cvmx_smix_rd_dat_s cn38xxp2;
-        struct cvmx_smix_rd_dat_s cn50xx;
-        struct cvmx_smix_rd_dat_s cn52xx;
-        struct cvmx_smix_rd_dat_s cn52xxp1;
-        struct cvmx_smix_rd_dat_s cn56xx;
-        struct cvmx_smix_rd_dat_s cn56xxp1;
-        struct cvmx_smix_rd_dat_s cn58xx;
-        struct cvmx_smix_rd_dat_s cn58xxp1;
-};
-
-union cvmx_smix_wr_dat {
-        uint64_t u64;
-        struct cvmx_smix_wr_dat_s {
-                uint64_t reserved_18_63:46;
-                uint64_t pending:1;
-                uint64_t val:1;
-                uint64_t dat:16;
-        } s;
-        struct cvmx_smix_wr_dat_s cn30xx;
-        struct cvmx_smix_wr_dat_s cn31xx;
-        struct cvmx_smix_wr_dat_s cn38xx;
-        struct cvmx_smix_wr_dat_s cn38xxp2;
-        struct cvmx_smix_wr_dat_s cn50xx;
-        struct cvmx_smix_wr_dat_s cn52xx;
-        struct cvmx_smix_wr_dat_s cn52xxp1;
-        struct cvmx_smix_wr_dat_s cn56xx;
-        struct cvmx_smix_wr_dat_s cn56xxp1;
-        struct cvmx_smix_wr_dat_s cn58xx;
-        struct cvmx_smix_wr_dat_s cn58xxp1;
-};
-
-#endif
diff --git a/drivers/staging/octeon/ethernet-defines.h b/drivers/staging/octeon/ethernet-defines.h
index 6a2cd50a17d..bdaec8d2ca0 100644
--- a/drivers/staging/octeon/ethernet-defines.h
+++ b/drivers/staging/octeon/ethernet-defines.h
@@ -59,7 +59,7 @@
 #ifndef __ETHERNET_DEFINES_H__
 #define __ETHERNET_DEFINES_H__
 
-#include "cvmx-config.h"
+#include <asm/octeon/cvmx-config.h>
 
 
 #define OCTEON_ETHERNET_VERSION "1.9"
diff --git a/drivers/staging/octeon/ethernet-mdio.c b/drivers/staging/octeon/ethernet-mdio.c
index f18e3e14041..63800ba71d0 100644
--- a/drivers/staging/octeon/ethernet-mdio.c
+++ b/drivers/staging/octeon/ethernet-mdio.c
@@ -38,9 +38,9 @@
 #include "ethernet-mdio.h"
 #include "ethernet-util.h"
 
-#include "cvmx-helper-board.h"
+#include <asm/octeon/cvmx-helper-board.h>
 
-#include "cvmx-smix-defs.h"
+#include <asm/octeon/cvmx-smix-defs.h>
 
 static void cvm_oct_get_drvinfo(struct net_device *dev,
                                 struct ethtool_drvinfo *info)
diff --git a/drivers/staging/octeon/ethernet-mem.c b/drivers/staging/octeon/ethernet-mem.c
index 635bb86cdcf..78b6cb74376 100644
--- a/drivers/staging/octeon/ethernet-mem.c
+++ b/drivers/staging/octeon/ethernet-mem.c
@@ -32,7 +32,7 @@
 
 #include "ethernet-defines.h"
 
-#include "cvmx-fpa.h"
+#include <asm/octeon/cvmx-fpa.h>
 
 /**
  * cvm_oct_fill_hw_skbuff - fill the supplied hardware pool with skbuffs
diff --git a/drivers/staging/octeon/ethernet-rgmii.c b/drivers/staging/octeon/ethernet-rgmii.c
index c3d73f8431a..d8f5f694ec3 100644
--- a/drivers/staging/octeon/ethernet-rgmii.c
+++ b/drivers/staging/octeon/ethernet-rgmii.c
@@ -37,11 +37,11 @@
 #include "octeon-ethernet.h"
 #include "ethernet-util.h"
 
-#include "cvmx-helper.h"
+#include <asm/octeon/cvmx-helper.h>
 
 #include <asm/octeon/cvmx-ipd-defs.h>
 #include <asm/octeon/cvmx-npi-defs.h>
-#include "cvmx-gmxx-defs.h"
+#include <asm/octeon/cvmx-gmxx-defs.h>
 
 DEFINE_SPINLOCK(global_register_lock);
 
diff --git a/drivers/staging/octeon/ethernet-rx.c b/drivers/staging/octeon/ethernet-rx.c
index 8b307b42879..400df8cbee5 100644
--- a/drivers/staging/octeon/ethernet-rx.c
+++ b/drivers/staging/octeon/ethernet-rx.c
@@ -52,14 +52,14 @@
 #include "octeon-ethernet.h"
 #include "ethernet-util.h"
 
-#include "cvmx-helper.h"
-#include "cvmx-wqe.h"
-#include "cvmx-fau.h"
-#include "cvmx-pow.h"
-#include "cvmx-pip.h"
-#include "cvmx-scratch.h"
-
-#include "cvmx-gmxx-defs.h"
+#include <asm/octeon/cvmx-helper.h>
+#include <asm/octeon/cvmx-wqe.h>
+#include <asm/octeon/cvmx-fau.h>
+#include <asm/octeon/cvmx-pow.h>
+#include <asm/octeon/cvmx-pip.h>
+#include <asm/octeon/cvmx-scratch.h>
+
+#include <asm/octeon/cvmx-gmxx-defs.h>
 
 struct cvm_napi_wrapper {
         struct napi_struct napi;
diff --git a/drivers/staging/octeon/ethernet-rx.h b/drivers/staging/octeon/ethernet-rx.h
index a0743b85d54..9240c85ce24 100644
--- a/drivers/staging/octeon/ethernet-rx.h
+++ b/drivers/staging/octeon/ethernet-rx.h
@@ -24,7 +24,7 @@
  * This file may also be available under a different license from Cavium.
  * Contact Cavium Networks for more information
 *********************************************************************/
-#include "cvmx-fau.h"
+#include <asm/octeon/cvmx-fau.h>
 
 void cvm_oct_poll_controller(struct net_device *dev);
 void cvm_oct_rx_initialize(void);
diff --git a/drivers/staging/octeon/ethernet-sgmii.c b/drivers/staging/octeon/ethernet-sgmii.c
index 5e148b512c9..d3e82430eba 100644
--- a/drivers/staging/octeon/ethernet-sgmii.c
+++ b/drivers/staging/octeon/ethernet-sgmii.c
@@ -35,9 +35,9 @@
 #include "octeon-ethernet.h"
 #include "ethernet-util.h"
 
-#include "cvmx-helper.h"
+#include <asm/octeon/cvmx-helper.h>
 
-#include "cvmx-gmxx-defs.h"
+#include <asm/octeon/cvmx-gmxx-defs.h>
 
 int cvm_oct_sgmii_open(struct net_device *dev)
 {
diff --git a/drivers/staging/octeon/ethernet-spi.c b/drivers/staging/octeon/ethernet-spi.c
index d0e2d514968..af8d62818f1 100644
--- a/drivers/staging/octeon/ethernet-spi.c
+++ b/drivers/staging/octeon/ethernet-spi.c
@@ -35,11 +35,11 @@
 #include "octeon-ethernet.h"
 #include "ethernet-util.h"
 
-#include "cvmx-spi.h"
+#include <asm/octeon/cvmx-spi.h>
 
 #include <asm/octeon/cvmx-npi-defs.h>
-#include "cvmx-spxx-defs.h"
-#include "cvmx-stxx-defs.h"
+#include <asm/octeon/cvmx-spxx-defs.h>
+#include <asm/octeon/cvmx-stxx-defs.h>
 
 static int number_spi_ports;
 static int need_retrain[2] = { 0, 0 };
diff --git a/drivers/staging/octeon/ethernet-tx.c b/drivers/staging/octeon/ethernet-tx.c
index 2542c374390..56d74dc2fbd 100644
--- a/drivers/staging/octeon/ethernet-tx.c
+++ b/drivers/staging/octeon/ethernet-tx.c
@@ -47,13 +47,13 @@
 #include "ethernet-tx.h"
 #include "ethernet-util.h"
 
-#include "cvmx-wqe.h"
-#include "cvmx-fau.h"
-#include "cvmx-pip.h"
-#include "cvmx-pko.h"
-#include "cvmx-helper.h"
+#include <asm/octeon/cvmx-wqe.h>
+#include <asm/octeon/cvmx-fau.h>
+#include <asm/octeon/cvmx-pip.h>
+#include <asm/octeon/cvmx-pko.h>
+#include <asm/octeon/cvmx-helper.h>
 
-#include "cvmx-gmxx-defs.h"
+#include <asm/octeon/cvmx-gmxx-defs.h>
 
 #define CVM_OCT_SKB_CB(skb)     ((u64 *)((skb)->cb))
 
diff --git a/drivers/staging/octeon/ethernet-xaui.c b/drivers/staging/octeon/ethernet-xaui.c
index 861a4b3fe85..419f8c34ecd 100644
--- a/drivers/staging/octeon/ethernet-xaui.c
+++ b/drivers/staging/octeon/ethernet-xaui.c
@@ -35,9 +35,9 @@
 #include "octeon-ethernet.h"
 #include "ethernet-util.h"
 
-#include "cvmx-helper.h"
+#include <asm/octeon/cvmx-helper.h>
 
-#include "cvmx-gmxx-defs.h"
+#include <asm/octeon/cvmx-gmxx-defs.h>
 
 int cvm_oct_xaui_open(struct net_device *dev)
 {
diff --git a/drivers/staging/octeon/ethernet.c b/drivers/staging/octeon/ethernet.c
index 076f86675ce..9112cd88215 100644
--- a/drivers/staging/octeon/ethernet.c
+++ b/drivers/staging/octeon/ethernet.c
@@ -44,14 +44,14 @@
 #include "ethernet-mdio.h"
 #include "ethernet-util.h"
 
-#include "cvmx-pip.h"
-#include "cvmx-pko.h"
-#include "cvmx-fau.h"
-#include "cvmx-ipd.h"
-#include "cvmx-helper.h"
-
-#include "cvmx-gmxx-defs.h"
-#include "cvmx-smix-defs.h"
+#include <asm/octeon/cvmx-pip.h>
+#include <asm/octeon/cvmx-pko.h>
+#include <asm/octeon/cvmx-fau.h>
+#include <asm/octeon/cvmx-ipd.h>
+#include <asm/octeon/cvmx-helper.h>
+
+#include <asm/octeon/cvmx-gmxx-defs.h>
+#include <asm/octeon/cvmx-smix-defs.h>
 
 #if defined(CONFIG_CAVIUM_OCTEON_NUM_PACKET_BUFFERS) \
         && CONFIG_CAVIUM_OCTEON_NUM_PACKET_BUFFERS
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 925a1e547a8..95a0f5fe7d4 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -1610,4 +1610,27 @@ config SERIAL_XILINX_PS_UART_CONSOLE
         help
           Enable a Xilinx PS UART port to be the system console.
 
+config SERIAL_AR933X
+        bool "AR933X serial port support"
+        depends on SOC_AR933X
+        select SERIAL_CORE
+        help
+          If you have an Atheros AR933X SOC based board and want to use the
+          built-in UART of the SoC, say Y to this option.
+
+config SERIAL_AR933X_CONSOLE
+        bool "Console on AR933X serial port"
+        depends on SERIAL_AR933X=y
+        select SERIAL_CORE_CONSOLE
+        help
+          Enable a built-in UART port of the AR933X to be the system console.
+
+config SERIAL_AR933X_NR_UARTS
+        int "Maximum number of AR933X serial ports"
+        depends on SERIAL_AR933X
+        default "2"
+        help
+          Set this to the number of serial ports you want the driver
+          to support.
+
 endmenu
diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile
index e10cf5b54b6..76811cc5859 100644
--- a/drivers/tty/serial/Makefile
+++ b/drivers/tty/serial/Makefile
@@ -94,3 +94,4 @@ obj-$(CONFIG_SERIAL_MSM_SMD)	+= msm_smd_tty.o
 obj-$(CONFIG_SERIAL_MXS_AUART) += mxs-auart.o
 obj-$(CONFIG_SERIAL_LANTIQ)     += lantiq.o
 obj-$(CONFIG_SERIAL_XILINX_PS_UART) += xilinx_uartps.o
+obj-$(CONFIG_SERIAL_AR933X)   += ar933x_uart.o
diff --git a/drivers/tty/serial/ar933x_uart.c b/drivers/tty/serial/ar933x_uart.c
new file mode 100644
index 00000000000..e4f60e2b87f
--- /dev/null
+++ b/drivers/tty/serial/ar933x_uart.c
@@ -0,0 +1,688 @@
+/*
+ *  Atheros AR933X SoC built-in UART driver
+ *
+ *  Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
+ *
+ *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/ioport.h>
+#include <linux/init.h>
+#include <linux/console.h>
+#include <linux/sysrq.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/tty.h>
+#include <linux/tty_flip.h>
+#include <linux/serial_core.h>
+#include <linux/serial.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+
+#include <asm/mach-ath79/ar933x_uart.h>
+#include <asm/mach-ath79/ar933x_uart_platform.h>
+
+#define DRIVER_NAME "ar933x-uart"
+
+#define AR933X_DUMMY_STATUS_RD  0x01
+
+static struct uart_driver ar933x_uart_driver;
+
+struct ar933x_uart_port {
+        struct uart_port        port;
+        unsigned int            ier;    /* shadow Interrupt Enable Register */
+};
+
+static inline unsigned int ar933x_uart_read(struct ar933x_uart_port *up,
+                                            int offset)
+{
+        return readl(up->port.membase + offset);
+}
+
+static inline void ar933x_uart_write(struct ar933x_uart_port *up,
+                                     int offset, unsigned int value)
+{
+        writel(value, up->port.membase + offset);
+}
+
+static inline void ar933x_uart_rmw(struct ar933x_uart_port *up,
+                                  unsigned int offset,
+                                  unsigned int mask,
+                                  unsigned int val)
+{
+        unsigned int t;
+
+        t = ar933x_uart_read(up, offset);
+        t &= ~mask;
+        t |= val;
+        ar933x_uart_write(up, offset, t);
+}
+
+static inline void ar933x_uart_rmw_set(struct ar933x_uart_port *up,
+                                       unsigned int offset,
+                                       unsigned int val)
+{
+        ar933x_uart_rmw(up, offset, 0, val);
+}
+
+static inline void ar933x_uart_rmw_clear(struct ar933x_uart_port *up,
+                                         unsigned int offset,
+                                         unsigned int val)
+{
+        ar933x_uart_rmw(up, offset, val, 0);
+}
+
+static inline void ar933x_uart_start_tx_interrupt(struct ar933x_uart_port *up)
+{
+        up->ier |= AR933X_UART_INT_TX_EMPTY;
+        ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier);
+}
+
+static inline void ar933x_uart_stop_tx_interrupt(struct ar933x_uart_port *up)
+{
+        up->ier &= ~AR933X_UART_INT_TX_EMPTY;
+        ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier);
+}
+
+static inline void ar933x_uart_putc(struct ar933x_uart_port *up, int ch)
+{
+        unsigned int rdata;
+
+        rdata = ch & AR933X_UART_DATA_TX_RX_MASK;
+        rdata |= AR933X_UART_DATA_TX_CSR;
+        ar933x_uart_write(up, AR933X_UART_DATA_REG, rdata);
+}
+
+static unsigned int ar933x_uart_tx_empty(struct uart_port *port)
+{
+        struct ar933x_uart_port *up = (struct ar933x_uart_port *) port;
+        unsigned long flags;
+        unsigned int rdata;
+
+        spin_lock_irqsave(&up->port.lock, flags);
+        rdata = ar933x_uart_read(up, AR933X_UART_DATA_REG);
+        spin_unlock_irqrestore(&up->port.lock, flags);
+
+        return (rdata & AR933X_UART_DATA_TX_CSR) ? 0 : TIOCSER_TEMT;
+}
+
+static unsigned int ar933x_uart_get_mctrl(struct uart_port *port)
+{
+        return TIOCM_CAR;
+}
+
+static void ar933x_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
+{
+}
+
+static void ar933x_uart_start_tx(struct uart_port *port)
+{
+        struct ar933x_uart_port *up = (struct ar933x_uart_port *) port;
+
+        ar933x_uart_start_tx_interrupt(up);
+}
+
+static void ar933x_uart_stop_tx(struct uart_port *port)
+{
+        struct ar933x_uart_port *up = (struct ar933x_uart_port *) port;
+
+        ar933x_uart_stop_tx_interrupt(up);
+}
+
+static void ar933x_uart_stop_rx(struct uart_port *port)
+{
+        struct ar933x_uart_port *up = (struct ar933x_uart_port *) port;
+
+        up->ier &= ~AR933X_UART_INT_RX_VALID;
+        ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier);
+}
+
+static void ar933x_uart_break_ctl(struct uart_port *port, int break_state)
+{
+        struct ar933x_uart_port *up = (struct ar933x_uart_port *) port;
+        unsigned long flags;
+
+        spin_lock_irqsave(&up->port.lock, flags);
+        if (break_state == -1)
+                ar933x_uart_rmw_set(up, AR933X_UART_CS_REG,
+                                    AR933X_UART_CS_TX_BREAK);
+        else
+                ar933x_uart_rmw_clear(up, AR933X_UART_CS_REG,
+                                      AR933X_UART_CS_TX_BREAK);
+        spin_unlock_irqrestore(&up->port.lock, flags);
+}
+
+static void ar933x_uart_enable_ms(struct uart_port *port)
+{
+}
+
+static void ar933x_uart_set_termios(struct uart_port *port,
+                                    struct ktermios *new,
+                                    struct ktermios *old)
+{
+        struct ar933x_uart_port *up = (struct ar933x_uart_port *) port;
+        unsigned int cs;
+        unsigned long flags;
+        unsigned int baud, scale;
+
+        /* Only CS8 is supported */
+        new->c_cflag &= ~CSIZE;
+        new->c_cflag |= CS8;
+
+        /* Only one stop bit is supported */
+        new->c_cflag &= ~CSTOPB;
+
+        cs = 0;
+        if (new->c_cflag & PARENB) {
+                if (!(new->c_cflag & PARODD))
+                        cs |= AR933X_UART_CS_PARITY_EVEN;
+                else
+                        cs |= AR933X_UART_CS_PARITY_ODD;
+        } else {
+                cs |= AR933X_UART_CS_PARITY_NONE;
+        }
+
+        /* Mark/space parity is not supported */
+        new->c_cflag &= ~CMSPAR;
+
+        baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
+        scale = (port->uartclk / (16 * baud)) - 1;
+
+        /*
+         * Ok, we're now changing the port state. Do it with
+         * interrupts disabled.
+         */
+        spin_lock_irqsave(&up->port.lock, flags);
+
+        /* Update the per-port timeout. */
+        uart_update_timeout(port, new->c_cflag, baud);
+
+        up->port.ignore_status_mask = 0;
+
+        /* ignore all characters if CREAD is not set */
+        if ((new->c_cflag & CREAD) == 0)
+                up->port.ignore_status_mask |= AR933X_DUMMY_STATUS_RD;
+
+        ar933x_uart_write(up, AR933X_UART_CLOCK_REG,
+                          scale << AR933X_UART_CLOCK_SCALE_S | 8192);
+
+        /* setup configuration register */
+        ar933x_uart_rmw(up, AR933X_UART_CS_REG, AR933X_UART_CS_PARITY_M, cs);
+
+        /* enable host interrupt */
+        ar933x_uart_rmw_set(up, AR933X_UART_CS_REG,
+                            AR933X_UART_CS_HOST_INT_EN);
+
+        spin_unlock_irqrestore(&up->port.lock, flags);
+
+        if (tty_termios_baud_rate(new))
+                tty_termios_encode_baud_rate(new, baud, baud);
+}
+
+static void ar933x_uart_rx_chars(struct ar933x_uart_port *up)
+{
+        struct tty_struct *tty;
+        int max_count = 256;
+
+        tty = tty_port_tty_get(&up->port.state->port);
+        do {
+                unsigned int rdata;
+                unsigned char ch;
+
+                rdata = ar933x_uart_read(up, AR933X_UART_DATA_REG);
+                if ((rdata & AR933X_UART_DATA_RX_CSR) == 0)
+                        break;
+
+                /* remove the character from the FIFO */
+                ar933x_uart_write(up, AR933X_UART_DATA_REG,
+                                  AR933X_UART_DATA_RX_CSR);
+
+                if (!tty) {
+                        /* discard the data if no tty available */
+                        continue;
+                }
+
+                up->port.icount.rx++;
+                ch = rdata & AR933X_UART_DATA_TX_RX_MASK;
+
+                if (uart_handle_sysrq_char(&up->port, ch))
+                        continue;
+
+                if ((up->port.ignore_status_mask & AR933X_DUMMY_STATUS_RD) == 0)
+                        tty_insert_flip_char(tty, ch, TTY_NORMAL);
+        } while (max_count-- > 0);
+
+        if (tty) {
+                tty_flip_buffer_push(tty);
+                tty_kref_put(tty);
+        }
+}
+
+static void ar933x_uart_tx_chars(struct ar933x_uart_port *up)
+{
+        struct circ_buf *xmit = &up->port.state->xmit;
+        int count;
+
+        if (uart_tx_stopped(&up->port))
+                return;
+
+        count = up->port.fifosize;
+        do {
+                unsigned int rdata;
+
+                rdata = ar933x_uart_read(up, AR933X_UART_DATA_REG);
+                if ((rdata & AR933X_UART_DATA_TX_CSR) == 0)
+                        break;
+
+                if (up->port.x_char) {
+                        ar933x_uart_putc(up, up->port.x_char);
+                        up->port.icount.tx++;
+                        up->port.x_char = 0;
+                        continue;
+                }
+
+                if (uart_circ_empty(xmit))
+                        break;
+
+                ar933x_uart_putc(up, xmit->buf[xmit->tail]);
+
+                xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
+                up->port.icount.tx++;
+        } while (--count > 0);
+
+        if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+                uart_write_wakeup(&up->port);
+
+        if (!uart_circ_empty(xmit))
+                ar933x_uart_start_tx_interrupt(up);
+}
+
+static irqreturn_t ar933x_uart_interrupt(int irq, void *dev_id)
+{
+        struct ar933x_uart_port *up = dev_id;
+        unsigned int status;
+
+        status = ar933x_uart_read(up, AR933X_UART_CS_REG);
+        if ((status & AR933X_UART_CS_HOST_INT) == 0)
+                return IRQ_NONE;
+
+        spin_lock(&up->port.lock);
+
+        status = ar933x_uart_read(up, AR933X_UART_INT_REG);
+        status &= ar933x_uart_read(up, AR933X_UART_INT_EN_REG);
+
+        if (status & AR933X_UART_INT_RX_VALID) {
+                ar933x_uart_write(up, AR933X_UART_INT_REG,
+                                  AR933X_UART_INT_RX_VALID);
+                ar933x_uart_rx_chars(up);
+        }
+
+        if (status & AR933X_UART_INT_TX_EMPTY) {
+                ar933x_uart_write(up, AR933X_UART_INT_REG,
+                                  AR933X_UART_INT_TX_EMPTY);
+                ar933x_uart_stop_tx_interrupt(up);
+                ar933x_uart_tx_chars(up);
+        }
+
+        spin_unlock(&up->port.lock);
+
+        return IRQ_HANDLED;
+}
+
+static int ar933x_uart_startup(struct uart_port *port)
+{
+        struct ar933x_uart_port *up = (struct ar933x_uart_port *) port;
+        unsigned long flags;
+        int ret;
+
+        ret = request_irq(up->port.irq, ar933x_uart_interrupt,
+                          up->port.irqflags, dev_name(up->port.dev), up);
+        if (ret)
+                return ret;
+
+        spin_lock_irqsave(&up->port.lock, flags);
+
+        /* Enable HOST interrupts */
+        ar933x_uart_rmw_set(up, AR933X_UART_CS_REG,
+                            AR933X_UART_CS_HOST_INT_EN);
+
+        /* Enable RX interrupts */
+        up->ier = AR933X_UART_INT_RX_VALID;
+        ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier);
+
+        spin_unlock_irqrestore(&up->port.lock, flags);
+
+        return 0;
+}
+
+static void ar933x_uart_shutdown(struct uart_port *port)
+{
+        struct ar933x_uart_port *up = (struct ar933x_uart_port *) port;
+
+        /* Disable all interrupts */
+        up->ier = 0;
+        ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier);
+
+        /* Disable break condition */
+        ar933x_uart_rmw_clear(up, AR933X_UART_CS_REG,
+                              AR933X_UART_CS_TX_BREAK);
+
+        free_irq(up->port.irq, up);
+}
+
+static const char *ar933x_uart_type(struct uart_port *port)
+{
+        return (port->type == PORT_AR933X) ? "AR933X UART" : NULL;
+}
+
+static void ar933x_uart_release_port(struct uart_port *port)
+{
+        /* Nothing to release ... */
+}
+
+static int ar933x_uart_request_port(struct uart_port *port)
+{
+        /* UARTs always present */
+        return 0;
+}
+
+static void ar933x_uart_config_port(struct uart_port *port, int flags)
+{
+        if (flags & UART_CONFIG_TYPE)
+                port->type = PORT_AR933X;
+}
+
+static int ar933x_uart_verify_port(struct uart_port *port,
+                                   struct serial_struct *ser)
+{
+        if (ser->type != PORT_UNKNOWN &&
+            ser->type != PORT_AR933X)
+                return -EINVAL;
+
+        if (ser->irq < 0 || ser->irq >= NR_IRQS)
+                return -EINVAL;
+
+        if (ser->baud_base < 28800)
+                return -EINVAL;
+
+        return 0;
+}
+
+static struct uart_ops ar933x_uart_ops = {
+        .tx_empty       = ar933x_uart_tx_empty,
+        .set_mctrl      = ar933x_uart_set_mctrl,
+        .get_mctrl      = ar933x_uart_get_mctrl,
+        .stop_tx        = ar933x_uart_stop_tx,
+        .start_tx       = ar933x_uart_start_tx,
+        .stop_rx        = ar933x_uart_stop_rx,
+        .enable_ms      = ar933x_uart_enable_ms,
+        .break_ctl      = ar933x_uart_break_ctl,
+        .startup        = ar933x_uart_startup,
+        .shutdown       = ar933x_uart_shutdown,
+        .set_termios    = ar933x_uart_set_termios,
+        .type           = ar933x_uart_type,
+        .release_port   = ar933x_uart_release_port,
+        .request_port   = ar933x_uart_request_port,
+        .config_port    = ar933x_uart_config_port,
+        .verify_port    = ar933x_uart_verify_port,
+};
+
+#ifdef CONFIG_SERIAL_AR933X_CONSOLE
+
+static struct ar933x_uart_port *
+ar933x_console_ports[CONFIG_SERIAL_AR933X_NR_UARTS];
+
+static void ar933x_uart_wait_xmitr(struct ar933x_uart_port *up)
+{
+        unsigned int status;
+        unsigned int timeout = 60000;
+
+        /* Wait up to 60ms for the character(s) to be sent. */
+        do {
+                status = ar933x_uart_read(up, AR933X_UART_DATA_REG);
+                if (--timeout == 0)
+                        break;
+                udelay(1);
+        } while ((status & AR933X_UART_DATA_TX_CSR) == 0);
+}
+
+static void ar933x_uart_console_putchar(struct uart_port *port, int ch)
+{
+        struct ar933x_uart_port *up = (struct ar933x_uart_port *) port;
+
+        ar933x_uart_wait_xmitr(up);
+        ar933x_uart_putc(up, ch);
+}
+
+static void ar933x_uart_console_write(struct console *co, const char *s,
+                                      unsigned int count)
+{
+        struct ar933x_uart_port *up = ar933x_console_ports[co->index];
+        unsigned long flags;
+        unsigned int int_en;
+        int locked = 1;
+
+        local_irq_save(flags);
+
+        if (up->port.sysrq)
+                locked = 0;
+        else if (oops_in_progress)
+                locked = spin_trylock(&up->port.lock);
+        else
+                spin_lock(&up->port.lock);
+
+        /*
+         * First save the IER then disable the interrupts
+         */
+        int_en = ar933x_uart_read(up, AR933X_UART_INT_EN_REG);
+        ar933x_uart_write(up, AR933X_UART_INT_EN_REG, 0);
+
+        uart_console_write(&up->port, s, count, ar933x_uart_console_putchar);
+
+        /*
+         * Finally, wait for transmitter to become empty
+         * and restore the IER
+         */
+        ar933x_uart_wait_xmitr(up);
+        ar933x_uart_write(up, AR933X_UART_INT_EN_REG, int_en);
+
+        ar933x_uart_write(up, AR933X_UART_INT_REG, AR933X_UART_INT_ALLINTS);
+
+        if (locked)
+                spin_unlock(&up->port.lock);
+
+        local_irq_restore(flags);
+}
+
+static int ar933x_uart_console_setup(struct console *co, char *options)
+{
+        struct ar933x_uart_port *up;
+        int baud = 115200;
+        int bits = 8;
+        int parity = 'n';
+        int flow = 'n';
+
+        if (co->index < 0 || co->index >= CONFIG_SERIAL_AR933X_NR_UARTS)
+                return -EINVAL;
+
+        up = ar933x_console_ports[co->index];
+        if (!up)
+                return -ENODEV;
+
+        if (options)
+                uart_parse_options(options, &baud, &parity, &bits, &flow);
+
+        return uart_set_options(&up->port, co, baud, parity, bits, flow);
+}
+
+static struct console ar933x_uart_console = {
+        .name           = "ttyATH",
+        .write          = ar933x_uart_console_write,
+        .device         = uart_console_device,
+        .setup          = ar933x_uart_console_setup,
+        .flags          = CON_PRINTBUFFER,
+        .index          = -1,
+        .data           = &ar933x_uart_driver,
+};
+
+static void ar933x_uart_add_console_port(struct ar933x_uart_port *up)
+{
+        ar933x_console_ports[up->port.line] = up;
+}
+
+#define AR933X_SERIAL_CONSOLE   (&ar933x_uart_console)
+
+#else
+
+static inline void ar933x_uart_add_console_port(struct ar933x_uart_port *up) {}
+
+#define AR933X_SERIAL_CONSOLE   NULL
+
+#endif /* CONFIG_SERIAL_AR933X_CONSOLE */
+
+static struct uart_driver ar933x_uart_driver = {
+        .owner          = THIS_MODULE,
+        .driver_name    = DRIVER_NAME,
+        .dev_name       = "ttyATH",
+        .nr             = CONFIG_SERIAL_AR933X_NR_UARTS,
+        .cons           = AR933X_SERIAL_CONSOLE,
+};
+
+static int __devinit ar933x_uart_probe(struct platform_device *pdev)
+{
+        struct ar933x_uart_platform_data *pdata;
+        struct ar933x_uart_port *up;
+        struct uart_port *port;
+        struct resource *mem_res;
+        struct resource *irq_res;
+        int id;
+        int ret;
+
+        pdata = pdev->dev.platform_data;
+        if (!pdata)
+                return -EINVAL;
+
+        id = pdev->id;
+        if (id == -1)
+                id = 0;
+
+        if (id > CONFIG_SERIAL_AR933X_NR_UARTS)
+                return -EINVAL;
+
+        mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!mem_res) {
+                dev_err(&pdev->dev, "no MEM resource\n");
+                return -EINVAL;
+        }
+
+        irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+        if (!irq_res) {
+                dev_err(&pdev->dev, "no IRQ resource\n");
+                return -EINVAL;
+        }
+
+        up = kzalloc(sizeof(struct ar933x_uart_port), GFP_KERNEL);
+        if (!up)
+                return -ENOMEM;
+
+        port = &up->port;
+        port->mapbase = mem_res->start;
+
+        port->membase = ioremap(mem_res->start, AR933X_UART_REGS_SIZE);
+        if (!port->membase) {
+                ret = -ENOMEM;
+                goto err_free_up;
+        }
+
+        port->line = id;
+        port->irq = irq_res->start;
+        port->dev = &pdev->dev;
+        port->type = PORT_AR933X;
+        port->iotype = UPIO_MEM32;
+        port->uartclk = pdata->uartclk;
+
+        port->regshift = 2;
+        port->fifosize = AR933X_UART_FIFO_SIZE;
+        port->ops = &ar933x_uart_ops;
+
+        ar933x_uart_add_console_port(up);
+
+        ret = uart_add_one_port(&ar933x_uart_driver, &up->port);
+        if (ret)
+                goto err_unmap;
+
+        platform_set_drvdata(pdev, up);
+        return 0;
+
+err_unmap:
+        iounmap(up->port.membase);
+err_free_up:
+        kfree(up);
+        return ret;
+}
+
+static int __devexit ar933x_uart_remove(struct platform_device *pdev)
+{
+        struct ar933x_uart_port *up;
+
+        up = platform_get_drvdata(pdev);
+        platform_set_drvdata(pdev, NULL);
+
+        if (up) {
+                uart_remove_one_port(&ar933x_uart_driver, &up->port);
+                iounmap(up->port.membase);
+                kfree(up);
+        }
+
+        return 0;
+}
+
+static struct platform_driver ar933x_uart_platform_driver = {
+        .probe          = ar933x_uart_probe,
+        .remove         = __devexit_p(ar933x_uart_remove),
+        .driver         = {
+                .name           = DRIVER_NAME,
+                .owner          = THIS_MODULE,
+        },
+};
+
+static int __init ar933x_uart_init(void)
+{
+        int ret;
+
+        ar933x_uart_driver.nr = CONFIG_SERIAL_AR933X_NR_UARTS;
+        ret = uart_register_driver(&ar933x_uart_driver);
+        if (ret)
+                goto err_out;
+
+        ret = platform_driver_register(&ar933x_uart_platform_driver);
+        if (ret)
+                goto err_unregister_uart_driver;
+
+        return 0;
+
+err_unregister_uart_driver:
+        uart_unregister_driver(&ar933x_uart_driver);
+err_out:
+        return ret;
+}
+
+static void __exit ar933x_uart_exit(void)
+{
+        platform_driver_unregister(&ar933x_uart_platform_driver);
+        uart_unregister_driver(&ar933x_uart_driver);
+}
+
+module_init(ar933x_uart_init);
+module_exit(ar933x_uart_exit);
+
+MODULE_DESCRIPTION("Atheros AR933X UART driver");
+MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:" DRIVER_NAME);
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 060e0e2b1ae..8b094b4f653 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -210,7 +210,7 @@ config USB_CNS3XXX_EHCI
 
 config USB_EHCI_ATH79
         bool "EHCI support for AR7XXX/AR9XXX SoCs"
-        depends on USB_EHCI_HCD && (SOC_AR71XX || SOC_AR724X || SOC_AR913X)
+        depends on USB_EHCI_HCD && (SOC_AR71XX || SOC_AR724X || SOC_AR913X || SOC_AR933X)
         select USB_EHCI_ROOT_HUB_TT
         default y
         ---help---
diff --git a/drivers/usb/host/ehci-ath79.c b/drivers/usb/host/ehci-ath79.c
index afb6743cf09..f1424f9bc36 100644
--- a/drivers/usb/host/ehci-ath79.c
+++ b/drivers/usb/host/ehci-ath79.c
@@ -33,6 +33,10 @@ static const struct platform_device_id ehci_ath79_id_table[] = {
                 .driver_data    = EHCI_ATH79_IP_V2,
         },
         {
+                .name           = "ar933x-ehci",
+                .driver_data    = EHCI_ATH79_IP_V2,
+        },
+        {
                 /* terminating entry */
         },
 };
diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h
index eadf33d0abb..3c35fb2f688 100644
--- a/include/linux/serial_core.h
+++ b/include/linux/serial_core.h
@@ -207,6 +207,10 @@
 /* Xilinx PSS UART */
 #define PORT_XUARTPS    98
 
+/* Atheros AR933X SoC */
+#define PORT_AR933X     99
+
+
 #ifdef __KERNEL__
 
 #include <linux/compiler.h>