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-rw-r--r--drivers/net/wireless/ath/ath9k/btcoex.c75
1 files changed, 44 insertions, 31 deletions
diff --git a/drivers/net/wireless/ath/ath9k/btcoex.c b/drivers/net/wireless/ath/ath9k/btcoex.c
index dfbcbd0969e..be699241ca7 100644
--- a/drivers/net/wireless/ath/ath9k/btcoex.c
+++ b/drivers/net/wireless/ath/ath9k/btcoex.c
@@ -225,48 +225,61 @@ static int ath_init_btcoex_info(struct ath_hw *ah,
225 return 0; 225 return 0;
226} 226}
227 227
228int ath9k_hw_btcoex_init(struct ath_hw *ah) 228static void ath9k_hw_btcoex_init_2wire(struct ath_hw *ah)
229{ 229{
230 struct ath_btcoex_info *btcoex_info = &ah->btcoex_info; 230 struct ath_btcoex_info *btcoex_info = &ah->btcoex_info;
231 int ret = 0;
232 231
233 if (btcoex_info->btcoex_scheme == ATH_BTCOEX_CFG_2WIRE) { 232 /* connect bt_active to baseband */
234 /* connect bt_active to baseband */ 233 REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL,
235 REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL, 234 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
236 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF | 235 AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));
237 AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));
238 236
239 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, 237 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
240 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB); 238 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
241 239
242 /* Set input mux for bt_active to gpio pin */ 240 /* Set input mux for bt_active to gpio pin */
243 REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1, 241 REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
244 AR_GPIO_INPUT_MUX1_BT_ACTIVE, 242 AR_GPIO_INPUT_MUX1_BT_ACTIVE,
245 btcoex_info->btactive_gpio); 243 btcoex_info->btactive_gpio);
246 244
247 /* Configure the desired gpio port for input */ 245 /* Configure the desired gpio port for input */
248 ath9k_hw_cfg_gpio_input(ah, btcoex_info->btactive_gpio); 246 ath9k_hw_cfg_gpio_input(ah, btcoex_info->btactive_gpio);
249 } else { 247}
250 /* btcoex 3-wire */ 248
251 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, 249static void ath9k_hw_btcoex_init_3wire(struct ath_hw *ah)
252 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB | 250{
253 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB)); 251 struct ath_btcoex_info *btcoex_info = &ah->btcoex_info;
254 252
255 /* Set input mux for bt_prority_async and 253 /* btcoex 3-wire */
256 * bt_active_async to GPIO pins */ 254 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
257 REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1, 255 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB |
258 AR_GPIO_INPUT_MUX1_BT_ACTIVE, 256 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB));
259 btcoex_info->btactive_gpio);
260 257
261 REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1, 258 /* Set input mux for bt_prority_async and
262 AR_GPIO_INPUT_MUX1_BT_PRIORITY, 259 * bt_active_async to GPIO pins */
263 btcoex_info->btpriority_gpio); 260 REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
261 AR_GPIO_INPUT_MUX1_BT_ACTIVE,
262 btcoex_info->btactive_gpio);
264 263
265 /* Configure the desired GPIO ports for input */ 264 REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
265 AR_GPIO_INPUT_MUX1_BT_PRIORITY,
266 btcoex_info->btpriority_gpio);
266 267
267 ath9k_hw_cfg_gpio_input(ah, btcoex_info->btactive_gpio); 268 /* Configure the desired GPIO ports for input */
268 ath9k_hw_cfg_gpio_input(ah, btcoex_info->btpriority_gpio); 269
270 ath9k_hw_cfg_gpio_input(ah, btcoex_info->btactive_gpio);
271 ath9k_hw_cfg_gpio_input(ah, btcoex_info->btpriority_gpio);
272}
273
274int ath9k_hw_btcoex_init(struct ath_hw *ah)
275{
276 struct ath_btcoex_info *btcoex_info = &ah->btcoex_info;
277 int ret = 0;
269 278
279 if (btcoex_info->btcoex_scheme == ATH_BTCOEX_CFG_2WIRE)
280 ath9k_hw_btcoex_init_2wire(ah);
281 else {
282 ath9k_hw_btcoex_init_3wire(ah);
270 ret = ath_init_btcoex_info(ah, btcoex_info); 283 ret = ath_init_btcoex_info(ah, btcoex_info);
271 } 284 }
272 285