aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
-rw-r--r--drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c9
1 files changed, 5 insertions, 4 deletions
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
index ffeaaa95ed9..f4c2fe52ab1 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
@@ -10536,6 +10536,9 @@ static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
10536{ 10536{
10537 struct bnx2x *bp; 10537 struct bnx2x *bp;
10538 int rc; 10538 int rc;
10539 bool chip_is_e1x = (board_type == BCM57710 ||
10540 board_type == BCM57711 ||
10541 board_type == BCM57711E);
10539 10542
10540 SET_NETDEV_DEV(dev, &pdev->dev); 10543 SET_NETDEV_DEV(dev, &pdev->dev);
10541 bp = netdev_priv(dev); 10544 bp = netdev_priv(dev);
@@ -10624,7 +10627,7 @@ static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
10624 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0); 10627 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
10625 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0); 10628 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
10626 10629
10627 if (CHIP_IS_E1x(bp)) { 10630 if (chip_is_e1x) {
10628 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0); 10631 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
10629 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0); 10632 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
10630 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0); 10633 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
@@ -10635,9 +10638,7 @@ static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
10635 * Enable internal target-read (in case we are probed after PF FLR). 10638 * Enable internal target-read (in case we are probed after PF FLR).
10636 * Must be done prior to any BAR read access. Only for 57712 and up 10639 * Must be done prior to any BAR read access. Only for 57712 and up
10637 */ 10640 */
10638 if (board_type != BCM57710 && 10641 if (!chip_is_e1x)
10639 board_type != BCM57711 &&
10640 board_type != BCM57711E)
10641 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); 10642 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
10642 10643
10643 /* Reset the load counter */ 10644 /* Reset the load counter */