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-rw-r--r--drivers/gpu/drm/radeon/evergreen.c30
-rw-r--r--drivers/gpu/drm/radeon/evergreend.h10
-rw-r--r--drivers/gpu/drm/radeon/ni.c35
-rw-r--r--drivers/gpu/drm/radeon/nid.h2
-rw-r--r--drivers/gpu/drm/radeon/r600.c28
-rw-r--r--drivers/gpu/drm/radeon/si.c18
-rw-r--r--drivers/gpu/drm/radeon/sid.h16
7 files changed, 112 insertions, 27 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 6dc9ee78f4a..f92f6bb1887 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -2309,19 +2309,19 @@ bool evergreen_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *rin
2309static int evergreen_gpu_soft_reset(struct radeon_device *rdev) 2309static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
2310{ 2310{
2311 struct evergreen_mc_save save; 2311 struct evergreen_mc_save save;
2312 u32 grbm_reset = 0; 2312 u32 grbm_reset = 0, tmp;
2313 2313
2314 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE)) 2314 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
2315 return 0; 2315 return 0;
2316 2316
2317 dev_info(rdev->dev, "GPU softreset \n"); 2317 dev_info(rdev->dev, "GPU softreset \n");
2318 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n", 2318 dev_info(rdev->dev, " GRBM_STATUS = 0x%08X\n",
2319 RREG32(GRBM_STATUS)); 2319 RREG32(GRBM_STATUS));
2320 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n", 2320 dev_info(rdev->dev, " GRBM_STATUS_SE0 = 0x%08X\n",
2321 RREG32(GRBM_STATUS_SE0)); 2321 RREG32(GRBM_STATUS_SE0));
2322 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n", 2322 dev_info(rdev->dev, " GRBM_STATUS_SE1 = 0x%08X\n",
2323 RREG32(GRBM_STATUS_SE1)); 2323 RREG32(GRBM_STATUS_SE1));
2324 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n", 2324 dev_info(rdev->dev, " SRBM_STATUS = 0x%08X\n",
2325 RREG32(SRBM_STATUS)); 2325 RREG32(SRBM_STATUS));
2326 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n", 2326 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
2327 RREG32(CP_STALLED_STAT1)); 2327 RREG32(CP_STALLED_STAT1));
@@ -2337,9 +2337,21 @@ static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
2337 if (evergreen_mc_wait_for_idle(rdev)) { 2337 if (evergreen_mc_wait_for_idle(rdev)) {
2338 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 2338 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2339 } 2339 }
2340
2340 /* Disable CP parsing/prefetching */ 2341 /* Disable CP parsing/prefetching */
2341 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT); 2342 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
2342 2343
2344 /* Disable DMA */
2345 tmp = RREG32(DMA_RB_CNTL);
2346 tmp &= ~DMA_RB_ENABLE;
2347 WREG32(DMA_RB_CNTL, tmp);
2348
2349 /* Reset dma */
2350 WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA);
2351 RREG32(SRBM_SOFT_RESET);
2352 udelay(50);
2353 WREG32(SRBM_SOFT_RESET, 0);
2354
2343 /* reset all the gfx blocks */ 2355 /* reset all the gfx blocks */
2344 grbm_reset = (SOFT_RESET_CP | 2356 grbm_reset = (SOFT_RESET_CP |
2345 SOFT_RESET_CB | 2357 SOFT_RESET_CB |
@@ -2362,13 +2374,13 @@ static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
2362 (void)RREG32(GRBM_SOFT_RESET); 2374 (void)RREG32(GRBM_SOFT_RESET);
2363 /* Wait a little for things to settle down */ 2375 /* Wait a little for things to settle down */
2364 udelay(50); 2376 udelay(50);
2365 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n", 2377 dev_info(rdev->dev, " GRBM_STATUS = 0x%08X\n",
2366 RREG32(GRBM_STATUS)); 2378 RREG32(GRBM_STATUS));
2367 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n", 2379 dev_info(rdev->dev, " GRBM_STATUS_SE0 = 0x%08X\n",
2368 RREG32(GRBM_STATUS_SE0)); 2380 RREG32(GRBM_STATUS_SE0));
2369 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n", 2381 dev_info(rdev->dev, " GRBM_STATUS_SE1 = 0x%08X\n",
2370 RREG32(GRBM_STATUS_SE1)); 2382 RREG32(GRBM_STATUS_SE1));
2371 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n", 2383 dev_info(rdev->dev, " SRBM_STATUS = 0x%08X\n",
2372 RREG32(SRBM_STATUS)); 2384 RREG32(SRBM_STATUS));
2373 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n", 2385 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
2374 RREG32(CP_STALLED_STAT1)); 2386 RREG32(CP_STALLED_STAT1));
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
index f82f98a11a7..5786a32e7bd 100644
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -742,8 +742,9 @@
742#define SOFT_RESET_ROM (1 << 14) 742#define SOFT_RESET_ROM (1 << 14)
743#define SOFT_RESET_SEM (1 << 15) 743#define SOFT_RESET_SEM (1 << 15)
744#define SOFT_RESET_VMC (1 << 17) 744#define SOFT_RESET_VMC (1 << 17)
745#define SOFT_RESET_DMA (1 << 20)
745#define SOFT_RESET_TST (1 << 21) 746#define SOFT_RESET_TST (1 << 21)
746#define SOFT_RESET_REGBB (1 << 22) 747#define SOFT_RESET_REGBB (1 << 22)
747#define SOFT_RESET_ORB (1 << 23) 748#define SOFT_RESET_ORB (1 << 23)
748 749
749/* display watermarks */ 750/* display watermarks */
@@ -2028,6 +2029,13 @@
2028#define CAYMAN_PACKET3_DEALLOC_STATE 0x14 2029#define CAYMAN_PACKET3_DEALLOC_STATE 0x14
2029 2030
2030/* DMA regs common on r6xx/r7xx/evergreen/ni */ 2031/* DMA regs common on r6xx/r7xx/evergreen/ni */
2032#define DMA_RB_CNTL 0xd000
2033# define DMA_RB_ENABLE (1 << 0)
2034# define DMA_RB_SIZE(x) ((x) << 1) /* log2 */
2035# define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */
2036# define DMA_RPTR_WRITEBACK_ENABLE (1 << 12)
2037# define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */
2038# define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */
2031#define DMA_STATUS_REG 0xd034 2039#define DMA_STATUS_REG 0xd034
2032 2040
2033#endif 2041#endif
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index 6dae3878e39..8a9a75d1cb0 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -1309,19 +1309,19 @@ void cayman_dma_fini(struct radeon_device *rdev)
1309static int cayman_gpu_soft_reset(struct radeon_device *rdev) 1309static int cayman_gpu_soft_reset(struct radeon_device *rdev)
1310{ 1310{
1311 struct evergreen_mc_save save; 1311 struct evergreen_mc_save save;
1312 u32 grbm_reset = 0; 1312 u32 grbm_reset = 0, tmp;
1313 1313
1314 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE)) 1314 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
1315 return 0; 1315 return 0;
1316 1316
1317 dev_info(rdev->dev, "GPU softreset \n"); 1317 dev_info(rdev->dev, "GPU softreset \n");
1318 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n", 1318 dev_info(rdev->dev, " GRBM_STATUS = 0x%08X\n",
1319 RREG32(GRBM_STATUS)); 1319 RREG32(GRBM_STATUS));
1320 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n", 1320 dev_info(rdev->dev, " GRBM_STATUS_SE0 = 0x%08X\n",
1321 RREG32(GRBM_STATUS_SE0)); 1321 RREG32(GRBM_STATUS_SE0));
1322 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n", 1322 dev_info(rdev->dev, " GRBM_STATUS_SE1 = 0x%08X\n",
1323 RREG32(GRBM_STATUS_SE1)); 1323 RREG32(GRBM_STATUS_SE1));
1324 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n", 1324 dev_info(rdev->dev, " SRBM_STATUS = 0x%08X\n",
1325 RREG32(SRBM_STATUS)); 1325 RREG32(SRBM_STATUS));
1326 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n", 1326 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
1327 RREG32(CP_STALLED_STAT1)); 1327 RREG32(CP_STALLED_STAT1));
@@ -1346,9 +1346,26 @@ static int cayman_gpu_soft_reset(struct radeon_device *rdev)
1346 if (evergreen_mc_wait_for_idle(rdev)) { 1346 if (evergreen_mc_wait_for_idle(rdev)) {
1347 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1347 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1348 } 1348 }
1349
1349 /* Disable CP parsing/prefetching */ 1350 /* Disable CP parsing/prefetching */
1350 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT); 1351 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
1351 1352
1353 /* dma0 */
1354 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
1355 tmp &= ~DMA_RB_ENABLE;
1356 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
1357
1358 /* dma1 */
1359 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
1360 tmp &= ~DMA_RB_ENABLE;
1361 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
1362
1363 /* Reset dma */
1364 WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA | SOFT_RESET_DMA1);
1365 RREG32(SRBM_SOFT_RESET);
1366 udelay(50);
1367 WREG32(SRBM_SOFT_RESET, 0);
1368
1352 /* reset all the gfx blocks */ 1369 /* reset all the gfx blocks */
1353 grbm_reset = (SOFT_RESET_CP | 1370 grbm_reset = (SOFT_RESET_CP |
1354 SOFT_RESET_CB | 1371 SOFT_RESET_CB |
@@ -1373,13 +1390,13 @@ static int cayman_gpu_soft_reset(struct radeon_device *rdev)
1373 /* Wait a little for things to settle down */ 1390 /* Wait a little for things to settle down */
1374 udelay(50); 1391 udelay(50);
1375 1392
1376 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n", 1393 dev_info(rdev->dev, " GRBM_STATUS = 0x%08X\n",
1377 RREG32(GRBM_STATUS)); 1394 RREG32(GRBM_STATUS));
1378 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n", 1395 dev_info(rdev->dev, " GRBM_STATUS_SE0 = 0x%08X\n",
1379 RREG32(GRBM_STATUS_SE0)); 1396 RREG32(GRBM_STATUS_SE0));
1380 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n", 1397 dev_info(rdev->dev, " GRBM_STATUS_SE1 = 0x%08X\n",
1381 RREG32(GRBM_STATUS_SE1)); 1398 RREG32(GRBM_STATUS_SE1));
1382 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n", 1399 dev_info(rdev->dev, " SRBM_STATUS = 0x%08X\n",
1383 RREG32(SRBM_STATUS)); 1400 RREG32(SRBM_STATUS));
1384 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n", 1401 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
1385 RREG32(CP_STALLED_STAT1)); 1402 RREG32(CP_STALLED_STAT1));
diff --git a/drivers/gpu/drm/radeon/nid.h b/drivers/gpu/drm/radeon/nid.h
index 22a62c673fe..48e5022ee92 100644
--- a/drivers/gpu/drm/radeon/nid.h
+++ b/drivers/gpu/drm/radeon/nid.h
@@ -65,7 +65,7 @@
65#define SOFT_RESET_VMC (1 << 17) 65#define SOFT_RESET_VMC (1 << 17)
66#define SOFT_RESET_DMA (1 << 20) 66#define SOFT_RESET_DMA (1 << 20)
67#define SOFT_RESET_TST (1 << 21) 67#define SOFT_RESET_TST (1 << 21)
68#define SOFT_RESET_REGBB (1 << 22) 68#define SOFT_RESET_REGBB (1 << 22)
69#define SOFT_RESET_ORB (1 << 23) 69#define SOFT_RESET_ORB (1 << 23)
70 70
71#define VM_CONTEXT0_REQUEST_RESPONSE 0x1470 71#define VM_CONTEXT0_REQUEST_RESPONSE 0x1470
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 252067bba2d..721b5afd792 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -1283,11 +1283,11 @@ static int r600_gpu_soft_reset(struct radeon_device *rdev)
1283 return 0; 1283 return 0;
1284 1284
1285 dev_info(rdev->dev, "GPU softreset \n"); 1285 dev_info(rdev->dev, "GPU softreset \n");
1286 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n", 1286 dev_info(rdev->dev, " R_008010_GRBM_STATUS = 0x%08X\n",
1287 RREG32(R_008010_GRBM_STATUS)); 1287 RREG32(R_008010_GRBM_STATUS));
1288 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n", 1288 dev_info(rdev->dev, " R_008014_GRBM_STATUS2 = 0x%08X\n",
1289 RREG32(R_008014_GRBM_STATUS2)); 1289 RREG32(R_008014_GRBM_STATUS2));
1290 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n", 1290 dev_info(rdev->dev, " R_000E50_SRBM_STATUS = 0x%08X\n",
1291 RREG32(R_000E50_SRBM_STATUS)); 1291 RREG32(R_000E50_SRBM_STATUS));
1292 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n", 1292 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
1293 RREG32(CP_STALLED_STAT1)); 1293 RREG32(CP_STALLED_STAT1));
@@ -1303,8 +1303,24 @@ static int r600_gpu_soft_reset(struct radeon_device *rdev)
1303 if (r600_mc_wait_for_idle(rdev)) { 1303 if (r600_mc_wait_for_idle(rdev)) {
1304 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1304 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1305 } 1305 }
1306
1306 /* Disable CP parsing/prefetching */ 1307 /* Disable CP parsing/prefetching */
1307 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); 1308 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1309
1310 /* Disable DMA */
1311 tmp = RREG32(DMA_RB_CNTL);
1312 tmp &= ~DMA_RB_ENABLE;
1313 WREG32(DMA_RB_CNTL, tmp);
1314
1315 /* Reset dma */
1316 if (rdev->family >= CHIP_RV770)
1317 WREG32(SRBM_SOFT_RESET, RV770_SOFT_RESET_DMA);
1318 else
1319 WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA);
1320 RREG32(SRBM_SOFT_RESET);
1321 udelay(50);
1322 WREG32(SRBM_SOFT_RESET, 0);
1323
1308 /* Check if any of the rendering block is busy and reset it */ 1324 /* Check if any of the rendering block is busy and reset it */
1309 if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) || 1325 if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
1310 (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) { 1326 (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
@@ -1336,11 +1352,11 @@ static int r600_gpu_soft_reset(struct radeon_device *rdev)
1336 WREG32(R_008020_GRBM_SOFT_RESET, 0); 1352 WREG32(R_008020_GRBM_SOFT_RESET, 0);
1337 /* Wait a little for things to settle down */ 1353 /* Wait a little for things to settle down */
1338 mdelay(1); 1354 mdelay(1);
1339 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n", 1355 dev_info(rdev->dev, " R_008010_GRBM_STATUS = 0x%08X\n",
1340 RREG32(R_008010_GRBM_STATUS)); 1356 RREG32(R_008010_GRBM_STATUS));
1341 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n", 1357 dev_info(rdev->dev, " R_008014_GRBM_STATUS2 = 0x%08X\n",
1342 RREG32(R_008014_GRBM_STATUS2)); 1358 RREG32(R_008014_GRBM_STATUS2));
1343 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n", 1359 dev_info(rdev->dev, " R_000E50_SRBM_STATUS = 0x%08X\n",
1344 RREG32(R_000E50_SRBM_STATUS)); 1360 RREG32(R_000E50_SRBM_STATUS));
1345 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n", 1361 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
1346 RREG32(CP_STALLED_STAT1)); 1362 RREG32(CP_STALLED_STAT1));
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 74d38452c5c..4bf17334927 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -2129,7 +2129,7 @@ bool si_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2129static int si_gpu_soft_reset(struct radeon_device *rdev) 2129static int si_gpu_soft_reset(struct radeon_device *rdev)
2130{ 2130{
2131 struct evergreen_mc_save save; 2131 struct evergreen_mc_save save;
2132 u32 grbm_reset = 0; 2132 u32 grbm_reset = 0, tmp;
2133 2133
2134 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE)) 2134 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
2135 return 0; 2135 return 0;
@@ -2159,6 +2159,22 @@ static int si_gpu_soft_reset(struct radeon_device *rdev)
2159 /* Disable CP parsing/prefetching */ 2159 /* Disable CP parsing/prefetching */
2160 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT); 2160 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
2161 2161
2162 /* dma0 */
2163 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
2164 tmp &= ~DMA_RB_ENABLE;
2165 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
2166
2167 /* dma1 */
2168 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
2169 tmp &= ~DMA_RB_ENABLE;
2170 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
2171
2172 /* Reset dma */
2173 WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA | SOFT_RESET_DMA1);
2174 RREG32(SRBM_SOFT_RESET);
2175 udelay(50);
2176 WREG32(SRBM_SOFT_RESET, 0);
2177
2162 /* reset all the gfx blocks */ 2178 /* reset all the gfx blocks */
2163 grbm_reset = (SOFT_RESET_CP | 2179 grbm_reset = (SOFT_RESET_CP |
2164 SOFT_RESET_CB | 2180 SOFT_RESET_CB |
diff --git a/drivers/gpu/drm/radeon/sid.h b/drivers/gpu/drm/radeon/sid.h
index 98909b264ac..c056aae814f 100644
--- a/drivers/gpu/drm/radeon/sid.h
+++ b/drivers/gpu/drm/radeon/sid.h
@@ -62,6 +62,22 @@
62 62
63#define SRBM_STATUS 0xE50 63#define SRBM_STATUS 0xE50
64 64
65#define SRBM_SOFT_RESET 0x0E60
66#define SOFT_RESET_BIF (1 << 1)
67#define SOFT_RESET_DC (1 << 5)
68#define SOFT_RESET_DMA1 (1 << 6)
69#define SOFT_RESET_GRBM (1 << 8)
70#define SOFT_RESET_HDP (1 << 9)
71#define SOFT_RESET_IH (1 << 10)
72#define SOFT_RESET_MC (1 << 11)
73#define SOFT_RESET_ROM (1 << 14)
74#define SOFT_RESET_SEM (1 << 15)
75#define SOFT_RESET_VMC (1 << 17)
76#define SOFT_RESET_DMA (1 << 20)
77#define SOFT_RESET_TST (1 << 21)
78#define SOFT_RESET_REGBB (1 << 22)
79#define SOFT_RESET_ORB (1 << 23)
80
65#define CC_SYS_RB_BACKEND_DISABLE 0xe80 81#define CC_SYS_RB_BACKEND_DISABLE 0xe80
66#define GC_USER_SYS_RB_BACKEND_DISABLE 0xe84 82#define GC_USER_SYS_RB_BACKEND_DISABLE 0xe84
67 83
generated by cgit v1.2.2 (git 2.25.0) at 2026-04-27 15:45:21 -0400