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-rw-r--r--drivers/net/wireless/rt2x00/Kconfig12
-rw-r--r--drivers/net/wireless/rt2x00/rt2800.h59
-rw-r--r--drivers/net/wireless/rt2x00/rt2800lib.c413
-rw-r--r--drivers/net/wireless/rt2x00/rt2800pci.c10
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00.h1
5 files changed, 440 insertions, 55 deletions
diff --git a/drivers/net/wireless/rt2x00/Kconfig b/drivers/net/wireless/rt2x00/Kconfig
index 6f383cd684b..f630552427b 100644
--- a/drivers/net/wireless/rt2x00/Kconfig
+++ b/drivers/net/wireless/rt2x00/Kconfig
@@ -97,6 +97,18 @@ config RT2800PCI_RT35XX
97 Support for these devices is non-functional at the moment and is 97 Support for these devices is non-functional at the moment and is
98 intended for testers and developers. 98 intended for testers and developers.
99 99
100config RT2800PCI_RT53XX
101 bool "rt2800-pci - Include support for rt53xx devices (EXPERIMENTAL)"
102 depends on EXPERIMENTAL
103 default n
104 ---help---
105 This adds support for rt53xx wireless chipset family to the
106 rt2800pci driver.
107 Supported chips: RT5390
108
109 Support for these devices is non-functional at the moment and is
110 intended for testers and developers.
111
100endif 112endif
101 113
102config RT2500USB 114config RT2500USB
diff --git a/drivers/net/wireless/rt2x00/rt2800.h b/drivers/net/wireless/rt2x00/rt2800.h
index 591ac32b014..6f4a2432c02 100644
--- a/drivers/net/wireless/rt2x00/rt2800.h
+++ b/drivers/net/wireless/rt2x00/rt2800.h
@@ -51,6 +51,7 @@
51 * RF3320 2.4G 1T1R(RT3350/RT3370/RT3390) 51 * RF3320 2.4G 1T1R(RT3350/RT3370/RT3390)
52 * RF3322 2.4G 2T2R(RT3352/RT3371/RT3372/RT3391/RT3392) 52 * RF3322 2.4G 2T2R(RT3352/RT3371/RT3372/RT3391/RT3392)
53 * RF3853 2.4G/5G 3T3R(RT3883/RT3563/RT3573/RT3593/RT3662) 53 * RF3853 2.4G/5G 3T3R(RT3883/RT3563/RT3573/RT3593/RT3662)
54 * RF5390 2.4G 1T1R
54 */ 55 */
55#define RF2820 0x0001 56#define RF2820 0x0001
56#define RF2850 0x0002 57#define RF2850 0x0002
@@ -65,6 +66,7 @@
65#define RF3320 0x000b 66#define RF3320 0x000b
66#define RF3322 0x000c 67#define RF3322 0x000c
67#define RF3853 0x000d 68#define RF3853 0x000d
69#define RF5390 0x5390
68 70
69/* 71/*
70 * Chipset revisions. 72 * Chipset revisions.
@@ -77,6 +79,7 @@
77#define REV_RT3071E 0x0211 79#define REV_RT3071E 0x0211
78#define REV_RT3090E 0x0211 80#define REV_RT3090E 0x0211
79#define REV_RT3390E 0x0211 81#define REV_RT3390E 0x0211
82#define REV_RT5390F 0x0502
80 83
81/* 84/*
82 * Signal information. 85 * Signal information.
@@ -121,6 +124,13 @@
121#define E2PROM_CSR_RELOAD FIELD32(0x00000080) 124#define E2PROM_CSR_RELOAD FIELD32(0x00000080)
122 125
123/* 126/*
127 * AUX_CTRL: Aux/PCI-E related configuration
128 */
129#define AUX_CTRL 0x10c
130#define AUX_CTRL_WAKE_PCIE_EN FIELD32(0x00000002)
131#define AUX_CTRL_FORCE_PCIE_CLK FIELD32(0x00000400)
132
133/*
124 * OPT_14: Unknown register used by rt3xxx devices. 134 * OPT_14: Unknown register used by rt3xxx devices.
125 */ 135 */
126#define OPT_14_CSR 0x0114 136#define OPT_14_CSR 0x0114
@@ -454,7 +464,7 @@
454 */ 464 */
455#define RF_CSR_CFG 0x0500 465#define RF_CSR_CFG 0x0500
456#define RF_CSR_CFG_DATA FIELD32(0x000000ff) 466#define RF_CSR_CFG_DATA FIELD32(0x000000ff)
457#define RF_CSR_CFG_REGNUM FIELD32(0x00001f00) 467#define RF_CSR_CFG_REGNUM FIELD32(0x00003f00)
458#define RF_CSR_CFG_WRITE FIELD32(0x00010000) 468#define RF_CSR_CFG_WRITE FIELD32(0x00010000)
459#define RF_CSR_CFG_BUSY FIELD32(0x00020000) 469#define RF_CSR_CFG_BUSY FIELD32(0x00020000)
460 470
@@ -1736,6 +1746,13 @@ struct mac_iveiv_entry {
1736 */ 1746 */
1737#define BBP4_TX_BF FIELD8(0x01) 1747#define BBP4_TX_BF FIELD8(0x01)
1738#define BBP4_BANDWIDTH FIELD8(0x18) 1748#define BBP4_BANDWIDTH FIELD8(0x18)
1749#define BBP4_MAC_IF_CTRL FIELD8(0x40)
1750
1751/*
1752 * BBP 109
1753 */
1754#define BBP109_TX0_POWER FIELD8(0x0f)
1755#define BBP109_TX1_POWER FIELD8(0xf0)
1739 1756
1740/* 1757/*
1741 * BBP 138: Unknown 1758 * BBP 138: Unknown
@@ -1746,6 +1763,11 @@ struct mac_iveiv_entry {
1746#define BBP138_TX_DAC2 FIELD8(0x40) 1763#define BBP138_TX_DAC2 FIELD8(0x40)
1747 1764
1748/* 1765/*
1766 * BBP 152: Rx Ant
1767 */
1768#define BBP152_RX_DEFAULT_ANT FIELD8(0x80)
1769
1770/*
1749 * RFCSR registers 1771 * RFCSR registers
1750 * The wordsize of the RFCSR is 8 bits. 1772 * The wordsize of the RFCSR is 8 bits.
1751 */ 1773 */
@@ -1754,12 +1776,18 @@ struct mac_iveiv_entry {
1754 * RFCSR 1: 1776 * RFCSR 1:
1755 */ 1777 */
1756#define RFCSR1_RF_BLOCK_EN FIELD8(0x01) 1778#define RFCSR1_RF_BLOCK_EN FIELD8(0x01)
1779#define RFCSR1_PLL_PD FIELD8(0x02)
1757#define RFCSR1_RX0_PD FIELD8(0x04) 1780#define RFCSR1_RX0_PD FIELD8(0x04)
1758#define RFCSR1_TX0_PD FIELD8(0x08) 1781#define RFCSR1_TX0_PD FIELD8(0x08)
1759#define RFCSR1_RX1_PD FIELD8(0x10) 1782#define RFCSR1_RX1_PD FIELD8(0x10)
1760#define RFCSR1_TX1_PD FIELD8(0x20) 1783#define RFCSR1_TX1_PD FIELD8(0x20)
1761 1784
1762/* 1785/*
1786 * RFCSR 2:
1787 */
1788#define RFCSR2_RESCAL_EN FIELD8(0x80)
1789
1790/*
1763 * RFCSR 6: 1791 * RFCSR 6:
1764 */ 1792 */
1765#define RFCSR6_R1 FIELD8(0x03) 1793#define RFCSR6_R1 FIELD8(0x03)
@@ -1771,6 +1799,11 @@ struct mac_iveiv_entry {
1771#define RFCSR7_RF_TUNING FIELD8(0x01) 1799#define RFCSR7_RF_TUNING FIELD8(0x01)
1772 1800
1773/* 1801/*
1802 * RFCSR 11:
1803 */
1804#define RFCSR11_R FIELD8(0x03)
1805
1806/*
1774 * RFCSR 12: 1807 * RFCSR 12:
1775 */ 1808 */
1776#define RFCSR12_TX_POWER FIELD8(0x1f) 1809#define RFCSR12_TX_POWER FIELD8(0x1f)
@@ -1791,6 +1824,7 @@ struct mac_iveiv_entry {
1791#define RFCSR17_TXMIXER_GAIN FIELD8(0x07) 1824#define RFCSR17_TXMIXER_GAIN FIELD8(0x07)
1792#define RFCSR17_TX_LO1_EN FIELD8(0x08) 1825#define RFCSR17_TX_LO1_EN FIELD8(0x08)
1793#define RFCSR17_R FIELD8(0x20) 1826#define RFCSR17_R FIELD8(0x20)
1827#define RFCSR17_CODE FIELD8(0x7f)
1794 1828
1795/* 1829/*
1796 * RFCSR 20: 1830 * RFCSR 20:
@@ -1823,6 +1857,9 @@ struct mac_iveiv_entry {
1823/* 1857/*
1824 * RFCSR 30: 1858 * RFCSR 30:
1825 */ 1859 */
1860#define RFCSR30_TX_H20M FIELD8(0x02)
1861#define RFCSR30_RX_H20M FIELD8(0x04)
1862#define RFCSR30_RX_VCM FIELD8(0x18)
1826#define RFCSR30_RF_CALIBRATION FIELD8(0x80) 1863#define RFCSR30_RF_CALIBRATION FIELD8(0x80)
1827 1864
1828/* 1865/*
@@ -1832,6 +1869,21 @@ struct mac_iveiv_entry {
1832#define RFCSR31_RX_H20M FIELD8(0x20) 1869#define RFCSR31_RX_H20M FIELD8(0x20)
1833 1870
1834/* 1871/*
1872 * RFCSR 38:
1873 */
1874#define RFCSR38_RX_LO1_EN FIELD8(0x20)
1875
1876/*
1877 * RFCSR 39:
1878 */
1879#define RFCSR39_RX_LO2_EN FIELD8(0x80)
1880
1881/*
1882 * RFCSR 49:
1883 */
1884#define RFCSR49_TX FIELD8(0x3f)
1885
1886/*
1835 * RF registers 1887 * RF registers
1836 */ 1888 */
1837 1889
@@ -1864,6 +1916,11 @@ struct mac_iveiv_entry {
1864 */ 1916 */
1865 1917
1866/* 1918/*
1919 * Chip ID
1920 */
1921#define EEPROM_CHIP_ID 0x0000
1922
1923/*
1867 * EEPROM Version 1924 * EEPROM Version
1868 */ 1925 */
1869#define EEPROM_VERSION 0x0001 1926#define EEPROM_VERSION 0x0001
diff --git a/drivers/net/wireless/rt2x00/rt2800lib.c b/drivers/net/wireless/rt2x00/rt2800lib.c
index 5dd10589cff..3da78bf0ca2 100644
--- a/drivers/net/wireless/rt2x00/rt2800lib.c
+++ b/drivers/net/wireless/rt2x00/rt2800lib.c
@@ -400,8 +400,15 @@ int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
400 if (rt2800_wait_csr_ready(rt2x00dev)) 400 if (rt2800_wait_csr_ready(rt2x00dev))
401 return -EBUSY; 401 return -EBUSY;
402 402
403 if (rt2x00_is_pci(rt2x00dev)) 403 if (rt2x00_is_pci(rt2x00dev)) {
404 if (rt2x00_rt(rt2x00dev, RT5390)) {
405 rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
406 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
407 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
408 rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
409 }
404 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002); 410 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
411 }
405 412
406 /* 413 /*
407 * Disable DMA, will be reenabled later when enabling 414 * Disable DMA, will be reenabled later when enabling
@@ -1573,6 +1580,99 @@ static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1573 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); 1580 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1574} 1581}
1575 1582
1583
1584#define RT5390_POWER_BOUND 0x27
1585#define RT5390_FREQ_OFFSET_BOUND 0x5f
1586
1587static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
1588 struct ieee80211_conf *conf,
1589 struct rf_channel *rf,
1590 struct channel_info *info)
1591{
1592 u8 rfcsr;
1593 u16 eeprom;
1594
1595 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
1596 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
1597 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
1598 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
1599 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
1600
1601 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
1602 if (info->default_power1 > RT5390_POWER_BOUND)
1603 rt2x00_set_field8(&rfcsr, RFCSR49_TX, RT5390_POWER_BOUND);
1604 else
1605 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
1606 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
1607
1608 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1609 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
1610 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
1611 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
1612 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
1613 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1614
1615 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
1616 if (rt2x00dev->freq_offset > RT5390_FREQ_OFFSET_BOUND)
1617 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, RT5390_FREQ_OFFSET_BOUND);
1618 else
1619 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
1620 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
1621
1622 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
1623 if (rf->channel <= 14) {
1624 int idx = rf->channel-1;
1625
1626 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST)) {
1627 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
1628 /* r55/r59 value array of channel 1~14 */
1629 static const char r55_bt_rev[] = {0x83, 0x83,
1630 0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
1631 0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
1632 static const char r59_bt_rev[] = {0x0e, 0x0e,
1633 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
1634 0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
1635
1636 rt2800_rfcsr_write(rt2x00dev, 55, r55_bt_rev[idx]);
1637 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt_rev[idx]);
1638 } else {
1639 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
1640 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
1641 0x88, 0x88, 0x86, 0x85, 0x84};
1642
1643 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
1644 }
1645 } else {
1646 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
1647 static const char r55_nonbt_rev[] = {0x23, 0x23,
1648 0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
1649 0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
1650 static const char r59_nonbt_rev[] = {0x07, 0x07,
1651 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
1652 0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
1653
1654 rt2800_rfcsr_write(rt2x00dev, 55, r55_nonbt_rev[idx]);
1655 rt2800_rfcsr_write(rt2x00dev, 59, r59_nonbt_rev[idx]);
1656 } else if (rt2x00_rt(rt2x00dev, RT5390)) {
1657 static const char r59_non_bt[] = {0x8f, 0x8f,
1658 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
1659 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
1660
1661 rt2800_rfcsr_write(rt2x00dev, 59, r59_non_bt[idx]);
1662 }
1663 }
1664 }
1665
1666 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1667 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
1668 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
1669 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1670
1671 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
1672 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1673 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
1674}
1675
1576static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev, 1676static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
1577 struct ieee80211_conf *conf, 1677 struct ieee80211_conf *conf,
1578 struct rf_channel *rf, 1678 struct rf_channel *rf,
@@ -1597,6 +1697,8 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
1597 rt2x00_rf(rt2x00dev, RF3052) || 1697 rt2x00_rf(rt2x00dev, RF3052) ||
1598 rt2x00_rf(rt2x00dev, RF3320)) 1698 rt2x00_rf(rt2x00dev, RF3320))
1599 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info); 1699 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
1700 else if (rt2x00_rf(rt2x00dev, RF5390))
1701 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
1600 else 1702 else
1601 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info); 1703 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
1602 1704
@@ -1609,12 +1711,14 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
1609 rt2800_bbp_write(rt2x00dev, 86, 0); 1711 rt2800_bbp_write(rt2x00dev, 86, 0);
1610 1712
1611 if (rf->channel <= 14) { 1713 if (rf->channel <= 14) {
1612 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) { 1714 if (!rt2x00_rt(rt2x00dev, RT5390)) {
1613 rt2800_bbp_write(rt2x00dev, 82, 0x62); 1715 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
1614 rt2800_bbp_write(rt2x00dev, 75, 0x46); 1716 rt2800_bbp_write(rt2x00dev, 82, 0x62);
1615 } else { 1717 rt2800_bbp_write(rt2x00dev, 75, 0x46);
1616 rt2800_bbp_write(rt2x00dev, 82, 0x84); 1718 } else {
1617 rt2800_bbp_write(rt2x00dev, 75, 0x50); 1719 rt2800_bbp_write(rt2x00dev, 82, 0x84);
1720 rt2800_bbp_write(rt2x00dev, 75, 0x50);
1721 }
1618 } 1722 }
1619 } else { 1723 } else {
1620 rt2800_bbp_write(rt2x00dev, 82, 0xf2); 1724 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
@@ -1993,7 +2097,8 @@ static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1993 if (rt2x00_rt(rt2x00dev, RT3070) || 2097 if (rt2x00_rt(rt2x00dev, RT3070) ||
1994 rt2x00_rt(rt2x00dev, RT3071) || 2098 rt2x00_rt(rt2x00dev, RT3071) ||
1995 rt2x00_rt(rt2x00dev, RT3090) || 2099 rt2x00_rt(rt2x00dev, RT3090) ||
1996 rt2x00_rt(rt2x00dev, RT3390)) 2100 rt2x00_rt(rt2x00dev, RT3390) ||
2101 rt2x00_rt(rt2x00dev, RT5390))
1997 return 0x1c + (2 * rt2x00dev->lna_gain); 2102 return 0x1c + (2 * rt2x00dev->lna_gain);
1998 else 2103 else
1999 return 0x2e + rt2x00dev->lna_gain; 2104 return 0x2e + rt2x00dev->lna_gain;
@@ -2125,6 +2230,10 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
2125 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); 2230 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2126 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 2231 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2127 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000001f); 2232 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000001f);
2233 } else if (rt2x00_rt(rt2x00dev, RT5390)) {
2234 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
2235 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2236 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2128 } else { 2237 } else {
2129 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000); 2238 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
2130 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 2239 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
@@ -2500,15 +2609,31 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
2500 rt2800_wait_bbp_ready(rt2x00dev))) 2609 rt2800_wait_bbp_ready(rt2x00dev)))
2501 return -EACCES; 2610 return -EACCES;
2502 2611
2503 if (rt2800_is_305x_soc(rt2x00dev)) 2612 if (rt2x00_rt(rt2x00dev, RT5390)) {
2613 rt2800_bbp_read(rt2x00dev, 4, &value);
2614 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
2615 rt2800_bbp_write(rt2x00dev, 4, value);
2616 }
2617
2618 if (rt2800_is_305x_soc(rt2x00dev) ||
2619 rt2x00_rt(rt2x00dev, RT5390))
2504 rt2800_bbp_write(rt2x00dev, 31, 0x08); 2620 rt2800_bbp_write(rt2x00dev, 31, 0x08);
2505 2621
2506 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 2622 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
2507 rt2800_bbp_write(rt2x00dev, 66, 0x38); 2623 rt2800_bbp_write(rt2x00dev, 66, 0x38);
2508 2624
2625 if (rt2x00_rt(rt2x00dev, RT5390))
2626 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
2627
2509 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) { 2628 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
2510 rt2800_bbp_write(rt2x00dev, 69, 0x16); 2629 rt2800_bbp_write(rt2x00dev, 69, 0x16);
2511 rt2800_bbp_write(rt2x00dev, 73, 0x12); 2630 rt2800_bbp_write(rt2x00dev, 73, 0x12);
2631 } else if (rt2x00_rt(rt2x00dev, RT5390)) {
2632 rt2800_bbp_write(rt2x00dev, 69, 0x12);
2633 rt2800_bbp_write(rt2x00dev, 73, 0x13);
2634 rt2800_bbp_write(rt2x00dev, 75, 0x46);
2635 rt2800_bbp_write(rt2x00dev, 76, 0x28);
2636 rt2800_bbp_write(rt2x00dev, 77, 0x59);
2512 } else { 2637 } else {
2513 rt2800_bbp_write(rt2x00dev, 69, 0x12); 2638 rt2800_bbp_write(rt2x00dev, 69, 0x12);
2514 rt2800_bbp_write(rt2x00dev, 73, 0x10); 2639 rt2800_bbp_write(rt2x00dev, 73, 0x10);
@@ -2519,7 +2644,8 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
2519 if (rt2x00_rt(rt2x00dev, RT3070) || 2644 if (rt2x00_rt(rt2x00dev, RT3070) ||
2520 rt2x00_rt(rt2x00dev, RT3071) || 2645 rt2x00_rt(rt2x00dev, RT3071) ||
2521 rt2x00_rt(rt2x00dev, RT3090) || 2646 rt2x00_rt(rt2x00dev, RT3090) ||
2522 rt2x00_rt(rt2x00dev, RT3390)) { 2647 rt2x00_rt(rt2x00dev, RT3390) ||
2648 rt2x00_rt(rt2x00dev, RT5390)) {
2523 rt2800_bbp_write(rt2x00dev, 79, 0x13); 2649 rt2800_bbp_write(rt2x00dev, 79, 0x13);
2524 rt2800_bbp_write(rt2x00dev, 80, 0x05); 2650 rt2800_bbp_write(rt2x00dev, 80, 0x05);
2525 rt2800_bbp_write(rt2x00dev, 81, 0x33); 2651 rt2800_bbp_write(rt2x00dev, 81, 0x33);
@@ -2531,35 +2657,62 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
2531 } 2657 }
2532 2658
2533 rt2800_bbp_write(rt2x00dev, 82, 0x62); 2659 rt2800_bbp_write(rt2x00dev, 82, 0x62);
2534 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 2660 if (rt2x00_rt(rt2x00dev, RT5390))
2661 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
2662 else
2663 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
2535 2664
2536 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D)) 2665 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
2537 rt2800_bbp_write(rt2x00dev, 84, 0x19); 2666 rt2800_bbp_write(rt2x00dev, 84, 0x19);
2667 else if (rt2x00_rt(rt2x00dev, RT5390))
2668 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
2538 else 2669 else
2539 rt2800_bbp_write(rt2x00dev, 84, 0x99); 2670 rt2800_bbp_write(rt2x00dev, 84, 0x99);
2540 2671
2541 rt2800_bbp_write(rt2x00dev, 86, 0x00); 2672 if (rt2x00_rt(rt2x00dev, RT5390))
2673 rt2800_bbp_write(rt2x00dev, 86, 0x38);
2674 else
2675 rt2800_bbp_write(rt2x00dev, 86, 0x00);
2676
2542 rt2800_bbp_write(rt2x00dev, 91, 0x04); 2677 rt2800_bbp_write(rt2x00dev, 91, 0x04);
2543 rt2800_bbp_write(rt2x00dev, 92, 0x00); 2678
2679 if (rt2x00_rt(rt2x00dev, RT5390))
2680 rt2800_bbp_write(rt2x00dev, 92, 0x02);
2681 else
2682 rt2800_bbp_write(rt2x00dev, 92, 0x00);
2544 2683
2545 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) || 2684 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
2546 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) || 2685 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
2547 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) || 2686 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
2548 rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) || 2687 rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
2688 rt2x00_rt(rt2x00dev, RT5390) ||
2549 rt2800_is_305x_soc(rt2x00dev)) 2689 rt2800_is_305x_soc(rt2x00dev))
2550 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 2690 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
2551 else 2691 else
2552 rt2800_bbp_write(rt2x00dev, 103, 0x00); 2692 rt2800_bbp_write(rt2x00dev, 103, 0x00);
2553 2693
2694 if (rt2x00_rt(rt2x00dev, RT5390))
2695 rt2800_bbp_write(rt2x00dev, 104, 0x92);
2696
2554 if (rt2800_is_305x_soc(rt2x00dev)) 2697 if (rt2800_is_305x_soc(rt2x00dev))
2555 rt2800_bbp_write(rt2x00dev, 105, 0x01); 2698 rt2800_bbp_write(rt2x00dev, 105, 0x01);
2699 else if (rt2x00_rt(rt2x00dev, RT5390))
2700 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
2556 else 2701 else
2557 rt2800_bbp_write(rt2x00dev, 105, 0x05); 2702 rt2800_bbp_write(rt2x00dev, 105, 0x05);
2558 rt2800_bbp_write(rt2x00dev, 106, 0x35); 2703
2704 if (rt2x00_rt(rt2x00dev, RT5390))
2705 rt2800_bbp_write(rt2x00dev, 106, 0x03);
2706 else
2707 rt2800_bbp_write(rt2x00dev, 106, 0x35);
2708
2709 if (rt2x00_rt(rt2x00dev, RT5390))
2710 rt2800_bbp_write(rt2x00dev, 128, 0x12);
2559 2711
2560 if (rt2x00_rt(rt2x00dev, RT3071) || 2712 if (rt2x00_rt(rt2x00dev, RT3071) ||
2561 rt2x00_rt(rt2x00dev, RT3090) || 2713 rt2x00_rt(rt2x00dev, RT3090) ||
2562 rt2x00_rt(rt2x00dev, RT3390)) { 2714 rt2x00_rt(rt2x00dev, RT3390) ||
2715 rt2x00_rt(rt2x00dev, RT5390)) {
2563 rt2800_bbp_read(rt2x00dev, 138, &value); 2716 rt2800_bbp_read(rt2x00dev, 138, &value);
2564 2717
2565 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom); 2718 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
@@ -2571,6 +2724,41 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
2571 rt2800_bbp_write(rt2x00dev, 138, value); 2724 rt2800_bbp_write(rt2x00dev, 138, value);
2572 } 2725 }
2573 2726
2727 if (rt2x00_rt(rt2x00dev, RT5390)) {
2728 int ant, div_mode;
2729
2730 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
2731 div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY);
2732 ant = (div_mode == 3) ? 1 : 0;
2733
2734 /* check if this is a Bluetooth combo card */
2735 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
2736 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST)) {
2737 u32 reg;
2738
2739 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
2740 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
2741 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT6, 0);
2742 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 0);
2743 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 0);
2744 if (ant == 0)
2745 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 1);
2746 else if (ant == 1)
2747 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 1);
2748 rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
2749 }
2750
2751 rt2800_bbp_read(rt2x00dev, 152, &value);
2752 if (ant == 0)
2753 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
2754 else
2755 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
2756 rt2800_bbp_write(rt2x00dev, 152, value);
2757
2758 /* Init frequency calibration */
2759 rt2800_bbp_write(rt2x00dev, 142, 1);
2760 rt2800_bbp_write(rt2x00dev, 143, 57);
2761 }
2574 2762
2575 for (i = 0; i < EEPROM_BBP_SIZE; i++) { 2763 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
2576 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom); 2764 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
@@ -2660,18 +2848,28 @@ static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
2660 !rt2x00_rt(rt2x00dev, RT3071) && 2848 !rt2x00_rt(rt2x00dev, RT3071) &&
2661 !rt2x00_rt(rt2x00dev, RT3090) && 2849 !rt2x00_rt(rt2x00dev, RT3090) &&
2662 !rt2x00_rt(rt2x00dev, RT3390) && 2850 !rt2x00_rt(rt2x00dev, RT3390) &&
2851 !rt2x00_rt(rt2x00dev, RT5390) &&
2663 !rt2800_is_305x_soc(rt2x00dev)) 2852 !rt2800_is_305x_soc(rt2x00dev))
2664 return 0; 2853 return 0;
2665 2854
2666 /* 2855 /*
2667 * Init RF calibration. 2856 * Init RF calibration.
2668 */ 2857 */
2669 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr); 2858 if (rt2x00_rt(rt2x00dev, RT5390)) {
2670 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1); 2859 rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
2671 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 2860 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
2672 msleep(1); 2861 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
2673 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0); 2862 msleep(1);
2674 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 2863 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0);
2864 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
2865 } else {
2866 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2867 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2868 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2869 msleep(1);
2870 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
2871 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2872 }
2675 2873
2676 if (rt2x00_rt(rt2x00dev, RT3070) || 2874 if (rt2x00_rt(rt2x00dev, RT3070) ||
2677 rt2x00_rt(rt2x00dev, RT3071) || 2875 rt2x00_rt(rt2x00dev, RT3071) ||
@@ -2762,6 +2960,87 @@ static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
2762 rt2800_rfcsr_write(rt2x00dev, 30, 0x00); 2960 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
2763 rt2800_rfcsr_write(rt2x00dev, 31, 0x00); 2961 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
2764 return 0; 2962 return 0;
2963 } else if (rt2x00_rt(rt2x00dev, RT5390)) {
2964 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
2965 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
2966 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
2967 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
2968 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
2969 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
2970 else
2971 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
2972 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
2973 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
2974 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
2975 rt2800_rfcsr_write(rt2x00dev, 12, 0xc6);
2976 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
2977 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
2978 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
2979 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
2980 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
2981 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
2982
2983 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
2984 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
2985 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
2986 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
2987 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
2988 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
2989 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
2990 else
2991 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
2992 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
2993 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
2994 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
2995 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
2996
2997 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
2998 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
2999 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
3000 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
3001 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
3002 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
3003 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
3004 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
3005 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
3006 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
3007
3008 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3009 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
3010 else
3011 rt2800_rfcsr_write(rt2x00dev, 40, 0x4b);
3012 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
3013 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
3014 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
3015 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
3016 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
3017 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3018 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
3019 else
3020 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
3021 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
3022 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
3023 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
3024
3025 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
3026 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3027 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
3028 else
3029 rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
3030 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
3031 rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
3032 rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
3033 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
3034 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
3035 rt2800_rfcsr_write(rt2x00dev, 59, 0x63);
3036
3037 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
3038 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3039 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
3040 else
3041 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
3042 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
3043 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
2765 } 3044 }
2766 3045
2767 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) { 3046 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
@@ -2815,21 +3094,23 @@ static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
2815 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15); 3094 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
2816 } 3095 }
2817 3096
2818 /* 3097 if (!rt2x00_rt(rt2x00dev, RT5390)) {
2819 * Set back to initial state 3098 /*
2820 */ 3099 * Set back to initial state
2821 rt2800_bbp_write(rt2x00dev, 24, 0); 3100 */
3101 rt2800_bbp_write(rt2x00dev, 24, 0);
2822 3102
2823 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr); 3103 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
2824 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0); 3104 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
2825 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); 3105 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
2826 3106
2827 /* 3107 /*
2828 * set BBP back to BW20 3108 * Set BBP back to BW20
2829 */ 3109 */
2830 rt2800_bbp_read(rt2x00dev, 4, &bbp); 3110 rt2800_bbp_read(rt2x00dev, 4, &bbp);
2831 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0); 3111 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
2832 rt2800_bbp_write(rt2x00dev, 4, bbp); 3112 rt2800_bbp_write(rt2x00dev, 4, bbp);
3113 }
2833 3114
2834 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) || 3115 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
2835 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 3116 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
@@ -2841,21 +3122,23 @@ static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
2841 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1); 3122 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
2842 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg); 3123 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
2843 3124
2844 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr); 3125 if (!rt2x00_rt(rt2x00dev, RT5390)) {
2845 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0); 3126 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
2846 if (rt2x00_rt(rt2x00dev, RT3070) || 3127 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
2847 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 3128 if (rt2x00_rt(rt2x00dev, RT3070) ||
2848 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) || 3129 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2849 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) { 3130 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2850 if (!test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) 3131 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
2851 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1); 3132 if (!test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
2852 } 3133 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
2853 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom); 3134 }
2854 if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1) 3135 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom);
2855 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN, 3136 if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1)
2856 rt2x00_get_field16(eeprom, 3137 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
2857 EEPROM_TXMIXER_GAIN_BG_VAL)); 3138 rt2x00_get_field16(eeprom,
2858 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr); 3139 EEPROM_TXMIXER_GAIN_BG_VAL));
3140 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
3141 }
2859 3142
2860 if (rt2x00_rt(rt2x00dev, RT3090)) { 3143 if (rt2x00_rt(rt2x00dev, RT3090)) {
2861 rt2800_bbp_read(rt2x00dev, 138, &bbp); 3144 rt2800_bbp_read(rt2x00dev, 138, &bbp);
@@ -2906,6 +3189,20 @@ static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
2906 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr); 3189 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
2907 } 3190 }
2908 3191
3192 if (rt2x00_rt(rt2x00dev, RT5390)) {
3193 rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
3194 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
3195 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
3196
3197 rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
3198 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
3199 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
3200
3201 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3202 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
3203 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3204 }
3205
2909 return 0; 3206 return 0;
2910} 3207}
2911 3208
@@ -3170,10 +3467,15 @@ int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
3170 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom); 3467 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3171 3468
3172 /* 3469 /*
3173 * Identify RF chipset. 3470 * Identify RF chipset by EEPROM value
3471 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
3472 * RT53xx: defined in "EEPROM_CHIP_ID" field
3174 */ 3473 */
3175 value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
3176 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg); 3474 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
3475 if (rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5390)
3476 rt2x00_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &value);
3477 else
3478 value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
3177 3479
3178 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET), 3480 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
3179 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION)); 3481 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
@@ -3185,7 +3487,8 @@ int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
3185 !rt2x00_rt(rt2x00dev, RT3071) && 3487 !rt2x00_rt(rt2x00dev, RT3071) &&
3186 !rt2x00_rt(rt2x00dev, RT3090) && 3488 !rt2x00_rt(rt2x00dev, RT3090) &&
3187 !rt2x00_rt(rt2x00dev, RT3390) && 3489 !rt2x00_rt(rt2x00dev, RT3390) &&
3188 !rt2x00_rt(rt2x00dev, RT3572)) { 3490 !rt2x00_rt(rt2x00dev, RT3572) &&
3491 !rt2x00_rt(rt2x00dev, RT5390)) {
3189 ERROR(rt2x00dev, "Invalid RT chipset detected.\n"); 3492 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
3190 return -ENODEV; 3493 return -ENODEV;
3191 } 3494 }
@@ -3199,7 +3502,8 @@ int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
3199 !rt2x00_rf(rt2x00dev, RF3021) && 3502 !rt2x00_rf(rt2x00dev, RF3021) &&
3200 !rt2x00_rf(rt2x00dev, RF3022) && 3503 !rt2x00_rf(rt2x00dev, RF3022) &&
3201 !rt2x00_rf(rt2x00dev, RF3052) && 3504 !rt2x00_rf(rt2x00dev, RF3052) &&
3202 !rt2x00_rf(rt2x00dev, RF3320)) { 3505 !rt2x00_rf(rt2x00dev, RF3320) &&
3506 !rt2x00_rf(rt2x00dev, RF5390)) {
3203 ERROR(rt2x00dev, "Invalid RF chipset detected.\n"); 3507 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
3204 return -ENODEV; 3508 return -ENODEV;
3205 } 3509 }
@@ -3496,7 +3800,8 @@ int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
3496 rt2x00_rf(rt2x00dev, RF2020) || 3800 rt2x00_rf(rt2x00dev, RF2020) ||
3497 rt2x00_rf(rt2x00dev, RF3021) || 3801 rt2x00_rf(rt2x00dev, RF3021) ||
3498 rt2x00_rf(rt2x00dev, RF3022) || 3802 rt2x00_rf(rt2x00dev, RF3022) ||
3499 rt2x00_rf(rt2x00dev, RF3320)) { 3803 rt2x00_rf(rt2x00dev, RF3320) ||
3804 rt2x00_rf(rt2x00dev, RF5390)) {
3500 spec->num_channels = 14; 3805 spec->num_channels = 14;
3501 spec->channels = rf_vals_3x; 3806 spec->channels = rf_vals_3x;
3502 } else if (rt2x00_rf(rt2x00dev, RF3052)) { 3807 } else if (rt2x00_rf(rt2x00dev, RF3052)) {
diff --git a/drivers/net/wireless/rt2x00/rt2800pci.c b/drivers/net/wireless/rt2x00/rt2800pci.c
index 6ac0ff23689..38605e9fe42 100644
--- a/drivers/net/wireless/rt2x00/rt2800pci.c
+++ b/drivers/net/wireless/rt2x00/rt2800pci.c
@@ -493,6 +493,13 @@ static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
493 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f); 493 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
494 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00); 494 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
495 495
496 if (rt2x00_rt(rt2x00dev, RT5390)) {
497 rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
498 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
499 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
500 rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
501 }
502
496 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003); 503 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
497 504
498 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg); 505 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
@@ -1127,6 +1134,9 @@ static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = {
1127 { PCI_DEVICE(0x1814, 0x3592), PCI_DEVICE_DATA(&rt2800pci_ops) }, 1134 { PCI_DEVICE(0x1814, 0x3592), PCI_DEVICE_DATA(&rt2800pci_ops) },
1128 { PCI_DEVICE(0x1814, 0x3593), PCI_DEVICE_DATA(&rt2800pci_ops) }, 1135 { PCI_DEVICE(0x1814, 0x3593), PCI_DEVICE_DATA(&rt2800pci_ops) },
1129#endif 1136#endif
1137#ifdef CONFIG_RT2800PCI_RT53XX
1138 { PCI_DEVICE(0x1814, 0x5390), PCI_DEVICE_DATA(&rt2800pci_ops) },
1139#endif
1130 { 0, } 1140 { 0, }
1131}; 1141};
1132#endif /* CONFIG_PCI */ 1142#endif /* CONFIG_PCI */
diff --git a/drivers/net/wireless/rt2x00/rt2x00.h b/drivers/net/wireless/rt2x00/rt2x00.h
index 64c6ef52fe5..1df432c1f2c 100644
--- a/drivers/net/wireless/rt2x00/rt2x00.h
+++ b/drivers/net/wireless/rt2x00/rt2x00.h
@@ -189,6 +189,7 @@ struct rt2x00_chip {
189#define RT3572 0x3572 189#define RT3572 0x3572
190#define RT3593 0x3593 /* PCIe */ 190#define RT3593 0x3593 /* PCIe */
191#define RT3883 0x3883 /* WSOC */ 191#define RT3883 0x3883 /* WSOC */
192#define RT5390 0x5390 /* 2.4GHz */
192 193
193 u16 rf; 194 u16 rf;
194 u16 rev; 195 u16 rev;
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-20 09:04:46 -0400