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-rw-r--r--drivers/media/video/gspca/tv8532.c136
1 files changed, 5 insertions, 131 deletions
diff --git a/drivers/media/video/gspca/tv8532.c b/drivers/media/video/gspca/tv8532.c
index c7b6eb1e04d..2316838ebc1 100644
--- a/drivers/media/video/gspca/tv8532.c
+++ b/drivers/media/video/gspca/tv8532.c
@@ -129,18 +129,6 @@ static const u8 eeprom_data[][3] = {
129 {0x05, 0x09, 0xf1}, 129 {0x05, 0x09, 0xf1},
130}; 130};
131 131
132static int reg_r(struct gspca_dev *gspca_dev,
133 __u16 index)
134{
135 usb_control_msg(gspca_dev->dev,
136 usb_rcvctrlpipe(gspca_dev->dev, 0),
137 0x03,
138 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
139 0, /* value */
140 index, gspca_dev->usb_buf, 1,
141 500);
142 return gspca_dev->usb_buf[0];
143}
144 132
145/* write 1 byte */ 133/* write 1 byte */
146static void reg_w1(struct gspca_dev *gspca_dev, 134static void reg_w1(struct gspca_dev *gspca_dev,
@@ -183,7 +171,6 @@ static void tv_8532WriteEEprom(struct gspca_dev *gspca_dev)
183 } 171 }
184 reg_w1(gspca_dev, R07_TABLE_LEN, i); 172 reg_w1(gspca_dev, R07_TABLE_LEN, i);
185 reg_w1(gspca_dev, R01_TIMING_CONTROL_LOW, CMD_EEprom_Close); 173 reg_w1(gspca_dev, R01_TIMING_CONTROL_LOW, CMD_EEprom_Close);
186 msleep(10);
187} 174}
188 175
189/* this function is called at probe time */ 176/* this function is called at probe time */
@@ -201,49 +188,8 @@ static int sd_config(struct gspca_dev *gspca_dev,
201 return 0; 188 return 0;
202} 189}
203 190
204static void tv_8532ReadRegisters(struct gspca_dev *gspca_dev)
205{
206 int i;
207 static u8 reg_tb[] = {
208 R0C_AD_WIDTHL,
209 R0D_AD_WIDTHH,
210 R28_QUANT,
211 R29_LINE,
212 R2C_POLARITY,
213 R2D_POINT,
214 R2E_POINTH,
215 R2F_POINTB,
216 R30_POINTBH,
217 R2A_HIGH_BUDGET,
218 R2B_LOW_BUDGET,
219 R34_VID,
220 R35_VIDH,
221 R36_PID,
222 R37_PIDH,
223 R83_AD_IDH,
224 R10_AD_COL_BEGINL,
225 R11_AD_COL_BEGINH,
226 R14_AD_ROW_BEGINL,
227 R15_AD_ROWBEGINH,
228 0
229 };
230
231 i = 0;
232 do {
233 reg_r(gspca_dev, reg_tb[i]);
234 i++;
235 } while (reg_tb[i] != 0);
236}
237
238static void tv_8532_setReg(struct gspca_dev *gspca_dev) 191static void tv_8532_setReg(struct gspca_dev *gspca_dev)
239{ 192{
240 reg_w1(gspca_dev, R10_AD_COL_BEGINL, 0x44);
241 /* begin active line */
242 reg_w1(gspca_dev, R11_AD_COL_BEGINH, 0x00);
243 /* mirror and digital gain */
244 reg_w1(gspca_dev, R00_PART_CONTROL, LATENT_CHANGE | EXPO_CHANGE);
245 /* = 0x84 */
246
247 reg_w1(gspca_dev, R3B_Test3, 0x0a); /* Test0Sel = 10 */ 193 reg_w1(gspca_dev, R3B_Test3, 0x0a); /* Test0Sel = 10 */
248 /******************************************************/ 194 /******************************************************/
249 reg_w1(gspca_dev, R0E_AD_HEIGHTL, 0x90); 195 reg_w1(gspca_dev, R0E_AD_HEIGHTL, 0x90);
@@ -255,75 +201,17 @@ static void tv_8532_setReg(struct gspca_dev *gspca_dev)
255 /* mirror and digital gain */ 201 /* mirror and digital gain */
256 reg_w1(gspca_dev, R14_AD_ROW_BEGINL, 0x0a); 202 reg_w1(gspca_dev, R14_AD_ROW_BEGINL, 0x0a);
257 203
258 reg_w1(gspca_dev, R91_AD_SLOPEREG, 0x00);
259 reg_w1(gspca_dev, R94_AD_BITCONTROL, 0x02); 204 reg_w1(gspca_dev, R94_AD_BITCONTROL, 0x02);
260
261 reg_w1(gspca_dev, R01_TIMING_CONTROL_LOW, CMD_EEprom_Close);
262
263 reg_w1(gspca_dev, R91_AD_SLOPEREG, 0x00); 205 reg_w1(gspca_dev, R91_AD_SLOPEREG, 0x00);
264 reg_w1(gspca_dev, R00_PART_CONTROL, LATENT_CHANGE | EXPO_CHANGE); 206 reg_w1(gspca_dev, R00_PART_CONTROL, LATENT_CHANGE | EXPO_CHANGE);
265 /* = 0x84 */ 207 /* = 0x84 */
266} 208}
267 209
268static void tv_8532_PollReg(struct gspca_dev *gspca_dev)
269{
270 int i;
271
272 /* strange polling from tgc */
273 for (i = 0; i < 10; i++) {
274 reg_w1(gspca_dev, R2C_POLARITY, 0x10);
275 reg_w1(gspca_dev, R00_PART_CONTROL,
276 LATENT_CHANGE | EXPO_CHANGE);
277 reg_w1(gspca_dev, R31_UPD, 0x01);
278 }
279}
280
281/* this function is called at probe and resume time */ 210/* this function is called at probe and resume time */
282static int sd_init(struct gspca_dev *gspca_dev) 211static int sd_init(struct gspca_dev *gspca_dev)
283{ 212{
284 tv_8532WriteEEprom(gspca_dev); 213 tv_8532WriteEEprom(gspca_dev);
285 214
286 reg_w1(gspca_dev, R91_AD_SLOPEREG, 0x32); /* slope begin 1,7V,
287 * slope rate 2 */
288 reg_w1(gspca_dev, R94_AD_BITCONTROL, 0x00);
289 tv_8532ReadRegisters(gspca_dev);
290 reg_w1(gspca_dev, R3B_Test3, 0x0b);
291 reg_w2(gspca_dev, R0E_AD_HEIGHTL, 0x0190);
292 reg_w2(gspca_dev, R1C_AD_EXPOSE_TIMEL, 0x018f);
293 reg_w1(gspca_dev, R0C_AD_WIDTHL, 0xe8);
294 reg_w1(gspca_dev, R0D_AD_WIDTHH, 0x03);
295
296 /*******************************************************************/
297 reg_w1(gspca_dev, R28_QUANT, 0x90);
298 /* no compress - fixed Q - quant 0 */
299 reg_w1(gspca_dev, R29_LINE, 0x81);
300 /* 0x84; // CIF | 4 packet 0x29 */
301
302 /************************************************/
303 reg_w1(gspca_dev, R2C_POLARITY, 0x10);
304 /* 0x48; //0x08; 0x2c */
305 reg_w1(gspca_dev, R2D_POINT, 0x14);
306 /* 0x38; 0x2d */
307 reg_w1(gspca_dev, R2E_POINTH, 0x01);
308 /* 0x04; 0x2e */
309 reg_w1(gspca_dev, R2F_POINTB, 0x12);
310 /* 0x04; 0x2f */
311 reg_w1(gspca_dev, R30_POINTBH, 0x01);
312 /* 0x04; 0x30 */
313 reg_w1(gspca_dev, R00_PART_CONTROL, LATENT_CHANGE | EXPO_CHANGE);
314 /* 0x00<-0x84 */
315 /*************************************************/
316 reg_w1(gspca_dev, R31_UPD, 0x01); /* update registers */
317 msleep(200);
318 reg_w1(gspca_dev, R31_UPD, 0x00); /* end update */
319 /*************************************************/
320 tv_8532_setReg(gspca_dev);
321 /*************************************************/
322 reg_w1(gspca_dev, R3B_Test3, 0x0b); /* Test0Sel = 11 = GPIO */
323 /*************************************************/
324 tv_8532_setReg(gspca_dev);
325 /*************************************************/
326 tv_8532_PollReg(gspca_dev);
327 return 0; 215 return 0;
328} 216}
329 217
@@ -341,15 +229,6 @@ static int sd_start(struct gspca_dev *gspca_dev)
341{ 229{
342 struct sd *sd = (struct sd *) gspca_dev; 230 struct sd *sd = (struct sd *) gspca_dev;
343 231
344 reg_w1(gspca_dev, R91_AD_SLOPEREG, 0x32); /* slope begin 1,7V,
345 * slope rate 2 */
346 reg_w1(gspca_dev, R94_AD_BITCONTROL, 0x00);
347 tv_8532ReadRegisters(gspca_dev);
348 reg_w1(gspca_dev, R3B_Test3, 0x0b);
349
350 reg_w2(gspca_dev, R0E_AD_HEIGHTL, 0x0190);
351 setbrightness(gspca_dev);
352
353 reg_w1(gspca_dev, R0C_AD_WIDTHL, 0xe8); /* 0x20; 0x0c */ 232 reg_w1(gspca_dev, R0C_AD_WIDTHL, 0xe8); /* 0x20; 0x0c */
354 reg_w1(gspca_dev, R0D_AD_WIDTHH, 0x03); 233 reg_w1(gspca_dev, R0D_AD_WIDTHH, 0x03);
355 234
@@ -371,19 +250,14 @@ static int sd_start(struct gspca_dev *gspca_dev)
371 reg_w1(gspca_dev, R2E_POINTH, 0x01); 250 reg_w1(gspca_dev, R2E_POINTH, 0x01);
372 reg_w1(gspca_dev, R2F_POINTB, 0x12); 251 reg_w1(gspca_dev, R2F_POINTB, 0x12);
373 reg_w1(gspca_dev, R30_POINTBH, 0x01); 252 reg_w1(gspca_dev, R30_POINTBH, 0x01);
374 reg_w1(gspca_dev, R00_PART_CONTROL, LATENT_CHANGE | EXPO_CHANGE); 253
254 tv_8532_setReg(gspca_dev);
255
256 setbrightness(gspca_dev);
257
375 /************************************************/ 258 /************************************************/
376 reg_w1(gspca_dev, R31_UPD, 0x01); /* update registers */ 259 reg_w1(gspca_dev, R31_UPD, 0x01); /* update registers */
377 msleep(200); 260 msleep(200);
378 reg_w1(gspca_dev, R31_UPD, 0x00); /* end update */
379 /************************************************/
380 tv_8532_setReg(gspca_dev);
381 /************************************************/
382 reg_w1(gspca_dev, R3B_Test3, 0x0b); /* Test0Sel = 11 = GPIO */
383 /************************************************/
384 tv_8532_setReg(gspca_dev);
385 /************************************************/
386 tv_8532_PollReg(gspca_dev);
387 reg_w1(gspca_dev, R31_UPD, 0x00); /* end update */ 261 reg_w1(gspca_dev, R31_UPD, 0x00); /* end update */
388 262
389 gspca_dev->empty_packet = 0; /* check the empty packets */ 263 gspca_dev->empty_packet = 0; /* check the empty packets */