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-rw-r--r--arch/mips/include/asm/netlogic/interrupt.h45
-rw-r--r--arch/mips/include/asm/netlogic/mips-extns.h76
-rw-r--r--arch/mips/include/asm/netlogic/psb-bootinfo.h109
-rw-r--r--arch/mips/include/asm/netlogic/xlr/gpio.h73
-rw-r--r--arch/mips/include/asm/netlogic/xlr/iomap.h131
-rw-r--r--arch/mips/include/asm/netlogic/xlr/pic.h231
-rw-r--r--arch/mips/include/asm/netlogic/xlr/xlr.h54
-rw-r--r--arch/mips/netlogic/xlr/irq.c216
-rw-r--r--arch/mips/netlogic/xlr/platform.c98
-rw-r--r--arch/mips/netlogic/xlr/setup.c188
-rw-r--r--arch/mips/netlogic/xlr/smp.c225
-rw-r--r--arch/mips/netlogic/xlr/smpboot.S94
-rw-r--r--arch/mips/netlogic/xlr/time.c51
-rw-r--r--arch/mips/netlogic/xlr/xlr_console.c46
14 files changed, 1637 insertions, 0 deletions
diff --git a/arch/mips/include/asm/netlogic/interrupt.h b/arch/mips/include/asm/netlogic/interrupt.h
new file mode 100644
index 00000000000..a85aadb6cfd
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/interrupt.h
@@ -0,0 +1,45 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef _ASM_NLM_INTERRUPT_H
36#define _ASM_NLM_INTERRUPT_H
37
38/* Defines for the IRQ numbers */
39
40#define IRQ_IPI_SMP_FUNCTION 3
41#define IRQ_IPI_SMP_RESCHEDULE 4
42#define IRQ_MSGRING 6
43#define IRQ_TIMER 7
44
45#endif
diff --git a/arch/mips/include/asm/netlogic/mips-extns.h b/arch/mips/include/asm/netlogic/mips-extns.h
new file mode 100644
index 00000000000..8c53d0ba4bf
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/mips-extns.h
@@ -0,0 +1,76 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef _ASM_NLM_MIPS_EXTS_H
36#define _ASM_NLM_MIPS_EXTS_H
37
38/*
39 * XLR and XLP interrupt request and interrupt mask registers
40 */
41#define read_c0_eirr() __read_64bit_c0_register($9, 6)
42#define read_c0_eimr() __read_64bit_c0_register($9, 7)
43#define write_c0_eirr(val) __write_64bit_c0_register($9, 6, val)
44
45/*
46 * Writing EIMR in 32 bit is a special case, the lower 8 bit of the
47 * EIMR is shadowed in the status register, so we cannot save and
48 * restore status register for split read.
49 */
50#define write_c0_eimr(val) \
51do { \
52 if (sizeof(unsigned long) == 4) { \
53 unsigned long __flags; \
54 \
55 local_irq_save(__flags); \
56 __asm__ __volatile__( \
57 ".set\tmips64\n\t" \
58 "dsll\t%L0, %L0, 32\n\t" \
59 "dsrl\t%L0, %L0, 32\n\t" \
60 "dsll\t%M0, %M0, 32\n\t" \
61 "or\t%L0, %L0, %M0\n\t" \
62 "dmtc0\t%L0, $9, 7\n\t" \
63 ".set\tmips0" \
64 : : "r" (val)); \
65 __flags = (__flags & 0xffff00ff) | (((val) & 0xff) << 8);\
66 local_irq_restore(__flags); \
67 } else \
68 __write_64bit_c0_register($9, 7, (val)); \
69} while (0)
70
71static inline int hard_smp_processor_id(void)
72{
73 return __read_32bit_c0_register($15, 1) & 0x3ff;
74}
75
76#endif /*_ASM_NLM_MIPS_EXTS_H */
diff --git a/arch/mips/include/asm/netlogic/psb-bootinfo.h b/arch/mips/include/asm/netlogic/psb-bootinfo.h
new file mode 100644
index 00000000000..6878307f0ee
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/psb-bootinfo.h
@@ -0,0 +1,109 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef _ASM_NETLOGIC_BOOTINFO_H
36#define _ASM_NETLOGIC_BOOTINFO_H
37
38struct psb_info {
39 uint64_t boot_level;
40 uint64_t io_base;
41 uint64_t output_device;
42 uint64_t uart_print;
43 uint64_t led_output;
44 uint64_t init;
45 uint64_t exit;
46 uint64_t warm_reset;
47 uint64_t wakeup;
48 uint64_t online_cpu_map;
49 uint64_t master_reentry_sp;
50 uint64_t master_reentry_gp;
51 uint64_t master_reentry_fn;
52 uint64_t slave_reentry_fn;
53 uint64_t magic_dword;
54 uint64_t uart_putchar;
55 uint64_t size;
56 uint64_t uart_getchar;
57 uint64_t nmi_handler;
58 uint64_t psb_version;
59 uint64_t mac_addr;
60 uint64_t cpu_frequency;
61 uint64_t board_version;
62 uint64_t malloc;
63 uint64_t free;
64 uint64_t global_shmem_addr;
65 uint64_t global_shmem_size;
66 uint64_t psb_os_cpu_map;
67 uint64_t userapp_cpu_map;
68 uint64_t wakeup_os;
69 uint64_t psb_mem_map;
70 uint64_t board_major_version;
71 uint64_t board_minor_version;
72 uint64_t board_manf_revision;
73 uint64_t board_serial_number;
74 uint64_t psb_physaddr_map;
75 uint64_t xlr_loaderip_config;
76 uint64_t bldr_envp;
77 uint64_t avail_mem_map;
78};
79
80enum {
81 NETLOGIC_IO_SPACE = 0x10,
82 PCIX_IO_SPACE,
83 PCIX_CFG_SPACE,
84 PCIX_MEMORY_SPACE,
85 HT_IO_SPACE,
86 HT_CFG_SPACE,
87 HT_MEMORY_SPACE,
88 SRAM_SPACE,
89 FLASH_CONTROLLER_SPACE
90};
91
92#define NLM_MAX_ARGS 64
93#define NLM_MAX_ENVS 32
94
95/* This is what netlboot passes and linux boot_mem_map is subtly different */
96#define NLM_BOOT_MEM_MAP_MAX 32
97struct nlm_boot_mem_map {
98 int nr_map;
99 struct nlm_boot_mem_map_entry {
100 uint64_t addr; /* start of memory segment */
101 uint64_t size; /* size of memory segment */
102 uint32_t type; /* type of memory segment */
103 } map[NLM_BOOT_MEM_MAP_MAX];
104};
105
106/* Pointer to saved boot loader info */
107extern struct psb_info nlm_prom_info;
108
109#endif
diff --git a/arch/mips/include/asm/netlogic/xlr/gpio.h b/arch/mips/include/asm/netlogic/xlr/gpio.h
new file mode 100644
index 00000000000..51f6ad4aeb1
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlr/gpio.h
@@ -0,0 +1,73 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef _ASM_NLM_GPIO_H
36#define _ASM_NLM_GPIO_H
37
38#define NETLOGIC_GPIO_INT_EN_REG 0
39#define NETLOGIC_GPIO_INPUT_INVERSION_REG 1
40#define NETLOGIC_GPIO_IO_DIR_REG 2
41#define NETLOGIC_GPIO_IO_DATA_WR_REG 3
42#define NETLOGIC_GPIO_IO_DATA_RD_REG 4
43
44#define NETLOGIC_GPIO_SWRESET_REG 8
45#define NETLOGIC_GPIO_DRAM1_CNTRL_REG 9
46#define NETLOGIC_GPIO_DRAM1_RATIO_REG 10
47#define NETLOGIC_GPIO_DRAM1_RESET_REG 11
48#define NETLOGIC_GPIO_DRAM1_STATUS_REG 12
49#define NETLOGIC_GPIO_DRAM2_CNTRL_REG 13
50#define NETLOGIC_GPIO_DRAM2_RATIO_REG 14
51#define NETLOGIC_GPIO_DRAM2_RESET_REG 15
52#define NETLOGIC_GPIO_DRAM2_STATUS_REG 16
53
54#define NETLOGIC_GPIO_PWRON_RESET_CFG_REG 21
55#define NETLOGIC_GPIO_BIST_ALL_GO_STATUS_REG 24
56#define NETLOGIC_GPIO_BIST_CPU_GO_STATUS_REG 25
57#define NETLOGIC_GPIO_BIST_DEV_GO_STATUS_REG 26
58
59#define NETLOGIC_GPIO_FUSE_BANK_REG 35
60#define NETLOGIC_GPIO_CPU_RESET_REG 40
61#define NETLOGIC_GPIO_RNG_REG 43
62
63#define NETLOGIC_PWRON_RESET_PCMCIA_BOOT 17
64#define NETLOGIC_GPIO_LED_BITMAP 0x1700000
65#define NETLOGIC_GPIO_LED_0_SHIFT 20
66#define NETLOGIC_GPIO_LED_1_SHIFT 24
67
68#define NETLOGIC_GPIO_LED_OUTPUT_CODE_RESET 0x01
69#define NETLOGIC_GPIO_LED_OUTPUT_CODE_HARD_RESET 0x02
70#define NETLOGIC_GPIO_LED_OUTPUT_CODE_SOFT_RESET 0x03
71#define NETLOGIC_GPIO_LED_OUTPUT_CODE_MAIN 0x04
72
73#endif
diff --git a/arch/mips/include/asm/netlogic/xlr/iomap.h b/arch/mips/include/asm/netlogic/xlr/iomap.h
new file mode 100644
index 00000000000..2e3a4dd5304
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlr/iomap.h
@@ -0,0 +1,131 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef _ASM_NLM_IOMAP_H
36#define _ASM_NLM_IOMAP_H
37
38#define DEFAULT_NETLOGIC_IO_BASE CKSEG1ADDR(0x1ef00000)
39#define NETLOGIC_IO_DDR2_CHN0_OFFSET 0x01000
40#define NETLOGIC_IO_DDR2_CHN1_OFFSET 0x02000
41#define NETLOGIC_IO_DDR2_CHN2_OFFSET 0x03000
42#define NETLOGIC_IO_DDR2_CHN3_OFFSET 0x04000
43#define NETLOGIC_IO_PIC_OFFSET 0x08000
44#define NETLOGIC_IO_UART_0_OFFSET 0x14000
45#define NETLOGIC_IO_UART_1_OFFSET 0x15100
46
47#define NETLOGIC_IO_SIZE 0x1000
48
49#define NETLOGIC_IO_BRIDGE_OFFSET 0x00000
50
51#define NETLOGIC_IO_RLD2_CHN0_OFFSET 0x05000
52#define NETLOGIC_IO_RLD2_CHN1_OFFSET 0x06000
53
54#define NETLOGIC_IO_SRAM_OFFSET 0x07000
55
56#define NETLOGIC_IO_PCIX_OFFSET 0x09000
57#define NETLOGIC_IO_HT_OFFSET 0x0A000
58
59#define NETLOGIC_IO_SECURITY_OFFSET 0x0B000
60
61#define NETLOGIC_IO_GMAC_0_OFFSET 0x0C000
62#define NETLOGIC_IO_GMAC_1_OFFSET 0x0D000
63#define NETLOGIC_IO_GMAC_2_OFFSET 0x0E000
64#define NETLOGIC_IO_GMAC_3_OFFSET 0x0F000
65
66/* XLS devices */
67#define NETLOGIC_IO_GMAC_4_OFFSET 0x20000
68#define NETLOGIC_IO_GMAC_5_OFFSET 0x21000
69#define NETLOGIC_IO_GMAC_6_OFFSET 0x22000
70#define NETLOGIC_IO_GMAC_7_OFFSET 0x23000
71
72#define NETLOGIC_IO_PCIE_0_OFFSET 0x1E000
73#define NETLOGIC_IO_PCIE_1_OFFSET 0x1F000
74#define NETLOGIC_IO_SRIO_0_OFFSET 0x1E000
75#define NETLOGIC_IO_SRIO_1_OFFSET 0x1F000
76
77#define NETLOGIC_IO_USB_0_OFFSET 0x24000
78#define NETLOGIC_IO_USB_1_OFFSET 0x25000
79
80#define NETLOGIC_IO_COMP_OFFSET 0x1D000
81/* end XLS devices */
82
83/* XLR devices */
84#define NETLOGIC_IO_SPI4_0_OFFSET 0x10000
85#define NETLOGIC_IO_XGMAC_0_OFFSET 0x11000
86#define NETLOGIC_IO_SPI4_1_OFFSET 0x12000
87#define NETLOGIC_IO_XGMAC_1_OFFSET 0x13000
88/* end XLR devices */
89
90#define NETLOGIC_IO_I2C_0_OFFSET 0x16000
91#define NETLOGIC_IO_I2C_1_OFFSET 0x17000
92
93#define NETLOGIC_IO_GPIO_OFFSET 0x18000
94#define NETLOGIC_IO_FLASH_OFFSET 0x19000
95#define NETLOGIC_IO_TB_OFFSET 0x1C000
96
97#define NETLOGIC_CPLD_OFFSET KSEG1ADDR(0x1d840000)
98
99/*
100 * Base Address (Virtual) of the PCI Config address space
101 * For now, choose 256M phys in kseg1 = 0xA0000000 + (1<<28)
102 * Config space spans 256 (num of buses) * 256 (num functions) * 256 bytes
103 * ie 1<<24 = 16M
104 */
105#define DEFAULT_PCI_CONFIG_BASE 0x18000000
106#define DEFAULT_HT_TYPE0_CFG_BASE 0x16000000
107#define DEFAULT_HT_TYPE1_CFG_BASE 0x17000000
108
109#ifndef __ASSEMBLY__
110#include <linux/types.h>
111#include <asm/byteorder.h>
112
113typedef volatile __u32 nlm_reg_t;
114extern unsigned long netlogic_io_base;
115
116/* FIXME read once in write_reg */
117#ifdef CONFIG_CPU_LITTLE_ENDIAN
118#define netlogic_read_reg(base, offset) ((base)[(offset)])
119#define netlogic_write_reg(base, offset, value) ((base)[(offset)] = (value))
120#else
121#define netlogic_read_reg(base, offset) (be32_to_cpu((base)[(offset)]))
122#define netlogic_write_reg(base, offset, value) \
123 ((base)[(offset)] = cpu_to_be32((value)))
124#endif
125
126#define netlogic_read_reg_le32(base, offset) (le32_to_cpu((base)[(offset)]))
127#define netlogic_write_reg_le32(base, offset, value) \
128 ((base)[(offset)] = cpu_to_le32((value)))
129#define netlogic_io_mmio(offset) ((nlm_reg_t *)(netlogic_io_base+(offset)))
130#endif /* __ASSEMBLY__ */
131#endif
diff --git a/arch/mips/include/asm/netlogic/xlr/pic.h b/arch/mips/include/asm/netlogic/xlr/pic.h
new file mode 100644
index 00000000000..5cceb746f08
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlr/pic.h
@@ -0,0 +1,231 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef _ASM_NLM_XLR_PIC_H
36#define _ASM_NLM_XLR_PIC_H
37
38#define PIC_CLKS_PER_SEC 66666666ULL
39/* PIC hardware interrupt numbers */
40#define PIC_IRT_WD_INDEX 0
41#define PIC_IRT_TIMER_0_INDEX 1
42#define PIC_IRT_TIMER_1_INDEX 2
43#define PIC_IRT_TIMER_2_INDEX 3
44#define PIC_IRT_TIMER_3_INDEX 4
45#define PIC_IRT_TIMER_4_INDEX 5
46#define PIC_IRT_TIMER_5_INDEX 6
47#define PIC_IRT_TIMER_6_INDEX 7
48#define PIC_IRT_TIMER_7_INDEX 8
49#define PIC_IRT_CLOCK_INDEX PIC_IRT_TIMER_7_INDEX
50#define PIC_IRT_UART_0_INDEX 9
51#define PIC_IRT_UART_1_INDEX 10
52#define PIC_IRT_I2C_0_INDEX 11
53#define PIC_IRT_I2C_1_INDEX 12
54#define PIC_IRT_PCMCIA_INDEX 13
55#define PIC_IRT_GPIO_INDEX 14
56#define PIC_IRT_HYPER_INDEX 15
57#define PIC_IRT_PCIX_INDEX 16
58/* XLS */
59#define PIC_IRT_CDE_INDEX 15
60#define PIC_IRT_BRIDGE_TB_XLS_INDEX 16
61/* XLS */
62#define PIC_IRT_GMAC0_INDEX 17
63#define PIC_IRT_GMAC1_INDEX 18
64#define PIC_IRT_GMAC2_INDEX 19
65#define PIC_IRT_GMAC3_INDEX 20
66#define PIC_IRT_XGS0_INDEX 21
67#define PIC_IRT_XGS1_INDEX 22
68#define PIC_IRT_HYPER_FATAL_INDEX 23
69#define PIC_IRT_PCIX_FATAL_INDEX 24
70#define PIC_IRT_BRIDGE_AERR_INDEX 25
71#define PIC_IRT_BRIDGE_BERR_INDEX 26
72#define PIC_IRT_BRIDGE_TB_XLR_INDEX 27
73#define PIC_IRT_BRIDGE_AERR_NMI_INDEX 28
74/* XLS */
75#define PIC_IRT_GMAC4_INDEX 21
76#define PIC_IRT_GMAC5_INDEX 22
77#define PIC_IRT_GMAC6_INDEX 23
78#define PIC_IRT_GMAC7_INDEX 24
79#define PIC_IRT_BRIDGE_ERR_INDEX 25
80#define PIC_IRT_PCIE_LINK0_INDEX 26
81#define PIC_IRT_PCIE_LINK1_INDEX 27
82#define PIC_IRT_PCIE_LINK2_INDEX 23
83#define PIC_IRT_PCIE_LINK3_INDEX 24
84#define PIC_IRT_PCIE_XLSB0_LINK2_INDEX 28
85#define PIC_IRT_PCIE_XLSB0_LINK3_INDEX 29
86#define PIC_IRT_SRIO_LINK0_INDEX 26
87#define PIC_IRT_SRIO_LINK1_INDEX 27
88#define PIC_IRT_SRIO_LINK2_INDEX 28
89#define PIC_IRT_SRIO_LINK3_INDEX 29
90#define PIC_IRT_PCIE_INT_INDEX 28
91#define PIC_IRT_PCIE_FATAL_INDEX 29
92#define PIC_IRT_GPIO_B_INDEX 30
93#define PIC_IRT_USB_INDEX 31
94/* XLS */
95#define PIC_NUM_IRTS 32
96
97
98#define PIC_CLOCK_TIMER 7
99
100/* PIC Registers */
101#define PIC_CTRL 0x00
102#define PIC_IPI 0x04
103#define PIC_INT_ACK 0x06
104
105#define WD_MAX_VAL_0 0x08
106#define WD_MAX_VAL_1 0x09
107#define WD_MASK_0 0x0a
108#define WD_MASK_1 0x0b
109#define WD_HEARBEAT_0 0x0c
110#define WD_HEARBEAT_1 0x0d
111
112#define PIC_IRT_0_BASE 0x40
113#define PIC_IRT_1_BASE 0x80
114#define PIC_TIMER_MAXVAL_0_BASE 0x100
115#define PIC_TIMER_MAXVAL_1_BASE 0x110
116#define PIC_TIMER_COUNT_0_BASE 0x120
117#define PIC_TIMER_COUNT_1_BASE 0x130
118
119#define PIC_IRT_0(picintr) (PIC_IRT_0_BASE + (picintr))
120#define PIC_IRT_1(picintr) (PIC_IRT_1_BASE + (picintr))
121
122#define PIC_TIMER_MAXVAL_0(i) (PIC_TIMER_MAXVAL_0_BASE + (i))
123#define PIC_TIMER_MAXVAL_1(i) (PIC_TIMER_MAXVAL_1_BASE + (i))
124#define PIC_TIMER_COUNT_0(i) (PIC_TIMER_COUNT_0_BASE + (i))
125#define PIC_TIMER_COUNT_1(i) (PIC_TIMER_COUNT_0_BASE + (i))
126
127/*
128 * Mapping between hardware interrupt numbers and IRQs on CPU
129 * we use a simple scheme to map PIC interrupts 0-31 to IRQs
130 * 8-39. This leaves the IRQ 0-7 for cpu interrupts like
131 * count/compare and FMN
132 */
133#define PIC_IRQ_BASE 8
134#define PIC_INTR_TO_IRQ(i) (PIC_IRQ_BASE + (i))
135#define PIC_IRQ_TO_INTR(i) ((i) - PIC_IRQ_BASE)
136
137#define PIC_IRT_FIRST_IRQ PIC_IRQ_BASE
138#define PIC_WD_IRQ PIC_INTR_TO_IRQ(PIC_IRT_WD_INDEX)
139#define PIC_TIMER_0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_0_INDEX)
140#define PIC_TIMER_1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_1_INDEX)
141#define PIC_TIMER_2_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_2_INDEX)
142#define PIC_TIMER_3_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_3_INDEX)
143#define PIC_TIMER_4_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_4_INDEX)
144#define PIC_TIMER_5_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_5_INDEX)
145#define PIC_TIMER_6_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_6_INDEX)
146#define PIC_TIMER_7_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_7_INDEX)
147#define PIC_CLOCK_IRQ (PIC_TIMER_7_IRQ)
148#define PIC_UART_0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_UART_0_INDEX)
149#define PIC_UART_1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_UART_1_INDEX)
150#define PIC_I2C_0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_I2C_0_INDEX)
151#define PIC_I2C_1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_I2C_1_INDEX)
152#define PIC_PCMCIA_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCMCIA_INDEX)
153#define PIC_GPIO_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GPIO_INDEX)
154#define PIC_HYPER_IRQ PIC_INTR_TO_IRQ(PIC_IRT_HYPER_INDEX)
155#define PIC_PCIX_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIX_INDEX)
156/* XLS */
157#define PIC_CDE_IRQ PIC_INTR_TO_IRQ(PIC_IRT_CDE_INDEX)
158#define PIC_BRIDGE_TB_XLS_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_TB_XLS_INDEX)
159/* end XLS */
160#define PIC_GMAC_0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC0_INDEX)
161#define PIC_GMAC_1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC1_INDEX)
162#define PIC_GMAC_2_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC2_INDEX)
163#define PIC_GMAC_3_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC3_INDEX)
164#define PIC_XGS_0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_XGS0_INDEX)
165#define PIC_XGS_1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_XGS1_INDEX)
166#define PIC_HYPER_FATAL_IRQ PIC_INTR_TO_IRQ(PIC_IRT_HYPER_FATAL_INDEX)
167#define PIC_PCIX_FATAL_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIX_FATAL_INDEX)
168#define PIC_BRIDGE_AERR_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_AERR_INDEX)
169#define PIC_BRIDGE_BERR_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_BERR_INDEX)
170#define PIC_BRIDGE_TB_XLR_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_TB_XLR_INDEX)
171#define PIC_BRIDGE_AERR_NMI_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_AERR_NMI_INDEX)
172/* XLS defines */
173#define PIC_GMAC_4_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC4_INDEX)
174#define PIC_GMAC_5_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC5_INDEX)
175#define PIC_GMAC_6_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC6_INDEX)
176#define PIC_GMAC_7_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC7_INDEX)
177#define PIC_BRIDGE_ERR_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_ERR_INDEX)
178#define PIC_PCIE_LINK0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_LINK0_INDEX)
179#define PIC_PCIE_LINK1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_LINK1_INDEX)
180#define PIC_PCIE_LINK2_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_LINK2_INDEX)
181#define PIC_PCIE_LINK3_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_LINK3_INDEX)
182#define PIC_PCIE_XLSB0_LINK2_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_XLSB0_LINK2_INDEX)
183#define PIC_PCIE_XLSB0_LINK3_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_XLSB0_LINK3_INDEX)
184#define PIC_SRIO_LINK0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_SRIO_LINK0_INDEX)
185#define PIC_SRIO_LINK1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_SRIO_LINK1_INDEX)
186#define PIC_SRIO_LINK2_IRQ PIC_INTR_TO_IRQ(PIC_IRT_SRIO_LINK2_INDEX)
187#define PIC_SRIO_LINK3_IRQ PIC_INTR_TO_IRQ(PIC_IRT_SRIO_LINK3_INDEX)
188#define PIC_PCIE_INT_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_INT__INDEX)
189#define PIC_PCIE_FATAL_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_FATAL_INDEX)
190#define PIC_GPIO_B_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GPIO_B_INDEX)
191#define PIC_USB_IRQ PIC_INTR_TO_IRQ(PIC_IRT_USB_INDEX)
192#define PIC_IRT_LAST_IRQ PIC_USB_IRQ
193/* end XLS */
194
195#ifndef __ASSEMBLY__
196static inline void pic_send_ipi(u32 ipi)
197{
198 nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
199
200 netlogic_write_reg(mmio, PIC_IPI, ipi);
201}
202
203static inline u32 pic_read_control(void)
204{
205 nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
206
207 return netlogic_read_reg(mmio, PIC_CTRL);
208}
209
210static inline void pic_write_control(u32 control)
211{
212 nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
213
214 netlogic_write_reg(mmio, PIC_CTRL, control);
215}
216
217static inline void pic_update_control(u32 control)
218{
219 nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
220
221 netlogic_write_reg(mmio, PIC_CTRL,
222 (control | netlogic_read_reg(mmio, PIC_CTRL)));
223}
224
225#define PIC_IRQ_IS_EDGE_TRIGGERED(irq) (((irq) >= PIC_TIMER_0_IRQ) && \
226 ((irq) <= PIC_TIMER_7_IRQ))
227#define PIC_IRQ_IS_IRT(irq) (((irq) >= PIC_IRT_FIRST_IRQ) && \
228 ((irq) <= PIC_IRT_LAST_IRQ))
229#endif
230
231#endif /* _ASM_NLM_XLR_PIC_H */
diff --git a/arch/mips/include/asm/netlogic/xlr/xlr.h b/arch/mips/include/asm/netlogic/xlr/xlr.h
new file mode 100644
index 00000000000..454c236d685
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlr/xlr.h
@@ -0,0 +1,54 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef _ASM_NLM_XLR_H
36#define _ASM_NLM_XLR_H
37
38/* Platform UART functions */
39struct uart_port;
40unsigned int nlm_xlr_uart_in(struct uart_port *, int);
41void nlm_xlr_uart_out(struct uart_port *, int, int);
42
43/* SMP support functions */
44void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc);
45void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc);
46int nlm_wakeup_secondary_cpus(u32 wakeup_mask);
47void nlm_smp_irq_init(void);
48void nlm_boot_smp_nmi(void);
49void prom_pre_boot_secondary_cpus(void);
50
51extern struct plat_smp_ops nlm_smp_ops;
52extern unsigned long nlm_common_ebase;
53
54#endif /* _ASM_NLM_XLR_H */
diff --git a/arch/mips/netlogic/xlr/irq.c b/arch/mips/netlogic/xlr/irq.c
new file mode 100644
index 00000000000..2033f5656f6
--- /dev/null
+++ b/arch/mips/netlogic/xlr/irq.c
@@ -0,0 +1,216 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <linux/kernel.h>
36#include <linux/init.h>
37#include <linux/linkage.h>
38#include <linux/interrupt.h>
39#include <linux/spinlock.h>
40#include <linux/mm.h>
41
42#include <asm/mipsregs.h>
43
44#include <asm/netlogic/xlr/iomap.h>
45#include <asm/netlogic/xlr/pic.h>
46#include <asm/netlogic/xlr/xlr.h>
47
48#include <asm/netlogic/interrupt.h>
49#include <asm/netlogic/mips-extns.h>
50
51static u64 nlm_irq_mask;
52static DEFINE_SPINLOCK(nlm_pic_lock);
53
54static void xlr_pic_enable(struct irq_data *d)
55{
56 nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
57 unsigned long flags;
58 nlm_reg_t reg;
59 int irq = d->irq;
60
61 WARN(!PIC_IRQ_IS_IRT(irq), "Bad irq %d", irq);
62
63 spin_lock_irqsave(&nlm_pic_lock, flags);
64 reg = netlogic_read_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE);
65 netlogic_write_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE,
66 reg | (1 << 6) | (1 << 30) | (1 << 31));
67 spin_unlock_irqrestore(&nlm_pic_lock, flags);
68}
69
70static void xlr_pic_mask(struct irq_data *d)
71{
72 nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
73 unsigned long flags;
74 nlm_reg_t reg;
75 int irq = d->irq;
76
77 WARN(!PIC_IRQ_IS_IRT(irq), "Bad irq %d", irq);
78
79 spin_lock_irqsave(&nlm_pic_lock, flags);
80 reg = netlogic_read_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE);
81 netlogic_write_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE,
82 reg | (1 << 6) | (1 << 30) | (0 << 31));
83 spin_unlock_irqrestore(&nlm_pic_lock, flags);
84}
85
86static void xlr_pic_ack(struct irq_data *d)
87{
88 unsigned long flags;
89 nlm_reg_t *mmio;
90 int irq = d->irq;
91
92 WARN(!PIC_IRQ_IS_IRT(irq), "Bad irq %d", irq);
93
94 mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
95 spin_lock_irqsave(&nlm_pic_lock, flags);
96 netlogic_write_reg(mmio, PIC_INT_ACK, (1 << (irq - PIC_IRQ_BASE)));
97 spin_unlock_irqrestore(&nlm_pic_lock, flags);
98}
99
100/*
101 * This chip definition handles interrupts routed thru the XLR
102 * hardware PIC, currently IRQs 8-39 are mapped to hardware intr
103 * 0-31 wired the XLR PIC
104 */
105static struct irq_chip xlr_pic = {
106 .name = "XLR-PIC",
107 .irq_enable = xlr_pic_enable,
108 .irq_mask = xlr_pic_mask,
109 .irq_ack = xlr_pic_ack,
110};
111
112static void rsvd_irq_handler(struct irq_data *d)
113{
114 WARN(d->irq >= PIC_IRQ_BASE, "Bad irq %d", d->irq);
115}
116
117/*
118 * Chip definition for CPU originated interrupts(timer, msg) and
119 * IPIs
120 */
121struct irq_chip nlm_cpu_intr = {
122 .name = "XLR-CPU-INTR",
123 .irq_enable = rsvd_irq_handler,
124 .irq_mask = rsvd_irq_handler,
125 .irq_ack = rsvd_irq_handler,
126};
127
128void __init init_xlr_irqs(void)
129{
130 nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
131 uint32_t thread_mask = 1;
132 int level, i;
133
134 pr_info("Interrupt thread mask [%x]\n", thread_mask);
135 for (i = 0; i < PIC_NUM_IRTS; i++) {
136 level = PIC_IRQ_IS_EDGE_TRIGGERED(i);
137
138 /* Bind all PIC irqs to boot cpu */
139 netlogic_write_reg(mmio, PIC_IRT_0_BASE + i, thread_mask);
140
141 /*
142 * Use local scheduling and high polarity for all IRTs
143 * Invalidate all IRTs, by default
144 */
145 netlogic_write_reg(mmio, PIC_IRT_1_BASE + i,
146 (level << 30) | (1 << 6) | (PIC_IRQ_BASE + i));
147 }
148
149 /* Make all IRQs as level triggered by default */
150 for (i = 0; i < NR_IRQS; i++) {
151 if (PIC_IRQ_IS_IRT(i))
152 irq_set_chip_and_handler(i, &xlr_pic, handle_level_irq);
153 else
154 irq_set_chip_and_handler(i, &nlm_cpu_intr,
155 handle_level_irq);
156 }
157#ifdef CONFIG_SMP
158 irq_set_chip_and_handler(IRQ_IPI_SMP_FUNCTION, &nlm_cpu_intr,
159 nlm_smp_function_ipi_handler);
160 irq_set_chip_and_handler(IRQ_IPI_SMP_RESCHEDULE, &nlm_cpu_intr,
161 nlm_smp_resched_ipi_handler);
162 nlm_irq_mask |=
163 ((1ULL << IRQ_IPI_SMP_FUNCTION) | (1ULL << IRQ_IPI_SMP_RESCHEDULE));
164#endif
165 /* unmask all PIC related interrupts. If no handler is installed by the
166 * drivers, it'll just ack the interrupt and return
167 */
168 for (i = PIC_IRT_FIRST_IRQ; i <= PIC_IRT_LAST_IRQ; i++)
169 nlm_irq_mask |= (1ULL << i);
170
171 nlm_irq_mask |= (1ULL << IRQ_TIMER);
172}
173
174void __init arch_init_irq(void)
175{
176 /* Initialize the irq descriptors */
177 init_xlr_irqs();
178 write_c0_eimr(nlm_irq_mask);
179}
180
181void __cpuinit nlm_smp_irq_init(void)
182{
183 /* set interrupt mask for non-zero cpus */
184 write_c0_eimr(nlm_irq_mask);
185}
186
187asmlinkage void plat_irq_dispatch(void)
188{
189 uint64_t eirr;
190 int i;
191
192 eirr = read_c0_eirr() & read_c0_eimr();
193 if (!eirr)
194 return;
195
196 /* no need of EIRR here, writing compare clears interrupt */
197 if (eirr & (1 << IRQ_TIMER)) {
198 do_IRQ(IRQ_TIMER);
199 return;
200 }
201
202 /* TODO use dcltz: optimize below code */
203 for (i = 63; i != -1; i--) {
204 if (eirr & (1ULL << i))
205 break;
206 }
207 if (i == -1) {
208 pr_err("no interrupt !!\n");
209 return;
210 }
211
212 /* Ack eirr */
213 write_c0_eirr(1ULL << i);
214
215 do_IRQ(i);
216}
diff --git a/arch/mips/netlogic/xlr/platform.c b/arch/mips/netlogic/xlr/platform.c
new file mode 100644
index 00000000000..609ec253464
--- /dev/null
+++ b/arch/mips/netlogic/xlr/platform.c
@@ -0,0 +1,98 @@
1/*
2 * Copyright 2011, Netlogic Microsystems.
3 * Copyright 2004, Matt Porter <mporter@kernel.crashing.org>
4 *
5 * This file is licensed under the terms of the GNU General Public
6 * License version 2. This program is licensed "as is" without any
7 * warranty of any kind, whether express or implied.
8 */
9
10#include <linux/device.h>
11#include <linux/platform_device.h>
12#include <linux/kernel.h>
13#include <linux/init.h>
14#include <linux/resource.h>
15#include <linux/serial_8250.h>
16#include <linux/serial_reg.h>
17
18#include <asm/netlogic/xlr/iomap.h>
19#include <asm/netlogic/xlr/pic.h>
20#include <asm/netlogic/xlr/xlr.h>
21
22unsigned int nlm_xlr_uart_in(struct uart_port *p, int offset)
23{
24 nlm_reg_t *mmio;
25 unsigned int value;
26
27 /* XLR uart does not need any mapping of regs */
28 mmio = (nlm_reg_t *)(p->membase + (offset << p->regshift));
29 value = netlogic_read_reg(mmio, 0);
30
31 /* See XLR/XLS errata */
32 if (offset == UART_MSR)
33 value ^= 0xF0;
34 else if (offset == UART_MCR)
35 value ^= 0x3;
36
37 return value;
38}
39
40void nlm_xlr_uart_out(struct uart_port *p, int offset, int value)
41{
42 nlm_reg_t *mmio;
43
44 /* XLR uart does not need any mapping of regs */
45 mmio = (nlm_reg_t *)(p->membase + (offset << p->regshift));
46
47 /* See XLR/XLS errata */
48 if (offset == UART_MSR)
49 value ^= 0xF0;
50 else if (offset == UART_MCR)
51 value ^= 0x3;
52
53 netlogic_write_reg(mmio, 0, value);
54}
55
56#define PORT(_irq) \
57 { \
58 .irq = _irq, \
59 .regshift = 2, \
60 .iotype = UPIO_MEM32, \
61 .flags = (UPF_SKIP_TEST | \
62 UPF_FIXED_TYPE | UPF_BOOT_AUTOCONF),\
63 .uartclk = PIC_CLKS_PER_SEC, \
64 .type = PORT_16550A, \
65 .serial_in = nlm_xlr_uart_in, \
66 .serial_out = nlm_xlr_uart_out, \
67 }
68
69static struct plat_serial8250_port xlr_uart_data[] = {
70 PORT(PIC_UART_0_IRQ),
71 PORT(PIC_UART_1_IRQ),
72 {},
73};
74
75static struct platform_device uart_device = {
76 .name = "serial8250",
77 .id = PLAT8250_DEV_PLATFORM,
78 .dev = {
79 .platform_data = xlr_uart_data,
80 },
81};
82
83static int __init nlm_uart_init(void)
84{
85 nlm_reg_t *mmio;
86
87 mmio = netlogic_io_mmio(NETLOGIC_IO_UART_0_OFFSET);
88 xlr_uart_data[0].membase = (void __iomem *)mmio;
89 xlr_uart_data[0].mapbase = CPHYSADDR((unsigned long)mmio);
90
91 mmio = netlogic_io_mmio(NETLOGIC_IO_UART_1_OFFSET);
92 xlr_uart_data[1].membase = (void __iomem *)mmio;
93 xlr_uart_data[1].mapbase = CPHYSADDR((unsigned long)mmio);
94
95 return platform_device_register(&uart_device);
96}
97
98arch_initcall(nlm_uart_init);
diff --git a/arch/mips/netlogic/xlr/setup.c b/arch/mips/netlogic/xlr/setup.c
new file mode 100644
index 00000000000..482802569e7
--- /dev/null
+++ b/arch/mips/netlogic/xlr/setup.c
@@ -0,0 +1,188 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <linux/kernel.h>
36#include <linux/serial_8250.h>
37#include <linux/pm.h>
38
39#include <asm/reboot.h>
40#include <asm/time.h>
41#include <asm/bootinfo.h>
42#include <asm/smp-ops.h>
43
44#include <asm/netlogic/interrupt.h>
45#include <asm/netlogic/psb-bootinfo.h>
46
47#include <asm/netlogic/xlr/xlr.h>
48#include <asm/netlogic/xlr/iomap.h>
49#include <asm/netlogic/xlr/pic.h>
50#include <asm/netlogic/xlr/gpio.h>
51
52unsigned long netlogic_io_base = (unsigned long)(DEFAULT_NETLOGIC_IO_BASE);
53unsigned long nlm_common_ebase = 0x0;
54struct psb_info nlm_prom_info;
55
56static void nlm_early_serial_setup(void)
57{
58 struct uart_port s;
59 nlm_reg_t *uart_base;
60
61 uart_base = netlogic_io_mmio(NETLOGIC_IO_UART_0_OFFSET);
62 memset(&s, 0, sizeof(s));
63 s.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
64 s.iotype = UPIO_MEM32;
65 s.regshift = 2;
66 s.irq = PIC_UART_0_IRQ;
67 s.uartclk = PIC_CLKS_PER_SEC;
68 s.serial_in = nlm_xlr_uart_in;
69 s.serial_out = nlm_xlr_uart_out;
70 s.mapbase = (unsigned long)uart_base;
71 s.membase = (unsigned char __iomem *)uart_base;
72 early_serial_setup(&s);
73}
74
75static void nlm_linux_exit(void)
76{
77 nlm_reg_t *mmio;
78
79 mmio = netlogic_io_mmio(NETLOGIC_IO_GPIO_OFFSET);
80 /* trigger a chip reset by writing 1 to GPIO_SWRESET_REG */
81 netlogic_write_reg(mmio, NETLOGIC_GPIO_SWRESET_REG, 1);
82 for ( ; ; )
83 cpu_wait();
84}
85
86void __init plat_mem_setup(void)
87{
88 panic_timeout = 5;
89 _machine_restart = (void (*)(char *))nlm_linux_exit;
90 _machine_halt = nlm_linux_exit;
91 pm_power_off = nlm_linux_exit;
92}
93
94const char *get_system_type(void)
95{
96 return "Netlogic XLR/XLS Series";
97}
98
99void __init prom_free_prom_memory(void)
100{
101 /* Nothing yet */
102}
103
104static void build_arcs_cmdline(int *argv)
105{
106 int i, remain, len;
107 char *arg;
108
109 remain = sizeof(arcs_cmdline) - 1;
110 arcs_cmdline[0] = '\0';
111 for (i = 0; argv[i] != 0; i++) {
112 arg = (char *)(long)argv[i];
113 len = strlen(arg);
114 if (len + 1 > remain)
115 break;
116 strcat(arcs_cmdline, arg);
117 strcat(arcs_cmdline, " ");
118 remain -= len + 1;
119 }
120
121 /* Add the default options here */
122 if ((strstr(arcs_cmdline, "console=")) == NULL) {
123 arg = "console=ttyS0,38400 ";
124 len = strlen(arg);
125 if (len > remain)
126 goto fail;
127 strcat(arcs_cmdline, arg);
128 remain -= len;
129 }
130#ifdef CONFIG_BLK_DEV_INITRD
131 if ((strstr(arcs_cmdline, "rdinit=")) == NULL) {
132 arg = "rdinit=/sbin/init ";
133 len = strlen(arg);
134 if (len > remain)
135 goto fail;
136 strcat(arcs_cmdline, arg);
137 remain -= len;
138 }
139#endif
140 return;
141fail:
142 panic("Cannot add %s, command line too big!", arg);
143}
144
145static void prom_add_memory(void)
146{
147 struct nlm_boot_mem_map *bootm;
148 u64 start, size;
149 u64 pref_backup = 512; /* avoid pref walking beyond end */
150 int i;
151
152 bootm = (void *)(long)nlm_prom_info.psb_mem_map;
153 for (i = 0; i < bootm->nr_map; i++) {
154 if (bootm->map[i].type != BOOT_MEM_RAM)
155 continue;
156 start = bootm->map[i].addr;
157 size = bootm->map[i].size;
158
159 /* Work around for using bootloader mem */
160 if (i == 0 && start == 0 && size == 0x0c000000)
161 size = 0x0ff00000;
162
163 add_memory_region(start, size - pref_backup, BOOT_MEM_RAM);
164 }
165}
166
167void __init prom_init(void)
168{
169 int *argv, *envp; /* passed as 32 bit ptrs */
170 struct psb_info *prom_infop;
171
172 /* truncate to 32 bit and sign extend all args */
173 argv = (int *)(long)(int)fw_arg1;
174 envp = (int *)(long)(int)fw_arg2;
175 prom_infop = (struct psb_info *)(long)(int)fw_arg3;
176
177 nlm_prom_info = *prom_infop;
178
179 nlm_early_serial_setup();
180 build_arcs_cmdline(argv);
181 nlm_common_ebase = read_c0_ebase() & (~((1 << 12) - 1));
182 prom_add_memory();
183
184#ifdef CONFIG_SMP
185 nlm_wakeup_secondary_cpus(nlm_prom_info.online_cpu_map);
186 register_smp_ops(&nlm_smp_ops);
187#endif
188}
diff --git a/arch/mips/netlogic/xlr/smp.c b/arch/mips/netlogic/xlr/smp.c
new file mode 100644
index 00000000000..b495a7f1433
--- /dev/null
+++ b/arch/mips/netlogic/xlr/smp.c
@@ -0,0 +1,225 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <linux/kernel.h>
36#include <linux/delay.h>
37#include <linux/init.h>
38#include <linux/smp.h>
39#include <linux/irq.h>
40
41#include <asm/mmu_context.h>
42
43#include <asm/netlogic/interrupt.h>
44#include <asm/netlogic/mips-extns.h>
45
46#include <asm/netlogic/xlr/iomap.h>
47#include <asm/netlogic/xlr/pic.h>
48#include <asm/netlogic/xlr/xlr.h>
49
50void core_send_ipi(int logical_cpu, unsigned int action)
51{
52 int cpu = cpu_logical_map(logical_cpu);
53 u32 tid = cpu & 0x3;
54 u32 pid = (cpu >> 2) & 0x07;
55 u32 ipi = (tid << 16) | (pid << 20);
56
57 if (action & SMP_CALL_FUNCTION)
58 ipi |= IRQ_IPI_SMP_FUNCTION;
59 else if (action & SMP_RESCHEDULE_YOURSELF)
60 ipi |= IRQ_IPI_SMP_RESCHEDULE;
61 else
62 return;
63
64 pic_send_ipi(ipi);
65}
66
67void nlm_send_ipi_single(int cpu, unsigned int action)
68{
69 core_send_ipi(cpu, action);
70}
71
72void nlm_send_ipi_mask(const struct cpumask *mask, unsigned int action)
73{
74 int cpu;
75
76 for_each_cpu(cpu, mask) {
77 core_send_ipi(cpu, action);
78 }
79}
80
81/* IRQ_IPI_SMP_FUNCTION Handler */
82void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc)
83{
84 smp_call_function_interrupt();
85}
86
87/* IRQ_IPI_SMP_RESCHEDULE handler */
88void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc)
89{
90 set_need_resched();
91}
92
93void nlm_common_ipi_handler(int irq, struct pt_regs *regs)
94{
95 if (irq == IRQ_IPI_SMP_FUNCTION) {
96 smp_call_function_interrupt();
97 } else {
98 /* Announce that we are for reschduling */
99 set_need_resched();
100 }
101}
102
103/*
104 * Called before going into mips code, early cpu init
105 */
106void nlm_early_init_secondary(void)
107{
108 write_c0_ebase((uint32_t)nlm_common_ebase);
109 /* TLB partition here later */
110}
111
112/*
113 * Code to run on secondary just after probing the CPU
114 */
115static void __cpuinit nlm_init_secondary(void)
116{
117 nlm_smp_irq_init();
118}
119
120void nlm_smp_finish(void)
121{
122#ifdef notyet
123 nlm_common_msgring_cpu_init();
124#endif
125}
126
127void nlm_cpus_done(void)
128{
129}
130
131/*
132 * Boot all other cpus in the system, initialize them, and bring them into
133 * the boot function
134 */
135int nlm_cpu_unblock[NR_CPUS];
136int nlm_cpu_ready[NR_CPUS];
137unsigned long nlm_next_gp;
138unsigned long nlm_next_sp;
139cpumask_t phys_cpu_present_map;
140
141void nlm_boot_secondary(int logical_cpu, struct task_struct *idle)
142{
143 unsigned long gp = (unsigned long)task_thread_info(idle);
144 unsigned long sp = (unsigned long)__KSTK_TOS(idle);
145 int cpu = cpu_logical_map(logical_cpu);
146
147 nlm_next_sp = sp;
148 nlm_next_gp = gp;
149
150 /* barrier */
151 __sync();
152 nlm_cpu_unblock[cpu] = 1;
153}
154
155void __init nlm_smp_setup(void)
156{
157 unsigned int boot_cpu;
158 int num_cpus, i;
159
160 boot_cpu = hard_smp_processor_id();
161 cpus_clear(phys_cpu_present_map);
162
163 cpu_set(boot_cpu, phys_cpu_present_map);
164 __cpu_number_map[boot_cpu] = 0;
165 __cpu_logical_map[0] = boot_cpu;
166 cpu_set(0, cpu_possible_map);
167
168 num_cpus = 1;
169 for (i = 0; i < NR_CPUS; i++) {
170 if (nlm_cpu_ready[i]) {
171 cpu_set(i, phys_cpu_present_map);
172 __cpu_number_map[i] = num_cpus;
173 __cpu_logical_map[num_cpus] = i;
174 cpu_set(num_cpus, cpu_possible_map);
175 ++num_cpus;
176 }
177 }
178
179 pr_info("Phys CPU present map: %lx, possible map %lx\n",
180 (unsigned long)phys_cpu_present_map.bits[0],
181 (unsigned long)cpu_possible_map.bits[0]);
182
183 pr_info("Detected %i Slave CPU(s)\n", num_cpus);
184}
185
186void nlm_prepare_cpus(unsigned int max_cpus)
187{
188}
189
190struct plat_smp_ops nlm_smp_ops = {
191 .send_ipi_single = nlm_send_ipi_single,
192 .send_ipi_mask = nlm_send_ipi_mask,
193 .init_secondary = nlm_init_secondary,
194 .smp_finish = nlm_smp_finish,
195 .cpus_done = nlm_cpus_done,
196 .boot_secondary = nlm_boot_secondary,
197 .smp_setup = nlm_smp_setup,
198 .prepare_cpus = nlm_prepare_cpus,
199};
200
201unsigned long secondary_entry_point;
202
203int nlm_wakeup_secondary_cpus(u32 wakeup_mask)
204{
205 unsigned int tid, pid, ipi, i, boot_cpu;
206 void *reset_vec;
207
208 secondary_entry_point = (unsigned long)prom_pre_boot_secondary_cpus;
209 reset_vec = (void *)CKSEG1ADDR(0x1fc00000);
210 memcpy(reset_vec, nlm_boot_smp_nmi, 0x80);
211 boot_cpu = hard_smp_processor_id();
212
213 for (i = 0; i < NR_CPUS; i++) {
214 if (i == boot_cpu)
215 continue;
216 if (wakeup_mask & (1u << i)) {
217 tid = i & 0x3;
218 pid = (i >> 2) & 0x7;
219 ipi = (tid << 16) | (pid << 20) | (1 << 8);
220 pic_send_ipi(ipi);
221 }
222 }
223
224 return 0;
225}
diff --git a/arch/mips/netlogic/xlr/smpboot.S b/arch/mips/netlogic/xlr/smpboot.S
new file mode 100644
index 00000000000..b8e074402c9
--- /dev/null
+++ b/arch/mips/netlogic/xlr/smpboot.S
@@ -0,0 +1,94 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <asm/asm.h>
36#include <asm/asm-offsets.h>
37#include <asm/regdef.h>
38#include <asm/mipsregs.h>
39
40
41/* Don't jump to linux function from Bootloader stack. Change it
42 * here. Kernel might allocate bootloader memory before all the CPUs are
43 * brought up (eg: Inode cache region) and we better don't overwrite this
44 * memory
45 */
46NESTED(prom_pre_boot_secondary_cpus, 16, sp)
47 .set mips64
48 mfc0 t0, $15, 1 # read ebase
49 andi t0, 0x1f # t0 has the processor_id()
50 sll t0, 2 # offset in cpu array
51
52 PTR_LA t1, nlm_cpu_ready # mark CPU ready
53 PTR_ADDU t1, t0
54 li t2, 1
55 sw t2, 0(t1)
56
57 PTR_LA t1, nlm_cpu_unblock
58 PTR_ADDU t1, t0
591: lw t2, 0(t1) # wait till unblocked
60 beqz t2, 1b
61 nop
62
63 PTR_LA t1, nlm_next_sp
64 PTR_L sp, 0(t1)
65 PTR_LA t1, nlm_next_gp
66 PTR_L gp, 0(t1)
67
68 PTR_LA t0, nlm_early_init_secondary
69 jalr t0
70 nop
71
72 PTR_LA t0, smp_bootstrap
73 jr t0
74 nop
75END(prom_pre_boot_secondary_cpus)
76
77NESTED(nlm_boot_smp_nmi, 0, sp)
78 .set push
79 .set noat
80 .set mips64
81 .set noreorder
82
83 /* Clear the NMI and BEV bits */
84 MFC0 k0, CP0_STATUS
85 li k1, 0xffb7ffff
86 and k0, k0, k1
87 MTC0 k0, CP0_STATUS
88
89 PTR_LA k1, secondary_entry_point
90 PTR_L k0, 0(k1)
91 jr k0
92 nop
93 .set pop
94END(nlm_boot_smp_nmi)
diff --git a/arch/mips/netlogic/xlr/time.c b/arch/mips/netlogic/xlr/time.c
new file mode 100644
index 00000000000..0d81b262593
--- /dev/null
+++ b/arch/mips/netlogic/xlr/time.c
@@ -0,0 +1,51 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <linux/init.h>
36
37#include <asm/time.h>
38#include <asm/netlogic/interrupt.h>
39#include <asm/netlogic/psb-bootinfo.h>
40
41unsigned int __cpuinit get_c0_compare_int(void)
42{
43 return IRQ_TIMER;
44}
45
46void __init plat_time_init(void)
47{
48 mips_hpt_frequency = nlm_prom_info.cpu_frequency;
49 pr_info("MIPS counter frequency [%ld]\n",
50 (unsigned long)mips_hpt_frequency);
51}
diff --git a/arch/mips/netlogic/xlr/xlr_console.c b/arch/mips/netlogic/xlr/xlr_console.c
new file mode 100644
index 00000000000..759df069220
--- /dev/null
+++ b/arch/mips/netlogic/xlr/xlr_console.c
@@ -0,0 +1,46 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <linux/types.h>
36#include <asm/netlogic/xlr/iomap.h>
37
38void prom_putchar(char c)
39{
40 nlm_reg_t *mmio;
41
42 mmio = netlogic_io_mmio(NETLOGIC_IO_UART_0_OFFSET);
43 while (netlogic_read_reg(mmio, 0x5) == 0)
44 ;
45 netlogic_write_reg(mmio, 0x0, c);
46}
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-23 19:10:45 -0400