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-rw-r--r--drivers/net/wireless/b43/lo.c64
-rw-r--r--drivers/net/wireless/b43/phy.c151
-rw-r--r--drivers/net/wireless/b43/phy.h44
3 files changed, 145 insertions, 114 deletions
diff --git a/drivers/net/wireless/b43/lo.c b/drivers/net/wireless/b43/lo.c
index 88f35e67e22..d890f366a23 100644
--- a/drivers/net/wireless/b43/lo.c
+++ b/drivers/net/wireless/b43/lo.c
@@ -555,20 +555,20 @@ struct lo_g_saved_values {
555 u16 phy_extg_01; 555 u16 phy_extg_01;
556 u16 phy_dacctl_hwpctl; 556 u16 phy_dacctl_hwpctl;
557 u16 phy_dacctl; 557 u16 phy_dacctl;
558 u16 phy_base_14; 558 u16 phy_cck_14;
559 u16 phy_hpwr_tssictl; 559 u16 phy_hpwr_tssictl;
560 u16 phy_analogover; 560 u16 phy_analogover;
561 u16 phy_analogoverval; 561 u16 phy_analogoverval;
562 u16 phy_rfover; 562 u16 phy_rfover;
563 u16 phy_rfoverval; 563 u16 phy_rfoverval;
564 u16 phy_classctl; 564 u16 phy_classctl;
565 u16 phy_base_3E; 565 u16 phy_cck_3E;
566 u16 phy_crs0; 566 u16 phy_crs0;
567 u16 phy_pgactl; 567 u16 phy_pgactl;
568 u16 phy_base_2A; 568 u16 phy_cck_2A;
569 u16 phy_syncctl; 569 u16 phy_syncctl;
570 u16 phy_base_30; 570 u16 phy_cck_30;
571 u16 phy_base_06; 571 u16 phy_cck_06;
572 572
573 /* Radio registers */ 573 /* Radio registers */
574 u16 radio_43; 574 u16 radio_43;
@@ -588,7 +588,7 @@ static void lo_measure_setup(struct b43_wldev *dev,
588 sav->phy_lo_mask = b43_phy_read(dev, B43_PHY_LO_MASK); 588 sav->phy_lo_mask = b43_phy_read(dev, B43_PHY_LO_MASK);
589 sav->phy_extg_01 = b43_phy_read(dev, B43_PHY_EXTG(0x01)); 589 sav->phy_extg_01 = b43_phy_read(dev, B43_PHY_EXTG(0x01));
590 sav->phy_dacctl_hwpctl = b43_phy_read(dev, B43_PHY_DACCTL); 590 sav->phy_dacctl_hwpctl = b43_phy_read(dev, B43_PHY_DACCTL);
591 sav->phy_base_14 = b43_phy_read(dev, B43_PHY_BASE(0x14)); 591 sav->phy_cck_14 = b43_phy_read(dev, B43_PHY_CCK(0x14));
592 sav->phy_hpwr_tssictl = b43_phy_read(dev, B43_PHY_HPWR_TSSICTL); 592 sav->phy_hpwr_tssictl = b43_phy_read(dev, B43_PHY_HPWR_TSSICTL);
593 593
594 b43_phy_write(dev, B43_PHY_HPWR_TSSICTL, 594 b43_phy_write(dev, B43_PHY_HPWR_TSSICTL,
@@ -600,14 +600,14 @@ static void lo_measure_setup(struct b43_wldev *dev,
600 b43_phy_write(dev, B43_PHY_DACCTL, 600 b43_phy_write(dev, B43_PHY_DACCTL,
601 b43_phy_read(dev, B43_PHY_DACCTL) 601 b43_phy_read(dev, B43_PHY_DACCTL)
602 | 0x40); 602 | 0x40);
603 b43_phy_write(dev, B43_PHY_BASE(0x14), 603 b43_phy_write(dev, B43_PHY_CCK(0x14),
604 b43_phy_read(dev, B43_PHY_BASE(0x14)) 604 b43_phy_read(dev, B43_PHY_CCK(0x14))
605 | 0x200); 605 | 0x200);
606 } 606 }
607 if (phy->type == B43_PHYTYPE_B && 607 if (phy->type == B43_PHYTYPE_B &&
608 phy->radio_ver == 0x2050 && phy->radio_rev < 6) { 608 phy->radio_ver == 0x2050 && phy->radio_rev < 6) {
609 b43_phy_write(dev, B43_PHY_BASE(0x16), 0x410); 609 b43_phy_write(dev, B43_PHY_CCK(0x16), 0x410);
610 b43_phy_write(dev, B43_PHY_BASE(0x17), 0x820); 610 b43_phy_write(dev, B43_PHY_CCK(0x17), 0x820);
611 } 611 }
612 if (!lo->rebuild && b43_has_hardware_pctl(phy)) 612 if (!lo->rebuild && b43_has_hardware_pctl(phy))
613 lo_read_power_vector(dev); 613 lo_read_power_vector(dev);
@@ -618,7 +618,7 @@ static void lo_measure_setup(struct b43_wldev *dev,
618 sav->phy_rfover = b43_phy_read(dev, B43_PHY_RFOVER); 618 sav->phy_rfover = b43_phy_read(dev, B43_PHY_RFOVER);
619 sav->phy_rfoverval = b43_phy_read(dev, B43_PHY_RFOVERVAL); 619 sav->phy_rfoverval = b43_phy_read(dev, B43_PHY_RFOVERVAL);
620 sav->phy_classctl = b43_phy_read(dev, B43_PHY_CLASSCTL); 620 sav->phy_classctl = b43_phy_read(dev, B43_PHY_CLASSCTL);
621 sav->phy_base_3E = b43_phy_read(dev, B43_PHY_BASE(0x3E)); 621 sav->phy_cck_3E = b43_phy_read(dev, B43_PHY_CCK(0x3E));
622 sav->phy_crs0 = b43_phy_read(dev, B43_PHY_CRS0); 622 sav->phy_crs0 = b43_phy_read(dev, B43_PHY_CRS0);
623 623
624 b43_phy_write(dev, B43_PHY_CLASSCTL, 624 b43_phy_write(dev, B43_PHY_CLASSCTL,
@@ -642,14 +642,14 @@ static void lo_measure_setup(struct b43_wldev *dev,
642 } else { 642 } else {
643 b43_phy_write(dev, B43_PHY_RFOVER, 0); 643 b43_phy_write(dev, B43_PHY_RFOVER, 0);
644 } 644 }
645 b43_phy_write(dev, B43_PHY_BASE(0x3E), 0); 645 b43_phy_write(dev, B43_PHY_CCK(0x3E), 0);
646 } 646 }
647 sav->reg_3F4 = b43_read16(dev, 0x3F4); 647 sav->reg_3F4 = b43_read16(dev, 0x3F4);
648 sav->reg_3E2 = b43_read16(dev, 0x3E2); 648 sav->reg_3E2 = b43_read16(dev, 0x3E2);
649 sav->radio_43 = b43_radio_read16(dev, 0x43); 649 sav->radio_43 = b43_radio_read16(dev, 0x43);
650 sav->radio_7A = b43_radio_read16(dev, 0x7A); 650 sav->radio_7A = b43_radio_read16(dev, 0x7A);
651 sav->phy_pgactl = b43_phy_read(dev, B43_PHY_PGACTL); 651 sav->phy_pgactl = b43_phy_read(dev, B43_PHY_PGACTL);
652 sav->phy_base_2A = b43_phy_read(dev, B43_PHY_BASE(0x2A)); 652 sav->phy_cck_2A = b43_phy_read(dev, B43_PHY_CCK(0x2A));
653 sav->phy_syncctl = b43_phy_read(dev, B43_PHY_SYNCCTL); 653 sav->phy_syncctl = b43_phy_read(dev, B43_PHY_SYNCCTL);
654 sav->phy_dacctl = b43_phy_read(dev, B43_PHY_DACCTL); 654 sav->phy_dacctl = b43_phy_read(dev, B43_PHY_DACCTL);
655 655
@@ -658,10 +658,10 @@ static void lo_measure_setup(struct b43_wldev *dev,
658 sav->radio_52 &= 0x00F0; 658 sav->radio_52 &= 0x00F0;
659 } 659 }
660 if (phy->type == B43_PHYTYPE_B) { 660 if (phy->type == B43_PHYTYPE_B) {
661 sav->phy_base_30 = b43_phy_read(dev, B43_PHY_BASE(0x30)); 661 sav->phy_cck_30 = b43_phy_read(dev, B43_PHY_CCK(0x30));
662 sav->phy_base_06 = b43_phy_read(dev, B43_PHY_BASE(0x06)); 662 sav->phy_cck_06 = b43_phy_read(dev, B43_PHY_CCK(0x06));
663 b43_phy_write(dev, B43_PHY_BASE(0x30), 0x00FF); 663 b43_phy_write(dev, B43_PHY_CCK(0x30), 0x00FF);
664 b43_phy_write(dev, B43_PHY_BASE(0x06), 0x3F3F); 664 b43_phy_write(dev, B43_PHY_CCK(0x06), 0x3F3F);
665 } else { 665 } else {
666 b43_write16(dev, 0x3E2, b43_read16(dev, 0x3E2) 666 b43_write16(dev, 0x3E2, b43_read16(dev, 0x3E2)
667 | 0x8000); 667 | 0x8000);
@@ -670,7 +670,7 @@ static void lo_measure_setup(struct b43_wldev *dev,
670 & 0xF000); 670 & 0xF000);
671 671
672 tmp = 672 tmp =
673 (phy->type == B43_PHYTYPE_G) ? B43_PHY_LO_MASK : B43_PHY_BASE(0x2E); 673 (phy->type == B43_PHYTYPE_G) ? B43_PHY_LO_MASK : B43_PHY_CCK(0x2E);
674 b43_phy_write(dev, tmp, 0x007F); 674 b43_phy_write(dev, tmp, 0x007F);
675 675
676 tmp = sav->phy_syncctl; 676 tmp = sav->phy_syncctl;
@@ -678,26 +678,26 @@ static void lo_measure_setup(struct b43_wldev *dev,
678 tmp = sav->radio_7A; 678 tmp = sav->radio_7A;
679 b43_radio_write16(dev, 0x007A, tmp & 0xFFF0); 679 b43_radio_write16(dev, 0x007A, tmp & 0xFFF0);
680 680
681 b43_phy_write(dev, B43_PHY_BASE(0x2A), 0x8A3); 681 b43_phy_write(dev, B43_PHY_CCK(0x2A), 0x8A3);
682 if (phy->type == B43_PHYTYPE_G || 682 if (phy->type == B43_PHYTYPE_G ||
683 (phy->type == B43_PHYTYPE_B && 683 (phy->type == B43_PHYTYPE_B &&
684 phy->radio_ver == 0x2050 && phy->radio_rev >= 6)) { 684 phy->radio_ver == 0x2050 && phy->radio_rev >= 6)) {
685 b43_phy_write(dev, B43_PHY_BASE(0x2B), 0x1003); 685 b43_phy_write(dev, B43_PHY_CCK(0x2B), 0x1003);
686 } else 686 } else
687 b43_phy_write(dev, B43_PHY_BASE(0x2B), 0x0802); 687 b43_phy_write(dev, B43_PHY_CCK(0x2B), 0x0802);
688 if (phy->rev >= 2) 688 if (phy->rev >= 2)
689 b43_dummy_transmission(dev); 689 b43_dummy_transmission(dev);
690 b43_radio_selectchannel(dev, 6, 0); 690 b43_radio_selectchannel(dev, 6, 0);
691 b43_radio_read16(dev, 0x51); /* dummy read */ 691 b43_radio_read16(dev, 0x51); /* dummy read */
692 if (phy->type == B43_PHYTYPE_G) 692 if (phy->type == B43_PHYTYPE_G)
693 b43_phy_write(dev, B43_PHY_BASE(0x2F), 0); 693 b43_phy_write(dev, B43_PHY_CCK(0x2F), 0);
694 if (lo->rebuild) 694 if (lo->rebuild)
695 lo_measure_txctl_values(dev); 695 lo_measure_txctl_values(dev);
696 if (phy->type == B43_PHYTYPE_G && phy->rev >= 3) { 696 if (phy->type == B43_PHYTYPE_G && phy->rev >= 3) {
697 b43_phy_write(dev, B43_PHY_LO_MASK, 0xC078); 697 b43_phy_write(dev, B43_PHY_LO_MASK, 0xC078);
698 } else { 698 } else {
699 if (phy->type == B43_PHYTYPE_B) 699 if (phy->type == B43_PHYTYPE_B)
700 b43_phy_write(dev, B43_PHY_BASE(0x2E), 0x8078); 700 b43_phy_write(dev, B43_PHY_CCK(0x2E), 0x8078);
701 else 701 else
702 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8078); 702 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8078);
703 } 703 }
@@ -732,17 +732,17 @@ static void lo_measure_restore(struct b43_wldev *dev,
732 } 732 }
733 if (phy->type == B43_PHYTYPE_G) { 733 if (phy->type == B43_PHYTYPE_G) {
734 if (phy->rev >= 3) 734 if (phy->rev >= 3)
735 b43_phy_write(dev, B43_PHY_BASE(0x2E), 0xC078); 735 b43_phy_write(dev, B43_PHY_CCK(0x2E), 0xC078);
736 else 736 else
737 b43_phy_write(dev, B43_PHY_BASE(0x2E), 0x8078); 737 b43_phy_write(dev, B43_PHY_CCK(0x2E), 0x8078);
738 if (phy->rev >= 2) 738 if (phy->rev >= 2)
739 b43_phy_write(dev, B43_PHY_BASE(0x2F), 0x0202); 739 b43_phy_write(dev, B43_PHY_CCK(0x2F), 0x0202);
740 else 740 else
741 b43_phy_write(dev, B43_PHY_BASE(0x2F), 0x0101); 741 b43_phy_write(dev, B43_PHY_CCK(0x2F), 0x0101);
742 } 742 }
743 b43_write16(dev, 0x3F4, sav->reg_3F4); 743 b43_write16(dev, 0x3F4, sav->reg_3F4);
744 b43_phy_write(dev, B43_PHY_PGACTL, sav->phy_pgactl); 744 b43_phy_write(dev, B43_PHY_PGACTL, sav->phy_pgactl);
745 b43_phy_write(dev, B43_PHY_BASE(0x2A), sav->phy_base_2A); 745 b43_phy_write(dev, B43_PHY_CCK(0x2A), sav->phy_cck_2A);
746 b43_phy_write(dev, B43_PHY_SYNCCTL, sav->phy_syncctl); 746 b43_phy_write(dev, B43_PHY_SYNCCTL, sav->phy_syncctl);
747 b43_phy_write(dev, B43_PHY_DACCTL, sav->phy_dacctl); 747 b43_phy_write(dev, B43_PHY_DACCTL, sav->phy_dacctl);
748 b43_radio_write16(dev, 0x43, sav->radio_43); 748 b43_radio_write16(dev, 0x43, sav->radio_43);
@@ -755,8 +755,8 @@ static void lo_measure_restore(struct b43_wldev *dev,
755 b43_write16(dev, 0x3E2, sav->reg_3E2); 755 b43_write16(dev, 0x3E2, sav->reg_3E2);
756 if (phy->type == B43_PHYTYPE_B && 756 if (phy->type == B43_PHYTYPE_B &&
757 phy->radio_ver == 0x2050 && phy->radio_rev <= 5) { 757 phy->radio_ver == 0x2050 && phy->radio_rev <= 5) {
758 b43_phy_write(dev, B43_PHY_BASE(0x30), sav->phy_base_30); 758 b43_phy_write(dev, B43_PHY_CCK(0x30), sav->phy_cck_30);
759 b43_phy_write(dev, B43_PHY_BASE(0x06), sav->phy_base_06); 759 b43_phy_write(dev, B43_PHY_CCK(0x06), sav->phy_cck_06);
760 } 760 }
761 if (phy->rev >= 2) { 761 if (phy->rev >= 2) {
762 b43_phy_write(dev, B43_PHY_ANALOGOVER, sav->phy_analogover); 762 b43_phy_write(dev, B43_PHY_ANALOGOVER, sav->phy_analogover);
@@ -765,7 +765,7 @@ static void lo_measure_restore(struct b43_wldev *dev,
765 b43_phy_write(dev, B43_PHY_CLASSCTL, sav->phy_classctl); 765 b43_phy_write(dev, B43_PHY_CLASSCTL, sav->phy_classctl);
766 b43_phy_write(dev, B43_PHY_RFOVER, sav->phy_rfover); 766 b43_phy_write(dev, B43_PHY_RFOVER, sav->phy_rfover);
767 b43_phy_write(dev, B43_PHY_RFOVERVAL, sav->phy_rfoverval); 767 b43_phy_write(dev, B43_PHY_RFOVERVAL, sav->phy_rfoverval);
768 b43_phy_write(dev, B43_PHY_BASE(0x3E), sav->phy_base_3E); 768 b43_phy_write(dev, B43_PHY_CCK(0x3E), sav->phy_cck_3E);
769 b43_phy_write(dev, B43_PHY_CRS0, sav->phy_crs0); 769 b43_phy_write(dev, B43_PHY_CRS0, sav->phy_crs0);
770 } 770 }
771 if (b43_has_hardware_pctl(phy)) { 771 if (b43_has_hardware_pctl(phy)) {
@@ -773,7 +773,7 @@ static void lo_measure_restore(struct b43_wldev *dev,
773 b43_phy_write(dev, B43_PHY_LO_MASK, tmp); 773 b43_phy_write(dev, B43_PHY_LO_MASK, tmp);
774 b43_phy_write(dev, B43_PHY_EXTG(0x01), sav->phy_extg_01); 774 b43_phy_write(dev, B43_PHY_EXTG(0x01), sav->phy_extg_01);
775 b43_phy_write(dev, B43_PHY_DACCTL, sav->phy_dacctl_hwpctl); 775 b43_phy_write(dev, B43_PHY_DACCTL, sav->phy_dacctl_hwpctl);
776 b43_phy_write(dev, B43_PHY_BASE(0x14), sav->phy_base_14); 776 b43_phy_write(dev, B43_PHY_CCK(0x14), sav->phy_cck_14);
777 b43_phy_write(dev, B43_PHY_HPWR_TSSICTL, sav->phy_hpwr_tssictl); 777 b43_phy_write(dev, B43_PHY_HPWR_TSSICTL, sav->phy_hpwr_tssictl);
778 } 778 }
779 b43_radio_selectchannel(dev, sav->old_channel, 1); 779 b43_radio_selectchannel(dev, sav->old_channel, 1);
diff --git a/drivers/net/wireless/b43/phy.c b/drivers/net/wireless/b43/phy.c
index b544f7ff14f..67b8a922b33 100644
--- a/drivers/net/wireless/b43/phy.c
+++ b/drivers/net/wireless/b43/phy.c
@@ -274,15 +274,30 @@ static inline u16 adjust_phyreg_for_phytype(struct b43_phy *phy,
274{ 274{
275 if (phy->type == B43_PHYTYPE_A) { 275 if (phy->type == B43_PHYTYPE_A) {
276 /* OFDM registers are base-registers for the A-PHY. */ 276 /* OFDM registers are base-registers for the A-PHY. */
277 offset &= ~B43_PHYROUTE_OFDM_GPHY; 277 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
278 offset &= ~B43_PHYROUTE;
279 offset |= B43_PHYROUTE_BASE;
280 }
278 } 281 }
279 if (offset & B43_PHYROUTE_EXT_GPHY) { 282
283#if B43_DEBUG
284 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
280 /* Ext-G registers are only available on G-PHYs */ 285 /* Ext-G registers are only available on G-PHYs */
281 if (phy->type != B43_PHYTYPE_G) { 286 if (phy->type != B43_PHYTYPE_G) {
282 b43dbg(dev->wl, "EXT-G PHY access at " 287 b43err(dev->wl, "Invalid EXT-G PHY access at "
283 "0x%04X on %u type PHY\n", offset, phy->type); 288 "0x%04X on PHY type %u\n", offset, phy->type);
289 dump_stack();
290 }
291 }
292 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_N_BMODE) {
293 /* N-BMODE registers are only available on N-PHYs */
294 if (phy->type != B43_PHYTYPE_N) {
295 b43err(dev->wl, "Invalid N-BMODE PHY access at "
296 "0x%04X on PHY type %u\n", offset, phy->type);
297 dump_stack();
284 } 298 }
285 } 299 }
300#endif /* B43_DEBUG */
286 301
287 return offset; 302 return offset;
288} 303}
@@ -302,7 +317,6 @@ void b43_phy_write(struct b43_wldev *dev, u16 offset, u16 val)
302 317
303 offset = adjust_phyreg_for_phytype(phy, offset, dev); 318 offset = adjust_phyreg_for_phytype(phy, offset, dev);
304 b43_write16(dev, B43_MMIO_PHY_CONTROL, offset); 319 b43_write16(dev, B43_MMIO_PHY_CONTROL, offset);
305 mmiowb();
306 b43_write16(dev, B43_MMIO_PHY_DATA, val); 320 b43_write16(dev, B43_MMIO_PHY_DATA, val);
307} 321}
308 322
@@ -1273,14 +1287,14 @@ static void b43_calc_loopback_gain(struct b43_wldev *dev)
1273 backup_phy[4] = b43_phy_read(dev, B43_PHY_ANALOGOVER); 1287 backup_phy[4] = b43_phy_read(dev, B43_PHY_ANALOGOVER);
1274 backup_phy[5] = b43_phy_read(dev, B43_PHY_ANALOGOVERVAL); 1288 backup_phy[5] = b43_phy_read(dev, B43_PHY_ANALOGOVERVAL);
1275 } 1289 }
1276 backup_phy[6] = b43_phy_read(dev, B43_PHY_BASE(0x5A)); 1290 backup_phy[6] = b43_phy_read(dev, B43_PHY_CCK(0x5A));
1277 backup_phy[7] = b43_phy_read(dev, B43_PHY_BASE(0x59)); 1291 backup_phy[7] = b43_phy_read(dev, B43_PHY_CCK(0x59));
1278 backup_phy[8] = b43_phy_read(dev, B43_PHY_BASE(0x58)); 1292 backup_phy[8] = b43_phy_read(dev, B43_PHY_CCK(0x58));
1279 backup_phy[9] = b43_phy_read(dev, B43_PHY_BASE(0x0A)); 1293 backup_phy[9] = b43_phy_read(dev, B43_PHY_CCK(0x0A));
1280 backup_phy[10] = b43_phy_read(dev, B43_PHY_BASE(0x03)); 1294 backup_phy[10] = b43_phy_read(dev, B43_PHY_CCK(0x03));
1281 backup_phy[11] = b43_phy_read(dev, B43_PHY_LO_MASK); 1295 backup_phy[11] = b43_phy_read(dev, B43_PHY_LO_MASK);
1282 backup_phy[12] = b43_phy_read(dev, B43_PHY_LO_CTL); 1296 backup_phy[12] = b43_phy_read(dev, B43_PHY_LO_CTL);
1283 backup_phy[13] = b43_phy_read(dev, B43_PHY_BASE(0x2B)); 1297 backup_phy[13] = b43_phy_read(dev, B43_PHY_CCK(0x2B));
1284 backup_phy[14] = b43_phy_read(dev, B43_PHY_PGACTL); 1298 backup_phy[14] = b43_phy_read(dev, B43_PHY_PGACTL);
1285 backup_phy[15] = b43_phy_read(dev, B43_PHY_LO_LEAKAGE); 1299 backup_phy[15] = b43_phy_read(dev, B43_PHY_LO_LEAKAGE);
1286 backup_bband = phy->bbatt.att; 1300 backup_bband = phy->bbatt.att;
@@ -1322,12 +1336,12 @@ static void b43_calc_loopback_gain(struct b43_wldev *dev)
1322 (b43_phy_read(dev, B43_PHY_RFOVERVAL) 1336 (b43_phy_read(dev, B43_PHY_RFOVERVAL)
1323 & 0xFFCF) | 0x10); 1337 & 0xFFCF) | 0x10);
1324 1338
1325 b43_phy_write(dev, B43_PHY_BASE(0x5A), 0x0780); 1339 b43_phy_write(dev, B43_PHY_CCK(0x5A), 0x0780);
1326 b43_phy_write(dev, B43_PHY_BASE(0x59), 0xC810); 1340 b43_phy_write(dev, B43_PHY_CCK(0x59), 0xC810);
1327 b43_phy_write(dev, B43_PHY_BASE(0x58), 0x000D); 1341 b43_phy_write(dev, B43_PHY_CCK(0x58), 0x000D);
1328 1342
1329 b43_phy_write(dev, B43_PHY_BASE(0x0A), 1343 b43_phy_write(dev, B43_PHY_CCK(0x0A),
1330 b43_phy_read(dev, B43_PHY_BASE(0x0A)) | 0x2000); 1344 b43_phy_read(dev, B43_PHY_CCK(0x0A)) | 0x2000);
1331 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */ 1345 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
1332 b43_phy_write(dev, B43_PHY_ANALOGOVER, 1346 b43_phy_write(dev, B43_PHY_ANALOGOVER,
1333 b43_phy_read(dev, B43_PHY_ANALOGOVER) | 0x0004); 1347 b43_phy_read(dev, B43_PHY_ANALOGOVER) | 0x0004);
@@ -1335,8 +1349,8 @@ static void b43_calc_loopback_gain(struct b43_wldev *dev)
1335 b43_phy_read(dev, 1349 b43_phy_read(dev,
1336 B43_PHY_ANALOGOVERVAL) & 0xFFFB); 1350 B43_PHY_ANALOGOVERVAL) & 0xFFFB);
1337 } 1351 }
1338 b43_phy_write(dev, B43_PHY_BASE(0x03), 1352 b43_phy_write(dev, B43_PHY_CCK(0x03),
1339 (b43_phy_read(dev, B43_PHY_BASE(0x03)) 1353 (b43_phy_read(dev, B43_PHY_CCK(0x03))
1340 & 0xFF9F) | 0x40); 1354 & 0xFF9F) | 0x40);
1341 1355
1342 if (phy->radio_rev == 8) { 1356 if (phy->radio_rev == 8) {
@@ -1354,11 +1368,11 @@ static void b43_calc_loopback_gain(struct b43_wldev *dev)
1354 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8020); 1368 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8020);
1355 b43_phy_write(dev, B43_PHY_LO_CTL, 0); 1369 b43_phy_write(dev, B43_PHY_LO_CTL, 0);
1356 1370
1357 b43_phy_write(dev, B43_PHY_BASE(0x2B), 1371 b43_phy_write(dev, B43_PHY_CCK(0x2B),
1358 (b43_phy_read(dev, B43_PHY_BASE(0x2B)) 1372 (b43_phy_read(dev, B43_PHY_CCK(0x2B))
1359 & 0xFFC0) | 0x01); 1373 & 0xFFC0) | 0x01);
1360 b43_phy_write(dev, B43_PHY_BASE(0x2B), 1374 b43_phy_write(dev, B43_PHY_CCK(0x2B),
1361 (b43_phy_read(dev, B43_PHY_BASE(0x2B)) 1375 (b43_phy_read(dev, B43_PHY_CCK(0x2B))
1362 & 0xC0FF) | 0x800); 1376 & 0xC0FF) | 0x800);
1363 1377
1364 b43_phy_write(dev, B43_PHY_RFOVER, 1378 b43_phy_write(dev, B43_PHY_RFOVER,
@@ -1429,14 +1443,14 @@ static void b43_calc_loopback_gain(struct b43_wldev *dev)
1429 b43_phy_write(dev, B43_PHY_ANALOGOVER, backup_phy[4]); 1443 b43_phy_write(dev, B43_PHY_ANALOGOVER, backup_phy[4]);
1430 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL, backup_phy[5]); 1444 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL, backup_phy[5]);
1431 } 1445 }
1432 b43_phy_write(dev, B43_PHY_BASE(0x5A), backup_phy[6]); 1446 b43_phy_write(dev, B43_PHY_CCK(0x5A), backup_phy[6]);
1433 b43_phy_write(dev, B43_PHY_BASE(0x59), backup_phy[7]); 1447 b43_phy_write(dev, B43_PHY_CCK(0x59), backup_phy[7]);
1434 b43_phy_write(dev, B43_PHY_BASE(0x58), backup_phy[8]); 1448 b43_phy_write(dev, B43_PHY_CCK(0x58), backup_phy[8]);
1435 b43_phy_write(dev, B43_PHY_BASE(0x0A), backup_phy[9]); 1449 b43_phy_write(dev, B43_PHY_CCK(0x0A), backup_phy[9]);
1436 b43_phy_write(dev, B43_PHY_BASE(0x03), backup_phy[10]); 1450 b43_phy_write(dev, B43_PHY_CCK(0x03), backup_phy[10]);
1437 b43_phy_write(dev, B43_PHY_LO_MASK, backup_phy[11]); 1451 b43_phy_write(dev, B43_PHY_LO_MASK, backup_phy[11]);
1438 b43_phy_write(dev, B43_PHY_LO_CTL, backup_phy[12]); 1452 b43_phy_write(dev, B43_PHY_LO_CTL, backup_phy[12]);
1439 b43_phy_write(dev, B43_PHY_BASE(0x2B), backup_phy[13]); 1453 b43_phy_write(dev, B43_PHY_CCK(0x2B), backup_phy[13]);
1440 b43_phy_write(dev, B43_PHY_PGACTL, backup_phy[14]); 1454 b43_phy_write(dev, B43_PHY_PGACTL, backup_phy[14]);
1441 1455
1442 b43_phy_set_baseband_attenuation(dev, backup_bband); 1456 b43_phy_set_baseband_attenuation(dev, backup_bband);
@@ -1528,19 +1542,19 @@ static void b43_phy_initg(struct b43_wldev *dev)
1528 | phy->lo_control->tx_bias); 1542 | phy->lo_control->tx_bias);
1529 } 1543 }
1530 if (phy->rev >= 6) { 1544 if (phy->rev >= 6) {
1531 b43_phy_write(dev, B43_PHY_BASE(0x36), 1545 b43_phy_write(dev, B43_PHY_CCK(0x36),
1532 (b43_phy_read(dev, B43_PHY_BASE(0x36)) 1546 (b43_phy_read(dev, B43_PHY_CCK(0x36))
1533 & 0x0FFF) | (phy->lo_control-> 1547 & 0x0FFF) | (phy->lo_control->
1534 tx_bias << 12)); 1548 tx_bias << 12));
1535 } 1549 }
1536 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) 1550 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL)
1537 b43_phy_write(dev, B43_PHY_BASE(0x2E), 0x8075); 1551 b43_phy_write(dev, B43_PHY_CCK(0x2E), 0x8075);
1538 else 1552 else
1539 b43_phy_write(dev, B43_PHY_BASE(0x2E), 0x807F); 1553 b43_phy_write(dev, B43_PHY_CCK(0x2E), 0x807F);
1540 if (phy->rev < 2) 1554 if (phy->rev < 2)
1541 b43_phy_write(dev, B43_PHY_BASE(0x2F), 0x101); 1555 b43_phy_write(dev, B43_PHY_CCK(0x2F), 0x101);
1542 else 1556 else
1543 b43_phy_write(dev, B43_PHY_BASE(0x2F), 0x202); 1557 b43_phy_write(dev, B43_PHY_CCK(0x2F), 0x202);
1544 } 1558 }
1545 if (phy->gmode || phy->rev >= 2) { 1559 if (phy->gmode || phy->rev >= 2) {
1546 b43_lo_g_adjust(dev); 1560 b43_lo_g_adjust(dev);
@@ -2168,9 +2182,12 @@ u16 b43_radio_read16(struct b43_wldev *dev, u16 offset)
2168{ 2182{
2169 struct b43_phy *phy = &dev->phy; 2183 struct b43_phy *phy = &dev->phy;
2170 2184
2185 /* Offset 1 is a 32-bit register. */
2186 B43_WARN_ON(offset == 1);
2187
2171 switch (phy->type) { 2188 switch (phy->type) {
2172 case B43_PHYTYPE_A: 2189 case B43_PHYTYPE_A:
2173 offset |= 0x0040; 2190 offset |= 0x40;
2174 break; 2191 break;
2175 case B43_PHYTYPE_B: 2192 case B43_PHYTYPE_B:
2176 if (phy->radio_ver == 0x2053) { 2193 if (phy->radio_ver == 0x2053) {
@@ -2186,6 +2203,14 @@ u16 b43_radio_read16(struct b43_wldev *dev, u16 offset)
2186 case B43_PHYTYPE_G: 2203 case B43_PHYTYPE_G:
2187 offset |= 0x80; 2204 offset |= 0x80;
2188 break; 2205 break;
2206 case B43_PHYTYPE_N:
2207 offset |= 0x100;
2208 break;
2209 case B43_PHYTYPE_LP:
2210 /* No adjustment required. */
2211 break;
2212 default:
2213 B43_WARN_ON(1);
2189 } 2214 }
2190 2215
2191 b43_write16(dev, B43_MMIO_RADIO_CONTROL, offset); 2216 b43_write16(dev, B43_MMIO_RADIO_CONTROL, offset);
@@ -2194,8 +2219,10 @@ u16 b43_radio_read16(struct b43_wldev *dev, u16 offset)
2194 2219
2195void b43_radio_write16(struct b43_wldev *dev, u16 offset, u16 val) 2220void b43_radio_write16(struct b43_wldev *dev, u16 offset, u16 val)
2196{ 2221{
2222 /* Offset 1 is a 32-bit register. */
2223 B43_WARN_ON(offset == 1);
2224
2197 b43_write16(dev, B43_MMIO_RADIO_CONTROL, offset); 2225 b43_write16(dev, B43_MMIO_RADIO_CONTROL, offset);
2198 mmiowb();
2199 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, val); 2226 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, val);
2200} 2227}
2201 2228
@@ -3480,10 +3507,10 @@ struct init2050_saved_values {
3480 u16 radio_52; 3507 u16 radio_52;
3481 /* PHY registers */ 3508 /* PHY registers */
3482 u16 phy_pgactl; 3509 u16 phy_pgactl;
3483 u16 phy_base_5A; 3510 u16 phy_cck_5A;
3484 u16 phy_base_59; 3511 u16 phy_cck_59;
3485 u16 phy_base_58; 3512 u16 phy_cck_58;
3486 u16 phy_base_30; 3513 u16 phy_cck_30;
3487 u16 phy_rfover; 3514 u16 phy_rfover;
3488 u16 phy_rfoverval; 3515 u16 phy_rfoverval;
3489 u16 phy_analogover; 3516 u16 phy_analogover;
@@ -3511,15 +3538,15 @@ u16 b43_radio_init2050(struct b43_wldev *dev)
3511 sav.radio_51 = b43_radio_read16(dev, 0x51); 3538 sav.radio_51 = b43_radio_read16(dev, 0x51);
3512 sav.radio_52 = b43_radio_read16(dev, 0x52); 3539 sav.radio_52 = b43_radio_read16(dev, 0x52);
3513 sav.phy_pgactl = b43_phy_read(dev, B43_PHY_PGACTL); 3540 sav.phy_pgactl = b43_phy_read(dev, B43_PHY_PGACTL);
3514 sav.phy_base_5A = b43_phy_read(dev, B43_PHY_BASE(0x5A)); 3541 sav.phy_cck_5A = b43_phy_read(dev, B43_PHY_CCK(0x5A));
3515 sav.phy_base_59 = b43_phy_read(dev, B43_PHY_BASE(0x59)); 3542 sav.phy_cck_59 = b43_phy_read(dev, B43_PHY_CCK(0x59));
3516 sav.phy_base_58 = b43_phy_read(dev, B43_PHY_BASE(0x58)); 3543 sav.phy_cck_58 = b43_phy_read(dev, B43_PHY_CCK(0x58));
3517 3544
3518 if (phy->type == B43_PHYTYPE_B) { 3545 if (phy->type == B43_PHYTYPE_B) {
3519 sav.phy_base_30 = b43_phy_read(dev, B43_PHY_BASE(0x30)); 3546 sav.phy_cck_30 = b43_phy_read(dev, B43_PHY_CCK(0x30));
3520 sav.reg_3EC = b43_read16(dev, 0x3EC); 3547 sav.reg_3EC = b43_read16(dev, 0x3EC);
3521 3548
3522 b43_phy_write(dev, B43_PHY_BASE(0x30), 0xFF); 3549 b43_phy_write(dev, B43_PHY_CCK(0x30), 0xFF);
3523 b43_write16(dev, 0x3EC, 0x3F3F); 3550 b43_write16(dev, 0x3EC, 0x3F3F);
3524 } else if (phy->gmode || phy->rev >= 2) { 3551 } else if (phy->gmode || phy->rev >= 2) {
3525 sav.phy_rfover = b43_phy_read(dev, B43_PHY_RFOVER); 3552 sav.phy_rfover = b43_phy_read(dev, B43_PHY_RFOVER);
@@ -3570,8 +3597,8 @@ u16 b43_radio_init2050(struct b43_wldev *dev)
3570 b43_write16(dev, 0x03E6, 0x0122); 3597 b43_write16(dev, 0x03E6, 0x0122);
3571 } else { 3598 } else {
3572 if (phy->analog >= 2) { 3599 if (phy->analog >= 2) {
3573 b43_phy_write(dev, B43_PHY_BASE(0x03), 3600 b43_phy_write(dev, B43_PHY_CCK(0x03),
3574 (b43_phy_read(dev, B43_PHY_BASE(0x03)) 3601 (b43_phy_read(dev, B43_PHY_CCK(0x03))
3575 & 0xFFBF) | 0x40); 3602 & 0xFFBF) | 0x40);
3576 } 3603 }
3577 b43_write16(dev, B43_MMIO_CHANNEL_EXT, 3604 b43_write16(dev, B43_MMIO_CHANNEL_EXT,
@@ -3588,7 +3615,7 @@ u16 b43_radio_init2050(struct b43_wldev *dev)
3588 LPD(0, 1, 1))); 3615 LPD(0, 1, 1)));
3589 } 3616 }
3590 b43_phy_write(dev, B43_PHY_PGACTL, 0xBFAF); 3617 b43_phy_write(dev, B43_PHY_PGACTL, 0xBFAF);
3591 b43_phy_write(dev, B43_PHY_BASE(0x2B), 0x1403); 3618 b43_phy_write(dev, B43_PHY_CCK(0x2B), 0x1403);
3592 if (phy->gmode || phy->rev >= 2) { 3619 if (phy->gmode || phy->rev >= 2) {
3593 b43_phy_write(dev, B43_PHY_RFOVERVAL, 3620 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3594 radio2050_rfover_val(dev, B43_PHY_RFOVERVAL, 3621 radio2050_rfover_val(dev, B43_PHY_RFOVERVAL,
@@ -3604,12 +3631,12 @@ u16 b43_radio_init2050(struct b43_wldev *dev)
3604 b43_radio_write16(dev, 0x43, (b43_radio_read16(dev, 0x43) 3631 b43_radio_write16(dev, 0x43, (b43_radio_read16(dev, 0x43)
3605 & 0xFFF0) | 0x0009); 3632 & 0xFFF0) | 0x0009);
3606 } 3633 }
3607 b43_phy_write(dev, B43_PHY_BASE(0x58), 0); 3634 b43_phy_write(dev, B43_PHY_CCK(0x58), 0);
3608 3635
3609 for (i = 0; i < 16; i++) { 3636 for (i = 0; i < 16; i++) {
3610 b43_phy_write(dev, B43_PHY_BASE(0x5A), 0x0480); 3637 b43_phy_write(dev, B43_PHY_CCK(0x5A), 0x0480);
3611 b43_phy_write(dev, B43_PHY_BASE(0x59), 0xC810); 3638 b43_phy_write(dev, B43_PHY_CCK(0x59), 0xC810);
3612 b43_phy_write(dev, B43_PHY_BASE(0x58), 0x000D); 3639 b43_phy_write(dev, B43_PHY_CCK(0x58), 0x000D);
3613 if (phy->gmode || phy->rev >= 2) { 3640 if (phy->gmode || phy->rev >= 2) {
3614 b43_phy_write(dev, B43_PHY_RFOVERVAL, 3641 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3615 radio2050_rfover_val(dev, 3642 radio2050_rfover_val(dev,
@@ -3635,7 +3662,7 @@ u16 b43_radio_init2050(struct b43_wldev *dev)
3635 b43_phy_write(dev, B43_PHY_PGACTL, 0xFFF0); 3662 b43_phy_write(dev, B43_PHY_PGACTL, 0xFFF0);
3636 udelay(20); 3663 udelay(20);
3637 tmp1 += b43_phy_read(dev, B43_PHY_LO_LEAKAGE); 3664 tmp1 += b43_phy_read(dev, B43_PHY_LO_LEAKAGE);
3638 b43_phy_write(dev, B43_PHY_BASE(0x58), 0); 3665 b43_phy_write(dev, B43_PHY_CCK(0x58), 0);
3639 if (phy->gmode || phy->rev >= 2) { 3666 if (phy->gmode || phy->rev >= 2) {
3640 b43_phy_write(dev, B43_PHY_RFOVERVAL, 3667 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3641 radio2050_rfover_val(dev, 3668 radio2050_rfover_val(dev,
@@ -3646,7 +3673,7 @@ u16 b43_radio_init2050(struct b43_wldev *dev)
3646 } 3673 }
3647 udelay(10); 3674 udelay(10);
3648 3675
3649 b43_phy_write(dev, B43_PHY_BASE(0x58), 0); 3676 b43_phy_write(dev, B43_PHY_CCK(0x58), 0);
3650 tmp1++; 3677 tmp1++;
3651 tmp1 >>= 9; 3678 tmp1 >>= 9;
3652 3679
@@ -3655,9 +3682,9 @@ u16 b43_radio_init2050(struct b43_wldev *dev)
3655 b43_radio_write16(dev, 0x78, radio78); 3682 b43_radio_write16(dev, 0x78, radio78);
3656 udelay(10); 3683 udelay(10);
3657 for (j = 0; j < 16; j++) { 3684 for (j = 0; j < 16; j++) {
3658 b43_phy_write(dev, B43_PHY_BASE(0x5A), 0x0D80); 3685 b43_phy_write(dev, B43_PHY_CCK(0x5A), 0x0D80);
3659 b43_phy_write(dev, B43_PHY_BASE(0x59), 0xC810); 3686 b43_phy_write(dev, B43_PHY_CCK(0x59), 0xC810);
3660 b43_phy_write(dev, B43_PHY_BASE(0x58), 0x000D); 3687 b43_phy_write(dev, B43_PHY_CCK(0x58), 0x000D);
3661 if (phy->gmode || phy->rev >= 2) { 3688 if (phy->gmode || phy->rev >= 2) {
3662 b43_phy_write(dev, B43_PHY_RFOVERVAL, 3689 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3663 radio2050_rfover_val(dev, 3690 radio2050_rfover_val(dev,
@@ -3686,7 +3713,7 @@ u16 b43_radio_init2050(struct b43_wldev *dev)
3686 b43_phy_write(dev, B43_PHY_PGACTL, 0xFFF0); 3713 b43_phy_write(dev, B43_PHY_PGACTL, 0xFFF0);
3687 udelay(10); 3714 udelay(10);
3688 tmp2 += b43_phy_read(dev, B43_PHY_LO_LEAKAGE); 3715 tmp2 += b43_phy_read(dev, B43_PHY_LO_LEAKAGE);
3689 b43_phy_write(dev, B43_PHY_BASE(0x58), 0); 3716 b43_phy_write(dev, B43_PHY_CCK(0x58), 0);
3690 if (phy->gmode || phy->rev >= 2) { 3717 if (phy->gmode || phy->rev >= 2) {
3691 b43_phy_write(dev, B43_PHY_RFOVERVAL, 3718 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3692 radio2050_rfover_val(dev, 3719 radio2050_rfover_val(dev,
@@ -3707,16 +3734,16 @@ u16 b43_radio_init2050(struct b43_wldev *dev)
3707 b43_radio_write16(dev, 0x51, sav.radio_51); 3734 b43_radio_write16(dev, 0x51, sav.radio_51);
3708 b43_radio_write16(dev, 0x52, sav.radio_52); 3735 b43_radio_write16(dev, 0x52, sav.radio_52);
3709 b43_radio_write16(dev, 0x43, sav.radio_43); 3736 b43_radio_write16(dev, 0x43, sav.radio_43);
3710 b43_phy_write(dev, B43_PHY_BASE(0x5A), sav.phy_base_5A); 3737 b43_phy_write(dev, B43_PHY_CCK(0x5A), sav.phy_cck_5A);
3711 b43_phy_write(dev, B43_PHY_BASE(0x59), sav.phy_base_59); 3738 b43_phy_write(dev, B43_PHY_CCK(0x59), sav.phy_cck_59);
3712 b43_phy_write(dev, B43_PHY_BASE(0x58), sav.phy_base_58); 3739 b43_phy_write(dev, B43_PHY_CCK(0x58), sav.phy_cck_58);
3713 b43_write16(dev, 0x3E6, sav.reg_3E6); 3740 b43_write16(dev, 0x3E6, sav.reg_3E6);
3714 if (phy->analog != 0) 3741 if (phy->analog != 0)
3715 b43_write16(dev, 0x3F4, sav.reg_3F4); 3742 b43_write16(dev, 0x3F4, sav.reg_3F4);
3716 b43_phy_write(dev, B43_PHY_SYNCCTL, sav.phy_syncctl); 3743 b43_phy_write(dev, B43_PHY_SYNCCTL, sav.phy_syncctl);
3717 b43_synth_pu_workaround(dev, phy->channel); 3744 b43_synth_pu_workaround(dev, phy->channel);
3718 if (phy->type == B43_PHYTYPE_B) { 3745 if (phy->type == B43_PHYTYPE_B) {
3719 b43_phy_write(dev, B43_PHY_BASE(0x30), sav.phy_base_30); 3746 b43_phy_write(dev, B43_PHY_CCK(0x30), sav.phy_cck_30);
3720 b43_write16(dev, 0x3EC, sav.reg_3EC); 3747 b43_write16(dev, 0x3EC, sav.reg_3EC);
3721 } else if (phy->gmode) { 3748 } else if (phy->gmode) {
3722 b43_write16(dev, B43_MMIO_PHY_RADIO, 3749 b43_write16(dev, B43_MMIO_PHY_RADIO,
diff --git a/drivers/net/wireless/b43/phy.h b/drivers/net/wireless/b43/phy.h
index 5d09fb13b89..4ee01d534ba 100644
--- a/drivers/net/wireless/b43/phy.h
+++ b/drivers/net/wireless/b43/phy.h
@@ -9,17 +9,21 @@ struct b43_phy;
9/*** PHY Registers ***/ 9/*** PHY Registers ***/
10 10
11/* Routing */ 11/* Routing */
12#define B43_PHYROUTE_OFDM_GPHY 0x0400 /* OFDM register routing for G-PHYs */ 12#define B43_PHYROUTE 0x0C00 /* PHY register routing bits mask */
13#define B43_PHYROUTE_EXT_GPHY 0x0800 /* Extended G-PHY registers */ 13#define B43_PHYROUTE_BASE 0x0000 /* Base registers */
14#define B43_PHYROUTE_N_BMODE 0x3000 /* N-PHY BMODE registers */ 14#define B43_PHYROUTE_OFDM_GPHY 0x0400 /* OFDM register routing for G-PHYs */
15 15#define B43_PHYROUTE_EXT_GPHY 0x0800 /* Extended G-PHY registers */
16/* Base registers. */ 16#define B43_PHYROUTE_N_BMODE 0x0C00 /* N-PHY BMODE registers */
17#define B43_PHY_BASE(reg) (reg) 17
18/* CCK (B-PHY) registers. */
19#define B43_PHY_CCK(reg) ((reg) | B43_PHYROUTE_BASE)
18/* N-PHY registers. */ 20/* N-PHY registers. */
19#define B43_PHY_N(reg) (reg) 21#define B43_PHY_N(reg) ((reg) | B43_PHYROUTE_BASE)
20/* OFDM (A) registers of a G-PHY */ 22/* N-PHY BMODE registers. */
23#define B43_PHY_N_BMODE(reg) ((reg) | B43_PHYROUTE_N_BMODE)
24/* OFDM (A-PHY) registers. */
21#define B43_PHY_OFDM(reg) ((reg) | B43_PHYROUTE_OFDM_GPHY) 25#define B43_PHY_OFDM(reg) ((reg) | B43_PHYROUTE_OFDM_GPHY)
22/* Extended G-PHY registers */ 26/* Extended G-PHY registers. */
23#define B43_PHY_EXTG(reg) ((reg) | B43_PHYROUTE_EXT_GPHY) 27#define B43_PHY_EXTG(reg) ((reg) | B43_PHYROUTE_EXT_GPHY)
24 28
25/* OFDM (A) PHY Registers */ 29/* OFDM (A) PHY Registers */
@@ -79,20 +83,20 @@ struct b43_phy;
79#define B43_PHY_GAIN_LTBASE B43_PHY_OFDM(0x3C0) /* Gain lookup table base */ 83#define B43_PHY_GAIN_LTBASE B43_PHY_OFDM(0x3C0) /* Gain lookup table base */
80 84
81/* CCK (B) PHY Registers */ 85/* CCK (B) PHY Registers */
82#define B43_PHY_VERSION_CCK B43_PHY_BASE(0x00) /* Versioning register for B-PHY */ 86#define B43_PHY_VERSION_CCK B43_PHY_CCK(0x00) /* Versioning register for B-PHY */
83#define B43_PHY_CCKBBANDCFG B43_PHY_BASE(0x01) /* Contains antenna 0/1 control bit */ 87#define B43_PHY_CCKBBANDCFG B43_PHY_CCK(0x01) /* Contains antenna 0/1 control bit */
84#define B43_PHY_PGACTL B43_PHY_BASE(0x15) /* PGA control */ 88#define B43_PHY_PGACTL B43_PHY_CCK(0x15) /* PGA control */
85#define B43_PHY_PGACTL_LPF 0x1000 /* Low pass filter (?) */ 89#define B43_PHY_PGACTL_LPF 0x1000 /* Low pass filter (?) */
86#define B43_PHY_PGACTL_LOWBANDW 0x0040 /* Low bandwidth flag */ 90#define B43_PHY_PGACTL_LOWBANDW 0x0040 /* Low bandwidth flag */
87#define B43_PHY_PGACTL_UNKNOWN 0xEFA0 91#define B43_PHY_PGACTL_UNKNOWN 0xEFA0
88#define B43_PHY_FBCTL1 B43_PHY_BASE(0x18) /* Frequency bandwidth control 1 */ 92#define B43_PHY_FBCTL1 B43_PHY_CCK(0x18) /* Frequency bandwidth control 1 */
89#define B43_PHY_ITSSI B43_PHY_BASE(0x29) /* Idle TSSI */ 93#define B43_PHY_ITSSI B43_PHY_CCK(0x29) /* Idle TSSI */
90#define B43_PHY_LO_LEAKAGE B43_PHY_BASE(0x2D) /* Measured LO leakage */ 94#define B43_PHY_LO_LEAKAGE B43_PHY_CCK(0x2D) /* Measured LO leakage */
91#define B43_PHY_ENERGY B43_PHY_BASE(0x33) /* Energy */ 95#define B43_PHY_ENERGY B43_PHY_CCK(0x33) /* Energy */
92#define B43_PHY_SYNCCTL B43_PHY_BASE(0x35) 96#define B43_PHY_SYNCCTL B43_PHY_CCK(0x35)
93#define B43_PHY_FBCTL2 B43_PHY_BASE(0x38) /* Frequency bandwidth control 2 */ 97#define B43_PHY_FBCTL2 B43_PHY_CCK(0x38) /* Frequency bandwidth control 2 */
94#define B43_PHY_DACCTL B43_PHY_BASE(0x60) /* DAC control */ 98#define B43_PHY_DACCTL B43_PHY_CCK(0x60) /* DAC control */
95#define B43_PHY_RCCALOVER B43_PHY_BASE(0x78) /* RC calibration override */ 99#define B43_PHY_RCCALOVER B43_PHY_CCK(0x78) /* RC calibration override */
96 100
97/* Extended G-PHY Registers */ 101/* Extended G-PHY Registers */
98#define B43_PHY_CLASSCTL B43_PHY_EXTG(0x02) /* Classify control */ 102#define B43_PHY_CLASSCTL B43_PHY_EXTG(0x02) /* Classify control */
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-21 21:49:00 -0400