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-rw-r--r--include/linux/mfd/wm8994/registers.h96
-rw-r--r--sound/soc/codecs/wm8994-tables.c12
2 files changed, 102 insertions, 6 deletions
diff --git a/include/linux/mfd/wm8994/registers.h b/include/linux/mfd/wm8994/registers.h
index 83a9caec0e4..8317b19a497 100644
--- a/include/linux/mfd/wm8994/registers.h
+++ b/include/linux/mfd/wm8994/registers.h
@@ -95,11 +95,15 @@
95#define WM8994_FLL1_CONTROL_3 0x222 95#define WM8994_FLL1_CONTROL_3 0x222
96#define WM8994_FLL1_CONTROL_4 0x223 96#define WM8994_FLL1_CONTROL_4 0x223
97#define WM8994_FLL1_CONTROL_5 0x224 97#define WM8994_FLL1_CONTROL_5 0x224
98#define WM8958_FLL1_EFS_1 0x226
99#define WM8958_FLL1_EFS_2 0x227
98#define WM8994_FLL2_CONTROL_1 0x240 100#define WM8994_FLL2_CONTROL_1 0x240
99#define WM8994_FLL2_CONTROL_2 0x241 101#define WM8994_FLL2_CONTROL_2 0x241
100#define WM8994_FLL2_CONTROL_3 0x242 102#define WM8994_FLL2_CONTROL_3 0x242
101#define WM8994_FLL2_CONTROL_4 0x243 103#define WM8994_FLL2_CONTROL_4 0x243
102#define WM8994_FLL2_CONTROL_5 0x244 104#define WM8994_FLL2_CONTROL_5 0x244
105#define WM8958_FLL2_EFS_1 0x246
106#define WM8958_FLL2_EFS_2 0x247
103#define WM8994_AIF1_CONTROL_1 0x300 107#define WM8994_AIF1_CONTROL_1 0x300
104#define WM8994_AIF1_CONTROL_2 0x301 108#define WM8994_AIF1_CONTROL_2 0x301
105#define WM8994_AIF1_MASTER_SLAVE 0x302 109#define WM8994_AIF1_MASTER_SLAVE 0x302
@@ -116,6 +120,7 @@
116#define WM8994_AIF2DAC_LRCLK 0x315 120#define WM8994_AIF2DAC_LRCLK 0x315
117#define WM8994_AIF2DAC_DATA 0x316 121#define WM8994_AIF2DAC_DATA 0x316
118#define WM8994_AIF2ADC_DATA 0x317 122#define WM8994_AIF2ADC_DATA 0x317
123#define WM1811_AIF2TX_CONTROL 0x318
119#define WM8958_AIF3_CONTROL_1 0x320 124#define WM8958_AIF3_CONTROL_1 0x320
120#define WM8958_AIF3_CONTROL_2 0x321 125#define WM8958_AIF3_CONTROL_2 0x321
121#define WM8958_AIF3DAC_DATA 0x322 126#define WM8958_AIF3DAC_DATA 0x322
@@ -166,6 +171,7 @@
166#define WM8994_AIF1_DAC1_EQ_BAND_5_A 0x491 171#define WM8994_AIF1_DAC1_EQ_BAND_5_A 0x491
167#define WM8994_AIF1_DAC1_EQ_BAND_5_B 0x492 172#define WM8994_AIF1_DAC1_EQ_BAND_5_B 0x492
168#define WM8994_AIF1_DAC1_EQ_BAND_5_PG 0x493 173#define WM8994_AIF1_DAC1_EQ_BAND_5_PG 0x493
174#define WM8994_AIF1_DAC1_EQ_BAND_1_C 0x494
169#define WM8994_AIF1_DAC2_EQ_GAINS_1 0x4A0 175#define WM8994_AIF1_DAC2_EQ_GAINS_1 0x4A0
170#define WM8994_AIF1_DAC2_EQ_GAINS_2 0x4A1 176#define WM8994_AIF1_DAC2_EQ_GAINS_2 0x4A1
171#define WM8994_AIF1_DAC2_EQ_BAND_1_A 0x4A2 177#define WM8994_AIF1_DAC2_EQ_BAND_1_A 0x4A2
@@ -186,6 +192,7 @@
186#define WM8994_AIF1_DAC2_EQ_BAND_5_A 0x4B1 192#define WM8994_AIF1_DAC2_EQ_BAND_5_A 0x4B1
187#define WM8994_AIF1_DAC2_EQ_BAND_5_B 0x4B2 193#define WM8994_AIF1_DAC2_EQ_BAND_5_B 0x4B2
188#define WM8994_AIF1_DAC2_EQ_BAND_5_PG 0x4B3 194#define WM8994_AIF1_DAC2_EQ_BAND_5_PG 0x4B3
195#define WM8994_AIF1_DAC2_EQ_BAND_1_C 0x4B4
189#define WM8994_AIF2_ADC_LEFT_VOLUME 0x500 196#define WM8994_AIF2_ADC_LEFT_VOLUME 0x500
190#define WM8994_AIF2_ADC_RIGHT_VOLUME 0x501 197#define WM8994_AIF2_ADC_RIGHT_VOLUME 0x501
191#define WM8994_AIF2_DAC_LEFT_VOLUME 0x502 198#define WM8994_AIF2_DAC_LEFT_VOLUME 0x502
@@ -219,6 +226,7 @@
219#define WM8994_AIF2_EQ_BAND_5_A 0x591 226#define WM8994_AIF2_EQ_BAND_5_A 0x591
220#define WM8994_AIF2_EQ_BAND_5_B 0x592 227#define WM8994_AIF2_EQ_BAND_5_B 0x592
221#define WM8994_AIF2_EQ_BAND_5_PG 0x593 228#define WM8994_AIF2_EQ_BAND_5_PG 0x593
229#define WM8994_AIF2_EQ_BAND_1_C 0x594
222#define WM8994_DAC1_MIXER_VOLUMES 0x600 230#define WM8994_DAC1_MIXER_VOLUMES 0x600
223#define WM8994_DAC1_LEFT_MIXER_ROUTING 0x601 231#define WM8994_DAC1_LEFT_MIXER_ROUTING 0x601
224#define WM8994_DAC1_RIGHT_MIXER_ROUTING 0x602 232#define WM8994_DAC1_RIGHT_MIXER_ROUTING 0x602
@@ -264,7 +272,43 @@
264#define WM8958_DSP2_RELEASETIME 0xA03 272#define WM8958_DSP2_RELEASETIME 0xA03
265#define WM8958_DSP2_VERMAJMIN 0xA04 273#define WM8958_DSP2_VERMAJMIN 0xA04
266#define WM8958_DSP2_VERBUILD 0xA05 274#define WM8958_DSP2_VERBUILD 0xA05
275#define WM8958_DSP2_TESTREG 0xA06
276#define WM8958_DSP2_XORREG 0xA07
277#define WM8958_DSP2_SHIFTMAXX 0xA08
278#define WM8958_DSP2_SHIFTMAXY 0xA09
279#define WM8958_DSP2_SHIFTMAXZ 0xA0A
280#define WM8958_DSP2_SHIFTMAXEXTLO 0xA0B
281#define WM8958_DSP2_AESSELECT 0xA0C
267#define WM8958_DSP2_EXECCONTROL 0xA0D 282#define WM8958_DSP2_EXECCONTROL 0xA0D
283#define WM8958_DSP2_SAMPLEBREAK 0xA0E
284#define WM8958_DSP2_COUNTBREAK 0xA0F
285#define WM8958_DSP2_INTSTATUS 0xA10
286#define WM8958_DSP2_EVENTSTATUS 0xA11
287#define WM8958_DSP2_INTMASK 0xA12
288#define WM8958_DSP2_CONFIGDWIDTH 0xA13
289#define WM8958_DSP2_CONFIGINSTR 0xA14
290#define WM8958_DSP2_CONFIGDMEM 0xA15
291#define WM8958_DSP2_CONFIGDELAYS 0xA16
292#define WM8958_DSP2_CONFIGNUMIO 0xA17
293#define WM8958_DSP2_CONFIGEXTDEPTH 0xA18
294#define WM8958_DSP2_CONFIGMULTIPLIER 0xA19
295#define WM8958_DSP2_CONFIGCTRLDWIDTH 0xA1A
296#define WM8958_DSP2_CONFIGPIPELINE 0xA1B
297#define WM8958_DSP2_SHIFTMAXEXTHI 0xA1C
298#define WM8958_DSP2_SWVERSIONREG 0xA1D
299#define WM8958_DSP2_CONFIGXMEM 0xA1E
300#define WM8958_DSP2_CONFIGYMEM 0xA1F
301#define WM8958_DSP2_CONFIGZMEM 0xA20
302#define WM8958_FW_BUILD_1 0x2000
303#define WM8958_FW_BUILD_0 0x2001
304#define WM8958_FW_ID_1 0x2002
305#define WM8958_FW_ID_0 0x2003
306#define WM8958_FW_MAJOR_1 0x2004
307#define WM8958_FW_MAJOR_0 0x2005
308#define WM8958_FW_MINOR_1 0x2006
309#define WM8958_FW_MINOR_0 0x2007
310#define WM8958_FW_PATCH_1 0x2008
311#define WM8958_FW_PATCH_0 0x2009
268#define WM8958_MBC_BAND_2_LOWER_CUTOFF_C1_1 0x2200 312#define WM8958_MBC_BAND_2_LOWER_CUTOFF_C1_1 0x2200
269#define WM8958_MBC_BAND_2_LOWER_CUTOFF_C1_2 0x2201 313#define WM8958_MBC_BAND_2_LOWER_CUTOFF_C1_2 0x2201
270#define WM8958_MBC_BAND_2_LOWER_CUTOFF_C2_1 0x2202 314#define WM8958_MBC_BAND_2_LOWER_CUTOFF_C2_1 0x2202
@@ -333,6 +377,14 @@
333#define WM8958_MBC_B2_PG2_2 0x242D 377#define WM8958_MBC_B2_PG2_2 0x242D
334#define WM8958_MBC_B1_PG2_1 0x242E 378#define WM8958_MBC_B1_PG2_1 0x242E
335#define WM8958_MBC_B1_PG2_2 0x242F 379#define WM8958_MBC_B1_PG2_2 0x242F
380#define WM8958_MBC_CROSSOVER_1 0x2600
381#define WM8958_MBC_CROSSOVER_2 0x2601
382#define WM8958_MBC_HPF_1 0x2602
383#define WM8958_MBC_HPF_2 0x2603
384#define WM8958_MBC_LPF_1 0x2606
385#define WM8958_MBC_LPF_2 0x2607
386#define WM8958_MBC_RMS_LIMIT_1 0x260A
387#define WM8958_MBC_RMS_LIMIT_2 0x260B
336#define WM8994_WRITE_SEQUENCER_0 0x3000 388#define WM8994_WRITE_SEQUENCER_0 0x3000
337#define WM8994_WRITE_SEQUENCER_1 0x3001 389#define WM8994_WRITE_SEQUENCER_1 0x3001
338#define WM8994_WRITE_SEQUENCER_2 0x3002 390#define WM8994_WRITE_SEQUENCER_2 0x3002
@@ -2389,6 +2441,10 @@
2389/* 2441/*
2390 * R548 (0x224) - FLL1 Control (5) 2442 * R548 (0x224) - FLL1 Control (5)
2391 */ 2443 */
2444#define WM8958_FLL1_BYP 0x8000 /* FLL1_BYP */
2445#define WM8958_FLL1_BYP_MASK 0x8000 /* FLL1_BYP */
2446#define WM8958_FLL1_BYP_SHIFT 15 /* FLL1_BYP */
2447#define WM8958_FLL1_BYP_WIDTH 1 /* FLL1_BYP */
2392#define WM8994_FLL1_FRC_NCO_VAL_MASK 0x1F80 /* FLL1_FRC_NCO_VAL - [12:7] */ 2448#define WM8994_FLL1_FRC_NCO_VAL_MASK 0x1F80 /* FLL1_FRC_NCO_VAL - [12:7] */
2393#define WM8994_FLL1_FRC_NCO_VAL_SHIFT 7 /* FLL1_FRC_NCO_VAL - [12:7] */ 2449#define WM8994_FLL1_FRC_NCO_VAL_SHIFT 7 /* FLL1_FRC_NCO_VAL - [12:7] */
2394#define WM8994_FLL1_FRC_NCO_VAL_WIDTH 6 /* FLL1_FRC_NCO_VAL - [12:7] */ 2450#define WM8994_FLL1_FRC_NCO_VAL_WIDTH 6 /* FLL1_FRC_NCO_VAL - [12:7] */
@@ -2404,6 +2460,24 @@
2404#define WM8994_FLL1_REFCLK_SRC_WIDTH 2 /* FLL1_REFCLK_SRC - [1:0] */ 2460#define WM8994_FLL1_REFCLK_SRC_WIDTH 2 /* FLL1_REFCLK_SRC - [1:0] */
2405 2461
2406/* 2462/*
2463 * R550 (0x226) - FLL1 EFS 1
2464 */
2465#define WM8958_FLL1_LAMBDA_MASK 0xFFFF /* FLL1_LAMBDA - [15:0] */
2466#define WM8958_FLL1_LAMBDA_SHIFT 0 /* FLL1_LAMBDA - [15:0] */
2467#define WM8958_FLL1_LAMBDA_WIDTH 16 /* FLL1_LAMBDA - [15:0] */
2468
2469/*
2470 * R551 (0x227) - FLL1 EFS 2
2471 */
2472#define WM8958_FLL1_LFSR_SEL_MASK 0x0006 /* FLL1_LFSR_SEL - [2:1] */
2473#define WM8958_FLL1_LFSR_SEL_SHIFT 1 /* FLL1_LFSR_SEL - [2:1] */
2474#define WM8958_FLL1_LFSR_SEL_WIDTH 2 /* FLL1_LFSR_SEL - [2:1] */
2475#define WM8958_FLL1_EFS_ENA 0x0001 /* FLL1_EFS_ENA */
2476#define WM8958_FLL1_EFS_ENA_MASK 0x0001 /* FLL1_EFS_ENA */
2477#define WM8958_FLL1_EFS_ENA_SHIFT 0 /* FLL1_EFS_ENA */
2478#define WM8958_FLL1_EFS_ENA_WIDTH 1 /* FLL1_EFS_ENA */
2479
2480/*
2407 * R576 (0x240) - FLL2 Control (1) 2481 * R576 (0x240) - FLL2 Control (1)
2408 */ 2482 */
2409#define WM8994_FLL2_FRAC 0x0004 /* FLL2_FRAC */ 2483#define WM8994_FLL2_FRAC 0x0004 /* FLL2_FRAC */
@@ -2452,6 +2526,10 @@
2452/* 2526/*
2453 * R580 (0x244) - FLL2 Control (5) 2527 * R580 (0x244) - FLL2 Control (5)
2454 */ 2528 */
2529#define WM8958_FLL2_BYP 0x8000 /* FLL2_BYP */
2530#define WM8958_FLL2_BYP_MASK 0x8000 /* FLL2_BYP */
2531#define WM8958_FLL2_BYP_SHIFT 15 /* FLL2_BYP */
2532#define WM8958_FLL2_BYP_WIDTH 1 /* FLL2_BYP */
2455#define WM8994_FLL2_FRC_NCO_VAL_MASK 0x1F80 /* FLL2_FRC_NCO_VAL - [12:7] */ 2533#define WM8994_FLL2_FRC_NCO_VAL_MASK 0x1F80 /* FLL2_FRC_NCO_VAL - [12:7] */
2456#define WM8994_FLL2_FRC_NCO_VAL_SHIFT 7 /* FLL2_FRC_NCO_VAL - [12:7] */ 2534#define WM8994_FLL2_FRC_NCO_VAL_SHIFT 7 /* FLL2_FRC_NCO_VAL - [12:7] */
2457#define WM8994_FLL2_FRC_NCO_VAL_WIDTH 6 /* FLL2_FRC_NCO_VAL - [12:7] */ 2535#define WM8994_FLL2_FRC_NCO_VAL_WIDTH 6 /* FLL2_FRC_NCO_VAL - [12:7] */
@@ -2467,6 +2545,24 @@
2467#define WM8994_FLL2_REFCLK_SRC_WIDTH 2 /* FLL2_REFCLK_SRC - [1:0] */ 2545#define WM8994_FLL2_REFCLK_SRC_WIDTH 2 /* FLL2_REFCLK_SRC - [1:0] */
2468 2546
2469/* 2547/*
2548 * R582 (0x246) - FLL2 EFS 1
2549 */
2550#define WM8958_FLL2_LAMBDA_MASK 0xFFFF /* FLL2_LAMBDA - [15:0] */
2551#define WM8958_FLL2_LAMBDA_SHIFT 0 /* FLL2_LAMBDA - [15:0] */
2552#define WM8958_FLL2_LAMBDA_WIDTH 16 /* FLL2_LAMBDA - [15:0] */
2553
2554/*
2555 * R583 (0x247) - FLL2 EFS 2
2556 */
2557#define WM8958_FLL2_LFSR_SEL_MASK 0x0006 /* FLL2_LFSR_SEL - [2:1] */
2558#define WM8958_FLL2_LFSR_SEL_SHIFT 1 /* FLL2_LFSR_SEL - [2:1] */
2559#define WM8958_FLL2_LFSR_SEL_WIDTH 2 /* FLL2_LFSR_SEL - [2:1] */
2560#define WM8958_FLL2_EFS_ENA 0x0001 /* FLL2_EFS_ENA */
2561#define WM8958_FLL2_EFS_ENA_MASK 0x0001 /* FLL2_EFS_ENA */
2562#define WM8958_FLL2_EFS_ENA_SHIFT 0 /* FLL2_EFS_ENA */
2563#define WM8958_FLL2_EFS_ENA_WIDTH 1 /* FLL2_EFS_ENA */
2564
2565/*
2470 * R768 (0x300) - AIF1 Control (1) 2566 * R768 (0x300) - AIF1 Control (1)
2471 */ 2567 */
2472#define WM8994_AIF1ADCL_SRC 0x8000 /* AIF1ADCL_SRC */ 2568#define WM8994_AIF1ADCL_SRC 0x8000 /* AIF1ADCL_SRC */
diff --git a/sound/soc/codecs/wm8994-tables.c b/sound/soc/codecs/wm8994-tables.c
index df5a8b9a250..6ed19d9e745 100644
--- a/sound/soc/codecs/wm8994-tables.c
+++ b/sound/soc/codecs/wm8994-tables.c
@@ -78,7 +78,7 @@ const struct wm8994_access_mask wm8994_access_masks[WM8994_CACHE_SIZE] = {
78 { 0x0000, 0x0000 }, /* R74 */ 78 { 0x0000, 0x0000 }, /* R74 */
79 { 0x0000, 0x0000 }, /* R75 */ 79 { 0x0000, 0x0000 }, /* R75 */
80 { 0x8000, 0x8000 }, /* R76 - Charge Pump (1) */ 80 { 0x8000, 0x8000 }, /* R76 - Charge Pump (1) */
81 { 0x0000, 0x0000 }, /* R77 */ 81 { 0x8000, 0x8000 }, /* R77 - Charge Pump (2) */
82 { 0x0000, 0x0000 }, /* R78 */ 82 { 0x0000, 0x0000 }, /* R78 */
83 { 0x0000, 0x0000 }, /* R79 */ 83 { 0x0000, 0x0000 }, /* R79 */
84 { 0x0000, 0x0000 }, /* R80 */ 84 { 0x0000, 0x0000 }, /* R80 */
@@ -1651,7 +1651,7 @@ const u16 wm8994_reg_defaults[WM8994_CACHE_SIZE] = {
1651 0x0000, /* R74 */ 1651 0x0000, /* R74 */
1652 0x0000, /* R75 */ 1652 0x0000, /* R75 */
1653 0x1F25, /* R76 - Charge Pump (1) */ 1653 0x1F25, /* R76 - Charge Pump (1) */
1654 0x0000, /* R77 */ 1654 0xAB19, /* R77 - Charge Pump (2) */
1655 0x0000, /* R78 */ 1655 0x0000, /* R78 */
1656 0x0000, /* R79 */ 1656 0x0000, /* R79 */
1657 0x0000, /* R80 */ 1657 0x0000, /* R80 */
@@ -2124,8 +2124,8 @@ const u16 wm8994_reg_defaults[WM8994_CACHE_SIZE] = {
2124 0x0000, /* R547 - FLL1 Control (4) */ 2124 0x0000, /* R547 - FLL1 Control (4) */
2125 0x0C80, /* R548 - FLL1 Control (5) */ 2125 0x0C80, /* R548 - FLL1 Control (5) */
2126 0x0000, /* R549 */ 2126 0x0000, /* R549 */
2127 0x0000, /* R550 */ 2127 0x0000, /* R550 - FLL1 EFS 1 */
2128 0x0000, /* R551 */ 2128 0x0006, /* R551 - FLL1 EFS 2 */
2129 0x0000, /* R552 */ 2129 0x0000, /* R552 */
2130 0x0000, /* R553 */ 2130 0x0000, /* R553 */
2131 0x0000, /* R554 */ 2131 0x0000, /* R554 */
@@ -2156,8 +2156,8 @@ const u16 wm8994_reg_defaults[WM8994_CACHE_SIZE] = {
2156 0x0000, /* R579 - FLL2 Control (4) */ 2156 0x0000, /* R579 - FLL2 Control (4) */
2157 0x0C80, /* R580 - FLL2 Control (5) */ 2157 0x0C80, /* R580 - FLL2 Control (5) */
2158 0x0000, /* R581 */ 2158 0x0000, /* R581 */
2159 0x0000, /* R582 */ 2159 0x0000, /* R582 - FLL2 EFS 1 */
2160 0x0000, /* R583 */ 2160 0x0006, /* R583 - FLL2 EFS 2 */
2161 0x0000, /* R584 */ 2161 0x0000, /* R584 */
2162 0x0000, /* R585 */ 2162 0x0000, /* R585 */
2163 0x0000, /* R586 */ 2163 0x0000, /* R586 */