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-rw-r--r--arch/sh/Kconfig1
-rw-r--r--arch/sh/boards/Kconfig5
-rw-r--r--arch/sh/boards/mach-dreamcast/irq.c32
-rw-r--r--arch/sh/boards/mach-se/7343/irq.c129
-rw-r--r--arch/sh/boards/mach-se/7343/setup.c10
-rw-r--r--arch/sh/boards/mach-se/7722/irq.c131
-rw-r--r--arch/sh/boards/mach-se/7722/setup.c6
-rw-r--r--arch/sh/boards/mach-se/7724/irq.c36
-rw-r--r--arch/sh/boards/mach-x3proto/gpio.c57
-rw-r--r--arch/sh/cchips/hd6446x/hd64461.c33
-rw-r--r--arch/sh/include/asm/bug.h4
-rw-r--r--arch/sh/include/asm/kdebug.h2
-rw-r--r--arch/sh/include/mach-se/mach/se7343.h7
-rw-r--r--arch/sh/include/mach-se/mach/se7722.h10
-rw-r--r--arch/sh/kernel/cpu/sh5/unwind.c63
-rw-r--r--arch/sh/kernel/dumpstack.c58
-rw-r--r--arch/sh/kernel/irq.c10
-rw-r--r--arch/sh/kernel/traps.c71
-rw-r--r--arch/sh/kernel/traps_32.c121
-rw-r--r--arch/sh/kernel/traps_64.c589
-rw-r--r--arch/sh/lib64/Makefile2
-rw-r--r--arch/sh/lib64/dbg.c248
-rw-r--r--arch/sh/mm/tlb-sh5.c2
-rw-r--r--drivers/sh/Kconfig1
-rw-r--r--drivers/sh/Makefile3
-rw-r--r--drivers/sh/clk/cpg.c333
-rw-r--r--drivers/sh/intc/Makefile2
-rw-r--r--drivers/sh/intc/dynamic.c57
-rw-r--r--drivers/sh/intc/virq.c4
-rw-r--r--drivers/sh/pfc.c739
-rw-r--r--drivers/sh/pfc/Kconfig26
-rw-r--r--drivers/sh/pfc/Makefile3
-rw-r--r--drivers/sh/pfc/core.c572
-rw-r--r--drivers/sh/pfc/gpio.c239
-rw-r--r--drivers/sh/pfc/pinctrl.c530
-rw-r--r--include/linux/sh_clk.h21
-rw-r--r--include/linux/sh_pfc.h65
37 files changed, 2244 insertions, 1978 deletions
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index 31d9db7913e..a24595d83ad 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -60,6 +60,7 @@ config SUPERH32
60 60
61config SUPERH64 61config SUPERH64
62 def_bool ARCH = "sh64" 62 def_bool ARCH = "sh64"
63 select KALLSYMS
63 64
64config ARCH_DEFCONFIG 65config ARCH_DEFCONFIG
65 string 66 string
diff --git a/arch/sh/boards/Kconfig b/arch/sh/boards/Kconfig
index 1f56b35d324..7048c03490d 100644
--- a/arch/sh/boards/Kconfig
+++ b/arch/sh/boards/Kconfig
@@ -44,6 +44,8 @@ config SH_7721_SOLUTION_ENGINE
44config SH_7722_SOLUTION_ENGINE 44config SH_7722_SOLUTION_ENGINE
45 bool "SolutionEngine7722" 45 bool "SolutionEngine7722"
46 select SOLUTION_ENGINE 46 select SOLUTION_ENGINE
47 select GENERIC_IRQ_CHIP
48 select IRQ_DOMAIN
47 depends on CPU_SUBTYPE_SH7722 49 depends on CPU_SUBTYPE_SH7722
48 help 50 help
49 Select 7722 SolutionEngine if configuring for a Hitachi SH772 51 Select 7722 SolutionEngine if configuring for a Hitachi SH772
@@ -80,6 +82,8 @@ config SH_7780_SOLUTION_ENGINE
80config SH_7343_SOLUTION_ENGINE 82config SH_7343_SOLUTION_ENGINE
81 bool "SolutionEngine7343" 83 bool "SolutionEngine7343"
82 select SOLUTION_ENGINE 84 select SOLUTION_ENGINE
85 select GENERIC_IRQ_CHIP
86 select IRQ_DOMAIN
83 depends on CPU_SUBTYPE_SH7343 87 depends on CPU_SUBTYPE_SH7343
84 help 88 help
85 Select 7343 SolutionEngine if configuring for a Hitachi 89 Select 7343 SolutionEngine if configuring for a Hitachi
@@ -295,6 +299,7 @@ config SH_X3PROTO
295 bool "SH-X3 Prototype board" 299 bool "SH-X3 Prototype board"
296 depends on CPU_SUBTYPE_SHX3 300 depends on CPU_SUBTYPE_SHX3
297 select NO_IOPORT if !PCI 301 select NO_IOPORT if !PCI
302 select IRQ_DOMAIN
298 303
299config SH_MAGIC_PANEL_R2 304config SH_MAGIC_PANEL_R2
300 bool "Magic Panel R2" 305 bool "Magic Panel R2"
diff --git a/arch/sh/boards/mach-dreamcast/irq.c b/arch/sh/boards/mach-dreamcast/irq.c
index f63d323f411..2789647abeb 100644
--- a/arch/sh/boards/mach-dreamcast/irq.c
+++ b/arch/sh/boards/mach-dreamcast/irq.c
@@ -8,10 +8,11 @@
8 * This file is part of the LinuxDC project (www.linuxdc.org) 8 * This file is part of the LinuxDC project (www.linuxdc.org)
9 * Released under the terms of the GNU GPL v2.0 9 * Released under the terms of the GNU GPL v2.0
10 */ 10 */
11
12#include <linux/irq.h> 11#include <linux/irq.h>
13#include <linux/io.h> 12#include <linux/io.h>
14#include <asm/irq.h> 13#include <linux/irq.h>
14#include <linux/export.h>
15#include <linux/err.h>
15#include <mach/sysasic.h> 16#include <mach/sysasic.h>
16 17
17/* 18/*
@@ -141,26 +142,15 @@ int systemasic_irq_demux(int irq)
141 142
142void systemasic_irq_init(void) 143void systemasic_irq_init(void)
143{ 144{
144 int i, nid = cpu_to_node(boot_cpu_data); 145 int irq_base, i;
145
146 /* Assign all virtual IRQs to the System ASIC int. handler */
147 for (i = HW_EVENT_IRQ_BASE; i < HW_EVENT_IRQ_MAX; i++) {
148 unsigned int irq;
149
150 irq = create_irq_nr(i, nid);
151 if (unlikely(irq == 0)) {
152 pr_err("%s: failed hooking irq %d for systemasic\n",
153 __func__, i);
154 return;
155 }
156 146
157 if (unlikely(irq != i)) { 147 irq_base = irq_alloc_descs(HW_EVENT_IRQ_BASE, HW_EVENT_IRQ_BASE,
158 pr_err("%s: got irq %d but wanted %d, bailing.\n", 148 HW_EVENT_IRQ_MAX - HW_EVENT_IRQ_BASE, -1);
159 __func__, irq, i); 149 if (IS_ERR_VALUE(irq_base)) {
160 destroy_irq(irq); 150 pr_err("%s: failed hooking irqs\n", __func__);
161 return; 151 return;
162 } 152 }
163 153
154 for (i = HW_EVENT_IRQ_BASE; i < HW_EVENT_IRQ_MAX; i++)
164 irq_set_chip_and_handler(i, &systemasic_int, handle_level_irq); 155 irq_set_chip_and_handler(i, &systemasic_int, handle_level_irq);
165 }
166} 156}
diff --git a/arch/sh/boards/mach-se/7343/irq.c b/arch/sh/boards/mach-se/7343/irq.c
index fd45ffc4834..7646bf0486c 100644
--- a/arch/sh/boards/mach-se/7343/irq.c
+++ b/arch/sh/boards/mach-se/7343/irq.c
@@ -1,86 +1,129 @@
1/* 1/*
2 * linux/arch/sh/boards/se/7343/irq.c 2 * Hitachi UL SolutionEngine 7343 FPGA IRQ Support.
3 * 3 *
4 * Copyright (C) 2008 Yoshihiro Shimoda 4 * Copyright (C) 2008 Yoshihiro Shimoda
5 * Copyright (C) 2012 Paul Mundt
5 * 6 *
6 * Based on linux/arch/sh/boards/se/7722/irq.c 7 * Based on linux/arch/sh/boards/se/7343/irq.c
7 * Copyright (C) 2007 Nobuhiro Iwamatsu 8 * Copyright (C) 2007 Nobuhiro Iwamatsu
8 * 9 *
9 * This file is subject to the terms and conditions of the GNU General Public 10 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive 11 * License. See the file "COPYING" in the main directory of this archive
11 * for more details. 12 * for more details.
12 */ 13 */
14#define DRV_NAME "SE7343-FPGA"
15#define pr_fmt(fmt) DRV_NAME ": " fmt
16
17#define irq_reg_readl ioread16
18#define irq_reg_writel iowrite16
19
13#include <linux/init.h> 20#include <linux/init.h>
14#include <linux/irq.h> 21#include <linux/irq.h>
15#include <linux/interrupt.h> 22#include <linux/interrupt.h>
23#include <linux/irqdomain.h>
16#include <linux/io.h> 24#include <linux/io.h>
25#include <asm/sizes.h>
17#include <mach-se/mach/se7343.h> 26#include <mach-se/mach/se7343.h>
18 27
19unsigned int se7343_fpga_irq[SE7343_FPGA_IRQ_NR] = { 0, }; 28#define PA_CPLD_BASE_ADDR 0x11400000
29#define PA_CPLD_ST_REG 0x08 /* CPLD Interrupt status register */
30#define PA_CPLD_IMSK_REG 0x0a /* CPLD Interrupt mask register */
20 31
21static void disable_se7343_irq(struct irq_data *data) 32static void __iomem *se7343_irq_regs;
22{ 33struct irq_domain *se7343_irq_domain;
23 unsigned int bit = (unsigned int)irq_data_get_irq_chip_data(data);
24 __raw_writew(__raw_readw(PA_CPLD_IMSK) | 1 << bit, PA_CPLD_IMSK);
25}
26 34
27static void enable_se7343_irq(struct irq_data *data) 35static void se7343_irq_demux(unsigned int irq, struct irq_desc *desc)
28{ 36{
29 unsigned int bit = (unsigned int)irq_data_get_irq_chip_data(data); 37 struct irq_data *data = irq_get_irq_data(irq);
30 __raw_writew(__raw_readw(PA_CPLD_IMSK) & ~(1 << bit), PA_CPLD_IMSK); 38 struct irq_chip *chip = irq_data_get_irq_chip(data);
31} 39 unsigned long mask;
40 int bit;
32 41
33static struct irq_chip se7343_irq_chip __read_mostly = { 42 chip->irq_mask_ack(data);
34 .name = "SE7343-FPGA",
35 .irq_mask = disable_se7343_irq,
36 .irq_unmask = enable_se7343_irq,
37};
38 43
39static void se7343_irq_demux(unsigned int irq, struct irq_desc *desc) 44 mask = ioread16(se7343_irq_regs + PA_CPLD_ST_REG);
45
46 for_each_set_bit(bit, &mask, SE7343_FPGA_IRQ_NR)
47 generic_handle_irq(irq_linear_revmap(se7343_irq_domain, bit));
48
49 chip->irq_unmask(data);
50}
51
52static void __init se7343_domain_init(void)
40{ 53{
41 unsigned short intv = __raw_readw(PA_CPLD_ST); 54 int i;
42 unsigned int ext_irq = 0;
43 55
44 intv &= (1 << SE7343_FPGA_IRQ_NR) - 1; 56 se7343_irq_domain = irq_domain_add_linear(NULL, SE7343_FPGA_IRQ_NR,
57 &irq_domain_simple_ops, NULL);
58 if (unlikely(!se7343_irq_domain)) {
59 printk("Failed to get IRQ domain\n");
60 return;
61 }
45 62
46 for (; intv; intv >>= 1, ext_irq++) { 63 for (i = 0; i < SE7343_FPGA_IRQ_NR; i++) {
47 if (!(intv & 1)) 64 int irq = irq_create_mapping(se7343_irq_domain, i);
48 continue;
49 65
50 generic_handle_irq(se7343_fpga_irq[ext_irq]); 66 if (unlikely(irq == 0)) {
67 printk("Failed to allocate IRQ %d\n", i);
68 return;
69 }
51 } 70 }
52} 71}
53 72
54/* 73static void __init se7343_gc_init(void)
55 * Initialize IRQ setting
56 */
57void __init init_7343se_IRQ(void)
58{ 74{
59 int i, irq; 75 struct irq_chip_generic *gc;
76 struct irq_chip_type *ct;
77 unsigned int irq_base;
60 78
61 __raw_writew(0, PA_CPLD_IMSK); /* disable all irqs */ 79 irq_base = irq_linear_revmap(se7343_irq_domain, 0);
62 __raw_writew(0x2000, 0xb03fffec); /* mrshpc irq enable */
63 80
64 for (i = 0; i < SE7343_FPGA_IRQ_NR; i++) { 81 gc = irq_alloc_generic_chip(DRV_NAME, 1, irq_base, se7343_irq_regs,
65 irq = create_irq(); 82 handle_level_irq);
66 if (irq < 0) 83 if (unlikely(!gc))
67 return; 84 return;
68 se7343_fpga_irq[i] = irq;
69 85
70 irq_set_chip_and_handler_name(se7343_fpga_irq[i], 86 ct = gc->chip_types;
71 &se7343_irq_chip, 87 ct->chip.irq_mask = irq_gc_mask_set_bit;
72 handle_level_irq, 88 ct->chip.irq_unmask = irq_gc_mask_clr_bit;
73 "level");
74 89
75 irq_set_chip_data(se7343_fpga_irq[i], (void *)i); 90 ct->regs.mask = PA_CPLD_IMSK_REG;
76 } 91
92 irq_setup_generic_chip(gc, IRQ_MSK(SE7343_FPGA_IRQ_NR),
93 IRQ_GC_INIT_MASK_CACHE,
94 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
77 95
78 irq_set_chained_handler(IRQ0_IRQ, se7343_irq_demux); 96 irq_set_chained_handler(IRQ0_IRQ, se7343_irq_demux);
79 irq_set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW); 97 irq_set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
98
80 irq_set_chained_handler(IRQ1_IRQ, se7343_irq_demux); 99 irq_set_chained_handler(IRQ1_IRQ, se7343_irq_demux);
81 irq_set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW); 100 irq_set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW);
101
82 irq_set_chained_handler(IRQ4_IRQ, se7343_irq_demux); 102 irq_set_chained_handler(IRQ4_IRQ, se7343_irq_demux);
83 irq_set_irq_type(IRQ4_IRQ, IRQ_TYPE_LEVEL_LOW); 103 irq_set_irq_type(IRQ4_IRQ, IRQ_TYPE_LEVEL_LOW);
104
84 irq_set_chained_handler(IRQ5_IRQ, se7343_irq_demux); 105 irq_set_chained_handler(IRQ5_IRQ, se7343_irq_demux);
85 irq_set_irq_type(IRQ5_IRQ, IRQ_TYPE_LEVEL_LOW); 106 irq_set_irq_type(IRQ5_IRQ, IRQ_TYPE_LEVEL_LOW);
86} 107}
108
109/*
110 * Initialize IRQ setting
111 */
112void __init init_7343se_IRQ(void)
113{
114 se7343_irq_regs = ioremap(PA_CPLD_BASE_ADDR, SZ_16);
115 if (unlikely(!se7343_irq_regs)) {
116 pr_err("Failed to remap CPLD\n");
117 return;
118 }
119
120 /*
121 * All FPGA IRQs disabled by default
122 */
123 iowrite16(0, se7343_irq_regs + PA_CPLD_IMSK_REG);
124
125 __raw_writew(0x2000, 0xb03fffec); /* mrshpc irq enable */
126
127 se7343_domain_init();
128 se7343_gc_init();
129}
diff --git a/arch/sh/boards/mach-se/7343/setup.c b/arch/sh/boards/mach-se/7343/setup.c
index d2370af56d7..8ce4f2a202a 100644
--- a/arch/sh/boards/mach-se/7343/setup.c
+++ b/arch/sh/boards/mach-se/7343/setup.c
@@ -5,6 +5,7 @@
5#include <linux/serial_reg.h> 5#include <linux/serial_reg.h>
6#include <linux/usb/isp116x.h> 6#include <linux/usb/isp116x.h>
7#include <linux/delay.h> 7#include <linux/delay.h>
8#include <linux/irqdomain.h>
8#include <asm/machvec.h> 9#include <asm/machvec.h>
9#include <mach-se/mach/se7343.h> 10#include <mach-se/mach/se7343.h>
10#include <asm/heartbeat.h> 11#include <asm/heartbeat.h>
@@ -145,11 +146,12 @@ static struct platform_device *sh7343se_platform_devices[] __initdata = {
145static int __init sh7343se_devices_setup(void) 146static int __init sh7343se_devices_setup(void)
146{ 147{
147 /* Wire-up dynamic vectors */ 148 /* Wire-up dynamic vectors */
148 serial_platform_data[0].irq = se7343_fpga_irq[SE7343_FPGA_IRQ_UARTA]; 149 serial_platform_data[0].irq = irq_find_mapping(se7343_irq_domain,
149 serial_platform_data[1].irq = se7343_fpga_irq[SE7343_FPGA_IRQ_UARTB]; 150 SE7343_FPGA_IRQ_UARTA);
150 151 serial_platform_data[1].irq = irq_find_mapping(se7343_irq_domain,
152 SE7343_FPGA_IRQ_UARTB);
151 usb_resources[2].start = usb_resources[2].end = 153 usb_resources[2].start = usb_resources[2].end =
152 se7343_fpga_irq[SE7343_FPGA_IRQ_USB]; 154 irq_find_mapping(se7343_irq_domain, SE7343_FPGA_IRQ_USB);
153 155
154 return platform_add_devices(sh7343se_platform_devices, 156 return platform_add_devices(sh7343se_platform_devices,
155 ARRAY_SIZE(sh7343se_platform_devices)); 157 ARRAY_SIZE(sh7343se_platform_devices));
diff --git a/arch/sh/boards/mach-se/7722/irq.c b/arch/sh/boards/mach-se/7722/irq.c
index aac92f21ebd..f5e2af1bf04 100644
--- a/arch/sh/boards/mach-se/7722/irq.c
+++ b/arch/sh/boards/mach-se/7722/irq.c
@@ -1,79 +1,96 @@
1/* 1/*
2 * linux/arch/sh/boards/se/7722/irq.c 2 * Hitachi UL SolutionEngine 7722 FPGA IRQ Support.
3 * 3 *
4 * Copyright (C) 2007 Nobuhiro Iwamatsu 4 * Copyright (C) 2007 Nobuhiro Iwamatsu
5 * 5 * Copyright (C) 2012 Paul Mundt
6 * Hitachi UL SolutionEngine 7722 Support.
7 * 6 *
8 * This file is subject to the terms and conditions of the GNU General Public 7 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive 8 * License. See the file "COPYING" in the main directory of this archive
10 * for more details. 9 * for more details.
11 */ 10 */
11#define DRV_NAME "SE7722-FPGA"
12#define pr_fmt(fmt) DRV_NAME ": " fmt
13
14#define irq_reg_readl ioread16
15#define irq_reg_writel iowrite16
16
12#include <linux/init.h> 17#include <linux/init.h>
13#include <linux/irq.h> 18#include <linux/irq.h>
14#include <linux/interrupt.h> 19#include <linux/interrupt.h>
15#include <asm/irq.h> 20#include <linux/irqdomain.h>
16#include <asm/io.h> 21#include <linux/io.h>
22#include <linux/err.h>
23#include <asm/sizes.h>
17#include <mach-se/mach/se7722.h> 24#include <mach-se/mach/se7722.h>
18 25
19unsigned int se7722_fpga_irq[SE7722_FPGA_IRQ_NR] = { 0, }; 26#define IRQ01_BASE_ADDR 0x11800000
27#define IRQ01_MODE_REG 0
28#define IRQ01_STS_REG 4
29#define IRQ01_MASK_REG 8
20 30
21static void disable_se7722_irq(struct irq_data *data) 31static void __iomem *se7722_irq_regs;
22{ 32struct irq_domain *se7722_irq_domain;
23 unsigned int bit = (unsigned int)irq_data_get_irq_chip_data(data);
24 __raw_writew(__raw_readw(IRQ01_MASK) | 1 << bit, IRQ01_MASK);
25}
26 33
27static void enable_se7722_irq(struct irq_data *data) 34static void se7722_irq_demux(unsigned int irq, struct irq_desc *desc)
28{ 35{
29 unsigned int bit = (unsigned int)irq_data_get_irq_chip_data(data); 36 struct irq_data *data = irq_get_irq_data(irq);
30 __raw_writew(__raw_readw(IRQ01_MASK) & ~(1 << bit), IRQ01_MASK); 37 struct irq_chip *chip = irq_data_get_irq_chip(data);
31} 38 unsigned long mask;
39 int bit;
32 40
33static struct irq_chip se7722_irq_chip __read_mostly = { 41 chip->irq_mask_ack(data);
34 .name = "SE7722-FPGA",
35 .irq_mask = disable_se7722_irq,
36 .irq_unmask = enable_se7722_irq,
37};
38 42
39static void se7722_irq_demux(unsigned int irq, struct irq_desc *desc) 43 mask = ioread16(se7722_irq_regs + IRQ01_STS_REG);
44
45 for_each_set_bit(bit, &mask, SE7722_FPGA_IRQ_NR)
46 generic_handle_irq(irq_linear_revmap(se7722_irq_domain, bit));
47
48 chip->irq_unmask(data);
49}
50
51static void __init se7722_domain_init(void)
40{ 52{
41 unsigned short intv = __raw_readw(IRQ01_STS); 53 int i;
42 unsigned int ext_irq = 0;
43 54
44 intv &= (1 << SE7722_FPGA_IRQ_NR) - 1; 55 se7722_irq_domain = irq_domain_add_linear(NULL, SE7722_FPGA_IRQ_NR,
56 &irq_domain_simple_ops, NULL);
57 if (unlikely(!se7722_irq_domain)) {
58 printk("Failed to get IRQ domain\n");
59 return;
60 }
45 61
46 for (; intv; intv >>= 1, ext_irq++) { 62 for (i = 0; i < SE7722_FPGA_IRQ_NR; i++) {
47 if (!(intv & 1)) 63 int irq = irq_create_mapping(se7722_irq_domain, i);
48 continue;
49 64
50 generic_handle_irq(se7722_fpga_irq[ext_irq]); 65 if (unlikely(irq == 0)) {
66 printk("Failed to allocate IRQ %d\n", i);
67 return;
68 }
51 } 69 }
52} 70}
53 71
54/* 72static void __init se7722_gc_init(void)
55 * Initialize IRQ setting
56 */
57void __init init_se7722_IRQ(void)
58{ 73{
59 int i, irq; 74 struct irq_chip_generic *gc;
75 struct irq_chip_type *ct;
76 unsigned int irq_base;
60 77
61 __raw_writew(0, IRQ01_MASK); /* disable all irqs */ 78 irq_base = irq_linear_revmap(se7722_irq_domain, 0);
62 __raw_writew(0x2000, 0xb03fffec); /* mrshpc irq enable */
63 79
64 for (i = 0; i < SE7722_FPGA_IRQ_NR; i++) { 80 gc = irq_alloc_generic_chip(DRV_NAME, 1, irq_base, se7722_irq_regs,
65 irq = create_irq(); 81 handle_level_irq);
66 if (irq < 0) 82 if (unlikely(!gc))
67 return; 83 return;
68 se7722_fpga_irq[i] = irq;
69 84
70 irq_set_chip_and_handler_name(se7722_fpga_irq[i], 85 ct = gc->chip_types;
71 &se7722_irq_chip, 86 ct->chip.irq_mask = irq_gc_mask_set_bit;
72 handle_level_irq, 87 ct->chip.irq_unmask = irq_gc_mask_clr_bit;
73 "level");
74 88
75 irq_set_chip_data(se7722_fpga_irq[i], (void *)i); 89 ct->regs.mask = IRQ01_MASK_REG;
76 } 90
91 irq_setup_generic_chip(gc, IRQ_MSK(SE7722_FPGA_IRQ_NR),
92 IRQ_GC_INIT_MASK_CACHE,
93 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
77 94
78 irq_set_chained_handler(IRQ0_IRQ, se7722_irq_demux); 95 irq_set_chained_handler(IRQ0_IRQ, se7722_irq_demux);
79 irq_set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW); 96 irq_set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
@@ -81,3 +98,25 @@ void __init init_se7722_IRQ(void)
81 irq_set_chained_handler(IRQ1_IRQ, se7722_irq_demux); 98 irq_set_chained_handler(IRQ1_IRQ, se7722_irq_demux);
82 irq_set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW); 99 irq_set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW);
83} 100}
101
102/*
103 * Initialize FPGA IRQs
104 */
105void __init init_se7722_IRQ(void)
106{
107 se7722_irq_regs = ioremap(IRQ01_BASE_ADDR, SZ_16);
108 if (unlikely(!se7722_irq_regs)) {
109 printk("Failed to remap IRQ01 regs\n");
110 return;
111 }
112
113 /*
114 * All FPGA IRQs disabled by default
115 */
116 iowrite16(0, se7722_irq_regs + IRQ01_MASK_REG);
117
118 __raw_writew(0x2000, 0xb03fffec); /* mrshpc irq enable */
119
120 se7722_domain_init();
121 se7722_gc_init();
122}
diff --git a/arch/sh/boards/mach-se/7722/setup.c b/arch/sh/boards/mach-se/7722/setup.c
index 8f7f0550cfd..e04e2bc4698 100644
--- a/arch/sh/boards/mach-se/7722/setup.c
+++ b/arch/sh/boards/mach-se/7722/setup.c
@@ -2,6 +2,7 @@
2 * linux/arch/sh/boards/se/7722/setup.c 2 * linux/arch/sh/boards/se/7722/setup.c
3 * 3 *
4 * Copyright (C) 2007 Nobuhiro Iwamatsu 4 * Copyright (C) 2007 Nobuhiro Iwamatsu
5 * Copyright (C) 2012 Paul Mundt
5 * 6 *
6 * Hitachi UL SolutionEngine 7722 Support. 7 * Hitachi UL SolutionEngine 7722 Support.
7 * 8 *
@@ -15,6 +16,7 @@
15#include <linux/ata_platform.h> 16#include <linux/ata_platform.h>
16#include <linux/input.h> 17#include <linux/input.h>
17#include <linux/input/sh_keysc.h> 18#include <linux/input/sh_keysc.h>
19#include <linux/irqdomain.h>
18#include <linux/smc91x.h> 20#include <linux/smc91x.h>
19#include <linux/sh_intc.h> 21#include <linux/sh_intc.h>
20#include <mach-se/mach/se7722.h> 22#include <mach-se/mach/se7722.h>
@@ -143,10 +145,10 @@ static int __init se7722_devices_setup(void)
143 145
144 /* Wire-up dynamic vectors */ 146 /* Wire-up dynamic vectors */
145 cf_ide_resources[2].start = cf_ide_resources[2].end = 147 cf_ide_resources[2].start = cf_ide_resources[2].end =
146 se7722_fpga_irq[SE7722_FPGA_IRQ_MRSHPC0]; 148 irq_find_mapping(se7722_irq_domain, SE7722_FPGA_IRQ_MRSHPC0);
147 149
148 smc91x_eth_resources[1].start = smc91x_eth_resources[1].end = 150 smc91x_eth_resources[1].start = smc91x_eth_resources[1].end =
149 se7722_fpga_irq[SE7722_FPGA_IRQ_SMC]; 151 irq_find_mapping(se7722_irq_domain, SE7722_FPGA_IRQ_SMC);
150 152
151 return platform_add_devices(se7722_devices, ARRAY_SIZE(se7722_devices)); 153 return platform_add_devices(se7722_devices, ARRAY_SIZE(se7722_devices));
152} 154}
diff --git a/arch/sh/boards/mach-se/7724/irq.c b/arch/sh/boards/mach-se/7724/irq.c
index c6342ce7768..5d1d3ec9a6c 100644
--- a/arch/sh/boards/mach-se/7724/irq.c
+++ b/arch/sh/boards/mach-se/7724/irq.c
@@ -17,8 +17,10 @@
17#include <linux/init.h> 17#include <linux/init.h>
18#include <linux/irq.h> 18#include <linux/irq.h>
19#include <linux/interrupt.h> 19#include <linux/interrupt.h>
20#include <asm/irq.h> 20#include <linux/export.h>
21#include <asm/io.h> 21#include <linux/topology.h>
22#include <linux/io.h>
23#include <linux/err.h>
22#include <mach-se/mach/se7724.h> 24#include <mach-se/mach/se7724.h>
23 25
24struct fpga_irq { 26struct fpga_irq {
@@ -111,7 +113,7 @@ static void se7724_irq_demux(unsigned int irq, struct irq_desc *desc)
111 */ 113 */
112void __init init_se7724_IRQ(void) 114void __init init_se7724_IRQ(void)
113{ 115{
114 int i, nid = cpu_to_node(boot_cpu_data); 116 int irq_base, i;
115 117
116 __raw_writew(0xffff, IRQ0_MR); /* mask all */ 118 __raw_writew(0xffff, IRQ0_MR); /* mask all */
117 __raw_writew(0xffff, IRQ1_MR); /* mask all */ 119 __raw_writew(0xffff, IRQ1_MR); /* mask all */
@@ -121,28 +123,16 @@ void __init init_se7724_IRQ(void)
121 __raw_writew(0x0000, IRQ2_SR); /* clear irq */ 123 __raw_writew(0x0000, IRQ2_SR); /* clear irq */
122 __raw_writew(0x002a, IRQ_MODE); /* set irq type */ 124 __raw_writew(0x002a, IRQ_MODE); /* set irq type */
123 125
124 for (i = 0; i < SE7724_FPGA_IRQ_NR; i++) { 126 irq_base = irq_alloc_descs(SE7724_FPGA_IRQ_BASE, SE7724_FPGA_IRQ_BASE,
125 int irq, wanted; 127 SE7724_FPGA_IRQ_NR, numa_node_id());
126 128 if (IS_ERR_VALUE(irq_base)) {
127 wanted = SE7724_FPGA_IRQ_BASE + i; 129 pr_err("%s: failed hooking irqs for FPGA\n", __func__);
128 130 return;
129 irq = create_irq_nr(wanted, nid); 131 }
130 if (unlikely(irq == 0)) {
131 pr_err("%s: failed hooking irq %d for FPGA\n",
132 __func__, wanted);
133 return;
134 }
135
136 if (unlikely(irq != wanted)) {
137 pr_err("%s: got irq %d but wanted %d, bailing.\n",
138 __func__, irq, wanted);
139 destroy_irq(irq);
140 return;
141 }
142 132
143 irq_set_chip_and_handler_name(irq, &se7724_irq_chip, 133 for (i = 0; i < SE7724_FPGA_IRQ_NR; i++)
134 irq_set_chip_and_handler_name(irq_base + i, &se7724_irq_chip,
144 handle_level_irq, "level"); 135 handle_level_irq, "level");
145 }
146 136
147 irq_set_chained_handler(IRQ0_IRQ, se7724_irq_demux); 137 irq_set_chained_handler(IRQ0_IRQ, se7724_irq_demux);
148 irq_set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW); 138 irq_set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
diff --git a/arch/sh/boards/mach-x3proto/gpio.c b/arch/sh/boards/mach-x3proto/gpio.c
index f33b2b57019..3ea65e9b56e 100644
--- a/arch/sh/boards/mach-x3proto/gpio.c
+++ b/arch/sh/boards/mach-x3proto/gpio.c
@@ -3,7 +3,7 @@
3 * 3 *
4 * Renesas SH-X3 Prototype Baseboard GPIO Support. 4 * Renesas SH-X3 Prototype Baseboard GPIO Support.
5 * 5 *
6 * Copyright (C) 2010 Paul Mundt 6 * Copyright (C) 2010 - 2012 Paul Mundt
7 * 7 *
8 * This file is subject to the terms and conditions of the GNU General Public 8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive 9 * License. See the file "COPYING" in the main directory of this archive
@@ -17,6 +17,7 @@
17#include <linux/irq.h> 17#include <linux/irq.h>
18#include <linux/kernel.h> 18#include <linux/kernel.h>
19#include <linux/spinlock.h> 19#include <linux/spinlock.h>
20#include <linux/irqdomain.h>
20#include <linux/io.h> 21#include <linux/io.h>
21#include <mach/ilsel.h> 22#include <mach/ilsel.h>
22#include <mach/hardware.h> 23#include <mach/hardware.h>
@@ -26,7 +27,7 @@
26#define KEYDETR 0xb81c0004 27#define KEYDETR 0xb81c0004
27 28
28static DEFINE_SPINLOCK(x3proto_gpio_lock); 29static DEFINE_SPINLOCK(x3proto_gpio_lock);
29static unsigned int x3proto_gpio_irq_map[NR_BASEBOARD_GPIOS] = { 0, }; 30static struct irq_domain *x3proto_irq_domain;
30 31
31static int x3proto_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) 32static int x3proto_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
32{ 33{
@@ -49,7 +50,14 @@ static int x3proto_gpio_get(struct gpio_chip *chip, unsigned gpio)
49 50
50static int x3proto_gpio_to_irq(struct gpio_chip *chip, unsigned gpio) 51static int x3proto_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
51{ 52{
52 return x3proto_gpio_irq_map[gpio]; 53 int virq;
54
55 if (gpio < chip->ngpio)
56 virq = irq_create_mapping(x3proto_irq_domain, gpio);
57 else
58 virq = -ENXIO;
59
60 return virq;
53} 61}
54 62
55static void x3proto_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) 63static void x3proto_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
@@ -62,9 +70,8 @@ static void x3proto_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
62 chip->irq_mask_ack(data); 70 chip->irq_mask_ack(data);
63 71
64 mask = __raw_readw(KEYDETR); 72 mask = __raw_readw(KEYDETR);
65
66 for_each_set_bit(pin, &mask, NR_BASEBOARD_GPIOS) 73 for_each_set_bit(pin, &mask, NR_BASEBOARD_GPIOS)
67 generic_handle_irq(x3proto_gpio_to_irq(NULL, pin)); 74 generic_handle_irq(irq_linear_revmap(x3proto_irq_domain, pin));
68 75
69 chip->irq_unmask(data); 76 chip->irq_unmask(data);
70} 77}
@@ -78,10 +85,23 @@ struct gpio_chip x3proto_gpio_chip = {
78 .ngpio = NR_BASEBOARD_GPIOS, 85 .ngpio = NR_BASEBOARD_GPIOS,
79}; 86};
80 87
88static int x3proto_gpio_irq_map(struct irq_domain *domain, unsigned int virq,
89 irq_hw_number_t hwirq)
90{
91 irq_set_chip_and_handler_name(virq, &dummy_irq_chip, handle_simple_irq,
92 "gpio");
93
94 return 0;
95}
96
97static struct irq_domain_ops x3proto_gpio_irq_ops = {
98 .map = x3proto_gpio_irq_map,
99 .xlate = irq_domain_xlate_twocell,
100};
101
81int __init x3proto_gpio_setup(void) 102int __init x3proto_gpio_setup(void)
82{ 103{
83 int ilsel; 104 int ilsel, ret;
84 int ret, i;
85 105
86 ilsel = ilsel_enable(ILSEL_KEY); 106 ilsel = ilsel_enable(ILSEL_KEY);
87 if (unlikely(ilsel < 0)) 107 if (unlikely(ilsel < 0))
@@ -91,21 +111,10 @@ int __init x3proto_gpio_setup(void)
91 if (unlikely(ret)) 111 if (unlikely(ret))
92 goto err_gpio; 112 goto err_gpio;
93 113
94 for (i = 0; i < NR_BASEBOARD_GPIOS; i++) { 114 x3proto_irq_domain = irq_domain_add_linear(NULL, NR_BASEBOARD_GPIOS,
95 unsigned long flags; 115 &x3proto_gpio_irq_ops, NULL);
96 int irq = create_irq(); 116 if (unlikely(!x3proto_irq_domain))
97 117 goto err_irq;
98 if (unlikely(irq < 0)) {
99 ret = -EINVAL;
100 goto err_irq;
101 }
102
103 spin_lock_irqsave(&x3proto_gpio_lock, flags);
104 x3proto_gpio_irq_map[i] = irq;
105 irq_set_chip_and_handler_name(irq, &dummy_irq_chip,
106 handle_simple_irq, "gpio");
107 spin_unlock_irqrestore(&x3proto_gpio_lock, flags);
108 }
109 118
110 pr_info("registering '%s' support, handling GPIOs %u -> %u, " 119 pr_info("registering '%s' support, handling GPIOs %u -> %u, "
111 "bound to IRQ %u\n", 120 "bound to IRQ %u\n",
@@ -119,10 +128,6 @@ int __init x3proto_gpio_setup(void)
119 return 0; 128 return 0;
120 129
121err_irq: 130err_irq:
122 for (; i >= 0; --i)
123 if (x3proto_gpio_irq_map[i])
124 destroy_irq(x3proto_gpio_irq_map[i]);
125
126 ret = gpiochip_remove(&x3proto_gpio_chip); 131 ret = gpiochip_remove(&x3proto_gpio_chip);
127 if (unlikely(ret)) 132 if (unlikely(ret))
128 pr_err("Failed deregistering GPIO\n"); 133 pr_err("Failed deregistering GPIO\n");
diff --git a/arch/sh/cchips/hd6446x/hd64461.c b/arch/sh/cchips/hd6446x/hd64461.c
index eb4ea4d44d5..e9735616bdc 100644
--- a/arch/sh/cchips/hd6446x/hd64461.c
+++ b/arch/sh/cchips/hd6446x/hd64461.c
@@ -73,10 +73,7 @@ static void hd64461_irq_demux(unsigned int irq, struct irq_desc *desc)
73 73
74int __init setup_hd64461(void) 74int __init setup_hd64461(void)
75{ 75{
76 int i, nid = cpu_to_node(boot_cpu_data); 76 int irq_base, i;
77
78 if (!MACH_HD64461)
79 return 0;
80 77
81 printk(KERN_INFO 78 printk(KERN_INFO
82 "HD64461 configured at 0x%x on irq %d(mapped into %d to %d)\n", 79 "HD64461 configured at 0x%x on irq %d(mapped into %d to %d)\n",
@@ -89,28 +86,16 @@ int __init setup_hd64461(void)
89#endif 86#endif
90 __raw_writew(0xffff, HD64461_NIMR); 87 __raw_writew(0xffff, HD64461_NIMR);
91 88
92 /* IRQ 80 -> 95 belongs to HD64461 */ 89 irq_base = irq_alloc_descs(HD64461_IRQBASE, HD64461_IRQBASE, 16, -1);
93 for (i = HD64461_IRQBASE; i < HD64461_IRQBASE + 16; i++) { 90 if (IS_ERR_VALUE(irq_base)) {
94 unsigned int irq; 91 pr_err("%s: failed hooking irqs for HD64461\n", __func__);
95 92 return irq_base;
96 irq = create_irq_nr(i, nid);
97 if (unlikely(irq == 0)) {
98 pr_err("%s: failed hooking irq %d for HD64461\n",
99 __func__, i);
100 return -EBUSY;
101 }
102
103 if (unlikely(irq != i)) {
104 pr_err("%s: got irq %d but wanted %d, bailing.\n",
105 __func__, irq, i);
106 destroy_irq(irq);
107 return -EINVAL;
108 }
109
110 irq_set_chip_and_handler(i, &hd64461_irq_chip,
111 handle_level_irq);
112 } 93 }
113 94
95 for (i = 0; i < 16; i++)
96 irq_set_chip_and_handler(irq_base + i, &hd64461_irq_chip,
97 handle_level_irq);
98
114 irq_set_chained_handler(CONFIG_HD64461_IRQ, hd64461_irq_demux); 99 irq_set_chained_handler(CONFIG_HD64461_IRQ, hd64461_irq_demux);
115 irq_set_irq_type(CONFIG_HD64461_IRQ, IRQ_TYPE_LEVEL_LOW); 100 irq_set_irq_type(CONFIG_HD64461_IRQ, IRQ_TYPE_LEVEL_LOW);
116 101
diff --git a/arch/sh/include/asm/bug.h b/arch/sh/include/asm/bug.h
index 2b87d86bfc4..dcf27807542 100644
--- a/arch/sh/include/asm/bug.h
+++ b/arch/sh/include/asm/bug.h
@@ -110,6 +110,10 @@ do { \
110#include <asm-generic/bug.h> 110#include <asm-generic/bug.h>
111 111
112struct pt_regs; 112struct pt_regs;
113
114/* arch/sh/kernel/traps.c */
113extern void die(const char *str, struct pt_regs *regs, long err) __attribute__ ((noreturn)); 115extern void die(const char *str, struct pt_regs *regs, long err) __attribute__ ((noreturn));
116extern void die_if_kernel(const char *str, struct pt_regs *regs, long err);
117extern void die_if_no_fixup(const char *str, struct pt_regs *regs, long err);
114 118
115#endif /* __ASM_SH_BUG_H */ 119#endif /* __ASM_SH_BUG_H */
diff --git a/arch/sh/include/asm/kdebug.h b/arch/sh/include/asm/kdebug.h
index a6201f10c27..8d6a831e7ba 100644
--- a/arch/sh/include/asm/kdebug.h
+++ b/arch/sh/include/asm/kdebug.h
@@ -10,6 +10,8 @@ enum die_val {
10 DIE_SSTEP, 10 DIE_SSTEP,
11}; 11};
12 12
13/* arch/sh/kernel/dumpstack.c */
13extern void printk_address(unsigned long address, int reliable); 14extern void printk_address(unsigned long address, int reliable);
15extern void dump_mem(const char *str, unsigned long bottom, unsigned long top);
14 16
15#endif /* __ASM_SH_KDEBUG_H */ 17#endif /* __ASM_SH_KDEBUG_H */
diff --git a/arch/sh/include/mach-se/mach/se7343.h b/arch/sh/include/mach-se/mach/se7343.h
index 50b5d575dff..542521c970c 100644
--- a/arch/sh/include/mach-se/mach/se7343.h
+++ b/arch/sh/include/mach-se/mach/se7343.h
@@ -50,9 +50,6 @@
50#define PA_LED 0xb0C00000 /* LED */ 50#define PA_LED 0xb0C00000 /* LED */
51#define LED_SHIFT 0 51#define LED_SHIFT 0
52#define PA_DIPSW 0xb0900000 /* Dip switch 31 */ 52#define PA_DIPSW 0xb0900000 /* Dip switch 31 */
53#define PA_CPLD_MODESET 0xb1400004 /* CPLD Mode set register */
54#define PA_CPLD_ST 0xb1400008 /* CPLD Interrupt status register */
55#define PA_CPLD_IMSK 0xb140000a /* CPLD Interrupt mask register */
56/* Area 5 */ 53/* Area 5 */
57#define PA_EXT5 0x14000000 54#define PA_EXT5 0x14000000
58#define PA_EXT5_SIZE 0x04000000 55#define PA_EXT5_SIZE 0x04000000
@@ -135,8 +132,10 @@
135 132
136#define SE7343_FPGA_IRQ_NR 12 133#define SE7343_FPGA_IRQ_NR 12
137 134
135struct irq_domain;
136
138/* arch/sh/boards/se/7343/irq.c */ 137/* arch/sh/boards/se/7343/irq.c */
139extern unsigned int se7343_fpga_irq[]; 138extern struct irq_domain *se7343_irq_domain;
140 139
141void init_7343se_IRQ(void); 140void init_7343se_IRQ(void);
142 141
diff --git a/arch/sh/include/mach-se/mach/se7722.h b/arch/sh/include/mach-se/mach/se7722.h
index 201081ebdbc..637e7ac753f 100644
--- a/arch/sh/include/mach-se/mach/se7722.h
+++ b/arch/sh/include/mach-se/mach/se7722.h
@@ -81,12 +81,6 @@
81#define IRQ0_IRQ evt2irq(0x600) 81#define IRQ0_IRQ evt2irq(0x600)
82#define IRQ1_IRQ evt2irq(0x620) 82#define IRQ1_IRQ evt2irq(0x620)
83 83
84#define IRQ01_MODE 0xb1800000
85#define IRQ01_STS 0xb1800004
86#define IRQ01_MASK 0xb1800008
87
88/* Bits in IRQ01_* registers */
89
90#define SE7722_FPGA_IRQ_USB 0 /* IRQ0 */ 84#define SE7722_FPGA_IRQ_USB 0 /* IRQ0 */
91#define SE7722_FPGA_IRQ_SMC 1 /* IRQ0 */ 85#define SE7722_FPGA_IRQ_SMC 1 /* IRQ0 */
92#define SE7722_FPGA_IRQ_MRSHPC0 2 /* IRQ1 */ 86#define SE7722_FPGA_IRQ_MRSHPC0 2 /* IRQ1 */
@@ -95,8 +89,10 @@
95#define SE7722_FPGA_IRQ_MRSHPC3 5 /* IRQ1 */ 89#define SE7722_FPGA_IRQ_MRSHPC3 5 /* IRQ1 */
96#define SE7722_FPGA_IRQ_NR 6 90#define SE7722_FPGA_IRQ_NR 6
97 91
92struct irq_domain;
93
98/* arch/sh/boards/se/7722/irq.c */ 94/* arch/sh/boards/se/7722/irq.c */
99extern unsigned int se7722_fpga_irq[]; 95extern struct irq_domain *se7722_irq_domain;
100 96
101void init_se7722_IRQ(void); 97void init_se7722_IRQ(void);
102 98
diff --git a/arch/sh/kernel/cpu/sh5/unwind.c b/arch/sh/kernel/cpu/sh5/unwind.c
index b205b25eaf4..10aed41757f 100644
--- a/arch/sh/kernel/cpu/sh5/unwind.c
+++ b/arch/sh/kernel/cpu/sh5/unwind.c
@@ -16,6 +16,8 @@
16#include <asm/ptrace.h> 16#include <asm/ptrace.h>
17#include <asm/processor.h> 17#include <asm/processor.h>
18#include <asm/io.h> 18#include <asm/io.h>
19#include <asm/unwinder.h>
20#include <asm/stacktrace.h>
19 21
20static u8 regcache[63]; 22static u8 regcache[63];
21 23
@@ -199,8 +201,11 @@ static int lookup_prev_stack_frame(unsigned long fp, unsigned long pc,
199 return 0; 201 return 0;
200} 202}
201 203
202/* Don't put this on the stack since we'll want to call sh64_unwind 204/*
203 * when we're close to underflowing the stack anyway. */ 205 * Don't put this on the stack since we'll want to call in to
206 * sh64_unwinder_dump() when we're close to underflowing the stack
207 * anyway.
208 */
204static struct pt_regs here_regs; 209static struct pt_regs here_regs;
205 210
206extern const char syscall_ret; 211extern const char syscall_ret;
@@ -208,17 +213,19 @@ extern const char ret_from_syscall;
208extern const char ret_from_exception; 213extern const char ret_from_exception;
209extern const char ret_from_irq; 214extern const char ret_from_irq;
210 215
211static void sh64_unwind_inner(struct pt_regs *regs); 216static void sh64_unwind_inner(const struct stacktrace_ops *ops,
217 void *data, struct pt_regs *regs);
212 218
213static void unwind_nested (unsigned long pc, unsigned long fp) 219static inline void unwind_nested(const struct stacktrace_ops *ops, void *data,
220 unsigned long pc, unsigned long fp)
214{ 221{
215 if ((fp >= __MEMORY_START) && 222 if ((fp >= __MEMORY_START) &&
216 ((fp & 7) == 0)) { 223 ((fp & 7) == 0))
217 sh64_unwind_inner((struct pt_regs *) fp); 224 sh64_unwind_inner(ops, data, (struct pt_regs *)fp);
218 }
219} 225}
220 226
221static void sh64_unwind_inner(struct pt_regs *regs) 227static void sh64_unwind_inner(const struct stacktrace_ops *ops,
228 void *data, struct pt_regs *regs)
222{ 229{
223 unsigned long pc, fp; 230 unsigned long pc, fp;
224 int ofs = 0; 231 int ofs = 0;
@@ -232,29 +239,29 @@ static void sh64_unwind_inner(struct pt_regs *regs)
232 int cond; 239 int cond;
233 unsigned long next_fp, next_pc; 240 unsigned long next_fp, next_pc;
234 241
235 if (pc == ((unsigned long) &syscall_ret & ~1)) { 242 if (pc == ((unsigned long)&syscall_ret & ~1)) {
236 printk("SYSCALL\n"); 243 printk("SYSCALL\n");
237 unwind_nested(pc,fp); 244 unwind_nested(ops, data, pc, fp);
238 return; 245 return;
239 } 246 }
240 247
241 if (pc == ((unsigned long) &ret_from_syscall & ~1)) { 248 if (pc == ((unsigned long)&ret_from_syscall & ~1)) {
242 printk("SYSCALL (PREEMPTED)\n"); 249 printk("SYSCALL (PREEMPTED)\n");
243 unwind_nested(pc,fp); 250 unwind_nested(ops, data, pc, fp);
244 return; 251 return;
245 } 252 }
246 253
247 /* In this case, the PC is discovered by lookup_prev_stack_frame but 254 /* In this case, the PC is discovered by lookup_prev_stack_frame but
248 it has 4 taken off it to look like the 'caller' */ 255 it has 4 taken off it to look like the 'caller' */
249 if (pc == ((unsigned long) &ret_from_exception & ~1)) { 256 if (pc == ((unsigned long)&ret_from_exception & ~1)) {
250 printk("EXCEPTION\n"); 257 printk("EXCEPTION\n");
251 unwind_nested(pc,fp); 258 unwind_nested(ops, data, pc, fp);
252 return; 259 return;
253 } 260 }
254 261
255 if (pc == ((unsigned long) &ret_from_irq & ~1)) { 262 if (pc == ((unsigned long)&ret_from_irq & ~1)) {
256 printk("IRQ\n"); 263 printk("IRQ\n");
257 unwind_nested(pc,fp); 264 unwind_nested(ops, data, pc, fp);
258 return; 265 return;
259 } 266 }
260 267
@@ -263,8 +270,7 @@ static void sh64_unwind_inner(struct pt_regs *regs)
263 270
264 pc -= ofs; 271 pc -= ofs;
265 272
266 printk("[<%08lx>] ", pc); 273 ops->address(data, pc, 1);
267 print_symbol("%s\n", pc);
268 274
269 if (first_pass) { 275 if (first_pass) {
270 /* If the innermost frame is a leaf function, it's 276 /* If the innermost frame is a leaf function, it's
@@ -287,10 +293,13 @@ static void sh64_unwind_inner(struct pt_regs *regs)
287 } 293 }
288 294
289 printk("\n"); 295 printk("\n");
290
291} 296}
292 297
293void sh64_unwind(struct pt_regs *regs) 298static void sh64_unwinder_dump(struct task_struct *task,
299 struct pt_regs *regs,
300 unsigned long *sp,
301 const struct stacktrace_ops *ops,
302 void *data)
294{ 303{
295 if (!regs) { 304 if (!regs) {
296 /* 305 /*
@@ -320,7 +329,17 @@ void sh64_unwind(struct pt_regs *regs)
320 ); 329 );
321 } 330 }
322 331
323 printk("\nCall Trace:\n"); 332 sh64_unwind_inner(ops, data, regs);
324 sh64_unwind_inner(regs);
325} 333}
326 334
335static struct unwinder sh64_unwinder = {
336 .name = "sh64-unwinder",
337 .dump = sh64_unwinder_dump,
338 .rating = 150,
339};
340
341static int __init sh64_unwinder_init(void)
342{
343 return unwinder_register(&sh64_unwinder);
344}
345early_initcall(sh64_unwinder_init);
diff --git a/arch/sh/kernel/dumpstack.c b/arch/sh/kernel/dumpstack.c
index 694158b9a50..7617dc4129a 100644
--- a/arch/sh/kernel/dumpstack.c
+++ b/arch/sh/kernel/dumpstack.c
@@ -2,13 +2,48 @@
2 * Copyright (C) 1991, 1992 Linus Torvalds 2 * Copyright (C) 1991, 1992 Linus Torvalds
3 * Copyright (C) 2000, 2001, 2002 Andi Kleen, SuSE Labs 3 * Copyright (C) 2000, 2001, 2002 Andi Kleen, SuSE Labs
4 * Copyright (C) 2009 Matt Fleming 4 * Copyright (C) 2009 Matt Fleming
5 * Copyright (C) 2002 - 2012 Paul Mundt
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
5 */ 10 */
6#include <linux/kallsyms.h> 11#include <linux/kallsyms.h>
7#include <linux/ftrace.h> 12#include <linux/ftrace.h>
8#include <linux/debug_locks.h> 13#include <linux/debug_locks.h>
14#include <linux/kdebug.h>
15#include <linux/export.h>
16#include <linux/uaccess.h>
9#include <asm/unwinder.h> 17#include <asm/unwinder.h>
10#include <asm/stacktrace.h> 18#include <asm/stacktrace.h>
11 19
20void dump_mem(const char *str, unsigned long bottom, unsigned long top)
21{
22 unsigned long p;
23 int i;
24
25 printk("%s(0x%08lx to 0x%08lx)\n", str, bottom, top);
26
27 for (p = bottom & ~31; p < top; ) {
28 printk("%04lx: ", p & 0xffff);
29
30 for (i = 0; i < 8; i++, p += 4) {
31 unsigned int val;
32
33 if (p < bottom || p >= top)
34 printk(" ");
35 else {
36 if (__get_user(val, (unsigned int __user *)p)) {
37 printk("\n");
38 return;
39 }
40 printk("%08x ", val);
41 }
42 }
43 printk("\n");
44 }
45}
46
12void printk_address(unsigned long address, int reliable) 47void printk_address(unsigned long address, int reliable)
13{ 48{
14 printk(" [<%p>] %s%pS\n", (void *) address, 49 printk(" [<%p>] %s%pS\n", (void *) address,
@@ -106,3 +141,26 @@ void show_trace(struct task_struct *tsk, unsigned long *sp,
106 141
107 debug_show_held_locks(tsk); 142 debug_show_held_locks(tsk);
108} 143}
144
145void show_stack(struct task_struct *tsk, unsigned long *sp)
146{
147 unsigned long stack;
148
149 if (!tsk)
150 tsk = current;
151 if (tsk == current)
152 sp = (unsigned long *)current_stack_pointer;
153 else
154 sp = (unsigned long *)tsk->thread.sp;
155
156 stack = (unsigned long)sp;
157 dump_mem("Stack: ", stack, THREAD_SIZE +
158 (unsigned long)task_stack_page(tsk));
159 show_trace(tsk, sp, NULL);
160}
161
162void dump_stack(void)
163{
164 show_stack(NULL, NULL);
165}
166EXPORT_SYMBOL(dump_stack);
diff --git a/arch/sh/kernel/irq.c b/arch/sh/kernel/irq.c
index dadce735f74..063af10ff3c 100644
--- a/arch/sh/kernel/irq.c
+++ b/arch/sh/kernel/irq.c
@@ -231,16 +231,6 @@ void __init init_IRQ(void)
231 irq_ctx_init(smp_processor_id()); 231 irq_ctx_init(smp_processor_id());
232} 232}
233 233
234#ifdef CONFIG_SPARSE_IRQ
235int __init arch_probe_nr_irqs(void)
236{
237 /*
238 * No pre-allocated IRQs.
239 */
240 return 0;
241}
242#endif
243
244#ifdef CONFIG_HOTPLUG_CPU 234#ifdef CONFIG_HOTPLUG_CPU
245static void route_irq(struct irq_data *data, unsigned int irq, unsigned int cpu) 235static void route_irq(struct irq_data *data, unsigned int irq, unsigned int cpu)
246{ 236{
diff --git a/arch/sh/kernel/traps.c b/arch/sh/kernel/traps.c
index a87e58a9e38..72246bc0688 100644
--- a/arch/sh/kernel/traps.c
+++ b/arch/sh/kernel/traps.c
@@ -6,9 +6,80 @@
6#include <linux/sched.h> 6#include <linux/sched.h>
7#include <linux/uaccess.h> 7#include <linux/uaccess.h>
8#include <linux/hardirq.h> 8#include <linux/hardirq.h>
9#include <linux/kernel.h>
10#include <linux/kexec.h>
11#include <linux/module.h>
9#include <asm/unwinder.h> 12#include <asm/unwinder.h>
10#include <asm/traps.h> 13#include <asm/traps.h>
11 14
15static DEFINE_SPINLOCK(die_lock);
16
17void die(const char *str, struct pt_regs *regs, long err)
18{
19 static int die_counter;
20
21 oops_enter();
22
23 spin_lock_irq(&die_lock);
24 console_verbose();
25 bust_spinlocks(1);
26
27 printk("%s: %04lx [#%d]\n", str, err & 0xffff, ++die_counter);
28 print_modules();
29 show_regs(regs);
30
31 printk("Process: %s (pid: %d, stack limit = %p)\n", current->comm,
32 task_pid_nr(current), task_stack_page(current) + 1);
33
34 if (!user_mode(regs) || in_interrupt())
35 dump_mem("Stack: ", regs->regs[15], THREAD_SIZE +
36 (unsigned long)task_stack_page(current));
37
38 notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV);
39
40 bust_spinlocks(0);
41 add_taint(TAINT_DIE);
42 spin_unlock_irq(&die_lock);
43 oops_exit();
44
45 if (kexec_should_crash(current))
46 crash_kexec(regs);
47
48 if (in_interrupt())
49 panic("Fatal exception in interrupt");
50
51 if (panic_on_oops)
52 panic("Fatal exception");
53
54 do_exit(SIGSEGV);
55}
56
57void die_if_kernel(const char *str, struct pt_regs *regs, long err)
58{
59 if (!user_mode(regs))
60 die(str, regs, err);
61}
62
63/*
64 * try and fix up kernelspace address errors
65 * - userspace errors just cause EFAULT to be returned, resulting in SEGV
66 * - kernel/userspace interfaces cause a jump to an appropriate handler
67 * - other kernel errors are bad
68 */
69void die_if_no_fixup(const char *str, struct pt_regs *regs, long err)
70{
71 if (!user_mode(regs)) {
72 const struct exception_table_entry *fixup;
73 fixup = search_exception_tables(regs->pc);
74 if (fixup) {
75 regs->pc = fixup->fixup;
76 return;
77 }
78
79 die(str, regs, err);
80 }
81}
82
12#ifdef CONFIG_GENERIC_BUG 83#ifdef CONFIG_GENERIC_BUG
13static void handle_BUG(struct pt_regs *regs) 84static void handle_BUG(struct pt_regs *regs)
14{ 85{
diff --git a/arch/sh/kernel/traps_32.c b/arch/sh/kernel/traps_32.c
index a37175deb73..5f513a64ded 100644
--- a/arch/sh/kernel/traps_32.c
+++ b/arch/sh/kernel/traps_32.c
@@ -16,13 +16,11 @@
16#include <linux/hardirq.h> 16#include <linux/hardirq.h>
17#include <linux/init.h> 17#include <linux/init.h>
18#include <linux/spinlock.h> 18#include <linux/spinlock.h>
19#include <linux/module.h>
20#include <linux/kallsyms.h> 19#include <linux/kallsyms.h>
21#include <linux/io.h> 20#include <linux/io.h>
22#include <linux/bug.h> 21#include <linux/bug.h>
23#include <linux/debug_locks.h> 22#include <linux/debug_locks.h>
24#include <linux/kdebug.h> 23#include <linux/kdebug.h>
25#include <linux/kexec.h>
26#include <linux/limits.h> 24#include <linux/limits.h>
27#include <linux/sysfs.h> 25#include <linux/sysfs.h>
28#include <linux/uaccess.h> 26#include <linux/uaccess.h>
@@ -48,102 +46,6 @@
48#define TRAP_ILLEGAL_SLOT_INST 13 46#define TRAP_ILLEGAL_SLOT_INST 13
49#endif 47#endif
50 48
51static void dump_mem(const char *str, unsigned long bottom, unsigned long top)
52{
53 unsigned long p;
54 int i;
55
56 printk("%s(0x%08lx to 0x%08lx)\n", str, bottom, top);
57
58 for (p = bottom & ~31; p < top; ) {
59 printk("%04lx: ", p & 0xffff);
60
61 for (i = 0; i < 8; i++, p += 4) {
62 unsigned int val;
63
64 if (p < bottom || p >= top)
65 printk(" ");
66 else {
67 if (__get_user(val, (unsigned int __user *)p)) {
68 printk("\n");
69 return;
70 }
71 printk("%08x ", val);
72 }
73 }
74 printk("\n");
75 }
76}
77
78static DEFINE_SPINLOCK(die_lock);
79
80void die(const char * str, struct pt_regs * regs, long err)
81{
82 static int die_counter;
83
84 oops_enter();
85
86 spin_lock_irq(&die_lock);
87 console_verbose();
88 bust_spinlocks(1);
89
90 printk("%s: %04lx [#%d]\n", str, err & 0xffff, ++die_counter);
91 print_modules();
92 show_regs(regs);
93
94 printk("Process: %s (pid: %d, stack limit = %p)\n", current->comm,
95 task_pid_nr(current), task_stack_page(current) + 1);
96
97 if (!user_mode(regs) || in_interrupt())
98 dump_mem("Stack: ", regs->regs[15], THREAD_SIZE +
99 (unsigned long)task_stack_page(current));
100
101 notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV);
102
103 bust_spinlocks(0);
104 add_taint(TAINT_DIE);
105 spin_unlock_irq(&die_lock);
106 oops_exit();
107
108 if (kexec_should_crash(current))
109 crash_kexec(regs);
110
111 if (in_interrupt())
112 panic("Fatal exception in interrupt");
113
114 if (panic_on_oops)
115 panic("Fatal exception");
116
117 do_exit(SIGSEGV);
118}
119
120static inline void die_if_kernel(const char *str, struct pt_regs *regs,
121 long err)
122{
123 if (!user_mode(regs))
124 die(str, regs, err);
125}
126
127/*
128 * try and fix up kernelspace address errors
129 * - userspace errors just cause EFAULT to be returned, resulting in SEGV
130 * - kernel/userspace interfaces cause a jump to an appropriate handler
131 * - other kernel errors are bad
132 */
133static void die_if_no_fixup(const char * str, struct pt_regs * regs, long err)
134{
135 if (!user_mode(regs)) {
136 const struct exception_table_entry *fixup;
137 fixup = search_exception_tables(regs->pc);
138 if (fixup) {
139 regs->pc = fixup->fixup;
140 return;
141 }
142
143 die(str, regs, err);
144 }
145}
146
147static inline void sign_extend(unsigned int count, unsigned char *dst) 49static inline void sign_extend(unsigned int count, unsigned char *dst)
148{ 50{
149#ifdef __LITTLE_ENDIAN__ 51#ifdef __LITTLE_ENDIAN__
@@ -900,26 +802,3 @@ void __init trap_init(void)
900 set_exception_table_vec(TRAP_UBC, breakpoint_trap_handler); 802 set_exception_table_vec(TRAP_UBC, breakpoint_trap_handler);
901#endif 803#endif
902} 804}
903
904void show_stack(struct task_struct *tsk, unsigned long *sp)
905{
906 unsigned long stack;
907
908 if (!tsk)
909 tsk = current;
910 if (tsk == current)
911 sp = (unsigned long *)current_stack_pointer;
912 else
913 sp = (unsigned long *)tsk->thread.sp;
914
915 stack = (unsigned long)sp;
916 dump_mem("Stack: ", stack, THREAD_SIZE +
917 (unsigned long)task_stack_page(tsk));
918 show_trace(tsk, sp, NULL);
919}
920
921void dump_stack(void)
922{
923 show_stack(NULL, NULL);
924}
925EXPORT_SYMBOL(dump_stack);
diff --git a/arch/sh/kernel/traps_64.c b/arch/sh/kernel/traps_64.c
index 8dae93ed8af..f87d20da179 100644
--- a/arch/sh/kernel/traps_64.c
+++ b/arch/sh/kernel/traps_64.c
@@ -27,283 +27,25 @@
27#include <linux/perf_event.h> 27#include <linux/perf_event.h>
28#include <asm/uaccess.h> 28#include <asm/uaccess.h>
29#include <asm/io.h> 29#include <asm/io.h>
30#include <linux/atomic.h> 30#include <asm/alignment.h>
31#include <asm/processor.h> 31#include <asm/processor.h>
32#include <asm/pgtable.h> 32#include <asm/pgtable.h>
33#include <asm/fpu.h> 33#include <asm/fpu.h>
34 34
35#undef DEBUG_EXCEPTION 35static int read_opcode(reg_size_t pc, insn_size_t *result_opcode, int from_user_mode)
36#ifdef DEBUG_EXCEPTION
37/* implemented in ../lib/dbg.c */
38extern void show_excp_regs(char *fname, int trapnr, int signr,
39 struct pt_regs *regs);
40#else
41#define show_excp_regs(a, b, c, d)
42#endif
43
44static void do_unhandled_exception(int trapnr, int signr, char *str, char *fn_name,
45 unsigned long error_code, struct pt_regs *regs, struct task_struct *tsk);
46
47#define DO_ERROR(trapnr, signr, str, name, tsk) \
48asmlinkage void do_##name(unsigned long error_code, struct pt_regs *regs) \
49{ \
50 do_unhandled_exception(trapnr, signr, str, __stringify(name), error_code, regs, current); \
51}
52
53static DEFINE_SPINLOCK(die_lock);
54
55void die(const char * str, struct pt_regs * regs, long err)
56{
57 console_verbose();
58 spin_lock_irq(&die_lock);
59 printk("%s: %lx\n", str, (err & 0xffffff));
60 show_regs(regs);
61 spin_unlock_irq(&die_lock);
62 do_exit(SIGSEGV);
63}
64
65static inline void die_if_kernel(const char * str, struct pt_regs * regs, long err)
66{
67 if (!user_mode(regs))
68 die(str, regs, err);
69}
70
71static void die_if_no_fixup(const char * str, struct pt_regs * regs, long err)
72{
73 if (!user_mode(regs)) {
74 const struct exception_table_entry *fixup;
75 fixup = search_exception_tables(regs->pc);
76 if (fixup) {
77 regs->pc = fixup->fixup;
78 return;
79 }
80 die(str, regs, err);
81 }
82}
83
84DO_ERROR(13, SIGILL, "illegal slot instruction", illegal_slot_inst, current)
85DO_ERROR(87, SIGSEGV, "address error (exec)", address_error_exec, current)
86
87
88/* Implement misaligned load/store handling for kernel (and optionally for user
89 mode too). Limitation : only SHmedia mode code is handled - there is no
90 handling at all for misaligned accesses occurring in SHcompact code yet. */
91
92static int misaligned_fixup(struct pt_regs *regs);
93
94asmlinkage void do_address_error_load(unsigned long error_code, struct pt_regs *regs)
95{
96 if (misaligned_fixup(regs) < 0) {
97 do_unhandled_exception(7, SIGSEGV, "address error(load)",
98 "do_address_error_load",
99 error_code, regs, current);
100 }
101 return;
102}
103
104asmlinkage void do_address_error_store(unsigned long error_code, struct pt_regs *regs)
105{
106 if (misaligned_fixup(regs) < 0) {
107 do_unhandled_exception(8, SIGSEGV, "address error(store)",
108 "do_address_error_store",
109 error_code, regs, current);
110 }
111 return;
112}
113
114#if defined(CONFIG_SH64_ID2815_WORKAROUND)
115
116#define OPCODE_INVALID 0
117#define OPCODE_USER_VALID 1
118#define OPCODE_PRIV_VALID 2
119
120/* getcon/putcon - requires checking which control register is referenced. */
121#define OPCODE_CTRL_REG 3
122
123/* Table of valid opcodes for SHmedia mode.
124 Form a 10-bit value by concatenating the major/minor opcodes i.e.
125 opcode[31:26,20:16]. The 6 MSBs of this value index into the following
126 array. The 4 LSBs select the bit-pair in the entry (bits 1:0 correspond to
127 LSBs==4'b0000 etc). */
128static unsigned long shmedia_opcode_table[64] = {
129 0x55554044,0x54445055,0x15141514,0x14541414,0x00000000,0x10001000,0x01110055,0x04050015,
130 0x00000444,0xc0000000,0x44545515,0x40405555,0x55550015,0x10005555,0x55555505,0x04050000,
131 0x00000555,0x00000404,0x00040445,0x15151414,0x00000000,0x00000000,0x00000000,0x00000000,
132 0x00000055,0x40404444,0x00000404,0xc0009495,0x00000000,0x00000000,0x00000000,0x00000000,
133 0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,
134 0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,
135 0x80005050,0x04005055,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,
136 0x81055554,0x00000404,0x55555555,0x55555555,0x00000000,0x00000000,0x00000000,0x00000000
137};
138
139void do_reserved_inst(unsigned long error_code, struct pt_regs *regs)
140{
141 /* Workaround SH5-101 cut2 silicon defect #2815 :
142 in some situations, inter-mode branches from SHcompact -> SHmedia
143 which should take ITLBMISS or EXECPROT exceptions at the target
144 falsely take RESINST at the target instead. */
145
146 unsigned long opcode = 0x6ff4fff0; /* guaranteed reserved opcode */
147 unsigned long pc, aligned_pc;
148 int get_user_error;
149 int trapnr = 12;
150 int signr = SIGILL;
151 char *exception_name = "reserved_instruction";
152
153 pc = regs->pc;
154 if ((pc & 3) == 1) {
155 /* SHmedia : check for defect. This requires executable vmas
156 to be readable too. */
157 aligned_pc = pc & ~3;
158 if (!access_ok(VERIFY_READ, aligned_pc, sizeof(unsigned long))) {
159 get_user_error = -EFAULT;
160 } else {
161 get_user_error = __get_user(opcode, (unsigned long *)aligned_pc);
162 }
163 if (get_user_error >= 0) {
164 unsigned long index, shift;
165 unsigned long major, minor, combined;
166 unsigned long reserved_field;
167 reserved_field = opcode & 0xf; /* These bits are currently reserved as zero in all valid opcodes */
168 major = (opcode >> 26) & 0x3f;
169 minor = (opcode >> 16) & 0xf;
170 combined = (major << 4) | minor;
171 index = major;
172 shift = minor << 1;
173 if (reserved_field == 0) {
174 int opcode_state = (shmedia_opcode_table[index] >> shift) & 0x3;
175 switch (opcode_state) {
176 case OPCODE_INVALID:
177 /* Trap. */
178 break;
179 case OPCODE_USER_VALID:
180 /* Restart the instruction : the branch to the instruction will now be from an RTE
181 not from SHcompact so the silicon defect won't be triggered. */
182 return;
183 case OPCODE_PRIV_VALID:
184 if (!user_mode(regs)) {
185 /* Should only ever get here if a module has
186 SHcompact code inside it. If so, the same fix up is needed. */
187 return; /* same reason */
188 }
189 /* Otherwise, user mode trying to execute a privileged instruction -
190 fall through to trap. */
191 break;
192 case OPCODE_CTRL_REG:
193 /* If in privileged mode, return as above. */
194 if (!user_mode(regs)) return;
195 /* In user mode ... */
196 if (combined == 0x9f) { /* GETCON */
197 unsigned long regno = (opcode >> 20) & 0x3f;
198 if (regno >= 62) {
199 return;
200 }
201 /* Otherwise, reserved or privileged control register, => trap */
202 } else if (combined == 0x1bf) { /* PUTCON */
203 unsigned long regno = (opcode >> 4) & 0x3f;
204 if (regno >= 62) {
205 return;
206 }
207 /* Otherwise, reserved or privileged control register, => trap */
208 } else {
209 /* Trap */
210 }
211 break;
212 default:
213 /* Fall through to trap. */
214 break;
215 }
216 }
217 /* fall through to normal resinst processing */
218 } else {
219 /* Error trying to read opcode. This typically means a
220 real fault, not a RESINST any more. So change the
221 codes. */
222 trapnr = 87;
223 exception_name = "address error (exec)";
224 signr = SIGSEGV;
225 }
226 }
227
228 do_unhandled_exception(trapnr, signr, exception_name, "do_reserved_inst", error_code, regs, current);
229}
230
231#else /* CONFIG_SH64_ID2815_WORKAROUND */
232
233/* If the workaround isn't needed, this is just a straightforward reserved
234 instruction */
235DO_ERROR(12, SIGILL, "reserved instruction", reserved_inst, current)
236
237#endif /* CONFIG_SH64_ID2815_WORKAROUND */
238
239/* Called with interrupts disabled */
240asmlinkage void do_exception_error(unsigned long ex, struct pt_regs *regs)
241{
242 show_excp_regs(__func__, -1, -1, regs);
243 die_if_kernel("exception", regs, ex);
244}
245
246int do_unknown_trapa(unsigned long scId, struct pt_regs *regs)
247{
248 /* Syscall debug */
249 printk("System call ID error: [0x1#args:8 #syscall:16 0x%lx]\n", scId);
250
251 die_if_kernel("unknown trapa", regs, scId);
252
253 return -ENOSYS;
254}
255
256void show_stack(struct task_struct *tsk, unsigned long *sp)
257{
258#ifdef CONFIG_KALLSYMS
259 extern void sh64_unwind(struct pt_regs *regs);
260 struct pt_regs *regs;
261
262 regs = tsk ? tsk->thread.kregs : NULL;
263
264 sh64_unwind(regs);
265#else
266 printk(KERN_ERR "Can't backtrace on sh64 without CONFIG_KALLSYMS\n");
267#endif
268}
269
270void show_task(unsigned long *sp)
271{
272 show_stack(NULL, sp);
273}
274
275void dump_stack(void)
276{
277 show_task(NULL);
278}
279/* Needed by any user of WARN_ON in view of the defn in include/asm-sh/bug.h */
280EXPORT_SYMBOL(dump_stack);
281
282static void do_unhandled_exception(int trapnr, int signr, char *str, char *fn_name,
283 unsigned long error_code, struct pt_regs *regs, struct task_struct *tsk)
284{
285 show_excp_regs(fn_name, trapnr, signr, regs);
286
287 if (user_mode(regs))
288 force_sig(signr, tsk);
289
290 die_if_no_fixup(str, regs, error_code);
291}
292
293static int read_opcode(unsigned long long pc, unsigned long *result_opcode, int from_user_mode)
294{ 36{
295 int get_user_error; 37 int get_user_error;
296 unsigned long aligned_pc; 38 unsigned long aligned_pc;
297 unsigned long opcode; 39 insn_size_t opcode;
298 40
299 if ((pc & 3) == 1) { 41 if ((pc & 3) == 1) {
300 /* SHmedia */ 42 /* SHmedia */
301 aligned_pc = pc & ~3; 43 aligned_pc = pc & ~3;
302 if (from_user_mode) { 44 if (from_user_mode) {
303 if (!access_ok(VERIFY_READ, aligned_pc, sizeof(unsigned long))) { 45 if (!access_ok(VERIFY_READ, aligned_pc, sizeof(insn_size_t))) {
304 get_user_error = -EFAULT; 46 get_user_error = -EFAULT;
305 } else { 47 } else {
306 get_user_error = __get_user(opcode, (unsigned long *)aligned_pc); 48 get_user_error = __get_user(opcode, (insn_size_t *)aligned_pc);
307 *result_opcode = opcode; 49 *result_opcode = opcode;
308 } 50 }
309 return get_user_error; 51 return get_user_error;
@@ -311,7 +53,7 @@ static int read_opcode(unsigned long long pc, unsigned long *result_opcode, int
311 /* If the fault was in the kernel, we can either read 53 /* If the fault was in the kernel, we can either read
312 * this directly, or if not, we fault. 54 * this directly, or if not, we fault.
313 */ 55 */
314 *result_opcode = *(unsigned long *) aligned_pc; 56 *result_opcode = *(insn_size_t *)aligned_pc;
315 return 0; 57 return 0;
316 } 58 }
317 } else if ((pc & 1) == 0) { 59 } else if ((pc & 1) == 0) {
@@ -337,17 +79,23 @@ static int address_is_sign_extended(__u64 a)
337#endif 79#endif
338} 80}
339 81
82/* return -1 for fault, 0 for OK */
340static int generate_and_check_address(struct pt_regs *regs, 83static int generate_and_check_address(struct pt_regs *regs,
341 __u32 opcode, 84 insn_size_t opcode,
342 int displacement_not_indexed, 85 int displacement_not_indexed,
343 int width_shift, 86 int width_shift,
344 __u64 *address) 87 __u64 *address)
345{ 88{
346 /* return -1 for fault, 0 for OK */
347
348 __u64 base_address, addr; 89 __u64 base_address, addr;
349 int basereg; 90 int basereg;
350 91
92 switch (1 << width_shift) {
93 case 1: inc_unaligned_byte_access(); break;
94 case 2: inc_unaligned_word_access(); break;
95 case 4: inc_unaligned_dword_access(); break;
96 case 8: inc_unaligned_multi_access(); break;
97 }
98
351 basereg = (opcode >> 20) & 0x3f; 99 basereg = (opcode >> 20) & 0x3f;
352 base_address = regs->regs[basereg]; 100 base_address = regs->regs[basereg];
353 if (displacement_not_indexed) { 101 if (displacement_not_indexed) {
@@ -364,28 +112,28 @@ static int generate_and_check_address(struct pt_regs *regs,
364 } 112 }
365 113
366 /* Check sign extended */ 114 /* Check sign extended */
367 if (!address_is_sign_extended(addr)) { 115 if (!address_is_sign_extended(addr))
368 return -1; 116 return -1;
369 }
370 117
371 /* Check accessible. For misaligned access in the kernel, assume the 118 /* Check accessible. For misaligned access in the kernel, assume the
372 address is always accessible (and if not, just fault when the 119 address is always accessible (and if not, just fault when the
373 load/store gets done.) */ 120 load/store gets done.) */
374 if (user_mode(regs)) { 121 if (user_mode(regs)) {
375 if (addr >= TASK_SIZE) { 122 inc_unaligned_user_access();
123
124 if (addr >= TASK_SIZE)
376 return -1; 125 return -1;
377 } 126 } else
378 /* Do access_ok check later - it depends on whether it's a load or a store. */ 127 inc_unaligned_kernel_access();
379 }
380 128
381 *address = addr; 129 *address = addr;
130
131 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, addr);
132 unaligned_fixups_notify(current, opcode, regs);
133
382 return 0; 134 return 0;
383} 135}
384 136
385static int user_mode_unaligned_fixup_count = 10;
386static int user_mode_unaligned_fixup_enable = 1;
387static int kernel_mode_unaligned_fixup_count = 32;
388
389static void misaligned_kernel_word_load(__u64 address, int do_sign_extend, __u64 *result) 137static void misaligned_kernel_word_load(__u64 address, int do_sign_extend, __u64 *result)
390{ 138{
391 unsigned short x; 139 unsigned short x;
@@ -415,7 +163,7 @@ static void misaligned_kernel_word_store(__u64 address, __u64 value)
415} 163}
416 164
417static int misaligned_load(struct pt_regs *regs, 165static int misaligned_load(struct pt_regs *regs,
418 __u32 opcode, 166 insn_size_t opcode,
419 int displacement_not_indexed, 167 int displacement_not_indexed,
420 int width_shift, 168 int width_shift,
421 int do_sign_extend) 169 int do_sign_extend)
@@ -427,11 +175,8 @@ static int misaligned_load(struct pt_regs *regs,
427 175
428 error = generate_and_check_address(regs, opcode, 176 error = generate_and_check_address(regs, opcode,
429 displacement_not_indexed, width_shift, &address); 177 displacement_not_indexed, width_shift, &address);
430 if (error < 0) { 178 if (error < 0)
431 return error; 179 return error;
432 }
433
434 perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, address);
435 180
436 destreg = (opcode >> 4) & 0x3f; 181 destreg = (opcode >> 4) & 0x3f;
437 if (user_mode(regs)) { 182 if (user_mode(regs)) {
@@ -490,11 +235,10 @@ static int misaligned_load(struct pt_regs *regs,
490 } 235 }
491 236
492 return 0; 237 return 0;
493
494} 238}
495 239
496static int misaligned_store(struct pt_regs *regs, 240static int misaligned_store(struct pt_regs *regs,
497 __u32 opcode, 241 insn_size_t opcode,
498 int displacement_not_indexed, 242 int displacement_not_indexed,
499 int width_shift) 243 int width_shift)
500{ 244{
@@ -505,11 +249,8 @@ static int misaligned_store(struct pt_regs *regs,
505 249
506 error = generate_and_check_address(regs, opcode, 250 error = generate_and_check_address(regs, opcode,
507 displacement_not_indexed, width_shift, &address); 251 displacement_not_indexed, width_shift, &address);
508 if (error < 0) { 252 if (error < 0)
509 return error; 253 return error;
510 }
511
512 perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, address);
513 254
514 srcreg = (opcode >> 4) & 0x3f; 255 srcreg = (opcode >> 4) & 0x3f;
515 if (user_mode(regs)) { 256 if (user_mode(regs)) {
@@ -563,13 +304,12 @@ static int misaligned_store(struct pt_regs *regs,
563 } 304 }
564 305
565 return 0; 306 return 0;
566
567} 307}
568 308
569/* Never need to fix up misaligned FPU accesses within the kernel since that's a real 309/* Never need to fix up misaligned FPU accesses within the kernel since that's a real
570 error. */ 310 error. */
571static int misaligned_fpu_load(struct pt_regs *regs, 311static int misaligned_fpu_load(struct pt_regs *regs,
572 __u32 opcode, 312 insn_size_t opcode,
573 int displacement_not_indexed, 313 int displacement_not_indexed,
574 int width_shift, 314 int width_shift,
575 int do_paired_load) 315 int do_paired_load)
@@ -581,11 +321,8 @@ static int misaligned_fpu_load(struct pt_regs *regs,
581 321
582 error = generate_and_check_address(regs, opcode, 322 error = generate_and_check_address(regs, opcode,
583 displacement_not_indexed, width_shift, &address); 323 displacement_not_indexed, width_shift, &address);
584 if (error < 0) { 324 if (error < 0)
585 return error; 325 return error;
586 }
587
588 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, address);
589 326
590 destreg = (opcode >> 4) & 0x3f; 327 destreg = (opcode >> 4) & 0x3f;
591 if (user_mode(regs)) { 328 if (user_mode(regs)) {
@@ -641,12 +378,10 @@ static int misaligned_fpu_load(struct pt_regs *regs,
641 die ("Misaligned FPU load inside kernel", regs, 0); 378 die ("Misaligned FPU load inside kernel", regs, 0);
642 return -1; 379 return -1;
643 } 380 }
644
645
646} 381}
647 382
648static int misaligned_fpu_store(struct pt_regs *regs, 383static int misaligned_fpu_store(struct pt_regs *regs,
649 __u32 opcode, 384 insn_size_t opcode,
650 int displacement_not_indexed, 385 int displacement_not_indexed,
651 int width_shift, 386 int width_shift,
652 int do_paired_load) 387 int do_paired_load)
@@ -658,11 +393,8 @@ static int misaligned_fpu_store(struct pt_regs *regs,
658 393
659 error = generate_and_check_address(regs, opcode, 394 error = generate_and_check_address(regs, opcode,
660 displacement_not_indexed, width_shift, &address); 395 displacement_not_indexed, width_shift, &address);
661 if (error < 0) { 396 if (error < 0)
662 return error; 397 return error;
663 }
664
665 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, address);
666 398
667 srcreg = (opcode >> 4) & 0x3f; 399 srcreg = (opcode >> 4) & 0x3f;
668 if (user_mode(regs)) { 400 if (user_mode(regs)) {
@@ -723,11 +455,13 @@ static int misaligned_fpu_store(struct pt_regs *regs,
723 455
724static int misaligned_fixup(struct pt_regs *regs) 456static int misaligned_fixup(struct pt_regs *regs)
725{ 457{
726 unsigned long opcode; 458 insn_size_t opcode;
727 int error; 459 int error;
728 int major, minor; 460 int major, minor;
461 unsigned int user_action;
729 462
730 if (!user_mode_unaligned_fixup_enable) 463 user_action = unaligned_user_action();
464 if (!(user_action & UM_FIXUP))
731 return -1; 465 return -1;
732 466
733 error = read_opcode(regs->pc, &opcode, user_mode(regs)); 467 error = read_opcode(regs->pc, &opcode, user_mode(regs));
@@ -737,23 +471,6 @@ static int misaligned_fixup(struct pt_regs *regs)
737 major = (opcode >> 26) & 0x3f; 471 major = (opcode >> 26) & 0x3f;
738 minor = (opcode >> 16) & 0xf; 472 minor = (opcode >> 16) & 0xf;
739 473
740 if (user_mode(regs) && (user_mode_unaligned_fixup_count > 0)) {
741 --user_mode_unaligned_fixup_count;
742 /* Only do 'count' worth of these reports, to remove a potential DoS against syslog */
743 printk("Fixing up unaligned userspace access in \"%s\" pid=%d pc=0x%08x ins=0x%08lx\n",
744 current->comm, task_pid_nr(current), (__u32)regs->pc, opcode);
745 } else if (!user_mode(regs) && (kernel_mode_unaligned_fixup_count > 0)) {
746 --kernel_mode_unaligned_fixup_count;
747 if (in_interrupt()) {
748 printk("Fixing up unaligned kernelspace access in interrupt pc=0x%08x ins=0x%08lx\n",
749 (__u32)regs->pc, opcode);
750 } else {
751 printk("Fixing up unaligned kernelspace access in \"%s\" pid=%d pc=0x%08x ins=0x%08lx\n",
752 current->comm, task_pid_nr(current), (__u32)regs->pc, opcode);
753 }
754 }
755
756
757 switch (major) { 474 switch (major) {
758 case (0x84>>2): /* LD.W */ 475 case (0x84>>2): /* LD.W */
759 error = misaligned_load(regs, opcode, 1, 1, 1); 476 error = misaligned_load(regs, opcode, 1, 1, 1);
@@ -878,59 +595,202 @@ static int misaligned_fixup(struct pt_regs *regs)
878 regs->pc += 4; /* Skip the instruction that's just been emulated */ 595 regs->pc += 4; /* Skip the instruction that's just been emulated */
879 return 0; 596 return 0;
880 } 597 }
598}
599
600static void do_unhandled_exception(int signr, char *str, unsigned long error,
601 struct pt_regs *regs)
602{
603 if (user_mode(regs))
604 force_sig(signr, current);
881 605
606 die_if_no_fixup(str, regs, error);
882} 607}
883 608
884static ctl_table unaligned_table[] = { 609#define DO_ERROR(signr, str, name) \
885 { 610asmlinkage void do_##name(unsigned long error_code, struct pt_regs *regs) \
886 .procname = "kernel_reports", 611{ \
887 .data = &kernel_mode_unaligned_fixup_count, 612 do_unhandled_exception(signr, str, error_code, regs); \
888 .maxlen = sizeof(int), 613}
889 .mode = 0644,
890 .proc_handler = proc_dointvec
891 },
892 {
893 .procname = "user_reports",
894 .data = &user_mode_unaligned_fixup_count,
895 .maxlen = sizeof(int),
896 .mode = 0644,
897 .proc_handler = proc_dointvec
898 },
899 {
900 .procname = "user_enable",
901 .data = &user_mode_unaligned_fixup_enable,
902 .maxlen = sizeof(int),
903 .mode = 0644,
904 .proc_handler = proc_dointvec},
905 {}
906};
907 614
908static ctl_table unaligned_root[] = { 615DO_ERROR(SIGILL, "illegal slot instruction", illegal_slot_inst)
909 { 616DO_ERROR(SIGSEGV, "address error (exec)", address_error_exec)
910 .procname = "unaligned_fixup", 617
911 .mode = 0555, 618#if defined(CONFIG_SH64_ID2815_WORKAROUND)
912 .child = unaligned_table 619
913 }, 620#define OPCODE_INVALID 0
914 {} 621#define OPCODE_USER_VALID 1
915}; 622#define OPCODE_PRIV_VALID 2
916 623
917static ctl_table sh64_root[] = { 624/* getcon/putcon - requires checking which control register is referenced. */
918 { 625#define OPCODE_CTRL_REG 3
919 .procname = "sh64", 626
920 .mode = 0555, 627/* Table of valid opcodes for SHmedia mode.
921 .child = unaligned_root 628 Form a 10-bit value by concatenating the major/minor opcodes i.e.
922 }, 629 opcode[31:26,20:16]. The 6 MSBs of this value index into the following
923 {} 630 array. The 4 LSBs select the bit-pair in the entry (bits 1:0 correspond to
631 LSBs==4'b0000 etc). */
632static unsigned long shmedia_opcode_table[64] = {
633 0x55554044,0x54445055,0x15141514,0x14541414,0x00000000,0x10001000,0x01110055,0x04050015,
634 0x00000444,0xc0000000,0x44545515,0x40405555,0x55550015,0x10005555,0x55555505,0x04050000,
635 0x00000555,0x00000404,0x00040445,0x15151414,0x00000000,0x00000000,0x00000000,0x00000000,
636 0x00000055,0x40404444,0x00000404,0xc0009495,0x00000000,0x00000000,0x00000000,0x00000000,
637 0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,
638 0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,
639 0x80005050,0x04005055,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,
640 0x81055554,0x00000404,0x55555555,0x55555555,0x00000000,0x00000000,0x00000000,0x00000000
924}; 641};
925static struct ctl_table_header *sysctl_header; 642
926static int __init init_sysctl(void) 643/* Workaround SH5-101 cut2 silicon defect #2815 :
644 in some situations, inter-mode branches from SHcompact -> SHmedia
645 which should take ITLBMISS or EXECPROT exceptions at the target
646 falsely take RESINST at the target instead. */
647void do_reserved_inst(unsigned long error_code, struct pt_regs *regs)
927{ 648{
928 sysctl_header = register_sysctl_table(sh64_root); 649 insn_size_t opcode = 0x6ff4fff0; /* guaranteed reserved opcode */
929 return 0; 650 unsigned long pc, aligned_pc;
651 unsigned long index, shift;
652 unsigned long major, minor, combined;
653 unsigned long reserved_field;
654 int opcode_state;
655 int get_user_error;
656 int signr = SIGILL;
657 char *exception_name = "reserved_instruction";
658
659 pc = regs->pc;
660
661 /* SHcompact is not handled */
662 if (unlikely((pc & 3) == 0))
663 goto out;
664
665 /* SHmedia : check for defect. This requires executable vmas
666 to be readable too. */
667 aligned_pc = pc & ~3;
668 if (!access_ok(VERIFY_READ, aligned_pc, sizeof(insn_size_t)))
669 get_user_error = -EFAULT;
670 else
671 get_user_error = __get_user(opcode, (insn_size_t *)aligned_pc);
672
673 if (get_user_error < 0) {
674 /*
675 * Error trying to read opcode. This typically means a
676 * real fault, not a RESINST any more. So change the
677 * codes.
678 */
679 exception_name = "address error (exec)";
680 signr = SIGSEGV;
681 goto out;
682 }
683
684 /* These bits are currently reserved as zero in all valid opcodes */
685 reserved_field = opcode & 0xf;
686 if (unlikely(reserved_field))
687 goto out; /* invalid opcode */
688
689 major = (opcode >> 26) & 0x3f;
690 minor = (opcode >> 16) & 0xf;
691 combined = (major << 4) | minor;
692 index = major;
693 shift = minor << 1;
694 opcode_state = (shmedia_opcode_table[index] >> shift) & 0x3;
695 switch (opcode_state) {
696 case OPCODE_INVALID:
697 /* Trap. */
698 break;
699 case OPCODE_USER_VALID:
700 /*
701 * Restart the instruction: the branch to the instruction
702 * will now be from an RTE not from SHcompact so the
703 * silicon defect won't be triggered.
704 */
705 return;
706 case OPCODE_PRIV_VALID:
707 if (!user_mode(regs)) {
708 /*
709 * Should only ever get here if a module has
710 * SHcompact code inside it. If so, the same fix
711 * up is needed.
712 */
713 return; /* same reason */
714 }
715
716 /*
717 * Otherwise, user mode trying to execute a privileged
718 * instruction - fall through to trap.
719 */
720 break;
721 case OPCODE_CTRL_REG:
722 /* If in privileged mode, return as above. */
723 if (!user_mode(regs))
724 return;
725
726 /* In user mode ... */
727 if (combined == 0x9f) { /* GETCON */
728 unsigned long regno = (opcode >> 20) & 0x3f;
729
730 if (regno >= 62)
731 return;
732
733 /* reserved/privileged control register => trap */
734 } else if (combined == 0x1bf) { /* PUTCON */
735 unsigned long regno = (opcode >> 4) & 0x3f;
736
737 if (regno >= 62)
738 return;
739
740 /* reserved/privileged control register => trap */
741 }
742
743 break;
744 default:
745 /* Fall through to trap. */
746 break;
747 }
748
749out:
750 do_unhandled_exception(signr, exception_name, error_code, regs);
930} 751}
931 752
932__initcall(init_sysctl); 753#else /* CONFIG_SH64_ID2815_WORKAROUND */
933 754
755/* If the workaround isn't needed, this is just a straightforward reserved
756 instruction */
757DO_ERROR(SIGILL, "reserved instruction", reserved_inst)
758
759#endif /* CONFIG_SH64_ID2815_WORKAROUND */
760
761/* Called with interrupts disabled */
762asmlinkage void do_exception_error(unsigned long ex, struct pt_regs *regs)
763{
764 die_if_kernel("exception", regs, ex);
765}
766
767asmlinkage int do_unknown_trapa(unsigned long scId, struct pt_regs *regs)
768{
769 /* Syscall debug */
770 printk("System call ID error: [0x1#args:8 #syscall:16 0x%lx]\n", scId);
771
772 die_if_kernel("unknown trapa", regs, scId);
773
774 return -ENOSYS;
775}
776
777/* Implement misaligned load/store handling for kernel (and optionally for user
778 mode too). Limitation : only SHmedia mode code is handled - there is no
779 handling at all for misaligned accesses occurring in SHcompact code yet. */
780
781asmlinkage void do_address_error_load(unsigned long error_code, struct pt_regs *regs)
782{
783 if (misaligned_fixup(regs) < 0)
784 do_unhandled_exception(SIGSEGV, "address error(load)",
785 error_code, regs);
786}
787
788asmlinkage void do_address_error_store(unsigned long error_code, struct pt_regs *regs)
789{
790 if (misaligned_fixup(regs) < 0)
791 do_unhandled_exception(SIGSEGV, "address error(store)",
792 error_code, regs);
793}
934 794
935asmlinkage void do_debug_interrupt(unsigned long code, struct pt_regs *regs) 795asmlinkage void do_debug_interrupt(unsigned long code, struct pt_regs *regs)
936{ 796{
@@ -942,10 +802,9 @@ asmlinkage void do_debug_interrupt(unsigned long code, struct pt_regs *regs)
942 of access we make to them - just go direct to their physical 802 of access we make to them - just go direct to their physical
943 addresses. */ 803 addresses. */
944 exp_cause = peek_real_address_q(DM_EXP_CAUSE_PHY); 804 exp_cause = peek_real_address_q(DM_EXP_CAUSE_PHY);
945 if (exp_cause & ~4) { 805 if (exp_cause & ~4)
946 printk("DM.EXP_CAUSE had unexpected bits set (=%08lx)\n", 806 printk("DM.EXP_CAUSE had unexpected bits set (=%08lx)\n",
947 (unsigned long)(exp_cause & 0xffffffff)); 807 (unsigned long)(exp_cause & 0xffffffff));
948 }
949 show_state(); 808 show_state();
950 /* Clear all DEBUGINT causes */ 809 /* Clear all DEBUGINT causes */
951 poke_real_address_q(DM_EXP_CAUSE_PHY, 0x0); 810 poke_real_address_q(DM_EXP_CAUSE_PHY, 0x0);
diff --git a/arch/sh/lib64/Makefile b/arch/sh/lib64/Makefile
index 1fee75aa1f9..69779ff741d 100644
--- a/arch/sh/lib64/Makefile
+++ b/arch/sh/lib64/Makefile
@@ -10,7 +10,7 @@
10# 10#
11 11
12# Panic should really be compiled as PIC 12# Panic should really be compiled as PIC
13lib-y := udelay.o dbg.o panic.o memcpy.o memset.o \ 13lib-y := udelay.o panic.o memcpy.o memset.o \
14 copy_user_memcpy.o copy_page.o strcpy.o strlen.o 14 copy_user_memcpy.o copy_page.o strcpy.o strlen.o
15 15
16# Extracted from libgcc 16# Extracted from libgcc
diff --git a/arch/sh/lib64/dbg.c b/arch/sh/lib64/dbg.c
deleted file mode 100644
index 6152a6a6d9c..00000000000
--- a/arch/sh/lib64/dbg.c
+++ /dev/null
@@ -1,248 +0,0 @@
1/*--------------------------------------------------------------------------
2--
3-- Identity : Linux50 Debug Funcions
4--
5-- File : arch/sh/lib64/dbg.c
6--
7-- Copyright 2000, 2001 STMicroelectronics Limited.
8-- Copyright 2004 Richard Curnow (evt_debug etc)
9--
10--------------------------------------------------------------------------*/
11#include <linux/types.h>
12#include <linux/kernel.h>
13#include <linux/sched.h>
14#include <linux/mm.h>
15#include <linux/fs.h>
16#include <asm/mmu_context.h>
17
18typedef u64 regType_t;
19
20static regType_t getConfigReg(u64 id)
21{
22 register u64 reg __asm__("r2");
23 asm volatile ("getcfg %1, 0, %0":"=r" (reg):"r"(id));
24 return (reg);
25}
26
27/* ======================================================================= */
28
29static char *szTab[] = { "4k", "64k", "1M", "512M" };
30static char *protTab[] = { "----",
31 "---R",
32 "--X-",
33 "--XR",
34 "-W--",
35 "-W-R",
36 "-WX-",
37 "-WXR",
38 "U---",
39 "U--R",
40 "U-X-",
41 "U-XR",
42 "UW--",
43 "UW-R",
44 "UWX-",
45 "UWXR"
46};
47#define ITLB_BASE 0x00000000
48#define DTLB_BASE 0x00800000
49#define MAX_TLBs 64
50/* PTE High */
51#define GET_VALID(pte) ((pte) & 0x1)
52#define GET_SHARED(pte) ((pte) & 0x2)
53#define GET_ASID(pte) ((pte >> 2) & 0x0ff)
54#define GET_EPN(pte) ((pte) & 0xfffff000)
55
56/* PTE Low */
57#define GET_CBEHAVIOR(pte) ((pte) & 0x3)
58#define GET_PAGE_SIZE(pte) szTab[((pte >> 3) & 0x3)]
59#define GET_PROTECTION(pte) protTab[((pte >> 6) & 0xf)]
60#define GET_PPN(pte) ((pte) & 0xfffff000)
61
62#define PAGE_1K_MASK 0x00000000
63#define PAGE_4K_MASK 0x00000010
64#define PAGE_64K_MASK 0x00000080
65#define MMU_PAGESIZE_MASK (PAGE_64K_MASK | PAGE_4K_MASK)
66#define PAGE_1MB_MASK MMU_PAGESIZE_MASK
67#define PAGE_1K (1024)
68#define PAGE_4K (1024 * 4)
69#define PAGE_64K (1024 * 64)
70#define PAGE_1MB (1024 * 1024)
71
72#define HOW_TO_READ_TLB_CONTENT \
73 "[ ID] PPN EPN ASID Share CB P.Size PROT.\n"
74
75void print_single_tlb(unsigned long tlb, int single_print)
76{
77 regType_t pteH;
78 regType_t pteL;
79 unsigned int valid, shared, asid, epn, cb, ppn;
80 char *pSize;
81 char *pProt;
82
83 /*
84 ** in case of single print <single_print> is true, this implies:
85 ** 1) print the TLB in any case also if NOT VALID
86 ** 2) print out the header
87 */
88
89 pteH = getConfigReg(tlb);
90 valid = GET_VALID(pteH);
91 if (single_print)
92 printk(HOW_TO_READ_TLB_CONTENT);
93 else if (!valid)
94 return;
95
96 pteL = getConfigReg(tlb + 1);
97
98 shared = GET_SHARED(pteH);
99 asid = GET_ASID(pteH);
100 epn = GET_EPN(pteH);
101 cb = GET_CBEHAVIOR(pteL);
102 pSize = GET_PAGE_SIZE(pteL);
103 pProt = GET_PROTECTION(pteL);
104 ppn = GET_PPN(pteL);
105 printk("[%c%2ld] 0x%08x 0x%08x %03d %02x %02x %4s %s\n",
106 ((valid) ? ' ' : 'u'), ((tlb & 0x0ffff) / TLB_STEP),
107 ppn, epn, asid, shared, cb, pSize, pProt);
108}
109
110void print_dtlb(void)
111{
112 int count;
113 unsigned long tlb;
114
115 printk(" ================= SH-5 D-TLBs Status ===================\n");
116 printk(HOW_TO_READ_TLB_CONTENT);
117 tlb = DTLB_BASE;
118 for (count = 0; count < MAX_TLBs; count++, tlb += TLB_STEP)
119 print_single_tlb(tlb, 0);
120 printk
121 (" =============================================================\n");
122}
123
124void print_itlb(void)
125{
126 int count;
127 unsigned long tlb;
128
129 printk(" ================= SH-5 I-TLBs Status ===================\n");
130 printk(HOW_TO_READ_TLB_CONTENT);
131 tlb = ITLB_BASE;
132 for (count = 0; count < MAX_TLBs; count++, tlb += TLB_STEP)
133 print_single_tlb(tlb, 0);
134 printk
135 (" =============================================================\n");
136}
137
138void show_excp_regs(char *from, int trapnr, int signr, struct pt_regs *regs)
139{
140
141 unsigned long long ah, al, bh, bl, ch, cl;
142
143 printk("\n");
144 printk("EXCEPTION - %s: task %d; Linux trap # %d; signal = %d\n",
145 ((from) ? from : "???"), current->pid, trapnr, signr);
146
147 asm volatile ("getcon " __EXPEVT ", %0":"=r"(ah));
148 asm volatile ("getcon " __EXPEVT ", %0":"=r"(al));
149 ah = (ah) >> 32;
150 al = (al) & 0xffffffff;
151 asm volatile ("getcon " __KCR1 ", %0":"=r"(bh));
152 asm volatile ("getcon " __KCR1 ", %0":"=r"(bl));
153 bh = (bh) >> 32;
154 bl = (bl) & 0xffffffff;
155 asm volatile ("getcon " __INTEVT ", %0":"=r"(ch));
156 asm volatile ("getcon " __INTEVT ", %0":"=r"(cl));
157 ch = (ch) >> 32;
158 cl = (cl) & 0xffffffff;
159 printk("EXPE: %08Lx%08Lx KCR1: %08Lx%08Lx INTE: %08Lx%08Lx\n",
160 ah, al, bh, bl, ch, cl);
161
162 asm volatile ("getcon " __PEXPEVT ", %0":"=r"(ah));
163 asm volatile ("getcon " __PEXPEVT ", %0":"=r"(al));
164 ah = (ah) >> 32;
165 al = (al) & 0xffffffff;
166 asm volatile ("getcon " __PSPC ", %0":"=r"(bh));
167 asm volatile ("getcon " __PSPC ", %0":"=r"(bl));
168 bh = (bh) >> 32;
169 bl = (bl) & 0xffffffff;
170 asm volatile ("getcon " __PSSR ", %0":"=r"(ch));
171 asm volatile ("getcon " __PSSR ", %0":"=r"(cl));
172 ch = (ch) >> 32;
173 cl = (cl) & 0xffffffff;
174 printk("PEXP: %08Lx%08Lx PSPC: %08Lx%08Lx PSSR: %08Lx%08Lx\n",
175 ah, al, bh, bl, ch, cl);
176
177 ah = (regs->pc) >> 32;
178 al = (regs->pc) & 0xffffffff;
179 bh = (regs->regs[18]) >> 32;
180 bl = (regs->regs[18]) & 0xffffffff;
181 ch = (regs->regs[15]) >> 32;
182 cl = (regs->regs[15]) & 0xffffffff;
183 printk("PC : %08Lx%08Lx LINK: %08Lx%08Lx SP : %08Lx%08Lx\n",
184 ah, al, bh, bl, ch, cl);
185
186 ah = (regs->sr) >> 32;
187 al = (regs->sr) & 0xffffffff;
188 asm volatile ("getcon " __TEA ", %0":"=r"(bh));
189 asm volatile ("getcon " __TEA ", %0":"=r"(bl));
190 bh = (bh) >> 32;
191 bl = (bl) & 0xffffffff;
192 asm volatile ("getcon " __KCR0 ", %0":"=r"(ch));
193 asm volatile ("getcon " __KCR0 ", %0":"=r"(cl));
194 ch = (ch) >> 32;
195 cl = (cl) & 0xffffffff;
196 printk("SR : %08Lx%08Lx TEA : %08Lx%08Lx KCR0: %08Lx%08Lx\n",
197 ah, al, bh, bl, ch, cl);
198
199 ah = (regs->regs[0]) >> 32;
200 al = (regs->regs[0]) & 0xffffffff;
201 bh = (regs->regs[1]) >> 32;
202 bl = (regs->regs[1]) & 0xffffffff;
203 ch = (regs->regs[2]) >> 32;
204 cl = (regs->regs[2]) & 0xffffffff;
205 printk("R0 : %08Lx%08Lx R1 : %08Lx%08Lx R2 : %08Lx%08Lx\n",
206 ah, al, bh, bl, ch, cl);
207
208 ah = (regs->regs[3]) >> 32;
209 al = (regs->regs[3]) & 0xffffffff;
210 bh = (regs->regs[4]) >> 32;
211 bl = (regs->regs[4]) & 0xffffffff;
212 ch = (regs->regs[5]) >> 32;
213 cl = (regs->regs[5]) & 0xffffffff;
214 printk("R3 : %08Lx%08Lx R4 : %08Lx%08Lx R5 : %08Lx%08Lx\n",
215 ah, al, bh, bl, ch, cl);
216
217 ah = (regs->regs[6]) >> 32;
218 al = (regs->regs[6]) & 0xffffffff;
219 bh = (regs->regs[7]) >> 32;
220 bl = (regs->regs[7]) & 0xffffffff;
221 ch = (regs->regs[8]) >> 32;
222 cl = (regs->regs[8]) & 0xffffffff;
223 printk("R6 : %08Lx%08Lx R7 : %08Lx%08Lx R8 : %08Lx%08Lx\n",
224 ah, al, bh, bl, ch, cl);
225
226 ah = (regs->regs[9]) >> 32;
227 al = (regs->regs[9]) & 0xffffffff;
228 bh = (regs->regs[10]) >> 32;
229 bl = (regs->regs[10]) & 0xffffffff;
230 ch = (regs->regs[11]) >> 32;
231 cl = (regs->regs[11]) & 0xffffffff;
232 printk("R9 : %08Lx%08Lx R10 : %08Lx%08Lx R11 : %08Lx%08Lx\n",
233 ah, al, bh, bl, ch, cl);
234 printk("....\n");
235
236 ah = (regs->tregs[0]) >> 32;
237 al = (regs->tregs[0]) & 0xffffffff;
238 bh = (regs->tregs[1]) >> 32;
239 bl = (regs->tregs[1]) & 0xffffffff;
240 ch = (regs->tregs[2]) >> 32;
241 cl = (regs->tregs[2]) & 0xffffffff;
242 printk("T0 : %08Lx%08Lx T1 : %08Lx%08Lx T2 : %08Lx%08Lx\n",
243 ah, al, bh, bl, ch, cl);
244 printk("....\n");
245
246 print_dtlb();
247 print_itlb();
248}
diff --git a/arch/sh/mm/tlb-sh5.c b/arch/sh/mm/tlb-sh5.c
index 3aea25dc431..ff1c40a31cb 100644
--- a/arch/sh/mm/tlb-sh5.c
+++ b/arch/sh/mm/tlb-sh5.c
@@ -17,7 +17,7 @@
17/** 17/**
18 * sh64_tlb_init - Perform initial setup for the DTLB and ITLB. 18 * sh64_tlb_init - Perform initial setup for the DTLB and ITLB.
19 */ 19 */
20int __init sh64_tlb_init(void) 20int __cpuinit sh64_tlb_init(void)
21{ 21{
22 /* Assign some sane DTLB defaults */ 22 /* Assign some sane DTLB defaults */
23 cpu_data->dtlb.entries = 64; 23 cpu_data->dtlb.entries = 64;
diff --git a/drivers/sh/Kconfig b/drivers/sh/Kconfig
index f168a615996..d860ef74356 100644
--- a/drivers/sh/Kconfig
+++ b/drivers/sh/Kconfig
@@ -1,5 +1,6 @@
1menu "SuperH / SH-Mobile Driver Options" 1menu "SuperH / SH-Mobile Driver Options"
2 2
3source "drivers/sh/intc/Kconfig" 3source "drivers/sh/intc/Kconfig"
4source "drivers/sh/pfc/Kconfig"
4 5
5endmenu 6endmenu
diff --git a/drivers/sh/Makefile b/drivers/sh/Makefile
index 7139ad2f208..e57895b1a42 100644
--- a/drivers/sh/Makefile
+++ b/drivers/sh/Makefile
@@ -5,6 +5,7 @@ obj-y := intc/
5 5
6obj-$(CONFIG_HAVE_CLK) += clk/ 6obj-$(CONFIG_HAVE_CLK) += clk/
7obj-$(CONFIG_MAPLE) += maple/ 7obj-$(CONFIG_MAPLE) += maple/
8obj-$(CONFIG_SH_PFC) += pfc/
8obj-$(CONFIG_SUPERHYWAY) += superhyway/ 9obj-$(CONFIG_SUPERHYWAY) += superhyway/
9obj-$(CONFIG_GENERIC_GPIO) += pfc.o 10
10obj-y += pm_runtime.o 11obj-y += pm_runtime.o
diff --git a/drivers/sh/clk/cpg.c b/drivers/sh/clk/cpg.c
index f0d015dd0fe..07e9fb4f804 100644
--- a/drivers/sh/clk/cpg.c
+++ b/drivers/sh/clk/cpg.c
@@ -14,6 +14,8 @@
14#include <linux/io.h> 14#include <linux/io.h>
15#include <linux/sh_clk.h> 15#include <linux/sh_clk.h>
16 16
17#define CPG_CKSTP_BIT BIT(8)
18
17static unsigned int sh_clk_read(struct clk *clk) 19static unsigned int sh_clk_read(struct clk *clk)
18{ 20{
19 if (clk->flags & CLK_ENABLE_REG_8BIT) 21 if (clk->flags & CLK_ENABLE_REG_8BIT)
@@ -66,71 +68,43 @@ int __init sh_clk_mstp_register(struct clk *clks, int nr)
66 return ret; 68 return ret;
67} 69}
68 70
69static long sh_clk_div_round_rate(struct clk *clk, unsigned long rate) 71/*
72 * Div/mult table lookup helpers
73 */
74static inline struct clk_div_table *clk_to_div_table(struct clk *clk)
70{ 75{
71 return clk_rate_table_round(clk, clk->freq_table, rate); 76 return clk->priv;
72} 77}
73 78
74static int sh_clk_div6_divisors[64] = { 79static inline struct clk_div_mult_table *clk_to_div_mult_table(struct clk *clk)
75 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 80{
76 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 81 return clk_to_div_table(clk)->div_mult_table;
77 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 82}
78 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64
79};
80 83
81static struct clk_div_mult_table sh_clk_div6_table = { 84/*
82 .divisors = sh_clk_div6_divisors, 85 * Common div ops
83 .nr_divisors = ARRAY_SIZE(sh_clk_div6_divisors), 86 */
84}; 87static long sh_clk_div_round_rate(struct clk *clk, unsigned long rate)
88{
89 return clk_rate_table_round(clk, clk->freq_table, rate);
90}
85 91
86static unsigned long sh_clk_div6_recalc(struct clk *clk) 92static unsigned long sh_clk_div_recalc(struct clk *clk)
87{ 93{
88 struct clk_div_mult_table *table = &sh_clk_div6_table; 94 struct clk_div_mult_table *table = clk_to_div_mult_table(clk);
89 unsigned int idx; 95 unsigned int idx;
90 96
91 clk_rate_table_build(clk, clk->freq_table, table->nr_divisors, 97 clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
92 table, NULL); 98 table, clk->arch_flags ? &clk->arch_flags : NULL);
93 99
94 idx = sh_clk_read(clk) & 0x003f; 100 idx = (sh_clk_read(clk) >> clk->enable_bit) & clk->div_mask;
95 101
96 return clk->freq_table[idx].frequency; 102 return clk->freq_table[idx].frequency;
97} 103}
98 104
99static int sh_clk_div6_set_parent(struct clk *clk, struct clk *parent) 105static int sh_clk_div_set_rate(struct clk *clk, unsigned long rate)
100{
101 struct clk_div_mult_table *table = &sh_clk_div6_table;
102 u32 value;
103 int ret, i;
104
105 if (!clk->parent_table || !clk->parent_num)
106 return -EINVAL;
107
108 /* Search the parent */
109 for (i = 0; i < clk->parent_num; i++)
110 if (clk->parent_table[i] == parent)
111 break;
112
113 if (i == clk->parent_num)
114 return -ENODEV;
115
116 ret = clk_reparent(clk, parent);
117 if (ret < 0)
118 return ret;
119
120 value = sh_clk_read(clk) &
121 ~(((1 << clk->src_width) - 1) << clk->src_shift);
122
123 sh_clk_write(value | (i << clk->src_shift), clk);
124
125 /* Rebuild the frequency table */
126 clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
127 table, NULL);
128
129 return 0;
130}
131
132static int sh_clk_div6_set_rate(struct clk *clk, unsigned long rate)
133{ 106{
107 struct clk_div_table *dt = clk_to_div_table(clk);
134 unsigned long value; 108 unsigned long value;
135 int idx; 109 int idx;
136 110
@@ -139,51 +113,53 @@ static int sh_clk_div6_set_rate(struct clk *clk, unsigned long rate)
139 return idx; 113 return idx;
140 114
141 value = sh_clk_read(clk); 115 value = sh_clk_read(clk);
142 value &= ~0x3f; 116 value &= ~(clk->div_mask << clk->enable_bit);
143 value |= idx; 117 value |= (idx << clk->enable_bit);
144 sh_clk_write(value, clk); 118 sh_clk_write(value, clk);
119
120 /* XXX: Should use a post-change notifier */
121 if (dt->kick)
122 dt->kick(clk);
123
145 return 0; 124 return 0;
146} 125}
147 126
148static int sh_clk_div6_enable(struct clk *clk) 127static int sh_clk_div_enable(struct clk *clk)
149{ 128{
150 unsigned long value; 129 sh_clk_write(sh_clk_read(clk) & ~CPG_CKSTP_BIT, clk);
151 int ret; 130 return 0;
152
153 ret = sh_clk_div6_set_rate(clk, clk->rate);
154 if (ret == 0) {
155 value = sh_clk_read(clk);
156 value &= ~0x100; /* clear stop bit to enable clock */
157 sh_clk_write(value, clk);
158 }
159 return ret;
160} 131}
161 132
162static void sh_clk_div6_disable(struct clk *clk) 133static void sh_clk_div_disable(struct clk *clk)
163{ 134{
164 unsigned long value; 135 unsigned int val;
165 136
166 value = sh_clk_read(clk); 137 val = sh_clk_read(clk);
167 value |= 0x100; /* stop clock */ 138 val |= CPG_CKSTP_BIT;
168 value |= 0x3f; /* VDIV bits must be non-zero, overwrite divider */ 139
169 sh_clk_write(value, clk); 140 /*
141 * div6 clocks require the divisor field to be non-zero or the
142 * above CKSTP toggle silently fails. Ensure that the divisor
143 * array is reset to its initial state on disable.
144 */
145 if (clk->flags & CLK_MASK_DIV_ON_DISABLE)
146 val |= clk->div_mask;
147
148 sh_clk_write(val, clk);
170} 149}
171 150
172static struct sh_clk_ops sh_clk_div6_clk_ops = { 151static struct sh_clk_ops sh_clk_div_clk_ops = {
173 .recalc = sh_clk_div6_recalc, 152 .recalc = sh_clk_div_recalc,
153 .set_rate = sh_clk_div_set_rate,
174 .round_rate = sh_clk_div_round_rate, 154 .round_rate = sh_clk_div_round_rate,
175 .set_rate = sh_clk_div6_set_rate,
176 .enable = sh_clk_div6_enable,
177 .disable = sh_clk_div6_disable,
178}; 155};
179 156
180static struct sh_clk_ops sh_clk_div6_reparent_clk_ops = { 157static struct sh_clk_ops sh_clk_div_enable_clk_ops = {
181 .recalc = sh_clk_div6_recalc, 158 .recalc = sh_clk_div_recalc,
159 .set_rate = sh_clk_div_set_rate,
182 .round_rate = sh_clk_div_round_rate, 160 .round_rate = sh_clk_div_round_rate,
183 .set_rate = sh_clk_div6_set_rate, 161 .enable = sh_clk_div_enable,
184 .enable = sh_clk_div6_enable, 162 .disable = sh_clk_div_disable,
185 .disable = sh_clk_div6_disable,
186 .set_parent = sh_clk_div6_set_parent,
187}; 163};
188 164
189static int __init sh_clk_init_parent(struct clk *clk) 165static int __init sh_clk_init_parent(struct clk *clk)
@@ -218,12 +194,12 @@ static int __init sh_clk_init_parent(struct clk *clk)
218 return 0; 194 return 0;
219} 195}
220 196
221static int __init sh_clk_div6_register_ops(struct clk *clks, int nr, 197static int __init sh_clk_div_register_ops(struct clk *clks, int nr,
222 struct sh_clk_ops *ops) 198 struct clk_div_table *table, struct sh_clk_ops *ops)
223{ 199{
224 struct clk *clkp; 200 struct clk *clkp;
225 void *freq_table; 201 void *freq_table;
226 int nr_divs = sh_clk_div6_table.nr_divisors; 202 int nr_divs = table->div_mult_table->nr_divisors;
227 int freq_table_size = sizeof(struct cpufreq_frequency_table); 203 int freq_table_size = sizeof(struct cpufreq_frequency_table);
228 int ret = 0; 204 int ret = 0;
229 int k; 205 int k;
@@ -231,7 +207,7 @@ static int __init sh_clk_div6_register_ops(struct clk *clks, int nr,
231 freq_table_size *= (nr_divs + 1); 207 freq_table_size *= (nr_divs + 1);
232 freq_table = kzalloc(freq_table_size * nr, GFP_KERNEL); 208 freq_table = kzalloc(freq_table_size * nr, GFP_KERNEL);
233 if (!freq_table) { 209 if (!freq_table) {
234 pr_err("sh_clk_div6_register: unable to alloc memory\n"); 210 pr_err("%s: unable to alloc memory\n", __func__);
235 return -ENOMEM; 211 return -ENOMEM;
236 } 212 }
237 213
@@ -239,47 +215,98 @@ static int __init sh_clk_div6_register_ops(struct clk *clks, int nr,
239 clkp = clks + k; 215 clkp = clks + k;
240 216
241 clkp->ops = ops; 217 clkp->ops = ops;
218 clkp->priv = table;
219
242 clkp->freq_table = freq_table + (k * freq_table_size); 220 clkp->freq_table = freq_table + (k * freq_table_size);
243 clkp->freq_table[nr_divs].frequency = CPUFREQ_TABLE_END; 221 clkp->freq_table[nr_divs].frequency = CPUFREQ_TABLE_END;
244 ret = clk_register(clkp);
245 if (ret < 0)
246 break;
247 222
248 ret = sh_clk_init_parent(clkp); 223 ret = clk_register(clkp);
224 if (ret == 0)
225 ret = sh_clk_init_parent(clkp);
249 } 226 }
250 227
251 return ret; 228 return ret;
252} 229}
253 230
254int __init sh_clk_div6_register(struct clk *clks, int nr) 231/*
255{ 232 * div6 support
256 return sh_clk_div6_register_ops(clks, nr, &sh_clk_div6_clk_ops); 233 */
257} 234static int sh_clk_div6_divisors[64] = {
235 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
236 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
237 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
238 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64
239};
258 240
259int __init sh_clk_div6_reparent_register(struct clk *clks, int nr) 241static struct clk_div_mult_table div6_div_mult_table = {
260{ 242 .divisors = sh_clk_div6_divisors,
261 return sh_clk_div6_register_ops(clks, nr, 243 .nr_divisors = ARRAY_SIZE(sh_clk_div6_divisors),
262 &sh_clk_div6_reparent_clk_ops); 244};
263}
264 245
265static unsigned long sh_clk_div4_recalc(struct clk *clk) 246static struct clk_div_table sh_clk_div6_table = {
247 .div_mult_table = &div6_div_mult_table,
248};
249
250static int sh_clk_div6_set_parent(struct clk *clk, struct clk *parent)
266{ 251{
267 struct clk_div4_table *d4t = clk->priv; 252 struct clk_div_mult_table *table = clk_to_div_mult_table(clk);
268 struct clk_div_mult_table *table = d4t->div_mult_table; 253 u32 value;
269 unsigned int idx; 254 int ret, i;
270 255
256 if (!clk->parent_table || !clk->parent_num)
257 return -EINVAL;
258
259 /* Search the parent */
260 for (i = 0; i < clk->parent_num; i++)
261 if (clk->parent_table[i] == parent)
262 break;
263
264 if (i == clk->parent_num)
265 return -ENODEV;
266
267 ret = clk_reparent(clk, parent);
268 if (ret < 0)
269 return ret;
270
271 value = sh_clk_read(clk) &
272 ~(((1 << clk->src_width) - 1) << clk->src_shift);
273
274 sh_clk_write(value | (i << clk->src_shift), clk);
275
276 /* Rebuild the frequency table */
271 clk_rate_table_build(clk, clk->freq_table, table->nr_divisors, 277 clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
272 table, &clk->arch_flags); 278 table, NULL);
273 279
274 idx = (sh_clk_read(clk) >> clk->enable_bit) & 0x000f; 280 return 0;
281}
275 282
276 return clk->freq_table[idx].frequency; 283static struct sh_clk_ops sh_clk_div6_reparent_clk_ops = {
284 .recalc = sh_clk_div_recalc,
285 .round_rate = sh_clk_div_round_rate,
286 .set_rate = sh_clk_div_set_rate,
287 .enable = sh_clk_div_enable,
288 .disable = sh_clk_div_disable,
289 .set_parent = sh_clk_div6_set_parent,
290};
291
292int __init sh_clk_div6_register(struct clk *clks, int nr)
293{
294 return sh_clk_div_register_ops(clks, nr, &sh_clk_div6_table,
295 &sh_clk_div_enable_clk_ops);
296}
297
298int __init sh_clk_div6_reparent_register(struct clk *clks, int nr)
299{
300 return sh_clk_div_register_ops(clks, nr, &sh_clk_div6_table,
301 &sh_clk_div6_reparent_clk_ops);
277} 302}
278 303
304/*
305 * div4 support
306 */
279static int sh_clk_div4_set_parent(struct clk *clk, struct clk *parent) 307static int sh_clk_div4_set_parent(struct clk *clk, struct clk *parent)
280{ 308{
281 struct clk_div4_table *d4t = clk->priv; 309 struct clk_div_mult_table *table = clk_to_div_mult_table(clk);
282 struct clk_div_mult_table *table = d4t->div_mult_table;
283 u32 value; 310 u32 value;
284 int ret; 311 int ret;
285 312
@@ -306,107 +333,31 @@ static int sh_clk_div4_set_parent(struct clk *clk, struct clk *parent)
306 return 0; 333 return 0;
307} 334}
308 335
309static int sh_clk_div4_set_rate(struct clk *clk, unsigned long rate)
310{
311 struct clk_div4_table *d4t = clk->priv;
312 unsigned long value;
313 int idx = clk_rate_table_find(clk, clk->freq_table, rate);
314 if (idx < 0)
315 return idx;
316
317 value = sh_clk_read(clk);
318 value &= ~(0xf << clk->enable_bit);
319 value |= (idx << clk->enable_bit);
320 sh_clk_write(value, clk);
321
322 if (d4t->kick)
323 d4t->kick(clk);
324
325 return 0;
326}
327
328static int sh_clk_div4_enable(struct clk *clk)
329{
330 sh_clk_write(sh_clk_read(clk) & ~(1 << 8), clk);
331 return 0;
332}
333
334static void sh_clk_div4_disable(struct clk *clk)
335{
336 sh_clk_write(sh_clk_read(clk) | (1 << 8), clk);
337}
338
339static struct sh_clk_ops sh_clk_div4_clk_ops = {
340 .recalc = sh_clk_div4_recalc,
341 .set_rate = sh_clk_div4_set_rate,
342 .round_rate = sh_clk_div_round_rate,
343};
344
345static struct sh_clk_ops sh_clk_div4_enable_clk_ops = {
346 .recalc = sh_clk_div4_recalc,
347 .set_rate = sh_clk_div4_set_rate,
348 .round_rate = sh_clk_div_round_rate,
349 .enable = sh_clk_div4_enable,
350 .disable = sh_clk_div4_disable,
351};
352
353static struct sh_clk_ops sh_clk_div4_reparent_clk_ops = { 336static struct sh_clk_ops sh_clk_div4_reparent_clk_ops = {
354 .recalc = sh_clk_div4_recalc, 337 .recalc = sh_clk_div_recalc,
355 .set_rate = sh_clk_div4_set_rate, 338 .set_rate = sh_clk_div_set_rate,
356 .round_rate = sh_clk_div_round_rate, 339 .round_rate = sh_clk_div_round_rate,
357 .enable = sh_clk_div4_enable, 340 .enable = sh_clk_div_enable,
358 .disable = sh_clk_div4_disable, 341 .disable = sh_clk_div_disable,
359 .set_parent = sh_clk_div4_set_parent, 342 .set_parent = sh_clk_div4_set_parent,
360}; 343};
361 344
362static int __init sh_clk_div4_register_ops(struct clk *clks, int nr,
363 struct clk_div4_table *table, struct sh_clk_ops *ops)
364{
365 struct clk *clkp;
366 void *freq_table;
367 int nr_divs = table->div_mult_table->nr_divisors;
368 int freq_table_size = sizeof(struct cpufreq_frequency_table);
369 int ret = 0;
370 int k;
371
372 freq_table_size *= (nr_divs + 1);
373 freq_table = kzalloc(freq_table_size * nr, GFP_KERNEL);
374 if (!freq_table) {
375 pr_err("sh_clk_div4_register: unable to alloc memory\n");
376 return -ENOMEM;
377 }
378
379 for (k = 0; !ret && (k < nr); k++) {
380 clkp = clks + k;
381
382 clkp->ops = ops;
383 clkp->priv = table;
384
385 clkp->freq_table = freq_table + (k * freq_table_size);
386 clkp->freq_table[nr_divs].frequency = CPUFREQ_TABLE_END;
387
388 ret = clk_register(clkp);
389 }
390
391 return ret;
392}
393
394int __init sh_clk_div4_register(struct clk *clks, int nr, 345int __init sh_clk_div4_register(struct clk *clks, int nr,
395 struct clk_div4_table *table) 346 struct clk_div4_table *table)
396{ 347{
397 return sh_clk_div4_register_ops(clks, nr, table, &sh_clk_div4_clk_ops); 348 return sh_clk_div_register_ops(clks, nr, table, &sh_clk_div_clk_ops);
398} 349}
399 350
400int __init sh_clk_div4_enable_register(struct clk *clks, int nr, 351int __init sh_clk_div4_enable_register(struct clk *clks, int nr,
401 struct clk_div4_table *table) 352 struct clk_div4_table *table)
402{ 353{
403 return sh_clk_div4_register_ops(clks, nr, table, 354 return sh_clk_div_register_ops(clks, nr, table,
404 &sh_clk_div4_enable_clk_ops); 355 &sh_clk_div_enable_clk_ops);
405} 356}
406 357
407int __init sh_clk_div4_reparent_register(struct clk *clks, int nr, 358int __init sh_clk_div4_reparent_register(struct clk *clks, int nr,
408 struct clk_div4_table *table) 359 struct clk_div4_table *table)
409{ 360{
410 return sh_clk_div4_register_ops(clks, nr, table, 361 return sh_clk_div_register_ops(clks, nr, table,
411 &sh_clk_div4_reparent_clk_ops); 362 &sh_clk_div4_reparent_clk_ops);
412} 363}
diff --git a/drivers/sh/intc/Makefile b/drivers/sh/intc/Makefile
index bb5df868d77..44f006d0947 100644
--- a/drivers/sh/intc/Makefile
+++ b/drivers/sh/intc/Makefile
@@ -1,4 +1,4 @@
1obj-y := access.o chip.o core.o dynamic.o handle.o virq.o 1obj-y := access.o chip.o core.o handle.o virq.o
2 2
3obj-$(CONFIG_INTC_BALANCING) += balancing.o 3obj-$(CONFIG_INTC_BALANCING) += balancing.o
4obj-$(CONFIG_INTC_USERIMASK) += userimask.o 4obj-$(CONFIG_INTC_USERIMASK) += userimask.o
diff --git a/drivers/sh/intc/dynamic.c b/drivers/sh/intc/dynamic.c
deleted file mode 100644
index 14eb01ef5d7..00000000000
--- a/drivers/sh/intc/dynamic.c
+++ /dev/null
@@ -1,57 +0,0 @@
1/*
2 * Dynamic IRQ management
3 *
4 * Copyright (C) 2010 Paul Mundt
5 *
6 * Modelled after arch/x86/kernel/apic/io_apic.c
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12#define pr_fmt(fmt) "intc: " fmt
13
14#include <linux/irq.h>
15#include <linux/bitmap.h>
16#include <linux/spinlock.h>
17#include <linux/module.h>
18#include "internals.h" /* only for activate_irq() damage.. */
19
20/*
21 * The IRQ bitmap provides a global map of bound IRQ vectors for a
22 * given platform. Allocation of IRQs are either static through the CPU
23 * vector map, or dynamic in the case of board mux vectors or MSI.
24 *
25 * As this is a central point for all IRQ controllers on the system,
26 * each of the available sources are mapped out here. This combined with
27 * sparseirq makes it quite trivial to keep the vector map tightly packed
28 * when dynamically creating IRQs, as well as tying in to otherwise
29 * unused irq_desc positions in the sparse array.
30 */
31
32/*
33 * Dynamic IRQ allocation and deallocation
34 */
35unsigned int create_irq_nr(unsigned int irq_want, int node)
36{
37 int irq = irq_alloc_desc_at(irq_want, node);
38 if (irq < 0)
39 return 0;
40
41 activate_irq(irq);
42 return irq;
43}
44
45int create_irq(void)
46{
47 int irq = irq_alloc_desc(numa_node_id());
48 if (irq >= 0)
49 activate_irq(irq);
50
51 return irq;
52}
53
54void destroy_irq(unsigned int irq)
55{
56 irq_free_desc(irq);
57}
diff --git a/drivers/sh/intc/virq.c b/drivers/sh/intc/virq.c
index 93cec21e788..f30ac9354ff 100644
--- a/drivers/sh/intc/virq.c
+++ b/drivers/sh/intc/virq.c
@@ -219,12 +219,14 @@ restart:
219 if (radix_tree_deref_retry(entry)) 219 if (radix_tree_deref_retry(entry))
220 goto restart; 220 goto restart;
221 221
222 irq = create_irq(); 222 irq = irq_alloc_desc(numa_node_id());
223 if (unlikely(irq < 0)) { 223 if (unlikely(irq < 0)) {
224 pr_err("no more free IRQs, bailing..\n"); 224 pr_err("no more free IRQs, bailing..\n");
225 break; 225 break;
226 } 226 }
227 227
228 activate_irq(irq);
229
228 pr_info("Setting up a chained VIRQ from %d -> %d\n", 230 pr_info("Setting up a chained VIRQ from %d -> %d\n",
229 irq, entry->pirq); 231 irq, entry->pirq);
230 232
diff --git a/drivers/sh/pfc.c b/drivers/sh/pfc.c
deleted file mode 100644
index 522c6c46d1b..00000000000
--- a/drivers/sh/pfc.c
+++ /dev/null
@@ -1,739 +0,0 @@
1/*
2 * Pinmuxed GPIO support for SuperH.
3 *
4 * Copyright (C) 2008 Magnus Damm
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
11
12#include <linux/errno.h>
13#include <linux/kernel.h>
14#include <linux/list.h>
15#include <linux/module.h>
16#include <linux/clk.h>
17#include <linux/err.h>
18#include <linux/io.h>
19#include <linux/irq.h>
20#include <linux/bitops.h>
21#include <linux/gpio.h>
22#include <linux/slab.h>
23#include <linux/ioport.h>
24
25static void pfc_iounmap(struct pinmux_info *pip)
26{
27 int k;
28
29 for (k = 0; k < pip->num_resources; k++)
30 if (pip->window[k].virt)
31 iounmap(pip->window[k].virt);
32
33 kfree(pip->window);
34 pip->window = NULL;
35}
36
37static int pfc_ioremap(struct pinmux_info *pip)
38{
39 struct resource *res;
40 int k;
41
42 if (!pip->num_resources)
43 return 0;
44
45 pip->window = kzalloc(pip->num_resources * sizeof(*pip->window),
46 GFP_NOWAIT);
47 if (!pip->window)
48 goto err1;
49
50 for (k = 0; k < pip->num_resources; k++) {
51 res = pip->resource + k;
52 WARN_ON(resource_type(res) != IORESOURCE_MEM);
53 pip->window[k].phys = res->start;
54 pip->window[k].size = resource_size(res);
55 pip->window[k].virt = ioremap_nocache(res->start,
56 resource_size(res));
57 if (!pip->window[k].virt)
58 goto err2;
59 }
60
61 return 0;
62
63err2:
64 pfc_iounmap(pip);
65err1:
66 return -1;
67}
68
69static void __iomem *pfc_phys_to_virt(struct pinmux_info *pip,
70 unsigned long address)
71{
72 struct pfc_window *window;
73 int k;
74
75 /* scan through physical windows and convert address */
76 for (k = 0; k < pip->num_resources; k++) {
77 window = pip->window + k;
78
79 if (address < window->phys)
80 continue;
81
82 if (address >= (window->phys + window->size))
83 continue;
84
85 return window->virt + (address - window->phys);
86 }
87
88 /* no windows defined, register must be 1:1 mapped virt:phys */
89 return (void __iomem *)address;
90}
91
92static int enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r)
93{
94 if (enum_id < r->begin)
95 return 0;
96
97 if (enum_id > r->end)
98 return 0;
99
100 return 1;
101}
102
103static unsigned long gpio_read_raw_reg(void __iomem *mapped_reg,
104 unsigned long reg_width)
105{
106 switch (reg_width) {
107 case 8:
108 return ioread8(mapped_reg);
109 case 16:
110 return ioread16(mapped_reg);
111 case 32:
112 return ioread32(mapped_reg);
113 }
114
115 BUG();
116 return 0;
117}
118
119static void gpio_write_raw_reg(void __iomem *mapped_reg,
120 unsigned long reg_width,
121 unsigned long data)
122{
123 switch (reg_width) {
124 case 8:
125 iowrite8(data, mapped_reg);
126 return;
127 case 16:
128 iowrite16(data, mapped_reg);
129 return;
130 case 32:
131 iowrite32(data, mapped_reg);
132 return;
133 }
134
135 BUG();
136}
137
138static int gpio_read_bit(struct pinmux_data_reg *dr,
139 unsigned long in_pos)
140{
141 unsigned long pos;
142
143 pos = dr->reg_width - (in_pos + 1);
144
145 pr_debug("read_bit: addr = %lx, pos = %ld, "
146 "r_width = %ld\n", dr->reg, pos, dr->reg_width);
147
148 return (gpio_read_raw_reg(dr->mapped_reg, dr->reg_width) >> pos) & 1;
149}
150
151static void gpio_write_bit(struct pinmux_data_reg *dr,
152 unsigned long in_pos, unsigned long value)
153{
154 unsigned long pos;
155
156 pos = dr->reg_width - (in_pos + 1);
157
158 pr_debug("write_bit addr = %lx, value = %d, pos = %ld, "
159 "r_width = %ld\n",
160 dr->reg, !!value, pos, dr->reg_width);
161
162 if (value)
163 set_bit(pos, &dr->reg_shadow);
164 else
165 clear_bit(pos, &dr->reg_shadow);
166
167 gpio_write_raw_reg(dr->mapped_reg, dr->reg_width, dr->reg_shadow);
168}
169
170static void config_reg_helper(struct pinmux_info *gpioc,
171 struct pinmux_cfg_reg *crp,
172 unsigned long in_pos,
173 void __iomem **mapped_regp,
174 unsigned long *maskp,
175 unsigned long *posp)
176{
177 int k;
178
179 *mapped_regp = pfc_phys_to_virt(gpioc, crp->reg);
180
181 if (crp->field_width) {
182 *maskp = (1 << crp->field_width) - 1;
183 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
184 } else {
185 *maskp = (1 << crp->var_field_width[in_pos]) - 1;
186 *posp = crp->reg_width;
187 for (k = 0; k <= in_pos; k++)
188 *posp -= crp->var_field_width[k];
189 }
190}
191
192static int read_config_reg(struct pinmux_info *gpioc,
193 struct pinmux_cfg_reg *crp,
194 unsigned long field)
195{
196 void __iomem *mapped_reg;
197 unsigned long mask, pos;
198
199 config_reg_helper(gpioc, crp, field, &mapped_reg, &mask, &pos);
200
201 pr_debug("read_reg: addr = %lx, field = %ld, "
202 "r_width = %ld, f_width = %ld\n",
203 crp->reg, field, crp->reg_width, crp->field_width);
204
205 return (gpio_read_raw_reg(mapped_reg, crp->reg_width) >> pos) & mask;
206}
207
208static void write_config_reg(struct pinmux_info *gpioc,
209 struct pinmux_cfg_reg *crp,
210 unsigned long field, unsigned long value)
211{
212 void __iomem *mapped_reg;
213 unsigned long mask, pos, data;
214
215 config_reg_helper(gpioc, crp, field, &mapped_reg, &mask, &pos);
216
217 pr_debug("write_reg addr = %lx, value = %ld, field = %ld, "
218 "r_width = %ld, f_width = %ld\n",
219 crp->reg, value, field, crp->reg_width, crp->field_width);
220
221 mask = ~(mask << pos);
222 value = value << pos;
223
224 data = gpio_read_raw_reg(mapped_reg, crp->reg_width);
225 data &= mask;
226 data |= value;
227
228 if (gpioc->unlock_reg)
229 gpio_write_raw_reg(pfc_phys_to_virt(gpioc, gpioc->unlock_reg),
230 32, ~data);
231
232 gpio_write_raw_reg(mapped_reg, crp->reg_width, data);
233}
234
235static int setup_data_reg(struct pinmux_info *gpioc, unsigned gpio)
236{
237 struct pinmux_gpio *gpiop = &gpioc->gpios[gpio];
238 struct pinmux_data_reg *data_reg;
239 int k, n;
240
241 if (!enum_in_range(gpiop->enum_id, &gpioc->data))
242 return -1;
243
244 k = 0;
245 while (1) {
246 data_reg = gpioc->data_regs + k;
247
248 if (!data_reg->reg_width)
249 break;
250
251 data_reg->mapped_reg = pfc_phys_to_virt(gpioc, data_reg->reg);
252
253 for (n = 0; n < data_reg->reg_width; n++) {
254 if (data_reg->enum_ids[n] == gpiop->enum_id) {
255 gpiop->flags &= ~PINMUX_FLAG_DREG;
256 gpiop->flags |= (k << PINMUX_FLAG_DREG_SHIFT);
257 gpiop->flags &= ~PINMUX_FLAG_DBIT;
258 gpiop->flags |= (n << PINMUX_FLAG_DBIT_SHIFT);
259 return 0;
260 }
261 }
262 k++;
263 }
264
265 BUG();
266
267 return -1;
268}
269
270static void setup_data_regs(struct pinmux_info *gpioc)
271{
272 struct pinmux_data_reg *drp;
273 int k;
274
275 for (k = gpioc->first_gpio; k <= gpioc->last_gpio; k++)
276 setup_data_reg(gpioc, k);
277
278 k = 0;
279 while (1) {
280 drp = gpioc->data_regs + k;
281
282 if (!drp->reg_width)
283 break;
284
285 drp->reg_shadow = gpio_read_raw_reg(drp->mapped_reg,
286 drp->reg_width);
287 k++;
288 }
289}
290
291static int get_data_reg(struct pinmux_info *gpioc, unsigned gpio,
292 struct pinmux_data_reg **drp, int *bitp)
293{
294 struct pinmux_gpio *gpiop = &gpioc->gpios[gpio];
295 int k, n;
296
297 if (!enum_in_range(gpiop->enum_id, &gpioc->data))
298 return -1;
299
300 k = (gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT;
301 n = (gpiop->flags & PINMUX_FLAG_DBIT) >> PINMUX_FLAG_DBIT_SHIFT;
302 *drp = gpioc->data_regs + k;
303 *bitp = n;
304 return 0;
305}
306
307static int get_config_reg(struct pinmux_info *gpioc, pinmux_enum_t enum_id,
308 struct pinmux_cfg_reg **crp,
309 int *fieldp, int *valuep,
310 unsigned long **cntp)
311{
312 struct pinmux_cfg_reg *config_reg;
313 unsigned long r_width, f_width, curr_width, ncomb;
314 int k, m, n, pos, bit_pos;
315
316 k = 0;
317 while (1) {
318 config_reg = gpioc->cfg_regs + k;
319
320 r_width = config_reg->reg_width;
321 f_width = config_reg->field_width;
322
323 if (!r_width)
324 break;
325
326 pos = 0;
327 m = 0;
328 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
329 if (f_width)
330 curr_width = f_width;
331 else
332 curr_width = config_reg->var_field_width[m];
333
334 ncomb = 1 << curr_width;
335 for (n = 0; n < ncomb; n++) {
336 if (config_reg->enum_ids[pos + n] == enum_id) {
337 *crp = config_reg;
338 *fieldp = m;
339 *valuep = n;
340 *cntp = &config_reg->cnt[m];
341 return 0;
342 }
343 }
344 pos += ncomb;
345 m++;
346 }
347 k++;
348 }
349
350 return -1;
351}
352
353static int get_gpio_enum_id(struct pinmux_info *gpioc, unsigned gpio,
354 int pos, pinmux_enum_t *enum_idp)
355{
356 pinmux_enum_t enum_id = gpioc->gpios[gpio].enum_id;
357 pinmux_enum_t *data = gpioc->gpio_data;
358 int k;
359
360 if (!enum_in_range(enum_id, &gpioc->data)) {
361 if (!enum_in_range(enum_id, &gpioc->mark)) {
362 pr_err("non data/mark enum_id for gpio %d\n", gpio);
363 return -1;
364 }
365 }
366
367 if (pos) {
368 *enum_idp = data[pos + 1];
369 return pos + 1;
370 }
371
372 for (k = 0; k < gpioc->gpio_data_size; k++) {
373 if (data[k] == enum_id) {
374 *enum_idp = data[k + 1];
375 return k + 1;
376 }
377 }
378
379 pr_err("cannot locate data/mark enum_id for gpio %d\n", gpio);
380 return -1;
381}
382
383enum { GPIO_CFG_DRYRUN, GPIO_CFG_REQ, GPIO_CFG_FREE };
384
385static int pinmux_config_gpio(struct pinmux_info *gpioc, unsigned gpio,
386 int pinmux_type, int cfg_mode)
387{
388 struct pinmux_cfg_reg *cr = NULL;
389 pinmux_enum_t enum_id;
390 struct pinmux_range *range;
391 int in_range, pos, field, value;
392 unsigned long *cntp;
393
394 switch (pinmux_type) {
395
396 case PINMUX_TYPE_FUNCTION:
397 range = NULL;
398 break;
399
400 case PINMUX_TYPE_OUTPUT:
401 range = &gpioc->output;
402 break;
403
404 case PINMUX_TYPE_INPUT:
405 range = &gpioc->input;
406 break;
407
408 case PINMUX_TYPE_INPUT_PULLUP:
409 range = &gpioc->input_pu;
410 break;
411
412 case PINMUX_TYPE_INPUT_PULLDOWN:
413 range = &gpioc->input_pd;
414 break;
415
416 default:
417 goto out_err;
418 }
419
420 pos = 0;
421 enum_id = 0;
422 field = 0;
423 value = 0;
424 while (1) {
425 pos = get_gpio_enum_id(gpioc, gpio, pos, &enum_id);
426 if (pos <= 0)
427 goto out_err;
428
429 if (!enum_id)
430 break;
431
432 /* first check if this is a function enum */
433 in_range = enum_in_range(enum_id, &gpioc->function);
434 if (!in_range) {
435 /* not a function enum */
436 if (range) {
437 /*
438 * other range exists, so this pin is
439 * a regular GPIO pin that now is being
440 * bound to a specific direction.
441 *
442 * for this case we only allow function enums
443 * and the enums that match the other range.
444 */
445 in_range = enum_in_range(enum_id, range);
446
447 /*
448 * special case pass through for fixed
449 * input-only or output-only pins without
450 * function enum register association.
451 */
452 if (in_range && enum_id == range->force)
453 continue;
454 } else {
455 /*
456 * no other range exists, so this pin
457 * must then be of the function type.
458 *
459 * allow function type pins to select
460 * any combination of function/in/out
461 * in their MARK lists.
462 */
463 in_range = 1;
464 }
465 }
466
467 if (!in_range)
468 continue;
469
470 if (get_config_reg(gpioc, enum_id, &cr,
471 &field, &value, &cntp) != 0)
472 goto out_err;
473
474 switch (cfg_mode) {
475 case GPIO_CFG_DRYRUN:
476 if (!*cntp ||
477 (read_config_reg(gpioc, cr, field) != value))
478 continue;
479 break;
480
481 case GPIO_CFG_REQ:
482 write_config_reg(gpioc, cr, field, value);
483 *cntp = *cntp + 1;
484 break;
485
486 case GPIO_CFG_FREE:
487 *cntp = *cntp - 1;
488 break;
489 }
490 }
491
492 return 0;
493 out_err:
494 return -1;
495}
496
497static DEFINE_SPINLOCK(gpio_lock);
498
499static struct pinmux_info *chip_to_pinmux(struct gpio_chip *chip)
500{
501 return container_of(chip, struct pinmux_info, chip);
502}
503
504static int sh_gpio_request(struct gpio_chip *chip, unsigned offset)
505{
506 struct pinmux_info *gpioc = chip_to_pinmux(chip);
507 struct pinmux_data_reg *dummy;
508 unsigned long flags;
509 int i, ret, pinmux_type;
510
511 ret = -EINVAL;
512
513 if (!gpioc)
514 goto err_out;
515
516 spin_lock_irqsave(&gpio_lock, flags);
517
518 if ((gpioc->gpios[offset].flags & PINMUX_FLAG_TYPE) != PINMUX_TYPE_NONE)
519 goto err_unlock;
520
521 /* setup pin function here if no data is associated with pin */
522
523 if (get_data_reg(gpioc, offset, &dummy, &i) != 0)
524 pinmux_type = PINMUX_TYPE_FUNCTION;
525 else
526 pinmux_type = PINMUX_TYPE_GPIO;
527
528 if (pinmux_type == PINMUX_TYPE_FUNCTION) {
529 if (pinmux_config_gpio(gpioc, offset,
530 pinmux_type,
531 GPIO_CFG_DRYRUN) != 0)
532 goto err_unlock;
533
534 if (pinmux_config_gpio(gpioc, offset,
535 pinmux_type,
536 GPIO_CFG_REQ) != 0)
537 BUG();
538 }
539
540 gpioc->gpios[offset].flags &= ~PINMUX_FLAG_TYPE;
541 gpioc->gpios[offset].flags |= pinmux_type;
542
543 ret = 0;
544 err_unlock:
545 spin_unlock_irqrestore(&gpio_lock, flags);
546 err_out:
547 return ret;
548}
549
550static void sh_gpio_free(struct gpio_chip *chip, unsigned offset)
551{
552 struct pinmux_info *gpioc = chip_to_pinmux(chip);
553 unsigned long flags;
554 int pinmux_type;
555
556 if (!gpioc)
557 return;
558
559 spin_lock_irqsave(&gpio_lock, flags);
560
561 pinmux_type = gpioc->gpios[offset].flags & PINMUX_FLAG_TYPE;
562 pinmux_config_gpio(gpioc, offset, pinmux_type, GPIO_CFG_FREE);
563 gpioc->gpios[offset].flags &= ~PINMUX_FLAG_TYPE;
564 gpioc->gpios[offset].flags |= PINMUX_TYPE_NONE;
565
566 spin_unlock_irqrestore(&gpio_lock, flags);
567}
568
569static int pinmux_direction(struct pinmux_info *gpioc,
570 unsigned gpio, int new_pinmux_type)
571{
572 int pinmux_type;
573 int ret = -EINVAL;
574
575 if (!gpioc)
576 goto err_out;
577
578 pinmux_type = gpioc->gpios[gpio].flags & PINMUX_FLAG_TYPE;
579
580 switch (pinmux_type) {
581 case PINMUX_TYPE_GPIO:
582 break;
583 case PINMUX_TYPE_OUTPUT:
584 case PINMUX_TYPE_INPUT:
585 case PINMUX_TYPE_INPUT_PULLUP:
586 case PINMUX_TYPE_INPUT_PULLDOWN:
587 pinmux_config_gpio(gpioc, gpio, pinmux_type, GPIO_CFG_FREE);
588 break;
589 default:
590 goto err_out;
591 }
592
593 if (pinmux_config_gpio(gpioc, gpio,
594 new_pinmux_type,
595 GPIO_CFG_DRYRUN) != 0)
596 goto err_out;
597
598 if (pinmux_config_gpio(gpioc, gpio,
599 new_pinmux_type,
600 GPIO_CFG_REQ) != 0)
601 BUG();
602
603 gpioc->gpios[gpio].flags &= ~PINMUX_FLAG_TYPE;
604 gpioc->gpios[gpio].flags |= new_pinmux_type;
605
606 ret = 0;
607 err_out:
608 return ret;
609}
610
611static int sh_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
612{
613 struct pinmux_info *gpioc = chip_to_pinmux(chip);
614 unsigned long flags;
615 int ret;
616
617 spin_lock_irqsave(&gpio_lock, flags);
618 ret = pinmux_direction(gpioc, offset, PINMUX_TYPE_INPUT);
619 spin_unlock_irqrestore(&gpio_lock, flags);
620
621 return ret;
622}
623
624static void sh_gpio_set_value(struct pinmux_info *gpioc,
625 unsigned gpio, int value)
626{
627 struct pinmux_data_reg *dr = NULL;
628 int bit = 0;
629
630 if (!gpioc || get_data_reg(gpioc, gpio, &dr, &bit) != 0)
631 BUG();
632 else
633 gpio_write_bit(dr, bit, value);
634}
635
636static int sh_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
637 int value)
638{
639 struct pinmux_info *gpioc = chip_to_pinmux(chip);
640 unsigned long flags;
641 int ret;
642
643 sh_gpio_set_value(gpioc, offset, value);
644 spin_lock_irqsave(&gpio_lock, flags);
645 ret = pinmux_direction(gpioc, offset, PINMUX_TYPE_OUTPUT);
646 spin_unlock_irqrestore(&gpio_lock, flags);
647
648 return ret;
649}
650
651static int sh_gpio_get_value(struct pinmux_info *gpioc, unsigned gpio)
652{
653 struct pinmux_data_reg *dr = NULL;
654 int bit = 0;
655
656 if (!gpioc || get_data_reg(gpioc, gpio, &dr, &bit) != 0)
657 return -EINVAL;
658
659 return gpio_read_bit(dr, bit);
660}
661
662static int sh_gpio_get(struct gpio_chip *chip, unsigned offset)
663{
664 return sh_gpio_get_value(chip_to_pinmux(chip), offset);
665}
666
667static void sh_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
668{
669 sh_gpio_set_value(chip_to_pinmux(chip), offset, value);
670}
671
672static int sh_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
673{
674 struct pinmux_info *gpioc = chip_to_pinmux(chip);
675 pinmux_enum_t enum_id;
676 pinmux_enum_t *enum_ids;
677 int i, k, pos;
678
679 pos = 0;
680 enum_id = 0;
681 while (1) {
682 pos = get_gpio_enum_id(gpioc, offset, pos, &enum_id);
683 if (pos <= 0 || !enum_id)
684 break;
685
686 for (i = 0; i < gpioc->gpio_irq_size; i++) {
687 enum_ids = gpioc->gpio_irq[i].enum_ids;
688 for (k = 0; enum_ids[k]; k++) {
689 if (enum_ids[k] == enum_id)
690 return gpioc->gpio_irq[i].irq;
691 }
692 }
693 }
694
695 return -ENOSYS;
696}
697
698int register_pinmux(struct pinmux_info *pip)
699{
700 struct gpio_chip *chip = &pip->chip;
701 int ret;
702
703 pr_info("%s handling gpio %d -> %d\n",
704 pip->name, pip->first_gpio, pip->last_gpio);
705
706 ret = pfc_ioremap(pip);
707 if (ret < 0)
708 return ret;
709
710 setup_data_regs(pip);
711
712 chip->request = sh_gpio_request;
713 chip->free = sh_gpio_free;
714 chip->direction_input = sh_gpio_direction_input;
715 chip->get = sh_gpio_get;
716 chip->direction_output = sh_gpio_direction_output;
717 chip->set = sh_gpio_set;
718 chip->to_irq = sh_gpio_to_irq;
719
720 WARN_ON(pip->first_gpio != 0); /* needs testing */
721
722 chip->label = pip->name;
723 chip->owner = THIS_MODULE;
724 chip->base = pip->first_gpio;
725 chip->ngpio = (pip->last_gpio - pip->first_gpio) + 1;
726
727 ret = gpiochip_add(chip);
728 if (ret < 0)
729 pfc_iounmap(pip);
730
731 return ret;
732}
733
734int unregister_pinmux(struct pinmux_info *pip)
735{
736 pr_info("%s deregistering\n", pip->name);
737 pfc_iounmap(pip);
738 return gpiochip_remove(&pip->chip);
739}
diff --git a/drivers/sh/pfc/Kconfig b/drivers/sh/pfc/Kconfig
new file mode 100644
index 00000000000..804f9ad1bf4
--- /dev/null
+++ b/drivers/sh/pfc/Kconfig
@@ -0,0 +1,26 @@
1comment "Pin function controller options"
2
3config SH_PFC
4 # XXX move off the gpio dependency
5 depends on GENERIC_GPIO
6 select GPIO_SH_PFC if ARCH_REQUIRE_GPIOLIB
7 select PINCTRL_SH_PFC
8 def_bool y
9
10#
11# Placeholder for now, rehome to drivers/pinctrl once the PFC APIs
12# have settled.
13#
14config PINCTRL_SH_PFC
15 tristate "SuperH PFC pin controller driver"
16 depends on SH_PFC
17 select PINCTRL
18 select PINMUX
19 select PINCONF
20
21config GPIO_SH_PFC
22 tristate "SuperH PFC GPIO support"
23 depends on SH_PFC && GPIOLIB
24 help
25 This enables support for GPIOs within the SoC's pin function
26 controller.
diff --git a/drivers/sh/pfc/Makefile b/drivers/sh/pfc/Makefile
new file mode 100644
index 00000000000..7916027cce3
--- /dev/null
+++ b/drivers/sh/pfc/Makefile
@@ -0,0 +1,3 @@
1obj-y += core.o
2obj-$(CONFIG_PINCTRL_SH_PFC) += pinctrl.o
3obj-$(CONFIG_GPIO_SH_PFC) += gpio.o
diff --git a/drivers/sh/pfc/core.c b/drivers/sh/pfc/core.c
new file mode 100644
index 00000000000..68169373c98
--- /dev/null
+++ b/drivers/sh/pfc/core.c
@@ -0,0 +1,572 @@
1/*
2 * SuperH Pin Function Controller support.
3 *
4 * Copyright (C) 2008 Magnus Damm
5 * Copyright (C) 2009 - 2012 Paul Mundt
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11#define pr_fmt(fmt) "sh_pfc " KBUILD_MODNAME ": " fmt
12
13#include <linux/errno.h>
14#include <linux/kernel.h>
15#include <linux/sh_pfc.h>
16#include <linux/module.h>
17#include <linux/err.h>
18#include <linux/io.h>
19#include <linux/bitops.h>
20#include <linux/slab.h>
21#include <linux/ioport.h>
22#include <linux/pinctrl/machine.h>
23
24static struct sh_pfc *sh_pfc __read_mostly;
25
26static inline bool sh_pfc_initialized(void)
27{
28 return !!sh_pfc;
29}
30
31static void pfc_iounmap(struct sh_pfc *pfc)
32{
33 int k;
34
35 for (k = 0; k < pfc->num_resources; k++)
36 if (pfc->window[k].virt)
37 iounmap(pfc->window[k].virt);
38
39 kfree(pfc->window);
40 pfc->window = NULL;
41}
42
43static int pfc_ioremap(struct sh_pfc *pfc)
44{
45 struct resource *res;
46 int k;
47
48 if (!pfc->num_resources)
49 return 0;
50
51 pfc->window = kzalloc(pfc->num_resources * sizeof(*pfc->window),
52 GFP_NOWAIT);
53 if (!pfc->window)
54 goto err1;
55
56 for (k = 0; k < pfc->num_resources; k++) {
57 res = pfc->resource + k;
58 WARN_ON(resource_type(res) != IORESOURCE_MEM);
59 pfc->window[k].phys = res->start;
60 pfc->window[k].size = resource_size(res);
61 pfc->window[k].virt = ioremap_nocache(res->start,
62 resource_size(res));
63 if (!pfc->window[k].virt)
64 goto err2;
65 }
66
67 return 0;
68
69err2:
70 pfc_iounmap(pfc);
71err1:
72 return -1;
73}
74
75static void __iomem *pfc_phys_to_virt(struct sh_pfc *pfc,
76 unsigned long address)
77{
78 struct pfc_window *window;
79 int k;
80
81 /* scan through physical windows and convert address */
82 for (k = 0; k < pfc->num_resources; k++) {
83 window = pfc->window + k;
84
85 if (address < window->phys)
86 continue;
87
88 if (address >= (window->phys + window->size))
89 continue;
90
91 return window->virt + (address - window->phys);
92 }
93
94 /* no windows defined, register must be 1:1 mapped virt:phys */
95 return (void __iomem *)address;
96}
97
98static int enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r)
99{
100 if (enum_id < r->begin)
101 return 0;
102
103 if (enum_id > r->end)
104 return 0;
105
106 return 1;
107}
108
109static unsigned long gpio_read_raw_reg(void __iomem *mapped_reg,
110 unsigned long reg_width)
111{
112 switch (reg_width) {
113 case 8:
114 return ioread8(mapped_reg);
115 case 16:
116 return ioread16(mapped_reg);
117 case 32:
118 return ioread32(mapped_reg);
119 }
120
121 BUG();
122 return 0;
123}
124
125static void gpio_write_raw_reg(void __iomem *mapped_reg,
126 unsigned long reg_width,
127 unsigned long data)
128{
129 switch (reg_width) {
130 case 8:
131 iowrite8(data, mapped_reg);
132 return;
133 case 16:
134 iowrite16(data, mapped_reg);
135 return;
136 case 32:
137 iowrite32(data, mapped_reg);
138 return;
139 }
140
141 BUG();
142}
143
144int sh_pfc_read_bit(struct pinmux_data_reg *dr, unsigned long in_pos)
145{
146 unsigned long pos;
147
148 pos = dr->reg_width - (in_pos + 1);
149
150 pr_debug("read_bit: addr = %lx, pos = %ld, "
151 "r_width = %ld\n", dr->reg, pos, dr->reg_width);
152
153 return (gpio_read_raw_reg(dr->mapped_reg, dr->reg_width) >> pos) & 1;
154}
155EXPORT_SYMBOL_GPL(sh_pfc_read_bit);
156
157void sh_pfc_write_bit(struct pinmux_data_reg *dr, unsigned long in_pos,
158 unsigned long value)
159{
160 unsigned long pos;
161
162 pos = dr->reg_width - (in_pos + 1);
163
164 pr_debug("write_bit addr = %lx, value = %d, pos = %ld, "
165 "r_width = %ld\n",
166 dr->reg, !!value, pos, dr->reg_width);
167
168 if (value)
169 set_bit(pos, &dr->reg_shadow);
170 else
171 clear_bit(pos, &dr->reg_shadow);
172
173 gpio_write_raw_reg(dr->mapped_reg, dr->reg_width, dr->reg_shadow);
174}
175EXPORT_SYMBOL_GPL(sh_pfc_write_bit);
176
177static void config_reg_helper(struct sh_pfc *pfc,
178 struct pinmux_cfg_reg *crp,
179 unsigned long in_pos,
180 void __iomem **mapped_regp,
181 unsigned long *maskp,
182 unsigned long *posp)
183{
184 int k;
185
186 *mapped_regp = pfc_phys_to_virt(pfc, crp->reg);
187
188 if (crp->field_width) {
189 *maskp = (1 << crp->field_width) - 1;
190 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
191 } else {
192 *maskp = (1 << crp->var_field_width[in_pos]) - 1;
193 *posp = crp->reg_width;
194 for (k = 0; k <= in_pos; k++)
195 *posp -= crp->var_field_width[k];
196 }
197}
198
199static int read_config_reg(struct sh_pfc *pfc,
200 struct pinmux_cfg_reg *crp,
201 unsigned long field)
202{
203 void __iomem *mapped_reg;
204 unsigned long mask, pos;
205
206 config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
207
208 pr_debug("read_reg: addr = %lx, field = %ld, "
209 "r_width = %ld, f_width = %ld\n",
210 crp->reg, field, crp->reg_width, crp->field_width);
211
212 return (gpio_read_raw_reg(mapped_reg, crp->reg_width) >> pos) & mask;
213}
214
215static void write_config_reg(struct sh_pfc *pfc,
216 struct pinmux_cfg_reg *crp,
217 unsigned long field, unsigned long value)
218{
219 void __iomem *mapped_reg;
220 unsigned long mask, pos, data;
221
222 config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
223
224 pr_debug("write_reg addr = %lx, value = %ld, field = %ld, "
225 "r_width = %ld, f_width = %ld\n",
226 crp->reg, value, field, crp->reg_width, crp->field_width);
227
228 mask = ~(mask << pos);
229 value = value << pos;
230
231 data = gpio_read_raw_reg(mapped_reg, crp->reg_width);
232 data &= mask;
233 data |= value;
234
235 if (pfc->unlock_reg)
236 gpio_write_raw_reg(pfc_phys_to_virt(pfc, pfc->unlock_reg),
237 32, ~data);
238
239 gpio_write_raw_reg(mapped_reg, crp->reg_width, data);
240}
241
242static int setup_data_reg(struct sh_pfc *pfc, unsigned gpio)
243{
244 struct pinmux_gpio *gpiop = &pfc->gpios[gpio];
245 struct pinmux_data_reg *data_reg;
246 int k, n;
247
248 if (!enum_in_range(gpiop->enum_id, &pfc->data))
249 return -1;
250
251 k = 0;
252 while (1) {
253 data_reg = pfc->data_regs + k;
254
255 if (!data_reg->reg_width)
256 break;
257
258 data_reg->mapped_reg = pfc_phys_to_virt(pfc, data_reg->reg);
259
260 for (n = 0; n < data_reg->reg_width; n++) {
261 if (data_reg->enum_ids[n] == gpiop->enum_id) {
262 gpiop->flags &= ~PINMUX_FLAG_DREG;
263 gpiop->flags |= (k << PINMUX_FLAG_DREG_SHIFT);
264 gpiop->flags &= ~PINMUX_FLAG_DBIT;
265 gpiop->flags |= (n << PINMUX_FLAG_DBIT_SHIFT);
266 return 0;
267 }
268 }
269 k++;
270 }
271
272 BUG();
273
274 return -1;
275}
276
277static void setup_data_regs(struct sh_pfc *pfc)
278{
279 struct pinmux_data_reg *drp;
280 int k;
281
282 for (k = pfc->first_gpio; k <= pfc->last_gpio; k++)
283 setup_data_reg(pfc, k);
284
285 k = 0;
286 while (1) {
287 drp = pfc->data_regs + k;
288
289 if (!drp->reg_width)
290 break;
291
292 drp->reg_shadow = gpio_read_raw_reg(drp->mapped_reg,
293 drp->reg_width);
294 k++;
295 }
296}
297
298int sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio,
299 struct pinmux_data_reg **drp, int *bitp)
300{
301 struct pinmux_gpio *gpiop = &pfc->gpios[gpio];
302 int k, n;
303
304 if (!enum_in_range(gpiop->enum_id, &pfc->data))
305 return -1;
306
307 k = (gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT;
308 n = (gpiop->flags & PINMUX_FLAG_DBIT) >> PINMUX_FLAG_DBIT_SHIFT;
309 *drp = pfc->data_regs + k;
310 *bitp = n;
311 return 0;
312}
313EXPORT_SYMBOL_GPL(sh_pfc_get_data_reg);
314
315static int get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id,
316 struct pinmux_cfg_reg **crp,
317 int *fieldp, int *valuep,
318 unsigned long **cntp)
319{
320 struct pinmux_cfg_reg *config_reg;
321 unsigned long r_width, f_width, curr_width, ncomb;
322 int k, m, n, pos, bit_pos;
323
324 k = 0;
325 while (1) {
326 config_reg = pfc->cfg_regs + k;
327
328 r_width = config_reg->reg_width;
329 f_width = config_reg->field_width;
330
331 if (!r_width)
332 break;
333
334 pos = 0;
335 m = 0;
336 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
337 if (f_width)
338 curr_width = f_width;
339 else
340 curr_width = config_reg->var_field_width[m];
341
342 ncomb = 1 << curr_width;
343 for (n = 0; n < ncomb; n++) {
344 if (config_reg->enum_ids[pos + n] == enum_id) {
345 *crp = config_reg;
346 *fieldp = m;
347 *valuep = n;
348 *cntp = &config_reg->cnt[m];
349 return 0;
350 }
351 }
352 pos += ncomb;
353 m++;
354 }
355 k++;
356 }
357
358 return -1;
359}
360
361int sh_pfc_gpio_to_enum(struct sh_pfc *pfc, unsigned gpio, int pos,
362 pinmux_enum_t *enum_idp)
363{
364 pinmux_enum_t enum_id = pfc->gpios[gpio].enum_id;
365 pinmux_enum_t *data = pfc->gpio_data;
366 int k;
367
368 if (!enum_in_range(enum_id, &pfc->data)) {
369 if (!enum_in_range(enum_id, &pfc->mark)) {
370 pr_err("non data/mark enum_id for gpio %d\n", gpio);
371 return -1;
372 }
373 }
374
375 if (pos) {
376 *enum_idp = data[pos + 1];
377 return pos + 1;
378 }
379
380 for (k = 0; k < pfc->gpio_data_size; k++) {
381 if (data[k] == enum_id) {
382 *enum_idp = data[k + 1];
383 return k + 1;
384 }
385 }
386
387 pr_err("cannot locate data/mark enum_id for gpio %d\n", gpio);
388 return -1;
389}
390EXPORT_SYMBOL_GPL(sh_pfc_gpio_to_enum);
391
392int sh_pfc_config_gpio(struct sh_pfc *pfc, unsigned gpio, int pinmux_type,
393 int cfg_mode)
394{
395 struct pinmux_cfg_reg *cr = NULL;
396 pinmux_enum_t enum_id;
397 struct pinmux_range *range;
398 int in_range, pos, field, value;
399 unsigned long *cntp;
400
401 switch (pinmux_type) {
402
403 case PINMUX_TYPE_FUNCTION:
404 range = NULL;
405 break;
406
407 case PINMUX_TYPE_OUTPUT:
408 range = &pfc->output;
409 break;
410
411 case PINMUX_TYPE_INPUT:
412 range = &pfc->input;
413 break;
414
415 case PINMUX_TYPE_INPUT_PULLUP:
416 range = &pfc->input_pu;
417 break;
418
419 case PINMUX_TYPE_INPUT_PULLDOWN:
420 range = &pfc->input_pd;
421 break;
422
423 default:
424 goto out_err;
425 }
426
427 pos = 0;
428 enum_id = 0;
429 field = 0;
430 value = 0;
431 while (1) {
432 pos = sh_pfc_gpio_to_enum(pfc, gpio, pos, &enum_id);
433 if (pos <= 0)
434 goto out_err;
435
436 if (!enum_id)
437 break;
438
439 /* first check if this is a function enum */
440 in_range = enum_in_range(enum_id, &pfc->function);
441 if (!in_range) {
442 /* not a function enum */
443 if (range) {
444 /*
445 * other range exists, so this pin is
446 * a regular GPIO pin that now is being
447 * bound to a specific direction.
448 *
449 * for this case we only allow function enums
450 * and the enums that match the other range.
451 */
452 in_range = enum_in_range(enum_id, range);
453
454 /*
455 * special case pass through for fixed
456 * input-only or output-only pins without
457 * function enum register association.
458 */
459 if (in_range && enum_id == range->force)
460 continue;
461 } else {
462 /*
463 * no other range exists, so this pin
464 * must then be of the function type.
465 *
466 * allow function type pins to select
467 * any combination of function/in/out
468 * in their MARK lists.
469 */
470 in_range = 1;
471 }
472 }
473
474 if (!in_range)
475 continue;
476
477 if (get_config_reg(pfc, enum_id, &cr,
478 &field, &value, &cntp) != 0)
479 goto out_err;
480
481 switch (cfg_mode) {
482 case GPIO_CFG_DRYRUN:
483 if (!*cntp ||
484 (read_config_reg(pfc, cr, field) != value))
485 continue;
486 break;
487
488 case GPIO_CFG_REQ:
489 write_config_reg(pfc, cr, field, value);
490 *cntp = *cntp + 1;
491 break;
492
493 case GPIO_CFG_FREE:
494 *cntp = *cntp - 1;
495 break;
496 }
497 }
498
499 return 0;
500 out_err:
501 return -1;
502}
503EXPORT_SYMBOL_GPL(sh_pfc_config_gpio);
504
505int register_sh_pfc(struct sh_pfc *pfc)
506{
507 int (*initroutine)(struct sh_pfc *) = NULL;
508 int ret;
509
510 /*
511 * Ensure that the type encoding fits
512 */
513 BUILD_BUG_ON(PINMUX_FLAG_TYPE > ((1 << PINMUX_FLAG_DBIT_SHIFT) - 1));
514
515 if (sh_pfc)
516 return -EBUSY;
517
518 ret = pfc_ioremap(pfc);
519 if (unlikely(ret < 0))
520 return ret;
521
522 spin_lock_init(&pfc->lock);
523
524 pinctrl_provide_dummies();
525 setup_data_regs(pfc);
526
527 sh_pfc = pfc;
528
529 /*
530 * Initialize pinctrl bindings first
531 */
532 initroutine = symbol_request(sh_pfc_register_pinctrl);
533 if (initroutine) {
534 ret = (*initroutine)(pfc);
535 symbol_put_addr(initroutine);
536
537 if (unlikely(ret != 0))
538 goto err;
539 } else {
540 pr_err("failed to initialize pinctrl bindings\n");
541 goto err;
542 }
543
544 /*
545 * Then the GPIO chip
546 */
547 initroutine = symbol_request(sh_pfc_register_gpiochip);
548 if (initroutine) {
549 ret = (*initroutine)(pfc);
550 symbol_put_addr(initroutine);
551
552 /*
553 * If the GPIO chip fails to come up we still leave the
554 * PFC state as it is, given that there are already
555 * extant users of it that have succeeded by this point.
556 */
557 if (unlikely(ret != 0)) {
558 pr_notice("failed to init GPIO chip, ignoring...\n");
559 ret = 0;
560 }
561 }
562
563 pr_info("%s support registered\n", pfc->name);
564
565 return 0;
566
567err:
568 pfc_iounmap(pfc);
569 sh_pfc = NULL;
570
571 return ret;
572}
diff --git a/drivers/sh/pfc/gpio.c b/drivers/sh/pfc/gpio.c
new file mode 100644
index 00000000000..62bca98474a
--- /dev/null
+++ b/drivers/sh/pfc/gpio.c
@@ -0,0 +1,239 @@
1/*
2 * SuperH Pin Function Controller GPIO driver.
3 *
4 * Copyright (C) 2008 Magnus Damm
5 * Copyright (C) 2009 - 2012 Paul Mundt
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11#define pr_fmt(fmt) "sh_pfc " KBUILD_MODNAME ": " fmt
12
13#include <linux/init.h>
14#include <linux/gpio.h>
15#include <linux/slab.h>
16#include <linux/spinlock.h>
17#include <linux/module.h>
18#include <linux/platform_device.h>
19#include <linux/pinctrl/consumer.h>
20
21struct sh_pfc_chip {
22 struct sh_pfc *pfc;
23 struct gpio_chip gpio_chip;
24};
25
26static struct sh_pfc_chip *gpio_to_pfc_chip(struct gpio_chip *gc)
27{
28 return container_of(gc, struct sh_pfc_chip, gpio_chip);
29}
30
31static struct sh_pfc *gpio_to_pfc(struct gpio_chip *gc)
32{
33 return gpio_to_pfc_chip(gc)->pfc;
34}
35
36static int sh_gpio_request(struct gpio_chip *gc, unsigned offset)
37{
38 return pinctrl_request_gpio(offset);
39}
40
41static void sh_gpio_free(struct gpio_chip *gc, unsigned offset)
42{
43 pinctrl_free_gpio(offset);
44}
45
46static void sh_gpio_set_value(struct sh_pfc *pfc, unsigned gpio, int value)
47{
48 struct pinmux_data_reg *dr = NULL;
49 int bit = 0;
50
51 if (!pfc || sh_pfc_get_data_reg(pfc, gpio, &dr, &bit) != 0)
52 BUG();
53 else
54 sh_pfc_write_bit(dr, bit, value);
55}
56
57static int sh_gpio_get_value(struct sh_pfc *pfc, unsigned gpio)
58{
59 struct pinmux_data_reg *dr = NULL;
60 int bit = 0;
61
62 if (!pfc || sh_pfc_get_data_reg(pfc, gpio, &dr, &bit) != 0)
63 return -EINVAL;
64
65 return sh_pfc_read_bit(dr, bit);
66}
67
68static int sh_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
69{
70 return pinctrl_gpio_direction_input(offset);
71}
72
73static int sh_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
74 int value)
75{
76 sh_gpio_set_value(gpio_to_pfc(gc), offset, value);
77
78 return pinctrl_gpio_direction_output(offset);
79}
80
81static int sh_gpio_get(struct gpio_chip *gc, unsigned offset)
82{
83 return sh_gpio_get_value(gpio_to_pfc(gc), offset);
84}
85
86static void sh_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
87{
88 sh_gpio_set_value(gpio_to_pfc(gc), offset, value);
89}
90
91static int sh_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
92{
93 struct sh_pfc *pfc = gpio_to_pfc(gc);
94 pinmux_enum_t enum_id;
95 pinmux_enum_t *enum_ids;
96 int i, k, pos;
97
98 pos = 0;
99 enum_id = 0;
100 while (1) {
101 pos = sh_pfc_gpio_to_enum(pfc, offset, pos, &enum_id);
102 if (pos <= 0 || !enum_id)
103 break;
104
105 for (i = 0; i < pfc->gpio_irq_size; i++) {
106 enum_ids = pfc->gpio_irq[i].enum_ids;
107 for (k = 0; enum_ids[k]; k++) {
108 if (enum_ids[k] == enum_id)
109 return pfc->gpio_irq[i].irq;
110 }
111 }
112 }
113
114 return -ENOSYS;
115}
116
117static void sh_pfc_gpio_setup(struct sh_pfc_chip *chip)
118{
119 struct sh_pfc *pfc = chip->pfc;
120 struct gpio_chip *gc = &chip->gpio_chip;
121
122 gc->request = sh_gpio_request;
123 gc->free = sh_gpio_free;
124 gc->direction_input = sh_gpio_direction_input;
125 gc->get = sh_gpio_get;
126 gc->direction_output = sh_gpio_direction_output;
127 gc->set = sh_gpio_set;
128 gc->to_irq = sh_gpio_to_irq;
129
130 WARN_ON(pfc->first_gpio != 0); /* needs testing */
131
132 gc->label = pfc->name;
133 gc->owner = THIS_MODULE;
134 gc->base = pfc->first_gpio;
135 gc->ngpio = (pfc->last_gpio - pfc->first_gpio) + 1;
136}
137
138int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
139{
140 struct sh_pfc_chip *chip;
141 int ret;
142
143 chip = kzalloc(sizeof(struct sh_pfc_chip), GFP_KERNEL);
144 if (unlikely(!chip))
145 return -ENOMEM;
146
147 chip->pfc = pfc;
148
149 sh_pfc_gpio_setup(chip);
150
151 ret = gpiochip_add(&chip->gpio_chip);
152 if (unlikely(ret < 0))
153 kfree(chip);
154
155 pr_info("%s handling gpio %d -> %d\n",
156 pfc->name, pfc->first_gpio, pfc->last_gpio);
157
158 return ret;
159}
160EXPORT_SYMBOL_GPL(sh_pfc_register_gpiochip);
161
162static int sh_pfc_gpio_match(struct gpio_chip *gc, void *data)
163{
164 return !!strstr(gc->label, data);
165}
166
167static int __devinit sh_pfc_gpio_probe(struct platform_device *pdev)
168{
169 struct sh_pfc_chip *chip;
170 struct gpio_chip *gc;
171
172 gc = gpiochip_find("_pfc", sh_pfc_gpio_match);
173 if (unlikely(!gc)) {
174 pr_err("Cant find gpio chip\n");
175 return -ENODEV;
176 }
177
178 chip = gpio_to_pfc_chip(gc);
179 platform_set_drvdata(pdev, chip);
180
181 pr_info("attaching to GPIO chip %s\n", chip->pfc->name);
182
183 return 0;
184}
185
186static int __devexit sh_pfc_gpio_remove(struct platform_device *pdev)
187{
188 struct sh_pfc_chip *chip = platform_get_drvdata(pdev);
189 int ret;
190
191 ret = gpiochip_remove(&chip->gpio_chip);
192 if (unlikely(ret < 0))
193 return ret;
194
195 kfree(chip);
196 return 0;
197}
198
199static struct platform_driver sh_pfc_gpio_driver = {
200 .probe = sh_pfc_gpio_probe,
201 .remove = __devexit_p(sh_pfc_gpio_remove),
202 .driver = {
203 .name = KBUILD_MODNAME,
204 .owner = THIS_MODULE,
205 },
206};
207
208static struct platform_device sh_pfc_gpio_device = {
209 .name = KBUILD_MODNAME,
210 .id = -1,
211};
212
213static int __init sh_pfc_gpio_init(void)
214{
215 int rc;
216
217 rc = platform_driver_register(&sh_pfc_gpio_driver);
218 if (likely(!rc)) {
219 rc = platform_device_register(&sh_pfc_gpio_device);
220 if (unlikely(rc))
221 platform_driver_unregister(&sh_pfc_gpio_driver);
222 }
223
224 return rc;
225}
226
227static void __exit sh_pfc_gpio_exit(void)
228{
229 platform_device_unregister(&sh_pfc_gpio_device);
230 platform_driver_unregister(&sh_pfc_gpio_driver);
231}
232
233module_init(sh_pfc_gpio_init);
234module_exit(sh_pfc_gpio_exit);
235
236MODULE_AUTHOR("Magnus Damm, Paul Mundt");
237MODULE_DESCRIPTION("GPIO driver for SuperH pin function controller");
238MODULE_LICENSE("GPL v2");
239MODULE_ALIAS("platform:pfc-gpio");
diff --git a/drivers/sh/pfc/pinctrl.c b/drivers/sh/pfc/pinctrl.c
new file mode 100644
index 00000000000..0802b6c0d65
--- /dev/null
+++ b/drivers/sh/pfc/pinctrl.c
@@ -0,0 +1,530 @@
1/*
2 * SuperH Pin Function Controller pinmux support.
3 *
4 * Copyright (C) 2012 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#define DRV_NAME "pinctrl-sh_pfc"
11
12#define pr_fmt(fmt) DRV_NAME " " KBUILD_MODNAME ": " fmt
13
14#include <linux/init.h>
15#include <linux/module.h>
16#include <linux/sh_pfc.h>
17#include <linux/err.h>
18#include <linux/slab.h>
19#include <linux/spinlock.h>
20#include <linux/platform_device.h>
21#include <linux/pinctrl/consumer.h>
22#include <linux/pinctrl/pinctrl.h>
23#include <linux/pinctrl/pinconf.h>
24#include <linux/pinctrl/pinmux.h>
25#include <linux/pinctrl/pinconf-generic.h>
26
27struct sh_pfc_pinctrl {
28 struct pinctrl_dev *pctl;
29 struct sh_pfc *pfc;
30
31 struct pinmux_gpio **functions;
32 unsigned int nr_functions;
33
34 struct pinctrl_pin_desc *pads;
35 unsigned int nr_pads;
36
37 spinlock_t lock;
38};
39
40static struct sh_pfc_pinctrl *sh_pfc_pmx;
41
42static int sh_pfc_get_groups_count(struct pinctrl_dev *pctldev)
43{
44 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
45
46 return pmx->nr_pads;
47}
48
49static const char *sh_pfc_get_group_name(struct pinctrl_dev *pctldev,
50 unsigned selector)
51{
52 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
53
54 return pmx->pads[selector].name;
55}
56
57static int sh_pfc_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
58 const unsigned **pins, unsigned *num_pins)
59{
60 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
61
62 *pins = &pmx->pads[group].number;
63 *num_pins = 1;
64
65 return 0;
66}
67
68static void sh_pfc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
69 unsigned offset)
70{
71 seq_printf(s, "%s", DRV_NAME);
72}
73
74static struct pinctrl_ops sh_pfc_pinctrl_ops = {
75 .get_groups_count = sh_pfc_get_groups_count,
76 .get_group_name = sh_pfc_get_group_name,
77 .get_group_pins = sh_pfc_get_group_pins,
78 .pin_dbg_show = sh_pfc_pin_dbg_show,
79};
80
81static int sh_pfc_get_functions_count(struct pinctrl_dev *pctldev)
82{
83 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
84
85 return pmx->nr_functions;
86}
87
88static const char *sh_pfc_get_function_name(struct pinctrl_dev *pctldev,
89 unsigned selector)
90{
91 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
92
93 return pmx->functions[selector]->name;
94}
95
96static int sh_pfc_get_function_groups(struct pinctrl_dev *pctldev, unsigned func,
97 const char * const **groups,
98 unsigned * const num_groups)
99{
100 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
101
102 *groups = &pmx->functions[func]->name;
103 *num_groups = 1;
104
105 return 0;
106}
107
108static int sh_pfc_noop_enable(struct pinctrl_dev *pctldev, unsigned func,
109 unsigned group)
110{
111 return 0;
112}
113
114static void sh_pfc_noop_disable(struct pinctrl_dev *pctldev, unsigned func,
115 unsigned group)
116{
117}
118
119static inline int sh_pfc_config_function(struct sh_pfc *pfc, unsigned offset)
120{
121 if (sh_pfc_config_gpio(pfc, offset,
122 PINMUX_TYPE_FUNCTION,
123 GPIO_CFG_DRYRUN) != 0)
124 return -EINVAL;
125
126 if (sh_pfc_config_gpio(pfc, offset,
127 PINMUX_TYPE_FUNCTION,
128 GPIO_CFG_REQ) != 0)
129 return -EINVAL;
130
131 return 0;
132}
133
134static int sh_pfc_reconfig_pin(struct sh_pfc *pfc, unsigned offset,
135 int new_type)
136{
137 unsigned long flags;
138 int pinmux_type;
139 int ret = -EINVAL;
140
141 spin_lock_irqsave(&pfc->lock, flags);
142
143 pinmux_type = pfc->gpios[offset].flags & PINMUX_FLAG_TYPE;
144
145 /*
146 * See if the present config needs to first be de-configured.
147 */
148 switch (pinmux_type) {
149 case PINMUX_TYPE_GPIO:
150 break;
151 case PINMUX_TYPE_OUTPUT:
152 case PINMUX_TYPE_INPUT:
153 case PINMUX_TYPE_INPUT_PULLUP:
154 case PINMUX_TYPE_INPUT_PULLDOWN:
155 sh_pfc_config_gpio(pfc, offset, pinmux_type, GPIO_CFG_FREE);
156 break;
157 default:
158 goto err;
159 }
160
161 /*
162 * Dry run
163 */
164 if (sh_pfc_config_gpio(pfc, offset, new_type,
165 GPIO_CFG_DRYRUN) != 0)
166 goto err;
167
168 /*
169 * Request
170 */
171 if (sh_pfc_config_gpio(pfc, offset, new_type,
172 GPIO_CFG_REQ) != 0)
173 goto err;
174
175 pfc->gpios[offset].flags &= ~PINMUX_FLAG_TYPE;
176 pfc->gpios[offset].flags |= new_type;
177
178 ret = 0;
179
180err:
181 spin_unlock_irqrestore(&pfc->lock, flags);
182
183 return ret;
184}
185
186
187static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev,
188 struct pinctrl_gpio_range *range,
189 unsigned offset)
190{
191 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
192 struct sh_pfc *pfc = pmx->pfc;
193 unsigned long flags;
194 int ret, pinmux_type;
195
196 spin_lock_irqsave(&pfc->lock, flags);
197
198 pinmux_type = pfc->gpios[offset].flags & PINMUX_FLAG_TYPE;
199
200 switch (pinmux_type) {
201 case PINMUX_TYPE_FUNCTION:
202 pr_notice_once("Use of GPIO API for function requests is "
203 "deprecated, convert to pinctrl\n");
204 /* handle for now */
205 ret = sh_pfc_config_function(pfc, offset);
206 if (unlikely(ret < 0))
207 goto err;
208
209 break;
210 case PINMUX_TYPE_GPIO:
211 break;
212 default:
213 pr_err("Unsupported mux type (%d), bailing...\n", pinmux_type);
214 return -ENOTSUPP;
215 }
216
217 ret = 0;
218
219err:
220 spin_unlock_irqrestore(&pfc->lock, flags);
221
222 return ret;
223}
224
225static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev,
226 struct pinctrl_gpio_range *range,
227 unsigned offset)
228{
229 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
230 struct sh_pfc *pfc = pmx->pfc;
231 unsigned long flags;
232 int pinmux_type;
233
234 spin_lock_irqsave(&pfc->lock, flags);
235
236 pinmux_type = pfc->gpios[offset].flags & PINMUX_FLAG_TYPE;
237
238 sh_pfc_config_gpio(pfc, offset, pinmux_type, GPIO_CFG_FREE);
239
240 spin_unlock_irqrestore(&pfc->lock, flags);
241}
242
243static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev,
244 struct pinctrl_gpio_range *range,
245 unsigned offset, bool input)
246{
247 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
248 int type = input ? PINMUX_TYPE_INPUT : PINMUX_TYPE_OUTPUT;
249
250 return sh_pfc_reconfig_pin(pmx->pfc, offset, type);
251}
252
253static struct pinmux_ops sh_pfc_pinmux_ops = {
254 .get_functions_count = sh_pfc_get_functions_count,
255 .get_function_name = sh_pfc_get_function_name,
256 .get_function_groups = sh_pfc_get_function_groups,
257 .enable = sh_pfc_noop_enable,
258 .disable = sh_pfc_noop_disable,
259 .gpio_request_enable = sh_pfc_gpio_request_enable,
260 .gpio_disable_free = sh_pfc_gpio_disable_free,
261 .gpio_set_direction = sh_pfc_gpio_set_direction,
262};
263
264static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
265 unsigned long *config)
266{
267 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
268 struct sh_pfc *pfc = pmx->pfc;
269
270 *config = pfc->gpios[pin].flags & PINMUX_FLAG_TYPE;
271
272 return 0;
273}
274
275static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
276 unsigned long config)
277{
278 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
279 struct sh_pfc *pfc = pmx->pfc;
280
281 /* Validate the new type */
282 if (config >= PINMUX_FLAG_TYPE)
283 return -EINVAL;
284
285 return sh_pfc_reconfig_pin(pmx->pfc, pin, config);
286}
287
288static void sh_pfc_pinconf_dbg_show(struct pinctrl_dev *pctldev,
289 struct seq_file *s, unsigned pin)
290{
291 const char *pinmux_type_str[] = {
292 [PINMUX_TYPE_NONE] = "none",
293 [PINMUX_TYPE_FUNCTION] = "function",
294 [PINMUX_TYPE_GPIO] = "gpio",
295 [PINMUX_TYPE_OUTPUT] = "output",
296 [PINMUX_TYPE_INPUT] = "input",
297 [PINMUX_TYPE_INPUT_PULLUP] = "input bias pull up",
298 [PINMUX_TYPE_INPUT_PULLDOWN] = "input bias pull down",
299 };
300 unsigned long config;
301 int rc;
302
303 rc = sh_pfc_pinconf_get(pctldev, pin, &config);
304 if (unlikely(rc != 0))
305 return;
306
307 seq_printf(s, " %s", pinmux_type_str[config]);
308}
309
310static struct pinconf_ops sh_pfc_pinconf_ops = {
311 .pin_config_get = sh_pfc_pinconf_get,
312 .pin_config_set = sh_pfc_pinconf_set,
313 .pin_config_dbg_show = sh_pfc_pinconf_dbg_show,
314};
315
316static struct pinctrl_gpio_range sh_pfc_gpio_range = {
317 .name = DRV_NAME,
318 .id = 0,
319};
320
321static struct pinctrl_desc sh_pfc_pinctrl_desc = {
322 .name = DRV_NAME,
323 .owner = THIS_MODULE,
324 .pctlops = &sh_pfc_pinctrl_ops,
325 .pmxops = &sh_pfc_pinmux_ops,
326 .confops = &sh_pfc_pinconf_ops,
327};
328
329int sh_pfc_register_pinctrl(struct sh_pfc *pfc)
330{
331 sh_pfc_pmx = kzalloc(sizeof(struct sh_pfc_pinctrl), GFP_KERNEL);
332 if (unlikely(!sh_pfc_pmx))
333 return -ENOMEM;
334
335 spin_lock_init(&sh_pfc_pmx->lock);
336
337 sh_pfc_pmx->pfc = pfc;
338
339 return 0;
340}
341EXPORT_SYMBOL_GPL(sh_pfc_register_pinctrl);
342
343static inline void __devinit sh_pfc_map_one_gpio(struct sh_pfc *pfc,
344 struct sh_pfc_pinctrl *pmx,
345 struct pinmux_gpio *gpio,
346 unsigned offset)
347{
348 struct pinmux_data_reg *dummy;
349 unsigned long flags;
350 int bit;
351
352 gpio->flags &= ~PINMUX_FLAG_TYPE;
353
354 if (sh_pfc_get_data_reg(pfc, offset, &dummy, &bit) == 0)
355 gpio->flags |= PINMUX_TYPE_GPIO;
356 else {
357 gpio->flags |= PINMUX_TYPE_FUNCTION;
358
359 spin_lock_irqsave(&pmx->lock, flags);
360 pmx->nr_functions++;
361 spin_unlock_irqrestore(&pmx->lock, flags);
362 }
363}
364
365/* pinmux ranges -> pinctrl pin descs */
366static int __devinit sh_pfc_map_gpios(struct sh_pfc *pfc,
367 struct sh_pfc_pinctrl *pmx)
368{
369 unsigned long flags;
370 int i;
371
372 pmx->nr_pads = pfc->last_gpio - pfc->first_gpio + 1;
373
374 pmx->pads = kmalloc(sizeof(struct pinctrl_pin_desc) * pmx->nr_pads,
375 GFP_KERNEL);
376 if (unlikely(!pmx->pads)) {
377 pmx->nr_pads = 0;
378 return -ENOMEM;
379 }
380
381 spin_lock_irqsave(&pfc->lock, flags);
382
383 /*
384 * We don't necessarily have a 1:1 mapping between pin and linux
385 * GPIO number, as the latter maps to the associated enum_id.
386 * Care needs to be taken to translate back to pin space when
387 * dealing with any pin configurations.
388 */
389 for (i = 0; i < pmx->nr_pads; i++) {
390 struct pinctrl_pin_desc *pin = pmx->pads + i;
391 struct pinmux_gpio *gpio = pfc->gpios + i;
392
393 pin->number = pfc->first_gpio + i;
394 pin->name = gpio->name;
395
396 /* XXX */
397 if (unlikely(!gpio->enum_id))
398 continue;
399
400 sh_pfc_map_one_gpio(pfc, pmx, gpio, i);
401 }
402
403 spin_unlock_irqrestore(&pfc->lock, flags);
404
405 sh_pfc_pinctrl_desc.pins = pmx->pads;
406 sh_pfc_pinctrl_desc.npins = pmx->nr_pads;
407
408 return 0;
409}
410
411static int __devinit sh_pfc_map_functions(struct sh_pfc *pfc,
412 struct sh_pfc_pinctrl *pmx)
413{
414 unsigned long flags;
415 int i, fn;
416
417 pmx->functions = kzalloc(pmx->nr_functions * sizeof(void *),
418 GFP_KERNEL);
419 if (unlikely(!pmx->functions))
420 return -ENOMEM;
421
422 spin_lock_irqsave(&pmx->lock, flags);
423
424 for (i = fn = 0; i < pmx->nr_pads; i++) {
425 struct pinmux_gpio *gpio = pfc->gpios + i;
426
427 if ((gpio->flags & PINMUX_FLAG_TYPE) == PINMUX_TYPE_FUNCTION)
428 pmx->functions[fn++] = gpio;
429 }
430
431 spin_unlock_irqrestore(&pmx->lock, flags);
432
433 return 0;
434}
435
436static int __devinit sh_pfc_pinctrl_probe(struct platform_device *pdev)
437{
438 struct sh_pfc *pfc;
439 int ret;
440
441 if (unlikely(!sh_pfc_pmx))
442 return -ENODEV;
443
444 pfc = sh_pfc_pmx->pfc;
445
446 ret = sh_pfc_map_gpios(pfc, sh_pfc_pmx);
447 if (unlikely(ret != 0))
448 return ret;
449
450 ret = sh_pfc_map_functions(pfc, sh_pfc_pmx);
451 if (unlikely(ret != 0))
452 goto free_pads;
453
454 sh_pfc_pmx->pctl = pinctrl_register(&sh_pfc_pinctrl_desc, &pdev->dev,
455 sh_pfc_pmx);
456 if (IS_ERR(sh_pfc_pmx->pctl)) {
457 ret = PTR_ERR(sh_pfc_pmx->pctl);
458 goto free_functions;
459 }
460
461 sh_pfc_gpio_range.npins = pfc->last_gpio - pfc->first_gpio + 1;
462 sh_pfc_gpio_range.base = pfc->first_gpio;
463 sh_pfc_gpio_range.pin_base = pfc->first_gpio;
464
465 pinctrl_add_gpio_range(sh_pfc_pmx->pctl, &sh_pfc_gpio_range);
466
467 platform_set_drvdata(pdev, sh_pfc_pmx);
468
469 return 0;
470
471free_functions:
472 kfree(sh_pfc_pmx->functions);
473free_pads:
474 kfree(sh_pfc_pmx->pads);
475 kfree(sh_pfc_pmx);
476
477 return ret;
478}
479
480static int __devexit sh_pfc_pinctrl_remove(struct platform_device *pdev)
481{
482 struct sh_pfc_pinctrl *pmx = platform_get_drvdata(pdev);
483
484 pinctrl_remove_gpio_range(pmx->pctl, &sh_pfc_gpio_range);
485 pinctrl_unregister(pmx->pctl);
486
487 platform_set_drvdata(pdev, NULL);
488
489 kfree(sh_pfc_pmx->functions);
490 kfree(sh_pfc_pmx->pads);
491 kfree(sh_pfc_pmx);
492
493 return 0;
494}
495
496static struct platform_driver sh_pfc_pinctrl_driver = {
497 .probe = sh_pfc_pinctrl_probe,
498 .remove = __devexit_p(sh_pfc_pinctrl_remove),
499 .driver = {
500 .name = DRV_NAME,
501 .owner = THIS_MODULE,
502 },
503};
504
505static struct platform_device sh_pfc_pinctrl_device = {
506 .name = DRV_NAME,
507 .id = -1,
508};
509
510static int __init sh_pfc_pinctrl_init(void)
511{
512 int rc;
513
514 rc = platform_driver_register(&sh_pfc_pinctrl_driver);
515 if (likely(!rc)) {
516 rc = platform_device_register(&sh_pfc_pinctrl_device);
517 if (unlikely(rc))
518 platform_driver_unregister(&sh_pfc_pinctrl_driver);
519 }
520
521 return rc;
522}
523
524static void __exit sh_pfc_pinctrl_exit(void)
525{
526 platform_driver_unregister(&sh_pfc_pinctrl_driver);
527}
528
529subsys_initcall(sh_pfc_pinctrl_init);
530module_exit(sh_pfc_pinctrl_exit);
diff --git a/include/linux/sh_clk.h b/include/linux/sh_clk.h
index c513b73cd7c..50910913b26 100644
--- a/include/linux/sh_clk.h
+++ b/include/linux/sh_clk.h
@@ -18,7 +18,6 @@ struct clk_mapping {
18 struct kref ref; 18 struct kref ref;
19}; 19};
20 20
21
22struct sh_clk_ops { 21struct sh_clk_ops {
23#ifdef CONFIG_SH_CLK_CPG_LEGACY 22#ifdef CONFIG_SH_CLK_CPG_LEGACY
24 void (*init)(struct clk *clk); 23 void (*init)(struct clk *clk);
@@ -31,6 +30,10 @@ struct sh_clk_ops {
31 long (*round_rate)(struct clk *clk, unsigned long rate); 30 long (*round_rate)(struct clk *clk, unsigned long rate);
32}; 31};
33 32
33#define SH_CLK_DIV_MSK(div) ((1 << (div)) - 1)
34#define SH_CLK_DIV4_MSK SH_CLK_DIV_MSK(4)
35#define SH_CLK_DIV6_MSK SH_CLK_DIV_MSK(6)
36
34struct clk { 37struct clk {
35 struct list_head node; 38 struct list_head node;
36 struct clk *parent; 39 struct clk *parent;
@@ -52,6 +55,7 @@ struct clk {
52 unsigned int enable_bit; 55 unsigned int enable_bit;
53 void __iomem *mapped_reg; 56 void __iomem *mapped_reg;
54 57
58 unsigned int div_mask;
55 unsigned long arch_flags; 59 unsigned long arch_flags;
56 void *priv; 60 void *priv;
57 struct clk_mapping *mapping; 61 struct clk_mapping *mapping;
@@ -65,6 +69,8 @@ struct clk {
65#define CLK_ENABLE_REG_16BIT BIT(2) 69#define CLK_ENABLE_REG_16BIT BIT(2)
66#define CLK_ENABLE_REG_8BIT BIT(3) 70#define CLK_ENABLE_REG_8BIT BIT(3)
67 71
72#define CLK_MASK_DIV_ON_DISABLE BIT(4)
73
68#define CLK_ENABLE_REG_MASK (CLK_ENABLE_REG_32BIT | \ 74#define CLK_ENABLE_REG_MASK (CLK_ENABLE_REG_32BIT | \
69 CLK_ENABLE_REG_16BIT | \ 75 CLK_ENABLE_REG_16BIT | \
70 CLK_ENABLE_REG_8BIT) 76 CLK_ENABLE_REG_8BIT)
@@ -146,14 +152,17 @@ static inline int __deprecated sh_clk_mstp32_register(struct clk *clks, int nr)
146 .enable_reg = (void __iomem *)_reg, \ 152 .enable_reg = (void __iomem *)_reg, \
147 .enable_bit = _shift, \ 153 .enable_bit = _shift, \
148 .arch_flags = _div_bitmap, \ 154 .arch_flags = _div_bitmap, \
155 .div_mask = SH_CLK_DIV4_MSK, \
149 .flags = _flags, \ 156 .flags = _flags, \
150} 157}
151 158
152struct clk_div4_table { 159struct clk_div_table {
153 struct clk_div_mult_table *div_mult_table; 160 struct clk_div_mult_table *div_mult_table;
154 void (*kick)(struct clk *clk); 161 void (*kick)(struct clk *clk);
155}; 162};
156 163
164#define clk_div4_table clk_div_table
165
157int sh_clk_div4_register(struct clk *clks, int nr, 166int sh_clk_div4_register(struct clk *clks, int nr,
158 struct clk_div4_table *table); 167 struct clk_div4_table *table);
159int sh_clk_div4_enable_register(struct clk *clks, int nr, 168int sh_clk_div4_enable_register(struct clk *clks, int nr,
@@ -165,7 +174,9 @@ int sh_clk_div4_reparent_register(struct clk *clks, int nr,
165 _num_parents, _src_shift, _src_width) \ 174 _num_parents, _src_shift, _src_width) \
166{ \ 175{ \
167 .enable_reg = (void __iomem *)_reg, \ 176 .enable_reg = (void __iomem *)_reg, \
168 .flags = _flags, \ 177 .enable_bit = 0, /* unused */ \
178 .flags = _flags | CLK_MASK_DIV_ON_DISABLE, \
179 .div_mask = SH_CLK_DIV6_MSK, \
169 .parent_table = _parents, \ 180 .parent_table = _parents, \
170 .parent_num = _num_parents, \ 181 .parent_num = _num_parents, \
171 .src_shift = _src_shift, \ 182 .src_shift = _src_shift, \
@@ -176,7 +187,9 @@ int sh_clk_div4_reparent_register(struct clk *clks, int nr,
176{ \ 187{ \
177 .parent = _parent, \ 188 .parent = _parent, \
178 .enable_reg = (void __iomem *)_reg, \ 189 .enable_reg = (void __iomem *)_reg, \
179 .flags = _flags, \ 190 .enable_bit = 0, /* unused */ \
191 .div_mask = SH_CLK_DIV6_MSK, \
192 .flags = _flags | CLK_MASK_DIV_ON_DISABLE, \
180} 193}
181 194
182int sh_clk_div6_register(struct clk *clks, int nr); 195int sh_clk_div6_register(struct clk *clks, int nr);
diff --git a/include/linux/sh_pfc.h b/include/linux/sh_pfc.h
index 5c15aed9c4b..c19a0925829 100644
--- a/include/linux/sh_pfc.h
+++ b/include/linux/sh_pfc.h
@@ -11,22 +11,24 @@
11#ifndef __SH_PFC_H 11#ifndef __SH_PFC_H
12#define __SH_PFC_H 12#define __SH_PFC_H
13 13
14#include <linux/stringify.h>
14#include <asm-generic/gpio.h> 15#include <asm-generic/gpio.h>
15 16
16typedef unsigned short pinmux_enum_t; 17typedef unsigned short pinmux_enum_t;
17typedef unsigned short pinmux_flag_t; 18typedef unsigned short pinmux_flag_t;
18 19
19#define PINMUX_TYPE_NONE 0 20enum {
20#define PINMUX_TYPE_FUNCTION 1 21 PINMUX_TYPE_NONE,
21#define PINMUX_TYPE_GPIO 2
22#define PINMUX_TYPE_OUTPUT 3
23#define PINMUX_TYPE_INPUT 4
24#define PINMUX_TYPE_INPUT_PULLUP 5
25#define PINMUX_TYPE_INPUT_PULLDOWN 6
26 22
27#define PINMUX_FLAG_TYPE (0x7) 23 PINMUX_TYPE_FUNCTION,
28#define PINMUX_FLAG_WANT_PULLUP (1 << 3) 24 PINMUX_TYPE_GPIO,
29#define PINMUX_FLAG_WANT_PULLDOWN (1 << 4) 25 PINMUX_TYPE_OUTPUT,
26 PINMUX_TYPE_INPUT,
27 PINMUX_TYPE_INPUT_PULLUP,
28 PINMUX_TYPE_INPUT_PULLDOWN,
29
30 PINMUX_FLAG_TYPE, /* must be last */
31};
30 32
31#define PINMUX_FLAG_DBIT_SHIFT 5 33#define PINMUX_FLAG_DBIT_SHIFT 5
32#define PINMUX_FLAG_DBIT (0x1f << PINMUX_FLAG_DBIT_SHIFT) 34#define PINMUX_FLAG_DBIT (0x1f << PINMUX_FLAG_DBIT_SHIFT)
@@ -36,9 +38,12 @@ typedef unsigned short pinmux_flag_t;
36struct pinmux_gpio { 38struct pinmux_gpio {
37 pinmux_enum_t enum_id; 39 pinmux_enum_t enum_id;
38 pinmux_flag_t flags; 40 pinmux_flag_t flags;
41 const char *name;
39}; 42};
40 43
41#define PINMUX_GPIO(gpio, data_or_mark) [gpio] = { data_or_mark } 44#define PINMUX_GPIO(gpio, data_or_mark) \
45 [gpio] = { .name = __stringify(gpio), .enum_id = data_or_mark, .flags = PINMUX_TYPE_NONE }
46
42#define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0 47#define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0
43 48
44struct pinmux_cfg_reg { 49struct pinmux_cfg_reg {
@@ -89,7 +94,7 @@ struct pfc_window {
89 unsigned long size; 94 unsigned long size;
90}; 95};
91 96
92struct pinmux_info { 97struct sh_pfc {
93 char *name; 98 char *name;
94 pinmux_enum_t reserved_id; 99 pinmux_enum_t reserved_id;
95 struct pinmux_range data; 100 struct pinmux_range data;
@@ -112,17 +117,45 @@ struct pinmux_info {
112 struct pinmux_irq *gpio_irq; 117 struct pinmux_irq *gpio_irq;
113 unsigned int gpio_irq_size; 118 unsigned int gpio_irq_size;
114 119
120 spinlock_t lock;
121
115 struct resource *resource; 122 struct resource *resource;
116 unsigned int num_resources; 123 unsigned int num_resources;
117 struct pfc_window *window; 124 struct pfc_window *window;
118 125
119 unsigned long unlock_reg; 126 unsigned long unlock_reg;
120
121 struct gpio_chip chip;
122}; 127};
123 128
124int register_pinmux(struct pinmux_info *pip); 129/* XXX compat for now */
125int unregister_pinmux(struct pinmux_info *pip); 130#define pinmux_info sh_pfc
131
132/* drivers/sh/pfc/gpio.c */
133int sh_pfc_register_gpiochip(struct sh_pfc *pfc);
134
135/* drivers/sh/pfc/pinctrl.c */
136int sh_pfc_register_pinctrl(struct sh_pfc *pfc);
137
138/* drivers/sh/pfc/core.c */
139int register_sh_pfc(struct sh_pfc *pfc);
140
141int sh_pfc_read_bit(struct pinmux_data_reg *dr, unsigned long in_pos);
142void sh_pfc_write_bit(struct pinmux_data_reg *dr, unsigned long in_pos,
143 unsigned long value);
144int sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio,
145 struct pinmux_data_reg **drp, int *bitp);
146int sh_pfc_gpio_to_enum(struct sh_pfc *pfc, unsigned gpio, int pos,
147 pinmux_enum_t *enum_idp);
148int sh_pfc_config_gpio(struct sh_pfc *pfc, unsigned gpio, int pinmux_type,
149 int cfg_mode);
150
151/* xxx */
152static inline int register_pinmux(struct pinmux_info *pip)
153{
154 struct sh_pfc *pfc = pip;
155 return register_sh_pfc(pfc);
156}
157
158enum { GPIO_CFG_DRYRUN, GPIO_CFG_REQ, GPIO_CFG_FREE };
126 159
127/* helper macro for port */ 160/* helper macro for port */
128#define PORT_1(fn, pfx, sfx) fn(pfx, sfx) 161#define PORT_1(fn, pfx, sfx) fn(pfx, sfx)
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-16 20:48:29 -0500