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-rw-r--r--drivers/gpu/drm/radeon/radeon_cursor.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_legacy_crtc.c11
-rw-r--r--drivers/gpu/drm/radeon/radeon_mode.h1
3 files changed, 9 insertions, 5 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_cursor.c b/drivers/gpu/drm/radeon/radeon_cursor.c
index 5232441f119..5f8ce370c4f 100644
--- a/drivers/gpu/drm/radeon/radeon_cursor.c
+++ b/drivers/gpu/drm/radeon/radeon_cursor.c
@@ -113,7 +113,7 @@ static void radeon_set_cursor(struct drm_crtc *crtc, struct drm_gem_object *obj,
113 WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, gpu_addr); 113 WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, gpu_addr);
114 else 114 else
115 /* offset is from DISP(2)_BASE_ADDRESS */ 115 /* offset is from DISP(2)_BASE_ADDRESS */
116 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, gpu_addr); 116 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, (gpu_addr-radeon_crtc->legacy_display_base_addr));
117} 117}
118 118
119int radeon_crtc_cursor_set(struct drm_crtc *crtc, 119int radeon_crtc_cursor_set(struct drm_crtc *crtc,
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
index 8086ecf7f03..14c1a5107fc 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
@@ -244,7 +244,12 @@ int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
244 if (radeon_gem_object_pin(obj, RADEON_GEM_DOMAIN_VRAM, &base)) { 244 if (radeon_gem_object_pin(obj, RADEON_GEM_DOMAIN_VRAM, &base)) {
245 return -EINVAL; 245 return -EINVAL;
246 } 246 }
247 crtc_offset = (u32)base; 247 /* if scanout was in GTT this really wouldn't work */
248 /* crtc offset is from display base addr not FB location */
249 radeon_crtc->legacy_display_base_addr = rdev->mc.vram_location;
250
251 base -= radeon_crtc->legacy_display_base_addr;
252
248 crtc_offset_cntl = 0; 253 crtc_offset_cntl = 0;
249 254
250 pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8); 255 pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
@@ -303,11 +308,9 @@ int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
303 308
304 base &= ~7; 309 base &= ~7;
305 310
306 /* update sarea TODO */
307
308 crtc_offset = (u32)base; 311 crtc_offset = (u32)base;
309 312
310 WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, rdev->mc.vram_location); 313 WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr);
311 314
312 if (ASIC_IS_R300(rdev)) { 315 if (ASIC_IS_R300(rdev)) {
313 if (radeon_crtc->crtc_id) 316 if (radeon_crtc->crtc_id)
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
index 9173b687462..86f766e868e 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -185,6 +185,7 @@ struct radeon_crtc {
185 uint64_t cursor_addr; 185 uint64_t cursor_addr;
186 int cursor_width; 186 int cursor_width;
187 int cursor_height; 187 int cursor_height;
188 uint32_t legacy_display_base_addr;
188}; 189};
189 190
190#define RADEON_USE_RMX 1 191#define RADEON_USE_RMX 1