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-rw-r--r--arch/arm/mach-omap1/board-ams-delta.c2
-rw-r--r--arch/arm/mach-omap1/board-generic.c4
-rw-r--r--arch/arm/mach-omap1/board-h2.c2
-rw-r--r--arch/arm/mach-omap1/board-h3.c2
-rw-r--r--arch/arm/mach-omap1/board-htcherald.c2
-rw-r--r--arch/arm/mach-omap1/board-innovator.c2
-rw-r--r--arch/arm/mach-omap1/board-nokia770.c2
-rw-r--r--arch/arm/mach-omap1/board-osk.c2
-rw-r--r--arch/arm/mach-omap1/board-palmte.c2
-rw-r--r--arch/arm/mach-omap1/board-palmtt.c2
-rw-r--r--arch/arm/mach-omap1/board-palmz71.c2
-rw-r--r--arch/arm/mach-omap1/board-sx1.c2
-rw-r--r--arch/arm/mach-omap1/board-voiceblue.c3
-rw-r--r--arch/arm/mach-omap1/clock_data.c3
-rw-r--r--arch/arm/mach-omap1/include/mach/usb.h165
-rw-r--r--arch/arm/mach-omap1/timer.c3
-rw-r--r--arch/arm/mach-omap1/usb.c116
-rw-r--r--arch/arm/mach-omap2/Kconfig3
-rw-r--r--arch/arm/mach-omap2/Makefile10
-rw-r--r--arch/arm/mach-omap2/board-2430sdp.c11
-rw-r--r--arch/arm/mach-omap2/board-apollon.c18
-rw-r--r--arch/arm/mach-omap2/board-generic.c18
-rw-r--r--arch/arm/mach-omap2/board-h4.c13
-rw-r--r--arch/arm/mach-omap2/clock2420_data.c43
-rw-r--r--arch/arm/mach-omap2/clock2430_data.c49
-rw-r--r--arch/arm/mach-omap2/clock3xxx_data.c36
-rw-r--r--arch/arm/mach-omap2/clock44xx_data.c34
-rw-r--r--arch/arm/mach-omap2/clockdomain.h4
-rw-r--r--arch/arm/mach-omap2/clockdomain33xx.c74
-rw-r--r--arch/arm/mach-omap2/clockdomains2420_data.c2
-rw-r--r--arch/arm/mach-omap2/clockdomains2430_data.c2
-rw-r--r--arch/arm/mach-omap2/clockdomains33xx_data.c196
-rw-r--r--arch/arm/mach-omap2/clockdomains3xxx_data.c2
-rw-r--r--arch/arm/mach-omap2/clockdomains44xx_data.c2
-rw-r--r--arch/arm/mach-omap2/clockdomains_common_data.c24
-rw-r--r--arch/arm/mach-omap2/cm-regbits-33xx.h687
-rw-r--r--arch/arm/mach-omap2/cm33xx.c313
-rw-r--r--arch/arm/mach-omap2/cm33xx.h420
-rw-r--r--arch/arm/mach-omap2/common.h3
-rw-r--r--arch/arm/mach-omap2/control.c43
-rw-r--r--arch/arm/mach-omap2/control.h41
-rw-r--r--arch/arm/mach-omap2/dsp.c4
-rw-r--r--arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h1
-rw-r--r--arch/arm/mach-omap2/include/mach/debug-macro.S17
-rw-r--r--arch/arm/mach-omap2/io.c13
-rw-r--r--arch/arm/mach-omap2/irq.c2
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.c427
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2420_data.c10
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2430_data.c16
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c8
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_3xxx_data.c33
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_44xx_data.c10
-rw-r--r--arch/arm/mach-omap2/powerdomain.h23
-rw-r--r--arch/arm/mach-omap2/powerdomain33xx.c229
-rw-r--r--arch/arm/mach-omap2/powerdomains33xx_data.c185
-rw-r--r--arch/arm/mach-omap2/prm-regbits-33xx.h357
-rw-r--r--arch/arm/mach-omap2/prm33xx.c135
-rw-r--r--arch/arm/mach-omap2/prm33xx.h129
-rw-r--r--arch/arm/mach-omap2/timer.c87
-rw-r--r--arch/arm/mach-omap2/usb-fs.c359
-rw-r--r--arch/arm/mach-omap2/voltage.h1
-rw-r--r--arch/arm/mach-omap2/voltagedomains33xx_data.c43
-rw-r--r--arch/arm/plat-omap/Makefile2
-rw-r--r--arch/arm/plat-omap/dma.c59
-rw-r--r--arch/arm/plat-omap/dmtimer.c111
-rw-r--r--arch/arm/plat-omap/include/plat/board.h38
-rw-r--r--arch/arm/plat-omap/include/plat/clock.h2
-rw-r--r--arch/arm/plat-omap/include/plat/dmtimer.h22
-rw-r--r--arch/arm/plat-omap/include/plat/dsp.h3
-rw-r--r--arch/arm/plat-omap/include/plat/omap_hwmod.h2
-rw-r--r--arch/arm/plat-omap/include/plat/serial.h4
-rw-r--r--arch/arm/plat-omap/include/plat/uncompress.h6
-rw-r--r--arch/arm/plat-omap/include/plat/usb.h196
-rw-r--r--arch/arm/plat-omap/usb.c145
-rw-r--r--drivers/usb/gadget/Kconfig2
-rw-r--r--drivers/usb/gadget/omap_udc.c3
-rw-r--r--drivers/usb/host/Kconfig2
-rw-r--r--drivers/usb/host/ohci-omap.c7
-rw-r--r--drivers/usb/otg/isp1301_omap.c2
79 files changed, 3752 insertions, 1307 deletions
diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c
index f2f8a584701..c53469802c0 100644
--- a/arch/arm/mach-omap1/board-ams-delta.c
+++ b/arch/arm/mach-omap1/board-ams-delta.c
@@ -37,12 +37,12 @@
37#include <plat/board-ams-delta.h> 37#include <plat/board-ams-delta.h>
38#include <plat/keypad.h> 38#include <plat/keypad.h>
39#include <plat/mux.h> 39#include <plat/mux.h>
40#include <plat/usb.h>
41#include <plat/board.h> 40#include <plat/board.h>
42 41
43#include <mach/hardware.h> 42#include <mach/hardware.h>
44#include <mach/ams-delta-fiq.h> 43#include <mach/ams-delta-fiq.h>
45#include <mach/camera.h> 44#include <mach/camera.h>
45#include <mach/usb.h>
46 46
47#include "iomap.h" 47#include "iomap.h"
48#include "common.h" 48#include "common.h"
diff --git a/arch/arm/mach-omap1/board-generic.c b/arch/arm/mach-omap1/board-generic.c
index e75e2d55a2d..6ec385e2b98 100644
--- a/arch/arm/mach-omap1/board-generic.c
+++ b/arch/arm/mach-omap1/board-generic.c
@@ -23,8 +23,10 @@
23#include <asm/mach/map.h> 23#include <asm/mach/map.h>
24 24
25#include <plat/mux.h> 25#include <plat/mux.h>
26#include <plat/usb.h>
27#include <plat/board.h> 26#include <plat/board.h>
27
28#include <mach/usb.h>
29
28#include "common.h" 30#include "common.h"
29 31
30/* assume no Mini-AB port */ 32/* assume no Mini-AB port */
diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
index a28e989a63f..44a4ab195fb 100644
--- a/arch/arm/mach-omap1/board-h2.c
+++ b/arch/arm/mach-omap1/board-h2.c
@@ -40,11 +40,11 @@
40#include <plat/dma.h> 40#include <plat/dma.h>
41#include <plat/tc.h> 41#include <plat/tc.h>
42#include <plat/irda.h> 42#include <plat/irda.h>
43#include <plat/usb.h>
44#include <plat/keypad.h> 43#include <plat/keypad.h>
45#include <plat/flash.h> 44#include <plat/flash.h>
46 45
47#include <mach/hardware.h> 46#include <mach/hardware.h>
47#include <mach/usb.h>
48 48
49#include "common.h" 49#include "common.h"
50#include "board-h2.h" 50#include "board-h2.h"
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c
index 108a8640fc6..86cb5a04a40 100644
--- a/arch/arm/mach-omap1/board-h3.c
+++ b/arch/arm/mach-omap1/board-h3.c
@@ -40,13 +40,13 @@
40 40
41#include <plat/mux.h> 41#include <plat/mux.h>
42#include <plat/tc.h> 42#include <plat/tc.h>
43#include <plat/usb.h>
44#include <plat/keypad.h> 43#include <plat/keypad.h>
45#include <plat/dma.h> 44#include <plat/dma.h>
46#include <plat/flash.h> 45#include <plat/flash.h>
47 46
48#include <mach/hardware.h> 47#include <mach/hardware.h>
49#include <mach/irqs.h> 48#include <mach/irqs.h>
49#include <mach/usb.h>
50 50
51#include "common.h" 51#include "common.h"
52#include "board-h3.h" 52#include "board-h3.h"
diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c
index 118a9d4a4c5..b3f6e943e66 100644
--- a/arch/arm/mach-omap1/board-htcherald.c
+++ b/arch/arm/mach-omap1/board-htcherald.c
@@ -44,10 +44,10 @@
44#include <plat/omap7xx.h> 44#include <plat/omap7xx.h>
45#include <plat/board.h> 45#include <plat/board.h>
46#include <plat/keypad.h> 46#include <plat/keypad.h>
47#include <plat/usb.h>
48#include <plat/mmc.h> 47#include <plat/mmc.h>
49 48
50#include <mach/irqs.h> 49#include <mach/irqs.h>
50#include <mach/usb.h>
51 51
52#include "common.h" 52#include "common.h"
53 53
diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c
index 7970223a559..f21c2966daa 100644
--- a/arch/arm/mach-omap1/board-innovator.c
+++ b/arch/arm/mach-omap1/board-innovator.c
@@ -35,11 +35,11 @@
35#include <plat/flash.h> 35#include <plat/flash.h>
36#include <plat/fpga.h> 36#include <plat/fpga.h>
37#include <plat/tc.h> 37#include <plat/tc.h>
38#include <plat/usb.h>
39#include <plat/keypad.h> 38#include <plat/keypad.h>
40#include <plat/mmc.h> 39#include <plat/mmc.h>
41 40
42#include <mach/hardware.h> 41#include <mach/hardware.h>
42#include <mach/usb.h>
43 43
44#include "iomap.h" 44#include "iomap.h"
45#include "common.h" 45#include "common.h"
diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
index 7212ae97f44..4007a372481 100644
--- a/arch/arm/mach-omap1/board-nokia770.c
+++ b/arch/arm/mach-omap1/board-nokia770.c
@@ -26,7 +26,6 @@
26#include <asm/mach/map.h> 26#include <asm/mach/map.h>
27 27
28#include <plat/mux.h> 28#include <plat/mux.h>
29#include <plat/usb.h>
30#include <plat/board.h> 29#include <plat/board.h>
31#include <plat/keypad.h> 30#include <plat/keypad.h>
32#include <plat/lcd_mipid.h> 31#include <plat/lcd_mipid.h>
@@ -34,6 +33,7 @@
34#include <plat/clock.h> 33#include <plat/clock.h>
35 34
36#include <mach/hardware.h> 35#include <mach/hardware.h>
36#include <mach/usb.h>
37 37
38#include "common.h" 38#include "common.h"
39 39
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index da8d872d3d1..8784705edb6 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -45,11 +45,11 @@
45#include <asm/mach/map.h> 45#include <asm/mach/map.h>
46 46
47#include <plat/flash.h> 47#include <plat/flash.h>
48#include <plat/usb.h>
49#include <plat/mux.h> 48#include <plat/mux.h>
50#include <plat/tc.h> 49#include <plat/tc.h>
51 50
52#include <mach/hardware.h> 51#include <mach/hardware.h>
52#include <mach/usb.h>
53 53
54#include "common.h" 54#include "common.h"
55 55
diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c
index 949b62a7369..26bcb9defcd 100644
--- a/arch/arm/mach-omap1/board-palmte.c
+++ b/arch/arm/mach-omap1/board-palmte.c
@@ -35,7 +35,6 @@
35 35
36#include <plat/flash.h> 36#include <plat/flash.h>
37#include <plat/mux.h> 37#include <plat/mux.h>
38#include <plat/usb.h>
39#include <plat/tc.h> 38#include <plat/tc.h>
40#include <plat/dma.h> 39#include <plat/dma.h>
41#include <plat/board.h> 40#include <plat/board.h>
@@ -43,6 +42,7 @@
43#include <plat/keypad.h> 42#include <plat/keypad.h>
44 43
45#include <mach/hardware.h> 44#include <mach/hardware.h>
45#include <mach/usb.h>
46 46
47#include "common.h" 47#include "common.h"
48 48
diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c
index 7f1e1cf2bf4..4d099446dfa 100644
--- a/arch/arm/mach-omap1/board-palmtt.c
+++ b/arch/arm/mach-omap1/board-palmtt.c
@@ -35,7 +35,6 @@
35#include <plat/led.h> 35#include <plat/led.h>
36#include <plat/flash.h> 36#include <plat/flash.h>
37#include <plat/mux.h> 37#include <plat/mux.h>
38#include <plat/usb.h>
39#include <plat/dma.h> 38#include <plat/dma.h>
40#include <plat/tc.h> 39#include <plat/tc.h>
41#include <plat/board.h> 40#include <plat/board.h>
@@ -43,6 +42,7 @@
43#include <plat/keypad.h> 42#include <plat/keypad.h>
44 43
45#include <mach/hardware.h> 44#include <mach/hardware.h>
45#include <mach/usb.h>
46 46
47#include "common.h" 47#include "common.h"
48 48
diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c
index 3c71c6bace2..cc71a26723e 100644
--- a/arch/arm/mach-omap1/board-palmz71.c
+++ b/arch/arm/mach-omap1/board-palmz71.c
@@ -37,7 +37,6 @@
37 37
38#include <plat/flash.h> 38#include <plat/flash.h>
39#include <plat/mux.h> 39#include <plat/mux.h>
40#include <plat/usb.h>
41#include <plat/dma.h> 40#include <plat/dma.h>
42#include <plat/tc.h> 41#include <plat/tc.h>
43#include <plat/board.h> 42#include <plat/board.h>
@@ -45,6 +44,7 @@
45#include <plat/keypad.h> 44#include <plat/keypad.h>
46 45
47#include <mach/hardware.h> 46#include <mach/hardware.h>
47#include <mach/usb.h>
48 48
49#include "common.h" 49#include "common.h"
50 50
diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c
index 3b7b82b1368..8c665bd16ac 100644
--- a/arch/arm/mach-omap1/board-sx1.c
+++ b/arch/arm/mach-omap1/board-sx1.c
@@ -37,13 +37,13 @@
37#include <plat/mux.h> 37#include <plat/mux.h>
38#include <plat/dma.h> 38#include <plat/dma.h>
39#include <plat/irda.h> 39#include <plat/irda.h>
40#include <plat/usb.h>
41#include <plat/tc.h> 40#include <plat/tc.h>
42#include <plat/board.h> 41#include <plat/board.h>
43#include <plat/keypad.h> 42#include <plat/keypad.h>
44#include <plat/board-sx1.h> 43#include <plat/board-sx1.h>
45 44
46#include <mach/hardware.h> 45#include <mach/hardware.h>
46#include <mach/usb.h>
47 47
48#include "common.h" 48#include "common.h"
49 49
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c
index afd67f0ec49..3497769eb35 100644
--- a/arch/arm/mach-omap1/board-voiceblue.c
+++ b/arch/arm/mach-omap1/board-voiceblue.c
@@ -35,9 +35,10 @@
35#include <plat/flash.h> 35#include <plat/flash.h>
36#include <plat/mux.h> 36#include <plat/mux.h>
37#include <plat/tc.h> 37#include <plat/tc.h>
38#include <plat/usb.h> 38#include <plat/board.h>
39 39
40#include <mach/hardware.h> 40#include <mach/hardware.h>
41#include <mach/usb.h>
41 42
42#include "common.h" 43#include "common.h"
43 44
diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c
index c6ce93f71d0..c007d80dfb6 100644
--- a/arch/arm/mach-omap1/clock_data.c
+++ b/arch/arm/mach-omap1/clock_data.c
@@ -25,10 +25,11 @@
25#include <plat/clock.h> 25#include <plat/clock.h>
26#include <plat/cpu.h> 26#include <plat/cpu.h>
27#include <plat/clkdev_omap.h> 27#include <plat/clkdev_omap.h>
28#include <plat/board.h>
28#include <plat/sram.h> /* for omap_sram_reprogram_clock() */ 29#include <plat/sram.h> /* for omap_sram_reprogram_clock() */
29#include <plat/usb.h> /* for OTG_BASE */
30 30
31#include <mach/hardware.h> 31#include <mach/hardware.h>
32#include <mach/usb.h> /* for OTG_BASE */
32 33
33#include "iomap.h" 34#include "iomap.h"
34#include "clock.h" 35#include "clock.h"
diff --git a/arch/arm/mach-omap1/include/mach/usb.h b/arch/arm/mach-omap1/include/mach/usb.h
new file mode 100644
index 00000000000..753cd5ce694
--- /dev/null
+++ b/arch/arm/mach-omap1/include/mach/usb.h
@@ -0,0 +1,165 @@
1/*
2 * FIXME correct answer depends on hmc_mode,
3 * as does (on omap1) any nonzero value for config->otg port number
4 */
5#ifdef CONFIG_USB_GADGET_OMAP
6#define is_usb0_device(config) 1
7#else
8#define is_usb0_device(config) 0
9#endif
10
11struct omap_usb_config {
12 /* Configure drivers according to the connectors on your board:
13 * - "A" connector (rectagular)
14 * ... for host/OHCI use, set "register_host".
15 * - "B" connector (squarish) or "Mini-B"
16 * ... for device/gadget use, set "register_dev".
17 * - "Mini-AB" connector (very similar to Mini-B)
18 * ... for OTG use as device OR host, initialize "otg"
19 */
20 unsigned register_host:1;
21 unsigned register_dev:1;
22 u8 otg; /* port number, 1-based: usb1 == 2 */
23
24 u8 hmc_mode;
25
26 /* implicitly true if otg: host supports remote wakeup? */
27 u8 rwc;
28
29 /* signaling pins used to talk to transceiver on usbN:
30 * 0 == usbN unused
31 * 2 == usb0-only, using internal transceiver
32 * 3 == 3 wire bidirectional
33 * 4 == 4 wire bidirectional
34 * 6 == 6 wire unidirectional (or TLL)
35 */
36 u8 pins[3];
37
38 struct platform_device *udc_device;
39 struct platform_device *ohci_device;
40 struct platform_device *otg_device;
41
42 u32 (*usb0_init)(unsigned nwires, unsigned is_device);
43 u32 (*usb1_init)(unsigned nwires);
44 u32 (*usb2_init)(unsigned nwires, unsigned alt_pingroup);
45
46 int (*ocpi_enable)(void);
47};
48
49void omap_otg_init(struct omap_usb_config *config);
50
51#if defined(CONFIG_USB) || defined(CONFIG_USB_MODULE)
52void omap1_usb_init(struct omap_usb_config *pdata);
53#else
54static inline void omap1_usb_init(struct omap_usb_config *pdata)
55{
56}
57#endif
58
59#define OMAP1_OTG_BASE 0xfffb0400
60#define OMAP1_UDC_BASE 0xfffb4000
61#define OMAP1_OHCI_BASE 0xfffba000
62
63#define OMAP2_OHCI_BASE 0x4805e000
64#define OMAP2_UDC_BASE 0x4805e200
65#define OMAP2_OTG_BASE 0x4805e300
66#define OTG_BASE OMAP1_OTG_BASE
67#define UDC_BASE OMAP1_UDC_BASE
68#define OMAP_OHCI_BASE OMAP1_OHCI_BASE
69
70/*
71 * OTG and transceiver registers, for OMAPs starting with ARM926
72 */
73#define OTG_REV (OTG_BASE + 0x00)
74#define OTG_SYSCON_1 (OTG_BASE + 0x04)
75# define USB2_TRX_MODE(w) (((w)>>24)&0x07)
76# define USB1_TRX_MODE(w) (((w)>>20)&0x07)
77# define USB0_TRX_MODE(w) (((w)>>16)&0x07)
78# define OTG_IDLE_EN (1 << 15)
79# define HST_IDLE_EN (1 << 14)
80# define DEV_IDLE_EN (1 << 13)
81# define OTG_RESET_DONE (1 << 2)
82# define OTG_SOFT_RESET (1 << 1)
83#define OTG_SYSCON_2 (OTG_BASE + 0x08)
84# define OTG_EN (1 << 31)
85# define USBX_SYNCHRO (1 << 30)
86# define OTG_MST16 (1 << 29)
87# define SRP_GPDATA (1 << 28)
88# define SRP_GPDVBUS (1 << 27)
89# define SRP_GPUVBUS(w) (((w)>>24)&0x07)
90# define A_WAIT_VRISE(w) (((w)>>20)&0x07)
91# define B_ASE_BRST(w) (((w)>>16)&0x07)
92# define SRP_DPW (1 << 14)
93# define SRP_DATA (1 << 13)
94# define SRP_VBUS (1 << 12)
95# define OTG_PADEN (1 << 10)
96# define HMC_PADEN (1 << 9)
97# define UHOST_EN (1 << 8)
98# define HMC_TLLSPEED (1 << 7)
99# define HMC_TLLATTACH (1 << 6)
100# define OTG_HMC(w) (((w)>>0)&0x3f)
101#define OTG_CTRL (OTG_BASE + 0x0c)
102# define OTG_USB2_EN (1 << 29)
103# define OTG_USB2_DP (1 << 28)
104# define OTG_USB2_DM (1 << 27)
105# define OTG_USB1_EN (1 << 26)
106# define OTG_USB1_DP (1 << 25)
107# define OTG_USB1_DM (1 << 24)
108# define OTG_USB0_EN (1 << 23)
109# define OTG_USB0_DP (1 << 22)
110# define OTG_USB0_DM (1 << 21)
111# define OTG_ASESSVLD (1 << 20)
112# define OTG_BSESSEND (1 << 19)
113# define OTG_BSESSVLD (1 << 18)
114# define OTG_VBUSVLD (1 << 17)
115# define OTG_ID (1 << 16)
116# define OTG_DRIVER_SEL (1 << 15)
117# define OTG_A_SETB_HNPEN (1 << 12)
118# define OTG_A_BUSREQ (1 << 11)
119# define OTG_B_HNPEN (1 << 9)
120# define OTG_B_BUSREQ (1 << 8)
121# define OTG_BUSDROP (1 << 7)
122# define OTG_PULLDOWN (1 << 5)
123# define OTG_PULLUP (1 << 4)
124# define OTG_DRV_VBUS (1 << 3)
125# define OTG_PD_VBUS (1 << 2)
126# define OTG_PU_VBUS (1 << 1)
127# define OTG_PU_ID (1 << 0)
128#define OTG_IRQ_EN (OTG_BASE + 0x10) /* 16-bit */
129# define DRIVER_SWITCH (1 << 15)
130# define A_VBUS_ERR (1 << 13)
131# define A_REQ_TMROUT (1 << 12)
132# define A_SRP_DETECT (1 << 11)
133# define B_HNP_FAIL (1 << 10)
134# define B_SRP_TMROUT (1 << 9)
135# define B_SRP_DONE (1 << 8)
136# define B_SRP_STARTED (1 << 7)
137# define OPRT_CHG (1 << 0)
138#define OTG_IRQ_SRC (OTG_BASE + 0x14) /* 16-bit */
139 // same bits as in IRQ_EN
140#define OTG_OUTCTRL (OTG_BASE + 0x18) /* 16-bit */
141# define OTGVPD (1 << 14)
142# define OTGVPU (1 << 13)
143# define OTGPUID (1 << 12)
144# define USB2VDR (1 << 10)
145# define USB2PDEN (1 << 9)
146# define USB2PUEN (1 << 8)
147# define USB1VDR (1 << 6)
148# define USB1PDEN (1 << 5)
149# define USB1PUEN (1 << 4)
150# define USB0VDR (1 << 2)
151# define USB0PDEN (1 << 1)
152# define USB0PUEN (1 << 0)
153#define OTG_TEST (OTG_BASE + 0x20) /* 16-bit */
154#define OTG_VENDOR_CODE (OTG_BASE + 0xfc) /* 16-bit */
155
156/*-------------------------------------------------------------------------*/
157
158/* OMAP1 */
159#define USB_TRANSCEIVER_CTRL (0xfffe1000 + 0x0064)
160# define CONF_USB2_UNI_R (1 << 8)
161# define CONF_USB1_UNI_R (1 << 7)
162# define CONF_USB_PORT0_R(x) (((x)>>4)&0x7)
163# define CONF_USB0_ISOLATE_R (1 << 3)
164# define CONF_USB_PWRDN_DM_R (1 << 2)
165# define CONF_USB_PWRDN_DP_R (1 << 1)
diff --git a/arch/arm/mach-omap1/timer.c b/arch/arm/mach-omap1/timer.c
index 64c65bcb2d6..aa81593db1a 100644
--- a/arch/arm/mach-omap1/timer.c
+++ b/arch/arm/mach-omap1/timer.c
@@ -140,7 +140,8 @@ static int __init omap1_dm_timer_init(void)
140 } 140 }
141 141
142 pdata->set_timer_src = omap1_dm_timer_set_src; 142 pdata->set_timer_src = omap1_dm_timer_set_src;
143 pdata->needs_manual_reset = 1; 143 pdata->timer_capability = OMAP_TIMER_ALWON |
144 OMAP_TIMER_NEEDS_RESET;
144 145
145 ret = platform_device_add_data(pdev, pdata, sizeof(*pdata)); 146 ret = platform_device_add_data(pdev, pdata, sizeof(*pdata));
146 if (ret) { 147 if (ret) {
diff --git a/arch/arm/mach-omap1/usb.c b/arch/arm/mach-omap1/usb.c
index e61afd92276..65f88176fba 100644
--- a/arch/arm/mach-omap1/usb.c
+++ b/arch/arm/mach-omap1/usb.c
@@ -27,7 +27,8 @@
27#include <asm/irq.h> 27#include <asm/irq.h>
28 28
29#include <plat/mux.h> 29#include <plat/mux.h>
30#include <plat/usb.h> 30
31#include <mach/usb.h>
31 32
32#include "common.h" 33#include "common.h"
33 34
@@ -55,6 +56,119 @@
55#define INT_USB_IRQ_HGEN INT_USB_HHC_1 56#define INT_USB_IRQ_HGEN INT_USB_HHC_1
56#define INT_USB_IRQ_OTG IH2_BASE + 8 57#define INT_USB_IRQ_OTG IH2_BASE + 8
57 58
59#ifdef CONFIG_ARCH_OMAP_OTG
60
61void __init
62omap_otg_init(struct omap_usb_config *config)
63{
64 u32 syscon;
65 int alt_pingroup = 0;
66
67 /* NOTE: no bus or clock setup (yet?) */
68
69 syscon = omap_readl(OTG_SYSCON_1) & 0xffff;
70 if (!(syscon & OTG_RESET_DONE))
71 pr_debug("USB resets not complete?\n");
72
73 //omap_writew(0, OTG_IRQ_EN);
74
75 /* pin muxing and transceiver pinouts */
76 if (config->pins[0] > 2) /* alt pingroup 2 */
77 alt_pingroup = 1;
78 syscon |= config->usb0_init(config->pins[0], is_usb0_device(config));
79 syscon |= config->usb1_init(config->pins[1]);
80 syscon |= config->usb2_init(config->pins[2], alt_pingroup);
81 pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1));
82 omap_writel(syscon, OTG_SYSCON_1);
83
84 syscon = config->hmc_mode;
85 syscon |= USBX_SYNCHRO | (4 << 16) /* B_ASE0_BRST */;
86#ifdef CONFIG_USB_OTG
87 if (config->otg)
88 syscon |= OTG_EN;
89#endif
90 if (cpu_class_is_omap1())
91 pr_debug("USB_TRANSCEIVER_CTRL = %03x\n",
92 omap_readl(USB_TRANSCEIVER_CTRL));
93 pr_debug("OTG_SYSCON_2 = %08x\n", omap_readl(OTG_SYSCON_2));
94 omap_writel(syscon, OTG_SYSCON_2);
95
96 printk("USB: hmc %d", config->hmc_mode);
97 if (!alt_pingroup)
98 printk(", usb2 alt %d wires", config->pins[2]);
99 else if (config->pins[0])
100 printk(", usb0 %d wires%s", config->pins[0],
101 is_usb0_device(config) ? " (dev)" : "");
102 if (config->pins[1])
103 printk(", usb1 %d wires", config->pins[1]);
104 if (!alt_pingroup && config->pins[2])
105 printk(", usb2 %d wires", config->pins[2]);
106 if (config->otg)
107 printk(", Mini-AB on usb%d", config->otg - 1);
108 printk("\n");
109
110 if (cpu_class_is_omap1()) {
111 u16 w;
112
113 /* leave USB clocks/controllers off until needed */
114 w = omap_readw(ULPD_SOFT_REQ);
115 w &= ~SOFT_USB_CLK_REQ;
116 omap_writew(w, ULPD_SOFT_REQ);
117
118 w = omap_readw(ULPD_CLOCK_CTRL);
119 w &= ~USB_MCLK_EN;
120 w |= DIS_USB_PVCI_CLK;
121 omap_writew(w, ULPD_CLOCK_CTRL);
122 }
123 syscon = omap_readl(OTG_SYSCON_1);
124 syscon |= HST_IDLE_EN|DEV_IDLE_EN|OTG_IDLE_EN;
125
126#ifdef CONFIG_USB_GADGET_OMAP
127 if (config->otg || config->register_dev) {
128 struct platform_device *udc_device = config->udc_device;
129 int status;
130
131 syscon &= ~DEV_IDLE_EN;
132 udc_device->dev.platform_data = config;
133 status = platform_device_register(udc_device);
134 if (status)
135 pr_debug("can't register UDC device, %d\n", status);
136 }
137#endif
138
139#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
140 if (config->otg || config->register_host) {
141 struct platform_device *ohci_device = config->ohci_device;
142 int status;
143
144 syscon &= ~HST_IDLE_EN;
145 ohci_device->dev.platform_data = config;
146 status = platform_device_register(ohci_device);
147 if (status)
148 pr_debug("can't register OHCI device, %d\n", status);
149 }
150#endif
151
152#ifdef CONFIG_USB_OTG
153 if (config->otg) {
154 struct platform_device *otg_device = config->otg_device;
155 int status;
156
157 syscon &= ~OTG_IDLE_EN;
158 otg_device->dev.platform_data = config;
159 status = platform_device_register(otg_device);
160 if (status)
161 pr_debug("can't register OTG device, %d\n", status);
162 }
163#endif
164 pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1));
165 omap_writel(syscon, OTG_SYSCON_1);
166}
167
168#else
169void omap_otg_init(struct omap_usb_config *config) {}
170#endif
171
58#ifdef CONFIG_USB_GADGET_OMAP 172#ifdef CONFIG_USB_GADGET_OMAP
59 173
60static struct resource udc_resources[] = { 174static struct resource udc_resources[] = {
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 4cf5142f22c..042f157a8f9 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -64,19 +64,16 @@ config SOC_OMAP2420
64 depends on ARCH_OMAP2 64 depends on ARCH_OMAP2
65 default y 65 default y
66 select OMAP_DM_TIMER 66 select OMAP_DM_TIMER
67 select ARCH_OMAP_OTG
68 67
69config SOC_OMAP2430 68config SOC_OMAP2430
70 bool "OMAP2430 support" 69 bool "OMAP2430 support"
71 depends on ARCH_OMAP2 70 depends on ARCH_OMAP2
72 default y 71 default y
73 select ARCH_OMAP_OTG
74 72
75config SOC_OMAP3430 73config SOC_OMAP3430
76 bool "OMAP3430 support" 74 bool "OMAP3430 support"
77 depends on ARCH_OMAP3 75 depends on ARCH_OMAP3
78 default y 76 default y
79 select ARCH_OMAP_OTG
80 77
81config SOC_TI81XX 78config SOC_TI81XX
82 bool "TI81XX support" 79 bool "TI81XX support"
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index fa742f3c262..54ad3a4b612 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -90,6 +90,7 @@ obj-$(CONFIG_ARCH_OMAP3) += vc3xxx_data.o vp3xxx_data.o
90obj-$(CONFIG_ARCH_OMAP4) += prcm.o cminst44xx.o cm44xx.o 90obj-$(CONFIG_ARCH_OMAP4) += prcm.o cminst44xx.o cm44xx.o
91obj-$(CONFIG_ARCH_OMAP4) += prcm_mpu44xx.o prminst44xx.o 91obj-$(CONFIG_ARCH_OMAP4) += prcm_mpu44xx.o prminst44xx.o
92obj-$(CONFIG_ARCH_OMAP4) += vc44xx_data.o vp44xx_data.o prm44xx.o 92obj-$(CONFIG_ARCH_OMAP4) += vc44xx_data.o vp44xx_data.o prm44xx.o
93obj-$(CONFIG_SOC_AM33XX) += prcm.o prm33xx.o cm33xx.o
93 94
94# OMAP voltage domains 95# OMAP voltage domains
95voltagedomain-common := voltage.o vc.o vp.o 96voltagedomain-common := voltage.o vc.o vp.o
@@ -99,6 +100,7 @@ obj-$(CONFIG_ARCH_OMAP3) += $(voltagedomain-common)
99obj-$(CONFIG_ARCH_OMAP3) += voltagedomains3xxx_data.o 100obj-$(CONFIG_ARCH_OMAP3) += voltagedomains3xxx_data.o
100obj-$(CONFIG_ARCH_OMAP4) += $(voltagedomain-common) 101obj-$(CONFIG_ARCH_OMAP4) += $(voltagedomain-common)
101obj-$(CONFIG_ARCH_OMAP4) += voltagedomains44xx_data.o 102obj-$(CONFIG_ARCH_OMAP4) += voltagedomains44xx_data.o
103obj-$(CONFIG_SOC_AM33XX) += voltagedomains33xx_data.o
102 104
103# OMAP powerdomain framework 105# OMAP powerdomain framework
104powerdomain-common += powerdomain.o powerdomain-common.o 106powerdomain-common += powerdomain.o powerdomain-common.o
@@ -113,10 +115,11 @@ obj-$(CONFIG_ARCH_OMAP3) += powerdomains2xxx_3xxx_data.o
113obj-$(CONFIG_ARCH_OMAP4) += $(powerdomain-common) 115obj-$(CONFIG_ARCH_OMAP4) += $(powerdomain-common)
114obj-$(CONFIG_ARCH_OMAP4) += powerdomain44xx.o 116obj-$(CONFIG_ARCH_OMAP4) += powerdomain44xx.o
115obj-$(CONFIG_ARCH_OMAP4) += powerdomains44xx_data.o 117obj-$(CONFIG_ARCH_OMAP4) += powerdomains44xx_data.o
118obj-$(CONFIG_SOC_AM33XX) += powerdomain33xx.o
119obj-$(CONFIG_SOC_AM33XX) += powerdomains33xx_data.o
116 120
117# PRCM clockdomain control 121# PRCM clockdomain control
118clockdomain-common += clockdomain.o 122clockdomain-common += clockdomain.o
119clockdomain-common += clockdomains_common_data.o
120obj-$(CONFIG_ARCH_OMAP2) += $(clockdomain-common) 123obj-$(CONFIG_ARCH_OMAP2) += $(clockdomain-common)
121obj-$(CONFIG_ARCH_OMAP2) += clockdomain2xxx_3xxx.o 124obj-$(CONFIG_ARCH_OMAP2) += clockdomain2xxx_3xxx.o
122obj-$(CONFIG_ARCH_OMAP2) += clockdomains2xxx_3xxx_data.o 125obj-$(CONFIG_ARCH_OMAP2) += clockdomains2xxx_3xxx_data.o
@@ -129,6 +132,8 @@ obj-$(CONFIG_ARCH_OMAP3) += clockdomains3xxx_data.o
129obj-$(CONFIG_ARCH_OMAP4) += $(clockdomain-common) 132obj-$(CONFIG_ARCH_OMAP4) += $(clockdomain-common)
130obj-$(CONFIG_ARCH_OMAP4) += clockdomain44xx.o 133obj-$(CONFIG_ARCH_OMAP4) += clockdomain44xx.o
131obj-$(CONFIG_ARCH_OMAP4) += clockdomains44xx_data.o 134obj-$(CONFIG_ARCH_OMAP4) += clockdomains44xx_data.o
135obj-$(CONFIG_SOC_AM33XX) += clockdomain33xx.o
136obj-$(CONFIG_SOC_AM33XX) += clockdomains33xx_data.o
132 137
133# Clock framework 138# Clock framework
134obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o 139obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o
@@ -244,9 +249,6 @@ obj-y += $(omap-flash-y) $(omap-flash-m)
244omap-hsmmc-$(CONFIG_MMC_OMAP_HS) := hsmmc.o 249omap-hsmmc-$(CONFIG_MMC_OMAP_HS) := hsmmc.o
245obj-y += $(omap-hsmmc-m) $(omap-hsmmc-y) 250obj-y += $(omap-hsmmc-m) $(omap-hsmmc-y)
246 251
247
248usbfs-$(CONFIG_ARCH_OMAP_OTG) := usb-fs.o
249obj-y += $(usbfs-m) $(usbfs-y)
250obj-y += usb-musb.o 252obj-y += usb-musb.o
251obj-y += omap_phy_internal.o 253obj-y += omap_phy_internal.o
252 254
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index 99ca6bad5c3..6523aeabf9f 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -254,16 +254,6 @@ static struct omap2_hsmmc_info mmc[] __initdata = {
254 {} /* Terminator */ 254 {} /* Terminator */
255}; 255};
256 256
257static struct omap_usb_config sdp2430_usb_config __initdata = {
258 .otg = 1,
259#ifdef CONFIG_USB_GADGET_OMAP
260 .hmc_mode = 0x0,
261#elif defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
262 .hmc_mode = 0x1,
263#endif
264 .pins[0] = 3,
265};
266
267#ifdef CONFIG_OMAP_MUX 257#ifdef CONFIG_OMAP_MUX
268static struct omap_board_mux board_mux[] __initdata = { 258static struct omap_board_mux board_mux[] __initdata = {
269 { .reg_offset = OMAP_MUX_TERMINATOR }, 259 { .reg_offset = OMAP_MUX_TERMINATOR },
@@ -280,7 +270,6 @@ static void __init omap_2430sdp_init(void)
280 omap_serial_init(); 270 omap_serial_init();
281 omap_sdrc_init(NULL, NULL); 271 omap_sdrc_init(NULL, NULL);
282 omap_hsmmc_init(mmc); 272 omap_hsmmc_init(mmc);
283 omap2_usbfs_init(&sdp2430_usb_config);
284 273
285 omap_mux_init_signal("usb0hs_stp", OMAP_PULL_ENA | OMAP_PULL_UP); 274 omap_mux_init_signal("usb0hs_stp", OMAP_PULL_ENA | OMAP_PULL_UP);
286 usb_musb_init(NULL); 275 usb_musb_init(NULL);
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index 502c31e123b..519bcd3079e 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -35,7 +35,6 @@
35#include <asm/mach/flash.h> 35#include <asm/mach/flash.h>
36 36
37#include <plat/led.h> 37#include <plat/led.h>
38#include <plat/usb.h>
39#include <plat/board.h> 38#include <plat/board.h>
40#include "common.h" 39#include "common.h"
41#include <plat/gpmc.h> 40#include <plat/gpmc.h>
@@ -253,13 +252,6 @@ out:
253 clk_put(gpmc_fck); 252 clk_put(gpmc_fck);
254} 253}
255 254
256static struct omap_usb_config apollon_usb_config __initdata = {
257 .register_dev = 1,
258 .hmc_mode = 0x14, /* 0:dev 1:host1 2:disable */
259
260 .pins[0] = 6,
261};
262
263static struct panel_generic_dpi_data apollon_panel_data = { 255static struct panel_generic_dpi_data apollon_panel_data = {
264 .name = "apollon", 256 .name = "apollon",
265}; 257};
@@ -297,15 +289,6 @@ static void __init apollon_led_init(void)
297 gpio_request_array(apollon_gpio_leds, ARRAY_SIZE(apollon_gpio_leds)); 289 gpio_request_array(apollon_gpio_leds, ARRAY_SIZE(apollon_gpio_leds));
298} 290}
299 291
300static void __init apollon_usb_init(void)
301{
302 /* USB device */
303 /* DEVICE_SUSPEND */
304 omap_mux_init_signal("mcbsp2_clkx.gpio_12", 0);
305 gpio_request_one(12, GPIOF_OUT_INIT_LOW, "USB suspend");
306 omap2_usbfs_init(&apollon_usb_config);
307}
308
309#ifdef CONFIG_OMAP_MUX 292#ifdef CONFIG_OMAP_MUX
310static struct omap_board_mux board_mux[] __initdata = { 293static struct omap_board_mux board_mux[] __initdata = {
311 { .reg_offset = OMAP_MUX_TERMINATOR }, 294 { .reg_offset = OMAP_MUX_TERMINATOR },
@@ -321,7 +304,6 @@ static void __init omap_apollon_init(void)
321 apollon_init_smc91x(); 304 apollon_init_smc91x();
322 apollon_led_init(); 305 apollon_led_init();
323 apollon_flash_init(); 306 apollon_flash_init();
324 apollon_usb_init();
325 307
326 /* REVISIT: where's the correct place */ 308 /* REVISIT: where's the correct place */
327 omap_mux_init_signal("sys_nirq", OMAP_PULL_ENA | OMAP_PULL_UP); 309 omap_mux_init_signal("sys_nirq", OMAP_PULL_ENA | OMAP_PULL_UP);
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 20293465786..2f2abfb82d8 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -112,6 +112,24 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)")
112MACHINE_END 112MACHINE_END
113#endif 113#endif
114 114
115#ifdef CONFIG_SOC_AM33XX
116static const char *am33xx_boards_compat[] __initdata = {
117 "ti,am33xx",
118 NULL,
119};
120
121DT_MACHINE_START(AM33XX_DT, "Generic AM33XX (Flattened Device Tree)")
122 .reserve = omap_reserve,
123 .map_io = am33xx_map_io,
124 .init_early = am33xx_init_early,
125 .init_irq = omap_init_irq,
126 .handle_irq = omap3_intc_handle_irq,
127 .init_machine = omap_generic_init,
128 .timer = &omap3_am33xx_timer,
129 .dt_compat = am33xx_boards_compat,
130MACHINE_END
131#endif
132
115#ifdef CONFIG_ARCH_OMAP4 133#ifdef CONFIG_ARCH_OMAP4
116static const char *omap4_boards_compat[] __initdata = { 134static const char *omap4_boards_compat[] __initdata = {
117 "ti,omap4", 135 "ti,omap4",
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index 876becf8205..ace20482e3e 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -32,7 +32,6 @@
32#include <asm/mach/arch.h> 32#include <asm/mach/arch.h>
33#include <asm/mach/map.h> 33#include <asm/mach/map.h>
34 34
35#include <plat/usb.h>
36#include <plat/board.h> 35#include <plat/board.h>
37#include "common.h" 36#include "common.h"
38#include <plat/menelaus.h> 37#include <plat/menelaus.h>
@@ -329,17 +328,6 @@ static void __init h4_init_flash(void)
329 h4_flash_resource.end = base + SZ_64M - 1; 328 h4_flash_resource.end = base + SZ_64M - 1;
330} 329}
331 330
332static struct omap_usb_config h4_usb_config __initdata = {
333 /* S1.10 OFF -- usb "download port"
334 * usb0 switched to Mini-B port and isp1105 transceiver;
335 * S2.POS3 = ON, S2.POS4 = OFF ... to enable battery charging
336 */
337 .register_dev = 1,
338 .pins[0] = 3,
339/* .hmc_mode = 0x14,*/ /* 0:dev 1:host 2:disable */
340 .hmc_mode = 0x00, /* 0:dev|otg 1:disable 2:disable */
341};
342
343static struct at24_platform_data m24c01 = { 331static struct at24_platform_data m24c01 = {
344 .byte_len = SZ_1K / 8, 332 .byte_len = SZ_1K / 8,
345 .page_size = 16, 333 .page_size = 16,
@@ -381,7 +369,6 @@ static void __init omap_h4_init(void)
381 ARRAY_SIZE(h4_i2c_board_info)); 369 ARRAY_SIZE(h4_i2c_board_info));
382 370
383 platform_add_devices(h4_devices, ARRAY_SIZE(h4_devices)); 371 platform_add_devices(h4_devices, ARRAY_SIZE(h4_devices));
384 omap2_usbfs_init(&h4_usb_config);
385 omap_serial_init(); 372 omap_serial_init();
386 omap_sdrc_init(NULL, NULL); 373 omap_sdrc_init(NULL, NULL);
387 h4_init_flash(); 374 h4_init_flash();
diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c
index bace9308a4d..002745181ad 100644
--- a/arch/arm/mach-omap2/clock2420_data.c
+++ b/arch/arm/mach-omap2/clock2420_data.c
@@ -1774,8 +1774,6 @@ static struct omap_clk omap2420_clks[] = {
1774 CLK(NULL, "osc_ck", &osc_ck, CK_242X), 1774 CLK(NULL, "osc_ck", &osc_ck, CK_242X),
1775 CLK(NULL, "sys_ck", &sys_ck, CK_242X), 1775 CLK(NULL, "sys_ck", &sys_ck, CK_242X),
1776 CLK(NULL, "alt_ck", &alt_ck, CK_242X), 1776 CLK(NULL, "alt_ck", &alt_ck, CK_242X),
1777 CLK("omap-mcbsp.1", "pad_fck", &mcbsp_clks, CK_242X),
1778 CLK("omap-mcbsp.2", "pad_fck", &mcbsp_clks, CK_242X),
1779 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_242X), 1777 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_242X),
1780 /* internal analog sources */ 1778 /* internal analog sources */
1781 CLK(NULL, "dpll_ck", &dpll_ck, CK_242X), 1779 CLK(NULL, "dpll_ck", &dpll_ck, CK_242X),
@@ -1784,8 +1782,6 @@ static struct omap_clk omap2420_clks[] = {
1784 /* internal prcm root sources */ 1782 /* internal prcm root sources */
1785 CLK(NULL, "func_54m_ck", &func_54m_ck, CK_242X), 1783 CLK(NULL, "func_54m_ck", &func_54m_ck, CK_242X),
1786 CLK(NULL, "core_ck", &core_ck, CK_242X), 1784 CLK(NULL, "core_ck", &core_ck, CK_242X),
1787 CLK("omap-mcbsp.1", "prcm_fck", &func_96m_ck, CK_242X),
1788 CLK("omap-mcbsp.2", "prcm_fck", &func_96m_ck, CK_242X),
1789 CLK(NULL, "func_96m_ck", &func_96m_ck, CK_242X), 1785 CLK(NULL, "func_96m_ck", &func_96m_ck, CK_242X),
1790 CLK(NULL, "func_48m_ck", &func_48m_ck, CK_242X), 1786 CLK(NULL, "func_48m_ck", &func_48m_ck, CK_242X),
1791 CLK(NULL, "func_12m_ck", &func_12m_ck, CK_242X), 1787 CLK(NULL, "func_12m_ck", &func_12m_ck, CK_242X),
@@ -1901,42 +1897,9 @@ static struct omap_clk omap2420_clks[] = {
1901 CLK(NULL, "pka_ick", &pka_ick, CK_242X), 1897 CLK(NULL, "pka_ick", &pka_ick, CK_242X),
1902 CLK(NULL, "usb_fck", &usb_fck, CK_242X), 1898 CLK(NULL, "usb_fck", &usb_fck, CK_242X),
1903 CLK("musb-hdrc", "fck", &osc_ck, CK_242X), 1899 CLK("musb-hdrc", "fck", &osc_ck, CK_242X),
1904 CLK("omap_timer.1", "32k_ck", &func_32k_ck, CK_243X), 1900 CLK(NULL, "timer_32k_ck", &func_32k_ck, CK_243X),
1905 CLK("omap_timer.2", "32k_ck", &func_32k_ck, CK_243X), 1901 CLK(NULL, "timer_sys_ck", &sys_ck, CK_243X),
1906 CLK("omap_timer.3", "32k_ck", &func_32k_ck, CK_243X), 1902 CLK(NULL, "timer_ext_ck", &alt_ck, CK_243X),
1907 CLK("omap_timer.4", "32k_ck", &func_32k_ck, CK_243X),
1908 CLK("omap_timer.5", "32k_ck", &func_32k_ck, CK_243X),
1909 CLK("omap_timer.6", "32k_ck", &func_32k_ck, CK_243X),
1910 CLK("omap_timer.7", "32k_ck", &func_32k_ck, CK_243X),
1911 CLK("omap_timer.8", "32k_ck", &func_32k_ck, CK_243X),
1912 CLK("omap_timer.9", "32k_ck", &func_32k_ck, CK_243X),
1913 CLK("omap_timer.10", "32k_ck", &func_32k_ck, CK_243X),
1914 CLK("omap_timer.11", "32k_ck", &func_32k_ck, CK_243X),
1915 CLK("omap_timer.12", "32k_ck", &func_32k_ck, CK_243X),
1916 CLK("omap_timer.1", "sys_ck", &sys_ck, CK_243X),
1917 CLK("omap_timer.2", "sys_ck", &sys_ck, CK_243X),
1918 CLK("omap_timer.3", "sys_ck", &sys_ck, CK_243X),
1919 CLK("omap_timer.4", "sys_ck", &sys_ck, CK_243X),
1920 CLK("omap_timer.5", "sys_ck", &sys_ck, CK_243X),
1921 CLK("omap_timer.6", "sys_ck", &sys_ck, CK_243X),
1922 CLK("omap_timer.7", "sys_ck", &sys_ck, CK_243X),
1923 CLK("omap_timer.8", "sys_ck", &sys_ck, CK_243X),
1924 CLK("omap_timer.9", "sys_ck", &sys_ck, CK_243X),
1925 CLK("omap_timer.10", "sys_ck", &sys_ck, CK_243X),
1926 CLK("omap_timer.11", "sys_ck", &sys_ck, CK_243X),
1927 CLK("omap_timer.12", "sys_ck", &sys_ck, CK_243X),
1928 CLK("omap_timer.1", "alt_ck", &alt_ck, CK_243X),
1929 CLK("omap_timer.2", "alt_ck", &alt_ck, CK_243X),
1930 CLK("omap_timer.3", "alt_ck", &alt_ck, CK_243X),
1931 CLK("omap_timer.4", "alt_ck", &alt_ck, CK_243X),
1932 CLK("omap_timer.5", "alt_ck", &alt_ck, CK_243X),
1933 CLK("omap_timer.6", "alt_ck", &alt_ck, CK_243X),
1934 CLK("omap_timer.7", "alt_ck", &alt_ck, CK_243X),
1935 CLK("omap_timer.8", "alt_ck", &alt_ck, CK_243X),
1936 CLK("omap_timer.9", "alt_ck", &alt_ck, CK_243X),
1937 CLK("omap_timer.10", "alt_ck", &alt_ck, CK_243X),
1938 CLK("omap_timer.11", "alt_ck", &alt_ck, CK_243X),
1939 CLK("omap_timer.12", "alt_ck", &alt_ck, CK_243X),
1940}; 1903};
1941 1904
1942/* 1905/*
diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
index 3b4d09a5039..cacabb070e2 100644
--- a/arch/arm/mach-omap2/clock2430_data.c
+++ b/arch/arm/mach-omap2/clock2430_data.c
@@ -1858,11 +1858,6 @@ static struct omap_clk omap2430_clks[] = {
1858 CLK(NULL, "osc_ck", &osc_ck, CK_243X), 1858 CLK(NULL, "osc_ck", &osc_ck, CK_243X),
1859 CLK(NULL, "sys_ck", &sys_ck, CK_243X), 1859 CLK(NULL, "sys_ck", &sys_ck, CK_243X),
1860 CLK(NULL, "alt_ck", &alt_ck, CK_243X), 1860 CLK(NULL, "alt_ck", &alt_ck, CK_243X),
1861 CLK("omap-mcbsp.1", "pad_fck", &mcbsp_clks, CK_243X),
1862 CLK("omap-mcbsp.2", "pad_fck", &mcbsp_clks, CK_243X),
1863 CLK("omap-mcbsp.3", "pad_fck", &mcbsp_clks, CK_243X),
1864 CLK("omap-mcbsp.4", "pad_fck", &mcbsp_clks, CK_243X),
1865 CLK("omap-mcbsp.5", "pad_fck", &mcbsp_clks, CK_243X),
1866 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_243X), 1861 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_243X),
1867 /* internal analog sources */ 1862 /* internal analog sources */
1868 CLK(NULL, "dpll_ck", &dpll_ck, CK_243X), 1863 CLK(NULL, "dpll_ck", &dpll_ck, CK_243X),
@@ -1871,11 +1866,6 @@ static struct omap_clk omap2430_clks[] = {
1871 /* internal prcm root sources */ 1866 /* internal prcm root sources */
1872 CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X), 1867 CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X),
1873 CLK(NULL, "core_ck", &core_ck, CK_243X), 1868 CLK(NULL, "core_ck", &core_ck, CK_243X),
1874 CLK("omap-mcbsp.1", "prcm_fck", &func_96m_ck, CK_243X),
1875 CLK("omap-mcbsp.2", "prcm_fck", &func_96m_ck, CK_243X),
1876 CLK("omap-mcbsp.3", "prcm_fck", &func_96m_ck, CK_243X),
1877 CLK("omap-mcbsp.4", "prcm_fck", &func_96m_ck, CK_243X),
1878 CLK("omap-mcbsp.5", "prcm_fck", &func_96m_ck, CK_243X),
1879 CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X), 1869 CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X),
1880 CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X), 1870 CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X),
1881 CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X), 1871 CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X),
@@ -2000,42 +1990,9 @@ static struct omap_clk omap2430_clks[] = {
2000 CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X), 1990 CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X),
2001 CLK("omap_hsmmc.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X), 1991 CLK("omap_hsmmc.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X),
2002 CLK("omap_hsmmc.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X), 1992 CLK("omap_hsmmc.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X),
2003 CLK("omap_timer.1", "32k_ck", &func_32k_ck, CK_243X), 1993 CLK(NULL, "timer_32k_ck", &func_32k_ck, CK_243X),
2004 CLK("omap_timer.2", "32k_ck", &func_32k_ck, CK_243X), 1994 CLK(NULL, "timer_sys_ck", &sys_ck, CK_243X),
2005 CLK("omap_timer.3", "32k_ck", &func_32k_ck, CK_243X), 1995 CLK(NULL, "timer_ext_ck", &alt_ck, CK_243X),
2006 CLK("omap_timer.4", "32k_ck", &func_32k_ck, CK_243X),
2007 CLK("omap_timer.5", "32k_ck", &func_32k_ck, CK_243X),
2008 CLK("omap_timer.6", "32k_ck", &func_32k_ck, CK_243X),
2009 CLK("omap_timer.7", "32k_ck", &func_32k_ck, CK_243X),
2010 CLK("omap_timer.8", "32k_ck", &func_32k_ck, CK_243X),
2011 CLK("omap_timer.9", "32k_ck", &func_32k_ck, CK_243X),
2012 CLK("omap_timer.10", "32k_ck", &func_32k_ck, CK_243X),
2013 CLK("omap_timer.11", "32k_ck", &func_32k_ck, CK_243X),
2014 CLK("omap_timer.12", "32k_ck", &func_32k_ck, CK_243X),
2015 CLK("omap_timer.1", "sys_ck", &sys_ck, CK_243X),
2016 CLK("omap_timer.2", "sys_ck", &sys_ck, CK_243X),
2017 CLK("omap_timer.3", "sys_ck", &sys_ck, CK_243X),
2018 CLK("omap_timer.4", "sys_ck", &sys_ck, CK_243X),
2019 CLK("omap_timer.5", "sys_ck", &sys_ck, CK_243X),
2020 CLK("omap_timer.6", "sys_ck", &sys_ck, CK_243X),
2021 CLK("omap_timer.7", "sys_ck", &sys_ck, CK_243X),
2022 CLK("omap_timer.8", "sys_ck", &sys_ck, CK_243X),
2023 CLK("omap_timer.9", "sys_ck", &sys_ck, CK_243X),
2024 CLK("omap_timer.10", "sys_ck", &sys_ck, CK_243X),
2025 CLK("omap_timer.11", "sys_ck", &sys_ck, CK_243X),
2026 CLK("omap_timer.12", "sys_ck", &sys_ck, CK_243X),
2027 CLK("omap_timer.1", "alt_ck", &alt_ck, CK_243X),
2028 CLK("omap_timer.2", "alt_ck", &alt_ck, CK_243X),
2029 CLK("omap_timer.3", "alt_ck", &alt_ck, CK_243X),
2030 CLK("omap_timer.4", "alt_ck", &alt_ck, CK_243X),
2031 CLK("omap_timer.5", "alt_ck", &alt_ck, CK_243X),
2032 CLK("omap_timer.6", "alt_ck", &alt_ck, CK_243X),
2033 CLK("omap_timer.7", "alt_ck", &alt_ck, CK_243X),
2034 CLK("omap_timer.8", "alt_ck", &alt_ck, CK_243X),
2035 CLK("omap_timer.9", "alt_ck", &alt_ck, CK_243X),
2036 CLK("omap_timer.10", "alt_ck", &alt_ck, CK_243X),
2037 CLK("omap_timer.11", "alt_ck", &alt_ck, CK_243X),
2038 CLK("omap_timer.12", "alt_ck", &alt_ck, CK_243X),
2039}; 1996};
2040 1997
2041/* 1998/*
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index 1efdec236ae..71a1d338380 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -3236,11 +3236,6 @@ static struct omap_clk omap3xxx_clks[] = {
3236 CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_3XXX), 3236 CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_3XXX),
3237 CLK(NULL, "sys_ck", &sys_ck, CK_3XXX), 3237 CLK(NULL, "sys_ck", &sys_ck, CK_3XXX),
3238 CLK(NULL, "sys_altclk", &sys_altclk, CK_3XXX), 3238 CLK(NULL, "sys_altclk", &sys_altclk, CK_3XXX),
3239 CLK("omap-mcbsp.1", "pad_fck", &mcbsp_clks, CK_3XXX),
3240 CLK("omap-mcbsp.2", "pad_fck", &mcbsp_clks, CK_3XXX),
3241 CLK("omap-mcbsp.3", "pad_fck", &mcbsp_clks, CK_3XXX),
3242 CLK("omap-mcbsp.4", "pad_fck", &mcbsp_clks, CK_3XXX),
3243 CLK("omap-mcbsp.5", "pad_fck", &mcbsp_clks, CK_3XXX),
3244 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_3XXX), 3239 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_3XXX),
3245 CLK(NULL, "sys_clkout1", &sys_clkout1, CK_3XXX), 3240 CLK(NULL, "sys_clkout1", &sys_clkout1, CK_3XXX),
3246 CLK(NULL, "dpll1_ck", &dpll1_ck, CK_3XXX), 3241 CLK(NULL, "dpll1_ck", &dpll1_ck, CK_3XXX),
@@ -3307,8 +3302,6 @@ static struct omap_clk omap3xxx_clks[] = {
3307 CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3302 CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3308 CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3303 CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3309 CLK("usbhs_omap", "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3304 CLK("usbhs_omap", "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3310 CLK("omap-mcbsp.1", "prcm_fck", &core_96m_fck, CK_3XXX),
3311 CLK("omap-mcbsp.5", "prcm_fck", &core_96m_fck, CK_3XXX),
3312 CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX), 3305 CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX),
3313 CLK(NULL, "mmchs3_fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3306 CLK(NULL, "mmchs3_fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3314 CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_3XXX), 3307 CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_3XXX),
@@ -3413,9 +3406,6 @@ static struct omap_clk omap3xxx_clks[] = {
3413 CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX), 3406 CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX),
3414 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_3XXX), 3407 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_3XXX),
3415 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_3XXX), 3408 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_3XXX),
3416 CLK("omap-mcbsp.2", "prcm_fck", &per_96m_fck, CK_3XXX),
3417 CLK("omap-mcbsp.3", "prcm_fck", &per_96m_fck, CK_3XXX),
3418 CLK("omap-mcbsp.4", "prcm_fck", &per_96m_fck, CK_3XXX),
3419 CLK(NULL, "per_96m_fck", &per_96m_fck, CK_3XXX), 3409 CLK(NULL, "per_96m_fck", &per_96m_fck, CK_3XXX),
3420 CLK(NULL, "per_48m_fck", &per_48m_fck, CK_3XXX), 3410 CLK(NULL, "per_48m_fck", &per_48m_fck, CK_3XXX),
3421 CLK(NULL, "uart3_fck", &uart3_fck, CK_3XXX), 3411 CLK(NULL, "uart3_fck", &uart3_fck, CK_3XXX),
@@ -3482,30 +3472,8 @@ static struct omap_clk omap3xxx_clks[] = {
3482 CLK("musb-am35x", "fck", &hsotgusb_fck_am35xx, CK_AM35XX), 3472 CLK("musb-am35x", "fck", &hsotgusb_fck_am35xx, CK_AM35XX),
3483 CLK(NULL, "hecc_ck", &hecc_ck, CK_AM35XX), 3473 CLK(NULL, "hecc_ck", &hecc_ck, CK_AM35XX),
3484 CLK(NULL, "uart4_ick", &uart4_ick_am35xx, CK_AM35XX), 3474 CLK(NULL, "uart4_ick", &uart4_ick_am35xx, CK_AM35XX),
3485 CLK("omap_timer.1", "32k_ck", &omap_32k_fck, CK_3XXX), 3475 CLK(NULL, "timer_32k_ck", &omap_32k_fck, CK_3XXX),
3486 CLK("omap_timer.2", "32k_ck", &omap_32k_fck, CK_3XXX), 3476 CLK(NULL, "timer_sys_ck", &sys_ck, CK_3XXX),
3487 CLK("omap_timer.3", "32k_ck", &omap_32k_fck, CK_3XXX),
3488 CLK("omap_timer.4", "32k_ck", &omap_32k_fck, CK_3XXX),
3489 CLK("omap_timer.5", "32k_ck", &omap_32k_fck, CK_3XXX),
3490 CLK("omap_timer.6", "32k_ck", &omap_32k_fck, CK_3XXX),
3491 CLK("omap_timer.7", "32k_ck", &omap_32k_fck, CK_3XXX),
3492 CLK("omap_timer.8", "32k_ck", &omap_32k_fck, CK_3XXX),
3493 CLK("omap_timer.9", "32k_ck", &omap_32k_fck, CK_3XXX),
3494 CLK("omap_timer.10", "32k_ck", &omap_32k_fck, CK_3XXX),
3495 CLK("omap_timer.11", "32k_ck", &omap_32k_fck, CK_3XXX),
3496 CLK("omap_timer.12", "32k_ck", &omap_32k_fck, CK_3XXX),
3497 CLK("omap_timer.1", "sys_ck", &sys_ck, CK_3XXX),
3498 CLK("omap_timer.2", "sys_ck", &sys_ck, CK_3XXX),
3499 CLK("omap_timer.3", "sys_ck", &sys_ck, CK_3XXX),
3500 CLK("omap_timer.4", "sys_ck", &sys_ck, CK_3XXX),
3501 CLK("omap_timer.5", "sys_ck", &sys_ck, CK_3XXX),
3502 CLK("omap_timer.6", "sys_ck", &sys_ck, CK_3XXX),
3503 CLK("omap_timer.7", "sys_ck", &sys_ck, CK_3XXX),
3504 CLK("omap_timer.8", "sys_ck", &sys_ck, CK_3XXX),
3505 CLK("omap_timer.9", "sys_ck", &sys_ck, CK_3XXX),
3506 CLK("omap_timer.10", "sys_ck", &sys_ck, CK_3XXX),
3507 CLK("omap_timer.11", "sys_ck", &sys_ck, CK_3XXX),
3508 CLK("omap_timer.12", "sys_ck", &sys_ck, CK_3XXX),
3509}; 3477};
3510 3478
3511 3479
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index ba6f9a0a43e..de53b7014b8 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -3385,28 +3385,18 @@ static struct omap_clk omap44xx_clks[] = {
3385 CLK("usbhs_omap", "usbhost_ick", &dummy_ck, CK_443X), 3385 CLK("usbhs_omap", "usbhost_ick", &dummy_ck, CK_443X),
3386 CLK("usbhs_omap", "usbtll_fck", &dummy_ck, CK_443X), 3386 CLK("usbhs_omap", "usbtll_fck", &dummy_ck, CK_443X),
3387 CLK("omap_wdt", "ick", &dummy_ck, CK_443X), 3387 CLK("omap_wdt", "ick", &dummy_ck, CK_443X),
3388 CLK("omap_timer.1", "32k_ck", &sys_32k_ck, CK_443X), 3388 CLK(NULL, "timer_32k_ck", &sys_32k_ck, CK_443X),
3389 CLK("omap_timer.2", "32k_ck", &sys_32k_ck, CK_443X), 3389 CLK("omap_timer.1", "timer_sys_ck", &sys_clkin_ck, CK_443X),
3390 CLK("omap_timer.3", "32k_ck", &sys_32k_ck, CK_443X), 3390 CLK("omap_timer.2", "timer_sys_ck", &sys_clkin_ck, CK_443X),
3391 CLK("omap_timer.4", "32k_ck", &sys_32k_ck, CK_443X), 3391 CLK("omap_timer.3", "timer_sys_ck", &sys_clkin_ck, CK_443X),
3392 CLK("omap_timer.5", "32k_ck", &sys_32k_ck, CK_443X), 3392 CLK("omap_timer.4", "timer_sys_ck", &sys_clkin_ck, CK_443X),
3393 CLK("omap_timer.6", "32k_ck", &sys_32k_ck, CK_443X), 3393 CLK("omap_timer.9", "timer_sys_ck", &sys_clkin_ck, CK_443X),
3394 CLK("omap_timer.7", "32k_ck", &sys_32k_ck, CK_443X), 3394 CLK("omap_timer.10", "timer_sys_ck", &sys_clkin_ck, CK_443X),
3395 CLK("omap_timer.8", "32k_ck", &sys_32k_ck, CK_443X), 3395 CLK("omap_timer.11", "timer_sys_ck", &sys_clkin_ck, CK_443X),
3396 CLK("omap_timer.9", "32k_ck", &sys_32k_ck, CK_443X), 3396 CLK("omap_timer.5", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
3397 CLK("omap_timer.10", "32k_ck", &sys_32k_ck, CK_443X), 3397 CLK("omap_timer.6", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
3398 CLK("omap_timer.11", "32k_ck", &sys_32k_ck, CK_443X), 3398 CLK("omap_timer.7", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
3399 CLK("omap_timer.1", "sys_ck", &sys_clkin_ck, CK_443X), 3399 CLK("omap_timer.8", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
3400 CLK("omap_timer.2", "sys_ck", &sys_clkin_ck, CK_443X),
3401 CLK("omap_timer.3", "sys_ck", &sys_clkin_ck, CK_443X),
3402 CLK("omap_timer.4", "sys_ck", &sys_clkin_ck, CK_443X),
3403 CLK("omap_timer.9", "sys_ck", &sys_clkin_ck, CK_443X),
3404 CLK("omap_timer.10", "sys_ck", &sys_clkin_ck, CK_443X),
3405 CLK("omap_timer.11", "sys_ck", &sys_clkin_ck, CK_443X),
3406 CLK("omap_timer.5", "sys_ck", &syc_clk_div_ck, CK_443X),
3407 CLK("omap_timer.6", "sys_ck", &syc_clk_div_ck, CK_443X),
3408 CLK("omap_timer.7", "sys_ck", &syc_clk_div_ck, CK_443X),
3409 CLK("omap_timer.8", "sys_ck", &syc_clk_div_ck, CK_443X),
3410}; 3400};
3411 3401
3412int __init omap4xxx_clk_init(void) 3402int __init omap4xxx_clk_init(void)
diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
index f7b58609bad..0a8c7b67858 100644
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -195,6 +195,7 @@ int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh);
195extern void __init omap242x_clockdomains_init(void); 195extern void __init omap242x_clockdomains_init(void);
196extern void __init omap243x_clockdomains_init(void); 196extern void __init omap243x_clockdomains_init(void);
197extern void __init omap3xxx_clockdomains_init(void); 197extern void __init omap3xxx_clockdomains_init(void);
198extern void __init am33xx_clockdomains_init(void);
198extern void __init omap44xx_clockdomains_init(void); 199extern void __init omap44xx_clockdomains_init(void);
199extern void _clkdm_add_autodeps(struct clockdomain *clkdm); 200extern void _clkdm_add_autodeps(struct clockdomain *clkdm);
200extern void _clkdm_del_autodeps(struct clockdomain *clkdm); 201extern void _clkdm_del_autodeps(struct clockdomain *clkdm);
@@ -202,11 +203,10 @@ extern void _clkdm_del_autodeps(struct clockdomain *clkdm);
202extern struct clkdm_ops omap2_clkdm_operations; 203extern struct clkdm_ops omap2_clkdm_operations;
203extern struct clkdm_ops omap3_clkdm_operations; 204extern struct clkdm_ops omap3_clkdm_operations;
204extern struct clkdm_ops omap4_clkdm_operations; 205extern struct clkdm_ops omap4_clkdm_operations;
206extern struct clkdm_ops am33xx_clkdm_operations;
205 207
206extern struct clkdm_dep gfx_24xx_wkdeps[]; 208extern struct clkdm_dep gfx_24xx_wkdeps[];
207extern struct clkdm_dep dsp_24xx_wkdeps[]; 209extern struct clkdm_dep dsp_24xx_wkdeps[];
208extern struct clockdomain wkup_common_clkdm; 210extern struct clockdomain wkup_common_clkdm;
209extern struct clockdomain prm_common_clkdm;
210extern struct clockdomain cm_common_clkdm;
211 211
212#endif 212#endif
diff --git a/arch/arm/mach-omap2/clockdomain33xx.c b/arch/arm/mach-omap2/clockdomain33xx.c
new file mode 100644
index 00000000000..aca6388fad7
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomain33xx.c
@@ -0,0 +1,74 @@
1/*
2 * AM33XX clockdomain control
3 *
4 * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
5 * Vaibhav Hiremath <hvaibhav@ti.com>
6 *
7 * Derived from mach-omap2/clockdomain44xx.c written by Rajendra Nayak
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation version 2.
12 *
13 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
14 * kind, whether express or implied; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/kernel.h>
20
21#include "clockdomain.h"
22#include "cm33xx.h"
23
24
25static int am33xx_clkdm_sleep(struct clockdomain *clkdm)
26{
27 am33xx_cm_clkdm_force_sleep(clkdm->cm_inst, clkdm->clkdm_offs);
28 return 0;
29}
30
31static int am33xx_clkdm_wakeup(struct clockdomain *clkdm)
32{
33 am33xx_cm_clkdm_force_wakeup(clkdm->cm_inst, clkdm->clkdm_offs);
34 return 0;
35}
36
37static void am33xx_clkdm_allow_idle(struct clockdomain *clkdm)
38{
39 am33xx_cm_clkdm_enable_hwsup(clkdm->cm_inst, clkdm->clkdm_offs);
40}
41
42static void am33xx_clkdm_deny_idle(struct clockdomain *clkdm)
43{
44 am33xx_cm_clkdm_disable_hwsup(clkdm->cm_inst, clkdm->clkdm_offs);
45}
46
47static int am33xx_clkdm_clk_enable(struct clockdomain *clkdm)
48{
49 if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
50 return am33xx_clkdm_wakeup(clkdm);
51
52 return 0;
53}
54
55static int am33xx_clkdm_clk_disable(struct clockdomain *clkdm)
56{
57 bool hwsup = false;
58
59 hwsup = am33xx_cm_is_clkdm_in_hwsup(clkdm->cm_inst, clkdm->clkdm_offs);
60
61 if (!hwsup && (clkdm->flags & CLKDM_CAN_FORCE_SLEEP))
62 am33xx_clkdm_sleep(clkdm);
63
64 return 0;
65}
66
67struct clkdm_ops am33xx_clkdm_operations = {
68 .clkdm_sleep = am33xx_clkdm_sleep,
69 .clkdm_wakeup = am33xx_clkdm_wakeup,
70 .clkdm_allow_idle = am33xx_clkdm_allow_idle,
71 .clkdm_deny_idle = am33xx_clkdm_deny_idle,
72 .clkdm_clk_enable = am33xx_clkdm_clk_enable,
73 .clkdm_clk_disable = am33xx_clkdm_clk_disable,
74};
diff --git a/arch/arm/mach-omap2/clockdomains2420_data.c b/arch/arm/mach-omap2/clockdomains2420_data.c
index 0ab8e46d5b2..5c741852fac 100644
--- a/arch/arm/mach-omap2/clockdomains2420_data.c
+++ b/arch/arm/mach-omap2/clockdomains2420_data.c
@@ -131,8 +131,6 @@ static struct clockdomain dss_2420_clkdm = {
131 131
132static struct clockdomain *clockdomains_omap242x[] __initdata = { 132static struct clockdomain *clockdomains_omap242x[] __initdata = {
133 &wkup_common_clkdm, 133 &wkup_common_clkdm,
134 &cm_common_clkdm,
135 &prm_common_clkdm,
136 &mpu_2420_clkdm, 134 &mpu_2420_clkdm,
137 &iva1_2420_clkdm, 135 &iva1_2420_clkdm,
138 &dsp_2420_clkdm, 136 &dsp_2420_clkdm,
diff --git a/arch/arm/mach-omap2/clockdomains2430_data.c b/arch/arm/mach-omap2/clockdomains2430_data.c
index 3645ed04489..f09617555e1 100644
--- a/arch/arm/mach-omap2/clockdomains2430_data.c
+++ b/arch/arm/mach-omap2/clockdomains2430_data.c
@@ -157,8 +157,6 @@ static struct clockdomain dss_2430_clkdm = {
157 157
158static struct clockdomain *clockdomains_omap243x[] __initdata = { 158static struct clockdomain *clockdomains_omap243x[] __initdata = {
159 &wkup_common_clkdm, 159 &wkup_common_clkdm,
160 &cm_common_clkdm,
161 &prm_common_clkdm,
162 &mpu_2430_clkdm, 160 &mpu_2430_clkdm,
163 &mdm_clkdm, 161 &mdm_clkdm,
164 &dsp_2430_clkdm, 162 &dsp_2430_clkdm,
diff --git a/arch/arm/mach-omap2/clockdomains33xx_data.c b/arch/arm/mach-omap2/clockdomains33xx_data.c
new file mode 100644
index 00000000000..32c90fd9eba
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomains33xx_data.c
@@ -0,0 +1,196 @@
1/*
2 * AM33XX Clock Domain data.
3 *
4 * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
5 * Vaibhav Hiremath <hvaibhav@ti.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/kernel.h>
18#include <linux/io.h>
19
20#include "clockdomain.h"
21#include "cm.h"
22#include "cm33xx.h"
23#include "cm-regbits-33xx.h"
24
25static struct clockdomain l4ls_am33xx_clkdm = {
26 .name = "l4ls_clkdm",
27 .pwrdm = { .name = "per_pwrdm" },
28 .cm_inst = AM33XX_CM_PER_MOD,
29 .clkdm_offs = AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET,
30 .flags = CLKDM_CAN_SWSUP,
31};
32
33static struct clockdomain l3s_am33xx_clkdm = {
34 .name = "l3s_clkdm",
35 .pwrdm = { .name = "per_pwrdm" },
36 .cm_inst = AM33XX_CM_PER_MOD,
37 .clkdm_offs = AM33XX_CM_PER_L3S_CLKSTCTRL_OFFSET,
38 .flags = CLKDM_CAN_SWSUP,
39};
40
41static struct clockdomain l4fw_am33xx_clkdm = {
42 .name = "l4fw_clkdm",
43 .pwrdm = { .name = "per_pwrdm" },
44 .cm_inst = AM33XX_CM_PER_MOD,
45 .clkdm_offs = AM33XX_CM_PER_L4FW_CLKSTCTRL_OFFSET,
46 .flags = CLKDM_CAN_SWSUP,
47};
48
49static struct clockdomain l3_am33xx_clkdm = {
50 .name = "l3_clkdm",
51 .pwrdm = { .name = "per_pwrdm" },
52 .cm_inst = AM33XX_CM_PER_MOD,
53 .clkdm_offs = AM33XX_CM_PER_L3_CLKSTCTRL_OFFSET,
54 .flags = CLKDM_CAN_SWSUP,
55};
56
57static struct clockdomain l4hs_am33xx_clkdm = {
58 .name = "l4hs_clkdm",
59 .pwrdm = { .name = "per_pwrdm" },
60 .cm_inst = AM33XX_CM_PER_MOD,
61 .clkdm_offs = AM33XX_CM_PER_L4HS_CLKSTCTRL_OFFSET,
62 .flags = CLKDM_CAN_SWSUP,
63};
64
65static struct clockdomain ocpwp_l3_am33xx_clkdm = {
66 .name = "ocpwp_l3_clkdm",
67 .pwrdm = { .name = "per_pwrdm" },
68 .cm_inst = AM33XX_CM_PER_MOD,
69 .clkdm_offs = AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL_OFFSET,
70 .flags = CLKDM_CAN_SWSUP,
71};
72
73static struct clockdomain pruss_ocp_am33xx_clkdm = {
74 .name = "pruss_ocp_clkdm",
75 .pwrdm = { .name = "per_pwrdm" },
76 .cm_inst = AM33XX_CM_PER_MOD,
77 .clkdm_offs = AM33XX_CM_PER_PRUSS_CLKSTCTRL_OFFSET,
78 .flags = CLKDM_CAN_SWSUP,
79};
80
81static struct clockdomain cpsw_125mhz_am33xx_clkdm = {
82 .name = "cpsw_125mhz_clkdm",
83 .pwrdm = { .name = "per_pwrdm" },
84 .cm_inst = AM33XX_CM_PER_MOD,
85 .clkdm_offs = AM33XX_CM_PER_CPSW_CLKSTCTRL_OFFSET,
86 .flags = CLKDM_CAN_SWSUP,
87};
88
89static struct clockdomain lcdc_am33xx_clkdm = {
90 .name = "lcdc_clkdm",
91 .pwrdm = { .name = "per_pwrdm" },
92 .cm_inst = AM33XX_CM_PER_MOD,
93 .clkdm_offs = AM33XX_CM_PER_LCDC_CLKSTCTRL_OFFSET,
94 .flags = CLKDM_CAN_SWSUP,
95};
96
97static struct clockdomain clk_24mhz_am33xx_clkdm = {
98 .name = "clk_24mhz_clkdm",
99 .pwrdm = { .name = "per_pwrdm" },
100 .cm_inst = AM33XX_CM_PER_MOD,
101 .clkdm_offs = AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL_OFFSET,
102 .flags = CLKDM_CAN_SWSUP,
103};
104
105static struct clockdomain l4_wkup_am33xx_clkdm = {
106 .name = "l4_wkup_clkdm",
107 .pwrdm = { .name = "wkup_pwrdm" },
108 .cm_inst = AM33XX_CM_WKUP_MOD,
109 .clkdm_offs = AM33XX_CM_WKUP_CLKSTCTRL_OFFSET,
110 .flags = CLKDM_CAN_SWSUP,
111};
112
113static struct clockdomain l3_aon_am33xx_clkdm = {
114 .name = "l3_aon_clkdm",
115 .pwrdm = { .name = "wkup_pwrdm" },
116 .cm_inst = AM33XX_CM_WKUP_MOD,
117 .clkdm_offs = AM33XX_CM_L3_AON_CLKSTCTRL_OFFSET,
118 .flags = CLKDM_CAN_SWSUP,
119};
120
121static struct clockdomain l4_wkup_aon_am33xx_clkdm = {
122 .name = "l4_wkup_aon_clkdm",
123 .pwrdm = { .name = "wkup_pwrdm" },
124 .cm_inst = AM33XX_CM_WKUP_MOD,
125 .clkdm_offs = AM33XX_CM_L4_WKUP_AON_CLKSTCTRL_OFFSET,
126 .flags = CLKDM_CAN_SWSUP,
127};
128
129static struct clockdomain mpu_am33xx_clkdm = {
130 .name = "mpu_clkdm",
131 .pwrdm = { .name = "mpu_pwrdm" },
132 .cm_inst = AM33XX_CM_MPU_MOD,
133 .clkdm_offs = AM33XX_CM_MPU_CLKSTCTRL_OFFSET,
134 .flags = CLKDM_CAN_SWSUP,
135};
136
137static struct clockdomain l4_rtc_am33xx_clkdm = {
138 .name = "l4_rtc_clkdm",
139 .pwrdm = { .name = "rtc_pwrdm" },
140 .cm_inst = AM33XX_CM_RTC_MOD,
141 .clkdm_offs = AM33XX_CM_RTC_CLKSTCTRL_OFFSET,
142 .flags = CLKDM_CAN_SWSUP,
143};
144
145static struct clockdomain gfx_l3_am33xx_clkdm = {
146 .name = "gfx_l3_clkdm",
147 .pwrdm = { .name = "gfx_pwrdm" },
148 .cm_inst = AM33XX_CM_GFX_MOD,
149 .clkdm_offs = AM33XX_CM_GFX_L3_CLKSTCTRL_OFFSET,
150 .flags = CLKDM_CAN_SWSUP,
151};
152
153static struct clockdomain gfx_l4ls_gfx_am33xx_clkdm = {
154 .name = "gfx_l4ls_gfx_clkdm",
155 .pwrdm = { .name = "gfx_pwrdm" },
156 .cm_inst = AM33XX_CM_GFX_MOD,
157 .clkdm_offs = AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1_OFFSET,
158 .flags = CLKDM_CAN_SWSUP,
159};
160
161static struct clockdomain l4_cefuse_am33xx_clkdm = {
162 .name = "l4_cefuse_clkdm",
163 .pwrdm = { .name = "cefuse_pwrdm" },
164 .cm_inst = AM33XX_CM_CEFUSE_MOD,
165 .clkdm_offs = AM33XX_CM_CEFUSE_CLKSTCTRL_OFFSET,
166 .flags = CLKDM_CAN_SWSUP,
167};
168
169static struct clockdomain *clockdomains_am33xx[] __initdata = {
170 &l4ls_am33xx_clkdm,
171 &l3s_am33xx_clkdm,
172 &l4fw_am33xx_clkdm,
173 &l3_am33xx_clkdm,
174 &l4hs_am33xx_clkdm,
175 &ocpwp_l3_am33xx_clkdm,
176 &pruss_ocp_am33xx_clkdm,
177 &cpsw_125mhz_am33xx_clkdm,
178 &lcdc_am33xx_clkdm,
179 &clk_24mhz_am33xx_clkdm,
180 &l4_wkup_am33xx_clkdm,
181 &l3_aon_am33xx_clkdm,
182 &l4_wkup_aon_am33xx_clkdm,
183 &mpu_am33xx_clkdm,
184 &l4_rtc_am33xx_clkdm,
185 &gfx_l3_am33xx_clkdm,
186 &gfx_l4ls_gfx_am33xx_clkdm,
187 &l4_cefuse_am33xx_clkdm,
188 NULL,
189};
190
191void __init am33xx_clockdomains_init(void)
192{
193 clkdm_register_platform_funcs(&am33xx_clkdm_operations);
194 clkdm_register_clkdms(clockdomains_am33xx);
195 clkdm_complete_init();
196}
diff --git a/arch/arm/mach-omap2/clockdomains3xxx_data.c b/arch/arm/mach-omap2/clockdomains3xxx_data.c
index 6038adb9771..2cdc17c9d2f 100644
--- a/arch/arm/mach-omap2/clockdomains3xxx_data.c
+++ b/arch/arm/mach-omap2/clockdomains3xxx_data.c
@@ -347,8 +347,6 @@ static struct clkdm_autodep clkdm_autodeps[] = {
347 347
348static struct clockdomain *clockdomains_omap3430_common[] __initdata = { 348static struct clockdomain *clockdomains_omap3430_common[] __initdata = {
349 &wkup_common_clkdm, 349 &wkup_common_clkdm,
350 &cm_common_clkdm,
351 &prm_common_clkdm,
352 &mpu_3xxx_clkdm, 350 &mpu_3xxx_clkdm,
353 &neon_clkdm, 351 &neon_clkdm,
354 &iva2_clkdm, 352 &iva2_clkdm,
diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c b/arch/arm/mach-omap2/clockdomains44xx_data.c
index c5342584749..bd7ed13515c 100644
--- a/arch/arm/mach-omap2/clockdomains44xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains44xx_data.c
@@ -430,8 +430,6 @@ static struct clockdomain *clockdomains_omap44xx[] __initdata = {
430 &l4_wkup_44xx_clkdm, 430 &l4_wkup_44xx_clkdm,
431 &emu_sys_44xx_clkdm, 431 &emu_sys_44xx_clkdm,
432 &l3_dma_44xx_clkdm, 432 &l3_dma_44xx_clkdm,
433 &prm_common_clkdm,
434 &cm_common_clkdm,
435 NULL 433 NULL
436}; 434};
437 435
diff --git a/arch/arm/mach-omap2/clockdomains_common_data.c b/arch/arm/mach-omap2/clockdomains_common_data.c
deleted file mode 100644
index 615b1f04967..00000000000
--- a/arch/arm/mach-omap2/clockdomains_common_data.c
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * OMAP2+-common clockdomain data
3 *
4 * Copyright (C) 2008-2012 Texas Instruments, Inc.
5 * Copyright (C) 2008-2010 Nokia Corporation
6 *
7 * Paul Walmsley, Jouni Högander
8 */
9
10#include <linux/kernel.h>
11#include <linux/io.h>
12
13#include "clockdomain.h"
14
15/* These are implicit clockdomains - they are never defined as such in TRM */
16struct clockdomain prm_common_clkdm = {
17 .name = "prm_clkdm",
18 .pwrdm = { .name = "wkup_pwrdm" },
19};
20
21struct clockdomain cm_common_clkdm = {
22 .name = "cm_clkdm",
23 .pwrdm = { .name = "core_pwrdm" },
24};
diff --git a/arch/arm/mach-omap2/cm-regbits-33xx.h b/arch/arm/mach-omap2/cm-regbits-33xx.h
new file mode 100644
index 00000000000..532027ee3d8
--- /dev/null
+++ b/arch/arm/mach-omap2/cm-regbits-33xx.h
@@ -0,0 +1,687 @@
1/*
2 * AM33XX Power Management register bits
3 *
4 * This file is automatically generated from the AM33XX hardware databases.
5 * Vaibhav Hiremath <hvaibhav@ti.com>
6 *
7 * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation version 2.
12 *
13 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
14 * kind, whether express or implied; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19
20#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H
21#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H
22
23/*
24 * Used by CM_AUTOIDLE_DPLL_CORE, CM_AUTOIDLE_DPLL_DDR, CM_AUTOIDLE_DPLL_DISP,
25 * CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER
26 */
27#define AM33XX_AUTO_DPLL_MODE_SHIFT 0
28#define AM33XX_AUTO_DPLL_MODE_MASK (0x7 << 0)
29
30/* Used by CM_WKUP_CLKSTCTRL */
31#define AM33XX_CLKACTIVITY_ADC_FCLK_SHIFT 14
32#define AM33XX_CLKACTIVITY_ADC_FCLK_MASK (1 << 16)
33
34/* Used by CM_PER_L4LS_CLKSTCTRL */
35#define AM33XX_CLKACTIVITY_CAN_CLK_SHIFT 11
36#define AM33XX_CLKACTIVITY_CAN_CLK_MASK (1 << 11)
37
38/* Used by CM_PER_CLK_24MHZ_CLKSTCTRL */
39#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_SHIFT 4
40#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_MASK (1 << 4)
41
42/* Used by CM_PER_CPSW_CLKSTCTRL */
43#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_SHIFT 4
44#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_MASK (1 << 4)
45
46/* Used by CM_PER_L4HS_CLKSTCTRL */
47#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_SHIFT 4
48#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_MASK (1 << 4)
49
50/* Used by CM_PER_L4HS_CLKSTCTRL */
51#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_SHIFT 5
52#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_MASK (1 << 5)
53
54/* Used by CM_PER_L4HS_CLKSTCTRL */
55#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_SHIFT 6
56#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_MASK (1 << 6)
57
58/* Used by CM_PER_L3_CLKSTCTRL */
59#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_SHIFT 6
60#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_MASK (1 << 6)
61
62/* Used by CM_CEFUSE_CLKSTCTRL */
63#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9
64#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9)
65
66/* Used by CM_L3_AON_CLKSTCTRL */
67#define AM33XX_CLKACTIVITY_DBGSYSCLK_SHIFT 2
68#define AM33XX_CLKACTIVITY_DBGSYSCLK_MASK (1 << 2)
69
70/* Used by CM_L3_AON_CLKSTCTRL */
71#define AM33XX_CLKACTIVITY_DEBUG_CLKA_SHIFT 4
72#define AM33XX_CLKACTIVITY_DEBUG_CLKA_MASK (1 << 4)
73
74/* Used by CM_PER_L3_CLKSTCTRL */
75#define AM33XX_CLKACTIVITY_EMIF_GCLK_SHIFT 2
76#define AM33XX_CLKACTIVITY_EMIF_GCLK_MASK (1 << 2)
77
78/* Used by CM_GFX_L3_CLKSTCTRL */
79#define AM33XX_CLKACTIVITY_GFX_FCLK_SHIFT 9
80#define AM33XX_CLKACTIVITY_GFX_FCLK_MASK (1 << 9)
81
82/* Used by CM_GFX_L3_CLKSTCTRL */
83#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_SHIFT 8
84#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_MASK (1 << 8)
85
86/* Used by CM_WKUP_CLKSTCTRL */
87#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_SHIFT 8
88#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_MASK (1 << 8)
89
90/* Used by CM_PER_L4LS_CLKSTCTRL */
91#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_SHIFT 19
92#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_MASK (1 << 19)
93
94/* Used by CM_PER_L4LS_CLKSTCTRL */
95#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_SHIFT 20
96#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_MASK (1 << 20)
97
98/* Used by CM_PER_L4LS_CLKSTCTRL */
99#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_SHIFT 21
100#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_MASK (1 << 21)
101
102/* Used by CM_PER_L4LS_CLKSTCTRL */
103#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_SHIFT 22
104#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_MASK (1 << 22)
105
106/* Used by CM_PER_L4LS_CLKSTCTRL */
107#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_SHIFT 26
108#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_MASK (1 << 26)
109
110/* Used by CM_PER_L4LS_CLKSTCTRL */
111#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_SHIFT 18
112#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_MASK (1 << 18)
113
114/* Used by CM_WKUP_CLKSTCTRL */
115#define AM33XX_CLKACTIVITY_I2C0_GFCLK_SHIFT 11
116#define AM33XX_CLKACTIVITY_I2C0_GFCLK_MASK (1 << 11)
117
118/* Used by CM_PER_L4LS_CLKSTCTRL */
119#define AM33XX_CLKACTIVITY_I2C_FCLK_SHIFT 24
120#define AM33XX_CLKACTIVITY_I2C_FCLK_MASK (1 << 24)
121
122/* Used by CM_PER_PRUSS_CLKSTCTRL */
123#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_SHIFT 5
124#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_MASK (1 << 5)
125
126/* Used by CM_PER_PRUSS_CLKSTCTRL */
127#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_SHIFT 4
128#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_MASK (1 << 4)
129
130/* Used by CM_PER_PRUSS_CLKSTCTRL */
131#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_SHIFT 6
132#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_MASK (1 << 6)
133
134/* Used by CM_PER_L3S_CLKSTCTRL */
135#define AM33XX_CLKACTIVITY_L3S_GCLK_SHIFT 3
136#define AM33XX_CLKACTIVITY_L3S_GCLK_MASK (1 << 3)
137
138/* Used by CM_L3_AON_CLKSTCTRL */
139#define AM33XX_CLKACTIVITY_L3_AON_GCLK_SHIFT 3
140#define AM33XX_CLKACTIVITY_L3_AON_GCLK_MASK (1 << 3)
141
142/* Used by CM_PER_L3_CLKSTCTRL */
143#define AM33XX_CLKACTIVITY_L3_GCLK_SHIFT 4
144#define AM33XX_CLKACTIVITY_L3_GCLK_MASK (1 << 4)
145
146/* Used by CM_PER_L4FW_CLKSTCTRL */
147#define AM33XX_CLKACTIVITY_L4FW_GCLK_SHIFT 8
148#define AM33XX_CLKACTIVITY_L4FW_GCLK_MASK (1 << 8)
149
150/* Used by CM_PER_L4HS_CLKSTCTRL */
151#define AM33XX_CLKACTIVITY_L4HS_GCLK_SHIFT 3
152#define AM33XX_CLKACTIVITY_L4HS_GCLK_MASK (1 << 3)
153
154/* Used by CM_PER_L4LS_CLKSTCTRL */
155#define AM33XX_CLKACTIVITY_L4LS_GCLK_SHIFT 8
156#define AM33XX_CLKACTIVITY_L4LS_GCLK_MASK (1 << 8)
157
158/* Used by CM_GFX_L4LS_GFX_CLKSTCTRL__1 */
159#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_SHIFT 8
160#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_MASK (1 << 8)
161
162/* Used by CM_CEFUSE_CLKSTCTRL */
163#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8
164#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_MASK (1 << 8)
165
166/* Used by CM_RTC_CLKSTCTRL */
167#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_SHIFT 8
168#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_MASK (1 << 8)
169
170/* Used by CM_L4_WKUP_AON_CLKSTCTRL */
171#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_SHIFT 2
172#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_MASK (1 << 2)
173
174/* Used by CM_WKUP_CLKSTCTRL */
175#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_SHIFT 2
176#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_MASK (1 << 2)
177
178/* Used by CM_PER_L4LS_CLKSTCTRL */
179#define AM33XX_CLKACTIVITY_LCDC_GCLK_SHIFT 17
180#define AM33XX_CLKACTIVITY_LCDC_GCLK_MASK (1 << 17)
181
182/* Used by CM_PER_LCDC_CLKSTCTRL */
183#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_SHIFT 4
184#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_MASK (1 << 4)
185
186/* Used by CM_PER_LCDC_CLKSTCTRL */
187#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_SHIFT 5
188#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_MASK (1 << 5)
189
190/* Used by CM_PER_L3_CLKSTCTRL */
191#define AM33XX_CLKACTIVITY_MCASP_GCLK_SHIFT 7
192#define AM33XX_CLKACTIVITY_MCASP_GCLK_MASK (1 << 7)
193
194/* Used by CM_PER_L3_CLKSTCTRL */
195#define AM33XX_CLKACTIVITY_MMC_FCLK_SHIFT 3
196#define AM33XX_CLKACTIVITY_MMC_FCLK_MASK (1 << 3)
197
198/* Used by CM_MPU_CLKSTCTRL */
199#define AM33XX_CLKACTIVITY_MPU_CLK_SHIFT 2
200#define AM33XX_CLKACTIVITY_MPU_CLK_MASK (1 << 2)
201
202/* Used by CM_PER_OCPWP_L3_CLKSTCTRL */
203#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_SHIFT 4
204#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_MASK (1 << 4)
205
206/* Used by CM_PER_OCPWP_L3_CLKSTCTRL */
207#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_SHIFT 5
208#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_MASK (1 << 5)
209
210/* Used by CM_RTC_CLKSTCTRL */
211#define AM33XX_CLKACTIVITY_RTC_32KCLK_SHIFT 9
212#define AM33XX_CLKACTIVITY_RTC_32KCLK_MASK (1 << 9)
213
214/* Used by CM_PER_L4LS_CLKSTCTRL */
215#define AM33XX_CLKACTIVITY_SPI_GCLK_SHIFT 25
216#define AM33XX_CLKACTIVITY_SPI_GCLK_MASK (1 << 25)
217
218/* Used by CM_WKUP_CLKSTCTRL */
219#define AM33XX_CLKACTIVITY_SR_SYSCLK_SHIFT 3
220#define AM33XX_CLKACTIVITY_SR_SYSCLK_MASK (1 << 3)
221
222/* Used by CM_WKUP_CLKSTCTRL */
223#define AM33XX_CLKACTIVITY_TIMER0_GCLK_SHIFT 10
224#define AM33XX_CLKACTIVITY_TIMER0_GCLK_MASK (1 << 10)
225
226/* Used by CM_WKUP_CLKSTCTRL */
227#define AM33XX_CLKACTIVITY_TIMER1_GCLK_SHIFT 13
228#define AM33XX_CLKACTIVITY_TIMER1_GCLK_MASK (1 << 13)
229
230/* Used by CM_PER_L4LS_CLKSTCTRL */
231#define AM33XX_CLKACTIVITY_TIMER2_GCLK_SHIFT 14
232#define AM33XX_CLKACTIVITY_TIMER2_GCLK_MASK (1 << 14)
233
234/* Used by CM_PER_L4LS_CLKSTCTRL */
235#define AM33XX_CLKACTIVITY_TIMER3_GCLK_SHIFT 15
236#define AM33XX_CLKACTIVITY_TIMER3_GCLK_MASK (1 << 15)
237
238/* Used by CM_PER_L4LS_CLKSTCTRL */
239#define AM33XX_CLKACTIVITY_TIMER4_GCLK_SHIFT 16
240#define AM33XX_CLKACTIVITY_TIMER4_GCLK_MASK (1 << 16)
241
242/* Used by CM_PER_L4LS_CLKSTCTRL */
243#define AM33XX_CLKACTIVITY_TIMER5_GCLK_SHIFT 27
244#define AM33XX_CLKACTIVITY_TIMER5_GCLK_MASK (1 << 27)
245
246/* Used by CM_PER_L4LS_CLKSTCTRL */
247#define AM33XX_CLKACTIVITY_TIMER6_GCLK_SHIFT 28
248#define AM33XX_CLKACTIVITY_TIMER6_GCLK_MASK (1 << 28)
249
250/* Used by CM_PER_L4LS_CLKSTCTRL */
251#define AM33XX_CLKACTIVITY_TIMER7_GCLK_SHIFT 13
252#define AM33XX_CLKACTIVITY_TIMER7_GCLK_MASK (1 << 13)
253
254/* Used by CM_WKUP_CLKSTCTRL */
255#define AM33XX_CLKACTIVITY_UART0_GFCLK_SHIFT 12
256#define AM33XX_CLKACTIVITY_UART0_GFCLK_MASK (1 << 12)
257
258/* Used by CM_PER_L4LS_CLKSTCTRL */
259#define AM33XX_CLKACTIVITY_UART_GFCLK_SHIFT 10
260#define AM33XX_CLKACTIVITY_UART_GFCLK_MASK (1 << 10)
261
262/* Used by CM_WKUP_CLKSTCTRL */
263#define AM33XX_CLKACTIVITY_WDT0_GCLK_SHIFT 9
264#define AM33XX_CLKACTIVITY_WDT0_GCLK_MASK (1 << 9)
265
266/* Used by CM_WKUP_CLKSTCTRL */
267#define AM33XX_CLKACTIVITY_WDT1_GCLK_SHIFT 4
268#define AM33XX_CLKACTIVITY_WDT1_GCLK_MASK (1 << 4)
269
270/* Used by CLKSEL_GFX_FCLK */
271#define AM33XX_CLKDIV_SEL_GFX_FCLK_SHIFT 0
272#define AM33XX_CLKDIV_SEL_GFX_FCLK_MASK (1 << 0)
273
274/* Used by CM_CLKOUT_CTRL */
275#define AM33XX_CLKOUT2DIV_SHIFT 3
276#define AM33XX_CLKOUT2DIV_MASK (0x05 << 3)
277
278/* Used by CM_CLKOUT_CTRL */
279#define AM33XX_CLKOUT2EN_SHIFT 7
280#define AM33XX_CLKOUT2EN_MASK (1 << 7)
281
282/* Used by CM_CLKOUT_CTRL */
283#define AM33XX_CLKOUT2SOURCE_SHIFT 0
284#define AM33XX_CLKOUT2SOURCE_MASK (0x02 << 0)
285
286/*
287 * Used by CLKSEL_GPIO0_DBCLK, CLKSEL_LCDC_PIXEL_CLK, CLKSEL_TIMER2_CLK,
288 * CLKSEL_TIMER3_CLK, CLKSEL_TIMER4_CLK, CLKSEL_TIMER5_CLK, CLKSEL_TIMER6_CLK,
289 * CLKSEL_TIMER7_CLK
290 */
291#define AM33XX_CLKSEL_SHIFT 0
292#define AM33XX_CLKSEL_MASK (0x01 << 0)
293
294/*
295 * Renamed from CLKSEL Used by CLKSEL_PRUSS_OCP_CLK, CLKSEL_WDT1_CLK,
296 * CM_CPTS_RFT_CLKSEL
297 */
298#define AM33XX_CLKSEL_0_0_SHIFT 0
299#define AM33XX_CLKSEL_0_0_MASK (1 << 0)
300
301#define AM33XX_CLKSEL_0_1_SHIFT 0
302#define AM33XX_CLKSEL_0_1_MASK (3 << 0)
303
304/* Renamed from CLKSEL Used by CLKSEL_TIMER1MS_CLK */
305#define AM33XX_CLKSEL_0_2_SHIFT 0
306#define AM33XX_CLKSEL_0_2_MASK (7 << 0)
307
308/* Used by CLKSEL_GFX_FCLK */
309#define AM33XX_CLKSEL_GFX_FCLK_SHIFT 1
310#define AM33XX_CLKSEL_GFX_FCLK_MASK (1 << 1)
311
312/*
313 * Used by CM_MPU_CLKSTCTRL, CM_RTC_CLKSTCTRL, CM_PER_CLK_24MHZ_CLKSTCTRL,
314 * CM_PER_CPSW_CLKSTCTRL, CM_PER_PRUSS_CLKSTCTRL, CM_PER_L3S_CLKSTCTRL,
315 * CM_PER_L3_CLKSTCTRL, CM_PER_L4FW_CLKSTCTRL, CM_PER_L4HS_CLKSTCTRL,
316 * CM_PER_L4LS_CLKSTCTRL, CM_PER_LCDC_CLKSTCTRL, CM_PER_OCPWP_L3_CLKSTCTRL,
317 * CM_L3_AON_CLKSTCTRL, CM_L4_WKUP_AON_CLKSTCTRL, CM_WKUP_CLKSTCTRL,
318 * CM_GFX_L3_CLKSTCTRL, CM_GFX_L4LS_GFX_CLKSTCTRL__1, CM_CEFUSE_CLKSTCTRL
319 */
320#define AM33XX_CLKTRCTRL_SHIFT 0
321#define AM33XX_CLKTRCTRL_MASK (0x3 << 0)
322
323/*
324 * Used by CM_SSC_DELTAMSTEP_DPLL_CORE, CM_SSC_DELTAMSTEP_DPLL_DDR,
325 * CM_SSC_DELTAMSTEP_DPLL_DISP, CM_SSC_DELTAMSTEP_DPLL_MPU,
326 * CM_SSC_DELTAMSTEP_DPLL_PER
327 */
328#define AM33XX_DELTAMSTEP_SHIFT 0
329#define AM33XX_DELTAMSTEP_MASK (0x19 << 0)
330
331/* Used by CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP, CM_CLKSEL_DPLL_MPU */
332#define AM33XX_DPLL_BYP_CLKSEL_SHIFT 23
333#define AM33XX_DPLL_BYP_CLKSEL_MASK (1 << 23)
334
335/* Used by CM_CLKDCOLDO_DPLL_PER */
336#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8
337#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_MASK (1 << 8)
338
339/* Used by CM_CLKDCOLDO_DPLL_PER */
340#define AM33XX_DPLL_CLKDCOLDO_PWDN_SHIFT 12
341#define AM33XX_DPLL_CLKDCOLDO_PWDN_MASK (1 << 12)
342
343/* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */
344#define AM33XX_DPLL_CLKOUT_DIV_SHIFT 0
345#define AM33XX_DPLL_CLKOUT_DIV_MASK (0x1f << 0)
346
347/* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_PER */
348#define AM33XX_DPLL_CLKOUT_DIV_0_6_SHIFT 0
349#define AM33XX_DPLL_CLKOUT_DIV_0_6_MASK (0x06 << 0)
350
351/* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */
352#define AM33XX_DPLL_CLKOUT_DIVCHACK_SHIFT 5
353#define AM33XX_DPLL_CLKOUT_DIVCHACK_MASK (1 << 5)
354
355/* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_PER */
356#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_SHIFT 7
357#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_MASK (1 << 7)
358
359/*
360 * Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU,
361 * CM_DIV_M2_DPLL_PER
362 */
363#define AM33XX_DPLL_CLKOUT_GATE_CTRL_SHIFT 8
364#define AM33XX_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8)
365
366/*
367 * Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP,
368 * CM_CLKSEL_DPLL_MPU
369 */
370#define AM33XX_DPLL_DIV_SHIFT 0
371#define AM33XX_DPLL_DIV_MASK (0x7f << 0)
372
373#define AM33XX_DPLL_PER_DIV_MASK (0xff << 0)
374
375/* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_PERIPH */
376#define AM33XX_DPLL_DIV_0_7_SHIFT 0
377#define AM33XX_DPLL_DIV_0_7_MASK (0x07 << 0)
378
379/*
380 * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
381 * CM_CLKMODE_DPLL_MPU
382 */
383#define AM33XX_DPLL_DRIFTGUARD_EN_SHIFT 8
384#define AM33XX_DPLL_DRIFTGUARD_EN_MASK (1 << 8)
385
386/*
387 * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
388 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
389 */
390#define AM33XX_DPLL_EN_SHIFT 0
391#define AM33XX_DPLL_EN_MASK (0x7 << 0)
392
393/*
394 * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
395 * CM_CLKMODE_DPLL_MPU
396 */
397#define AM33XX_DPLL_LPMODE_EN_SHIFT 10
398#define AM33XX_DPLL_LPMODE_EN_MASK (1 << 10)
399
400/*
401 * Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP,
402 * CM_CLKSEL_DPLL_MPU
403 */
404#define AM33XX_DPLL_MULT_SHIFT 8
405#define AM33XX_DPLL_MULT_MASK (0x7ff << 8)
406
407/* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_PERIPH */
408#define AM33XX_DPLL_MULT_PERIPH_SHIFT 8
409#define AM33XX_DPLL_MULT_PERIPH_MASK (0xfff << 8)
410
411/*
412 * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
413 * CM_CLKMODE_DPLL_MPU
414 */
415#define AM33XX_DPLL_REGM4XEN_SHIFT 11
416#define AM33XX_DPLL_REGM4XEN_MASK (1 << 11)
417
418/* Used by CM_CLKSEL_DPLL_PERIPH */
419#define AM33XX_DPLL_SD_DIV_SHIFT 24
420#define AM33XX_DPLL_SD_DIV_MASK (24, 31)
421
422/*
423 * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
424 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
425 */
426#define AM33XX_DPLL_SSC_ACK_SHIFT 13
427#define AM33XX_DPLL_SSC_ACK_MASK (1 << 13)
428
429/*
430 * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
431 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
432 */
433#define AM33XX_DPLL_SSC_DOWNSPREAD_SHIFT 14
434#define AM33XX_DPLL_SSC_DOWNSPREAD_MASK (1 << 14)
435
436/*
437 * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
438 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
439 */
440#define AM33XX_DPLL_SSC_EN_SHIFT 12
441#define AM33XX_DPLL_SSC_EN_MASK (1 << 12)
442
443/* Used by CM_DIV_M4_DPLL_CORE */
444#define AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT 0
445#define AM33XX_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0)
446
447/* Used by CM_DIV_M4_DPLL_CORE */
448#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5
449#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_MASK (1 << 5)
450
451/* Used by CM_DIV_M4_DPLL_CORE */
452#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8
453#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK (1 << 8)
454
455/* Used by CM_DIV_M4_DPLL_CORE */
456#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12
457#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_MASK (1 << 12)
458
459/* Used by CM_DIV_M5_DPLL_CORE */
460#define AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT 0
461#define AM33XX_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0)
462
463/* Used by CM_DIV_M5_DPLL_CORE */
464#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5
465#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_MASK (1 << 5)
466
467/* Used by CM_DIV_M5_DPLL_CORE */
468#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8
469#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK (1 << 8)
470
471/* Used by CM_DIV_M5_DPLL_CORE */
472#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12
473#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_MASK (1 << 12)
474
475/* Used by CM_DIV_M6_DPLL_CORE */
476#define AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT 0
477#define AM33XX_HSDIVIDER_CLKOUT3_DIV_MASK (0x04 << 0)
478
479/* Used by CM_DIV_M6_DPLL_CORE */
480#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5
481#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_MASK (1 << 5)
482
483/* Used by CM_DIV_M6_DPLL_CORE */
484#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8
485#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK (1 << 8)
486
487/* Used by CM_DIV_M6_DPLL_CORE */
488#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12
489#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_MASK (1 << 12)
490
491/*
492 * Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL,
493 * CM_PER_AES1_CLKCTRL, CM_PER_CLKDIV32K_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL,
494 * CM_PER_DCAN0_CLKCTRL, CM_PER_DCAN1_CLKCTRL, CM_PER_DES_CLKCTRL,
495 * CM_PER_ELM_CLKCTRL, CM_PER_EMIF_CLKCTRL, CM_PER_EMIF_FW_CLKCTRL,
496 * CM_PER_EPWMSS0_CLKCTRL, CM_PER_EPWMSS1_CLKCTRL, CM_PER_EPWMSS2_CLKCTRL,
497 * CM_PER_GPIO1_CLKCTRL, CM_PER_GPIO2_CLKCTRL, CM_PER_GPIO3_CLKCTRL,
498 * CM_PER_GPIO4_CLKCTRL, CM_PER_GPIO5_CLKCTRL, CM_PER_GPIO6_CLKCTRL,
499 * CM_PER_GPMC_CLKCTRL, CM_PER_I2C1_CLKCTRL, CM_PER_I2C2_CLKCTRL,
500 * CM_PER_PRUSS_CLKCTRL, CM_PER_IEEE5000_CLKCTRL, CM_PER_L3_CLKCTRL,
501 * CM_PER_L3_INSTR_CLKCTRL, CM_PER_L4FW_CLKCTRL, CM_PER_L4HS_CLKCTRL,
502 * CM_PER_L4LS_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MAILBOX0_CLKCTRL,
503 * CM_PER_MAILBOX1_CLKCTRL, CM_PER_MCASP0_CLKCTRL, CM_PER_MCASP1_CLKCTRL,
504 * CM_PER_MCASP2_CLKCTRL, CM_PER_MLB_CLKCTRL, CM_PER_MMC0_CLKCTRL,
505 * CM_PER_MMC1_CLKCTRL, CM_PER_MMC2_CLKCTRL, CM_PER_MSTR_EXPS_CLKCTRL,
506 * CM_PER_OCMCRAM_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL,
507 * CM_PER_PKA_CLKCTRL, CM_PER_RNG_CLKCTRL, CM_PER_SHA0_CLKCTRL,
508 * CM_PER_SLV_EXPS_CLKCTRL, CM_PER_SPARE0_CLKCTRL, CM_PER_SPARE1_CLKCTRL,
509 * CM_PER_SPARE_CLKCTRL, CM_PER_SPI0_CLKCTRL, CM_PER_SPI1_CLKCTRL,
510 * CM_PER_SPI2_CLKCTRL, CM_PER_SPI3_CLKCTRL, CM_PER_SPINLOCK_CLKCTRL,
511 * CM_PER_TIMER2_CLKCTRL, CM_PER_TIMER3_CLKCTRL, CM_PER_TIMER4_CLKCTRL,
512 * CM_PER_TIMER5_CLKCTRL, CM_PER_TIMER6_CLKCTRL, CM_PER_TIMER7_CLKCTRL,
513 * CM_PER_TPCC_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL,
514 * CM_PER_TPTC2_CLKCTRL, CM_PER_UART1_CLKCTRL, CM_PER_UART2_CLKCTRL,
515 * CM_PER_UART3_CLKCTRL, CM_PER_UART4_CLKCTRL, CM_PER_UART5_CLKCTRL,
516 * CM_PER_USB0_CLKCTRL, CM_WKUP_ADC_TSC_CLKCTRL, CM_WKUP_CONTROL_CLKCTRL,
517 * CM_WKUP_DEBUGSS_CLKCTRL, CM_WKUP_GPIO0_CLKCTRL, CM_WKUP_I2C0_CLKCTRL,
518 * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SMARTREFLEX0_CLKCTRL,
519 * CM_WKUP_SMARTREFLEX1_CLKCTRL, CM_WKUP_TIMER0_CLKCTRL,
520 * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_UART0_CLKCTRL, CM_WKUP_WDT0_CLKCTRL,
521 * CM_WKUP_WDT1_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL,
522 * CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL
523 */
524#define AM33XX_IDLEST_SHIFT 16
525#define AM33XX_IDLEST_MASK (0x3 << 16)
526#define AM33XX_IDLEST_VAL 0x3
527
528/* Used by CM_MAC_CLKSEL */
529#define AM33XX_MII_CLK_SEL_SHIFT 2
530#define AM33XX_MII_CLK_SEL_MASK (1 << 2)
531
532/*
533 * Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR,
534 * CM_SSC_MODFREQDIV_DPLL_DISP, CM_SSC_MODFREQDIV_DPLL_MPU,
535 * CM_SSC_MODFREQDIV_DPLL_PER
536 */
537#define AM33XX_MODFREQDIV_EXPONENT_SHIFT 8
538#define AM33XX_MODFREQDIV_EXPONENT_MASK (0x10 << 8)
539
540/*
541 * Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR,
542 * CM_SSC_MODFREQDIV_DPLL_DISP, CM_SSC_MODFREQDIV_DPLL_MPU,
543 * CM_SSC_MODFREQDIV_DPLL_PER
544 */
545#define AM33XX_MODFREQDIV_MANTISSA_SHIFT 0
546#define AM33XX_MODFREQDIV_MANTISSA_MASK (0x06 << 0)
547
548/*
549 * Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL,
550 * CM_PER_AES1_CLKCTRL, CM_PER_CLKDIV32K_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL,
551 * CM_PER_DCAN0_CLKCTRL, CM_PER_DCAN1_CLKCTRL, CM_PER_DES_CLKCTRL,
552 * CM_PER_ELM_CLKCTRL, CM_PER_EMIF_CLKCTRL, CM_PER_EMIF_FW_CLKCTRL,
553 * CM_PER_EPWMSS0_CLKCTRL, CM_PER_EPWMSS1_CLKCTRL, CM_PER_EPWMSS2_CLKCTRL,
554 * CM_PER_GPIO1_CLKCTRL, CM_PER_GPIO2_CLKCTRL, CM_PER_GPIO3_CLKCTRL,
555 * CM_PER_GPIO4_CLKCTRL, CM_PER_GPIO5_CLKCTRL, CM_PER_GPIO6_CLKCTRL,
556 * CM_PER_GPMC_CLKCTRL, CM_PER_I2C1_CLKCTRL, CM_PER_I2C2_CLKCTRL,
557 * CM_PER_PRUSS_CLKCTRL, CM_PER_IEEE5000_CLKCTRL, CM_PER_L3_CLKCTRL,
558 * CM_PER_L3_INSTR_CLKCTRL, CM_PER_L4FW_CLKCTRL, CM_PER_L4HS_CLKCTRL,
559 * CM_PER_L4LS_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MAILBOX0_CLKCTRL,
560 * CM_PER_MAILBOX1_CLKCTRL, CM_PER_MCASP0_CLKCTRL, CM_PER_MCASP1_CLKCTRL,
561 * CM_PER_MCASP2_CLKCTRL, CM_PER_MLB_CLKCTRL, CM_PER_MMC0_CLKCTRL,
562 * CM_PER_MMC1_CLKCTRL, CM_PER_MMC2_CLKCTRL, CM_PER_MSTR_EXPS_CLKCTRL,
563 * CM_PER_OCMCRAM_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL,
564 * CM_PER_PKA_CLKCTRL, CM_PER_RNG_CLKCTRL, CM_PER_SHA0_CLKCTRL,
565 * CM_PER_SLV_EXPS_CLKCTRL, CM_PER_SPARE0_CLKCTRL, CM_PER_SPARE1_CLKCTRL,
566 * CM_PER_SPARE_CLKCTRL, CM_PER_SPI0_CLKCTRL, CM_PER_SPI1_CLKCTRL,
567 * CM_PER_SPI2_CLKCTRL, CM_PER_SPI3_CLKCTRL, CM_PER_SPINLOCK_CLKCTRL,
568 * CM_PER_TIMER2_CLKCTRL, CM_PER_TIMER3_CLKCTRL, CM_PER_TIMER4_CLKCTRL,
569 * CM_PER_TIMER5_CLKCTRL, CM_PER_TIMER6_CLKCTRL, CM_PER_TIMER7_CLKCTRL,
570 * CM_PER_TPCC_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL,
571 * CM_PER_TPTC2_CLKCTRL, CM_PER_UART1_CLKCTRL, CM_PER_UART2_CLKCTRL,
572 * CM_PER_UART3_CLKCTRL, CM_PER_UART4_CLKCTRL, CM_PER_UART5_CLKCTRL,
573 * CM_PER_USB0_CLKCTRL, CM_WKUP_ADC_TSC_CLKCTRL, CM_WKUP_CONTROL_CLKCTRL,
574 * CM_WKUP_DEBUGSS_CLKCTRL, CM_WKUP_GPIO0_CLKCTRL, CM_WKUP_I2C0_CLKCTRL,
575 * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SMARTREFLEX0_CLKCTRL,
576 * CM_WKUP_SMARTREFLEX1_CLKCTRL, CM_WKUP_TIMER0_CLKCTRL,
577 * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_UART0_CLKCTRL, CM_WKUP_WDT0_CLKCTRL,
578 * CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL,
579 * CM_GFX_GFX_CLKCTRL, CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL,
580 * CM_CEFUSE_CEFUSE_CLKCTRL
581 */
582#define AM33XX_MODULEMODE_SHIFT 0
583#define AM33XX_MODULEMODE_MASK (0x3 << 0)
584
585/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
586#define AM33XX_OPTCLK_DEBUG_CLKA_SHIFT 30
587#define AM33XX_OPTCLK_DEBUG_CLKA_MASK (1 << 30)
588
589/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
590#define AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT 19
591#define AM33XX_OPTFCLKEN_DBGSYSCLK_MASK (1 << 19)
592
593/* Used by CM_WKUP_GPIO0_CLKCTRL */
594#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT 18
595#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_MASK (1 << 18)
596
597/* Used by CM_PER_GPIO1_CLKCTRL */
598#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT 18
599#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_MASK (1 << 18)
600
601/* Used by CM_PER_GPIO2_CLKCTRL */
602#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT 18
603#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_MASK (1 << 18)
604
605/* Used by CM_PER_GPIO3_CLKCTRL */
606#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT 18
607#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_MASK (1 << 18)
608
609/* Used by CM_PER_GPIO4_CLKCTRL */
610#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_SHIFT 18
611#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_MASK (1 << 18)
612
613/* Used by CM_PER_GPIO5_CLKCTRL */
614#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_SHIFT 18
615#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_MASK (1 << 18)
616
617/* Used by CM_PER_GPIO6_CLKCTRL */
618#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_SHIFT 18
619#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_MASK (1 << 18)
620
621/*
622 * Used by CM_MPU_MPU_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL, CM_PER_PRUSS_CLKCTRL,
623 * CM_PER_IEEE5000_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MLB_CLKCTRL,
624 * CM_PER_MSTR_EXPS_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL,
625 * CM_PER_SPARE_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL,
626 * CM_PER_TPTC2_CLKCTRL, CM_PER_USB0_CLKCTRL, CM_WKUP_DEBUGSS_CLKCTRL,
627 * CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL
628 */
629#define AM33XX_STBYST_SHIFT 18
630#define AM33XX_STBYST_MASK (1 << 18)
631
632/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
633#define AM33XX_STM_PMD_CLKDIVSEL_SHIFT 27
634#define AM33XX_STM_PMD_CLKDIVSEL_MASK (0x29 << 27)
635
636/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
637#define AM33XX_STM_PMD_CLKSEL_SHIFT 22
638#define AM33XX_STM_PMD_CLKSEL_MASK (0x23 << 22)
639
640/*
641 * Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP,
642 * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER
643 */
644#define AM33XX_ST_DPLL_CLK_SHIFT 0
645#define AM33XX_ST_DPLL_CLK_MASK (1 << 0)
646
647/* Used by CM_CLKDCOLDO_DPLL_PER */
648#define AM33XX_ST_DPLL_CLKDCOLDO_SHIFT 8
649#define AM33XX_ST_DPLL_CLKDCOLDO_MASK (1 << 8)
650
651/*
652 * Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU,
653 * CM_DIV_M2_DPLL_PER
654 */
655#define AM33XX_ST_DPLL_CLKOUT_SHIFT 9
656#define AM33XX_ST_DPLL_CLKOUT_MASK (1 << 9)
657
658/* Used by CM_DIV_M4_DPLL_CORE */
659#define AM33XX_ST_HSDIVIDER_CLKOUT1_SHIFT 9
660#define AM33XX_ST_HSDIVIDER_CLKOUT1_MASK (1 << 9)
661
662/* Used by CM_DIV_M5_DPLL_CORE */
663#define AM33XX_ST_HSDIVIDER_CLKOUT2_SHIFT 9
664#define AM33XX_ST_HSDIVIDER_CLKOUT2_MASK (1 << 9)
665
666/* Used by CM_DIV_M6_DPLL_CORE */
667#define AM33XX_ST_HSDIVIDER_CLKOUT3_SHIFT 9
668#define AM33XX_ST_HSDIVIDER_CLKOUT3_MASK (1 << 9)
669
670/*
671 * Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP,
672 * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER
673 */
674#define AM33XX_ST_MN_BYPASS_SHIFT 8
675#define AM33XX_ST_MN_BYPASS_MASK (1 << 8)
676
677/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
678#define AM33XX_TRC_PMD_CLKDIVSEL_SHIFT 24
679#define AM33XX_TRC_PMD_CLKDIVSEL_MASK (0x26 << 24)
680
681/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
682#define AM33XX_TRC_PMD_CLKSEL_SHIFT 20
683#define AM33XX_TRC_PMD_CLKSEL_MASK (0x21 << 20)
684
685/* Used by CONTROL_SEC_CLK_CTRL */
686#define AM33XX_TIMER0_CLKSEL_MASK (0x3 << 4)
687#endif
diff --git a/arch/arm/mach-omap2/cm33xx.c b/arch/arm/mach-omap2/cm33xx.c
new file mode 100644
index 00000000000..13f56eafef0
--- /dev/null
+++ b/arch/arm/mach-omap2/cm33xx.c
@@ -0,0 +1,313 @@
1/*
2 * AM33XX CM functions
3 *
4 * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
5 * Vaibhav Hiremath <hvaibhav@ti.com>
6 *
7 * Reference taken from from OMAP4 cminst44xx.c
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation version 2.
12 *
13 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
14 * kind, whether express or implied; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/kernel.h>
20#include <linux/types.h>
21#include <linux/errno.h>
22#include <linux/err.h>
23#include <linux/io.h>
24
25#include <plat/common.h>
26
27#include "cm.h"
28#include "cm33xx.h"
29#include "cm-regbits-34xx.h"
30#include "cm-regbits-33xx.h"
31#include "prm33xx.h"
32
33/*
34 * CLKCTRL_IDLEST_*: possible values for the CM_*_CLKCTRL.IDLEST bitfield:
35 *
36 * 0x0 func: Module is fully functional, including OCP
37 * 0x1 trans: Module is performing transition: wakeup, or sleep, or sleep
38 * abortion
39 * 0x2 idle: Module is in Idle mode (only OCP part). It is functional if
40 * using separate functional clock
41 * 0x3 disabled: Module is disabled and cannot be accessed
42 *
43 */
44#define CLKCTRL_IDLEST_FUNCTIONAL 0x0
45#define CLKCTRL_IDLEST_INTRANSITION 0x1
46#define CLKCTRL_IDLEST_INTERFACE_IDLE 0x2
47#define CLKCTRL_IDLEST_DISABLED 0x3
48
49/* Private functions */
50
51/* Read a register in a CM instance */
52static inline u32 am33xx_cm_read_reg(s16 inst, u16 idx)
53{
54 return __raw_readl(cm_base + inst + idx);
55}
56
57/* Write into a register in a CM */
58static inline void am33xx_cm_write_reg(u32 val, s16 inst, u16 idx)
59{
60 __raw_writel(val, cm_base + inst + idx);
61}
62
63/* Read-modify-write a register in CM */
64static inline u32 am33xx_cm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx)
65{
66 u32 v;
67
68 v = am33xx_cm_read_reg(inst, idx);
69 v &= ~mask;
70 v |= bits;
71 am33xx_cm_write_reg(v, inst, idx);
72
73 return v;
74}
75
76static inline u32 am33xx_cm_set_reg_bits(u32 bits, s16 inst, s16 idx)
77{
78 return am33xx_cm_rmw_reg_bits(bits, bits, inst, idx);
79}
80
81static inline u32 am33xx_cm_clear_reg_bits(u32 bits, s16 inst, s16 idx)
82{
83 return am33xx_cm_rmw_reg_bits(bits, 0x0, inst, idx);
84}
85
86static inline u32 am33xx_cm_read_reg_bits(u16 inst, s16 idx, u32 mask)
87{
88 u32 v;
89
90 v = am33xx_cm_read_reg(inst, idx);
91 v &= mask;
92 v >>= __ffs(mask);
93
94 return v;
95}
96
97/**
98 * _clkctrl_idlest - read a CM_*_CLKCTRL register; mask & shift IDLEST bitfield
99 * @inst: CM instance register offset (*_INST macro)
100 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
101 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
102 *
103 * Return the IDLEST bitfield of a CM_*_CLKCTRL register, shifted down to
104 * bit 0.
105 */
106static u32 _clkctrl_idlest(u16 inst, s16 cdoffs, u16 clkctrl_offs)
107{
108 u32 v = am33xx_cm_read_reg(inst, clkctrl_offs);
109 v &= AM33XX_IDLEST_MASK;
110 v >>= AM33XX_IDLEST_SHIFT;
111 return v;
112}
113
114/**
115 * _is_module_ready - can module registers be accessed without causing an abort?
116 * @inst: CM instance register offset (*_INST macro)
117 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
118 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
119 *
120 * Returns true if the module's CM_*_CLKCTRL.IDLEST bitfield is either
121 * *FUNCTIONAL or *INTERFACE_IDLE; false otherwise.
122 */
123static bool _is_module_ready(u16 inst, s16 cdoffs, u16 clkctrl_offs)
124{
125 u32 v;
126
127 v = _clkctrl_idlest(inst, cdoffs, clkctrl_offs);
128
129 return (v == CLKCTRL_IDLEST_FUNCTIONAL ||
130 v == CLKCTRL_IDLEST_INTERFACE_IDLE) ? true : false;
131}
132
133/**
134 * _clktrctrl_write - write @c to a CM_CLKSTCTRL.CLKTRCTRL register bitfield
135 * @c: CLKTRCTRL register bitfield (LSB = bit 0, i.e., unshifted)
136 * @inst: CM instance register offset (*_INST macro)
137 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
138 *
139 * @c must be the unshifted value for CLKTRCTRL - i.e., this function
140 * will handle the shift itself.
141 */
142static void _clktrctrl_write(u8 c, s16 inst, u16 cdoffs)
143{
144 u32 v;
145
146 v = am33xx_cm_read_reg(inst, cdoffs);
147 v &= ~AM33XX_CLKTRCTRL_MASK;
148 v |= c << AM33XX_CLKTRCTRL_SHIFT;
149 am33xx_cm_write_reg(v, inst, cdoffs);
150}
151
152/* Public functions */
153
154/**
155 * am33xx_cm_is_clkdm_in_hwsup - is a clockdomain in hwsup idle mode?
156 * @inst: CM instance register offset (*_INST macro)
157 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
158 *
159 * Returns true if the clockdomain referred to by (@inst, @cdoffs)
160 * is in hardware-supervised idle mode, or 0 otherwise.
161 */
162bool am33xx_cm_is_clkdm_in_hwsup(s16 inst, u16 cdoffs)
163{
164 u32 v;
165
166 v = am33xx_cm_read_reg(inst, cdoffs);
167 v &= AM33XX_CLKTRCTRL_MASK;
168 v >>= AM33XX_CLKTRCTRL_SHIFT;
169
170 return (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? true : false;
171}
172
173/**
174 * am33xx_cm_clkdm_enable_hwsup - put a clockdomain in hwsup-idle mode
175 * @inst: CM instance register offset (*_INST macro)
176 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
177 *
178 * Put a clockdomain referred to by (@inst, @cdoffs) into
179 * hardware-supervised idle mode. No return value.
180 */
181void am33xx_cm_clkdm_enable_hwsup(s16 inst, u16 cdoffs)
182{
183 _clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, inst, cdoffs);
184}
185
186/**
187 * am33xx_cm_clkdm_disable_hwsup - put a clockdomain in swsup-idle mode
188 * @inst: CM instance register offset (*_INST macro)
189 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
190 *
191 * Put a clockdomain referred to by (@inst, @cdoffs) into
192 * software-supervised idle mode, i.e., controlled manually by the
193 * Linux OMAP clockdomain code. No return value.
194 */
195void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs)
196{
197 _clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, inst, cdoffs);
198}
199
200/**
201 * am33xx_cm_clkdm_force_sleep - try to put a clockdomain into idle
202 * @inst: CM instance register offset (*_INST macro)
203 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
204 *
205 * Put a clockdomain referred to by (@inst, @cdoffs) into idle
206 * No return value.
207 */
208void am33xx_cm_clkdm_force_sleep(s16 inst, u16 cdoffs)
209{
210 _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, inst, cdoffs);
211}
212
213/**
214 * am33xx_cm_clkdm_force_wakeup - try to take a clockdomain out of idle
215 * @inst: CM instance register offset (*_INST macro)
216 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
217 *
218 * Take a clockdomain referred to by (@inst, @cdoffs) out of idle,
219 * waking it up. No return value.
220 */
221void am33xx_cm_clkdm_force_wakeup(s16 inst, u16 cdoffs)
222{
223 _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, inst, cdoffs);
224}
225
226/*
227 *
228 */
229
230/**
231 * am33xx_cm_wait_module_ready - wait for a module to be in 'func' state
232 * @inst: CM instance register offset (*_INST macro)
233 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
234 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
235 *
236 * Wait for the module IDLEST to be functional. If the idle state is in any
237 * the non functional state (trans, idle or disabled), module and thus the
238 * sysconfig cannot be accessed and will probably lead to an "imprecise
239 * external abort"
240 */
241int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs, u16 clkctrl_offs)
242{
243 int i = 0;
244
245 if (!clkctrl_offs)
246 return 0;
247
248 omap_test_timeout(_is_module_ready(inst, cdoffs, clkctrl_offs),
249 MAX_MODULE_READY_TIME, i);
250
251 return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
252}
253
254/**
255 * am33xx_cm_wait_module_idle - wait for a module to be in 'disabled'
256 * state
257 * @inst: CM instance register offset (*_INST macro)
258 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
259 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
260 *
261 * Wait for the module IDLEST to be disabled. Some PRCM transition,
262 * like reset assertion or parent clock de-activation must wait the
263 * module to be fully disabled.
264 */
265int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs, u16 clkctrl_offs)
266{
267 int i = 0;
268
269 if (!clkctrl_offs)
270 return 0;
271
272 omap_test_timeout((_clkctrl_idlest(inst, cdoffs, clkctrl_offs) ==
273 CLKCTRL_IDLEST_DISABLED),
274 MAX_MODULE_READY_TIME, i);
275
276 return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
277}
278
279/**
280 * am33xx_cm_module_enable - Enable the modulemode inside CLKCTRL
281 * @mode: Module mode (SW or HW)
282 * @inst: CM instance register offset (*_INST macro)
283 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
284 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
285 *
286 * No return value.
287 */
288void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs, u16 clkctrl_offs)
289{
290 u32 v;
291
292 v = am33xx_cm_read_reg(inst, clkctrl_offs);
293 v &= ~AM33XX_MODULEMODE_MASK;
294 v |= mode << AM33XX_MODULEMODE_SHIFT;
295 am33xx_cm_write_reg(v, inst, clkctrl_offs);
296}
297
298/**
299 * am33xx_cm_module_disable - Disable the module inside CLKCTRL
300 * @inst: CM instance register offset (*_INST macro)
301 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
302 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
303 *
304 * No return value.
305 */
306void am33xx_cm_module_disable(u16 inst, s16 cdoffs, u16 clkctrl_offs)
307{
308 u32 v;
309
310 v = am33xx_cm_read_reg(inst, clkctrl_offs);
311 v &= ~AM33XX_MODULEMODE_MASK;
312 am33xx_cm_write_reg(v, inst, clkctrl_offs);
313}
diff --git a/arch/arm/mach-omap2/cm33xx.h b/arch/arm/mach-omap2/cm33xx.h
new file mode 100644
index 00000000000..5fa0b62e1a7
--- /dev/null
+++ b/arch/arm/mach-omap2/cm33xx.h
@@ -0,0 +1,420 @@
1/*
2 * AM33XX CM offset macros
3 *
4 * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
5 * Vaibhav Hiremath <hvaibhav@ti.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#ifndef __ARCH_ARM_MACH_OMAP2_CM_33XX_H
18#define __ARCH_ARM_MACH_OMAP2_CM_33XX_H
19
20#include <linux/delay.h>
21#include <linux/errno.h>
22#include <linux/err.h>
23#include <linux/io.h>
24
25#include "common.h"
26
27#include "cm.h"
28#include "cm-regbits-33xx.h"
29#include "cm33xx.h"
30
31/* CM base address */
32#define AM33XX_CM_BASE 0x44e00000
33
34#define AM33XX_CM_REGADDR(inst, reg) \
35 AM33XX_L4_WK_IO_ADDRESS(AM33XX_CM_BASE + (inst) + (reg))
36
37/* CM instances */
38#define AM33XX_CM_PER_MOD 0x0000
39#define AM33XX_CM_WKUP_MOD 0x0400
40#define AM33XX_CM_DPLL_MOD 0x0500
41#define AM33XX_CM_MPU_MOD 0x0600
42#define AM33XX_CM_DEVICE_MOD 0x0700
43#define AM33XX_CM_RTC_MOD 0x0800
44#define AM33XX_CM_GFX_MOD 0x0900
45#define AM33XX_CM_CEFUSE_MOD 0x0A00
46
47/* CM */
48
49/* CM.PER_CM register offsets */
50#define AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET 0x0000
51#define AM33XX_CM_PER_L4LS_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0000)
52#define AM33XX_CM_PER_L3S_CLKSTCTRL_OFFSET 0x0004
53#define AM33XX_CM_PER_L3S_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0004)
54#define AM33XX_CM_PER_L4FW_CLKSTCTRL_OFFSET 0x0008
55#define AM33XX_CM_PER_L4FW_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0008)
56#define AM33XX_CM_PER_L3_CLKSTCTRL_OFFSET 0x000c
57#define AM33XX_CM_PER_L3_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x000c)
58#define AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET 0x0014
59#define AM33XX_CM_PER_CPGMAC0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0014)
60#define AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET 0x0018
61#define AM33XX_CM_PER_LCDC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0018)
62#define AM33XX_CM_PER_USB0_CLKCTRL_OFFSET 0x001c
63#define AM33XX_CM_PER_USB0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x001c)
64#define AM33XX_CM_PER_MLB_CLKCTRL_OFFSET 0x0020
65#define AM33XX_CM_PER_MLB_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0020)
66#define AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET 0x0024
67#define AM33XX_CM_PER_TPTC0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0024)
68#define AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET 0x0028
69#define AM33XX_CM_PER_EMIF_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0028)
70#define AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET 0x002c
71#define AM33XX_CM_PER_OCMCRAM_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x002c)
72#define AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET 0x0030
73#define AM33XX_CM_PER_GPMC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0030)
74#define AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET 0x0034
75#define AM33XX_CM_PER_MCASP0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0034)
76#define AM33XX_CM_PER_UART5_CLKCTRL_OFFSET 0x0038
77#define AM33XX_CM_PER_UART5_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0038)
78#define AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET 0x003c
79#define AM33XX_CM_PER_MMC0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x003c)
80#define AM33XX_CM_PER_ELM_CLKCTRL_OFFSET 0x0040
81#define AM33XX_CM_PER_ELM_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0040)
82#define AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET 0x0044
83#define AM33XX_CM_PER_I2C2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0044)
84#define AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET 0x0048
85#define AM33XX_CM_PER_I2C1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0048)
86#define AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET 0x004c
87#define AM33XX_CM_PER_SPI0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x004c)
88#define AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET 0x0050
89#define AM33XX_CM_PER_SPI1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0050)
90#define AM33XX_CM_PER_SPI2_CLKCTRL_OFFSET 0x0054
91#define AM33XX_CM_PER_SPI2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0054)
92#define AM33XX_CM_PER_SPI3_CLKCTRL_OFFSET 0x0058
93#define AM33XX_CM_PER_SPI3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0058)
94#define AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET 0x0060
95#define AM33XX_CM_PER_L4LS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0060)
96#define AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET 0x0064
97#define AM33XX_CM_PER_L4FW_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0064)
98#define AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET 0x0068
99#define AM33XX_CM_PER_MCASP1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0068)
100#define AM33XX_CM_PER_UART1_CLKCTRL_OFFSET 0x006c
101#define AM33XX_CM_PER_UART1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x006c)
102#define AM33XX_CM_PER_UART2_CLKCTRL_OFFSET 0x0070
103#define AM33XX_CM_PER_UART2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0070)
104#define AM33XX_CM_PER_UART3_CLKCTRL_OFFSET 0x0074
105#define AM33XX_CM_PER_UART3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0074)
106#define AM33XX_CM_PER_UART4_CLKCTRL_OFFSET 0x0078
107#define AM33XX_CM_PER_UART4_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0078)
108#define AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET 0x007c
109#define AM33XX_CM_PER_TIMER7_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x007c)
110#define AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET 0x0080
111#define AM33XX_CM_PER_TIMER2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0080)
112#define AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET 0x0084
113#define AM33XX_CM_PER_TIMER3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0084)
114#define AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET 0x0088
115#define AM33XX_CM_PER_TIMER4_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0088)
116#define AM33XX_CM_PER_MCASP2_CLKCTRL_OFFSET 0x008c
117#define AM33XX_CM_PER_MCASP2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x008c)
118#define AM33XX_CM_PER_RNG_CLKCTRL_OFFSET 0x0090
119#define AM33XX_CM_PER_RNG_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0090)
120#define AM33XX_CM_PER_AES0_CLKCTRL_OFFSET 0x0094
121#define AM33XX_CM_PER_AES0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0094)
122#define AM33XX_CM_PER_AES1_CLKCTRL_OFFSET 0x0098
123#define AM33XX_CM_PER_AES1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0098)
124#define AM33XX_CM_PER_DES_CLKCTRL_OFFSET 0x009c
125#define AM33XX_CM_PER_DES_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x009c)
126#define AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET 0x00a0
127#define AM33XX_CM_PER_SHA0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a0)
128#define AM33XX_CM_PER_PKA_CLKCTRL_OFFSET 0x00a4
129#define AM33XX_CM_PER_PKA_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a4)
130#define AM33XX_CM_PER_GPIO6_CLKCTRL_OFFSET 0x00a8
131#define AM33XX_CM_PER_GPIO6_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a8)
132#define AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET 0x00ac
133#define AM33XX_CM_PER_GPIO1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00ac)
134#define AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET 0x00b0
135#define AM33XX_CM_PER_GPIO2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b0)
136#define AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET 0x00b4
137#define AM33XX_CM_PER_GPIO3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b4)
138#define AM33XX_CM_PER_GPIO4_CLKCTRL_OFFSET 0x00b8
139#define AM33XX_CM_PER_GPIO4_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b8)
140#define AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET 0x00bc
141#define AM33XX_CM_PER_TPCC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00bc)
142#define AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET 0x00c0
143#define AM33XX_CM_PER_DCAN0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00c0)
144#define AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET 0x00c4
145#define AM33XX_CM_PER_DCAN1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00c4)
146#define AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET 0x00cc
147#define AM33XX_CM_PER_EPWMSS1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00cc)
148#define AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET 0x00d0
149#define AM33XX_CM_PER_EMIF_FW_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d0)
150#define AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET 0x00d4
151#define AM33XX_CM_PER_EPWMSS0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d4)
152#define AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET 0x00d8
153#define AM33XX_CM_PER_EPWMSS2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d8)
154#define AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET 0x00dc
155#define AM33XX_CM_PER_L3_INSTR_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00dc)
156#define AM33XX_CM_PER_L3_CLKCTRL_OFFSET 0x00e0
157#define AM33XX_CM_PER_L3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e0)
158#define AM33XX_CM_PER_IEEE5000_CLKCTRL_OFFSET 0x00e4
159#define AM33XX_CM_PER_IEEE5000_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e4)
160#define AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET 0x00e8
161#define AM33XX_CM_PER_PRUSS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e8)
162#define AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET 0x00ec
163#define AM33XX_CM_PER_TIMER5_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00ec)
164#define AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET 0x00f0
165#define AM33XX_CM_PER_TIMER6_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f0)
166#define AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET 0x00f4
167#define AM33XX_CM_PER_MMC1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f4)
168#define AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET 0x00f8
169#define AM33XX_CM_PER_MMC2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f8)
170#define AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET 0x00fc
171#define AM33XX_CM_PER_TPTC1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00fc)
172#define AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET 0x0100
173#define AM33XX_CM_PER_TPTC2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0100)
174#define AM33XX_CM_PER_GPIO5_CLKCTRL_OFFSET 0x0104
175#define AM33XX_CM_PER_GPIO5_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0104)
176#define AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET 0x010c
177#define AM33XX_CM_PER_SPINLOCK_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x010c)
178#define AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET 0x0110
179#define AM33XX_CM_PER_MAILBOX0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0110)
180#define AM33XX_CM_PER_L4HS_CLKSTCTRL_OFFSET 0x011c
181#define AM33XX_CM_PER_L4HS_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x011c)
182#define AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET 0x0120
183#define AM33XX_CM_PER_L4HS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0120)
184#define AM33XX_CM_PER_MSTR_EXPS_CLKCTRL_OFFSET 0x0124
185#define AM33XX_CM_PER_MSTR_EXPS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0124)
186#define AM33XX_CM_PER_SLV_EXPS_CLKCTRL_OFFSET 0x0128
187#define AM33XX_CM_PER_SLV_EXPS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0128)
188#define AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL_OFFSET 0x012c
189#define AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x012c)
190#define AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET 0x0130
191#define AM33XX_CM_PER_OCPWP_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0130)
192#define AM33XX_CM_PER_MAILBOX1_CLKCTRL_OFFSET 0x0134
193#define AM33XX_CM_PER_MAILBOX1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0134)
194#define AM33XX_CM_PER_PRUSS_CLKSTCTRL_OFFSET 0x0140
195#define AM33XX_CM_PER_PRUSS_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0140)
196#define AM33XX_CM_PER_CPSW_CLKSTCTRL_OFFSET 0x0144
197#define AM33XX_CM_PER_CPSW_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0144)
198#define AM33XX_CM_PER_LCDC_CLKSTCTRL_OFFSET 0x0148
199#define AM33XX_CM_PER_LCDC_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0148)
200#define AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET 0x014c
201#define AM33XX_CM_PER_CLKDIV32K_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x014c)
202#define AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL_OFFSET 0x0150
203#define AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0150)
204
205/* CM.WKUP_CM register offsets */
206#define AM33XX_CM_WKUP_CLKSTCTRL_OFFSET 0x0000
207#define AM33XX_CM_WKUP_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0000)
208#define AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET 0x0004
209#define AM33XX_CM_WKUP_CONTROL_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0004)
210#define AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET 0x0008
211#define AM33XX_CM_WKUP_GPIO0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0008)
212#define AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET 0x000c
213#define AM33XX_CM_WKUP_L4WKUP_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x000c)
214#define AM33XX_CM_WKUP_TIMER0_CLKCTRL_OFFSET 0x0010
215#define AM33XX_CM_WKUP_TIMER0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0010)
216#define AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET 0x0014
217#define AM33XX_CM_WKUP_DEBUGSS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0014)
218#define AM33XX_CM_L3_AON_CLKSTCTRL_OFFSET 0x0018
219#define AM33XX_CM_L3_AON_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0018)
220#define AM33XX_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x001c
221#define AM33XX_CM_AUTOIDLE_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x001c)
222#define AM33XX_CM_IDLEST_DPLL_MPU_OFFSET 0x0020
223#define AM33XX_CM_IDLEST_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0020)
224#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0024
225#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0024)
226#define AM33XX_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x0028
227#define AM33XX_CM_SSC_MODFREQDIV_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0028)
228#define AM33XX_CM_CLKSEL_DPLL_MPU_OFFSET 0x002c
229#define AM33XX_CM_CLKSEL_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x002c)
230#define AM33XX_CM_AUTOIDLE_DPLL_DDR_OFFSET 0x0030
231#define AM33XX_CM_AUTOIDLE_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0030)
232#define AM33XX_CM_IDLEST_DPLL_DDR_OFFSET 0x0034
233#define AM33XX_CM_IDLEST_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0034)
234#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DDR_OFFSET 0x0038
235#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0038)
236#define AM33XX_CM_SSC_MODFREQDIV_DPLL_DDR_OFFSET 0x003c
237#define AM33XX_CM_SSC_MODFREQDIV_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x003c)
238#define AM33XX_CM_CLKSEL_DPLL_DDR_OFFSET 0x0040
239#define AM33XX_CM_CLKSEL_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0040)
240#define AM33XX_CM_AUTOIDLE_DPLL_DISP_OFFSET 0x0044
241#define AM33XX_CM_AUTOIDLE_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0044)
242#define AM33XX_CM_IDLEST_DPLL_DISP_OFFSET 0x0048
243#define AM33XX_CM_IDLEST_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0048)
244#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DISP_OFFSET 0x004c
245#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x004c)
246#define AM33XX_CM_SSC_MODFREQDIV_DPLL_DISP_OFFSET 0x0050
247#define AM33XX_CM_SSC_MODFREQDIV_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0050)
248#define AM33XX_CM_CLKSEL_DPLL_DISP_OFFSET 0x0054
249#define AM33XX_CM_CLKSEL_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0054)
250#define AM33XX_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0058
251#define AM33XX_CM_AUTOIDLE_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0058)
252#define AM33XX_CM_IDLEST_DPLL_CORE_OFFSET 0x005c
253#define AM33XX_CM_IDLEST_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x005c)
254#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0060
255#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0060)
256#define AM33XX_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x0064
257#define AM33XX_CM_SSC_MODFREQDIV_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0064)
258#define AM33XX_CM_CLKSEL_DPLL_CORE_OFFSET 0x0068
259#define AM33XX_CM_CLKSEL_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0068)
260#define AM33XX_CM_AUTOIDLE_DPLL_PER_OFFSET 0x006c
261#define AM33XX_CM_AUTOIDLE_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x006c)
262#define AM33XX_CM_IDLEST_DPLL_PER_OFFSET 0x0070
263#define AM33XX_CM_IDLEST_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0070)
264#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0074
265#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0074)
266#define AM33XX_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x0078
267#define AM33XX_CM_SSC_MODFREQDIV_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0078)
268#define AM33XX_CM_CLKDCOLDO_DPLL_PER_OFFSET 0x007c
269#define AM33XX_CM_CLKDCOLDO_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x007c)
270#define AM33XX_CM_DIV_M4_DPLL_CORE_OFFSET 0x0080
271#define AM33XX_CM_DIV_M4_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0080)
272#define AM33XX_CM_DIV_M5_DPLL_CORE_OFFSET 0x0084
273#define AM33XX_CM_DIV_M5_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0084)
274#define AM33XX_CM_CLKMODE_DPLL_MPU_OFFSET 0x0088
275#define AM33XX_CM_CLKMODE_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0088)
276#define AM33XX_CM_CLKMODE_DPLL_PER_OFFSET 0x008c
277#define AM33XX_CM_CLKMODE_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x008c)
278#define AM33XX_CM_CLKMODE_DPLL_CORE_OFFSET 0x0090
279#define AM33XX_CM_CLKMODE_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0090)
280#define AM33XX_CM_CLKMODE_DPLL_DDR_OFFSET 0x0094
281#define AM33XX_CM_CLKMODE_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0094)
282#define AM33XX_CM_CLKMODE_DPLL_DISP_OFFSET 0x0098
283#define AM33XX_CM_CLKMODE_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0098)
284#define AM33XX_CM_CLKSEL_DPLL_PERIPH_OFFSET 0x009c
285#define AM33XX_CM_CLKSEL_DPLL_PERIPH AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x009c)
286#define AM33XX_CM_DIV_M2_DPLL_DDR_OFFSET 0x00a0
287#define AM33XX_CM_DIV_M2_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a0)
288#define AM33XX_CM_DIV_M2_DPLL_DISP_OFFSET 0x00a4
289#define AM33XX_CM_DIV_M2_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a4)
290#define AM33XX_CM_DIV_M2_DPLL_MPU_OFFSET 0x00a8
291#define AM33XX_CM_DIV_M2_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a8)
292#define AM33XX_CM_DIV_M2_DPLL_PER_OFFSET 0x00ac
293#define AM33XX_CM_DIV_M2_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00ac)
294#define AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET 0x00b0
295#define AM33XX_CM_WKUP_WKUP_M3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b0)
296#define AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET 0x00b4
297#define AM33XX_CM_WKUP_UART0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b4)
298#define AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET 0x00b8
299#define AM33XX_CM_WKUP_I2C0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b8)
300#define AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET 0x00bc
301#define AM33XX_CM_WKUP_ADC_TSC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00bc)
302#define AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET 0x00c0
303#define AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c0)
304#define AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET 0x00c4
305#define AM33XX_CM_WKUP_TIMER1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c4)
306#define AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET 0x00c8
307#define AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c8)
308#define AM33XX_CM_L4_WKUP_AON_CLKSTCTRL_OFFSET 0x00cc
309#define AM33XX_CM_L4_WKUP_AON_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00cc)
310#define AM33XX_CM_WKUP_WDT0_CLKCTRL_OFFSET 0x00d0
311#define AM33XX_CM_WKUP_WDT0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d0)
312#define AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET 0x00d4
313#define AM33XX_CM_WKUP_WDT1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d4)
314#define AM33XX_CM_DIV_M6_DPLL_CORE_OFFSET 0x00d8
315#define AM33XX_CM_DIV_M6_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d8)
316
317/* CM.DPLL_CM register offsets */
318#define AM33XX_CLKSEL_TIMER7_CLK_OFFSET 0x0004
319#define AM33XX_CLKSEL_TIMER7_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0004)
320#define AM33XX_CLKSEL_TIMER2_CLK_OFFSET 0x0008
321#define AM33XX_CLKSEL_TIMER2_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0008)
322#define AM33XX_CLKSEL_TIMER3_CLK_OFFSET 0x000c
323#define AM33XX_CLKSEL_TIMER3_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x000c)
324#define AM33XX_CLKSEL_TIMER4_CLK_OFFSET 0x0010
325#define AM33XX_CLKSEL_TIMER4_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0010)
326#define AM33XX_CM_MAC_CLKSEL_OFFSET 0x0014
327#define AM33XX_CM_MAC_CLKSEL AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0014)
328#define AM33XX_CLKSEL_TIMER5_CLK_OFFSET 0x0018
329#define AM33XX_CLKSEL_TIMER5_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0018)
330#define AM33XX_CLKSEL_TIMER6_CLK_OFFSET 0x001c
331#define AM33XX_CLKSEL_TIMER6_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x001c)
332#define AM33XX_CM_CPTS_RFT_CLKSEL_OFFSET 0x0020
333#define AM33XX_CM_CPTS_RFT_CLKSEL AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0020)
334#define AM33XX_CLKSEL_TIMER1MS_CLK_OFFSET 0x0028
335#define AM33XX_CLKSEL_TIMER1MS_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0028)
336#define AM33XX_CLKSEL_GFX_FCLK_OFFSET 0x002c
337#define AM33XX_CLKSEL_GFX_FCLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x002c)
338#define AM33XX_CLKSEL_PRUSS_OCP_CLK_OFFSET 0x0030
339#define AM33XX_CLKSEL_PRUSS_OCP_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0030)
340#define AM33XX_CLKSEL_LCDC_PIXEL_CLK_OFFSET 0x0034
341#define AM33XX_CLKSEL_LCDC_PIXEL_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0034)
342#define AM33XX_CLKSEL_WDT1_CLK_OFFSET 0x0038
343#define AM33XX_CLKSEL_WDT1_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0038)
344#define AM33XX_CLKSEL_GPIO0_DBCLK_OFFSET 0x003c
345#define AM33XX_CLKSEL_GPIO0_DBCLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x003c)
346
347/* CM.MPU_CM register offsets */
348#define AM33XX_CM_MPU_CLKSTCTRL_OFFSET 0x0000
349#define AM33XX_CM_MPU_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_MPU_MOD, 0x0000)
350#define AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET 0x0004
351#define AM33XX_CM_MPU_MPU_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_MPU_MOD, 0x0004)
352
353/* CM.DEVICE_CM register offsets */
354#define AM33XX_CM_CLKOUT_CTRL_OFFSET 0x0000
355#define AM33XX_CM_CLKOUT_CTRL AM33XX_CM_REGADDR(AM33XX_CM_DEVICE_MOD, 0x0000)
356
357/* CM.RTC_CM register offsets */
358#define AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET 0x0000
359#define AM33XX_CM_RTC_RTC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_RTC_MOD, 0x0000)
360#define AM33XX_CM_RTC_CLKSTCTRL_OFFSET 0x0004
361#define AM33XX_CM_RTC_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_RTC_MOD, 0x0004)
362
363/* CM.GFX_CM register offsets */
364#define AM33XX_CM_GFX_L3_CLKSTCTRL_OFFSET 0x0000
365#define AM33XX_CM_GFX_L3_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0000)
366#define AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET 0x0004
367#define AM33XX_CM_GFX_GFX_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0004)
368#define AM33XX_CM_GFX_BITBLT_CLKCTRL_OFFSET 0x0008
369#define AM33XX_CM_GFX_BITBLT_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0008)
370#define AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1_OFFSET 0x000c
371#define AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1 AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x000c)
372#define AM33XX_CM_GFX_MMUCFG_CLKCTRL_OFFSET 0x0010
373#define AM33XX_CM_GFX_MMUCFG_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0010)
374#define AM33XX_CM_GFX_MMUDATA_CLKCTRL_OFFSET 0x0014
375#define AM33XX_CM_GFX_MMUDATA_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0014)
376
377/* CM.CEFUSE_CM register offsets */
378#define AM33XX_CM_CEFUSE_CLKSTCTRL_OFFSET 0x0000
379#define AM33XX_CM_CEFUSE_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_CEFUSE_MOD, 0x0000)
380#define AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020
381#define AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_CEFUSE_MOD, 0x0020)
382
383
384extern bool am33xx_cm_is_clkdm_in_hwsup(s16 inst, u16 cdoffs);
385extern void am33xx_cm_clkdm_enable_hwsup(s16 inst, u16 cdoffs);
386extern void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs);
387extern void am33xx_cm_clkdm_force_sleep(s16 inst, u16 cdoffs);
388extern void am33xx_cm_clkdm_force_wakeup(s16 inst, u16 cdoffs);
389
390#ifdef CONFIG_SOC_AM33XX
391extern int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs,
392 u16 clkctrl_offs);
393extern void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs,
394 u16 clkctrl_offs);
395extern void am33xx_cm_module_disable(u16 inst, s16 cdoffs,
396 u16 clkctrl_offs);
397extern int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs,
398 u16 clkctrl_offs);
399#else
400static inline int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs,
401 u16 clkctrl_offs)
402{
403 return 0;
404}
405static inline void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs,
406 u16 clkctrl_offs)
407{
408}
409static inline void am33xx_cm_module_disable(u16 inst, s16 cdoffs,
410 u16 clkctrl_offs)
411{
412}
413static inline int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs,
414 u16 clkctrl_offs)
415{
416 return 0;
417}
418#endif
419
420#endif
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index be9dfd1abe6..5d99c1b2cb4 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -120,6 +120,7 @@ extern void omap2_init_common_infrastructure(void);
120extern struct sys_timer omap2_timer; 120extern struct sys_timer omap2_timer;
121extern struct sys_timer omap3_timer; 121extern struct sys_timer omap3_timer;
122extern struct sys_timer omap3_secure_timer; 122extern struct sys_timer omap3_secure_timer;
123extern struct sys_timer omap3_am33xx_timer;
123extern struct sys_timer omap4_timer; 124extern struct sys_timer omap4_timer;
124 125
125void omap2420_init_early(void); 126void omap2420_init_early(void);
@@ -128,8 +129,10 @@ void omap3430_init_early(void);
128void omap35xx_init_early(void); 129void omap35xx_init_early(void);
129void omap3630_init_early(void); 130void omap3630_init_early(void);
130void omap3_init_early(void); /* Do not use this one */ 131void omap3_init_early(void); /* Do not use this one */
132void am33xx_init_early(void);
131void am35xx_init_early(void); 133void am35xx_init_early(void);
132void ti81xx_init_early(void); 134void ti81xx_init_early(void);
135void am33xx_init_early(void);
133void omap4430_init_early(void); 136void omap4430_init_early(void);
134void omap3_init_late(void); /* Do not use this one */ 137void omap3_init_late(void); /* Do not use this one */
135void omap4430_init_late(void); 138void omap4430_init_late(void);
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 08e674bb041..3223b81e753 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -241,6 +241,49 @@ void omap3_ctrl_write_boot_mode(u8 bootmode)
241 241
242#endif 242#endif
243 243
244/**
245 * omap_ctrl_write_dsp_boot_addr - set boot address for a remote processor
246 * @bootaddr: physical address of the boot loader
247 *
248 * Set boot address for the boot loader of a supported processor
249 * when a power ON sequence occurs.
250 */
251void omap_ctrl_write_dsp_boot_addr(u32 bootaddr)
252{
253 u32 offset = cpu_is_omap243x() ? OMAP243X_CONTROL_IVA2_BOOTADDR :
254 cpu_is_omap34xx() ? OMAP343X_CONTROL_IVA2_BOOTADDR :
255 cpu_is_omap44xx() ? OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR :
256 0;
257
258 if (!offset) {
259 pr_err("%s: unsupported omap type\n", __func__);
260 return;
261 }
262
263 omap_ctrl_writel(bootaddr, offset);
264}
265
266/**
267 * omap_ctrl_write_dsp_boot_mode - set boot mode for a remote processor
268 * @bootmode: 8-bit value to pass to some boot code
269 *
270 * Sets boot mode for the boot loader of a supported processor
271 * when a power ON sequence occurs.
272 */
273void omap_ctrl_write_dsp_boot_mode(u8 bootmode)
274{
275 u32 offset = cpu_is_omap243x() ? OMAP243X_CONTROL_IVA2_BOOTMOD :
276 cpu_is_omap34xx() ? OMAP343X_CONTROL_IVA2_BOOTMOD :
277 0;
278
279 if (!offset) {
280 pr_err("%s: unsupported omap type\n", __func__);
281 return;
282 }
283
284 omap_ctrl_writel(bootmode, offset);
285}
286
244#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) 287#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
245/* 288/*
246 * Clears the scratchpad contents in case of cold boot- 289 * Clears the scratchpad contents in case of cold boot-
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index a406fd045ce..5baf305386e 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -21,6 +21,8 @@
21#include <mach/ctrl_module_pad_core_44xx.h> 21#include <mach/ctrl_module_pad_core_44xx.h>
22#include <mach/ctrl_module_pad_wkup_44xx.h> 22#include <mach/ctrl_module_pad_wkup_44xx.h>
23 23
24#include <plat/am33xx.h>
25
24#ifndef __ASSEMBLY__ 26#ifndef __ASSEMBLY__
25#define OMAP242X_CTRL_REGADDR(reg) \ 27#define OMAP242X_CTRL_REGADDR(reg) \
26 OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) 28 OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
@@ -28,6 +30,8 @@
28 OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) 30 OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
29#define OMAP343X_CTRL_REGADDR(reg) \ 31#define OMAP343X_CTRL_REGADDR(reg) \
30 OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) 32 OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
33#define AM33XX_CTRL_REGADDR(reg) \
34 AM33XX_L4_WK_IO_ADDRESS(AM33XX_SCM_BASE + (reg))
31#else 35#else
32#define OMAP242X_CTRL_REGADDR(reg) \ 36#define OMAP242X_CTRL_REGADDR(reg) \
33 OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) 37 OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
@@ -35,6 +39,8 @@
35 OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) 39 OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
36#define OMAP343X_CTRL_REGADDR(reg) \ 40#define OMAP343X_CTRL_REGADDR(reg) \
37 OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) 41 OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
42#define AM33XX_CTRL_REGADDR(reg) \
43 AM33XX_L4_WK_IO_ADDRESS(AM33XX_SCM_BASE + (reg))
38#endif /* __ASSEMBLY__ */ 44#endif /* __ASSEMBLY__ */
39 45
40/* 46/*
@@ -312,15 +318,15 @@
312 OMAP343X_SCRATCHPAD + reg) 318 OMAP343X_SCRATCHPAD + reg)
313 319
314/* AM35XX_CONTROL_IPSS_CLK_CTRL bits */ 320/* AM35XX_CONTROL_IPSS_CLK_CTRL bits */
315#define AM35XX_USBOTG_VBUSP_CLK_SHIFT 0 321#define AM35XX_USBOTG_VBUSP_CLK_SHIFT 0
316#define AM35XX_CPGMAC_VBUSP_CLK_SHIFT 1 322#define AM35XX_CPGMAC_VBUSP_CLK_SHIFT 1
317#define AM35XX_VPFE_VBUSP_CLK_SHIFT 2 323#define AM35XX_VPFE_VBUSP_CLK_SHIFT 2
318#define AM35XX_HECC_VBUSP_CLK_SHIFT 3 324#define AM35XX_HECC_VBUSP_CLK_SHIFT 3
319#define AM35XX_USBOTG_FCLK_SHIFT 8 325#define AM35XX_USBOTG_FCLK_SHIFT 8
320#define AM35XX_CPGMAC_FCLK_SHIFT 9 326#define AM35XX_CPGMAC_FCLK_SHIFT 9
321#define AM35XX_VPFE_FCLK_SHIFT 10 327#define AM35XX_VPFE_FCLK_SHIFT 10
322 328
323/*AM35XX CONTROL_LVL_INTR_CLEAR bits*/ 329/* AM35XX CONTROL_LVL_INTR_CLEAR bits */
324#define AM35XX_CPGMAC_C0_MISC_PULSE_CLR BIT(0) 330#define AM35XX_CPGMAC_C0_MISC_PULSE_CLR BIT(0)
325#define AM35XX_CPGMAC_C0_RX_PULSE_CLR BIT(1) 331#define AM35XX_CPGMAC_C0_RX_PULSE_CLR BIT(1)
326#define AM35XX_CPGMAC_C0_RX_THRESH_CLR BIT(2) 332#define AM35XX_CPGMAC_C0_RX_THRESH_CLR BIT(2)
@@ -330,21 +336,22 @@
330#define AM35XX_VPFE_CCDC_VD1_INT_CLR BIT(6) 336#define AM35XX_VPFE_CCDC_VD1_INT_CLR BIT(6)
331#define AM35XX_VPFE_CCDC_VD2_INT_CLR BIT(7) 337#define AM35XX_VPFE_CCDC_VD2_INT_CLR BIT(7)
332 338
333/*AM35XX CONTROL_IP_SW_RESET bits*/ 339/* AM35XX CONTROL_IP_SW_RESET bits */
334#define AM35XX_USBOTGSS_SW_RST BIT(0) 340#define AM35XX_USBOTGSS_SW_RST BIT(0)
335#define AM35XX_CPGMACSS_SW_RST BIT(1) 341#define AM35XX_CPGMACSS_SW_RST BIT(1)
336#define AM35XX_VPFE_VBUSP_SW_RST BIT(2) 342#define AM35XX_VPFE_VBUSP_SW_RST BIT(2)
337#define AM35XX_HECC_SW_RST BIT(3) 343#define AM35XX_HECC_SW_RST BIT(3)
338#define AM35XX_VPFE_PCLK_SW_RST BIT(4) 344#define AM35XX_VPFE_PCLK_SW_RST BIT(4)
339 345
340/* 346/* AM33XX CONTROL_STATUS register */
341 * CONTROL AM33XX STATUS register
342 */
343#define AM33XX_CONTROL_STATUS 0x040 347#define AM33XX_CONTROL_STATUS 0x040
348#define AM33XX_CONTROL_SEC_CLK_CTRL 0x1bc
344 349
345/* 350/* AM33XX CONTROL_STATUS bitfields (partial) */
346 * CONTROL OMAP STATUS register to identify OMAP3 features 351#define AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT 22
347 */ 352#define AM33XX_CONTROL_STATUS_SYSBOOT1_MASK (0x3 << 22)
353
354/* CONTROL OMAP STATUS register to identify OMAP3 features */
348#define OMAP3_CONTROL_OMAP_STATUS 0x044c 355#define OMAP3_CONTROL_OMAP_STATUS 0x044c
349 356
350#define OMAP3_SGX_SHIFT 13 357#define OMAP3_SGX_SHIFT 13
@@ -397,6 +404,8 @@ extern u32 omap3_arm_context[128];
397extern void omap3_control_save_context(void); 404extern void omap3_control_save_context(void);
398extern void omap3_control_restore_context(void); 405extern void omap3_control_restore_context(void);
399extern void omap3_ctrl_write_boot_mode(u8 bootmode); 406extern void omap3_ctrl_write_boot_mode(u8 bootmode);
407extern void omap_ctrl_write_dsp_boot_addr(u32 bootaddr);
408extern void omap_ctrl_write_dsp_boot_mode(u8 bootmode);
400extern void omap3630_ctrl_disable_rta(void); 409extern void omap3630_ctrl_disable_rta(void);
401extern int omap3_ctrl_save_padconf(void); 410extern int omap3_ctrl_save_padconf(void);
402#else 411#else
diff --git a/arch/arm/mach-omap2/dsp.c b/arch/arm/mach-omap2/dsp.c
index 88ffa1e645c..a636ebc16b3 100644
--- a/arch/arm/mach-omap2/dsp.c
+++ b/arch/arm/mach-omap2/dsp.c
@@ -23,6 +23,7 @@
23 23
24#include <asm/memblock.h> 24#include <asm/memblock.h>
25 25
26#include "control.h"
26#include "cm2xxx_3xxx.h" 27#include "cm2xxx_3xxx.h"
27#include "prm2xxx_3xxx.h" 28#include "prm2xxx_3xxx.h"
28#ifdef CONFIG_BRIDGE_DVFS 29#ifdef CONFIG_BRIDGE_DVFS
@@ -46,6 +47,9 @@ static struct omap_dsp_platform_data omap_dsp_pdata __initdata = {
46 .dsp_cm_read = omap2_cm_read_mod_reg, 47 .dsp_cm_read = omap2_cm_read_mod_reg,
47 .dsp_cm_write = omap2_cm_write_mod_reg, 48 .dsp_cm_write = omap2_cm_write_mod_reg,
48 .dsp_cm_rmw_bits = omap2_cm_rmw_mod_reg_bits, 49 .dsp_cm_rmw_bits = omap2_cm_rmw_mod_reg_bits,
50
51 .set_bootaddr = omap_ctrl_write_dsp_boot_addr,
52 .set_bootmode = omap_ctrl_write_dsp_boot_mode,
49}; 53};
50 54
51static phys_addr_t omap_dsp_phys_mempool_base; 55static phys_addr_t omap_dsp_phys_mempool_base;
diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h
index 2f7ac70a20d..01970824e0e 100644
--- a/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h
+++ b/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h
@@ -42,6 +42,7 @@
42#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_1 0x0268 42#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_1 0x0268
43#define OMAP4_CTRL_MODULE_CORE_STATUS 0x02c4 43#define OMAP4_CTRL_MODULE_CORE_STATUS 0x02c4
44#define OMAP4_CTRL_MODULE_CORE_DEV_CONF 0x0300 44#define OMAP4_CTRL_MODULE_CORE_DEV_CONF 0x0300
45#define OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR 0x0304
45#define OMAP4_CTRL_MODULE_CORE_LDOVBB_IVA_VOLTAGE_CTRL 0x0314 46#define OMAP4_CTRL_MODULE_CORE_LDOVBB_IVA_VOLTAGE_CTRL 0x0314
46#define OMAP4_CTRL_MODULE_CORE_LDOVBB_MPU_VOLTAGE_CTRL 0x0318 47#define OMAP4_CTRL_MODULE_CORE_LDOVBB_MPU_VOLTAGE_CTRL 0x0318
47#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_IVA_VOLTAGE_CTRL 0x0320 48#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_IVA_VOLTAGE_CTRL 0x0320
diff --git a/arch/arm/mach-omap2/include/mach/debug-macro.S b/arch/arm/mach-omap2/include/mach/debug-macro.S
index cdfc2a1f0e7..d7f844a99a7 100644
--- a/arch/arm/mach-omap2/include/mach/debug-macro.S
+++ b/arch/arm/mach-omap2/include/mach/debug-macro.S
@@ -72,6 +72,8 @@ omap_uart_lsr: .word 0
72 beq 82f @ configure UART2 72 beq 82f @ configure UART2
73 cmp \rp, #TI81XXUART3 @ ti81Xx UART offsets different 73 cmp \rp, #TI81XXUART3 @ ti81Xx UART offsets different
74 beq 83f @ configure UART3 74 beq 83f @ configure UART3
75 cmp \rp, #AM33XXUART1 @ AM33XX UART offsets different
76 beq 84f @ configure UART1
75 cmp \rp, #ZOOM_UART @ only on zoom2/3 77 cmp \rp, #ZOOM_UART @ only on zoom2/3
76 beq 95f @ configure ZOOM_UART 78 beq 95f @ configure ZOOM_UART
77 79
@@ -100,7 +102,9 @@ omap_uart_lsr: .word 0
100 b 98f 102 b 98f
10183: mov \rp, #UART_OFFSET(TI81XX_UART3_BASE) 10383: mov \rp, #UART_OFFSET(TI81XX_UART3_BASE)
102 b 98f 104 b 98f
103 10584: ldr \rp, =AM33XX_UART1_BASE
106 and \rp, \rp, #0x00ffffff
107 b 97f
10495: ldr \rp, =ZOOM_UART_BASE 10895: ldr \rp, =ZOOM_UART_BASE
105 str \rp, [\tmp, #0] @ omap_uart_phys 109 str \rp, [\tmp, #0] @ omap_uart_phys
106 ldr \rp, =ZOOM_UART_VIRT 110 ldr \rp, =ZOOM_UART_VIRT
@@ -109,6 +113,17 @@ omap_uart_lsr: .word 0
109 str \rp, [\tmp, #8] @ omap_uart_lsr 113 str \rp, [\tmp, #8] @ omap_uart_lsr
110 b 10b 114 b 10b
111 115
116 /* AM33XX: Store both phys and virt address for the uart */
11797: add \rp, \rp, #0x44000000 @ phys base
118 str \rp, [\tmp, #0] @ omap_uart_phys
119 sub \rp, \rp, #0x44000000 @ phys base
120 add \rp, \rp, #0xf9000000 @ virt base
121 str \rp, [\tmp, #4] @ omap_uart_virt
122 mov \rp, #(UART_LSR << OMAP_PORT_SHIFT)
123 str \rp, [\tmp, #8] @ omap_uart_lsr
124
125 b 10b
126
112 /* Store both phys and virt address for the uart */ 127 /* Store both phys and virt address for the uart */
11398: add \rp, \rp, #0x48000000 @ phys base 12898: add \rp, \rp, #0x48000000 @ phys base
114 str \rp, [\tmp, #0] @ omap_uart_phys 129 str \rp, [\tmp, #0] @ omap_uart_phys
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 8d014ba04ab..cb6c11cd8df 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -477,6 +477,19 @@ void __init ti81xx_init_late(void)
477} 477}
478#endif 478#endif
479 479
480#ifdef CONFIG_SOC_AM33XX
481void __init am33xx_init_early(void)
482{
483 omap2_set_globals_am33xx();
484 omap3xxx_check_revision();
485 ti81xx_check_features();
486 omap_common_init_early();
487 am33xx_voltagedomains_init();
488 am33xx_powerdomains_init();
489 am33xx_clockdomains_init();
490}
491#endif
492
480#ifdef CONFIG_ARCH_OMAP4 493#ifdef CONFIG_ARCH_OMAP4
481void __init omap4430_init_early(void) 494void __init omap4430_init_early(void)
482{ 495{
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 6038a8c84b7..d5b34febd82 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -280,7 +280,7 @@ int __init omap_intc_of_init(struct device_node *node,
280 return 0; 280 return 0;
281} 281}
282 282
283#ifdef CONFIG_ARCH_OMAP3 283#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX)
284static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)]; 284static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];
285 285
286void omap_intc_save_context(void) 286void omap_intc_save_context(void)
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 773193670ea..f97f0624bca 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -166,6 +166,31 @@
166 */ 166 */
167#define LINKS_PER_OCP_IF 2 167#define LINKS_PER_OCP_IF 2
168 168
169/**
170 * struct omap_hwmod_soc_ops - fn ptrs for some SoC-specific operations
171 * @enable_module: function to enable a module (via MODULEMODE)
172 * @disable_module: function to disable a module (via MODULEMODE)
173 *
174 * XXX Eventually this functionality will be hidden inside the PRM/CM
175 * device drivers. Until then, this should avoid huge blocks of cpu_is_*()
176 * conditionals in this code.
177 */
178struct omap_hwmod_soc_ops {
179 void (*enable_module)(struct omap_hwmod *oh);
180 int (*disable_module)(struct omap_hwmod *oh);
181 int (*wait_target_ready)(struct omap_hwmod *oh);
182 int (*assert_hardreset)(struct omap_hwmod *oh,
183 struct omap_hwmod_rst_info *ohri);
184 int (*deassert_hardreset)(struct omap_hwmod *oh,
185 struct omap_hwmod_rst_info *ohri);
186 int (*is_hardreset_asserted)(struct omap_hwmod *oh,
187 struct omap_hwmod_rst_info *ohri);
188 int (*init_clkdm)(struct omap_hwmod *oh);
189};
190
191/* soc_ops: adapts the omap_hwmod code to the currently-booted SoC */
192static struct omap_hwmod_soc_ops soc_ops;
193
169/* omap_hwmod_list contains all registered struct omap_hwmods */ 194/* omap_hwmod_list contains all registered struct omap_hwmods */
170static LIST_HEAD(omap_hwmod_list); 195static LIST_HEAD(omap_hwmod_list);
171 196
@@ -186,6 +211,9 @@ static struct omap_hwmod_link *linkspace;
186 */ 211 */
187static unsigned short free_ls, max_ls, ls_supp; 212static unsigned short free_ls, max_ls, ls_supp;
188 213
214/* inited: set to true once the hwmod code is initialized */
215static bool inited;
216
189/* Private functions */ 217/* Private functions */
190 218
191/** 219/**
@@ -771,23 +799,19 @@ static void _disable_optional_clocks(struct omap_hwmod *oh)
771} 799}
772 800
773/** 801/**
774 * _enable_module - enable CLKCTRL modulemode on OMAP4 802 * _omap4_enable_module - enable CLKCTRL modulemode on OMAP4
775 * @oh: struct omap_hwmod * 803 * @oh: struct omap_hwmod *
776 * 804 *
777 * Enables the PRCM module mode related to the hwmod @oh. 805 * Enables the PRCM module mode related to the hwmod @oh.
778 * No return value. 806 * No return value.
779 */ 807 */
780static void _enable_module(struct omap_hwmod *oh) 808static void _omap4_enable_module(struct omap_hwmod *oh)
781{ 809{
782 /* The module mode does not exist prior OMAP4 */
783 if (cpu_is_omap24xx() || cpu_is_omap34xx())
784 return;
785
786 if (!oh->clkdm || !oh->prcm.omap4.modulemode) 810 if (!oh->clkdm || !oh->prcm.omap4.modulemode)
787 return; 811 return;
788 812
789 pr_debug("omap_hwmod: %s: _enable_module: %d\n", 813 pr_debug("omap_hwmod: %s: %s: %d\n",
790 oh->name, oh->prcm.omap4.modulemode); 814 oh->name, __func__, oh->prcm.omap4.modulemode);
791 815
792 omap4_cminst_module_enable(oh->prcm.omap4.modulemode, 816 omap4_cminst_module_enable(oh->prcm.omap4.modulemode,
793 oh->clkdm->prcm_partition, 817 oh->clkdm->prcm_partition,
@@ -807,10 +831,7 @@ static void _enable_module(struct omap_hwmod *oh)
807 */ 831 */
808static int _omap4_wait_target_disable(struct omap_hwmod *oh) 832static int _omap4_wait_target_disable(struct omap_hwmod *oh)
809{ 833{
810 if (!cpu_is_omap44xx()) 834 if (!oh || !oh->clkdm)
811 return 0;
812
813 if (!oh)
814 return -EINVAL; 835 return -EINVAL;
815 836
816 if (oh->_int_flags & _HWMOD_NO_MPU_PORT) 837 if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
@@ -1285,24 +1306,20 @@ static struct omap_hwmod *_lookup(const char *name)
1285 1306
1286 return oh; 1307 return oh;
1287} 1308}
1309
1288/** 1310/**
1289 * _init_clkdm - look up a clockdomain name, store pointer in omap_hwmod 1311 * _init_clkdm - look up a clockdomain name, store pointer in omap_hwmod
1290 * @oh: struct omap_hwmod * 1312 * @oh: struct omap_hwmod *
1291 * 1313 *
1292 * Convert a clockdomain name stored in a struct omap_hwmod into a 1314 * Convert a clockdomain name stored in a struct omap_hwmod into a
1293 * clockdomain pointer, and save it into the struct omap_hwmod. 1315 * clockdomain pointer, and save it into the struct omap_hwmod.
1294 * return -EINVAL if clkdm_name does not exist or if the lookup failed. 1316 * Return -EINVAL if the clkdm_name lookup failed.
1295 */ 1317 */
1296static int _init_clkdm(struct omap_hwmod *oh) 1318static int _init_clkdm(struct omap_hwmod *oh)
1297{ 1319{
1298 if (cpu_is_omap24xx() || cpu_is_omap34xx()) 1320 if (!oh->clkdm_name)
1299 return 0; 1321 return 0;
1300 1322
1301 if (!oh->clkdm_name) {
1302 pr_warning("omap_hwmod: %s: no clkdm_name\n", oh->name);
1303 return -EINVAL;
1304 }
1305
1306 oh->clkdm = clkdm_lookup(oh->clkdm_name); 1323 oh->clkdm = clkdm_lookup(oh->clkdm_name);
1307 if (!oh->clkdm) { 1324 if (!oh->clkdm) {
1308 pr_warning("omap_hwmod: %s: could not associate to clkdm %s\n", 1325 pr_warning("omap_hwmod: %s: could not associate to clkdm %s\n",
@@ -1338,7 +1355,8 @@ static int _init_clocks(struct omap_hwmod *oh, void *data)
1338 ret |= _init_main_clk(oh); 1355 ret |= _init_main_clk(oh);
1339 ret |= _init_interface_clks(oh); 1356 ret |= _init_interface_clks(oh);
1340 ret |= _init_opt_clks(oh); 1357 ret |= _init_opt_clks(oh);
1341 ret |= _init_clkdm(oh); 1358 if (soc_ops.init_clkdm)
1359 ret |= soc_ops.init_clkdm(oh);
1342 1360
1343 if (!ret) 1361 if (!ret)
1344 oh->_state = _HWMOD_STATE_CLKS_INITED; 1362 oh->_state = _HWMOD_STATE_CLKS_INITED;
@@ -1349,53 +1367,6 @@ static int _init_clocks(struct omap_hwmod *oh, void *data)
1349} 1367}
1350 1368
1351/** 1369/**
1352 * _wait_target_ready - wait for a module to leave slave idle
1353 * @oh: struct omap_hwmod *
1354 *
1355 * Wait for a module @oh to leave slave idle. Returns 0 if the module
1356 * does not have an IDLEST bit or if the module successfully leaves
1357 * slave idle; otherwise, pass along the return value of the
1358 * appropriate *_cm*_wait_module_ready() function.
1359 */
1360static int _wait_target_ready(struct omap_hwmod *oh)
1361{
1362 struct omap_hwmod_ocp_if *os;
1363 int ret;
1364
1365 if (!oh)
1366 return -EINVAL;
1367
1368 if (oh->flags & HWMOD_NO_IDLEST)
1369 return 0;
1370
1371 os = _find_mpu_rt_port(oh);
1372 if (!os)
1373 return 0;
1374
1375 /* XXX check module SIDLEMODE */
1376
1377 /* XXX check clock enable states */
1378
1379 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1380 ret = omap2_cm_wait_module_ready(oh->prcm.omap2.module_offs,
1381 oh->prcm.omap2.idlest_reg_id,
1382 oh->prcm.omap2.idlest_idle_bit);
1383 } else if (cpu_is_omap44xx()) {
1384 if (!oh->clkdm)
1385 return -EINVAL;
1386
1387 ret = omap4_cminst_wait_module_ready(oh->clkdm->prcm_partition,
1388 oh->clkdm->cm_inst,
1389 oh->clkdm->clkdm_offs,
1390 oh->prcm.omap4.clkctrl_offs);
1391 } else {
1392 BUG();
1393 };
1394
1395 return ret;
1396}
1397
1398/**
1399 * _lookup_hardreset - fill register bit info for this hwmod/reset line 1370 * _lookup_hardreset - fill register bit info for this hwmod/reset line
1400 * @oh: struct omap_hwmod * 1371 * @oh: struct omap_hwmod *
1401 * @name: name of the reset line in the context of this hwmod 1372 * @name: name of the reset line in the context of this hwmod
@@ -1431,32 +1402,31 @@ static u8 _lookup_hardreset(struct omap_hwmod *oh, const char *name,
1431 * @oh: struct omap_hwmod * 1402 * @oh: struct omap_hwmod *
1432 * @name: name of the reset line to lookup and assert 1403 * @name: name of the reset line to lookup and assert
1433 * 1404 *
1434 * Some IP like dsp, ipu or iva contain processor that require 1405 * Some IP like dsp, ipu or iva contain processor that require an HW
1435 * an HW reset line to be assert / deassert in order to enable fully 1406 * reset line to be assert / deassert in order to enable fully the IP.
1436 * the IP. 1407 * Returns -EINVAL if @oh is null, -ENOSYS if we have no way of
1408 * asserting the hardreset line on the currently-booted SoC, or passes
1409 * along the return value from _lookup_hardreset() or the SoC's
1410 * assert_hardreset code.
1437 */ 1411 */
1438static int _assert_hardreset(struct omap_hwmod *oh, const char *name) 1412static int _assert_hardreset(struct omap_hwmod *oh, const char *name)
1439{ 1413{
1440 struct omap_hwmod_rst_info ohri; 1414 struct omap_hwmod_rst_info ohri;
1441 u8 ret; 1415 u8 ret = -EINVAL;
1442 1416
1443 if (!oh) 1417 if (!oh)
1444 return -EINVAL; 1418 return -EINVAL;
1445 1419
1420 if (!soc_ops.assert_hardreset)
1421 return -ENOSYS;
1422
1446 ret = _lookup_hardreset(oh, name, &ohri); 1423 ret = _lookup_hardreset(oh, name, &ohri);
1447 if (IS_ERR_VALUE(ret)) 1424 if (IS_ERR_VALUE(ret))
1448 return ret; 1425 return ret;
1449 1426
1450 if (cpu_is_omap24xx() || cpu_is_omap34xx()) 1427 ret = soc_ops.assert_hardreset(oh, &ohri);
1451 return omap2_prm_assert_hardreset(oh->prcm.omap2.module_offs, 1428
1452 ohri.rst_shift); 1429 return ret;
1453 else if (cpu_is_omap44xx())
1454 return omap4_prminst_assert_hardreset(ohri.rst_shift,
1455 oh->clkdm->pwrdm.ptr->prcm_partition,
1456 oh->clkdm->pwrdm.ptr->prcm_offs,
1457 oh->prcm.omap4.rstctrl_offs);
1458 else
1459 return -EINVAL;
1460} 1430}
1461 1431
1462/** 1432/**
@@ -1465,38 +1435,29 @@ static int _assert_hardreset(struct omap_hwmod *oh, const char *name)
1465 * @oh: struct omap_hwmod * 1435 * @oh: struct omap_hwmod *
1466 * @name: name of the reset line to look up and deassert 1436 * @name: name of the reset line to look up and deassert
1467 * 1437 *
1468 * Some IP like dsp, ipu or iva contain processor that require 1438 * Some IP like dsp, ipu or iva contain processor that require an HW
1469 * an HW reset line to be assert / deassert in order to enable fully 1439 * reset line to be assert / deassert in order to enable fully the IP.
1470 * the IP. 1440 * Returns -EINVAL if @oh is null, -ENOSYS if we have no way of
1441 * deasserting the hardreset line on the currently-booted SoC, or passes
1442 * along the return value from _lookup_hardreset() or the SoC's
1443 * deassert_hardreset code.
1471 */ 1444 */
1472static int _deassert_hardreset(struct omap_hwmod *oh, const char *name) 1445static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
1473{ 1446{
1474 struct omap_hwmod_rst_info ohri; 1447 struct omap_hwmod_rst_info ohri;
1475 int ret; 1448 int ret = -EINVAL;
1476 1449
1477 if (!oh) 1450 if (!oh)
1478 return -EINVAL; 1451 return -EINVAL;
1479 1452
1453 if (!soc_ops.deassert_hardreset)
1454 return -ENOSYS;
1455
1480 ret = _lookup_hardreset(oh, name, &ohri); 1456 ret = _lookup_hardreset(oh, name, &ohri);
1481 if (IS_ERR_VALUE(ret)) 1457 if (IS_ERR_VALUE(ret))
1482 return ret; 1458 return ret;
1483 1459
1484 if (cpu_is_omap24xx() || cpu_is_omap34xx()) { 1460 ret = soc_ops.deassert_hardreset(oh, &ohri);
1485 ret = omap2_prm_deassert_hardreset(oh->prcm.omap2.module_offs,
1486 ohri.rst_shift,
1487 ohri.st_shift);
1488 } else if (cpu_is_omap44xx()) {
1489 if (ohri.st_shift)
1490 pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n",
1491 oh->name, name);
1492 ret = omap4_prminst_deassert_hardreset(ohri.rst_shift,
1493 oh->clkdm->pwrdm.ptr->prcm_partition,
1494 oh->clkdm->pwrdm.ptr->prcm_offs,
1495 oh->prcm.omap4.rstctrl_offs);
1496 } else {
1497 return -EINVAL;
1498 }
1499
1500 if (ret == -EBUSY) 1461 if (ret == -EBUSY)
1501 pr_warning("omap_hwmod: %s: failed to hardreset\n", oh->name); 1462 pr_warning("omap_hwmod: %s: failed to hardreset\n", oh->name);
1502 1463
@@ -1509,31 +1470,28 @@ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
1509 * @oh: struct omap_hwmod * 1470 * @oh: struct omap_hwmod *
1510 * @name: name of the reset line to look up and read 1471 * @name: name of the reset line to look up and read
1511 * 1472 *
1512 * Return the state of the reset line. 1473 * Return the state of the reset line. Returns -EINVAL if @oh is
1474 * null, -ENOSYS if we have no way of reading the hardreset line
1475 * status on the currently-booted SoC, or passes along the return
1476 * value from _lookup_hardreset() or the SoC's is_hardreset_asserted
1477 * code.
1513 */ 1478 */
1514static int _read_hardreset(struct omap_hwmod *oh, const char *name) 1479static int _read_hardreset(struct omap_hwmod *oh, const char *name)
1515{ 1480{
1516 struct omap_hwmod_rst_info ohri; 1481 struct omap_hwmod_rst_info ohri;
1517 u8 ret; 1482 u8 ret = -EINVAL;
1518 1483
1519 if (!oh) 1484 if (!oh)
1520 return -EINVAL; 1485 return -EINVAL;
1521 1486
1487 if (!soc_ops.is_hardreset_asserted)
1488 return -ENOSYS;
1489
1522 ret = _lookup_hardreset(oh, name, &ohri); 1490 ret = _lookup_hardreset(oh, name, &ohri);
1523 if (IS_ERR_VALUE(ret)) 1491 if (IS_ERR_VALUE(ret))
1524 return ret; 1492 return ret;
1525 1493
1526 if (cpu_is_omap24xx() || cpu_is_omap34xx()) { 1494 return soc_ops.is_hardreset_asserted(oh, &ohri);
1527 return omap2_prm_is_hardreset_asserted(oh->prcm.omap2.module_offs,
1528 ohri.st_shift);
1529 } else if (cpu_is_omap44xx()) {
1530 return omap4_prminst_is_hardreset_asserted(ohri.rst_shift,
1531 oh->clkdm->pwrdm.ptr->prcm_partition,
1532 oh->clkdm->pwrdm.ptr->prcm_offs,
1533 oh->prcm.omap4.rstctrl_offs);
1534 } else {
1535 return -EINVAL;
1536 }
1537} 1495}
1538 1496
1539/** 1497/**
@@ -1571,10 +1529,6 @@ static int _omap4_disable_module(struct omap_hwmod *oh)
1571{ 1529{
1572 int v; 1530 int v;
1573 1531
1574 /* The module mode does not exist prior OMAP4 */
1575 if (!cpu_is_omap44xx())
1576 return -EINVAL;
1577
1578 if (!oh->clkdm || !oh->prcm.omap4.modulemode) 1532 if (!oh->clkdm || !oh->prcm.omap4.modulemode)
1579 return -EINVAL; 1533 return -EINVAL;
1580 1534
@@ -1814,9 +1768,11 @@ static int _enable(struct omap_hwmod *oh)
1814 } 1768 }
1815 1769
1816 _enable_clocks(oh); 1770 _enable_clocks(oh);
1817 _enable_module(oh); 1771 if (soc_ops.enable_module)
1772 soc_ops.enable_module(oh);
1818 1773
1819 r = _wait_target_ready(oh); 1774 r = (soc_ops.wait_target_ready) ? soc_ops.wait_target_ready(oh) :
1775 -EINVAL;
1820 if (!r) { 1776 if (!r) {
1821 /* 1777 /*
1822 * Set the clockdomain to HW_AUTO only if the target is ready, 1778 * Set the clockdomain to HW_AUTO only if the target is ready,
@@ -1870,7 +1826,8 @@ static int _idle(struct omap_hwmod *oh)
1870 _idle_sysc(oh); 1826 _idle_sysc(oh);
1871 _del_initiator_dep(oh, mpu_oh); 1827 _del_initiator_dep(oh, mpu_oh);
1872 1828
1873 _omap4_disable_module(oh); 1829 if (soc_ops.disable_module)
1830 soc_ops.disable_module(oh);
1874 1831
1875 /* 1832 /*
1876 * The module must be in idle mode before disabling any parents 1833 * The module must be in idle mode before disabling any parents
@@ -1975,7 +1932,8 @@ static int _shutdown(struct omap_hwmod *oh)
1975 if (oh->_state == _HWMOD_STATE_ENABLED) { 1932 if (oh->_state == _HWMOD_STATE_ENABLED) {
1976 _del_initiator_dep(oh, mpu_oh); 1933 _del_initiator_dep(oh, mpu_oh);
1977 /* XXX what about the other system initiators here? dma, dsp */ 1934 /* XXX what about the other system initiators here? dma, dsp */
1978 _omap4_disable_module(oh); 1935 if (soc_ops.disable_module)
1936 soc_ops.disable_module(oh);
1979 _disable_clocks(oh); 1937 _disable_clocks(oh);
1980 if (oh->clkdm) 1938 if (oh->clkdm)
1981 clkdm_hwmod_disable(oh->clkdm, oh); 1939 clkdm_hwmod_disable(oh->clkdm, oh);
@@ -2431,6 +2389,194 @@ static int __init _alloc_linkspace(struct omap_hwmod_ocp_if **ois)
2431 return 0; 2389 return 0;
2432} 2390}
2433 2391
2392/* Static functions intended only for use in soc_ops field function pointers */
2393
2394/**
2395 * _omap2_wait_target_ready - wait for a module to leave slave idle
2396 * @oh: struct omap_hwmod *
2397 *
2398 * Wait for a module @oh to leave slave idle. Returns 0 if the module
2399 * does not have an IDLEST bit or if the module successfully leaves
2400 * slave idle; otherwise, pass along the return value of the
2401 * appropriate *_cm*_wait_module_ready() function.
2402 */
2403static int _omap2_wait_target_ready(struct omap_hwmod *oh)
2404{
2405 if (!oh)
2406 return -EINVAL;
2407
2408 if (oh->flags & HWMOD_NO_IDLEST)
2409 return 0;
2410
2411 if (!_find_mpu_rt_port(oh))
2412 return 0;
2413
2414 /* XXX check module SIDLEMODE, hardreset status, enabled clocks */
2415
2416 return omap2_cm_wait_module_ready(oh->prcm.omap2.module_offs,
2417 oh->prcm.omap2.idlest_reg_id,
2418 oh->prcm.omap2.idlest_idle_bit);
2419}
2420
2421/**
2422 * _omap4_wait_target_ready - wait for a module to leave slave idle
2423 * @oh: struct omap_hwmod *
2424 *
2425 * Wait for a module @oh to leave slave idle. Returns 0 if the module
2426 * does not have an IDLEST bit or if the module successfully leaves
2427 * slave idle; otherwise, pass along the return value of the
2428 * appropriate *_cm*_wait_module_ready() function.
2429 */
2430static int _omap4_wait_target_ready(struct omap_hwmod *oh)
2431{
2432 if (!oh || !oh->clkdm)
2433 return -EINVAL;
2434
2435 if (oh->flags & HWMOD_NO_IDLEST)
2436 return 0;
2437
2438 if (!_find_mpu_rt_port(oh))
2439 return 0;
2440
2441 /* XXX check module SIDLEMODE, hardreset status */
2442
2443 return omap4_cminst_wait_module_ready(oh->clkdm->prcm_partition,
2444 oh->clkdm->cm_inst,
2445 oh->clkdm->clkdm_offs,
2446 oh->prcm.omap4.clkctrl_offs);
2447}
2448
2449/**
2450 * _omap2_assert_hardreset - call OMAP2 PRM hardreset fn with hwmod args
2451 * @oh: struct omap_hwmod * to assert hardreset
2452 * @ohri: hardreset line data
2453 *
2454 * Call omap2_prm_assert_hardreset() with parameters extracted from
2455 * the hwmod @oh and the hardreset line data @ohri. Only intended for
2456 * use as an soc_ops function pointer. Passes along the return value
2457 * from omap2_prm_assert_hardreset(). XXX This function is scheduled
2458 * for removal when the PRM code is moved into drivers/.
2459 */
2460static int _omap2_assert_hardreset(struct omap_hwmod *oh,
2461 struct omap_hwmod_rst_info *ohri)
2462{
2463 return omap2_prm_assert_hardreset(oh->prcm.omap2.module_offs,
2464 ohri->rst_shift);
2465}
2466
2467/**
2468 * _omap2_deassert_hardreset - call OMAP2 PRM hardreset fn with hwmod args
2469 * @oh: struct omap_hwmod * to deassert hardreset
2470 * @ohri: hardreset line data
2471 *
2472 * Call omap2_prm_deassert_hardreset() with parameters extracted from
2473 * the hwmod @oh and the hardreset line data @ohri. Only intended for
2474 * use as an soc_ops function pointer. Passes along the return value
2475 * from omap2_prm_deassert_hardreset(). XXX This function is
2476 * scheduled for removal when the PRM code is moved into drivers/.
2477 */
2478static int _omap2_deassert_hardreset(struct omap_hwmod *oh,
2479 struct omap_hwmod_rst_info *ohri)
2480{
2481 return omap2_prm_deassert_hardreset(oh->prcm.omap2.module_offs,
2482 ohri->rst_shift,
2483 ohri->st_shift);
2484}
2485
2486/**
2487 * _omap2_is_hardreset_asserted - call OMAP2 PRM hardreset fn with hwmod args
2488 * @oh: struct omap_hwmod * to test hardreset
2489 * @ohri: hardreset line data
2490 *
2491 * Call omap2_prm_is_hardreset_asserted() with parameters extracted
2492 * from the hwmod @oh and the hardreset line data @ohri. Only
2493 * intended for use as an soc_ops function pointer. Passes along the
2494 * return value from omap2_prm_is_hardreset_asserted(). XXX This
2495 * function is scheduled for removal when the PRM code is moved into
2496 * drivers/.
2497 */
2498static int _omap2_is_hardreset_asserted(struct omap_hwmod *oh,
2499 struct omap_hwmod_rst_info *ohri)
2500{
2501 return omap2_prm_is_hardreset_asserted(oh->prcm.omap2.module_offs,
2502 ohri->st_shift);
2503}
2504
2505/**
2506 * _omap4_assert_hardreset - call OMAP4 PRM hardreset fn with hwmod args
2507 * @oh: struct omap_hwmod * to assert hardreset
2508 * @ohri: hardreset line data
2509 *
2510 * Call omap4_prminst_assert_hardreset() with parameters extracted
2511 * from the hwmod @oh and the hardreset line data @ohri. Only
2512 * intended for use as an soc_ops function pointer. Passes along the
2513 * return value from omap4_prminst_assert_hardreset(). XXX This
2514 * function is scheduled for removal when the PRM code is moved into
2515 * drivers/.
2516 */
2517static int _omap4_assert_hardreset(struct omap_hwmod *oh,
2518 struct omap_hwmod_rst_info *ohri)
2519{
2520 if (!oh->clkdm)
2521 return -EINVAL;
2522
2523 return omap4_prminst_assert_hardreset(ohri->rst_shift,
2524 oh->clkdm->pwrdm.ptr->prcm_partition,
2525 oh->clkdm->pwrdm.ptr->prcm_offs,
2526 oh->prcm.omap4.rstctrl_offs);
2527}
2528
2529/**
2530 * _omap4_deassert_hardreset - call OMAP4 PRM hardreset fn with hwmod args
2531 * @oh: struct omap_hwmod * to deassert hardreset
2532 * @ohri: hardreset line data
2533 *
2534 * Call omap4_prminst_deassert_hardreset() with parameters extracted
2535 * from the hwmod @oh and the hardreset line data @ohri. Only
2536 * intended for use as an soc_ops function pointer. Passes along the
2537 * return value from omap4_prminst_deassert_hardreset(). XXX This
2538 * function is scheduled for removal when the PRM code is moved into
2539 * drivers/.
2540 */
2541static int _omap4_deassert_hardreset(struct omap_hwmod *oh,
2542 struct omap_hwmod_rst_info *ohri)
2543{
2544 if (!oh->clkdm)
2545 return -EINVAL;
2546
2547 if (ohri->st_shift)
2548 pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n",
2549 oh->name, ohri->name);
2550 return omap4_prminst_deassert_hardreset(ohri->rst_shift,
2551 oh->clkdm->pwrdm.ptr->prcm_partition,
2552 oh->clkdm->pwrdm.ptr->prcm_offs,
2553 oh->prcm.omap4.rstctrl_offs);
2554}
2555
2556/**
2557 * _omap4_is_hardreset_asserted - call OMAP4 PRM hardreset fn with hwmod args
2558 * @oh: struct omap_hwmod * to test hardreset
2559 * @ohri: hardreset line data
2560 *
2561 * Call omap4_prminst_is_hardreset_asserted() with parameters
2562 * extracted from the hwmod @oh and the hardreset line data @ohri.
2563 * Only intended for use as an soc_ops function pointer. Passes along
2564 * the return value from omap4_prminst_is_hardreset_asserted(). XXX
2565 * This function is scheduled for removal when the PRM code is moved
2566 * into drivers/.
2567 */
2568static int _omap4_is_hardreset_asserted(struct omap_hwmod *oh,
2569 struct omap_hwmod_rst_info *ohri)
2570{
2571 if (!oh->clkdm)
2572 return -EINVAL;
2573
2574 return omap4_prminst_is_hardreset_asserted(ohri->rst_shift,
2575 oh->clkdm->pwrdm.ptr->prcm_partition,
2576 oh->clkdm->pwrdm.ptr->prcm_offs,
2577 oh->prcm.omap4.rstctrl_offs);
2578}
2579
2434/* Public functions */ 2580/* Public functions */
2435 2581
2436u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs) 2582u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs)
@@ -2563,12 +2709,18 @@ int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data),
2563 * 2709 *
2564 * Intended to be called early in boot before the clock framework is 2710 * Intended to be called early in boot before the clock framework is
2565 * initialized. If @ois is not null, will register all omap_hwmods 2711 * initialized. If @ois is not null, will register all omap_hwmods
2566 * listed in @ois that are valid for this chip. Returns 0. 2712 * listed in @ois that are valid for this chip. Returns -EINVAL if
2713 * omap_hwmod_init() hasn't been called before calling this function,
2714 * -ENOMEM if the link memory area can't be allocated, or 0 upon
2715 * success.
2567 */ 2716 */
2568int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois) 2717int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois)
2569{ 2718{
2570 int r, i; 2719 int r, i;
2571 2720
2721 if (!inited)
2722 return -EINVAL;
2723
2572 if (!ois) 2724 if (!ois)
2573 return 0; 2725 return 0;
2574 2726
@@ -3401,3 +3553,32 @@ int omap_hwmod_pad_route_irq(struct omap_hwmod *oh, int pad_idx, int irq_idx)
3401 3553
3402 return 0; 3554 return 0;
3403} 3555}
3556
3557/**
3558 * omap_hwmod_init - initialize the hwmod code
3559 *
3560 * Sets up some function pointers needed by the hwmod code to operate on the
3561 * currently-booted SoC. Intended to be called once during kernel init
3562 * before any hwmods are registered. No return value.
3563 */
3564void __init omap_hwmod_init(void)
3565{
3566 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
3567 soc_ops.wait_target_ready = _omap2_wait_target_ready;
3568 soc_ops.assert_hardreset = _omap2_assert_hardreset;
3569 soc_ops.deassert_hardreset = _omap2_deassert_hardreset;
3570 soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted;
3571 } else if (cpu_is_omap44xx()) {
3572 soc_ops.enable_module = _omap4_enable_module;
3573 soc_ops.disable_module = _omap4_disable_module;
3574 soc_ops.wait_target_ready = _omap4_wait_target_ready;
3575 soc_ops.assert_hardreset = _omap4_assert_hardreset;
3576 soc_ops.deassert_hardreset = _omap4_deassert_hardreset;
3577 soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted;
3578 soc_ops.init_clkdm = _init_clkdm;
3579 } else {
3580 WARN(1, "omap_hwmod: unknown SoC type\n");
3581 }
3582
3583 inited = true;
3584}
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index a7640d1b215..50cfab61b0e 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -192,6 +192,11 @@ static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
192 .name = "mcbsp", 192 .name = "mcbsp",
193}; 193};
194 194
195static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
196 { .role = "pad_fck", .clk = "mcbsp_clks" },
197 { .role = "prcm_fck", .clk = "func_96m_ck" },
198};
199
195/* mcbsp1 */ 200/* mcbsp1 */
196static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = { 201static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = {
197 { .name = "tx", .irq = 59 }, 202 { .name = "tx", .irq = 59 },
@@ -214,6 +219,8 @@ static struct omap_hwmod omap2420_mcbsp1_hwmod = {
214 .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT, 219 .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
215 }, 220 },
216 }, 221 },
222 .opt_clks = mcbsp_opt_clks,
223 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
217}; 224};
218 225
219/* mcbsp2 */ 226/* mcbsp2 */
@@ -238,6 +245,8 @@ static struct omap_hwmod omap2420_mcbsp2_hwmod = {
238 .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT, 245 .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
239 }, 246 },
240 }, 247 },
248 .opt_clks = mcbsp_opt_clks,
249 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
241}; 250};
242 251
243static struct omap_hwmod_class_sysconfig omap2420_msdi_sysc = { 252static struct omap_hwmod_class_sysconfig omap2420_msdi_sysc = {
@@ -585,5 +594,6 @@ static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
585 594
586int __init omap2420_hwmod_init(void) 595int __init omap2420_hwmod_init(void)
587{ 596{
597 omap_hwmod_init();
588 return omap_hwmod_register_links(omap2420_hwmod_ocp_ifs); 598 return omap_hwmod_register_links(omap2420_hwmod_ocp_ifs);
589} 599}
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 4d726498123..58b5bc196d3 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -296,6 +296,11 @@ static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = {
296 .rev = MCBSP_CONFIG_TYPE2, 296 .rev = MCBSP_CONFIG_TYPE2,
297}; 297};
298 298
299static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
300 { .role = "pad_fck", .clk = "mcbsp_clks" },
301 { .role = "prcm_fck", .clk = "func_96m_ck" },
302};
303
299/* mcbsp1 */ 304/* mcbsp1 */
300static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = { 305static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = {
301 { .name = "tx", .irq = 59 }, 306 { .name = "tx", .irq = 59 },
@@ -320,6 +325,8 @@ static struct omap_hwmod omap2430_mcbsp1_hwmod = {
320 .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT, 325 .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
321 }, 326 },
322 }, 327 },
328 .opt_clks = mcbsp_opt_clks,
329 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
323}; 330};
324 331
325/* mcbsp2 */ 332/* mcbsp2 */
@@ -345,6 +352,8 @@ static struct omap_hwmod omap2430_mcbsp2_hwmod = {
345 .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT, 352 .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
346 }, 353 },
347 }, 354 },
355 .opt_clks = mcbsp_opt_clks,
356 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
348}; 357};
349 358
350/* mcbsp3 */ 359/* mcbsp3 */
@@ -370,6 +379,8 @@ static struct omap_hwmod omap2430_mcbsp3_hwmod = {
370 .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT, 379 .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT,
371 }, 380 },
372 }, 381 },
382 .opt_clks = mcbsp_opt_clks,
383 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
373}; 384};
374 385
375/* mcbsp4 */ 386/* mcbsp4 */
@@ -401,6 +412,8 @@ static struct omap_hwmod omap2430_mcbsp4_hwmod = {
401 .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT, 412 .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT,
402 }, 413 },
403 }, 414 },
415 .opt_clks = mcbsp_opt_clks,
416 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
404}; 417};
405 418
406/* mcbsp5 */ 419/* mcbsp5 */
@@ -432,6 +445,8 @@ static struct omap_hwmod omap2430_mcbsp5_hwmod = {
432 .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT, 445 .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT,
433 }, 446 },
434 }, 447 },
448 .opt_clks = mcbsp_opt_clks,
449 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
435}; 450};
436 451
437/* MMC/SD/SDIO common */ 452/* MMC/SD/SDIO common */
@@ -938,5 +953,6 @@ static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = {
938 953
939int __init omap2430_hwmod_init(void) 954int __init omap2430_hwmod_init(void)
940{ 955{
956 omap_hwmod_init();
941 return omap_hwmod_register_links(omap2430_hwmod_ocp_ifs); 957 return omap_hwmod_register_links(omap2430_hwmod_ocp_ifs);
942} 958}
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
index 83eafd96eca..afad69c6ba6 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
@@ -68,7 +68,6 @@ static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = {
68struct omap_hwmod_class omap2xxx_timer_hwmod_class = { 68struct omap_hwmod_class omap2xxx_timer_hwmod_class = {
69 .name = "timer", 69 .name = "timer",
70 .sysc = &omap2xxx_timer_sysc, 70 .sysc = &omap2xxx_timer_sysc,
71 .rev = OMAP_TIMER_IP_VERSION_1,
72}; 71};
73 72
74/* 73/*
@@ -257,7 +256,6 @@ struct omap_hwmod omap2xxx_timer2_hwmod = {
257 .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT, 256 .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
258 }, 257 },
259 }, 258 },
260 .dev_attr = &capability_alwon_dev_attr,
261 .class = &omap2xxx_timer_hwmod_class, 259 .class = &omap2xxx_timer_hwmod_class,
262}; 260};
263 261
@@ -276,7 +274,6 @@ struct omap_hwmod omap2xxx_timer3_hwmod = {
276 .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT, 274 .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
277 }, 275 },
278 }, 276 },
279 .dev_attr = &capability_alwon_dev_attr,
280 .class = &omap2xxx_timer_hwmod_class, 277 .class = &omap2xxx_timer_hwmod_class,
281}; 278};
282 279
@@ -295,7 +292,6 @@ struct omap_hwmod omap2xxx_timer4_hwmod = {
295 .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT, 292 .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
296 }, 293 },
297 }, 294 },
298 .dev_attr = &capability_alwon_dev_attr,
299 .class = &omap2xxx_timer_hwmod_class, 295 .class = &omap2xxx_timer_hwmod_class,
300}; 296};
301 297
@@ -314,7 +310,6 @@ struct omap_hwmod omap2xxx_timer5_hwmod = {
314 .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT, 310 .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
315 }, 311 },
316 }, 312 },
317 .dev_attr = &capability_alwon_dev_attr,
318 .class = &omap2xxx_timer_hwmod_class, 313 .class = &omap2xxx_timer_hwmod_class,
319}; 314};
320 315
@@ -333,7 +328,6 @@ struct omap_hwmod omap2xxx_timer6_hwmod = {
333 .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT, 328 .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
334 }, 329 },
335 }, 330 },
336 .dev_attr = &capability_alwon_dev_attr,
337 .class = &omap2xxx_timer_hwmod_class, 331 .class = &omap2xxx_timer_hwmod_class,
338}; 332};
339 333
@@ -352,7 +346,6 @@ struct omap_hwmod omap2xxx_timer7_hwmod = {
352 .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT, 346 .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
353 }, 347 },
354 }, 348 },
355 .dev_attr = &capability_alwon_dev_attr,
356 .class = &omap2xxx_timer_hwmod_class, 349 .class = &omap2xxx_timer_hwmod_class,
357}; 350};
358 351
@@ -371,7 +364,6 @@ struct omap_hwmod omap2xxx_timer8_hwmod = {
371 .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT, 364 .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
372 }, 365 },
373 }, 366 },
374 .dev_attr = &capability_alwon_dev_attr,
375 .class = &omap2xxx_timer_hwmod_class, 367 .class = &omap2xxx_timer_hwmod_class,
376}; 368};
377 369
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index b26d3c9bca1..6491e057d9c 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -129,7 +129,6 @@ static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
129static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = { 129static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
130 .name = "timer", 130 .name = "timer",
131 .sysc = &omap3xxx_timer_1ms_sysc, 131 .sysc = &omap3xxx_timer_1ms_sysc,
132 .rev = OMAP_TIMER_IP_VERSION_1,
133}; 132};
134 133
135static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = { 134static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
@@ -145,12 +144,11 @@ static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
145static struct omap_hwmod_class omap3xxx_timer_hwmod_class = { 144static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
146 .name = "timer", 145 .name = "timer",
147 .sysc = &omap3xxx_timer_sysc, 146 .sysc = &omap3xxx_timer_sysc,
148 .rev = OMAP_TIMER_IP_VERSION_1,
149}; 147};
150 148
151/* secure timers dev attribute */ 149/* secure timers dev attribute */
152static struct omap_timer_capability_dev_attr capability_secure_dev_attr = { 150static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
153 .timer_capability = OMAP_TIMER_SECURE, 151 .timer_capability = OMAP_TIMER_ALWON | OMAP_TIMER_SECURE,
154}; 152};
155 153
156/* always-on timers dev attribute */ 154/* always-on timers dev attribute */
@@ -195,7 +193,6 @@ static struct omap_hwmod omap3xxx_timer2_hwmod = {
195 .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT, 193 .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
196 }, 194 },
197 }, 195 },
198 .dev_attr = &capability_alwon_dev_attr,
199 .class = &omap3xxx_timer_1ms_hwmod_class, 196 .class = &omap3xxx_timer_1ms_hwmod_class,
200}; 197};
201 198
@@ -213,7 +210,6 @@ static struct omap_hwmod omap3xxx_timer3_hwmod = {
213 .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT, 210 .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
214 }, 211 },
215 }, 212 },
216 .dev_attr = &capability_alwon_dev_attr,
217 .class = &omap3xxx_timer_hwmod_class, 213 .class = &omap3xxx_timer_hwmod_class,
218}; 214};
219 215
@@ -231,7 +227,6 @@ static struct omap_hwmod omap3xxx_timer4_hwmod = {
231 .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT, 227 .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
232 }, 228 },
233 }, 229 },
234 .dev_attr = &capability_alwon_dev_attr,
235 .class = &omap3xxx_timer_hwmod_class, 230 .class = &omap3xxx_timer_hwmod_class,
236}; 231};
237 232
@@ -249,7 +244,6 @@ static struct omap_hwmod omap3xxx_timer5_hwmod = {
249 .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT, 244 .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
250 }, 245 },
251 }, 246 },
252 .dev_attr = &capability_alwon_dev_attr,
253 .class = &omap3xxx_timer_hwmod_class, 247 .class = &omap3xxx_timer_hwmod_class,
254}; 248};
255 249
@@ -267,7 +261,6 @@ static struct omap_hwmod omap3xxx_timer6_hwmod = {
267 .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT, 261 .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
268 }, 262 },
269 }, 263 },
270 .dev_attr = &capability_alwon_dev_attr,
271 .class = &omap3xxx_timer_hwmod_class, 264 .class = &omap3xxx_timer_hwmod_class,
272}; 265};
273 266
@@ -285,7 +278,6 @@ static struct omap_hwmod omap3xxx_timer7_hwmod = {
285 .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT, 278 .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
286 }, 279 },
287 }, 280 },
288 .dev_attr = &capability_alwon_dev_attr,
289 .class = &omap3xxx_timer_hwmod_class, 281 .class = &omap3xxx_timer_hwmod_class,
290}; 282};
291 283
@@ -1074,6 +1066,17 @@ static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
1074 .rev = MCBSP_CONFIG_TYPE3, 1066 .rev = MCBSP_CONFIG_TYPE3,
1075}; 1067};
1076 1068
1069/* McBSP functional clock mapping */
1070static struct omap_hwmod_opt_clk mcbsp15_opt_clks[] = {
1071 { .role = "pad_fck", .clk = "mcbsp_clks" },
1072 { .role = "prcm_fck", .clk = "core_96m_fck" },
1073};
1074
1075static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = {
1076 { .role = "pad_fck", .clk = "mcbsp_clks" },
1077 { .role = "prcm_fck", .clk = "per_96m_fck" },
1078};
1079
1077/* mcbsp1 */ 1080/* mcbsp1 */
1078static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = { 1081static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
1079 { .name = "common", .irq = 16 }, 1082 { .name = "common", .irq = 16 },
@@ -1097,6 +1100,8 @@ static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
1097 .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT, 1100 .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
1098 }, 1101 },
1099 }, 1102 },
1103 .opt_clks = mcbsp15_opt_clks,
1104 .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks),
1100}; 1105};
1101 1106
1102/* mcbsp2 */ 1107/* mcbsp2 */
@@ -1126,6 +1131,8 @@ static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
1126 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, 1131 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
1127 }, 1132 },
1128 }, 1133 },
1134 .opt_clks = mcbsp234_opt_clks,
1135 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
1129 .dev_attr = &omap34xx_mcbsp2_dev_attr, 1136 .dev_attr = &omap34xx_mcbsp2_dev_attr,
1130}; 1137};
1131 1138
@@ -1156,6 +1163,8 @@ static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
1156 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, 1163 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
1157 }, 1164 },
1158 }, 1165 },
1166 .opt_clks = mcbsp234_opt_clks,
1167 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
1159 .dev_attr = &omap34xx_mcbsp3_dev_attr, 1168 .dev_attr = &omap34xx_mcbsp3_dev_attr,
1160}; 1169};
1161 1170
@@ -1188,6 +1197,8 @@ static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
1188 .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT, 1197 .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
1189 }, 1198 },
1190 }, 1199 },
1200 .opt_clks = mcbsp234_opt_clks,
1201 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
1191}; 1202};
1192 1203
1193/* mcbsp5 */ 1204/* mcbsp5 */
@@ -1219,6 +1230,8 @@ static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
1219 .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT, 1230 .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
1220 }, 1231 },
1221 }, 1232 },
1233 .opt_clks = mcbsp15_opt_clks,
1234 .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks),
1222}; 1235};
1223 1236
1224/* 'mcbsp sidetone' class */ 1237/* 'mcbsp sidetone' class */
@@ -3283,6 +3296,8 @@ int __init omap3xxx_hwmod_init(void)
3283 struct omap_hwmod_ocp_if **h = NULL; 3296 struct omap_hwmod_ocp_if **h = NULL;
3284 unsigned int rev; 3297 unsigned int rev;
3285 3298
3299 omap_hwmod_init();
3300
3286 /* Register hwmod links common to all OMAP3 */ 3301 /* Register hwmod links common to all OMAP3 */
3287 r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs); 3302 r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs);
3288 if (r < 0) 3303 if (r < 0)
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index f30e861ce6d..1b1d04141c3 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -2544,14 +2544,12 @@ static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
2544static struct omap_hwmod omap44xx_cm_core_aon_hwmod = { 2544static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
2545 .name = "cm_core_aon", 2545 .name = "cm_core_aon",
2546 .class = &omap44xx_prcm_hwmod_class, 2546 .class = &omap44xx_prcm_hwmod_class,
2547 .clkdm_name = "cm_clkdm",
2548}; 2547};
2549 2548
2550/* cm_core */ 2549/* cm_core */
2551static struct omap_hwmod omap44xx_cm_core_hwmod = { 2550static struct omap_hwmod omap44xx_cm_core_hwmod = {
2552 .name = "cm_core", 2551 .name = "cm_core",
2553 .class = &omap44xx_prcm_hwmod_class, 2552 .class = &omap44xx_prcm_hwmod_class,
2554 .clkdm_name = "cm_clkdm",
2555}; 2553};
2556 2554
2557/* prm */ 2555/* prm */
@@ -2568,7 +2566,6 @@ static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
2568static struct omap_hwmod omap44xx_prm_hwmod = { 2566static struct omap_hwmod omap44xx_prm_hwmod = {
2569 .name = "prm", 2567 .name = "prm",
2570 .class = &omap44xx_prcm_hwmod_class, 2568 .class = &omap44xx_prcm_hwmod_class,
2571 .clkdm_name = "prm_clkdm",
2572 .mpu_irqs = omap44xx_prm_irqs, 2569 .mpu_irqs = omap44xx_prm_irqs,
2573 .rst_lines = omap44xx_prm_resets, 2570 .rst_lines = omap44xx_prm_resets,
2574 .rst_lines_cnt = ARRAY_SIZE(omap44xx_prm_resets), 2571 .rst_lines_cnt = ARRAY_SIZE(omap44xx_prm_resets),
@@ -2947,7 +2944,6 @@ static struct omap_hwmod omap44xx_timer2_hwmod = {
2947 .modulemode = MODULEMODE_SWCTRL, 2944 .modulemode = MODULEMODE_SWCTRL,
2948 }, 2945 },
2949 }, 2946 },
2950 .dev_attr = &capability_alwon_dev_attr,
2951}; 2947};
2952 2948
2953/* timer3 */ 2949/* timer3 */
@@ -2969,7 +2965,6 @@ static struct omap_hwmod omap44xx_timer3_hwmod = {
2969 .modulemode = MODULEMODE_SWCTRL, 2965 .modulemode = MODULEMODE_SWCTRL,
2970 }, 2966 },
2971 }, 2967 },
2972 .dev_attr = &capability_alwon_dev_attr,
2973}; 2968};
2974 2969
2975/* timer4 */ 2970/* timer4 */
@@ -2991,7 +2986,6 @@ static struct omap_hwmod omap44xx_timer4_hwmod = {
2991 .modulemode = MODULEMODE_SWCTRL, 2986 .modulemode = MODULEMODE_SWCTRL,
2992 }, 2987 },
2993 }, 2988 },
2994 .dev_attr = &capability_alwon_dev_attr,
2995}; 2989};
2996 2990
2997/* timer5 */ 2991/* timer5 */
@@ -3013,7 +3007,6 @@ static struct omap_hwmod omap44xx_timer5_hwmod = {
3013 .modulemode = MODULEMODE_SWCTRL, 3007 .modulemode = MODULEMODE_SWCTRL,
3014 }, 3008 },
3015 }, 3009 },
3016 .dev_attr = &capability_alwon_dev_attr,
3017}; 3010};
3018 3011
3019/* timer6 */ 3012/* timer6 */
@@ -3036,7 +3029,6 @@ static struct omap_hwmod omap44xx_timer6_hwmod = {
3036 .modulemode = MODULEMODE_SWCTRL, 3029 .modulemode = MODULEMODE_SWCTRL,
3037 }, 3030 },
3038 }, 3031 },
3039 .dev_attr = &capability_alwon_dev_attr,
3040}; 3032};
3041 3033
3042/* timer7 */ 3034/* timer7 */
@@ -3058,7 +3050,6 @@ static struct omap_hwmod omap44xx_timer7_hwmod = {
3058 .modulemode = MODULEMODE_SWCTRL, 3050 .modulemode = MODULEMODE_SWCTRL,
3059 }, 3051 },
3060 }, 3052 },
3061 .dev_attr = &capability_alwon_dev_attr,
3062}; 3053};
3063 3054
3064/* timer8 */ 3055/* timer8 */
@@ -6148,6 +6139,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
6148 6139
6149int __init omap44xx_hwmod_init(void) 6140int __init omap44xx_hwmod_init(void)
6150{ 6141{
6142 omap_hwmod_init();
6151 return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs); 6143 return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
6152} 6144}
6153 6145
diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
index 8f88d65c46e..a8a95184243 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -67,9 +67,9 @@
67 67
68/* 68/*
69 * Maximum number of clockdomains that can be associated with a powerdomain. 69 * Maximum number of clockdomains that can be associated with a powerdomain.
70 * CORE powerdomain on OMAP4 is the worst case 70 * PER powerdomain on AM33XX is the worst case
71 */ 71 */
72#define PWRDM_MAX_CLKDMS 9 72#define PWRDM_MAX_CLKDMS 11
73 73
74/* XXX A completely arbitrary number. What is reasonable here? */ 74/* XXX A completely arbitrary number. What is reasonable here? */
75#define PWRDM_TRANSITION_BAILOUT 100000 75#define PWRDM_TRANSITION_BAILOUT 100000
@@ -92,6 +92,15 @@ struct powerdomain;
92 * @pwrdm_clkdms: Clockdomains in this powerdomain 92 * @pwrdm_clkdms: Clockdomains in this powerdomain
93 * @node: list_head linking all powerdomains 93 * @node: list_head linking all powerdomains
94 * @voltdm_node: list_head linking all powerdomains in a voltagedomain 94 * @voltdm_node: list_head linking all powerdomains in a voltagedomain
95 * @pwrstctrl_offs: (AM33XX only) XXX_PWRSTCTRL reg offset from prcm_offs
96 * @pwrstst_offs: (AM33XX only) XXX_PWRSTST reg offset from prcm_offs
97 * @logicretstate_mask: (AM33XX only) mask for logic retention bitfield
98 * in @pwrstctrl_offs
99 * @mem_on_mask: (AM33XX only) mask for mem on bitfield in @pwrstctrl_offs
100 * @mem_ret_mask: (AM33XX only) mask for mem ret bitfield in @pwrstctrl_offs
101 * @mem_pwrst_mask: (AM33XX only) mask for mem state bitfield in @pwrstst_offs
102 * @mem_retst_mask: (AM33XX only) mask for mem retention state bitfield
103 * in @pwrstctrl_offs
95 * @state: 104 * @state:
96 * @state_counter: 105 * @state_counter:
97 * @timer: 106 * @timer:
@@ -121,6 +130,14 @@ struct powerdomain {
121 unsigned ret_logic_off_counter; 130 unsigned ret_logic_off_counter;
122 unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS]; 131 unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS];
123 132
133 const u8 pwrstctrl_offs;
134 const u8 pwrstst_offs;
135 const u32 logicretstate_mask;
136 const u32 mem_on_mask[PWRDM_MAX_MEM_BANKS];
137 const u32 mem_ret_mask[PWRDM_MAX_MEM_BANKS];
138 const u32 mem_pwrst_mask[PWRDM_MAX_MEM_BANKS];
139 const u32 mem_retst_mask[PWRDM_MAX_MEM_BANKS];
140
124#ifdef CONFIG_PM_DEBUG 141#ifdef CONFIG_PM_DEBUG
125 s64 timer; 142 s64 timer;
126 s64 state_timer[PWRDM_MAX_PWRSTS]; 143 s64 state_timer[PWRDM_MAX_PWRSTS];
@@ -222,10 +239,12 @@ bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm);
222extern void omap242x_powerdomains_init(void); 239extern void omap242x_powerdomains_init(void);
223extern void omap243x_powerdomains_init(void); 240extern void omap243x_powerdomains_init(void);
224extern void omap3xxx_powerdomains_init(void); 241extern void omap3xxx_powerdomains_init(void);
242extern void am33xx_powerdomains_init(void);
225extern void omap44xx_powerdomains_init(void); 243extern void omap44xx_powerdomains_init(void);
226 244
227extern struct pwrdm_ops omap2_pwrdm_operations; 245extern struct pwrdm_ops omap2_pwrdm_operations;
228extern struct pwrdm_ops omap3_pwrdm_operations; 246extern struct pwrdm_ops omap3_pwrdm_operations;
247extern struct pwrdm_ops am33xx_pwrdm_operations;
229extern struct pwrdm_ops omap4_pwrdm_operations; 248extern struct pwrdm_ops omap4_pwrdm_operations;
230 249
231/* Common Internal functions used across OMAP rev's */ 250/* Common Internal functions used across OMAP rev's */
diff --git a/arch/arm/mach-omap2/powerdomain33xx.c b/arch/arm/mach-omap2/powerdomain33xx.c
new file mode 100644
index 00000000000..67c5663899b
--- /dev/null
+++ b/arch/arm/mach-omap2/powerdomain33xx.c
@@ -0,0 +1,229 @@
1/*
2 * AM33XX Powerdomain control
3 *
4 * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * Derived from mach-omap2/powerdomain44xx.c written by Rajendra Nayak
7 * <rnayak@ti.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation version 2.
12 *
13 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
14 * kind, whether express or implied; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/io.h>
20#include <linux/errno.h>
21#include <linux/delay.h>
22
23#include <plat/prcm.h>
24
25#include "powerdomain.h"
26#include "prm33xx.h"
27#include "prm-regbits-33xx.h"
28
29
30static int am33xx_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
31{
32 am33xx_prm_rmw_reg_bits(OMAP_POWERSTATE_MASK,
33 (pwrst << OMAP_POWERSTATE_SHIFT),
34 pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
35 return 0;
36}
37
38static int am33xx_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
39{
40 u32 v;
41
42 v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
43 v &= OMAP_POWERSTATE_MASK;
44 v >>= OMAP_POWERSTATE_SHIFT;
45
46 return v;
47}
48
49static int am33xx_pwrdm_read_pwrst(struct powerdomain *pwrdm)
50{
51 u32 v;
52
53 v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
54 v &= OMAP_POWERSTATEST_MASK;
55 v >>= OMAP_POWERSTATEST_SHIFT;
56
57 return v;
58}
59
60static int am33xx_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
61{
62 u32 v;
63
64 v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
65 v &= AM33XX_LASTPOWERSTATEENTERED_MASK;
66 v >>= AM33XX_LASTPOWERSTATEENTERED_SHIFT;
67
68 return v;
69}
70
71static int am33xx_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
72{
73 am33xx_prm_rmw_reg_bits(AM33XX_LOWPOWERSTATECHANGE_MASK,
74 (1 << AM33XX_LOWPOWERSTATECHANGE_SHIFT),
75 pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
76 return 0;
77}
78
79static int am33xx_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
80{
81 am33xx_prm_rmw_reg_bits(AM33XX_LASTPOWERSTATEENTERED_MASK,
82 AM33XX_LASTPOWERSTATEENTERED_MASK,
83 pwrdm->prcm_offs, pwrdm->pwrstst_offs);
84 return 0;
85}
86
87static int am33xx_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
88{
89 u32 m;
90
91 m = pwrdm->logicretstate_mask;
92 if (!m)
93 return -EINVAL;
94
95 am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)),
96 pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
97
98 return 0;
99}
100
101static int am33xx_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
102{
103 u32 v;
104
105 v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
106 v &= AM33XX_LOGICSTATEST_MASK;
107 v >>= AM33XX_LOGICSTATEST_SHIFT;
108
109 return v;
110}
111
112static int am33xx_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
113{
114 u32 v, m;
115
116 m = pwrdm->logicretstate_mask;
117 if (!m)
118 return -EINVAL;
119
120 v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
121 v &= m;
122 v >>= __ffs(m);
123
124 return v;
125}
126
127static int am33xx_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
128 u8 pwrst)
129{
130 u32 m;
131
132 m = pwrdm->mem_on_mask[bank];
133 if (!m)
134 return -EINVAL;
135
136 am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)),
137 pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
138
139 return 0;
140}
141
142static int am33xx_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
143 u8 pwrst)
144{
145 u32 m;
146
147 m = pwrdm->mem_ret_mask[bank];
148 if (!m)
149 return -EINVAL;
150
151 am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)),
152 pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
153
154 return 0;
155}
156
157static int am33xx_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
158{
159 u32 m, v;
160
161 m = pwrdm->mem_pwrst_mask[bank];
162 if (!m)
163 return -EINVAL;
164
165 v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
166 v &= m;
167 v >>= __ffs(m);
168
169 return v;
170}
171
172static int am33xx_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
173{
174 u32 m, v;
175
176 m = pwrdm->mem_retst_mask[bank];
177 if (!m)
178 return -EINVAL;
179
180 v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
181 v &= m;
182 v >>= __ffs(m);
183
184 return v;
185}
186
187static int am33xx_pwrdm_wait_transition(struct powerdomain *pwrdm)
188{
189 u32 c = 0;
190
191 /*
192 * REVISIT: pwrdm_wait_transition() may be better implemented
193 * via a callback and a periodic timer check -- how long do we expect
194 * powerdomain transitions to take?
195 */
196
197 /* XXX Is this udelay() value meaningful? */
198 while ((am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs)
199 & OMAP_INTRANSITION_MASK) &&
200 (c++ < PWRDM_TRANSITION_BAILOUT))
201 udelay(1);
202
203 if (c > PWRDM_TRANSITION_BAILOUT) {
204 pr_err("powerdomain: %s: waited too long to complete transition\n",
205 pwrdm->name);
206 return -EAGAIN;
207 }
208
209 pr_debug("powerdomain: completed transition in %d loops\n", c);
210
211 return 0;
212}
213
214struct pwrdm_ops am33xx_pwrdm_operations = {
215 .pwrdm_set_next_pwrst = am33xx_pwrdm_set_next_pwrst,
216 .pwrdm_read_next_pwrst = am33xx_pwrdm_read_next_pwrst,
217 .pwrdm_read_pwrst = am33xx_pwrdm_read_pwrst,
218 .pwrdm_read_prev_pwrst = am33xx_pwrdm_read_prev_pwrst,
219 .pwrdm_set_logic_retst = am33xx_pwrdm_set_logic_retst,
220 .pwrdm_read_logic_pwrst = am33xx_pwrdm_read_logic_pwrst,
221 .pwrdm_read_logic_retst = am33xx_pwrdm_read_logic_retst,
222 .pwrdm_clear_all_prev_pwrst = am33xx_pwrdm_clear_all_prev_pwrst,
223 .pwrdm_set_lowpwrstchange = am33xx_pwrdm_set_lowpwrstchange,
224 .pwrdm_read_mem_pwrst = am33xx_pwrdm_read_mem_pwrst,
225 .pwrdm_read_mem_retst = am33xx_pwrdm_read_mem_retst,
226 .pwrdm_set_mem_onst = am33xx_pwrdm_set_mem_onst,
227 .pwrdm_set_mem_retst = am33xx_pwrdm_set_mem_retst,
228 .pwrdm_wait_transition = am33xx_pwrdm_wait_transition,
229};
diff --git a/arch/arm/mach-omap2/powerdomains33xx_data.c b/arch/arm/mach-omap2/powerdomains33xx_data.c
new file mode 100644
index 00000000000..869adb82569
--- /dev/null
+++ b/arch/arm/mach-omap2/powerdomains33xx_data.c
@@ -0,0 +1,185 @@
1/*
2 * AM33XX Power domain data
3 *
4 * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18
19#include "powerdomain.h"
20#include "prcm-common.h"
21#include "prm-regbits-33xx.h"
22#include "prm33xx.h"
23
24static struct powerdomain gfx_33xx_pwrdm = {
25 .name = "gfx_pwrdm",
26 .voltdm = { .name = "core" },
27 .prcm_offs = AM33XX_PRM_GFX_MOD,
28 .pwrstctrl_offs = AM33XX_PM_GFX_PWRSTCTRL_OFFSET,
29 .pwrstst_offs = AM33XX_PM_GFX_PWRSTST_OFFSET,
30 .pwrsts = PWRSTS_OFF_RET_ON,
31 .pwrsts_logic_ret = PWRSTS_OFF_RET,
32 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
33 .banks = 1,
34 .logicretstate_mask = AM33XX_LOGICRETSTATE_MASK,
35 .mem_on_mask = {
36 [0] = AM33XX_GFX_MEM_ONSTATE_MASK, /* gfx_mem */
37 },
38 .mem_ret_mask = {
39 [0] = AM33XX_GFX_MEM_RETSTATE_MASK, /* gfx_mem */
40 },
41 .mem_pwrst_mask = {
42 [0] = AM33XX_GFX_MEM_STATEST_MASK, /* gfx_mem */
43 },
44 .mem_retst_mask = {
45 [0] = AM33XX_GFX_MEM_RETSTATE_MASK, /* gfx_mem */
46 },
47 .pwrsts_mem_ret = {
48 [0] = PWRSTS_OFF_RET, /* gfx_mem */
49 },
50 .pwrsts_mem_on = {
51 [0] = PWRSTS_ON, /* gfx_mem */
52 },
53};
54
55static struct powerdomain rtc_33xx_pwrdm = {
56 .name = "rtc_pwrdm",
57 .voltdm = { .name = "rtc" },
58 .prcm_offs = AM33XX_PRM_RTC_MOD,
59 .pwrstctrl_offs = AM33XX_PM_RTC_PWRSTCTRL_OFFSET,
60 .pwrstst_offs = AM33XX_PM_RTC_PWRSTST_OFFSET,
61 .pwrsts = PWRSTS_ON,
62 .logicretstate_mask = AM33XX_LOGICRETSTATE_MASK,
63};
64
65static struct powerdomain wkup_33xx_pwrdm = {
66 .name = "wkup_pwrdm",
67 .voltdm = { .name = "core" },
68 .prcm_offs = AM33XX_PRM_WKUP_MOD,
69 .pwrstctrl_offs = AM33XX_PM_WKUP_PWRSTCTRL_OFFSET,
70 .pwrstst_offs = AM33XX_PM_WKUP_PWRSTST_OFFSET,
71 .pwrsts = PWRSTS_ON,
72 .logicretstate_mask = AM33XX_LOGICRETSTATE_3_3_MASK,
73};
74
75static struct powerdomain per_33xx_pwrdm = {
76 .name = "per_pwrdm",
77 .voltdm = { .name = "core" },
78 .prcm_offs = AM33XX_PRM_PER_MOD,
79 .pwrstctrl_offs = AM33XX_PM_PER_PWRSTCTRL_OFFSET,
80 .pwrstst_offs = AM33XX_PM_PER_PWRSTST_OFFSET,
81 .pwrsts = PWRSTS_OFF_RET_ON,
82 .pwrsts_logic_ret = PWRSTS_OFF_RET,
83 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
84 .banks = 3,
85 .logicretstate_mask = AM33XX_LOGICRETSTATE_3_3_MASK,
86 .mem_on_mask = {
87 [0] = AM33XX_PRUSS_MEM_ONSTATE_MASK, /* pruss_mem */
88 [1] = AM33XX_PER_MEM_ONSTATE_MASK, /* per_mem */
89 [2] = AM33XX_RAM_MEM_ONSTATE_MASK, /* ram_mem */
90 },
91 .mem_ret_mask = {
92 [0] = AM33XX_PRUSS_MEM_RETSTATE_MASK, /* pruss_mem */
93 [1] = AM33XX_PER_MEM_RETSTATE_MASK, /* per_mem */
94 [2] = AM33XX_RAM_MEM_RETSTATE_MASK, /* ram_mem */
95 },
96 .mem_pwrst_mask = {
97 [0] = AM33XX_PRUSS_MEM_STATEST_MASK, /* pruss_mem */
98 [1] = AM33XX_PER_MEM_STATEST_MASK, /* per_mem */
99 [2] = AM33XX_RAM_MEM_STATEST_MASK, /* ram_mem */
100 },
101 .mem_retst_mask = {
102 [0] = AM33XX_PRUSS_MEM_RETSTATE_MASK, /* pruss_mem */
103 [1] = AM33XX_PER_MEM_RETSTATE_MASK, /* per_mem */
104 [2] = AM33XX_RAM_MEM_RETSTATE_MASK, /* ram_mem */
105 },
106 .pwrsts_mem_ret = {
107 [0] = PWRSTS_OFF_RET, /* pruss_mem */
108 [1] = PWRSTS_OFF_RET, /* per_mem */
109 [2] = PWRSTS_OFF_RET, /* ram_mem */
110 },
111 .pwrsts_mem_on = {
112 [0] = PWRSTS_ON, /* pruss_mem */
113 [1] = PWRSTS_ON, /* per_mem */
114 [2] = PWRSTS_ON, /* ram_mem */
115 },
116};
117
118static struct powerdomain mpu_33xx_pwrdm = {
119 .name = "mpu_pwrdm",
120 .voltdm = { .name = "mpu" },
121 .prcm_offs = AM33XX_PRM_MPU_MOD,
122 .pwrstctrl_offs = AM33XX_PM_MPU_PWRSTCTRL_OFFSET,
123 .pwrstst_offs = AM33XX_PM_MPU_PWRSTST_OFFSET,
124 .pwrsts = PWRSTS_OFF_RET_ON,
125 .pwrsts_logic_ret = PWRSTS_OFF_RET,
126 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
127 .banks = 3,
128 .logicretstate_mask = AM33XX_LOGICRETSTATE_MASK,
129 .mem_on_mask = {
130 [0] = AM33XX_MPU_L1_ONSTATE_MASK, /* mpu_l1 */
131 [1] = AM33XX_MPU_L2_ONSTATE_MASK, /* mpu_l2 */
132 [2] = AM33XX_MPU_RAM_ONSTATE_MASK, /* mpu_ram */
133 },
134 .mem_ret_mask = {
135 [0] = AM33XX_MPU_L1_RETSTATE_MASK, /* mpu_l1 */
136 [1] = AM33XX_MPU_L2_RETSTATE_MASK, /* mpu_l2 */
137 [2] = AM33XX_MPU_RAM_RETSTATE_MASK, /* mpu_ram */
138 },
139 .mem_pwrst_mask = {
140 [0] = AM33XX_MPU_L1_STATEST_MASK, /* mpu_l1 */
141 [1] = AM33XX_MPU_L2_STATEST_MASK, /* mpu_l2 */
142 [2] = AM33XX_MPU_RAM_STATEST_MASK, /* mpu_ram */
143 },
144 .mem_retst_mask = {
145 [0] = AM33XX_MPU_L1_RETSTATE_MASK, /* mpu_l1 */
146 [1] = AM33XX_MPU_L2_RETSTATE_MASK, /* mpu_l2 */
147 [2] = AM33XX_MPU_RAM_RETSTATE_MASK, /* mpu_ram */
148 },
149 .pwrsts_mem_ret = {
150 [0] = PWRSTS_OFF_RET, /* mpu_l1 */
151 [1] = PWRSTS_OFF_RET, /* mpu_l2 */
152 [2] = PWRSTS_OFF_RET, /* mpu_ram */
153 },
154 .pwrsts_mem_on = {
155 [0] = PWRSTS_ON, /* mpu_l1 */
156 [1] = PWRSTS_ON, /* mpu_l2 */
157 [2] = PWRSTS_ON, /* mpu_ram */
158 },
159};
160
161static struct powerdomain cefuse_33xx_pwrdm = {
162 .name = "cefuse_pwrdm",
163 .voltdm = { .name = "core" },
164 .prcm_offs = AM33XX_PRM_CEFUSE_MOD,
165 .pwrstctrl_offs = AM33XX_PM_CEFUSE_PWRSTCTRL_OFFSET,
166 .pwrstst_offs = AM33XX_PM_CEFUSE_PWRSTST_OFFSET,
167 .pwrsts = PWRSTS_OFF_ON,
168};
169
170static struct powerdomain *powerdomains_am33xx[] __initdata = {
171 &gfx_33xx_pwrdm,
172 &rtc_33xx_pwrdm,
173 &wkup_33xx_pwrdm,
174 &per_33xx_pwrdm,
175 &mpu_33xx_pwrdm,
176 &cefuse_33xx_pwrdm,
177 NULL,
178};
179
180void __init am33xx_powerdomains_init(void)
181{
182 pwrdm_register_platform_funcs(&am33xx_pwrdm_operations);
183 pwrdm_register_pwrdms(powerdomains_am33xx);
184 pwrdm_complete_init();
185}
diff --git a/arch/arm/mach-omap2/prm-regbits-33xx.h b/arch/arm/mach-omap2/prm-regbits-33xx.h
new file mode 100644
index 00000000000..0221b5c20e8
--- /dev/null
+++ b/arch/arm/mach-omap2/prm-regbits-33xx.h
@@ -0,0 +1,357 @@
1/*
2 * AM33XX PRM_XXX register bits
3 *
4 * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_33XX_H
17#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_33XX_H
18
19#include "prm.h"
20
21/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
22#define AM33XX_ABBOFF_ACT_EXPORT_SHIFT 1
23#define AM33XX_ABBOFF_ACT_EXPORT_MASK (1 << 1)
24
25/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
26#define AM33XX_ABBOFF_SLEEP_EXPORT_SHIFT 2
27#define AM33XX_ABBOFF_SLEEP_EXPORT_MASK (1 << 2)
28
29/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
30#define AM33XX_AIPOFF_SHIFT 8
31#define AM33XX_AIPOFF_MASK (1 << 8)
32
33/* Used by PM_WKUP_PWRSTST */
34#define AM33XX_DEBUGSS_MEM_STATEST_SHIFT 17
35#define AM33XX_DEBUGSS_MEM_STATEST_MASK (0x3 << 17)
36
37/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
38#define AM33XX_DISABLE_RTA_EXPORT_SHIFT 0
39#define AM33XX_DISABLE_RTA_EXPORT_MASK (1 << 0)
40
41/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
42#define AM33XX_DPLL_CORE_RECAL_EN_SHIFT 12
43#define AM33XX_DPLL_CORE_RECAL_EN_MASK (1 << 12)
44
45/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
46#define AM33XX_DPLL_CORE_RECAL_ST_SHIFT 12
47#define AM33XX_DPLL_CORE_RECAL_ST_MASK (1 << 12)
48
49/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
50#define AM33XX_DPLL_DDR_RECAL_EN_SHIFT 14
51#define AM33XX_DPLL_DDR_RECAL_EN_MASK (1 << 14)
52
53/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
54#define AM33XX_DPLL_DDR_RECAL_ST_SHIFT 14
55#define AM33XX_DPLL_DDR_RECAL_ST_MASK (1 << 14)
56
57/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
58#define AM33XX_DPLL_DISP_RECAL_EN_SHIFT 15
59#define AM33XX_DPLL_DISP_RECAL_EN_MASK (1 << 15)
60
61/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
62#define AM33XX_DPLL_DISP_RECAL_ST_SHIFT 13
63#define AM33XX_DPLL_DISP_RECAL_ST_MASK (1 << 13)
64
65/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
66#define AM33XX_DPLL_MPU_RECAL_EN_SHIFT 11
67#define AM33XX_DPLL_MPU_RECAL_EN_MASK (1 << 11)
68
69/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
70#define AM33XX_DPLL_MPU_RECAL_ST_SHIFT 11
71#define AM33XX_DPLL_MPU_RECAL_ST_MASK (1 << 11)
72
73/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
74#define AM33XX_DPLL_PER_RECAL_EN_SHIFT 13
75#define AM33XX_DPLL_PER_RECAL_EN_MASK (1 << 13)
76
77/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
78#define AM33XX_DPLL_PER_RECAL_ST_SHIFT 15
79#define AM33XX_DPLL_PER_RECAL_ST_MASK (1 << 15)
80
81/* Used by RM_WKUP_RSTST */
82#define AM33XX_EMULATION_M3_RST_SHIFT 6
83#define AM33XX_EMULATION_M3_RST_MASK (1 << 6)
84
85/* Used by RM_MPU_RSTST */
86#define AM33XX_EMULATION_MPU_RST_SHIFT 5
87#define AM33XX_EMULATION_MPU_RST_MASK (1 << 5)
88
89/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
90#define AM33XX_ENFUNC1_EXPORT_SHIFT 3
91#define AM33XX_ENFUNC1_EXPORT_MASK (1 << 3)
92
93/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
94#define AM33XX_ENFUNC3_EXPORT_SHIFT 5
95#define AM33XX_ENFUNC3_EXPORT_MASK (1 << 5)
96
97/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
98#define AM33XX_ENFUNC4_SHIFT 6
99#define AM33XX_ENFUNC4_MASK (1 << 6)
100
101/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
102#define AM33XX_ENFUNC5_SHIFT 7
103#define AM33XX_ENFUNC5_MASK (1 << 7)
104
105/* Used by PRM_RSTST */
106#define AM33XX_EXTERNAL_WARM_RST_SHIFT 5
107#define AM33XX_EXTERNAL_WARM_RST_MASK (1 << 5)
108
109/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
110#define AM33XX_FORCEWKUP_EN_SHIFT 10
111#define AM33XX_FORCEWKUP_EN_MASK (1 << 10)
112
113/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
114#define AM33XX_FORCEWKUP_ST_SHIFT 10
115#define AM33XX_FORCEWKUP_ST_MASK (1 << 10)
116
117/* Used by PM_GFX_PWRSTCTRL */
118#define AM33XX_GFX_MEM_ONSTATE_SHIFT 17
119#define AM33XX_GFX_MEM_ONSTATE_MASK (0x3 << 17)
120
121/* Used by PM_GFX_PWRSTCTRL */
122#define AM33XX_GFX_MEM_RETSTATE_SHIFT 6
123#define AM33XX_GFX_MEM_RETSTATE_MASK (1 << 6)
124
125/* Used by PM_GFX_PWRSTST */
126#define AM33XX_GFX_MEM_STATEST_SHIFT 4
127#define AM33XX_GFX_MEM_STATEST_MASK (0x3 << 4)
128
129/* Used by RM_GFX_RSTCTRL, RM_GFX_RSTST */
130#define AM33XX_GFX_RST_SHIFT 0
131#define AM33XX_GFX_RST_MASK (1 << 0)
132
133/* Used by PRM_RSTST */
134#define AM33XX_GLOBAL_COLD_RST_SHIFT 0
135#define AM33XX_GLOBAL_COLD_RST_MASK (1 << 0)
136
137/* Used by PRM_RSTST */
138#define AM33XX_GLOBAL_WARM_SW_RST_SHIFT 1
139#define AM33XX_GLOBAL_WARM_SW_RST_MASK (1 << 1)
140
141/* Used by RM_WKUP_RSTST */
142#define AM33XX_ICECRUSHER_M3_RST_SHIFT 7
143#define AM33XX_ICECRUSHER_M3_RST_MASK (1 << 7)
144
145/* Used by RM_MPU_RSTST */
146#define AM33XX_ICECRUSHER_MPU_RST_SHIFT 6
147#define AM33XX_ICECRUSHER_MPU_RST_MASK (1 << 6)
148
149/* Used by PRM_RSTST */
150#define AM33XX_ICEPICK_RST_SHIFT 9
151#define AM33XX_ICEPICK_RST_MASK (1 << 9)
152
153/* Used by RM_PER_RSTCTRL */
154#define AM33XX_PRUSS_LRST_SHIFT 1
155#define AM33XX_PRUSS_LRST_MASK (1 << 1)
156
157/* Used by PM_PER_PWRSTCTRL */
158#define AM33XX_PRUSS_MEM_ONSTATE_SHIFT 5
159#define AM33XX_PRUSS_MEM_ONSTATE_MASK (0x3 << 5)
160
161/* Used by PM_PER_PWRSTCTRL */
162#define AM33XX_PRUSS_MEM_RETSTATE_SHIFT 7
163#define AM33XX_PRUSS_MEM_RETSTATE_MASK (1 << 7)
164
165/* Used by PM_PER_PWRSTST */
166#define AM33XX_PRUSS_MEM_STATEST_SHIFT 23
167#define AM33XX_PRUSS_MEM_STATEST_MASK (0x3 << 23)
168
169/*
170 * Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST,
171 * PM_WKUP_PWRSTST, PM_RTC_PWRSTST
172 */
173#define AM33XX_INTRANSITION_SHIFT 20
174#define AM33XX_INTRANSITION_MASK (1 << 20)
175
176/* Used by PM_CEFUSE_PWRSTST */
177#define AM33XX_LASTPOWERSTATEENTERED_SHIFT 24
178#define AM33XX_LASTPOWERSTATEENTERED_MASK (0x3 << 24)
179
180/* Used by PM_GFX_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_RTC_PWRSTCTRL */
181#define AM33XX_LOGICRETSTATE_SHIFT 2
182#define AM33XX_LOGICRETSTATE_MASK (1 << 2)
183
184/* Renamed from LOGICRETSTATE Used by PM_PER_PWRSTCTRL, PM_WKUP_PWRSTCTRL */
185#define AM33XX_LOGICRETSTATE_3_3_SHIFT 3
186#define AM33XX_LOGICRETSTATE_3_3_MASK (1 << 3)
187
188/*
189 * Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST,
190 * PM_WKUP_PWRSTST, PM_RTC_PWRSTST
191 */
192#define AM33XX_LOGICSTATEST_SHIFT 2
193#define AM33XX_LOGICSTATEST_MASK (1 << 2)
194
195/*
196 * Used by PM_GFX_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, PM_PER_PWRSTCTRL,
197 * PM_MPU_PWRSTCTRL, PM_WKUP_PWRSTCTRL, PM_RTC_PWRSTCTRL
198 */
199#define AM33XX_LOWPOWERSTATECHANGE_SHIFT 4
200#define AM33XX_LOWPOWERSTATECHANGE_MASK (1 << 4)
201
202/* Used by PM_MPU_PWRSTCTRL */
203#define AM33XX_MPU_L1_ONSTATE_SHIFT 18
204#define AM33XX_MPU_L1_ONSTATE_MASK (0x3 << 18)
205
206/* Used by PM_MPU_PWRSTCTRL */
207#define AM33XX_MPU_L1_RETSTATE_SHIFT 22
208#define AM33XX_MPU_L1_RETSTATE_MASK (1 << 22)
209
210/* Used by PM_MPU_PWRSTST */
211#define AM33XX_MPU_L1_STATEST_SHIFT 6
212#define AM33XX_MPU_L1_STATEST_MASK (0x3 << 6)
213
214/* Used by PM_MPU_PWRSTCTRL */
215#define AM33XX_MPU_L2_ONSTATE_SHIFT 20
216#define AM33XX_MPU_L2_ONSTATE_MASK (0x3 << 20)
217
218/* Used by PM_MPU_PWRSTCTRL */
219#define AM33XX_MPU_L2_RETSTATE_SHIFT 23
220#define AM33XX_MPU_L2_RETSTATE_MASK (1 << 23)
221
222/* Used by PM_MPU_PWRSTST */
223#define AM33XX_MPU_L2_STATEST_SHIFT 8
224#define AM33XX_MPU_L2_STATEST_MASK (0x3 << 8)
225
226/* Used by PM_MPU_PWRSTCTRL */
227#define AM33XX_MPU_RAM_ONSTATE_SHIFT 16
228#define AM33XX_MPU_RAM_ONSTATE_MASK (0x3 << 16)
229
230/* Used by PM_MPU_PWRSTCTRL */
231#define AM33XX_MPU_RAM_RETSTATE_SHIFT 24
232#define AM33XX_MPU_RAM_RETSTATE_MASK (1 << 24)
233
234/* Used by PM_MPU_PWRSTST */
235#define AM33XX_MPU_RAM_STATEST_SHIFT 4
236#define AM33XX_MPU_RAM_STATEST_MASK (0x3 << 4)
237
238/* Used by PRM_RSTST */
239#define AM33XX_MPU_SECURITY_VIOL_RST_SHIFT 2
240#define AM33XX_MPU_SECURITY_VIOL_RST_MASK (1 << 2)
241
242/* Used by PRM_SRAM_COUNT */
243#define AM33XX_PCHARGECNT_VALUE_SHIFT 0
244#define AM33XX_PCHARGECNT_VALUE_MASK (0x3f << 0)
245
246/* Used by RM_PER_RSTCTRL */
247#define AM33XX_PCI_LRST_SHIFT 0
248#define AM33XX_PCI_LRST_MASK (1 << 0)
249
250/* Renamed from PCI_LRST Used by RM_PER_RSTST */
251#define AM33XX_PCI_LRST_5_5_SHIFT 5
252#define AM33XX_PCI_LRST_5_5_MASK (1 << 5)
253
254/* Used by PM_PER_PWRSTCTRL */
255#define AM33XX_PER_MEM_ONSTATE_SHIFT 25
256#define AM33XX_PER_MEM_ONSTATE_MASK (0x3 << 25)
257
258/* Used by PM_PER_PWRSTCTRL */
259#define AM33XX_PER_MEM_RETSTATE_SHIFT 29
260#define AM33XX_PER_MEM_RETSTATE_MASK (1 << 29)
261
262/* Used by PM_PER_PWRSTST */
263#define AM33XX_PER_MEM_STATEST_SHIFT 17
264#define AM33XX_PER_MEM_STATEST_MASK (0x3 << 17)
265
266/*
267 * Used by PM_GFX_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, PM_PER_PWRSTCTRL,
268 * PM_MPU_PWRSTCTRL
269 */
270#define AM33XX_POWERSTATE_SHIFT 0
271#define AM33XX_POWERSTATE_MASK (0x3 << 0)
272
273/* Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST */
274#define AM33XX_POWERSTATEST_SHIFT 0
275#define AM33XX_POWERSTATEST_MASK (0x3 << 0)
276
277/* Used by PM_PER_PWRSTCTRL */
278#define AM33XX_RAM_MEM_ONSTATE_SHIFT 30
279#define AM33XX_RAM_MEM_ONSTATE_MASK (0x3 << 30)
280
281/* Used by PM_PER_PWRSTCTRL */
282#define AM33XX_RAM_MEM_RETSTATE_SHIFT 27
283#define AM33XX_RAM_MEM_RETSTATE_MASK (1 << 27)
284
285/* Used by PM_PER_PWRSTST */
286#define AM33XX_RAM_MEM_STATEST_SHIFT 21
287#define AM33XX_RAM_MEM_STATEST_MASK (0x3 << 21)
288
289/* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */
290#define AM33XX_RETMODE_ENABLE_SHIFT 0
291#define AM33XX_RETMODE_ENABLE_MASK (1 << 0)
292
293/* Used by REVISION_PRM */
294#define AM33XX_REV_SHIFT 0
295#define AM33XX_REV_MASK (0xff << 0)
296
297/* Used by PRM_RSTTIME */
298#define AM33XX_RSTTIME1_SHIFT 0
299#define AM33XX_RSTTIME1_MASK (0xff << 0)
300
301/* Used by PRM_RSTTIME */
302#define AM33XX_RSTTIME2_SHIFT 8
303#define AM33XX_RSTTIME2_MASK (0x1f << 8)
304
305/* Used by PRM_RSTCTRL */
306#define AM33XX_RST_GLOBAL_COLD_SW_SHIFT 1
307#define AM33XX_RST_GLOBAL_COLD_SW_MASK (1 << 1)
308
309/* Used by PRM_RSTCTRL */
310#define AM33XX_RST_GLOBAL_WARM_SW_SHIFT 0
311#define AM33XX_RST_GLOBAL_WARM_SW_MASK (1 << 0)
312
313/* Used by PRM_SRAM_COUNT */
314#define AM33XX_SLPCNT_VALUE_SHIFT 16
315#define AM33XX_SLPCNT_VALUE_MASK (0xff << 16)
316
317/* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */
318#define AM33XX_SRAMLDO_STATUS_SHIFT 8
319#define AM33XX_SRAMLDO_STATUS_MASK (1 << 8)
320
321/* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */
322#define AM33XX_SRAM_IN_TRANSITION_SHIFT 9
323#define AM33XX_SRAM_IN_TRANSITION_MASK (1 << 9)
324
325/* Used by PRM_SRAM_COUNT */
326#define AM33XX_STARTUP_COUNT_SHIFT 24
327#define AM33XX_STARTUP_COUNT_MASK (0xff << 24)
328
329/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
330#define AM33XX_TRANSITION_EN_SHIFT 8
331#define AM33XX_TRANSITION_EN_MASK (1 << 8)
332
333/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
334#define AM33XX_TRANSITION_ST_SHIFT 8
335#define AM33XX_TRANSITION_ST_MASK (1 << 8)
336
337/* Used by PRM_SRAM_COUNT */
338#define AM33XX_VSETUPCNT_VALUE_SHIFT 8
339#define AM33XX_VSETUPCNT_VALUE_MASK (0xff << 8)
340
341/* Used by PRM_RSTST */
342#define AM33XX_WDT0_RST_SHIFT 3
343#define AM33XX_WDT0_RST_MASK (1 << 3)
344
345/* Used by PRM_RSTST */
346#define AM33XX_WDT1_RST_SHIFT 4
347#define AM33XX_WDT1_RST_MASK (1 << 4)
348
349/* Used by RM_WKUP_RSTCTRL */
350#define AM33XX_WKUP_M3_LRST_SHIFT 3
351#define AM33XX_WKUP_M3_LRST_MASK (1 << 3)
352
353/* Renamed from WKUP_M3_LRST Used by RM_WKUP_RSTST */
354#define AM33XX_WKUP_M3_LRST_5_5_SHIFT 5
355#define AM33XX_WKUP_M3_LRST_5_5_MASK (1 << 5)
356
357#endif
diff --git a/arch/arm/mach-omap2/prm33xx.c b/arch/arm/mach-omap2/prm33xx.c
new file mode 100644
index 00000000000..e7dbb6cf125
--- /dev/null
+++ b/arch/arm/mach-omap2/prm33xx.c
@@ -0,0 +1,135 @@
1/*
2 * AM33XX PRM functions
3 *
4 * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/kernel.h>
17#include <linux/types.h>
18#include <linux/errno.h>
19#include <linux/err.h>
20#include <linux/io.h>
21
22#include <plat/common.h>
23
24#include "common.h"
25#include "prm33xx.h"
26#include "prm-regbits-33xx.h"
27
28/* Read a register in a PRM instance */
29u32 am33xx_prm_read_reg(s16 inst, u16 idx)
30{
31 return __raw_readl(prm_base + inst + idx);
32}
33
34/* Write into a register in a PRM instance */
35void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx)
36{
37 __raw_writel(val, prm_base + inst + idx);
38}
39
40/* Read-modify-write a register in PRM. Caller must lock */
41u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx)
42{
43 u32 v;
44
45 v = am33xx_prm_read_reg(inst, idx);
46 v &= ~mask;
47 v |= bits;
48 am33xx_prm_write_reg(v, inst, idx);
49
50 return v;
51}
52
53/**
54 * am33xx_prm_is_hardreset_asserted - read the HW reset line state of
55 * submodules contained in the hwmod module
56 * @shift: register bit shift corresponding to the reset line to check
57 * @inst: CM instance register offset (*_INST macro)
58 * @rstctrl_offs: RM_RSTCTRL register address offset for this module
59 *
60 * Returns 1 if the (sub)module hardreset line is currently asserted,
61 * 0 if the (sub)module hardreset line is not currently asserted, or
62 * -EINVAL upon parameter error.
63 */
64int am33xx_prm_is_hardreset_asserted(u8 shift, s16 inst, u16 rstctrl_offs)
65{
66 u32 v;
67
68 v = am33xx_prm_read_reg(inst, rstctrl_offs);
69 v &= 1 << shift;
70 v >>= shift;
71
72 return v;
73}
74
75/**
76 * am33xx_prm_assert_hardreset - assert the HW reset line of a submodule
77 * @shift: register bit shift corresponding to the reset line to assert
78 * @inst: CM instance register offset (*_INST macro)
79 * @rstctrl_reg: RM_RSTCTRL register address for this module
80 *
81 * Some IPs like dsp, ipu or iva contain processors that require an HW
82 * reset line to be asserted / deasserted in order to fully enable the
83 * IP. These modules may have multiple hard-reset lines that reset
84 * different 'submodules' inside the IP block. This function will
85 * place the submodule into reset. Returns 0 upon success or -EINVAL
86 * upon an argument error.
87 */
88int am33xx_prm_assert_hardreset(u8 shift, s16 inst, u16 rstctrl_offs)
89{
90 u32 mask = 1 << shift;
91
92 am33xx_prm_rmw_reg_bits(mask, mask, inst, rstctrl_offs);
93
94 return 0;
95}
96
97/**
98 * am33xx_prm_deassert_hardreset - deassert a submodule hardreset line and
99 * wait
100 * @shift: register bit shift corresponding to the reset line to deassert
101 * @inst: CM instance register offset (*_INST macro)
102 * @rstctrl_reg: RM_RSTCTRL register address for this module
103 * @rstst_reg: RM_RSTST register address for this module
104 *
105 * Some IPs like dsp, ipu or iva contain processors that require an HW
106 * reset line to be asserted / deasserted in order to fully enable the
107 * IP. These modules may have multiple hard-reset lines that reset
108 * different 'submodules' inside the IP block. This function will
109 * take the submodule out of reset and wait until the PRCM indicates
110 * that the reset has completed before returning. Returns 0 upon success or
111 * -EINVAL upon an argument error, -EEXIST if the submodule was already out
112 * of reset, or -EBUSY if the submodule did not exit reset promptly.
113 */
114int am33xx_prm_deassert_hardreset(u8 shift, s16 inst,
115 u16 rstctrl_offs, u16 rstst_offs)
116{
117 int c;
118 u32 mask = 1 << shift;
119
120 /* Check the current status to avoid de-asserting the line twice */
121 if (am33xx_prm_is_hardreset_asserted(shift, inst, rstctrl_offs) == 0)
122 return -EEXIST;
123
124 /* Clear the reset status by writing 1 to the status bit */
125 am33xx_prm_rmw_reg_bits(0xffffffff, mask, inst, rstst_offs);
126 /* de-assert the reset control line */
127 am33xx_prm_rmw_reg_bits(mask, 0, inst, rstctrl_offs);
128 /* wait the status to be set */
129
130 omap_test_timeout(am33xx_prm_is_hardreset_asserted(shift, inst,
131 rstst_offs),
132 MAX_MODULE_HARDRESET_WAIT, c);
133
134 return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
135}
diff --git a/arch/arm/mach-omap2/prm33xx.h b/arch/arm/mach-omap2/prm33xx.h
new file mode 100644
index 00000000000..3f25c563a82
--- /dev/null
+++ b/arch/arm/mach-omap2/prm33xx.h
@@ -0,0 +1,129 @@
1/*
2 * AM33XX PRM instance offset macros
3 *
4 * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#ifndef __ARCH_ARM_MACH_OMAP2_PRM33XX_H
17#define __ARCH_ARM_MACH_OMAP2_PRM33XX_H
18
19#include "prcm-common.h"
20#include "prm.h"
21
22#define AM33XX_PRM_BASE 0x44E00000
23
24#define AM33XX_PRM_REGADDR(inst, reg) \
25 AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRM_BASE + (inst) + (reg))
26
27
28/* PRM instances */
29#define AM33XX_PRM_OCP_SOCKET_MOD 0x0B00
30#define AM33XX_PRM_PER_MOD 0x0C00
31#define AM33XX_PRM_WKUP_MOD 0x0D00
32#define AM33XX_PRM_MPU_MOD 0x0E00
33#define AM33XX_PRM_DEVICE_MOD 0x0F00
34#define AM33XX_PRM_RTC_MOD 0x1000
35#define AM33XX_PRM_GFX_MOD 0x1100
36#define AM33XX_PRM_CEFUSE_MOD 0x1200
37
38/* PRM */
39
40/* PRM.OCP_SOCKET_PRM register offsets */
41#define AM33XX_REVISION_PRM_OFFSET 0x0000
42#define AM33XX_REVISION_PRM AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0000)
43#define AM33XX_PRM_IRQSTATUS_MPU_OFFSET 0x0004
44#define AM33XX_PRM_IRQSTATUS_MPU AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0004)
45#define AM33XX_PRM_IRQENABLE_MPU_OFFSET 0x0008
46#define AM33XX_PRM_IRQENABLE_MPU AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0008)
47#define AM33XX_PRM_IRQSTATUS_M3_OFFSET 0x000c
48#define AM33XX_PRM_IRQSTATUS_M3 AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x000c)
49#define AM33XX_PRM_IRQENABLE_M3_OFFSET 0x0010
50#define AM33XX_PRM_IRQENABLE_M3 AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0010)
51
52/* PRM.PER_PRM register offsets */
53#define AM33XX_RM_PER_RSTCTRL_OFFSET 0x0000
54#define AM33XX_RM_PER_RSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0000)
55#define AM33XX_RM_PER_RSTST_OFFSET 0x0004
56#define AM33XX_RM_PER_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0004)
57#define AM33XX_PM_PER_PWRSTST_OFFSET 0x0008
58#define AM33XX_PM_PER_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0008)
59#define AM33XX_PM_PER_PWRSTCTRL_OFFSET 0x000c
60#define AM33XX_PM_PER_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x000c)
61
62/* PRM.WKUP_PRM register offsets */
63#define AM33XX_RM_WKUP_RSTCTRL_OFFSET 0x0000
64#define AM33XX_RM_WKUP_RSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0000)
65#define AM33XX_PM_WKUP_PWRSTCTRL_OFFSET 0x0004
66#define AM33XX_PM_WKUP_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0004)
67#define AM33XX_PM_WKUP_PWRSTST_OFFSET 0x0008
68#define AM33XX_PM_WKUP_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0008)
69#define AM33XX_RM_WKUP_RSTST_OFFSET 0x000c
70#define AM33XX_RM_WKUP_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x000c)
71
72/* PRM.MPU_PRM register offsets */
73#define AM33XX_PM_MPU_PWRSTCTRL_OFFSET 0x0000
74#define AM33XX_PM_MPU_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0000)
75#define AM33XX_PM_MPU_PWRSTST_OFFSET 0x0004
76#define AM33XX_PM_MPU_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0004)
77#define AM33XX_RM_MPU_RSTST_OFFSET 0x0008
78#define AM33XX_RM_MPU_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0008)
79
80/* PRM.DEVICE_PRM register offsets */
81#define AM33XX_PRM_RSTCTRL_OFFSET 0x0000
82#define AM33XX_PRM_RSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0000)
83#define AM33XX_PRM_RSTTIME_OFFSET 0x0004
84#define AM33XX_PRM_RSTTIME AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0004)
85#define AM33XX_PRM_RSTST_OFFSET 0x0008
86#define AM33XX_PRM_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0008)
87#define AM33XX_PRM_SRAM_COUNT_OFFSET 0x000c
88#define AM33XX_PRM_SRAM_COUNT AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x000c)
89#define AM33XX_PRM_LDO_SRAM_CORE_SETUP_OFFSET 0x0010
90#define AM33XX_PRM_LDO_SRAM_CORE_SETUP AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0010)
91#define AM33XX_PRM_LDO_SRAM_CORE_CTRL_OFFSET 0x0014
92#define AM33XX_PRM_LDO_SRAM_CORE_CTRL AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0014)
93#define AM33XX_PRM_LDO_SRAM_MPU_SETUP_OFFSET 0x0018
94#define AM33XX_PRM_LDO_SRAM_MPU_SETUP AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0018)
95#define AM33XX_PRM_LDO_SRAM_MPU_CTRL_OFFSET 0x001c
96#define AM33XX_PRM_LDO_SRAM_MPU_CTRL AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x001c)
97
98/* PRM.RTC_PRM register offsets */
99#define AM33XX_PM_RTC_PWRSTCTRL_OFFSET 0x0000
100#define AM33XX_PM_RTC_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_RTC_MOD, 0x0000)
101#define AM33XX_PM_RTC_PWRSTST_OFFSET 0x0004
102#define AM33XX_PM_RTC_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_RTC_MOD, 0x0004)
103
104/* PRM.GFX_PRM register offsets */
105#define AM33XX_PM_GFX_PWRSTCTRL_OFFSET 0x0000
106#define AM33XX_PM_GFX_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0000)
107#define AM33XX_RM_GFX_RSTCTRL_OFFSET 0x0004
108#define AM33XX_RM_GFX_RSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0004)
109#define AM33XX_PM_GFX_PWRSTST_OFFSET 0x0010
110#define AM33XX_PM_GFX_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0010)
111#define AM33XX_RM_GFX_RSTST_OFFSET 0x0014
112#define AM33XX_RM_GFX_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0014)
113
114/* PRM.CEFUSE_PRM register offsets */
115#define AM33XX_PM_CEFUSE_PWRSTCTRL_OFFSET 0x0000
116#define AM33XX_PM_CEFUSE_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_CEFUSE_MOD, 0x0000)
117#define AM33XX_PM_CEFUSE_PWRSTST_OFFSET 0x0004
118#define AM33XX_PM_CEFUSE_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_CEFUSE_MOD, 0x0004)
119
120extern u32 am33xx_prm_read_reg(s16 inst, u16 idx);
121extern void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx);
122extern u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
123extern void am33xx_prm_global_warm_sw_reset(void);
124extern int am33xx_prm_is_hardreset_asserted(u8 shift, s16 inst,
125 u16 rstctrl_offs);
126extern int am33xx_prm_assert_hardreset(u8 shift, s16 inst, u16 rstctrl_offs);
127extern int am33xx_prm_deassert_hardreset(u8 shift, s16 inst,
128 u16 rstctrl_offs, u16 rstst_offs);
129#endif
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 840929bd9da..b5b5d92acd9 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -69,11 +69,6 @@
69#define OMAP3_SECURE_TIMER 1 69#define OMAP3_SECURE_TIMER 1
70#endif 70#endif
71 71
72/* MAX_GPTIMER_ID: number of GPTIMERs on the chip */
73#define MAX_GPTIMER_ID 12
74
75static u32 sys_timer_reserved;
76
77/* Clockevent code */ 72/* Clockevent code */
78 73
79static struct omap_dm_timer clkev; 74static struct omap_dm_timer clkev;
@@ -180,7 +175,8 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
180 175
181 omap_hwmod_enable(oh); 176 omap_hwmod_enable(oh);
182 177
183 sys_timer_reserved |= (1 << (gptimer_id - 1)); 178 if (omap_dm_timer_reserve_systimer(gptimer_id))
179 return -ENODEV;
184 180
185 if (gptimer_id != 12) { 181 if (gptimer_id != 12) {
186 struct clk *src; 182 struct clk *src;
@@ -368,6 +364,11 @@ OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE,
368OMAP_SYS_TIMER(3_secure) 364OMAP_SYS_TIMER(3_secure)
369#endif 365#endif
370 366
367#ifdef CONFIG_SOC_AM33XX
368OMAP_SYS_TIMER_INIT(3_am33xx, 1, OMAP4_MPU_SOURCE, 2, OMAP4_MPU_SOURCE)
369OMAP_SYS_TIMER(3_am33xx)
370#endif
371
371#ifdef CONFIG_ARCH_OMAP4 372#ifdef CONFIG_ARCH_OMAP4
372#ifdef CONFIG_LOCAL_TIMERS 373#ifdef CONFIG_LOCAL_TIMERS
373static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 374static DEFINE_TWD_LOCAL_TIMER(twd_local_timer,
@@ -394,66 +395,6 @@ OMAP_SYS_TIMER(4)
394#endif 395#endif
395 396
396/** 397/**
397 * omap2_dm_timer_set_src - change the timer input clock source
398 * @pdev: timer platform device pointer
399 * @source: array index of parent clock source
400 */
401static int omap2_dm_timer_set_src(struct platform_device *pdev, int source)
402{
403 int ret;
404 struct dmtimer_platform_data *pdata = pdev->dev.platform_data;
405 struct clk *fclk, *parent;
406 char *parent_name = NULL;
407
408 fclk = clk_get(&pdev->dev, "fck");
409 if (IS_ERR_OR_NULL(fclk)) {
410 dev_err(&pdev->dev, "%s: %d: clk_get() FAILED\n",
411 __func__, __LINE__);
412 return -EINVAL;
413 }
414
415 switch (source) {
416 case OMAP_TIMER_SRC_SYS_CLK:
417 parent_name = "sys_ck";
418 break;
419
420 case OMAP_TIMER_SRC_32_KHZ:
421 parent_name = "32k_ck";
422 break;
423
424 case OMAP_TIMER_SRC_EXT_CLK:
425 if (pdata->timer_ip_version == OMAP_TIMER_IP_VERSION_1) {
426 parent_name = "alt_ck";
427 break;
428 }
429 dev_err(&pdev->dev, "%s: %d: invalid clk src.\n",
430 __func__, __LINE__);
431 clk_put(fclk);
432 return -EINVAL;
433 }
434
435 parent = clk_get(&pdev->dev, parent_name);
436 if (IS_ERR_OR_NULL(parent)) {
437 dev_err(&pdev->dev, "%s: %d: clk_get() %s FAILED\n",
438 __func__, __LINE__, parent_name);
439 clk_put(fclk);
440 return -EINVAL;
441 }
442
443 ret = clk_set_parent(fclk, parent);
444 if (IS_ERR_VALUE(ret)) {
445 dev_err(&pdev->dev, "%s: clk_set_parent() to %s FAILED\n",
446 __func__, parent_name);
447 ret = -EINVAL;
448 }
449
450 clk_put(parent);
451 clk_put(fclk);
452
453 return ret;
454}
455
456/**
457 * omap_timer_init - build and register timer device with an 398 * omap_timer_init - build and register timer device with an
458 * associated timer hwmod 399 * associated timer hwmod
459 * @oh: timer hwmod pointer to be used to build timer device 400 * @oh: timer hwmod pointer to be used to build timer device
@@ -473,7 +414,6 @@ static int __init omap_timer_init(struct omap_hwmod *oh, void *unused)
473 struct dmtimer_platform_data *pdata; 414 struct dmtimer_platform_data *pdata;
474 struct platform_device *pdev; 415 struct platform_device *pdev;
475 struct omap_timer_capability_dev_attr *timer_dev_attr; 416 struct omap_timer_capability_dev_attr *timer_dev_attr;
476 struct powerdomain *pwrdm;
477 417
478 pr_debug("%s: %s\n", __func__, oh->name); 418 pr_debug("%s: %s\n", __func__, oh->name);
479 419
@@ -501,18 +441,9 @@ static int __init omap_timer_init(struct omap_hwmod *oh, void *unused)
501 */ 441 */
502 sscanf(oh->name, "timer%2d", &id); 442 sscanf(oh->name, "timer%2d", &id);
503 443
504 pdata->set_timer_src = omap2_dm_timer_set_src; 444 if (timer_dev_attr)
505 pdata->timer_ip_version = oh->class->rev; 445 pdata->timer_capability = timer_dev_attr->timer_capability;
506 446
507 /* Mark clocksource and clockevent timers as reserved */
508 if ((sys_timer_reserved >> (id - 1)) & 0x1)
509 pdata->reserved = 1;
510
511 pwrdm = omap_hwmod_get_pwrdm(oh);
512 pdata->loses_context = pwrdm_can_ever_lose_context(pwrdm);
513#ifdef CONFIG_PM
514 pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count;
515#endif
516 pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata), 447 pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata),
517 NULL, 0, 0); 448 NULL, 0, 0);
518 449
diff --git a/arch/arm/mach-omap2/usb-fs.c b/arch/arm/mach-omap2/usb-fs.c
deleted file mode 100644
index 1481078763b..00000000000
--- a/arch/arm/mach-omap2/usb-fs.c
+++ /dev/null
@@ -1,359 +0,0 @@
1/*
2 * Platform level USB initialization for FS USB OTG controller on omap1 and 24xx
3 *
4 * Copyright (C) 2004 Texas Instruments, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#include <linux/module.h>
22#include <linux/kernel.h>
23#include <linux/types.h>
24#include <linux/errno.h>
25#include <linux/init.h>
26#include <linux/platform_device.h>
27#include <linux/clk.h>
28#include <linux/err.h>
29
30#include <asm/irq.h>
31
32#include <plat/usb.h>
33#include <plat/board.h>
34
35#include "control.h"
36#include "mux.h"
37
38#define INT_USB_IRQ_GEN INT_24XX_USB_IRQ_GEN
39#define INT_USB_IRQ_NISO INT_24XX_USB_IRQ_NISO
40#define INT_USB_IRQ_ISO INT_24XX_USB_IRQ_ISO
41#define INT_USB_IRQ_HGEN INT_24XX_USB_IRQ_HGEN
42#define INT_USB_IRQ_OTG INT_24XX_USB_IRQ_OTG
43
44#if defined(CONFIG_ARCH_OMAP2)
45
46#ifdef CONFIG_USB_GADGET_OMAP
47
48static struct resource udc_resources[] = {
49 /* order is significant! */
50 { /* registers */
51 .start = UDC_BASE,
52 .end = UDC_BASE + 0xff,
53 .flags = IORESOURCE_MEM,
54 }, { /* general IRQ */
55 .start = INT_USB_IRQ_GEN,
56 .flags = IORESOURCE_IRQ,
57 }, { /* PIO IRQ */
58 .start = INT_USB_IRQ_NISO,
59 .flags = IORESOURCE_IRQ,
60 }, { /* SOF IRQ */
61 .start = INT_USB_IRQ_ISO,
62 .flags = IORESOURCE_IRQ,
63 },
64};
65
66static u64 udc_dmamask = ~(u32)0;
67
68static struct platform_device udc_device = {
69 .name = "omap_udc",
70 .id = -1,
71 .dev = {
72 .dma_mask = &udc_dmamask,
73 .coherent_dma_mask = 0xffffffff,
74 },
75 .num_resources = ARRAY_SIZE(udc_resources),
76 .resource = udc_resources,
77};
78
79static inline void udc_device_init(struct omap_usb_config *pdata)
80{
81 pdata->udc_device = &udc_device;
82}
83
84#else
85
86static inline void udc_device_init(struct omap_usb_config *pdata)
87{
88}
89
90#endif
91
92#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
93
94/* The dmamask must be set for OHCI to work */
95static u64 ohci_dmamask = ~(u32)0;
96
97static struct resource ohci_resources[] = {
98 {
99 .start = OMAP_OHCI_BASE,
100 .end = OMAP_OHCI_BASE + 0xff,
101 .flags = IORESOURCE_MEM,
102 },
103 {
104 .start = INT_USB_IRQ_HGEN,
105 .flags = IORESOURCE_IRQ,
106 },
107};
108
109static struct platform_device ohci_device = {
110 .name = "ohci",
111 .id = -1,
112 .dev = {
113 .dma_mask = &ohci_dmamask,
114 .coherent_dma_mask = 0xffffffff,
115 },
116 .num_resources = ARRAY_SIZE(ohci_resources),
117 .resource = ohci_resources,
118};
119
120static inline void ohci_device_init(struct omap_usb_config *pdata)
121{
122 pdata->ohci_device = &ohci_device;
123}
124
125#else
126
127static inline void ohci_device_init(struct omap_usb_config *pdata)
128{
129}
130
131#endif
132
133#if defined(CONFIG_USB_OTG) && defined(CONFIG_ARCH_OMAP_OTG)
134
135static struct resource otg_resources[] = {
136 /* order is significant! */
137 {
138 .start = OTG_BASE,
139 .end = OTG_BASE + 0xff,
140 .flags = IORESOURCE_MEM,
141 }, {
142 .start = INT_USB_IRQ_OTG,
143 .flags = IORESOURCE_IRQ,
144 },
145};
146
147static struct platform_device otg_device = {
148 .name = "omap_otg",
149 .id = -1,
150 .num_resources = ARRAY_SIZE(otg_resources),
151 .resource = otg_resources,
152};
153
154static inline void otg_device_init(struct omap_usb_config *pdata)
155{
156 pdata->otg_device = &otg_device;
157}
158
159#else
160
161static inline void otg_device_init(struct omap_usb_config *pdata)
162{
163}
164
165#endif
166
167static void omap2_usb_devconf_clear(u8 port, u32 mask)
168{
169 u32 r;
170
171 r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
172 r &= ~USBTXWRMODEI(port, mask);
173 omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
174}
175
176static void omap2_usb_devconf_set(u8 port, u32 mask)
177{
178 u32 r;
179
180 r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
181 r |= USBTXWRMODEI(port, mask);
182 omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
183}
184
185static void omap2_usb2_disable_5pinbitll(void)
186{
187 u32 r;
188
189 r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
190 r &= ~(USBTXWRMODEI(2, USB_BIDIR_TLL) | USBT2TLL5PI);
191 omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
192}
193
194static void omap2_usb2_enable_5pinunitll(void)
195{
196 u32 r;
197
198 r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
199 r |= USBTXWRMODEI(2, USB_UNIDIR_TLL) | USBT2TLL5PI;
200 omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
201}
202
203static u32 __init omap2_usb0_init(unsigned nwires, unsigned is_device)
204{
205 u32 syscon1 = 0;
206
207 omap2_usb_devconf_clear(0, USB_BIDIR_TLL);
208
209 if (nwires == 0)
210 return 0;
211
212 if (is_device)
213 omap_mux_init_signal("usb0_puen", 0);
214
215 omap_mux_init_signal("usb0_dat", 0);
216 omap_mux_init_signal("usb0_txen", 0);
217 omap_mux_init_signal("usb0_se0", 0);
218 if (nwires != 3)
219 omap_mux_init_signal("usb0_rcv", 0);
220
221 switch (nwires) {
222 case 3:
223 syscon1 = 2;
224 omap2_usb_devconf_set(0, USB_BIDIR);
225 break;
226 case 4:
227 syscon1 = 1;
228 omap2_usb_devconf_set(0, USB_BIDIR);
229 break;
230 case 6:
231 syscon1 = 3;
232 omap_mux_init_signal("usb0_vp", 0);
233 omap_mux_init_signal("usb0_vm", 0);
234 omap2_usb_devconf_set(0, USB_UNIDIR);
235 break;
236 default:
237 printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
238 0, nwires);
239 }
240
241 return syscon1 << 16;
242}
243
244static u32 __init omap2_usb1_init(unsigned nwires)
245{
246 u32 syscon1 = 0;
247
248 omap2_usb_devconf_clear(1, USB_BIDIR_TLL);
249
250 if (nwires == 0)
251 return 0;
252
253 /* NOTE: board-specific code must set up pin muxing for usb1,
254 * since each signal could come out on either of two balls.
255 */
256
257 switch (nwires) {
258 case 2:
259 /* NOTE: board-specific code must override this setting if
260 * this TLL link is not using DP/DM
261 */
262 syscon1 = 1;
263 omap2_usb_devconf_set(1, USB_BIDIR_TLL);
264 break;
265 case 3:
266 syscon1 = 2;
267 omap2_usb_devconf_set(1, USB_BIDIR);
268 break;
269 case 4:
270 syscon1 = 1;
271 omap2_usb_devconf_set(1, USB_BIDIR);
272 break;
273 case 6:
274 default:
275 printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
276 1, nwires);
277 }
278
279 return syscon1 << 20;
280}
281
282static u32 __init omap2_usb2_init(unsigned nwires, unsigned alt_pingroup)
283{
284 u32 syscon1 = 0;
285
286 omap2_usb2_disable_5pinbitll();
287 alt_pingroup = 0;
288
289 /* NOTE omap1 erratum: must leave USB2_UNI_R set if usb0 in use */
290 if (alt_pingroup || nwires == 0)
291 return 0;
292
293 omap_mux_init_signal("usb2_dat", 0);
294 omap_mux_init_signal("usb2_se0", 0);
295 if (nwires > 2)
296 omap_mux_init_signal("usb2_txen", 0);
297 if (nwires > 3)
298 omap_mux_init_signal("usb2_rcv", 0);
299
300 switch (nwires) {
301 case 2:
302 /* NOTE: board-specific code must override this setting if
303 * this TLL link is not using DP/DM
304 */
305 syscon1 = 1;
306 omap2_usb_devconf_set(2, USB_BIDIR_TLL);
307 break;
308 case 3:
309 syscon1 = 2;
310 omap2_usb_devconf_set(2, USB_BIDIR);
311 break;
312 case 4:
313 syscon1 = 1;
314 omap2_usb_devconf_set(2, USB_BIDIR);
315 break;
316 case 5:
317 /* NOTE: board-specific code must mux this setting depending
318 * on TLL link using DP/DM. Something must also
319 * set up OTG_SYSCON2.HMC_TLL{ATTACH,SPEED}
320 * 2420: hdq_sio.usb2_tllse0 or vlynq_rx0.usb2_tllse0
321 * 2430: hdq_sio.usb2_tllse0 or sdmmc2_dat0.usb2_tllse0
322 */
323
324 syscon1 = 3;
325 omap2_usb2_enable_5pinunitll();
326 break;
327 case 6:
328 default:
329 printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
330 2, nwires);
331 }
332
333 return syscon1 << 24;
334}
335
336void __init omap2_usbfs_init(struct omap_usb_config *pdata)
337{
338 struct clk *ick;
339
340 if (!cpu_is_omap24xx())
341 return;
342
343 ick = clk_get(NULL, "usb_l4_ick");
344 if (IS_ERR(ick))
345 return;
346
347 clk_enable(ick);
348 pdata->usb0_init = omap2_usb0_init;
349 pdata->usb1_init = omap2_usb1_init;
350 pdata->usb2_init = omap2_usb2_init;
351 udc_device_init(pdata);
352 ohci_device_init(pdata);
353 otg_device_init(pdata);
354 omap_otg_init(pdata);
355 clk_disable(ick);
356 clk_put(ick);
357}
358
359#endif
diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
index 16a1b092cf3..a7c43c1042b 100644
--- a/arch/arm/mach-omap2/voltage.h
+++ b/arch/arm/mach-omap2/voltage.h
@@ -156,6 +156,7 @@ int omap_voltage_late_init(void);
156 156
157extern void omap2xxx_voltagedomains_init(void); 157extern void omap2xxx_voltagedomains_init(void);
158extern void omap3xxx_voltagedomains_init(void); 158extern void omap3xxx_voltagedomains_init(void);
159extern void am33xx_voltagedomains_init(void);
159extern void omap44xx_voltagedomains_init(void); 160extern void omap44xx_voltagedomains_init(void);
160 161
161struct voltagedomain *voltdm_lookup(const char *name); 162struct voltagedomain *voltdm_lookup(const char *name);
diff --git a/arch/arm/mach-omap2/voltagedomains33xx_data.c b/arch/arm/mach-omap2/voltagedomains33xx_data.c
new file mode 100644
index 00000000000..965458dc0cb
--- /dev/null
+++ b/arch/arm/mach-omap2/voltagedomains33xx_data.c
@@ -0,0 +1,43 @@
1/*
2 * AM33XX voltage domain data
3 *
4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18
19#include "voltage.h"
20
21static struct voltagedomain am33xx_voltdm_mpu = {
22 .name = "mpu",
23};
24
25static struct voltagedomain am33xx_voltdm_core = {
26 .name = "core",
27};
28
29static struct voltagedomain am33xx_voltdm_rtc = {
30 .name = "rtc",
31};
32
33static struct voltagedomain *voltagedomains_am33xx[] __initdata = {
34 &am33xx_voltdm_mpu,
35 &am33xx_voltdm_core,
36 &am33xx_voltdm_rtc,
37 NULL,
38};
39
40void __init am33xx_voltagedomains_init(void)
41{
42 voltdm_init(voltagedomains_am33xx);
43}
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index ed8605f0115..6d87532871c 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -4,7 +4,7 @@
4 4
5# Common support 5# Common support
6obj-y := common.o sram.o clock.o devices.o dma.o mux.o \ 6obj-y := common.o sram.o clock.o devices.o dma.o mux.o \
7 usb.o fb.o counter_32k.o 7 fb.o counter_32k.o
8obj-m := 8obj-m :=
9obj-n := 9obj-n :=
10obj- := 10obj- :=
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index cb16ade437c..7fe626761e5 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -573,22 +573,25 @@ EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
573 573
574static inline void omap_enable_channel_irq(int lch) 574static inline void omap_enable_channel_irq(int lch)
575{ 575{
576 u32 status;
577
578 /* Clear CSR */ 576 /* Clear CSR */
579 if (cpu_class_is_omap1()) 577 if (cpu_class_is_omap1())
580 status = p->dma_read(CSR, lch); 578 p->dma_read(CSR, lch);
581 else if (cpu_class_is_omap2()) 579 else
582 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch); 580 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
583 581
584 /* Enable some nice interrupts. */ 582 /* Enable some nice interrupts. */
585 p->dma_write(dma_chan[lch].enabled_irqs, CICR, lch); 583 p->dma_write(dma_chan[lch].enabled_irqs, CICR, lch);
586} 584}
587 585
588static void omap_disable_channel_irq(int lch) 586static inline void omap_disable_channel_irq(int lch)
589{ 587{
590 if (cpu_class_is_omap2()) 588 /* disable channel interrupts */
591 p->dma_write(0, CICR, lch); 589 p->dma_write(0, CICR, lch);
590 /* Clear CSR */
591 if (cpu_class_is_omap1())
592 p->dma_read(CSR, lch);
593 else
594 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
592} 595}
593 596
594void omap_enable_dma_irq(int lch, u16 bits) 597void omap_enable_dma_irq(int lch, u16 bits)
@@ -632,14 +635,14 @@ static inline void disable_lnk(int lch)
632 l = p->dma_read(CLNK_CTRL, lch); 635 l = p->dma_read(CLNK_CTRL, lch);
633 636
634 /* Disable interrupts */ 637 /* Disable interrupts */
638 omap_disable_channel_irq(lch);
639
635 if (cpu_class_is_omap1()) { 640 if (cpu_class_is_omap1()) {
636 p->dma_write(0, CICR, lch);
637 /* Set the STOP_LNK bit */ 641 /* Set the STOP_LNK bit */
638 l |= 1 << 14; 642 l |= 1 << 14;
639 } 643 }
640 644
641 if (cpu_class_is_omap2()) { 645 if (cpu_class_is_omap2()) {
642 omap_disable_channel_irq(lch);
643 /* Clear the ENABLE_LNK bit */ 646 /* Clear the ENABLE_LNK bit */
644 l &= ~(1 << 15); 647 l &= ~(1 << 15);
645 } 648 }
@@ -657,6 +660,9 @@ static inline void omap2_enable_irq_lch(int lch)
657 return; 660 return;
658 661
659 spin_lock_irqsave(&dma_chan_lock, flags); 662 spin_lock_irqsave(&dma_chan_lock, flags);
663 /* clear IRQ STATUS */
664 p->dma_write(1 << lch, IRQSTATUS_L0, lch);
665 /* Enable interrupt */
660 val = p->dma_read(IRQENABLE_L0, lch); 666 val = p->dma_read(IRQENABLE_L0, lch);
661 val |= 1 << lch; 667 val |= 1 << lch;
662 p->dma_write(val, IRQENABLE_L0, lch); 668 p->dma_write(val, IRQENABLE_L0, lch);
@@ -672,9 +678,12 @@ static inline void omap2_disable_irq_lch(int lch)
672 return; 678 return;
673 679
674 spin_lock_irqsave(&dma_chan_lock, flags); 680 spin_lock_irqsave(&dma_chan_lock, flags);
681 /* Disable interrupt */
675 val = p->dma_read(IRQENABLE_L0, lch); 682 val = p->dma_read(IRQENABLE_L0, lch);
676 val &= ~(1 << lch); 683 val &= ~(1 << lch);
677 p->dma_write(val, IRQENABLE_L0, lch); 684 p->dma_write(val, IRQENABLE_L0, lch);
685 /* clear IRQ STATUS */
686 p->dma_write(1 << lch, IRQSTATUS_L0, lch);
678 spin_unlock_irqrestore(&dma_chan_lock, flags); 687 spin_unlock_irqrestore(&dma_chan_lock, flags);
679} 688}
680 689
@@ -745,11 +754,8 @@ int omap_request_dma(int dev_id, const char *dev_name,
745 } 754 }
746 755
747 if (cpu_class_is_omap2()) { 756 if (cpu_class_is_omap2()) {
748 omap2_enable_irq_lch(free_ch);
749 omap_enable_channel_irq(free_ch); 757 omap_enable_channel_irq(free_ch);
750 /* Clear the CSR register and IRQ status register */ 758 omap2_enable_irq_lch(free_ch);
751 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, free_ch);
752 p->dma_write(1 << free_ch, IRQSTATUS_L0, 0);
753 } 759 }
754 760
755 *dma_ch_out = free_ch; 761 *dma_ch_out = free_ch;
@@ -768,27 +774,19 @@ void omap_free_dma(int lch)
768 return; 774 return;
769 } 775 }
770 776
771 if (cpu_class_is_omap1()) { 777 /* Disable interrupt for logical channel */
772 /* Disable all DMA interrupts for the channel. */ 778 if (cpu_class_is_omap2())
773 p->dma_write(0, CICR, lch);
774 /* Make sure the DMA transfer is stopped. */
775 p->dma_write(0, CCR, lch);
776 }
777
778 if (cpu_class_is_omap2()) {
779 omap2_disable_irq_lch(lch); 779 omap2_disable_irq_lch(lch);
780 780
781 /* Clear the CSR register and IRQ status register */ 781 /* Disable all DMA interrupts for the channel. */
782 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch); 782 omap_disable_channel_irq(lch);
783 p->dma_write(1 << lch, IRQSTATUS_L0, lch);
784 783
785 /* Disable all DMA interrupts for the channel. */ 784 /* Make sure the DMA transfer is stopped. */
786 p->dma_write(0, CICR, lch); 785 p->dma_write(0, CCR, lch);
787 786
788 /* Make sure the DMA transfer is stopped. */ 787 /* Clear registers */
789 p->dma_write(0, CCR, lch); 788 if (cpu_class_is_omap2())
790 omap_clear_dma(lch); 789 omap_clear_dma(lch);
791 }
792 790
793 spin_lock_irqsave(&dma_chan_lock, flags); 791 spin_lock_irqsave(&dma_chan_lock, flags);
794 dma_chan[lch].dev_id = -1; 792 dma_chan[lch].dev_id = -1;
@@ -943,8 +941,7 @@ void omap_stop_dma(int lch)
943 u32 l; 941 u32 l;
944 942
945 /* Disable all interrupts on the channel */ 943 /* Disable all interrupts on the channel */
946 if (cpu_class_is_omap1()) 944 omap_disable_channel_irq(lch);
947 p->dma_write(0, CICR, lch);
948 945
949 l = p->dma_read(CCR, lch); 946 l = p->dma_read(CCR, lch);
950 if (IS_DMA_ERRATA(DMA_ERRATA_i541) && 947 if (IS_DMA_ERRATA(DMA_ERRATA_i541) &&
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 3b0cfeb33d0..54ed4e6e429 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -42,9 +42,11 @@
42#include <linux/pm_runtime.h> 42#include <linux/pm_runtime.h>
43 43
44#include <plat/dmtimer.h> 44#include <plat/dmtimer.h>
45#include <plat/omap-pm.h>
45 46
46#include <mach/hardware.h> 47#include <mach/hardware.h>
47 48
49static u32 omap_reserved_systimers;
48static LIST_HEAD(omap_timer_list); 50static LIST_HEAD(omap_timer_list);
49static DEFINE_SPINLOCK(dm_timer_lock); 51static DEFINE_SPINLOCK(dm_timer_lock);
50 52
@@ -133,17 +135,22 @@ static void omap_dm_timer_reset(struct omap_dm_timer *timer)
133 135
134int omap_dm_timer_prepare(struct omap_dm_timer *timer) 136int omap_dm_timer_prepare(struct omap_dm_timer *timer)
135{ 137{
136 struct dmtimer_platform_data *pdata = timer->pdev->dev.platform_data;
137 int ret; 138 int ret;
138 139
139 timer->fclk = clk_get(&timer->pdev->dev, "fck"); 140 /*
140 if (WARN_ON_ONCE(IS_ERR_OR_NULL(timer->fclk))) { 141 * FIXME: OMAP1 devices do not use the clock framework for dmtimers so
141 timer->fclk = NULL; 142 * do not call clk_get() for these devices.
142 dev_err(&timer->pdev->dev, ": No fclk handle.\n"); 143 */
143 return -EINVAL; 144 if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) {
145 timer->fclk = clk_get(&timer->pdev->dev, "fck");
146 if (WARN_ON_ONCE(IS_ERR_OR_NULL(timer->fclk))) {
147 timer->fclk = NULL;
148 dev_err(&timer->pdev->dev, ": No fclk handle.\n");
149 return -EINVAL;
150 }
144 } 151 }
145 152
146 if (pdata->needs_manual_reset) 153 if (timer->capability & OMAP_TIMER_NEEDS_RESET)
147 omap_dm_timer_reset(timer); 154 omap_dm_timer_reset(timer);
148 155
149 ret = omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ); 156 ret = omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ);
@@ -152,6 +159,21 @@ int omap_dm_timer_prepare(struct omap_dm_timer *timer)
152 return ret; 159 return ret;
153} 160}
154 161
162static inline u32 omap_dm_timer_reserved_systimer(int id)
163{
164 return (omap_reserved_systimers & (1 << (id - 1))) ? 1 : 0;
165}
166
167int omap_dm_timer_reserve_systimer(int id)
168{
169 if (omap_dm_timer_reserved_systimer(id))
170 return -ENODEV;
171
172 omap_reserved_systimers |= (1 << (id - 1));
173
174 return 0;
175}
176
155struct omap_dm_timer *omap_dm_timer_request(void) 177struct omap_dm_timer *omap_dm_timer_request(void)
156{ 178{
157 struct omap_dm_timer *timer = NULL, *t; 179 struct omap_dm_timer *timer = NULL, *t;
@@ -325,10 +347,9 @@ int omap_dm_timer_start(struct omap_dm_timer *timer)
325 347
326 omap_dm_timer_enable(timer); 348 omap_dm_timer_enable(timer);
327 349
328 if (timer->loses_context) { 350 if (!(timer->capability & OMAP_TIMER_ALWON)) {
329 u32 ctx_loss_cnt_after = 351 if (omap_pm_get_dev_context_loss_count(&timer->pdev->dev) !=
330 timer->get_context_loss_count(&timer->pdev->dev); 352 timer->ctx_loss_count)
331 if (ctx_loss_cnt_after != timer->ctx_loss_count)
332 omap_timer_restore_context(timer); 353 omap_timer_restore_context(timer);
333 } 354 }
334 355
@@ -347,20 +368,18 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_start);
347int omap_dm_timer_stop(struct omap_dm_timer *timer) 368int omap_dm_timer_stop(struct omap_dm_timer *timer)
348{ 369{
349 unsigned long rate = 0; 370 unsigned long rate = 0;
350 struct dmtimer_platform_data *pdata;
351 371
352 if (unlikely(!timer)) 372 if (unlikely(!timer))
353 return -EINVAL; 373 return -EINVAL;
354 374
355 pdata = timer->pdev->dev.platform_data; 375 if (!(timer->capability & OMAP_TIMER_NEEDS_RESET))
356 if (!pdata->needs_manual_reset)
357 rate = clk_get_rate(timer->fclk); 376 rate = clk_get_rate(timer->fclk);
358 377
359 __omap_dm_timer_stop(timer, timer->posted, rate); 378 __omap_dm_timer_stop(timer, timer->posted, rate);
360 379
361 if (timer->loses_context && timer->get_context_loss_count) 380 if (!(timer->capability & OMAP_TIMER_ALWON))
362 timer->ctx_loss_count = 381 timer->ctx_loss_count =
363 timer->get_context_loss_count(&timer->pdev->dev); 382 omap_pm_get_dev_context_loss_count(&timer->pdev->dev);
364 383
365 /* 384 /*
366 * Since the register values are computed and written within 385 * Since the register values are computed and written within
@@ -378,6 +397,8 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_stop);
378int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source) 397int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
379{ 398{
380 int ret; 399 int ret;
400 char *parent_name = NULL;
401 struct clk *fclk, *parent;
381 struct dmtimer_platform_data *pdata; 402 struct dmtimer_platform_data *pdata;
382 403
383 if (unlikely(!timer)) 404 if (unlikely(!timer))
@@ -388,7 +409,49 @@ int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
388 if (source < 0 || source >= 3) 409 if (source < 0 || source >= 3)
389 return -EINVAL; 410 return -EINVAL;
390 411
391 ret = pdata->set_timer_src(timer->pdev, source); 412 /*
413 * FIXME: Used for OMAP1 devices only because they do not currently
414 * use the clock framework to set the parent clock. To be removed
415 * once OMAP1 migrated to using clock framework for dmtimers
416 */
417 if (pdata->set_timer_src)
418 return pdata->set_timer_src(timer->pdev, source);
419
420 fclk = clk_get(&timer->pdev->dev, "fck");
421 if (IS_ERR_OR_NULL(fclk)) {
422 pr_err("%s: fck not found\n", __func__);
423 return -EINVAL;
424 }
425
426 switch (source) {
427 case OMAP_TIMER_SRC_SYS_CLK:
428 parent_name = "timer_sys_ck";
429 break;
430
431 case OMAP_TIMER_SRC_32_KHZ:
432 parent_name = "timer_32k_ck";
433 break;
434
435 case OMAP_TIMER_SRC_EXT_CLK:
436 parent_name = "timer_ext_ck";
437 break;
438 }
439
440 parent = clk_get(&timer->pdev->dev, parent_name);
441 if (IS_ERR_OR_NULL(parent)) {
442 pr_err("%s: %s not found\n", __func__, parent_name);
443 ret = -EINVAL;
444 goto out;
445 }
446
447 ret = clk_set_parent(fclk, parent);
448 if (IS_ERR_VALUE(ret))
449 pr_err("%s: failed to set %s as parent\n", __func__,
450 parent_name);
451
452 clk_put(parent);
453out:
454 clk_put(fclk);
392 455
393 return ret; 456 return ret;
394} 457}
@@ -431,10 +494,9 @@ int omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload,
431 494
432 omap_dm_timer_enable(timer); 495 omap_dm_timer_enable(timer);
433 496
434 if (timer->loses_context) { 497 if (!(timer->capability & OMAP_TIMER_ALWON)) {
435 u32 ctx_loss_cnt_after = 498 if (omap_pm_get_dev_context_loss_count(&timer->pdev->dev) !=
436 timer->get_context_loss_count(&timer->pdev->dev); 499 timer->ctx_loss_count)
437 if (ctx_loss_cnt_after != timer->ctx_loss_count)
438 omap_timer_restore_context(timer); 500 omap_timer_restore_context(timer);
439 } 501 }
440 502
@@ -674,13 +736,12 @@ static int __devinit omap_dm_timer_probe(struct platform_device *pdev)
674 736
675 timer->id = pdev->id; 737 timer->id = pdev->id;
676 timer->irq = irq->start; 738 timer->irq = irq->start;
677 timer->reserved = pdata->reserved; 739 timer->reserved = omap_dm_timer_reserved_systimer(timer->id);
678 timer->pdev = pdev; 740 timer->pdev = pdev;
679 timer->loses_context = pdata->loses_context; 741 timer->capability = pdata->timer_capability;
680 timer->get_context_loss_count = pdata->get_context_loss_count;
681 742
682 /* Skip pm_runtime_enable for OMAP1 */ 743 /* Skip pm_runtime_enable for OMAP1 */
683 if (!pdata->needs_manual_reset) { 744 if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) {
684 pm_runtime_enable(&pdev->dev); 745 pm_runtime_enable(&pdev->dev);
685 pm_runtime_irq_safe(&pdev->dev); 746 pm_runtime_irq_safe(&pdev->dev);
686 } 747 }
diff --git a/arch/arm/plat-omap/include/plat/board.h b/arch/arm/plat-omap/include/plat/board.h
index 4814c5b6530..e62f20a5c0a 100644
--- a/arch/arm/plat-omap/include/plat/board.h
+++ b/arch/arm/plat-omap/include/plat/board.h
@@ -57,44 +57,6 @@ struct omap_camera_sensor_config {
57 int (*power_off)(void * data); 57 int (*power_off)(void * data);
58}; 58};
59 59
60struct omap_usb_config {
61 /* Configure drivers according to the connectors on your board:
62 * - "A" connector (rectagular)
63 * ... for host/OHCI use, set "register_host".
64 * - "B" connector (squarish) or "Mini-B"
65 * ... for device/gadget use, set "register_dev".
66 * - "Mini-AB" connector (very similar to Mini-B)
67 * ... for OTG use as device OR host, initialize "otg"
68 */
69 unsigned register_host:1;
70 unsigned register_dev:1;
71 u8 otg; /* port number, 1-based: usb1 == 2 */
72
73 u8 hmc_mode;
74
75 /* implicitly true if otg: host supports remote wakeup? */
76 u8 rwc;
77
78 /* signaling pins used to talk to transceiver on usbN:
79 * 0 == usbN unused
80 * 2 == usb0-only, using internal transceiver
81 * 3 == 3 wire bidirectional
82 * 4 == 4 wire bidirectional
83 * 6 == 6 wire unidirectional (or TLL)
84 */
85 u8 pins[3];
86
87 struct platform_device *udc_device;
88 struct platform_device *ohci_device;
89 struct platform_device *otg_device;
90
91 u32 (*usb0_init)(unsigned nwires, unsigned is_device);
92 u32 (*usb1_init)(unsigned nwires);
93 u32 (*usb2_init)(unsigned nwires, unsigned alt_pingroup);
94
95 int (*ocpi_enable)(void);
96};
97
98struct omap_lcd_config { 60struct omap_lcd_config {
99 char panel_name[16]; 61 char panel_name[16];
100 char ctrl_name[16]; 62 char ctrl_name[16];
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index d0ef57c1d71..656b9862279 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -156,7 +156,6 @@ struct dpll_data {
156 u8 min_divider; 156 u8 min_divider;
157 u16 max_divider; 157 u16 max_divider;
158 u8 modes; 158 u8 modes;
159#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
160 void __iomem *autoidle_reg; 159 void __iomem *autoidle_reg;
161 void __iomem *idlest_reg; 160 void __iomem *idlest_reg;
162 u32 autoidle_mask; 161 u32 autoidle_mask;
@@ -167,7 +166,6 @@ struct dpll_data {
167 u8 auto_recal_bit; 166 u8 auto_recal_bit;
168 u8 recal_en_bit; 167 u8 recal_en_bit;
169 u8 recal_st_bit; 168 u8 recal_st_bit;
170# endif
171 u8 flags; 169 u8 flags;
172}; 170};
173 171
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
index 5da73562e48..19e7fa577bd 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -55,23 +55,17 @@
55#define OMAP_TIMER_TRIGGER_OVERFLOW 0x01 55#define OMAP_TIMER_TRIGGER_OVERFLOW 0x01
56#define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02 56#define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02
57 57
58/*
59 * IP revision identifier so that Highlander IP
60 * in OMAP4 can be distinguished.
61 */
62#define OMAP_TIMER_IP_VERSION_1 0x1
63
64/* timer capabilities used in hwmod database */ 58/* timer capabilities used in hwmod database */
65#define OMAP_TIMER_SECURE 0x80000000 59#define OMAP_TIMER_SECURE 0x80000000
66#define OMAP_TIMER_ALWON 0x40000000 60#define OMAP_TIMER_ALWON 0x40000000
67#define OMAP_TIMER_HAS_PWM 0x20000000 61#define OMAP_TIMER_HAS_PWM 0x20000000
62#define OMAP_TIMER_NEEDS_RESET 0x10000000
68 63
69struct omap_timer_capability_dev_attr { 64struct omap_timer_capability_dev_attr {
70 u32 timer_capability; 65 u32 timer_capability;
71}; 66};
72 67
73struct omap_dm_timer; 68struct omap_dm_timer;
74struct clk;
75 69
76struct timer_regs { 70struct timer_regs {
77 u32 tidr; 71 u32 tidr;
@@ -96,16 +90,12 @@ struct timer_regs {
96}; 90};
97 91
98struct dmtimer_platform_data { 92struct dmtimer_platform_data {
93 /* set_timer_src - Only used for OMAP1 devices */
99 int (*set_timer_src)(struct platform_device *pdev, int source); 94 int (*set_timer_src)(struct platform_device *pdev, int source);
100 int timer_ip_version; 95 u32 timer_capability;
101 u32 needs_manual_reset:1;
102 bool reserved;
103
104 bool loses_context;
105
106 int (*get_context_loss_count)(struct device *dev);
107}; 96};
108 97
98int omap_dm_timer_reserve_systimer(int id);
109struct omap_dm_timer *omap_dm_timer_request(void); 99struct omap_dm_timer *omap_dm_timer_request(void);
110struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id); 100struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id);
111int omap_dm_timer_free(struct omap_dm_timer *timer); 101int omap_dm_timer_free(struct omap_dm_timer *timer);
@@ -272,13 +262,11 @@ struct omap_dm_timer {
272 unsigned reserved:1; 262 unsigned reserved:1;
273 unsigned posted:1; 263 unsigned posted:1;
274 struct timer_regs context; 264 struct timer_regs context;
275 bool loses_context;
276 int ctx_loss_count; 265 int ctx_loss_count;
277 int revision; 266 int revision;
267 u32 capability;
278 struct platform_device *pdev; 268 struct platform_device *pdev;
279 struct list_head node; 269 struct list_head node;
280
281 int (*get_context_loss_count)(struct device *dev);
282}; 270};
283 271
284int omap_dm_timer_prepare(struct omap_dm_timer *timer); 272int omap_dm_timer_prepare(struct omap_dm_timer *timer);
diff --git a/arch/arm/plat-omap/include/plat/dsp.h b/arch/arm/plat-omap/include/plat/dsp.h
index 9c604b390f9..5927709b190 100644
--- a/arch/arm/plat-omap/include/plat/dsp.h
+++ b/arch/arm/plat-omap/include/plat/dsp.h
@@ -18,6 +18,9 @@ struct omap_dsp_platform_data {
18 u32 (*dsp_cm_read)(s16 , u16); 18 u32 (*dsp_cm_read)(s16 , u16);
19 u32 (*dsp_cm_rmw_bits)(u32, u32, s16, s16); 19 u32 (*dsp_cm_rmw_bits)(u32, u32, s16, s16);
20 20
21 void (*set_bootaddr)(u32);
22 void (*set_bootmode)(u8);
23
21 phys_addr_t phys_mempool_base; 24 phys_addr_t phys_mempool_base;
22 phys_addr_t phys_mempool_size; 25 phys_addr_t phys_mempool_size;
23}; 26};
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index c835b7194ff..a8ecc53b367 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -629,6 +629,8 @@ int omap_hwmod_no_setup_reset(struct omap_hwmod *oh);
629 629
630int omap_hwmod_pad_route_irq(struct omap_hwmod *oh, int pad_idx, int irq_idx); 630int omap_hwmod_pad_route_irq(struct omap_hwmod *oh, int pad_idx, int irq_idx);
631 631
632extern void __init omap_hwmod_init(void);
633
632/* 634/*
633 * Chip variant-specific hwmod init routines - XXX should be converted 635 * Chip variant-specific hwmod init routines - XXX should be converted
634 * to use initcalls once the initial boot ordering is straightened out 636 * to use initcalls once the initial boot ordering is straightened out
diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h
index b073e5f2b19..28e2d250c2f 100644
--- a/arch/arm/plat-omap/include/plat/serial.h
+++ b/arch/arm/plat-omap/include/plat/serial.h
@@ -60,6 +60,9 @@
60/* AM3505/3517 UART4 */ 60/* AM3505/3517 UART4 */
61#define AM35XX_UART4_BASE 0x4809E000 /* Only on AM3505/3517 */ 61#define AM35XX_UART4_BASE 0x4809E000 /* Only on AM3505/3517 */
62 62
63/* AM33XX serial port */
64#define AM33XX_UART1_BASE 0x44E09000
65
63/* External port on Zoom2/3 */ 66/* External port on Zoom2/3 */
64#define ZOOM_UART_BASE 0x10000000 67#define ZOOM_UART_BASE 0x10000000
65#define ZOOM_UART_VIRT 0xfa400000 68#define ZOOM_UART_VIRT 0xfa400000
@@ -93,6 +96,7 @@
93#define TI81XXUART1 81 96#define TI81XXUART1 81
94#define TI81XXUART2 82 97#define TI81XXUART2 82
95#define TI81XXUART3 83 98#define TI81XXUART3 83
99#define AM33XXUART1 84
96#define ZOOM_UART 95 /* Only on zoom2/3 */ 100#define ZOOM_UART 95 /* Only on zoom2/3 */
97 101
98/* This is only used by 8250.c for omap1510 */ 102/* This is only used by 8250.c for omap1510 */
diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h
index cc3f11ba7a9..ac432339021 100644
--- a/arch/arm/plat-omap/include/plat/uncompress.h
+++ b/arch/arm/plat-omap/include/plat/uncompress.h
@@ -103,6 +103,10 @@ static inline void flush(void)
103 _DEBUG_LL_ENTRY(mach, TI81XX_UART##p##_BASE, OMAP_PORT_SHIFT, \ 103 _DEBUG_LL_ENTRY(mach, TI81XX_UART##p##_BASE, OMAP_PORT_SHIFT, \
104 TI81XXUART##p) 104 TI81XXUART##p)
105 105
106#define DEBUG_LL_AM33XX(p, mach) \
107 _DEBUG_LL_ENTRY(mach, AM33XX_UART##p##_BASE, OMAP_PORT_SHIFT, \
108 AM33XXUART##p)
109
106static inline void __arch_decomp_setup(unsigned long arch_id) 110static inline void __arch_decomp_setup(unsigned long arch_id)
107{ 111{
108 int port = 0; 112 int port = 0;
@@ -183,6 +187,8 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
183 /* TI8148 base boards using UART1 */ 187 /* TI8148 base boards using UART1 */
184 DEBUG_LL_TI81XX(1, ti8148evm); 188 DEBUG_LL_TI81XX(1, ti8148evm);
185 189
190 /* AM33XX base boards using UART1 */
191 DEBUG_LL_AM33XX(1, am335xevm);
186 } while (0); 192 } while (0);
187} 193}
188 194
diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h
index 762eeb0626c..548a4c8d63d 100644
--- a/arch/arm/plat-omap/include/plat/usb.h
+++ b/arch/arm/plat-omap/include/plat/usb.h
@@ -44,6 +44,8 @@ struct usbhs_omap_board_data {
44 struct regulator *regulator[OMAP3_HS_USB_PORTS]; 44 struct regulator *regulator[OMAP3_HS_USB_PORTS];
45}; 45};
46 46
47#ifdef CONFIG_ARCH_OMAP2PLUS
48
47struct ehci_hcd_omap_platform_data { 49struct ehci_hcd_omap_platform_data {
48 enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS]; 50 enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS];
49 int reset_gpio_port[OMAP3_HS_USB_PORTS]; 51 int reset_gpio_port[OMAP3_HS_USB_PORTS];
@@ -64,26 +66,6 @@ struct usbhs_omap_platform_data {
64}; 66};
65/*-------------------------------------------------------------------------*/ 67/*-------------------------------------------------------------------------*/
66 68
67#define OMAP1_OTG_BASE 0xfffb0400
68#define OMAP1_UDC_BASE 0xfffb4000
69#define OMAP1_OHCI_BASE 0xfffba000
70
71#define OMAP2_OHCI_BASE 0x4805e000
72#define OMAP2_UDC_BASE 0x4805e200
73#define OMAP2_OTG_BASE 0x4805e300
74
75#ifdef CONFIG_ARCH_OMAP1
76
77#define OTG_BASE OMAP1_OTG_BASE
78#define UDC_BASE OMAP1_UDC_BASE
79#define OMAP_OHCI_BASE OMAP1_OHCI_BASE
80
81#else
82
83#define OTG_BASE OMAP2_OTG_BASE
84#define UDC_BASE OMAP2_UDC_BASE
85#define OMAP_OHCI_BASE OMAP2_OHCI_BASE
86
87struct omap_musb_board_data { 69struct omap_musb_board_data {
88 u8 interface_type; 70 u8 interface_type;
89 u8 mode; 71 u8 mode;
@@ -107,44 +89,6 @@ extern int omap4430_phy_init(struct device *dev);
107extern int omap4430_phy_exit(struct device *dev); 89extern int omap4430_phy_exit(struct device *dev);
108extern int omap4430_phy_suspend(struct device *dev, int suspend); 90extern int omap4430_phy_suspend(struct device *dev, int suspend);
109 91
110/*
111 * NOTE: Please update omap USB drivers to use ioremap + read/write
112 */
113
114#define OMAP2_L4_IO_OFFSET 0xb2000000
115#define OMAP2_L4_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L4_IO_OFFSET)
116
117static inline u8 omap_readb(u32 pa)
118{
119 return __raw_readb(OMAP2_L4_IO_ADDRESS(pa));
120}
121
122static inline u16 omap_readw(u32 pa)
123{
124 return __raw_readw(OMAP2_L4_IO_ADDRESS(pa));
125}
126
127static inline u32 omap_readl(u32 pa)
128{
129 return __raw_readl(OMAP2_L4_IO_ADDRESS(pa));
130}
131
132static inline void omap_writeb(u8 v, u32 pa)
133{
134 __raw_writeb(v, OMAP2_L4_IO_ADDRESS(pa));
135}
136
137
138static inline void omap_writew(u16 v, u32 pa)
139{
140 __raw_writew(v, OMAP2_L4_IO_ADDRESS(pa));
141}
142
143static inline void omap_writel(u32 v, u32 pa)
144{
145 __raw_writel(v, OMAP2_L4_IO_ADDRESS(pa));
146}
147
148#endif 92#endif
149 93
150extern void am35x_musb_reset(void); 94extern void am35x_musb_reset(void);
@@ -153,142 +97,6 @@ extern void am35x_musb_clear_irq(void);
153extern void am35x_set_mode(u8 musb_mode); 97extern void am35x_set_mode(u8 musb_mode);
154extern void ti81xx_musb_phy_power(u8 on); 98extern void ti81xx_musb_phy_power(u8 on);
155 99
156/*
157 * FIXME correct answer depends on hmc_mode,
158 * as does (on omap1) any nonzero value for config->otg port number
159 */
160#ifdef CONFIG_USB_GADGET_OMAP
161#define is_usb0_device(config) 1
162#else
163#define is_usb0_device(config) 0
164#endif
165
166void omap_otg_init(struct omap_usb_config *config);
167
168#if defined(CONFIG_USB) || defined(CONFIG_USB_MODULE)
169void omap1_usb_init(struct omap_usb_config *pdata);
170#else
171static inline void omap1_usb_init(struct omap_usb_config *pdata)
172{
173}
174#endif
175
176#if defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_ARCH_OMAP_OTG_MODULE)
177void omap2_usbfs_init(struct omap_usb_config *pdata);
178#else
179static inline void omap2_usbfs_init(struct omap_usb_config *pdata)
180{
181}
182#endif
183
184/*-------------------------------------------------------------------------*/
185
186/*
187 * OTG and transceiver registers, for OMAPs starting with ARM926
188 */
189#define OTG_REV (OTG_BASE + 0x00)
190#define OTG_SYSCON_1 (OTG_BASE + 0x04)
191# define USB2_TRX_MODE(w) (((w)>>24)&0x07)
192# define USB1_TRX_MODE(w) (((w)>>20)&0x07)
193# define USB0_TRX_MODE(w) (((w)>>16)&0x07)
194# define OTG_IDLE_EN (1 << 15)
195# define HST_IDLE_EN (1 << 14)
196# define DEV_IDLE_EN (1 << 13)
197# define OTG_RESET_DONE (1 << 2)
198# define OTG_SOFT_RESET (1 << 1)
199#define OTG_SYSCON_2 (OTG_BASE + 0x08)
200# define OTG_EN (1 << 31)
201# define USBX_SYNCHRO (1 << 30)
202# define OTG_MST16 (1 << 29)
203# define SRP_GPDATA (1 << 28)
204# define SRP_GPDVBUS (1 << 27)
205# define SRP_GPUVBUS(w) (((w)>>24)&0x07)
206# define A_WAIT_VRISE(w) (((w)>>20)&0x07)
207# define B_ASE_BRST(w) (((w)>>16)&0x07)
208# define SRP_DPW (1 << 14)
209# define SRP_DATA (1 << 13)
210# define SRP_VBUS (1 << 12)
211# define OTG_PADEN (1 << 10)
212# define HMC_PADEN (1 << 9)
213# define UHOST_EN (1 << 8)
214# define HMC_TLLSPEED (1 << 7)
215# define HMC_TLLATTACH (1 << 6)
216# define OTG_HMC(w) (((w)>>0)&0x3f)
217#define OTG_CTRL (OTG_BASE + 0x0c)
218# define OTG_USB2_EN (1 << 29)
219# define OTG_USB2_DP (1 << 28)
220# define OTG_USB2_DM (1 << 27)
221# define OTG_USB1_EN (1 << 26)
222# define OTG_USB1_DP (1 << 25)
223# define OTG_USB1_DM (1 << 24)
224# define OTG_USB0_EN (1 << 23)
225# define OTG_USB0_DP (1 << 22)
226# define OTG_USB0_DM (1 << 21)
227# define OTG_ASESSVLD (1 << 20)
228# define OTG_BSESSEND (1 << 19)
229# define OTG_BSESSVLD (1 << 18)
230# define OTG_VBUSVLD (1 << 17)
231# define OTG_ID (1 << 16)
232# define OTG_DRIVER_SEL (1 << 15)
233# define OTG_A_SETB_HNPEN (1 << 12)
234# define OTG_A_BUSREQ (1 << 11)
235# define OTG_B_HNPEN (1 << 9)
236# define OTG_B_BUSREQ (1 << 8)
237# define OTG_BUSDROP (1 << 7)
238# define OTG_PULLDOWN (1 << 5)
239# define OTG_PULLUP (1 << 4)
240# define OTG_DRV_VBUS (1 << 3)
241# define OTG_PD_VBUS (1 << 2)
242# define OTG_PU_VBUS (1 << 1)
243# define OTG_PU_ID (1 << 0)
244#define OTG_IRQ_EN (OTG_BASE + 0x10) /* 16-bit */
245# define DRIVER_SWITCH (1 << 15)
246# define A_VBUS_ERR (1 << 13)
247# define A_REQ_TMROUT (1 << 12)
248# define A_SRP_DETECT (1 << 11)
249# define B_HNP_FAIL (1 << 10)
250# define B_SRP_TMROUT (1 << 9)
251# define B_SRP_DONE (1 << 8)
252# define B_SRP_STARTED (1 << 7)
253# define OPRT_CHG (1 << 0)
254#define OTG_IRQ_SRC (OTG_BASE + 0x14) /* 16-bit */
255 // same bits as in IRQ_EN
256#define OTG_OUTCTRL (OTG_BASE + 0x18) /* 16-bit */
257# define OTGVPD (1 << 14)
258# define OTGVPU (1 << 13)
259# define OTGPUID (1 << 12)
260# define USB2VDR (1 << 10)
261# define USB2PDEN (1 << 9)
262# define USB2PUEN (1 << 8)
263# define USB1VDR (1 << 6)
264# define USB1PDEN (1 << 5)
265# define USB1PUEN (1 << 4)
266# define USB0VDR (1 << 2)
267# define USB0PDEN (1 << 1)
268# define USB0PUEN (1 << 0)
269#define OTG_TEST (OTG_BASE + 0x20) /* 16-bit */
270#define OTG_VENDOR_CODE (OTG_BASE + 0xfc) /* 16-bit */
271
272/*-------------------------------------------------------------------------*/
273
274/* OMAP1 */
275#define USB_TRANSCEIVER_CTRL (0xfffe1000 + 0x0064)
276# define CONF_USB2_UNI_R (1 << 8)
277# define CONF_USB1_UNI_R (1 << 7)
278# define CONF_USB_PORT0_R(x) (((x)>>4)&0x7)
279# define CONF_USB0_ISOLATE_R (1 << 3)
280# define CONF_USB_PWRDN_DM_R (1 << 2)
281# define CONF_USB_PWRDN_DP_R (1 << 1)
282
283/* OMAP2 */
284# define USB_UNIDIR 0x0
285# define USB_UNIDIR_TLL 0x1
286# define USB_BIDIR 0x2
287# define USB_BIDIR_TLL 0x3
288# define USBTXWRMODEI(port, x) ((x) << (22 - (port * 2)))
289# define USBT2TLL5PI (1 << 17)
290# define USB0PUENACTLOI (1 << 16)
291# define USBSTANDBYCTRL (1 << 15)
292/* AM35x */ 100/* AM35x */
293/* USB 2.0 PHY Control */ 101/* USB 2.0 PHY Control */
294#define CONF2_PHY_GPIOMODE (1 << 23) 102#define CONF2_PHY_GPIOMODE (1 << 23)
diff --git a/arch/arm/plat-omap/usb.c b/arch/arm/plat-omap/usb.c
deleted file mode 100644
index daa0327381b..00000000000
--- a/arch/arm/plat-omap/usb.c
+++ /dev/null
@@ -1,145 +0,0 @@
1 /*
2 * arch/arm/plat-omap/usb.c -- platform level USB initialization
3 *
4 * Copyright (C) 2004 Texas Instruments, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#undef DEBUG
22
23#include <linux/module.h>
24#include <linux/kernel.h>
25#include <linux/init.h>
26#include <linux/platform_device.h>
27#include <linux/io.h>
28
29#include <plat/usb.h>
30#include <plat/board.h>
31
32#include <mach/hardware.h>
33
34#ifdef CONFIG_ARCH_OMAP_OTG
35
36void __init
37omap_otg_init(struct omap_usb_config *config)
38{
39 u32 syscon;
40 int alt_pingroup = 0;
41
42 /* NOTE: no bus or clock setup (yet?) */
43
44 syscon = omap_readl(OTG_SYSCON_1) & 0xffff;
45 if (!(syscon & OTG_RESET_DONE))
46 pr_debug("USB resets not complete?\n");
47
48 //omap_writew(0, OTG_IRQ_EN);
49
50 /* pin muxing and transceiver pinouts */
51 if (config->pins[0] > 2) /* alt pingroup 2 */
52 alt_pingroup = 1;
53 syscon |= config->usb0_init(config->pins[0], is_usb0_device(config));
54 syscon |= config->usb1_init(config->pins[1]);
55 syscon |= config->usb2_init(config->pins[2], alt_pingroup);
56 pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1));
57 omap_writel(syscon, OTG_SYSCON_1);
58
59 syscon = config->hmc_mode;
60 syscon |= USBX_SYNCHRO | (4 << 16) /* B_ASE0_BRST */;
61#ifdef CONFIG_USB_OTG
62 if (config->otg)
63 syscon |= OTG_EN;
64#endif
65 if (cpu_class_is_omap1())
66 pr_debug("USB_TRANSCEIVER_CTRL = %03x\n",
67 omap_readl(USB_TRANSCEIVER_CTRL));
68 pr_debug("OTG_SYSCON_2 = %08x\n", omap_readl(OTG_SYSCON_2));
69 omap_writel(syscon, OTG_SYSCON_2);
70
71 printk("USB: hmc %d", config->hmc_mode);
72 if (!alt_pingroup)
73 printk(", usb2 alt %d wires", config->pins[2]);
74 else if (config->pins[0])
75 printk(", usb0 %d wires%s", config->pins[0],
76 is_usb0_device(config) ? " (dev)" : "");
77 if (config->pins[1])
78 printk(", usb1 %d wires", config->pins[1]);
79 if (!alt_pingroup && config->pins[2])
80 printk(", usb2 %d wires", config->pins[2]);
81 if (config->otg)
82 printk(", Mini-AB on usb%d", config->otg - 1);
83 printk("\n");
84
85 if (cpu_class_is_omap1()) {
86 u16 w;
87
88 /* leave USB clocks/controllers off until needed */
89 w = omap_readw(ULPD_SOFT_REQ);
90 w &= ~SOFT_USB_CLK_REQ;
91 omap_writew(w, ULPD_SOFT_REQ);
92
93 w = omap_readw(ULPD_CLOCK_CTRL);
94 w &= ~USB_MCLK_EN;
95 w |= DIS_USB_PVCI_CLK;
96 omap_writew(w, ULPD_CLOCK_CTRL);
97 }
98 syscon = omap_readl(OTG_SYSCON_1);
99 syscon |= HST_IDLE_EN|DEV_IDLE_EN|OTG_IDLE_EN;
100
101#ifdef CONFIG_USB_GADGET_OMAP
102 if (config->otg || config->register_dev) {
103 struct platform_device *udc_device = config->udc_device;
104 int status;
105
106 syscon &= ~DEV_IDLE_EN;
107 udc_device->dev.platform_data = config;
108 status = platform_device_register(udc_device);
109 if (status)
110 pr_debug("can't register UDC device, %d\n", status);
111 }
112#endif
113
114#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
115 if (config->otg || config->register_host) {
116 struct platform_device *ohci_device = config->ohci_device;
117 int status;
118
119 syscon &= ~HST_IDLE_EN;
120 ohci_device->dev.platform_data = config;
121 status = platform_device_register(ohci_device);
122 if (status)
123 pr_debug("can't register OHCI device, %d\n", status);
124 }
125#endif
126
127#ifdef CONFIG_USB_OTG
128 if (config->otg) {
129 struct platform_device *otg_device = config->otg_device;
130 int status;
131
132 syscon &= ~OTG_IDLE_EN;
133 otg_device->dev.platform_data = config;
134 status = platform_device_register(otg_device);
135 if (status)
136 pr_debug("can't register OTG device, %d\n", status);
137 }
138#endif
139 pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1));
140 omap_writel(syscon, OTG_SYSCON_1);
141}
142
143#else
144void omap_otg_init(struct omap_usb_config *config) {}
145#endif
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index bddc8fd9a7b..271ca161d7e 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -185,7 +185,7 @@ config USB_FUSB300
185 185
186config USB_OMAP 186config USB_OMAP
187 tristate "OMAP USB Device Controller" 187 tristate "OMAP USB Device Controller"
188 depends on ARCH_OMAP 188 depends on ARCH_OMAP1
189 select ISP1301_OMAP if MACH_OMAP_H2 || MACH_OMAP_H3 || MACH_OMAP_H4_OTG 189 select ISP1301_OMAP if MACH_OMAP_H2 || MACH_OMAP_H3 || MACH_OMAP_H4_OTG
190 select USB_OTG_UTILS if ARCH_OMAP 190 select USB_OTG_UTILS if ARCH_OMAP
191 help 191 help
diff --git a/drivers/usb/gadget/omap_udc.c b/drivers/usb/gadget/omap_udc.c
index a460e8c204f..89cbd2b22ab 100644
--- a/drivers/usb/gadget/omap_udc.c
+++ b/drivers/usb/gadget/omap_udc.c
@@ -44,7 +44,8 @@
44#include <asm/mach-types.h> 44#include <asm/mach-types.h>
45 45
46#include <plat/dma.h> 46#include <plat/dma.h>
47#include <plat/usb.h> 47
48#include <mach/usb.h>
48 49
49#include "omap_udc.h" 50#include "omap_udc.h"
50 51
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 83e58df29fe..dcfaaa91a3f 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -308,7 +308,7 @@ config USB_OHCI_HCD
308 308
309config USB_OHCI_HCD_OMAP1 309config USB_OHCI_HCD_OMAP1
310 bool "OHCI support for OMAP1/2 chips" 310 bool "OHCI support for OMAP1/2 chips"
311 depends on USB_OHCI_HCD && (ARCH_OMAP1 || ARCH_OMAP2) 311 depends on USB_OHCI_HCD && ARCH_OMAP1
312 default y 312 default y
313 ---help--- 313 ---help---
314 Enables support for the OHCI controller on OMAP1/2 chips. 314 Enables support for the OHCI controller on OMAP1/2 chips.
diff --git a/drivers/usb/host/ohci-omap.c b/drivers/usb/host/ohci-omap.c
index 9ce35d0d9d5..b02c344e2cc 100644
--- a/drivers/usb/host/ohci-omap.c
+++ b/drivers/usb/host/ohci-omap.c
@@ -20,14 +20,15 @@
20#include <linux/clk.h> 20#include <linux/clk.h>
21#include <linux/gpio.h> 21#include <linux/gpio.h>
22 22
23#include <mach/hardware.h>
24#include <asm/io.h> 23#include <asm/io.h>
25#include <asm/mach-types.h> 24#include <asm/mach-types.h>
26 25
27#include <plat/mux.h> 26#include <plat/mux.h>
28#include <mach/irqs.h>
29#include <plat/fpga.h> 27#include <plat/fpga.h>
30#include <plat/usb.h> 28
29#include <mach/hardware.h>
30#include <mach/irqs.h>
31#include <mach/usb.h>
31 32
32 33
33/* OMAP-1510 OHCI has its own MMU for DMA */ 34/* OMAP-1510 OHCI has its own MMU for DMA */
diff --git a/drivers/usb/otg/isp1301_omap.c b/drivers/usb/otg/isp1301_omap.c
index 70cf5d7bca4..e0558dfcfaf 100644
--- a/drivers/usb/otg/isp1301_omap.c
+++ b/drivers/usb/otg/isp1301_omap.c
@@ -36,9 +36,9 @@
36#include <asm/irq.h> 36#include <asm/irq.h>
37#include <asm/mach-types.h> 37#include <asm/mach-types.h>
38 38
39#include <plat/usb.h>
40#include <plat/mux.h> 39#include <plat/mux.h>
41 40
41#include <mach/usb.h>
42 42
43#ifndef DEBUG 43#ifndef DEBUG
44#undef VERBOSE 44#undef VERBOSE
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-02 15:15:56 -0500