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-rw-r--r--arch/arm/mach-pxa/em-x270.c1
-rw-r--r--arch/arm/mach-pxa/pxa27x.c2
-rw-r--r--arch/arm/mach-pxa/pxa3xx.c2
-rw-r--r--drivers/usb/gadget/pxa2xx_udc.c10
-rw-r--r--include/asm-arm/arch-pxa/pxa-regs.h412
-rw-r--r--include/asm-arm/arch-pxa/pxa25x-udc.h163
-rw-r--r--include/asm-arm/arch-pxa/pxa27x-udc.h256
7 files changed, 430 insertions, 416 deletions
diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c
index edc4f07a230..1269ac99150 100644
--- a/arch/arm/mach-pxa/em-x270.c
+++ b/arch/arm/mach-pxa/em-x270.c
@@ -24,6 +24,7 @@
24 24
25#include <asm/arch/pxa-regs.h> 25#include <asm/arch/pxa-regs.h>
26#include <asm/arch/pxa2xx-gpio.h> 26#include <asm/arch/pxa2xx-gpio.h>
27#include <asm/arch/pxa27x-udc.h>
27#include <asm/arch/pxafb.h> 28#include <asm/arch/pxafb.h>
28#include <asm/arch/ohci.h> 29#include <asm/arch/ohci.h>
29#include <asm/arch/mmc.h> 30#include <asm/arch/mmc.h>
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index 7e945836e12..cdaf573e0f1 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -353,7 +353,7 @@ void __init pxa_set_i2c_power_info(struct i2c_pxa_platform_data *info)
353} 353}
354 354
355static struct platform_device *devices[] __initdata = { 355static struct platform_device *devices[] __initdata = {
356 &pxa_device_udc, 356/* &pxa_device_udc, The UDC driver is PXA25x only */
357 &pxa_device_ffuart, 357 &pxa_device_ffuart,
358 &pxa_device_btuart, 358 &pxa_device_btuart,
359 &pxa_device_stuart, 359 &pxa_device_stuart,
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index 644550bfa33..7fbe78649da 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -520,7 +520,7 @@ void __init pxa3xx_init_irq(void)
520 */ 520 */
521 521
522static struct platform_device *devices[] __initdata = { 522static struct platform_device *devices[] __initdata = {
523 &pxa_device_udc, 523/* &pxa_device_udc, The UDC driver is PXA25x only */
524 &pxa_device_ffuart, 524 &pxa_device_ffuart,
525 &pxa_device_btuart, 525 &pxa_device_btuart,
526 &pxa_device_stuart, 526 &pxa_device_stuart,
diff --git a/drivers/usb/gadget/pxa2xx_udc.c b/drivers/usb/gadget/pxa2xx_udc.c
index 08f699b1fc5..63db96adc0b 100644
--- a/drivers/usb/gadget/pxa2xx_udc.c
+++ b/drivers/usb/gadget/pxa2xx_udc.c
@@ -46,19 +46,25 @@
46#include <linux/err.h> 46#include <linux/err.h>
47#include <linux/seq_file.h> 47#include <linux/seq_file.h>
48#include <linux/debugfs.h> 48#include <linux/debugfs.h>
49#include <linux/io.h>
49 50
50#include <asm/byteorder.h> 51#include <asm/byteorder.h>
51#include <asm/dma.h> 52#include <asm/dma.h>
52#include <asm/gpio.h> 53#include <asm/gpio.h>
53#include <asm/io.h>
54#include <asm/system.h> 54#include <asm/system.h>
55#include <asm/mach-types.h> 55#include <asm/mach-types.h>
56#include <asm/unaligned.h> 56#include <asm/unaligned.h>
57#include <asm/hardware.h>
58 57
59#include <linux/usb/ch9.h> 58#include <linux/usb/ch9.h>
60#include <linux/usb/gadget.h> 59#include <linux/usb/gadget.h>
61 60
61/*
62 * This driver is PXA25x only. Grab the right register definitions.
63 */
64#ifdef CONFIG_ARCH_PXA
65#include <asm/arch/pxa25x-udc.h>
66#endif
67
62#include <asm/mach/udc_pxa2xx.h> 68#include <asm/mach/udc_pxa2xx.h>
63 69
64 70
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index 4b2ea1e95c5..68d74287730 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -600,418 +600,6 @@
600 600
601 601
602/* 602/*
603 * USB Device Controller
604 * PXA25x and PXA27x USB device controller registers are different.
605 */
606#if defined(CONFIG_PXA25x)
607
608#define UDC_RES1 __REG(0x40600004) /* UDC Undocumented - Reserved1 */
609#define UDC_RES2 __REG(0x40600008) /* UDC Undocumented - Reserved2 */
610#define UDC_RES3 __REG(0x4060000C) /* UDC Undocumented - Reserved3 */
611
612#define UDCCR __REG(0x40600000) /* UDC Control Register */
613#define UDCCR_UDE (1 << 0) /* UDC enable */
614#define UDCCR_UDA (1 << 1) /* UDC active */
615#define UDCCR_RSM (1 << 2) /* Device resume */
616#define UDCCR_RESIR (1 << 3) /* Resume interrupt request */
617#define UDCCR_SUSIR (1 << 4) /* Suspend interrupt request */
618#define UDCCR_SRM (1 << 5) /* Suspend/resume interrupt mask */
619#define UDCCR_RSTIR (1 << 6) /* Reset interrupt request */
620#define UDCCR_REM (1 << 7) /* Reset interrupt mask */
621
622#define UDCCS0 __REG(0x40600010) /* UDC Endpoint 0 Control/Status Register */
623#define UDCCS0_OPR (1 << 0) /* OUT packet ready */
624#define UDCCS0_IPR (1 << 1) /* IN packet ready */
625#define UDCCS0_FTF (1 << 2) /* Flush Tx FIFO */
626#define UDCCS0_DRWF (1 << 3) /* Device remote wakeup feature */
627#define UDCCS0_SST (1 << 4) /* Sent stall */
628#define UDCCS0_FST (1 << 5) /* Force stall */
629#define UDCCS0_RNE (1 << 6) /* Receive FIFO no empty */
630#define UDCCS0_SA (1 << 7) /* Setup active */
631
632/* Bulk IN - Endpoint 1,6,11 */
633#define UDCCS1 __REG(0x40600014) /* UDC Endpoint 1 (IN) Control/Status Register */
634#define UDCCS6 __REG(0x40600028) /* UDC Endpoint 6 (IN) Control/Status Register */
635#define UDCCS11 __REG(0x4060003C) /* UDC Endpoint 11 (IN) Control/Status Register */
636
637#define UDCCS_BI_TFS (1 << 0) /* Transmit FIFO service */
638#define UDCCS_BI_TPC (1 << 1) /* Transmit packet complete */
639#define UDCCS_BI_FTF (1 << 2) /* Flush Tx FIFO */
640#define UDCCS_BI_TUR (1 << 3) /* Transmit FIFO underrun */
641#define UDCCS_BI_SST (1 << 4) /* Sent stall */
642#define UDCCS_BI_FST (1 << 5) /* Force stall */
643#define UDCCS_BI_TSP (1 << 7) /* Transmit short packet */
644
645/* Bulk OUT - Endpoint 2,7,12 */
646#define UDCCS2 __REG(0x40600018) /* UDC Endpoint 2 (OUT) Control/Status Register */
647#define UDCCS7 __REG(0x4060002C) /* UDC Endpoint 7 (OUT) Control/Status Register */
648#define UDCCS12 __REG(0x40600040) /* UDC Endpoint 12 (OUT) Control/Status Register */
649
650#define UDCCS_BO_RFS (1 << 0) /* Receive FIFO service */
651#define UDCCS_BO_RPC (1 << 1) /* Receive packet complete */
652#define UDCCS_BO_DME (1 << 3) /* DMA enable */
653#define UDCCS_BO_SST (1 << 4) /* Sent stall */
654#define UDCCS_BO_FST (1 << 5) /* Force stall */
655#define UDCCS_BO_RNE (1 << 6) /* Receive FIFO not empty */
656#define UDCCS_BO_RSP (1 << 7) /* Receive short packet */
657
658/* Isochronous IN - Endpoint 3,8,13 */
659#define UDCCS3 __REG(0x4060001C) /* UDC Endpoint 3 (IN) Control/Status Register */
660#define UDCCS8 __REG(0x40600030) /* UDC Endpoint 8 (IN) Control/Status Register */
661#define UDCCS13 __REG(0x40600044) /* UDC Endpoint 13 (IN) Control/Status Register */
662
663#define UDCCS_II_TFS (1 << 0) /* Transmit FIFO service */
664#define UDCCS_II_TPC (1 << 1) /* Transmit packet complete */
665#define UDCCS_II_FTF (1 << 2) /* Flush Tx FIFO */
666#define UDCCS_II_TUR (1 << 3) /* Transmit FIFO underrun */
667#define UDCCS_II_TSP (1 << 7) /* Transmit short packet */
668
669/* Isochronous OUT - Endpoint 4,9,14 */
670#define UDCCS4 __REG(0x40600020) /* UDC Endpoint 4 (OUT) Control/Status Register */
671#define UDCCS9 __REG(0x40600034) /* UDC Endpoint 9 (OUT) Control/Status Register */
672#define UDCCS14 __REG(0x40600048) /* UDC Endpoint 14 (OUT) Control/Status Register */
673
674#define UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */
675#define UDCCS_IO_RPC (1 << 1) /* Receive packet complete */
676#define UDCCS_IO_ROF (1 << 2) /* Receive overflow */
677#define UDCCS_IO_DME (1 << 3) /* DMA enable */
678#define UDCCS_IO_RNE (1 << 6) /* Receive FIFO not empty */
679#define UDCCS_IO_RSP (1 << 7) /* Receive short packet */
680
681/* Interrupt IN - Endpoint 5,10,15 */
682#define UDCCS5 __REG(0x40600024) /* UDC Endpoint 5 (Interrupt) Control/Status Register */
683#define UDCCS10 __REG(0x40600038) /* UDC Endpoint 10 (Interrupt) Control/Status Register */
684#define UDCCS15 __REG(0x4060004C) /* UDC Endpoint 15 (Interrupt) Control/Status Register */
685
686#define UDCCS_INT_TFS (1 << 0) /* Transmit FIFO service */
687#define UDCCS_INT_TPC (1 << 1) /* Transmit packet complete */
688#define UDCCS_INT_FTF (1 << 2) /* Flush Tx FIFO */
689#define UDCCS_INT_TUR (1 << 3) /* Transmit FIFO underrun */
690#define UDCCS_INT_SST (1 << 4) /* Sent stall */
691#define UDCCS_INT_FST (1 << 5) /* Force stall */
692#define UDCCS_INT_TSP (1 << 7) /* Transmit short packet */
693
694#define UFNRH __REG(0x40600060) /* UDC Frame Number Register High */
695#define UFNRL __REG(0x40600064) /* UDC Frame Number Register Low */
696#define UBCR2 __REG(0x40600068) /* UDC Byte Count Reg 2 */
697#define UBCR4 __REG(0x4060006c) /* UDC Byte Count Reg 4 */
698#define UBCR7 __REG(0x40600070) /* UDC Byte Count Reg 7 */
699#define UBCR9 __REG(0x40600074) /* UDC Byte Count Reg 9 */
700#define UBCR12 __REG(0x40600078) /* UDC Byte Count Reg 12 */
701#define UBCR14 __REG(0x4060007c) /* UDC Byte Count Reg 14 */
702#define UDDR0 __REG(0x40600080) /* UDC Endpoint 0 Data Register */
703#define UDDR1 __REG(0x40600100) /* UDC Endpoint 1 Data Register */
704#define UDDR2 __REG(0x40600180) /* UDC Endpoint 2 Data Register */
705#define UDDR3 __REG(0x40600200) /* UDC Endpoint 3 Data Register */
706#define UDDR4 __REG(0x40600400) /* UDC Endpoint 4 Data Register */
707#define UDDR5 __REG(0x406000A0) /* UDC Endpoint 5 Data Register */
708#define UDDR6 __REG(0x40600600) /* UDC Endpoint 6 Data Register */
709#define UDDR7 __REG(0x40600680) /* UDC Endpoint 7 Data Register */
710#define UDDR8 __REG(0x40600700) /* UDC Endpoint 8 Data Register */
711#define UDDR9 __REG(0x40600900) /* UDC Endpoint 9 Data Register */
712#define UDDR10 __REG(0x406000C0) /* UDC Endpoint 10 Data Register */
713#define UDDR11 __REG(0x40600B00) /* UDC Endpoint 11 Data Register */
714#define UDDR12 __REG(0x40600B80) /* UDC Endpoint 12 Data Register */
715#define UDDR13 __REG(0x40600C00) /* UDC Endpoint 13 Data Register */
716#define UDDR14 __REG(0x40600E00) /* UDC Endpoint 14 Data Register */
717#define UDDR15 __REG(0x406000E0) /* UDC Endpoint 15 Data Register */
718
719#define UICR0 __REG(0x40600050) /* UDC Interrupt Control Register 0 */
720
721#define UICR0_IM0 (1 << 0) /* Interrupt mask ep 0 */
722#define UICR0_IM1 (1 << 1) /* Interrupt mask ep 1 */
723#define UICR0_IM2 (1 << 2) /* Interrupt mask ep 2 */
724#define UICR0_IM3 (1 << 3) /* Interrupt mask ep 3 */
725#define UICR0_IM4 (1 << 4) /* Interrupt mask ep 4 */
726#define UICR0_IM5 (1 << 5) /* Interrupt mask ep 5 */
727#define UICR0_IM6 (1 << 6) /* Interrupt mask ep 6 */
728#define UICR0_IM7 (1 << 7) /* Interrupt mask ep 7 */
729
730#define UICR1 __REG(0x40600054) /* UDC Interrupt Control Register 1 */
731
732#define UICR1_IM8 (1 << 0) /* Interrupt mask ep 8 */
733#define UICR1_IM9 (1 << 1) /* Interrupt mask ep 9 */
734#define UICR1_IM10 (1 << 2) /* Interrupt mask ep 10 */
735#define UICR1_IM11 (1 << 3) /* Interrupt mask ep 11 */
736#define UICR1_IM12 (1 << 4) /* Interrupt mask ep 12 */
737#define UICR1_IM13 (1 << 5) /* Interrupt mask ep 13 */
738#define UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */
739#define UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */
740
741#define USIR0 __REG(0x40600058) /* UDC Status Interrupt Register 0 */
742
743#define USIR0_IR0 (1 << 0) /* Interrupt request ep 0 */
744#define USIR0_IR1 (1 << 1) /* Interrupt request ep 1 */
745#define USIR0_IR2 (1 << 2) /* Interrupt request ep 2 */
746#define USIR0_IR3 (1 << 3) /* Interrupt request ep 3 */
747#define USIR0_IR4 (1 << 4) /* Interrupt request ep 4 */
748#define USIR0_IR5 (1 << 5) /* Interrupt request ep 5 */
749#define USIR0_IR6 (1 << 6) /* Interrupt request ep 6 */
750#define USIR0_IR7 (1 << 7) /* Interrupt request ep 7 */
751
752#define USIR1 __REG(0x4060005C) /* UDC Status Interrupt Register 1 */
753
754#define USIR1_IR8 (1 << 0) /* Interrupt request ep 8 */
755#define USIR1_IR9 (1 << 1) /* Interrupt request ep 9 */
756#define USIR1_IR10 (1 << 2) /* Interrupt request ep 10 */
757#define USIR1_IR11 (1 << 3) /* Interrupt request ep 11 */
758#define USIR1_IR12 (1 << 4) /* Interrupt request ep 12 */
759#define USIR1_IR13 (1 << 5) /* Interrupt request ep 13 */
760#define USIR1_IR14 (1 << 6) /* Interrupt request ep 14 */
761#define USIR1_IR15 (1 << 7) /* Interrupt request ep 15 */
762
763#elif defined(CONFIG_PXA27x)
764
765#define UDCCR __REG(0x40600000) /* UDC Control Register */
766#define UDCCR_OEN (1 << 31) /* On-the-Go Enable */
767#define UDCCR_AALTHNP (1 << 30) /* A-device Alternate Host Negotiation
768 Protocol Port Support */
769#define UDCCR_AHNP (1 << 29) /* A-device Host Negotiation Protocol
770 Support */
771#define UDCCR_BHNP (1 << 28) /* B-device Host Negotiation Protocol
772 Enable */
773#define UDCCR_DWRE (1 << 16) /* Device Remote Wake-up Enable */
774#define UDCCR_ACN (0x03 << 11) /* Active UDC configuration Number */
775#define UDCCR_ACN_S 11
776#define UDCCR_AIN (0x07 << 8) /* Active UDC interface Number */
777#define UDCCR_AIN_S 8
778#define UDCCR_AAISN (0x07 << 5) /* Active UDC Alternate Interface
779 Setting Number */
780#define UDCCR_AAISN_S 5
781#define UDCCR_SMAC (1 << 4) /* Switch Endpoint Memory to Active
782 Configuration */
783#define UDCCR_EMCE (1 << 3) /* Endpoint Memory Configuration
784 Error */
785#define UDCCR_UDR (1 << 2) /* UDC Resume */
786#define UDCCR_UDA (1 << 1) /* UDC Active */
787#define UDCCR_UDE (1 << 0) /* UDC Enable */
788
789#define UDCICR0 __REG(0x40600004) /* UDC Interrupt Control Register0 */
790#define UDCICR1 __REG(0x40600008) /* UDC Interrupt Control Register1 */
791#define UDCICR_FIFOERR (1 << 1) /* FIFO Error interrupt for EP */
792#define UDCICR_PKTCOMPL (1 << 0) /* Packet Complete interrupt for EP */
793
794#define UDC_INT_FIFOERROR (0x2)
795#define UDC_INT_PACKETCMP (0x1)
796
797#define UDCICR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
798#define UDCICR1_IECC (1 << 31) /* IntEn - Configuration Change */
799#define UDCICR1_IESOF (1 << 30) /* IntEn - Start of Frame */
800#define UDCICR1_IERU (1 << 29) /* IntEn - Resume */
801#define UDCICR1_IESU (1 << 28) /* IntEn - Suspend */
802#define UDCICR1_IERS (1 << 27) /* IntEn - Reset */
803
804#define UDCISR0 __REG(0x4060000C) /* UDC Interrupt Status Register 0 */
805#define UDCISR1 __REG(0x40600010) /* UDC Interrupt Status Register 1 */
806#define UDCISR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
807#define UDCISR1_IRCC (1 << 31) /* IntReq - Configuration Change */
808#define UDCISR1_IRSOF (1 << 30) /* IntReq - Start of Frame */
809#define UDCISR1_IRRU (1 << 29) /* IntReq - Resume */
810#define UDCISR1_IRSU (1 << 28) /* IntReq - Suspend */
811#define UDCISR1_IRRS (1 << 27) /* IntReq - Reset */
812
813#define UDCFNR __REG(0x40600014) /* UDC Frame Number Register */
814#define UDCOTGICR __REG(0x40600018) /* UDC On-The-Go interrupt control */
815#define UDCOTGICR_IESF (1 << 24) /* OTG SET_FEATURE command recvd */
816#define UDCOTGICR_IEXR (1 << 17) /* Extra Transciever Interrupt
817 Rising Edge Interrupt Enable */
818#define UDCOTGICR_IEXF (1 << 16) /* Extra Transciever Interrupt
819 Falling Edge Interrupt Enable */
820#define UDCOTGICR_IEVV40R (1 << 9) /* OTG Vbus Valid 4.0V Rising Edge
821 Interrupt Enable */
822#define UDCOTGICR_IEVV40F (1 << 8) /* OTG Vbus Valid 4.0V Falling Edge
823 Interrupt Enable */
824#define UDCOTGICR_IEVV44R (1 << 7) /* OTG Vbus Valid 4.4V Rising Edge
825 Interrupt Enable */
826#define UDCOTGICR_IEVV44F (1 << 6) /* OTG Vbus Valid 4.4V Falling Edge
827 Interrupt Enable */
828#define UDCOTGICR_IESVR (1 << 5) /* OTG Session Valid Rising Edge
829 Interrupt Enable */
830#define UDCOTGICR_IESVF (1 << 4) /* OTG Session Valid Falling Edge
831 Interrupt Enable */
832#define UDCOTGICR_IESDR (1 << 3) /* OTG A-Device SRP Detect Rising
833 Edge Interrupt Enable */
834#define UDCOTGICR_IESDF (1 << 2) /* OTG A-Device SRP Detect Falling
835 Edge Interrupt Enable */
836#define UDCOTGICR_IEIDR (1 << 1) /* OTG ID Change Rising Edge
837 Interrupt Enable */
838#define UDCOTGICR_IEIDF (1 << 0) /* OTG ID Change Falling Edge
839 Interrupt Enable */
840
841#define UP2OCR __REG(0x40600020) /* USB Port 2 Output Control register */
842
843#define UP2OCR_CPVEN (1 << 0) /* Charge Pump Vbus Enable */
844#define UP2OCR_CPVPE (1 << 1) /* Charge Pump Vbus Pulse Enable */
845#define UP2OCR_DPPDE (1 << 2) /* Host Port 2 Transceiver D+ Pull Down Enable */
846#define UP2OCR_DMPDE (1 << 3) /* Host Port 2 Transceiver D- Pull Down Enable */
847#define UP2OCR_DPPUE (1 << 4) /* Host Port 2 Transceiver D+ Pull Up Enable */
848#define UP2OCR_DMPUE (1 << 5) /* Host Port 2 Transceiver D- Pull Up Enable */
849#define UP2OCR_DPPUBE (1 << 6) /* Host Port 2 Transceiver D+ Pull Up Bypass Enable */
850#define UP2OCR_DMPUBE (1 << 7) /* Host Port 2 Transceiver D- Pull Up Bypass Enable */
851#define UP2OCR_EXSP (1 << 8) /* External Transceiver Speed Control */
852#define UP2OCR_EXSUS (1 << 9) /* External Transceiver Speed Enable */
853#define UP2OCR_IDON (1 << 10) /* OTG ID Read Enable */
854#define UP2OCR_HXS (1 << 16) /* Host Port 2 Transceiver Output Select */
855#define UP2OCR_HXOE (1 << 17) /* Host Port 2 Transceiver Output Enable */
856#define UP2OCR_SEOS (1 << 24) /* Single-Ended Output Select */
857
858#define UDCCSN(x) __REG2(0x40600100, (x) << 2)
859#define UDCCSR0 __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */
860#define UDCCSR0_SA (1 << 7) /* Setup Active */
861#define UDCCSR0_RNE (1 << 6) /* Receive FIFO Not Empty */
862#define UDCCSR0_FST (1 << 5) /* Force Stall */
863#define UDCCSR0_SST (1 << 4) /* Sent Stall */
864#define UDCCSR0_DME (1 << 3) /* DMA Enable */
865#define UDCCSR0_FTF (1 << 2) /* Flush Transmit FIFO */
866#define UDCCSR0_IPR (1 << 1) /* IN Packet Ready */
867#define UDCCSR0_OPC (1 << 0) /* OUT Packet Complete */
868
869#define UDCCSRA __REG(0x40600104) /* UDC Control/Status register - Endpoint A */
870#define UDCCSRB __REG(0x40600108) /* UDC Control/Status register - Endpoint B */
871#define UDCCSRC __REG(0x4060010C) /* UDC Control/Status register - Endpoint C */
872#define UDCCSRD __REG(0x40600110) /* UDC Control/Status register - Endpoint D */
873#define UDCCSRE __REG(0x40600114) /* UDC Control/Status register - Endpoint E */
874#define UDCCSRF __REG(0x40600118) /* UDC Control/Status register - Endpoint F */
875#define UDCCSRG __REG(0x4060011C) /* UDC Control/Status register - Endpoint G */
876#define UDCCSRH __REG(0x40600120) /* UDC Control/Status register - Endpoint H */
877#define UDCCSRI __REG(0x40600124) /* UDC Control/Status register - Endpoint I */
878#define UDCCSRJ __REG(0x40600128) /* UDC Control/Status register - Endpoint J */
879#define UDCCSRK __REG(0x4060012C) /* UDC Control/Status register - Endpoint K */
880#define UDCCSRL __REG(0x40600130) /* UDC Control/Status register - Endpoint L */
881#define UDCCSRM __REG(0x40600134) /* UDC Control/Status register - Endpoint M */
882#define UDCCSRN __REG(0x40600138) /* UDC Control/Status register - Endpoint N */
883#define UDCCSRP __REG(0x4060013C) /* UDC Control/Status register - Endpoint P */
884#define UDCCSRQ __REG(0x40600140) /* UDC Control/Status register - Endpoint Q */
885#define UDCCSRR __REG(0x40600144) /* UDC Control/Status register - Endpoint R */
886#define UDCCSRS __REG(0x40600148) /* UDC Control/Status register - Endpoint S */
887#define UDCCSRT __REG(0x4060014C) /* UDC Control/Status register - Endpoint T */
888#define UDCCSRU __REG(0x40600150) /* UDC Control/Status register - Endpoint U */
889#define UDCCSRV __REG(0x40600154) /* UDC Control/Status register - Endpoint V */
890#define UDCCSRW __REG(0x40600158) /* UDC Control/Status register - Endpoint W */
891#define UDCCSRX __REG(0x4060015C) /* UDC Control/Status register - Endpoint X */
892
893#define UDCCSR_DPE (1 << 9) /* Data Packet Error */
894#define UDCCSR_FEF (1 << 8) /* Flush Endpoint FIFO */
895#define UDCCSR_SP (1 << 7) /* Short Packet Control/Status */
896#define UDCCSR_BNE (1 << 6) /* Buffer Not Empty (IN endpoints) */
897#define UDCCSR_BNF (1 << 6) /* Buffer Not Full (OUT endpoints) */
898#define UDCCSR_FST (1 << 5) /* Force STALL */
899#define UDCCSR_SST (1 << 4) /* Sent STALL */
900#define UDCCSR_DME (1 << 3) /* DMA Enable */
901#define UDCCSR_TRN (1 << 2) /* Tx/Rx NAK */
902#define UDCCSR_PC (1 << 1) /* Packet Complete */
903#define UDCCSR_FS (1 << 0) /* FIFO needs service */
904
905#define UDCBCN(x) __REG2(0x40600200, (x)<<2)
906#define UDCBCR0 __REG(0x40600200) /* Byte Count Register - EP0 */
907#define UDCBCRA __REG(0x40600204) /* Byte Count Register - EPA */
908#define UDCBCRB __REG(0x40600208) /* Byte Count Register - EPB */
909#define UDCBCRC __REG(0x4060020C) /* Byte Count Register - EPC */
910#define UDCBCRD __REG(0x40600210) /* Byte Count Register - EPD */
911#define UDCBCRE __REG(0x40600214) /* Byte Count Register - EPE */
912#define UDCBCRF __REG(0x40600218) /* Byte Count Register - EPF */
913#define UDCBCRG __REG(0x4060021C) /* Byte Count Register - EPG */
914#define UDCBCRH __REG(0x40600220) /* Byte Count Register - EPH */
915#define UDCBCRI __REG(0x40600224) /* Byte Count Register - EPI */
916#define UDCBCRJ __REG(0x40600228) /* Byte Count Register - EPJ */
917#define UDCBCRK __REG(0x4060022C) /* Byte Count Register - EPK */
918#define UDCBCRL __REG(0x40600230) /* Byte Count Register - EPL */
919#define UDCBCRM __REG(0x40600234) /* Byte Count Register - EPM */
920#define UDCBCRN __REG(0x40600238) /* Byte Count Register - EPN */
921#define UDCBCRP __REG(0x4060023C) /* Byte Count Register - EPP */
922#define UDCBCRQ __REG(0x40600240) /* Byte Count Register - EPQ */
923#define UDCBCRR __REG(0x40600244) /* Byte Count Register - EPR */
924#define UDCBCRS __REG(0x40600248) /* Byte Count Register - EPS */
925#define UDCBCRT __REG(0x4060024C) /* Byte Count Register - EPT */
926#define UDCBCRU __REG(0x40600250) /* Byte Count Register - EPU */
927#define UDCBCRV __REG(0x40600254) /* Byte Count Register - EPV */
928#define UDCBCRW __REG(0x40600258) /* Byte Count Register - EPW */
929#define UDCBCRX __REG(0x4060025C) /* Byte Count Register - EPX */
930
931#define UDCDN(x) __REG2(0x40600300, (x)<<2)
932#define PHYS_UDCDN(x) (0x40600300 + ((x)<<2))
933#define PUDCDN(x) (volatile u32 *)(io_p2v(PHYS_UDCDN((x))))
934#define UDCDR0 __REG(0x40600300) /* Data Register - EP0 */
935#define UDCDRA __REG(0x40600304) /* Data Register - EPA */
936#define UDCDRB __REG(0x40600308) /* Data Register - EPB */
937#define UDCDRC __REG(0x4060030C) /* Data Register - EPC */
938#define UDCDRD __REG(0x40600310) /* Data Register - EPD */
939#define UDCDRE __REG(0x40600314) /* Data Register - EPE */
940#define UDCDRF __REG(0x40600318) /* Data Register - EPF */
941#define UDCDRG __REG(0x4060031C) /* Data Register - EPG */
942#define UDCDRH __REG(0x40600320) /* Data Register - EPH */
943#define UDCDRI __REG(0x40600324) /* Data Register - EPI */
944#define UDCDRJ __REG(0x40600328) /* Data Register - EPJ */
945#define UDCDRK __REG(0x4060032C) /* Data Register - EPK */
946#define UDCDRL __REG(0x40600330) /* Data Register - EPL */
947#define UDCDRM __REG(0x40600334) /* Data Register - EPM */
948#define UDCDRN __REG(0x40600338) /* Data Register - EPN */
949#define UDCDRP __REG(0x4060033C) /* Data Register - EPP */
950#define UDCDRQ __REG(0x40600340) /* Data Register - EPQ */
951#define UDCDRR __REG(0x40600344) /* Data Register - EPR */
952#define UDCDRS __REG(0x40600348) /* Data Register - EPS */
953#define UDCDRT __REG(0x4060034C) /* Data Register - EPT */
954#define UDCDRU __REG(0x40600350) /* Data Register - EPU */
955#define UDCDRV __REG(0x40600354) /* Data Register - EPV */
956#define UDCDRW __REG(0x40600358) /* Data Register - EPW */
957#define UDCDRX __REG(0x4060035C) /* Data Register - EPX */
958
959#define UDCCN(x) __REG2(0x40600400, (x)<<2)
960#define UDCCRA __REG(0x40600404) /* Configuration register EPA */
961#define UDCCRB __REG(0x40600408) /* Configuration register EPB */
962#define UDCCRC __REG(0x4060040C) /* Configuration register EPC */
963#define UDCCRD __REG(0x40600410) /* Configuration register EPD */
964#define UDCCRE __REG(0x40600414) /* Configuration register EPE */
965#define UDCCRF __REG(0x40600418) /* Configuration register EPF */
966#define UDCCRG __REG(0x4060041C) /* Configuration register EPG */
967#define UDCCRH __REG(0x40600420) /* Configuration register EPH */
968#define UDCCRI __REG(0x40600424) /* Configuration register EPI */
969#define UDCCRJ __REG(0x40600428) /* Configuration register EPJ */
970#define UDCCRK __REG(0x4060042C) /* Configuration register EPK */
971#define UDCCRL __REG(0x40600430) /* Configuration register EPL */
972#define UDCCRM __REG(0x40600434) /* Configuration register EPM */
973#define UDCCRN __REG(0x40600438) /* Configuration register EPN */
974#define UDCCRP __REG(0x4060043C) /* Configuration register EPP */
975#define UDCCRQ __REG(0x40600440) /* Configuration register EPQ */
976#define UDCCRR __REG(0x40600444) /* Configuration register EPR */
977#define UDCCRS __REG(0x40600448) /* Configuration register EPS */
978#define UDCCRT __REG(0x4060044C) /* Configuration register EPT */
979#define UDCCRU __REG(0x40600450) /* Configuration register EPU */
980#define UDCCRV __REG(0x40600454) /* Configuration register EPV */
981#define UDCCRW __REG(0x40600458) /* Configuration register EPW */
982#define UDCCRX __REG(0x4060045C) /* Configuration register EPX */
983
984#define UDCCONR_CN (0x03 << 25) /* Configuration Number */
985#define UDCCONR_CN_S (25)
986#define UDCCONR_IN (0x07 << 22) /* Interface Number */
987#define UDCCONR_IN_S (22)
988#define UDCCONR_AISN (0x07 << 19) /* Alternate Interface Number */
989#define UDCCONR_AISN_S (19)
990#define UDCCONR_EN (0x0f << 15) /* Endpoint Number */
991#define UDCCONR_EN_S (15)
992#define UDCCONR_ET (0x03 << 13) /* Endpoint Type: */
993#define UDCCONR_ET_S (13)
994#define UDCCONR_ET_INT (0x03 << 13) /* Interrupt */
995#define UDCCONR_ET_BULK (0x02 << 13) /* Bulk */
996#define UDCCONR_ET_ISO (0x01 << 13) /* Isochronous */
997#define UDCCONR_ET_NU (0x00 << 13) /* Not used */
998#define UDCCONR_ED (1 << 12) /* Endpoint Direction */
999#define UDCCONR_MPS (0x3ff << 2) /* Maximum Packet Size */
1000#define UDCCONR_MPS_S (2)
1001#define UDCCONR_DE (1 << 1) /* Double Buffering Enable */
1002#define UDCCONR_EE (1 << 0) /* Endpoint Enable */
1003
1004
1005#define UDC_INT_FIFOERROR (0x2)
1006#define UDC_INT_PACKETCMP (0x1)
1007
1008#define UDC_FNR_MASK (0x7ff)
1009
1010#define UDCCSR_WR_MASK (UDCCSR_DME|UDCCSR_FST)
1011#define UDC_BCR_MASK (0x3ff)
1012#endif
1013
1014/*
1015 * Fast Infrared Communication Port 603 * Fast Infrared Communication Port
1016 */ 604 */
1017 605
diff --git a/include/asm-arm/arch-pxa/pxa25x-udc.h b/include/asm-arm/arch-pxa/pxa25x-udc.h
new file mode 100644
index 00000000000..840305916b6
--- /dev/null
+++ b/include/asm-arm/arch-pxa/pxa25x-udc.h
@@ -0,0 +1,163 @@
1#ifndef _ASM_ARCH_PXA25X_UDC_H
2#define _ASM_ARCH_PXA25X_UDC_H
3
4#ifdef _ASM_ARCH_PXA27X_UDC_H
5#error You can't include both PXA25x and PXA27x UDC support
6#endif
7
8#define UDC_RES1 __REG(0x40600004) /* UDC Undocumented - Reserved1 */
9#define UDC_RES2 __REG(0x40600008) /* UDC Undocumented - Reserved2 */
10#define UDC_RES3 __REG(0x4060000C) /* UDC Undocumented - Reserved3 */
11
12#define UDCCR __REG(0x40600000) /* UDC Control Register */
13#define UDCCR_UDE (1 << 0) /* UDC enable */
14#define UDCCR_UDA (1 << 1) /* UDC active */
15#define UDCCR_RSM (1 << 2) /* Device resume */
16#define UDCCR_RESIR (1 << 3) /* Resume interrupt request */
17#define UDCCR_SUSIR (1 << 4) /* Suspend interrupt request */
18#define UDCCR_SRM (1 << 5) /* Suspend/resume interrupt mask */
19#define UDCCR_RSTIR (1 << 6) /* Reset interrupt request */
20#define UDCCR_REM (1 << 7) /* Reset interrupt mask */
21
22#define UDCCS0 __REG(0x40600010) /* UDC Endpoint 0 Control/Status Register */
23#define UDCCS0_OPR (1 << 0) /* OUT packet ready */
24#define UDCCS0_IPR (1 << 1) /* IN packet ready */
25#define UDCCS0_FTF (1 << 2) /* Flush Tx FIFO */
26#define UDCCS0_DRWF (1 << 3) /* Device remote wakeup feature */
27#define UDCCS0_SST (1 << 4) /* Sent stall */
28#define UDCCS0_FST (1 << 5) /* Force stall */
29#define UDCCS0_RNE (1 << 6) /* Receive FIFO no empty */
30#define UDCCS0_SA (1 << 7) /* Setup active */
31
32/* Bulk IN - Endpoint 1,6,11 */
33#define UDCCS1 __REG(0x40600014) /* UDC Endpoint 1 (IN) Control/Status Register */
34#define UDCCS6 __REG(0x40600028) /* UDC Endpoint 6 (IN) Control/Status Register */
35#define UDCCS11 __REG(0x4060003C) /* UDC Endpoint 11 (IN) Control/Status Register */
36
37#define UDCCS_BI_TFS (1 << 0) /* Transmit FIFO service */
38#define UDCCS_BI_TPC (1 << 1) /* Transmit packet complete */
39#define UDCCS_BI_FTF (1 << 2) /* Flush Tx FIFO */
40#define UDCCS_BI_TUR (1 << 3) /* Transmit FIFO underrun */
41#define UDCCS_BI_SST (1 << 4) /* Sent stall */
42#define UDCCS_BI_FST (1 << 5) /* Force stall */
43#define UDCCS_BI_TSP (1 << 7) /* Transmit short packet */
44
45/* Bulk OUT - Endpoint 2,7,12 */
46#define UDCCS2 __REG(0x40600018) /* UDC Endpoint 2 (OUT) Control/Status Register */
47#define UDCCS7 __REG(0x4060002C) /* UDC Endpoint 7 (OUT) Control/Status Register */
48#define UDCCS12 __REG(0x40600040) /* UDC Endpoint 12 (OUT) Control/Status Register */
49
50#define UDCCS_BO_RFS (1 << 0) /* Receive FIFO service */
51#define UDCCS_BO_RPC (1 << 1) /* Receive packet complete */
52#define UDCCS_BO_DME (1 << 3) /* DMA enable */
53#define UDCCS_BO_SST (1 << 4) /* Sent stall */
54#define UDCCS_BO_FST (1 << 5) /* Force stall */
55#define UDCCS_BO_RNE (1 << 6) /* Receive FIFO not empty */
56#define UDCCS_BO_RSP (1 << 7) /* Receive short packet */
57
58/* Isochronous IN - Endpoint 3,8,13 */
59#define UDCCS3 __REG(0x4060001C) /* UDC Endpoint 3 (IN) Control/Status Register */
60#define UDCCS8 __REG(0x40600030) /* UDC Endpoint 8 (IN) Control/Status Register */
61#define UDCCS13 __REG(0x40600044) /* UDC Endpoint 13 (IN) Control/Status Register */
62
63#define UDCCS_II_TFS (1 << 0) /* Transmit FIFO service */
64#define UDCCS_II_TPC (1 << 1) /* Transmit packet complete */
65#define UDCCS_II_FTF (1 << 2) /* Flush Tx FIFO */
66#define UDCCS_II_TUR (1 << 3) /* Transmit FIFO underrun */
67#define UDCCS_II_TSP (1 << 7) /* Transmit short packet */
68
69/* Isochronous OUT - Endpoint 4,9,14 */
70#define UDCCS4 __REG(0x40600020) /* UDC Endpoint 4 (OUT) Control/Status Register */
71#define UDCCS9 __REG(0x40600034) /* UDC Endpoint 9 (OUT) Control/Status Register */
72#define UDCCS14 __REG(0x40600048) /* UDC Endpoint 14 (OUT) Control/Status Register */
73
74#define UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */
75#define UDCCS_IO_RPC (1 << 1) /* Receive packet complete */
76#define UDCCS_IO_ROF (1 << 2) /* Receive overflow */
77#define UDCCS_IO_DME (1 << 3) /* DMA enable */
78#define UDCCS_IO_RNE (1 << 6) /* Receive FIFO not empty */
79#define UDCCS_IO_RSP (1 << 7) /* Receive short packet */
80
81/* Interrupt IN - Endpoint 5,10,15 */
82#define UDCCS5 __REG(0x40600024) /* UDC Endpoint 5 (Interrupt) Control/Status Register */
83#define UDCCS10 __REG(0x40600038) /* UDC Endpoint 10 (Interrupt) Control/Status Register */
84#define UDCCS15 __REG(0x4060004C) /* UDC Endpoint 15 (Interrupt) Control/Status Register */
85
86#define UDCCS_INT_TFS (1 << 0) /* Transmit FIFO service */
87#define UDCCS_INT_TPC (1 << 1) /* Transmit packet complete */
88#define UDCCS_INT_FTF (1 << 2) /* Flush Tx FIFO */
89#define UDCCS_INT_TUR (1 << 3) /* Transmit FIFO underrun */
90#define UDCCS_INT_SST (1 << 4) /* Sent stall */
91#define UDCCS_INT_FST (1 << 5) /* Force stall */
92#define UDCCS_INT_TSP (1 << 7) /* Transmit short packet */
93
94#define UFNRH __REG(0x40600060) /* UDC Frame Number Register High */
95#define UFNRL __REG(0x40600064) /* UDC Frame Number Register Low */
96#define UBCR2 __REG(0x40600068) /* UDC Byte Count Reg 2 */
97#define UBCR4 __REG(0x4060006c) /* UDC Byte Count Reg 4 */
98#define UBCR7 __REG(0x40600070) /* UDC Byte Count Reg 7 */
99#define UBCR9 __REG(0x40600074) /* UDC Byte Count Reg 9 */
100#define UBCR12 __REG(0x40600078) /* UDC Byte Count Reg 12 */
101#define UBCR14 __REG(0x4060007c) /* UDC Byte Count Reg 14 */
102#define UDDR0 __REG(0x40600080) /* UDC Endpoint 0 Data Register */
103#define UDDR1 __REG(0x40600100) /* UDC Endpoint 1 Data Register */
104#define UDDR2 __REG(0x40600180) /* UDC Endpoint 2 Data Register */
105#define UDDR3 __REG(0x40600200) /* UDC Endpoint 3 Data Register */
106#define UDDR4 __REG(0x40600400) /* UDC Endpoint 4 Data Register */
107#define UDDR5 __REG(0x406000A0) /* UDC Endpoint 5 Data Register */
108#define UDDR6 __REG(0x40600600) /* UDC Endpoint 6 Data Register */
109#define UDDR7 __REG(0x40600680) /* UDC Endpoint 7 Data Register */
110#define UDDR8 __REG(0x40600700) /* UDC Endpoint 8 Data Register */
111#define UDDR9 __REG(0x40600900) /* UDC Endpoint 9 Data Register */
112#define UDDR10 __REG(0x406000C0) /* UDC Endpoint 10 Data Register */
113#define UDDR11 __REG(0x40600B00) /* UDC Endpoint 11 Data Register */
114#define UDDR12 __REG(0x40600B80) /* UDC Endpoint 12 Data Register */
115#define UDDR13 __REG(0x40600C00) /* UDC Endpoint 13 Data Register */
116#define UDDR14 __REG(0x40600E00) /* UDC Endpoint 14 Data Register */
117#define UDDR15 __REG(0x406000E0) /* UDC Endpoint 15 Data Register */
118
119#define UICR0 __REG(0x40600050) /* UDC Interrupt Control Register 0 */
120
121#define UICR0_IM0 (1 << 0) /* Interrupt mask ep 0 */
122#define UICR0_IM1 (1 << 1) /* Interrupt mask ep 1 */
123#define UICR0_IM2 (1 << 2) /* Interrupt mask ep 2 */
124#define UICR0_IM3 (1 << 3) /* Interrupt mask ep 3 */
125#define UICR0_IM4 (1 << 4) /* Interrupt mask ep 4 */
126#define UICR0_IM5 (1 << 5) /* Interrupt mask ep 5 */
127#define UICR0_IM6 (1 << 6) /* Interrupt mask ep 6 */
128#define UICR0_IM7 (1 << 7) /* Interrupt mask ep 7 */
129
130#define UICR1 __REG(0x40600054) /* UDC Interrupt Control Register 1 */
131
132#define UICR1_IM8 (1 << 0) /* Interrupt mask ep 8 */
133#define UICR1_IM9 (1 << 1) /* Interrupt mask ep 9 */
134#define UICR1_IM10 (1 << 2) /* Interrupt mask ep 10 */
135#define UICR1_IM11 (1 << 3) /* Interrupt mask ep 11 */
136#define UICR1_IM12 (1 << 4) /* Interrupt mask ep 12 */
137#define UICR1_IM13 (1 << 5) /* Interrupt mask ep 13 */
138#define UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */
139#define UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */
140
141#define USIR0 __REG(0x40600058) /* UDC Status Interrupt Register 0 */
142
143#define USIR0_IR0 (1 << 0) /* Interrupt request ep 0 */
144#define USIR0_IR1 (1 << 1) /* Interrupt request ep 1 */
145#define USIR0_IR2 (1 << 2) /* Interrupt request ep 2 */
146#define USIR0_IR3 (1 << 3) /* Interrupt request ep 3 */
147#define USIR0_IR4 (1 << 4) /* Interrupt request ep 4 */
148#define USIR0_IR5 (1 << 5) /* Interrupt request ep 5 */
149#define USIR0_IR6 (1 << 6) /* Interrupt request ep 6 */
150#define USIR0_IR7 (1 << 7) /* Interrupt request ep 7 */
151
152#define USIR1 __REG(0x4060005C) /* UDC Status Interrupt Register 1 */
153
154#define USIR1_IR8 (1 << 0) /* Interrupt request ep 8 */
155#define USIR1_IR9 (1 << 1) /* Interrupt request ep 9 */
156#define USIR1_IR10 (1 << 2) /* Interrupt request ep 10 */
157#define USIR1_IR11 (1 << 3) /* Interrupt request ep 11 */
158#define USIR1_IR12 (1 << 4) /* Interrupt request ep 12 */
159#define USIR1_IR13 (1 << 5) /* Interrupt request ep 13 */
160#define USIR1_IR14 (1 << 6) /* Interrupt request ep 14 */
161#define USIR1_IR15 (1 << 7) /* Interrupt request ep 15 */
162
163#endif
diff --git a/include/asm-arm/arch-pxa/pxa27x-udc.h b/include/asm-arm/arch-pxa/pxa27x-udc.h
new file mode 100644
index 00000000000..9cf0b1f8811
--- /dev/null
+++ b/include/asm-arm/arch-pxa/pxa27x-udc.h
@@ -0,0 +1,256 @@
1#ifndef _ASM_ARCH_PXA27X_UDC_H
2#define _ASM_ARCH_PXA27X_UDC_H
3
4#ifdef _ASM_ARCH_PXA25X_UDC_H
5#error You can't include both PXA25x and PXA27x UDC support
6#endif
7
8#define UDCCR __REG(0x40600000) /* UDC Control Register */
9#define UDCCR_OEN (1 << 31) /* On-the-Go Enable */
10#define UDCCR_AALTHNP (1 << 30) /* A-device Alternate Host Negotiation
11 Protocol Port Support */
12#define UDCCR_AHNP (1 << 29) /* A-device Host Negotiation Protocol
13 Support */
14#define UDCCR_BHNP (1 << 28) /* B-device Host Negotiation Protocol
15 Enable */
16#define UDCCR_DWRE (1 << 16) /* Device Remote Wake-up Enable */
17#define UDCCR_ACN (0x03 << 11) /* Active UDC configuration Number */
18#define UDCCR_ACN_S 11
19#define UDCCR_AIN (0x07 << 8) /* Active UDC interface Number */
20#define UDCCR_AIN_S 8
21#define UDCCR_AAISN (0x07 << 5) /* Active UDC Alternate Interface
22 Setting Number */
23#define UDCCR_AAISN_S 5
24#define UDCCR_SMAC (1 << 4) /* Switch Endpoint Memory to Active
25 Configuration */
26#define UDCCR_EMCE (1 << 3) /* Endpoint Memory Configuration
27 Error */
28#define UDCCR_UDR (1 << 2) /* UDC Resume */
29#define UDCCR_UDA (1 << 1) /* UDC Active */
30#define UDCCR_UDE (1 << 0) /* UDC Enable */
31
32#define UDCICR0 __REG(0x40600004) /* UDC Interrupt Control Register0 */
33#define UDCICR1 __REG(0x40600008) /* UDC Interrupt Control Register1 */
34#define UDCICR_FIFOERR (1 << 1) /* FIFO Error interrupt for EP */
35#define UDCICR_PKTCOMPL (1 << 0) /* Packet Complete interrupt for EP */
36
37#define UDC_INT_FIFOERROR (0x2)
38#define UDC_INT_PACKETCMP (0x1)
39
40#define UDCICR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
41#define UDCICR1_IECC (1 << 31) /* IntEn - Configuration Change */
42#define UDCICR1_IESOF (1 << 30) /* IntEn - Start of Frame */
43#define UDCICR1_IERU (1 << 29) /* IntEn - Resume */
44#define UDCICR1_IESU (1 << 28) /* IntEn - Suspend */
45#define UDCICR1_IERS (1 << 27) /* IntEn - Reset */
46
47#define UDCISR0 __REG(0x4060000C) /* UDC Interrupt Status Register 0 */
48#define UDCISR1 __REG(0x40600010) /* UDC Interrupt Status Register 1 */
49#define UDCISR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
50#define UDCISR1_IRCC (1 << 31) /* IntReq - Configuration Change */
51#define UDCISR1_IRSOF (1 << 30) /* IntReq - Start of Frame */
52#define UDCISR1_IRRU (1 << 29) /* IntReq - Resume */
53#define UDCISR1_IRSU (1 << 28) /* IntReq - Suspend */
54#define UDCISR1_IRRS (1 << 27) /* IntReq - Reset */
55
56#define UDCFNR __REG(0x40600014) /* UDC Frame Number Register */
57#define UDCOTGICR __REG(0x40600018) /* UDC On-The-Go interrupt control */
58#define UDCOTGICR_IESF (1 << 24) /* OTG SET_FEATURE command recvd */
59#define UDCOTGICR_IEXR (1 << 17) /* Extra Transciever Interrupt
60 Rising Edge Interrupt Enable */
61#define UDCOTGICR_IEXF (1 << 16) /* Extra Transciever Interrupt
62 Falling Edge Interrupt Enable */
63#define UDCOTGICR_IEVV40R (1 << 9) /* OTG Vbus Valid 4.0V Rising Edge
64 Interrupt Enable */
65#define UDCOTGICR_IEVV40F (1 << 8) /* OTG Vbus Valid 4.0V Falling Edge
66 Interrupt Enable */
67#define UDCOTGICR_IEVV44R (1 << 7) /* OTG Vbus Valid 4.4V Rising Edge
68 Interrupt Enable */
69#define UDCOTGICR_IEVV44F (1 << 6) /* OTG Vbus Valid 4.4V Falling Edge
70 Interrupt Enable */
71#define UDCOTGICR_IESVR (1 << 5) /* OTG Session Valid Rising Edge
72 Interrupt Enable */
73#define UDCOTGICR_IESVF (1 << 4) /* OTG Session Valid Falling Edge
74 Interrupt Enable */
75#define UDCOTGICR_IESDR (1 << 3) /* OTG A-Device SRP Detect Rising
76 Edge Interrupt Enable */
77#define UDCOTGICR_IESDF (1 << 2) /* OTG A-Device SRP Detect Falling
78 Edge Interrupt Enable */
79#define UDCOTGICR_IEIDR (1 << 1) /* OTG ID Change Rising Edge
80 Interrupt Enable */
81#define UDCOTGICR_IEIDF (1 << 0) /* OTG ID Change Falling Edge
82 Interrupt Enable */
83
84#define UP2OCR __REG(0x40600020) /* USB Port 2 Output Control register */
85
86#define UP2OCR_CPVEN (1 << 0) /* Charge Pump Vbus Enable */
87#define UP2OCR_CPVPE (1 << 1) /* Charge Pump Vbus Pulse Enable */
88#define UP2OCR_DPPDE (1 << 2) /* Host Port 2 Transceiver D+ Pull Down Enable */
89#define UP2OCR_DMPDE (1 << 3) /* Host Port 2 Transceiver D- Pull Down Enable */
90#define UP2OCR_DPPUE (1 << 4) /* Host Port 2 Transceiver D+ Pull Up Enable */
91#define UP2OCR_DMPUE (1 << 5) /* Host Port 2 Transceiver D- Pull Up Enable */
92#define UP2OCR_DPPUBE (1 << 6) /* Host Port 2 Transceiver D+ Pull Up Bypass Enable */
93#define UP2OCR_DMPUBE (1 << 7) /* Host Port 2 Transceiver D- Pull Up Bypass Enable */
94#define UP2OCR_EXSP (1 << 8) /* External Transceiver Speed Control */
95#define UP2OCR_EXSUS (1 << 9) /* External Transceiver Speed Enable */
96#define UP2OCR_IDON (1 << 10) /* OTG ID Read Enable */
97#define UP2OCR_HXS (1 << 16) /* Host Port 2 Transceiver Output Select */
98#define UP2OCR_HXOE (1 << 17) /* Host Port 2 Transceiver Output Enable */
99#define UP2OCR_SEOS (1 << 24) /* Single-Ended Output Select */
100
101#define UDCCSN(x) __REG2(0x40600100, (x) << 2)
102#define UDCCSR0 __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */
103#define UDCCSR0_SA (1 << 7) /* Setup Active */
104#define UDCCSR0_RNE (1 << 6) /* Receive FIFO Not Empty */
105#define UDCCSR0_FST (1 << 5) /* Force Stall */
106#define UDCCSR0_SST (1 << 4) /* Sent Stall */
107#define UDCCSR0_DME (1 << 3) /* DMA Enable */
108#define UDCCSR0_FTF (1 << 2) /* Flush Transmit FIFO */
109#define UDCCSR0_IPR (1 << 1) /* IN Packet Ready */
110#define UDCCSR0_OPC (1 << 0) /* OUT Packet Complete */
111
112#define UDCCSRA __REG(0x40600104) /* UDC Control/Status register - Endpoint A */
113#define UDCCSRB __REG(0x40600108) /* UDC Control/Status register - Endpoint B */
114#define UDCCSRC __REG(0x4060010C) /* UDC Control/Status register - Endpoint C */
115#define UDCCSRD __REG(0x40600110) /* UDC Control/Status register - Endpoint D */
116#define UDCCSRE __REG(0x40600114) /* UDC Control/Status register - Endpoint E */
117#define UDCCSRF __REG(0x40600118) /* UDC Control/Status register - Endpoint F */
118#define UDCCSRG __REG(0x4060011C) /* UDC Control/Status register - Endpoint G */
119#define UDCCSRH __REG(0x40600120) /* UDC Control/Status register - Endpoint H */
120#define UDCCSRI __REG(0x40600124) /* UDC Control/Status register - Endpoint I */
121#define UDCCSRJ __REG(0x40600128) /* UDC Control/Status register - Endpoint J */
122#define UDCCSRK __REG(0x4060012C) /* UDC Control/Status register - Endpoint K */
123#define UDCCSRL __REG(0x40600130) /* UDC Control/Status register - Endpoint L */
124#define UDCCSRM __REG(0x40600134) /* UDC Control/Status register - Endpoint M */
125#define UDCCSRN __REG(0x40600138) /* UDC Control/Status register - Endpoint N */
126#define UDCCSRP __REG(0x4060013C) /* UDC Control/Status register - Endpoint P */
127#define UDCCSRQ __REG(0x40600140) /* UDC Control/Status register - Endpoint Q */
128#define UDCCSRR __REG(0x40600144) /* UDC Control/Status register - Endpoint R */
129#define UDCCSRS __REG(0x40600148) /* UDC Control/Status register - Endpoint S */
130#define UDCCSRT __REG(0x4060014C) /* UDC Control/Status register - Endpoint T */
131#define UDCCSRU __REG(0x40600150) /* UDC Control/Status register - Endpoint U */
132#define UDCCSRV __REG(0x40600154) /* UDC Control/Status register - Endpoint V */
133#define UDCCSRW __REG(0x40600158) /* UDC Control/Status register - Endpoint W */
134#define UDCCSRX __REG(0x4060015C) /* UDC Control/Status register - Endpoint X */
135
136#define UDCCSR_DPE (1 << 9) /* Data Packet Error */
137#define UDCCSR_FEF (1 << 8) /* Flush Endpoint FIFO */
138#define UDCCSR_SP (1 << 7) /* Short Packet Control/Status */
139#define UDCCSR_BNE (1 << 6) /* Buffer Not Empty (IN endpoints) */
140#define UDCCSR_BNF (1 << 6) /* Buffer Not Full (OUT endpoints) */
141#define UDCCSR_FST (1 << 5) /* Force STALL */
142#define UDCCSR_SST (1 << 4) /* Sent STALL */
143#define UDCCSR_DME (1 << 3) /* DMA Enable */
144#define UDCCSR_TRN (1 << 2) /* Tx/Rx NAK */
145#define UDCCSR_PC (1 << 1) /* Packet Complete */
146#define UDCCSR_FS (1 << 0) /* FIFO needs service */
147
148#define UDCBCN(x) __REG2(0x40600200, (x)<<2)
149#define UDCBCR0 __REG(0x40600200) /* Byte Count Register - EP0 */
150#define UDCBCRA __REG(0x40600204) /* Byte Count Register - EPA */
151#define UDCBCRB __REG(0x40600208) /* Byte Count Register - EPB */
152#define UDCBCRC __REG(0x4060020C) /* Byte Count Register - EPC */
153#define UDCBCRD __REG(0x40600210) /* Byte Count Register - EPD */
154#define UDCBCRE __REG(0x40600214) /* Byte Count Register - EPE */
155#define UDCBCRF __REG(0x40600218) /* Byte Count Register - EPF */
156#define UDCBCRG __REG(0x4060021C) /* Byte Count Register - EPG */
157#define UDCBCRH __REG(0x40600220) /* Byte Count Register - EPH */
158#define UDCBCRI __REG(0x40600224) /* Byte Count Register - EPI */
159#define UDCBCRJ __REG(0x40600228) /* Byte Count Register - EPJ */
160#define UDCBCRK __REG(0x4060022C) /* Byte Count Register - EPK */
161#define UDCBCRL __REG(0x40600230) /* Byte Count Register - EPL */
162#define UDCBCRM __REG(0x40600234) /* Byte Count Register - EPM */
163#define UDCBCRN __REG(0x40600238) /* Byte Count Register - EPN */
164#define UDCBCRP __REG(0x4060023C) /* Byte Count Register - EPP */
165#define UDCBCRQ __REG(0x40600240) /* Byte Count Register - EPQ */
166#define UDCBCRR __REG(0x40600244) /* Byte Count Register - EPR */
167#define UDCBCRS __REG(0x40600248) /* Byte Count Register - EPS */
168#define UDCBCRT __REG(0x4060024C) /* Byte Count Register - EPT */
169#define UDCBCRU __REG(0x40600250) /* Byte Count Register - EPU */
170#define UDCBCRV __REG(0x40600254) /* Byte Count Register - EPV */
171#define UDCBCRW __REG(0x40600258) /* Byte Count Register - EPW */
172#define UDCBCRX __REG(0x4060025C) /* Byte Count Register - EPX */
173
174#define UDCDN(x) __REG2(0x40600300, (x)<<2)
175#define PHYS_UDCDN(x) (0x40600300 + ((x)<<2))
176#define PUDCDN(x) (volatile u32 *)(io_p2v(PHYS_UDCDN((x))))
177#define UDCDR0 __REG(0x40600300) /* Data Register - EP0 */
178#define UDCDRA __REG(0x40600304) /* Data Register - EPA */
179#define UDCDRB __REG(0x40600308) /* Data Register - EPB */
180#define UDCDRC __REG(0x4060030C) /* Data Register - EPC */
181#define UDCDRD __REG(0x40600310) /* Data Register - EPD */
182#define UDCDRE __REG(0x40600314) /* Data Register - EPE */
183#define UDCDRF __REG(0x40600318) /* Data Register - EPF */
184#define UDCDRG __REG(0x4060031C) /* Data Register - EPG */
185#define UDCDRH __REG(0x40600320) /* Data Register - EPH */
186#define UDCDRI __REG(0x40600324) /* Data Register - EPI */
187#define UDCDRJ __REG(0x40600328) /* Data Register - EPJ */
188#define UDCDRK __REG(0x4060032C) /* Data Register - EPK */
189#define UDCDRL __REG(0x40600330) /* Data Register - EPL */
190#define UDCDRM __REG(0x40600334) /* Data Register - EPM */
191#define UDCDRN __REG(0x40600338) /* Data Register - EPN */
192#define UDCDRP __REG(0x4060033C) /* Data Register - EPP */
193#define UDCDRQ __REG(0x40600340) /* Data Register - EPQ */
194#define UDCDRR __REG(0x40600344) /* Data Register - EPR */
195#define UDCDRS __REG(0x40600348) /* Data Register - EPS */
196#define UDCDRT __REG(0x4060034C) /* Data Register - EPT */
197#define UDCDRU __REG(0x40600350) /* Data Register - EPU */
198#define UDCDRV __REG(0x40600354) /* Data Register - EPV */
199#define UDCDRW __REG(0x40600358) /* Data Register - EPW */
200#define UDCDRX __REG(0x4060035C) /* Data Register - EPX */
201
202#define UDCCN(x) __REG2(0x40600400, (x)<<2)
203#define UDCCRA __REG(0x40600404) /* Configuration register EPA */
204#define UDCCRB __REG(0x40600408) /* Configuration register EPB */
205#define UDCCRC __REG(0x4060040C) /* Configuration register EPC */
206#define UDCCRD __REG(0x40600410) /* Configuration register EPD */
207#define UDCCRE __REG(0x40600414) /* Configuration register EPE */
208#define UDCCRF __REG(0x40600418) /* Configuration register EPF */
209#define UDCCRG __REG(0x4060041C) /* Configuration register EPG */
210#define UDCCRH __REG(0x40600420) /* Configuration register EPH */
211#define UDCCRI __REG(0x40600424) /* Configuration register EPI */
212#define UDCCRJ __REG(0x40600428) /* Configuration register EPJ */
213#define UDCCRK __REG(0x4060042C) /* Configuration register EPK */
214#define UDCCRL __REG(0x40600430) /* Configuration register EPL */
215#define UDCCRM __REG(0x40600434) /* Configuration register EPM */
216#define UDCCRN __REG(0x40600438) /* Configuration register EPN */
217#define UDCCRP __REG(0x4060043C) /* Configuration register EPP */
218#define UDCCRQ __REG(0x40600440) /* Configuration register EPQ */
219#define UDCCRR __REG(0x40600444) /* Configuration register EPR */
220#define UDCCRS __REG(0x40600448) /* Configuration register EPS */
221#define UDCCRT __REG(0x4060044C) /* Configuration register EPT */
222#define UDCCRU __REG(0x40600450) /* Configuration register EPU */
223#define UDCCRV __REG(0x40600454) /* Configuration register EPV */
224#define UDCCRW __REG(0x40600458) /* Configuration register EPW */
225#define UDCCRX __REG(0x4060045C) /* Configuration register EPX */
226
227#define UDCCONR_CN (0x03 << 25) /* Configuration Number */
228#define UDCCONR_CN_S (25)
229#define UDCCONR_IN (0x07 << 22) /* Interface Number */
230#define UDCCONR_IN_S (22)
231#define UDCCONR_AISN (0x07 << 19) /* Alternate Interface Number */
232#define UDCCONR_AISN_S (19)
233#define UDCCONR_EN (0x0f << 15) /* Endpoint Number */
234#define UDCCONR_EN_S (15)
235#define UDCCONR_ET (0x03 << 13) /* Endpoint Type: */
236#define UDCCONR_ET_S (13)
237#define UDCCONR_ET_INT (0x03 << 13) /* Interrupt */
238#define UDCCONR_ET_BULK (0x02 << 13) /* Bulk */
239#define UDCCONR_ET_ISO (0x01 << 13) /* Isochronous */
240#define UDCCONR_ET_NU (0x00 << 13) /* Not used */
241#define UDCCONR_ED (1 << 12) /* Endpoint Direction */
242#define UDCCONR_MPS (0x3ff << 2) /* Maximum Packet Size */
243#define UDCCONR_MPS_S (2)
244#define UDCCONR_DE (1 << 1) /* Double Buffering Enable */
245#define UDCCONR_EE (1 << 0) /* Endpoint Enable */
246
247
248#define UDC_INT_FIFOERROR (0x2)
249#define UDC_INT_PACKETCMP (0x1)
250
251#define UDC_FNR_MASK (0x7ff)
252
253#define UDCCSR_WR_MASK (UDCCSR_DME|UDCCSR_FST)
254#define UDC_BCR_MASK (0x3ff)
255
256#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-20 08:38:33 -0400