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-rw-r--r--drivers/video/omap2/dss/hdmi.c18
-rw-r--r--drivers/video/omap2/dss/ti_hdmi.h15
-rw-r--r--drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c20
3 files changed, 30 insertions, 23 deletions
diff --git a/drivers/video/omap2/dss/hdmi.c b/drivers/video/omap2/dss/hdmi.c
index 2a8a55d7c7d..5afc51bc618 100644
--- a/drivers/video/omap2/dss/hdmi.c
+++ b/drivers/video/omap2/dss/hdmi.c
@@ -366,7 +366,7 @@ static void hdmi_read_edid(struct omap_video_timings *dp)
366 memset(hdmi.edid, 0, HDMI_EDID_MAX_LENGTH); 366 memset(hdmi.edid, 0, HDMI_EDID_MAX_LENGTH);
367 367
368 if (!hdmi.edid_set) 368 if (!hdmi.edid_set)
369 ret = read_edid(&hdmi.ip_data, hdmi.edid, 369 ret = ti_hdmi_4xxx_read_edid(&hdmi.ip_data, hdmi.edid,
370 HDMI_EDID_MAX_LENGTH); 370 HDMI_EDID_MAX_LENGTH);
371 if (!ret) { 371 if (!ret) {
372 if (!memcmp(hdmi.edid, edid_header, sizeof(edid_header))) { 372 if (!memcmp(hdmi.edid, edid_header, sizeof(edid_header))) {
@@ -480,16 +480,16 @@ static int hdmi_power_on(struct omap_dss_device *dssdev)
480 480
481 hdmi_compute_pll(dssdev, phy, &hdmi.ip_data.pll_data); 481 hdmi_compute_pll(dssdev, phy, &hdmi.ip_data.pll_data);
482 482
483 hdmi_wp_video_start(&hdmi.ip_data, 0); 483 ti_hdmi_4xxx_wp_video_start(&hdmi.ip_data, 0);
484 484
485 /* config the PLL and PHY hdmi_set_pll_pwrfirst */ 485 /* config the PLL and PHY hdmi_set_pll_pwrfirst */
486 r = hdmi_pll_program(&hdmi.ip_data); 486 r = ti_hdmi_4xxx_pll_enable(&hdmi.ip_data);
487 if (r) { 487 if (r) {
488 DSSDBG("Failed to lock PLL\n"); 488 DSSDBG("Failed to lock PLL\n");
489 goto err; 489 goto err;
490 } 490 }
491 491
492 r = hdmi_phy_init(&hdmi.ip_data); 492 r = ti_hdmi_4xxx_phy_enable(&hdmi.ip_data);
493 if (r) { 493 if (r) {
494 DSSDBG("Failed to start PHY\n"); 494 DSSDBG("Failed to start PHY\n");
495 goto err; 495 goto err;
@@ -497,7 +497,7 @@ static int hdmi_power_on(struct omap_dss_device *dssdev)
497 497
498 hdmi.ip_data.cfg.cm.mode = hdmi.mode; 498 hdmi.ip_data.cfg.cm.mode = hdmi.mode;
499 hdmi.ip_data.cfg.cm.code = hdmi.code; 499 hdmi.ip_data.cfg.cm.code = hdmi.code;
500 hdmi_basic_configure(&hdmi.ip_data); 500 ti_hdmi_4xxx_basic_configure(&hdmi.ip_data);
501 501
502 /* Make selection of HDMI in DSS */ 502 /* Make selection of HDMI in DSS */
503 dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK); 503 dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK);
@@ -519,7 +519,7 @@ static int hdmi_power_on(struct omap_dss_device *dssdev)
519 519
520 dispc_mgr_enable(OMAP_DSS_CHANNEL_DIGIT, 1); 520 dispc_mgr_enable(OMAP_DSS_CHANNEL_DIGIT, 1);
521 521
522 hdmi_wp_video_start(&hdmi.ip_data, 1); 522 ti_hdmi_4xxx_wp_video_start(&hdmi.ip_data, 1);
523 523
524 return 0; 524 return 0;
525err: 525err:
@@ -531,9 +531,9 @@ static void hdmi_power_off(struct omap_dss_device *dssdev)
531{ 531{
532 dispc_mgr_enable(OMAP_DSS_CHANNEL_DIGIT, 0); 532 dispc_mgr_enable(OMAP_DSS_CHANNEL_DIGIT, 0);
533 533
534 hdmi_wp_video_start(&hdmi.ip_data, 0); 534 ti_hdmi_4xxx_wp_video_start(&hdmi.ip_data, 0);
535 hdmi_phy_off(&hdmi.ip_data); 535 ti_hdmi_4xxx_phy_disable(&hdmi.ip_data);
536 hdmi_set_pll_pwr(&hdmi.ip_data, HDMI_PLLPWRCMD_ALLOFF); 536 ti_hdmi_4xxx_pll_disable(&hdmi.ip_data);
537 hdmi_runtime_put(); 537 hdmi_runtime_put();
538 538
539 hdmi.edid_set = 0; 539 hdmi.edid_set = 0;
diff --git a/drivers/video/omap2/dss/ti_hdmi.h b/drivers/video/omap2/dss/ti_hdmi.h
index 7c630984767..823fbe655b8 100644
--- a/drivers/video/omap2/dss/ti_hdmi.h
+++ b/drivers/video/omap2/dss/ti_hdmi.h
@@ -91,11 +91,12 @@ struct hdmi_ip_data {
91 struct hdmi_config cfg; 91 struct hdmi_config cfg;
92 struct hdmi_pll_info pll_data; 92 struct hdmi_pll_info pll_data;
93}; 93};
94int hdmi_phy_init(struct hdmi_ip_data *ip_data); 94int ti_hdmi_4xxx_phy_enable(struct hdmi_ip_data *ip_data);
95void hdmi_phy_off(struct hdmi_ip_data *ip_data); 95void ti_hdmi_4xxx_phy_disable(struct hdmi_ip_data *ip_data);
96int read_edid(struct hdmi_ip_data *ip_data, u8 *pedid, u16 max_length); 96int ti_hdmi_4xxx_read_edid(struct hdmi_ip_data *ip_data,
97void hdmi_wp_video_start(struct hdmi_ip_data *ip_data, bool start); 97 u8 *pedid, u16 max_length);
98int hdmi_pll_program(struct hdmi_ip_data *ip_data); 98void ti_hdmi_4xxx_wp_video_start(struct hdmi_ip_data *ip_data, bool start);
99int hdmi_set_pll_pwr(struct hdmi_ip_data *ip_data, enum hdmi_pll_pwr val); 99int ti_hdmi_4xxx_pll_enable(struct hdmi_ip_data *ip_data);
100void hdmi_basic_configure(struct hdmi_ip_data *ip_data); 100void ti_hdmi_4xxx_pll_disable(struct hdmi_ip_data *ip_data);
101void ti_hdmi_4xxx_basic_configure(struct hdmi_ip_data *ip_data);
101#endif 102#endif
diff --git a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c
index c2a98f830b8..cb3a2d6753d 100644
--- a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c
+++ b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c
@@ -164,7 +164,7 @@ static int hdmi_set_phy_pwr(struct hdmi_ip_data *ip_data, enum hdmi_phy_pwr val)
164} 164}
165 165
166/* PLL_PWR_CMD */ 166/* PLL_PWR_CMD */
167int hdmi_set_pll_pwr(struct hdmi_ip_data *ip_data, enum hdmi_pll_pwr val) 167static int hdmi_set_pll_pwr(struct hdmi_ip_data *ip_data, enum hdmi_pll_pwr val)
168{ 168{
169 /* Command for power control of HDMI PLL */ 169 /* Command for power control of HDMI PLL */
170 REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL, val, 3, 2); 170 REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL, val, 3, 2);
@@ -194,7 +194,7 @@ static int hdmi_pll_reset(struct hdmi_ip_data *ip_data)
194 return 0; 194 return 0;
195} 195}
196 196
197int hdmi_pll_program(struct hdmi_ip_data *ip_data) 197int ti_hdmi_4xxx_pll_enable(struct hdmi_ip_data *ip_data)
198{ 198{
199 u16 r = 0; 199 u16 r = 0;
200 200
@@ -217,7 +217,12 @@ int hdmi_pll_program(struct hdmi_ip_data *ip_data)
217 return 0; 217 return 0;
218} 218}
219 219
220int hdmi_phy_init(struct hdmi_ip_data *ip_data) 220void ti_hdmi_4xxx_pll_disable(struct hdmi_ip_data *ip_data)
221{
222 hdmi_set_pll_pwr(ip_data, HDMI_PLLPWRCMD_ALLOFF);
223}
224
225int ti_hdmi_4xxx_phy_enable(struct hdmi_ip_data *ip_data)
221{ 226{
222 u16 r = 0; 227 u16 r = 0;
223 void __iomem *phy_base = hdmi_phy_base(ip_data); 228 void __iomem *phy_base = hdmi_phy_base(ip_data);
@@ -254,7 +259,7 @@ int hdmi_phy_init(struct hdmi_ip_data *ip_data)
254 return 0; 259 return 0;
255} 260}
256 261
257void hdmi_phy_off(struct hdmi_ip_data *ip_data) 262void ti_hdmi_4xxx_phy_disable(struct hdmi_ip_data *ip_data)
258{ 263{
259 hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_OFF); 264 hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_OFF);
260} 265}
@@ -360,7 +365,8 @@ static int hdmi_core_ddc_edid(struct hdmi_ip_data *ip_data,
360 return 0; 365 return 0;
361} 366}
362 367
363int read_edid(struct hdmi_ip_data *ip_data, u8 *pedid, u16 max_length) 368int ti_hdmi_4xxx_read_edid(struct hdmi_ip_data *ip_data,
369 u8 *pedid, u16 max_length)
364{ 370{
365 int r = 0, n = 0, i = 0; 371 int r = 0, n = 0, i = 0;
366 int max_ext_blocks = (max_length / 128) - 1; 372 int max_ext_blocks = (max_length / 128) - 1;
@@ -613,7 +619,7 @@ static void hdmi_wp_init(struct omap_video_timings *timings,
613 619
614} 620}
615 621
616void hdmi_wp_video_start(struct hdmi_ip_data *ip_data, bool start) 622void ti_hdmi_4xxx_wp_video_start(struct hdmi_ip_data *ip_data, bool start)
617{ 623{
618 REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, start, 31, 31); 624 REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, start, 31, 31);
619} 625}
@@ -680,7 +686,7 @@ static void hdmi_wp_video_config_timing(struct hdmi_ip_data *ip_data,
680 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_TIMING_V, timing_v); 686 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_TIMING_V, timing_v);
681} 687}
682 688
683void hdmi_basic_configure(struct hdmi_ip_data *ip_data) 689void ti_hdmi_4xxx_basic_configure(struct hdmi_ip_data *ip_data)
684{ 690{
685 /* HDMI */ 691 /* HDMI */
686 struct omap_video_timings video_timing; 692 struct omap_video_timings video_timing;