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-rw-r--r--drivers/net/wireless/iwlwifi/iwl-1000.c4
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-2000.c2
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-5000.c2
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-6000.c8
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-agn-rx.c8
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-agn-tt.c14
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-agn.c42
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-bus.h3
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-core.c28
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-core.h2
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-debugfs.c6
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-eeprom.c61
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-io.c193
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-io.h63
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-led.c9
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-mac80211.c27
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-pci.c4
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-testmode.c16
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-trans-pcie-int.h8
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-trans-pcie-rx.c82
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-trans-pcie-tx.c46
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-trans-pcie.c144
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-trans.h2
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-ucode.c37
24 files changed, 405 insertions, 406 deletions
diff --git a/drivers/net/wireless/iwlwifi/iwl-1000.c b/drivers/net/wireless/iwlwifi/iwl-1000.c
index cc04cce1156..f7a555b9d24 100644
--- a/drivers/net/wireless/iwlwifi/iwl-1000.c
+++ b/drivers/net/wireless/iwlwifi/iwl-1000.c
@@ -84,13 +84,13 @@ static void iwl1000_set_ct_threshold(struct iwl_priv *priv)
84static void iwl1000_nic_config(struct iwl_priv *priv) 84static void iwl1000_nic_config(struct iwl_priv *priv)
85{ 85{
86 /* set CSR_HW_CONFIG_REG for uCode use */ 86 /* set CSR_HW_CONFIG_REG for uCode use */
87 iwl_set_bit(bus(priv), CSR_HW_IF_CONFIG_REG, 87 iwl_set_bit(trans(priv), CSR_HW_IF_CONFIG_REG,
88 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI | 88 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
89 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI); 89 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
90 90
91 /* Setting digital SVR for 1000 card to 1.32V */ 91 /* Setting digital SVR for 1000 card to 1.32V */
92 /* locking is acquired in iwl_set_bits_mask_prph() function */ 92 /* locking is acquired in iwl_set_bits_mask_prph() function */
93 iwl_set_bits_mask_prph(bus(priv), APMG_DIGITAL_SVR_REG, 93 iwl_set_bits_mask_prph(trans(priv), APMG_DIGITAL_SVR_REG,
94 APMG_SVR_DIGITAL_VOLTAGE_1_32, 94 APMG_SVR_DIGITAL_VOLTAGE_1_32,
95 ~APMG_SVR_VOLTAGE_CONFIG_BIT_MSK); 95 ~APMG_SVR_VOLTAGE_CONFIG_BIT_MSK);
96} 96}
diff --git a/drivers/net/wireless/iwlwifi/iwl-2000.c b/drivers/net/wireless/iwlwifi/iwl-2000.c
index 00db092d8cd..87600345010 100644
--- a/drivers/net/wireless/iwlwifi/iwl-2000.c
+++ b/drivers/net/wireless/iwlwifi/iwl-2000.c
@@ -87,7 +87,7 @@ static void iwl2000_nic_config(struct iwl_priv *priv)
87 iwl_rf_config(priv); 87 iwl_rf_config(priv);
88 88
89 if (cfg(priv)->iq_invert) 89 if (cfg(priv)->iq_invert)
90 iwl_set_bit(bus(priv), CSR_GP_DRIVER_REG, 90 iwl_set_bit(trans(priv), CSR_GP_DRIVER_REG,
91 CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER); 91 CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER);
92} 92}
93 93
diff --git a/drivers/net/wireless/iwlwifi/iwl-5000.c b/drivers/net/wireless/iwlwifi/iwl-5000.c
index 47fd98b3652..5245a1422a6 100644
--- a/drivers/net/wireless/iwlwifi/iwl-5000.c
+++ b/drivers/net/wireless/iwlwifi/iwl-5000.c
@@ -73,7 +73,7 @@ static void iwl5000_nic_config(struct iwl_priv *priv)
73 * (PCIe power is lost before PERST# is asserted), 73 * (PCIe power is lost before PERST# is asserted),
74 * causing ME FW to lose ownership and not being able to obtain it back. 74 * causing ME FW to lose ownership and not being able to obtain it back.
75 */ 75 */
76 iwl_set_bits_mask_prph(bus(priv), APMG_PS_CTRL_REG, 76 iwl_set_bits_mask_prph(trans(priv), APMG_PS_CTRL_REG,
77 APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS, 77 APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS,
78 ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS); 78 ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS);
79 79
diff --git a/drivers/net/wireless/iwlwifi/iwl-6000.c b/drivers/net/wireless/iwlwifi/iwl-6000.c
index ab62c018fcd..464b8878467 100644
--- a/drivers/net/wireless/iwlwifi/iwl-6000.c
+++ b/drivers/net/wireless/iwlwifi/iwl-6000.c
@@ -82,7 +82,7 @@ static void iwl6050_additional_nic_config(struct iwl_priv *priv)
82{ 82{
83 /* Indicate calibration version to uCode. */ 83 /* Indicate calibration version to uCode. */
84 if (iwl_eeprom_calib_version(priv->shrd) >= 6) 84 if (iwl_eeprom_calib_version(priv->shrd) >= 6)
85 iwl_set_bit(bus(priv), CSR_GP_DRIVER_REG, 85 iwl_set_bit(trans(priv), CSR_GP_DRIVER_REG,
86 CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6); 86 CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6);
87} 87}
88 88
@@ -90,9 +90,9 @@ static void iwl6150_additional_nic_config(struct iwl_priv *priv)
90{ 90{
91 /* Indicate calibration version to uCode. */ 91 /* Indicate calibration version to uCode. */
92 if (iwl_eeprom_calib_version(priv->shrd) >= 6) 92 if (iwl_eeprom_calib_version(priv->shrd) >= 6)
93 iwl_set_bit(bus(priv), CSR_GP_DRIVER_REG, 93 iwl_set_bit(trans(priv), CSR_GP_DRIVER_REG,
94 CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6); 94 CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6);
95 iwl_set_bit(bus(priv), CSR_GP_DRIVER_REG, 95 iwl_set_bit(trans(priv), CSR_GP_DRIVER_REG,
96 CSR_GP_DRIVER_REG_BIT_6050_1x2); 96 CSR_GP_DRIVER_REG_BIT_6050_1x2);
97} 97}
98 98
@@ -104,7 +104,7 @@ static void iwl6000_nic_config(struct iwl_priv *priv)
104 /* no locking required for register write */ 104 /* no locking required for register write */
105 if (cfg(priv)->pa_type == IWL_PA_INTERNAL) { 105 if (cfg(priv)->pa_type == IWL_PA_INTERNAL) {
106 /* 2x2 IPA phy type */ 106 /* 2x2 IPA phy type */
107 iwl_write32(bus(priv), CSR_GP_DRIVER_REG, 107 iwl_write32(trans(priv), CSR_GP_DRIVER_REG,
108 CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA); 108 CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA);
109 } 109 }
110 /* do additional nic configuration if needed */ 110 /* do additional nic configuration if needed */
diff --git a/drivers/net/wireless/iwlwifi/iwl-agn-rx.c b/drivers/net/wireless/iwlwifi/iwl-agn-rx.c
index f127f913e5a..a14ddab783e 100644
--- a/drivers/net/wireless/iwlwifi/iwl-agn-rx.c
+++ b/drivers/net/wireless/iwlwifi/iwl-agn-rx.c
@@ -628,16 +628,16 @@ static int iwlagn_rx_card_state_notif(struct iwl_priv *priv,
628 if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED | 628 if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
629 CT_CARD_DISABLED)) { 629 CT_CARD_DISABLED)) {
630 630
631 iwl_write32(bus(priv), CSR_UCODE_DRV_GP1_SET, 631 iwl_write32(trans(priv), CSR_UCODE_DRV_GP1_SET,
632 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 632 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
633 633
634 iwl_write_direct32(bus(priv), HBUS_TARG_MBX_C, 634 iwl_write_direct32(trans(priv), HBUS_TARG_MBX_C,
635 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED); 635 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
636 636
637 if (!(flags & RXON_CARD_DISABLED)) { 637 if (!(flags & RXON_CARD_DISABLED)) {
638 iwl_write32(bus(priv), CSR_UCODE_DRV_GP1_CLR, 638 iwl_write32(trans(priv), CSR_UCODE_DRV_GP1_CLR,
639 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 639 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
640 iwl_write_direct32(bus(priv), HBUS_TARG_MBX_C, 640 iwl_write_direct32(trans(priv), HBUS_TARG_MBX_C,
641 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED); 641 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
642 } 642 }
643 if (flags & CT_CARD_DISABLED) 643 if (flags & CT_CARD_DISABLED)
diff --git a/drivers/net/wireless/iwlwifi/iwl-agn-tt.c b/drivers/net/wireless/iwlwifi/iwl-agn-tt.c
index 56c6def015a..c728ed75584 100644
--- a/drivers/net/wireless/iwlwifi/iwl-agn-tt.c
+++ b/drivers/net/wireless/iwlwifi/iwl-agn-tt.c
@@ -178,19 +178,19 @@ static void iwl_tt_check_exit_ct_kill(unsigned long data)
178 178
179 if (tt->state == IWL_TI_CT_KILL) { 179 if (tt->state == IWL_TI_CT_KILL) {
180 if (priv->thermal_throttle.ct_kill_toggle) { 180 if (priv->thermal_throttle.ct_kill_toggle) {
181 iwl_write32(bus(priv), CSR_UCODE_DRV_GP1_CLR, 181 iwl_write32(trans(priv), CSR_UCODE_DRV_GP1_CLR,
182 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT); 182 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
183 priv->thermal_throttle.ct_kill_toggle = false; 183 priv->thermal_throttle.ct_kill_toggle = false;
184 } else { 184 } else {
185 iwl_write32(bus(priv), CSR_UCODE_DRV_GP1_SET, 185 iwl_write32(trans(priv), CSR_UCODE_DRV_GP1_SET,
186 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT); 186 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
187 priv->thermal_throttle.ct_kill_toggle = true; 187 priv->thermal_throttle.ct_kill_toggle = true;
188 } 188 }
189 iwl_read32(bus(priv), CSR_UCODE_DRV_GP1); 189 iwl_read32(trans(priv), CSR_UCODE_DRV_GP1);
190 spin_lock_irqsave(&bus(priv)->reg_lock, flags); 190 spin_lock_irqsave(&trans(priv)->reg_lock, flags);
191 if (!iwl_grab_nic_access(bus(priv))) 191 if (!iwl_grab_nic_access(trans(priv)))
192 iwl_release_nic_access(bus(priv)); 192 iwl_release_nic_access(trans(priv));
193 spin_unlock_irqrestore(&bus(priv)->reg_lock, flags); 193 spin_unlock_irqrestore(&trans(priv)->reg_lock, flags);
194 194
195 /* Reschedule the ct_kill timer to occur in 195 /* Reschedule the ct_kill timer to occur in
196 * CT_KILL_EXIT_DURATION seconds to ensure we get a 196 * CT_KILL_EXIT_DURATION seconds to ensure we get a
diff --git a/drivers/net/wireless/iwlwifi/iwl-agn.c b/drivers/net/wireless/iwlwifi/iwl-agn.c
index 1a4ba9de99b..f79791500a9 100644
--- a/drivers/net/wireless/iwlwifi/iwl-agn.c
+++ b/drivers/net/wireless/iwlwifi/iwl-agn.c
@@ -328,14 +328,14 @@ static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
328 ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32)); 328 ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
329 329
330 /* Make sure device is powered up for SRAM reads */ 330 /* Make sure device is powered up for SRAM reads */
331 spin_lock_irqsave(&bus(priv)->reg_lock, reg_flags); 331 spin_lock_irqsave(&trans(priv)->reg_lock, reg_flags);
332 if (iwl_grab_nic_access(bus(priv))) { 332 if (iwl_grab_nic_access(trans(priv))) {
333 spin_unlock_irqrestore(&bus(priv)->reg_lock, reg_flags); 333 spin_unlock_irqrestore(&trans(priv)->reg_lock, reg_flags);
334 return; 334 return;
335 } 335 }
336 336
337 /* Set starting address; reads will auto-increment */ 337 /* Set starting address; reads will auto-increment */
338 iwl_write32(bus(priv), HBUS_TARG_MEM_RADDR, ptr); 338 iwl_write32(trans(priv), HBUS_TARG_MEM_RADDR, ptr);
339 rmb(); 339 rmb();
340 340
341 /* 341 /*
@@ -352,19 +352,19 @@ static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
352 * place event id # at far right for easier visual parsing. 352 * place event id # at far right for easier visual parsing.
353 */ 353 */
354 for (i = 0; i < num_events; i++) { 354 for (i = 0; i < num_events; i++) {
355 ev = iwl_read32(bus(priv), HBUS_TARG_MEM_RDAT); 355 ev = iwl_read32(trans(priv), HBUS_TARG_MEM_RDAT);
356 time = iwl_read32(bus(priv), HBUS_TARG_MEM_RDAT); 356 time = iwl_read32(trans(priv), HBUS_TARG_MEM_RDAT);
357 if (mode == 0) { 357 if (mode == 0) {
358 trace_iwlwifi_dev_ucode_cont_event(priv, 0, time, ev); 358 trace_iwlwifi_dev_ucode_cont_event(priv, 0, time, ev);
359 } else { 359 } else {
360 data = iwl_read32(bus(priv), HBUS_TARG_MEM_RDAT); 360 data = iwl_read32(trans(priv), HBUS_TARG_MEM_RDAT);
361 trace_iwlwifi_dev_ucode_cont_event(priv, time, 361 trace_iwlwifi_dev_ucode_cont_event(priv, time,
362 data, ev); 362 data, ev);
363 } 363 }
364 } 364 }
365 /* Allow device to power down */ 365 /* Allow device to power down */
366 iwl_release_nic_access(bus(priv)); 366 iwl_release_nic_access(trans(priv));
367 spin_unlock_irqrestore(&bus(priv)->reg_lock, reg_flags); 367 spin_unlock_irqrestore(&trans(priv)->reg_lock, reg_flags);
368} 368}
369 369
370static void iwl_continuous_event_trace(struct iwl_priv *priv) 370static void iwl_continuous_event_trace(struct iwl_priv *priv)
@@ -383,7 +383,7 @@ static void iwl_continuous_event_trace(struct iwl_priv *priv)
383 383
384 base = priv->shrd->device_pointers.log_event_table; 384 base = priv->shrd->device_pointers.log_event_table;
385 if (iwlagn_hw_valid_rtc_data_addr(base)) { 385 if (iwlagn_hw_valid_rtc_data_addr(base)) {
386 iwl_read_targ_mem_words(bus(priv), base, &read, sizeof(read)); 386 iwl_read_targ_mem_words(trans(priv), base, &read, sizeof(read));
387 387
388 capacity = read.capacity; 388 capacity = read.capacity;
389 mode = read.mode; 389 mode = read.mode;
@@ -583,7 +583,7 @@ static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
583 priv->firmware_name); 583 priv->firmware_name);
584 584
585 return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name, 585 return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
586 bus(priv)->dev, 586 trans(priv)->dev,
587 GFP_KERNEL, priv, iwl_ucode_callback); 587 GFP_KERNEL, priv, iwl_ucode_callback);
588} 588}
589 589
@@ -1158,7 +1158,7 @@ static void iwl_rf_kill_ct_config(struct iwl_priv *priv)
1158 int ret = 0; 1158 int ret = 0;
1159 1159
1160 spin_lock_irqsave(&priv->shrd->lock, flags); 1160 spin_lock_irqsave(&priv->shrd->lock, flags);
1161 iwl_write32(bus(priv), CSR_UCODE_DRV_GP1_CLR, 1161 iwl_write32(trans(priv), CSR_UCODE_DRV_GP1_CLR,
1162 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT); 1162 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
1163 spin_unlock_irqrestore(&priv->shrd->lock, flags); 1163 spin_unlock_irqrestore(&priv->shrd->lock, flags);
1164 priv->thermal_throttle.ct_kill_toggle = false; 1164 priv->thermal_throttle.ct_kill_toggle = false;
@@ -1693,7 +1693,7 @@ static void iwl_uninit_drv(struct iwl_priv *priv)
1693 1693
1694static u32 iwl_hw_detect(struct iwl_priv *priv) 1694static u32 iwl_hw_detect(struct iwl_priv *priv)
1695{ 1695{
1696 return iwl_read32(bus(priv), CSR_HW_REV); 1696 return iwl_read32(trans(priv), CSR_HW_REV);
1697} 1697}
1698 1698
1699/* Size of one Rx buffer in host DRAM */ 1699/* Size of one Rx buffer in host DRAM */
@@ -1727,32 +1727,32 @@ static int iwl_set_hw_params(struct iwl_priv *priv)
1727 1727
1728static void iwl_debug_config(struct iwl_priv *priv) 1728static void iwl_debug_config(struct iwl_priv *priv)
1729{ 1729{
1730 dev_printk(KERN_INFO, bus(priv)->dev, "CONFIG_IWLWIFI_DEBUG " 1730 dev_printk(KERN_INFO, trans(priv)->dev, "CONFIG_IWLWIFI_DEBUG "
1731#ifdef CONFIG_IWLWIFI_DEBUG 1731#ifdef CONFIG_IWLWIFI_DEBUG
1732 "enabled\n"); 1732 "enabled\n");
1733#else 1733#else
1734 "disabled\n"); 1734 "disabled\n");
1735#endif 1735#endif
1736 dev_printk(KERN_INFO, bus(priv)->dev, "CONFIG_IWLWIFI_DEBUGFS " 1736 dev_printk(KERN_INFO, trans(priv)->dev, "CONFIG_IWLWIFI_DEBUGFS "
1737#ifdef CONFIG_IWLWIFI_DEBUGFS 1737#ifdef CONFIG_IWLWIFI_DEBUGFS
1738 "enabled\n"); 1738 "enabled\n");
1739#else 1739#else
1740 "disabled\n"); 1740 "disabled\n");
1741#endif 1741#endif
1742 dev_printk(KERN_INFO, bus(priv)->dev, "CONFIG_IWLWIFI_DEVICE_TRACING " 1742 dev_printk(KERN_INFO, trans(priv)->dev, "CONFIG_IWLWIFI_DEVICE_TRACING "
1743#ifdef CONFIG_IWLWIFI_DEVICE_TRACING 1743#ifdef CONFIG_IWLWIFI_DEVICE_TRACING
1744 "enabled\n"); 1744 "enabled\n");
1745#else 1745#else
1746 "disabled\n"); 1746 "disabled\n");
1747#endif 1747#endif
1748 1748
1749 dev_printk(KERN_INFO, bus(priv)->dev, "CONFIG_IWLWIFI_DEVICE_TESTMODE " 1749 dev_printk(KERN_INFO, trans(priv)->dev, "CONFIG_IWLWIFI_DEVICE_TESTMODE "
1750#ifdef CONFIG_IWLWIFI_DEVICE_TESTMODE 1750#ifdef CONFIG_IWLWIFI_DEVICE_TESTMODE
1751 "enabled\n"); 1751 "enabled\n");
1752#else 1752#else
1753 "disabled\n"); 1753 "disabled\n");
1754#endif 1754#endif
1755 dev_printk(KERN_INFO, bus(priv)->dev, "CONFIG_IWLWIFI_P2P " 1755 dev_printk(KERN_INFO, trans(priv)->dev, "CONFIG_IWLWIFI_P2P "
1756#ifdef CONFIG_IWLWIFI_P2P 1756#ifdef CONFIG_IWLWIFI_P2P
1757 "enabled\n"); 1757 "enabled\n");
1758#else 1758#else
@@ -1810,7 +1810,7 @@ int iwl_probe(struct iwl_bus *bus, const struct iwl_trans_ops *trans_ops,
1810 /* these spin locks will be used in apm_ops.init and EEPROM access 1810 /* these spin locks will be used in apm_ops.init and EEPROM access
1811 * we should init now 1811 * we should init now
1812 */ 1812 */
1813 spin_lock_init(&bus(priv)->reg_lock); 1813 spin_lock_init(&trans(priv)->reg_lock);
1814 spin_lock_init(&priv->shrd->lock); 1814 spin_lock_init(&priv->shrd->lock);
1815 1815
1816 /* 1816 /*
@@ -1818,7 +1818,7 @@ int iwl_probe(struct iwl_bus *bus, const struct iwl_trans_ops *trans_ops,
1818 * strange state ... like being left stranded by a primary kernel 1818 * strange state ... like being left stranded by a primary kernel
1819 * and this is now the kdump kernel trying to start up 1819 * and this is now the kdump kernel trying to start up
1820 */ 1820 */
1821 iwl_write32(bus(priv), CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); 1821 iwl_write32(trans(priv), CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
1822 1822
1823 /*********************** 1823 /***********************
1824 * 3. Read REV register 1824 * 3. Read REV register
@@ -1903,7 +1903,7 @@ int iwl_probe(struct iwl_bus *bus, const struct iwl_trans_ops *trans_ops,
1903 iwl_enable_rfkill_int(priv); 1903 iwl_enable_rfkill_int(priv);
1904 1904
1905 /* If platform's RF_KILL switch is NOT set to KILL */ 1905 /* If platform's RF_KILL switch is NOT set to KILL */
1906 if (iwl_read32(bus(priv), 1906 if (iwl_read32(trans(priv),
1907 CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) 1907 CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
1908 clear_bit(STATUS_RF_KILL_HW, &priv->shrd->status); 1908 clear_bit(STATUS_RF_KILL_HW, &priv->shrd->status);
1909 else 1909 else
diff --git a/drivers/net/wireless/iwlwifi/iwl-bus.h b/drivers/net/wireless/iwlwifi/iwl-bus.h
index 981f7b79d39..ce1a9cc106e 100644
--- a/drivers/net/wireless/iwlwifi/iwl-bus.h
+++ b/drivers/net/wireless/iwlwifi/iwl-bus.h
@@ -142,15 +142,12 @@ struct iwl_bus_ops {
142 * @shrd - pointer to iwl_shared which holds shared data from the upper layer 142 * @shrd - pointer to iwl_shared which holds shared data from the upper layer
143 * NB: for the time being this needs to be set by the upper layer since 143 * NB: for the time being this needs to be set by the upper layer since
144 * it allocates the shared data 144 * it allocates the shared data
145 * @reg_lock - protect hw register access
146 */ 145 */
147struct iwl_bus { 146struct iwl_bus {
148 struct device *dev; 147 struct device *dev;
149 const struct iwl_bus_ops *ops; 148 const struct iwl_bus_ops *ops;
150 struct iwl_shared *shrd; 149 struct iwl_shared *shrd;
151 150
152 spinlock_t reg_lock;
153
154 /* pointer to bus specific struct */ 151 /* pointer to bus specific struct */
155 /*Ensure that this pointer will always be aligned to sizeof pointer */ 152 /*Ensure that this pointer will always be aligned to sizeof pointer */
156 char bus_specific[0] __attribute__((__aligned__(sizeof(void *)))); 153 char bus_specific[0] __attribute__((__aligned__(sizeof(void *))));
diff --git a/drivers/net/wireless/iwlwifi/iwl-core.c b/drivers/net/wireless/iwlwifi/iwl-core.c
index 7d6eef96454..c9022c5fa81 100644
--- a/drivers/net/wireless/iwlwifi/iwl-core.c
+++ b/drivers/net/wireless/iwlwifi/iwl-core.c
@@ -888,9 +888,9 @@ static int iwl_apm_stop_master(struct iwl_priv *priv)
888 int ret = 0; 888 int ret = 0;
889 889
890 /* stop device's busmaster DMA activity */ 890 /* stop device's busmaster DMA activity */
891 iwl_set_bit(bus(priv), CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); 891 iwl_set_bit(trans(priv), CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
892 892
893 ret = iwl_poll_bit(bus(priv), CSR_RESET, 893 ret = iwl_poll_bit(trans(priv), CSR_RESET,
894 CSR_RESET_REG_FLAG_MASTER_DISABLED, 894 CSR_RESET_REG_FLAG_MASTER_DISABLED,
895 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); 895 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
896 if (ret) 896 if (ret)
@@ -911,7 +911,7 @@ void iwl_apm_stop(struct iwl_priv *priv)
911 iwl_apm_stop_master(priv); 911 iwl_apm_stop_master(priv);
912 912
913 /* Reset the entire device */ 913 /* Reset the entire device */
914 iwl_set_bit(bus(priv), CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 914 iwl_set_bit(trans(priv), CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
915 915
916 udelay(10); 916 udelay(10);
917 917
@@ -919,7 +919,8 @@ void iwl_apm_stop(struct iwl_priv *priv)
919 * Clear "initialization complete" bit to move adapter from 919 * Clear "initialization complete" bit to move adapter from
920 * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 920 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
921 */ 921 */
922 iwl_clear_bit(bus(priv), CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 922 iwl_clear_bit(trans(priv), CSR_GP_CNTRL,
923 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
923} 924}
924 925
925 926
@@ -939,45 +940,46 @@ int iwl_apm_init(struct iwl_priv *priv)
939 */ 940 */
940 941
941 /* Disable L0S exit timer (platform NMI Work/Around) */ 942 /* Disable L0S exit timer (platform NMI Work/Around) */
942 iwl_set_bit(bus(priv), CSR_GIO_CHICKEN_BITS, 943 iwl_set_bit(trans(priv), CSR_GIO_CHICKEN_BITS,
943 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); 944 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
944 945
945 /* 946 /*
946 * Disable L0s without affecting L1; 947 * Disable L0s without affecting L1;
947 * don't wait for ICH L0s (ICH bug W/A) 948 * don't wait for ICH L0s (ICH bug W/A)
948 */ 949 */
949 iwl_set_bit(bus(priv), CSR_GIO_CHICKEN_BITS, 950 iwl_set_bit(trans(priv), CSR_GIO_CHICKEN_BITS,
950 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 951 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
951 952
952 /* Set FH wait threshold to maximum (HW error during stress W/A) */ 953 /* Set FH wait threshold to maximum (HW error during stress W/A) */
953 iwl_set_bit(bus(priv), CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); 954 iwl_set_bit(trans(priv), CSR_DBG_HPET_MEM_REG,
955 CSR_DBG_HPET_MEM_REG_VAL);
954 956
955 /* 957 /*
956 * Enable HAP INTA (interrupt from management bus) to 958 * Enable HAP INTA (interrupt from management bus) to
957 * wake device's PCI Express link L1a -> L0s 959 * wake device's PCI Express link L1a -> L0s
958 */ 960 */
959 iwl_set_bit(bus(priv), CSR_HW_IF_CONFIG_REG, 961 iwl_set_bit(trans(priv), CSR_HW_IF_CONFIG_REG,
960 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); 962 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
961 963
962 bus_apm_config(bus(priv)); 964 bus_apm_config(bus(priv));
963 965
964 /* Configure analog phase-lock-loop before activating to D0A */ 966 /* Configure analog phase-lock-loop before activating to D0A */
965 if (cfg(priv)->base_params->pll_cfg_val) 967 if (cfg(priv)->base_params->pll_cfg_val)
966 iwl_set_bit(bus(priv), CSR_ANA_PLL_CFG, 968 iwl_set_bit(trans(priv), CSR_ANA_PLL_CFG,
967 cfg(priv)->base_params->pll_cfg_val); 969 cfg(priv)->base_params->pll_cfg_val);
968 970
969 /* 971 /*
970 * Set "initialization complete" bit to move adapter from 972 * Set "initialization complete" bit to move adapter from
971 * D0U* --> D0A* (powered-up active) state. 973 * D0U* --> D0A* (powered-up active) state.
972 */ 974 */
973 iwl_set_bit(bus(priv), CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 975 iwl_set_bit(trans(priv), CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
974 976
975 /* 977 /*
976 * Wait for clock stabilization; once stabilized, access to 978 * Wait for clock stabilization; once stabilized, access to
977 * device-internal resources is supported, e.g. iwl_write_prph() 979 * device-internal resources is supported, e.g. iwl_write_prph()
978 * and accesses to uCode SRAM. 980 * and accesses to uCode SRAM.
979 */ 981 */
980 ret = iwl_poll_bit(bus(priv), CSR_GP_CNTRL, 982 ret = iwl_poll_bit(trans(priv), CSR_GP_CNTRL,
981 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 983 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
982 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); 984 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
983 if (ret < 0) { 985 if (ret < 0) {
@@ -992,11 +994,11 @@ int iwl_apm_init(struct iwl_priv *priv)
992 * do not disable clocks. This preserves any hardware bits already 994 * do not disable clocks. This preserves any hardware bits already
993 * set by default in "CLK_CTRL_REG" after reset. 995 * set by default in "CLK_CTRL_REG" after reset.
994 */ 996 */
995 iwl_write_prph(bus(priv), APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT); 997 iwl_write_prph(trans(priv), APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
996 udelay(20); 998 udelay(20);
997 999
998 /* Disable L1-Active */ 1000 /* Disable L1-Active */
999 iwl_set_bits_prph(bus(priv), APMG_PCIDEV_STT_REG, 1001 iwl_set_bits_prph(trans(priv), APMG_PCIDEV_STT_REG,
1000 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 1002 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1001 1003
1002 set_bit(STATUS_DEVICE_ENABLED, &priv->shrd->status); 1004 set_bit(STATUS_DEVICE_ENABLED, &priv->shrd->status);
diff --git a/drivers/net/wireless/iwlwifi/iwl-core.h b/drivers/net/wireless/iwlwifi/iwl-core.h
index 63f29111da1..e74bfb7bbb2 100644
--- a/drivers/net/wireless/iwlwifi/iwl-core.h
+++ b/drivers/net/wireless/iwlwifi/iwl-core.h
@@ -300,7 +300,7 @@ static inline bool iwl_advanced_bt_coexist(struct iwl_priv *priv)
300static inline void iwl_enable_rfkill_int(struct iwl_priv *priv) 300static inline void iwl_enable_rfkill_int(struct iwl_priv *priv)
301{ 301{
302 IWL_DEBUG_ISR(priv, "Enabling rfkill interrupt\n"); 302 IWL_DEBUG_ISR(priv, "Enabling rfkill interrupt\n");
303 iwl_write32(bus(priv), CSR_INT_MASK, CSR_INT_BIT_RF_KILL); 303 iwl_write32(trans(priv), CSR_INT_MASK, CSR_INT_BIT_RF_KILL);
304} 304}
305 305
306extern bool bt_siso_mode; 306extern bool bt_siso_mode;
diff --git a/drivers/net/wireless/iwlwifi/iwl-debugfs.c b/drivers/net/wireless/iwlwifi/iwl-debugfs.c
index 978a1d4c6a0..136de6fb3fa 100644
--- a/drivers/net/wireless/iwlwifi/iwl-debugfs.c
+++ b/drivers/net/wireless/iwlwifi/iwl-debugfs.c
@@ -263,7 +263,7 @@ static ssize_t iwl_dbgfs_sram_read(struct file *file,
263 sram = priv->dbgfs_sram_offset & ~0x3; 263 sram = priv->dbgfs_sram_offset & ~0x3;
264 264
265 /* read the first u32 from sram */ 265 /* read the first u32 from sram */
266 val = iwl_read_targ_mem(bus(priv), sram); 266 val = iwl_read_targ_mem(trans(priv), sram);
267 267
268 for (; len; len--) { 268 for (; len; len--) {
269 /* put the address at the start of every line */ 269 /* put the address at the start of every line */
@@ -282,7 +282,7 @@ static ssize_t iwl_dbgfs_sram_read(struct file *file,
282 if (++offset == 4) { 282 if (++offset == 4) {
283 sram += 4; 283 sram += 4;
284 offset = 0; 284 offset = 0;
285 val = iwl_read_targ_mem(bus(priv), sram); 285 val = iwl_read_targ_mem(trans(priv), sram);
286 } 286 }
287 287
288 /* put in extra spaces and split lines for human readability */ 288 /* put in extra spaces and split lines for human readability */
@@ -2055,7 +2055,7 @@ static ssize_t iwl_dbgfs_power_save_status_read(struct file *file,
2055 const size_t bufsz = sizeof(buf); 2055 const size_t bufsz = sizeof(buf);
2056 u32 pwrsave_status; 2056 u32 pwrsave_status;
2057 2057
2058 pwrsave_status = iwl_read32(bus(priv), CSR_GP_CNTRL) & 2058 pwrsave_status = iwl_read32(trans(priv), CSR_GP_CNTRL) &
2059 CSR_GP_REG_POWER_SAVE_STATUS_MSK; 2059 CSR_GP_REG_POWER_SAVE_STATUS_MSK;
2060 2060
2061 pos += scnprintf(buf + pos, bufsz - pos, "Power Save Status: "); 2061 pos += scnprintf(buf + pos, bufsz - pos, "Power Save Status: ");
diff --git a/drivers/net/wireless/iwlwifi/iwl-eeprom.c b/drivers/net/wireless/iwlwifi/iwl-eeprom.c
index ce214e0ab49..d1fd1cdb29c 100644
--- a/drivers/net/wireless/iwlwifi/iwl-eeprom.c
+++ b/drivers/net/wireless/iwlwifi/iwl-eeprom.c
@@ -156,16 +156,16 @@ static int iwl_eeprom_acquire_semaphore(struct iwl_bus *bus)
156 156
157 for (count = 0; count < EEPROM_SEM_RETRY_LIMIT; count++) { 157 for (count = 0; count < EEPROM_SEM_RETRY_LIMIT; count++) {
158 /* Request semaphore */ 158 /* Request semaphore */
159 iwl_set_bit(bus, CSR_HW_IF_CONFIG_REG, 159 iwl_set_bit(trans(bus), CSR_HW_IF_CONFIG_REG,
160 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM); 160 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM);
161 161
162 /* See if we got it */ 162 /* See if we got it */
163 ret = iwl_poll_bit(bus, CSR_HW_IF_CONFIG_REG, 163 ret = iwl_poll_bit(trans(bus), CSR_HW_IF_CONFIG_REG,
164 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM, 164 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM,
165 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM, 165 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM,
166 EEPROM_SEM_TIMEOUT); 166 EEPROM_SEM_TIMEOUT);
167 if (ret >= 0) { 167 if (ret >= 0) {
168 IWL_DEBUG_EEPROM(bus, 168 IWL_DEBUG_EEPROM(trans(bus),
169 "Acquired semaphore after %d tries.\n", 169 "Acquired semaphore after %d tries.\n",
170 count+1); 170 count+1);
171 return ret; 171 return ret;
@@ -177,14 +177,15 @@ static int iwl_eeprom_acquire_semaphore(struct iwl_bus *bus)
177 177
178static void iwl_eeprom_release_semaphore(struct iwl_bus *bus) 178static void iwl_eeprom_release_semaphore(struct iwl_bus *bus)
179{ 179{
180 iwl_clear_bit(bus, CSR_HW_IF_CONFIG_REG, 180 iwl_clear_bit(trans(bus), CSR_HW_IF_CONFIG_REG,
181 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM); 181 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM);
182 182
183} 183}
184 184
185static int iwl_eeprom_verify_signature(struct iwl_trans *trans) 185static int iwl_eeprom_verify_signature(struct iwl_trans *trans)
186{ 186{
187 u32 gp = iwl_read32(bus(trans), CSR_EEPROM_GP) & CSR_EEPROM_GP_VALID_MSK; 187 u32 gp = iwl_read32(trans, CSR_EEPROM_GP) &
188 CSR_EEPROM_GP_VALID_MSK;
188 int ret = 0; 189 int ret = 0;
189 190
190 IWL_DEBUG_EEPROM(trans, "EEPROM signature=0x%08x\n", gp); 191 IWL_DEBUG_EEPROM(trans, "EEPROM signature=0x%08x\n", gp);
@@ -305,13 +306,13 @@ void iwl_eeprom_get_mac(const struct iwl_shared *shrd, u8 *mac)
305 306
306static void iwl_set_otp_access(struct iwl_bus *bus, enum iwl_access_mode mode) 307static void iwl_set_otp_access(struct iwl_bus *bus, enum iwl_access_mode mode)
307{ 308{
308 iwl_read32(bus, CSR_OTP_GP_REG); 309 iwl_read32(trans(bus), CSR_OTP_GP_REG);
309 310
310 if (mode == IWL_OTP_ACCESS_ABSOLUTE) 311 if (mode == IWL_OTP_ACCESS_ABSOLUTE)
311 iwl_clear_bit(bus, CSR_OTP_GP_REG, 312 iwl_clear_bit(trans(bus), CSR_OTP_GP_REG,
312 CSR_OTP_GP_REG_OTP_ACCESS_MODE); 313 CSR_OTP_GP_REG_OTP_ACCESS_MODE);
313 else 314 else
314 iwl_set_bit(bus, CSR_OTP_GP_REG, 315 iwl_set_bit(trans(bus), CSR_OTP_GP_REG,
315 CSR_OTP_GP_REG_OTP_ACCESS_MODE); 316 CSR_OTP_GP_REG_OTP_ACCESS_MODE);
316} 317}
317 318
@@ -332,7 +333,7 @@ static int iwl_get_nvm_type(struct iwl_bus *bus, u32 hw_rev)
332 nvm_type = NVM_DEVICE_TYPE_EEPROM; 333 nvm_type = NVM_DEVICE_TYPE_EEPROM;
333 break; 334 break;
334 default: 335 default:
335 otpgp = iwl_read32(bus, CSR_OTP_GP_REG); 336 otpgp = iwl_read32(trans(bus), CSR_OTP_GP_REG);
336 if (otpgp & CSR_OTP_GP_REG_DEVICE_SELECT) 337 if (otpgp & CSR_OTP_GP_REG_DEVICE_SELECT)
337 nvm_type = NVM_DEVICE_TYPE_OTP; 338 nvm_type = NVM_DEVICE_TYPE_OTP;
338 else 339 else
@@ -347,22 +348,22 @@ static int iwl_init_otp_access(struct iwl_bus *bus)
347 int ret; 348 int ret;
348 349
349 /* Enable 40MHz radio clock */ 350 /* Enable 40MHz radio clock */
350 iwl_write32(bus, CSR_GP_CNTRL, 351 iwl_write32(trans(bus), CSR_GP_CNTRL,
351 iwl_read32(bus, CSR_GP_CNTRL) | 352 iwl_read32(trans(bus), CSR_GP_CNTRL) |
352 CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 353 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
353 354
354 /* wait for clock to be ready */ 355 /* wait for clock to be ready */
355 ret = iwl_poll_bit(bus, CSR_GP_CNTRL, 356 ret = iwl_poll_bit(trans(bus), CSR_GP_CNTRL,
356 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 357 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
357 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 358 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
358 25000); 359 25000);
359 if (ret < 0) 360 if (ret < 0)
360 IWL_ERR(bus, "Time out access OTP\n"); 361 IWL_ERR(bus, "Time out access OTP\n");
361 else { 362 else {
362 iwl_set_bits_prph(bus, APMG_PS_CTRL_REG, 363 iwl_set_bits_prph(trans(bus), APMG_PS_CTRL_REG,
363 APMG_PS_CTRL_VAL_RESET_REQ); 364 APMG_PS_CTRL_VAL_RESET_REQ);
364 udelay(5); 365 udelay(5);
365 iwl_clear_bits_prph(bus, APMG_PS_CTRL_REG, 366 iwl_clear_bits_prph(trans(bus), APMG_PS_CTRL_REG,
366 APMG_PS_CTRL_VAL_RESET_REQ); 367 APMG_PS_CTRL_VAL_RESET_REQ);
367 368
368 /* 369 /*
@@ -370,7 +371,7 @@ static int iwl_init_otp_access(struct iwl_bus *bus)
370 * this is only applicable for HW with OTP shadow RAM 371 * this is only applicable for HW with OTP shadow RAM
371 */ 372 */
372 if (cfg(bus)->base_params->shadow_ram_support) 373 if (cfg(bus)->base_params->shadow_ram_support)
373 iwl_set_bit(bus, CSR_DBG_LINK_PWR_MGMT_REG, 374 iwl_set_bit(trans(bus), CSR_DBG_LINK_PWR_MGMT_REG,
374 CSR_RESET_LINK_PWR_MGMT_DISABLED); 375 CSR_RESET_LINK_PWR_MGMT_DISABLED);
375 } 376 }
376 return ret; 377 return ret;
@@ -382,9 +383,9 @@ static int iwl_read_otp_word(struct iwl_bus *bus, u16 addr, __le16 *eeprom_data)
382 u32 r; 383 u32 r;
383 u32 otpgp; 384 u32 otpgp;
384 385
385 iwl_write32(bus, CSR_EEPROM_REG, 386 iwl_write32(trans(bus), CSR_EEPROM_REG,
386 CSR_EEPROM_REG_MSK_ADDR & (addr << 1)); 387 CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
387 ret = iwl_poll_bit(bus, CSR_EEPROM_REG, 388 ret = iwl_poll_bit(trans(bus), CSR_EEPROM_REG,
388 CSR_EEPROM_REG_READ_VALID_MSK, 389 CSR_EEPROM_REG_READ_VALID_MSK,
389 CSR_EEPROM_REG_READ_VALID_MSK, 390 CSR_EEPROM_REG_READ_VALID_MSK,
390 IWL_EEPROM_ACCESS_TIMEOUT); 391 IWL_EEPROM_ACCESS_TIMEOUT);
@@ -392,13 +393,13 @@ static int iwl_read_otp_word(struct iwl_bus *bus, u16 addr, __le16 *eeprom_data)
392 IWL_ERR(bus, "Time out reading OTP[%d]\n", addr); 393 IWL_ERR(bus, "Time out reading OTP[%d]\n", addr);
393 return ret; 394 return ret;
394 } 395 }
395 r = iwl_read32(bus, CSR_EEPROM_REG); 396 r = iwl_read32(trans(bus), CSR_EEPROM_REG);
396 /* check for ECC errors: */ 397 /* check for ECC errors: */
397 otpgp = iwl_read32(bus, CSR_OTP_GP_REG); 398 otpgp = iwl_read32(trans(bus), CSR_OTP_GP_REG);
398 if (otpgp & CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK) { 399 if (otpgp & CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK) {
399 /* stop in this case */ 400 /* stop in this case */
400 /* set the uncorrectable OTP ECC bit for acknowledgement */ 401 /* set the uncorrectable OTP ECC bit for acknowledgement */
401 iwl_set_bit(bus, CSR_OTP_GP_REG, 402 iwl_set_bit(trans(bus), CSR_OTP_GP_REG,
402 CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK); 403 CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK);
403 IWL_ERR(bus, "Uncorrectable OTP ECC error, abort OTP read\n"); 404 IWL_ERR(bus, "Uncorrectable OTP ECC error, abort OTP read\n");
404 return -EINVAL; 405 return -EINVAL;
@@ -406,7 +407,7 @@ static int iwl_read_otp_word(struct iwl_bus *bus, u16 addr, __le16 *eeprom_data)
406 if (otpgp & CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK) { 407 if (otpgp & CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK) {
407 /* continue in this case */ 408 /* continue in this case */
408 /* set the correctable OTP ECC bit for acknowledgement */ 409 /* set the correctable OTP ECC bit for acknowledgement */
409 iwl_set_bit(bus, CSR_OTP_GP_REG, 410 iwl_set_bit(trans(bus), CSR_OTP_GP_REG,
410 CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK); 411 CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK);
411 IWL_ERR(bus, "Correctable OTP ECC error, continue read\n"); 412 IWL_ERR(bus, "Correctable OTP ECC error, continue read\n");
412 } 413 }
@@ -656,7 +657,7 @@ int iwl_eeprom_init(struct iwl_priv *priv, u32 hw_rev)
656{ 657{
657 struct iwl_shared *shrd = priv->shrd; 658 struct iwl_shared *shrd = priv->shrd;
658 __le16 *e; 659 __le16 *e;
659 u32 gp = iwl_read32(bus(priv), CSR_EEPROM_GP); 660 u32 gp = iwl_read32(trans(priv), CSR_EEPROM_GP);
660 int sz; 661 int sz;
661 int ret; 662 int ret;
662 u16 addr; 663 u16 addr;
@@ -699,11 +700,11 @@ int iwl_eeprom_init(struct iwl_priv *priv, u32 hw_rev)
699 ret = -ENOENT; 700 ret = -ENOENT;
700 goto done; 701 goto done;
701 } 702 }
702 iwl_write32(bus(priv), CSR_EEPROM_GP, 703 iwl_write32(trans(priv), CSR_EEPROM_GP,
703 iwl_read32(bus(priv), CSR_EEPROM_GP) & 704 iwl_read32(trans(priv), CSR_EEPROM_GP) &
704 ~CSR_EEPROM_GP_IF_OWNER_MSK); 705 ~CSR_EEPROM_GP_IF_OWNER_MSK);
705 706
706 iwl_set_bit(bus(priv), CSR_OTP_GP_REG, 707 iwl_set_bit(trans(priv), CSR_OTP_GP_REG,
707 CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK | 708 CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK |
708 CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK); 709 CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK);
709 /* traversing the linked list if no shadow ram supported */ 710 /* traversing the linked list if no shadow ram supported */
@@ -728,10 +729,10 @@ int iwl_eeprom_init(struct iwl_priv *priv, u32 hw_rev)
728 for (addr = 0; addr < sz; addr += sizeof(u16)) { 729 for (addr = 0; addr < sz; addr += sizeof(u16)) {
729 u32 r; 730 u32 r;
730 731
731 iwl_write32(bus(priv), CSR_EEPROM_REG, 732 iwl_write32(trans(priv), CSR_EEPROM_REG,
732 CSR_EEPROM_REG_MSK_ADDR & (addr << 1)); 733 CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
733 734
734 ret = iwl_poll_bit(bus(priv), CSR_EEPROM_REG, 735 ret = iwl_poll_bit(trans(priv), CSR_EEPROM_REG,
735 CSR_EEPROM_REG_READ_VALID_MSK, 736 CSR_EEPROM_REG_READ_VALID_MSK,
736 CSR_EEPROM_REG_READ_VALID_MSK, 737 CSR_EEPROM_REG_READ_VALID_MSK,
737 IWL_EEPROM_ACCESS_TIMEOUT); 738 IWL_EEPROM_ACCESS_TIMEOUT);
@@ -739,7 +740,7 @@ int iwl_eeprom_init(struct iwl_priv *priv, u32 hw_rev)
739 IWL_ERR(priv, "Time out reading EEPROM[%d]\n", addr); 740 IWL_ERR(priv, "Time out reading EEPROM[%d]\n", addr);
740 goto done; 741 goto done;
741 } 742 }
742 r = iwl_read32(bus(priv), CSR_EEPROM_REG); 743 r = iwl_read32(trans(priv), CSR_EEPROM_REG);
743 e[addr / 2] = cpu_to_le16(r >> 16); 744 e[addr / 2] = cpu_to_le16(r >> 16);
744 } 745 }
745 } 746 }
@@ -1068,7 +1069,7 @@ void iwl_rf_config(struct iwl_priv *priv)
1068 1069
1069 /* write radio config values to register */ 1070 /* write radio config values to register */
1070 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) <= EEPROM_RF_CONFIG_TYPE_MAX) { 1071 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) <= EEPROM_RF_CONFIG_TYPE_MAX) {
1071 iwl_set_bit(bus(priv), CSR_HW_IF_CONFIG_REG, 1072 iwl_set_bit(trans(priv), CSR_HW_IF_CONFIG_REG,
1072 EEPROM_RF_CFG_TYPE_MSK(radio_cfg) | 1073 EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
1073 EEPROM_RF_CFG_STEP_MSK(radio_cfg) | 1074 EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
1074 EEPROM_RF_CFG_DASH_MSK(radio_cfg)); 1075 EEPROM_RF_CFG_DASH_MSK(radio_cfg));
@@ -1080,7 +1081,7 @@ void iwl_rf_config(struct iwl_priv *priv)
1080 WARN_ON(1); 1081 WARN_ON(1);
1081 1082
1082 /* set CSR_HW_CONFIG_REG for uCode use */ 1083 /* set CSR_HW_CONFIG_REG for uCode use */
1083 iwl_set_bit(bus(priv), CSR_HW_IF_CONFIG_REG, 1084 iwl_set_bit(trans(priv), CSR_HW_IF_CONFIG_REG,
1084 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI | 1085 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
1085 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI); 1086 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
1086} 1087}
diff --git a/drivers/net/wireless/iwlwifi/iwl-io.c b/drivers/net/wireless/iwlwifi/iwl-io.c
index 83fdff38115..e2e3b5c9cf7 100644
--- a/drivers/net/wireless/iwlwifi/iwl-io.c
+++ b/drivers/net/wireless/iwlwifi/iwl-io.c
@@ -34,41 +34,41 @@
34 34
35#define IWL_POLL_INTERVAL 10 /* microseconds */ 35#define IWL_POLL_INTERVAL 10 /* microseconds */
36 36
37static inline void __iwl_set_bit(struct iwl_bus *bus, u32 reg, u32 mask) 37static inline void __iwl_set_bit(struct iwl_trans *trans, u32 reg, u32 mask)
38{ 38{
39 iwl_write32(bus, reg, iwl_read32(bus, reg) | mask); 39 iwl_write32(trans, reg, iwl_read32(trans, reg) | mask);
40} 40}
41 41
42static inline void __iwl_clear_bit(struct iwl_bus *bus, u32 reg, u32 mask) 42static inline void __iwl_clear_bit(struct iwl_trans *trans, u32 reg, u32 mask)
43{ 43{
44 iwl_write32(bus, reg, iwl_read32(bus, reg) & ~mask); 44 iwl_write32(trans, reg, iwl_read32(trans, reg) & ~mask);
45} 45}
46 46
47void iwl_set_bit(struct iwl_bus *bus, u32 reg, u32 mask) 47void iwl_set_bit(struct iwl_trans *trans, u32 reg, u32 mask)
48{ 48{
49 unsigned long flags; 49 unsigned long flags;
50 50
51 spin_lock_irqsave(&bus->reg_lock, flags); 51 spin_lock_irqsave(&trans->reg_lock, flags);
52 __iwl_set_bit(bus, reg, mask); 52 __iwl_set_bit(trans, reg, mask);
53 spin_unlock_irqrestore(&bus->reg_lock, flags); 53 spin_unlock_irqrestore(&trans->reg_lock, flags);
54} 54}
55 55
56void iwl_clear_bit(struct iwl_bus *bus, u32 reg, u32 mask) 56void iwl_clear_bit(struct iwl_trans *trans, u32 reg, u32 mask)
57{ 57{
58 unsigned long flags; 58 unsigned long flags;
59 59
60 spin_lock_irqsave(&bus->reg_lock, flags); 60 spin_lock_irqsave(&trans->reg_lock, flags);
61 __iwl_clear_bit(bus, reg, mask); 61 __iwl_clear_bit(trans, reg, mask);
62 spin_unlock_irqrestore(&bus->reg_lock, flags); 62 spin_unlock_irqrestore(&trans->reg_lock, flags);
63} 63}
64 64
65int iwl_poll_bit(struct iwl_bus *bus, u32 addr, 65int iwl_poll_bit(struct iwl_trans *trans, u32 addr,
66 u32 bits, u32 mask, int timeout) 66 u32 bits, u32 mask, int timeout)
67{ 67{
68 int t = 0; 68 int t = 0;
69 69
70 do { 70 do {
71 if ((iwl_read32(bus, addr) & mask) == (bits & mask)) 71 if ((iwl_read32(trans, addr) & mask) == (bits & mask))
72 return t; 72 return t;
73 udelay(IWL_POLL_INTERVAL); 73 udelay(IWL_POLL_INTERVAL);
74 t += IWL_POLL_INTERVAL; 74 t += IWL_POLL_INTERVAL;
@@ -77,14 +77,15 @@ int iwl_poll_bit(struct iwl_bus *bus, u32 addr,
77 return -ETIMEDOUT; 77 return -ETIMEDOUT;
78} 78}
79 79
80int iwl_grab_nic_access_silent(struct iwl_bus *bus) 80int iwl_grab_nic_access_silent(struct iwl_trans *trans)
81{ 81{
82 int ret; 82 int ret;
83 83
84 lockdep_assert_held(&bus->reg_lock); 84 lockdep_assert_held(&trans->reg_lock);
85 85
86 /* this bit wakes up the NIC */ 86 /* this bit wakes up the NIC */
87 __iwl_set_bit(bus, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 87 __iwl_set_bit(trans, CSR_GP_CNTRL,
88 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
88 89
89 /* 90 /*
90 * These bits say the device is running, and should keep running for 91 * These bits say the device is running, and should keep running for
@@ -105,70 +106,70 @@ int iwl_grab_nic_access_silent(struct iwl_bus *bus)
105 * 5000 series and later (including 1000 series) have non-volatile SRAM, 106 * 5000 series and later (including 1000 series) have non-volatile SRAM,
106 * and do not save/restore SRAM when power cycling. 107 * and do not save/restore SRAM when power cycling.
107 */ 108 */
108 ret = iwl_poll_bit(bus, CSR_GP_CNTRL, 109 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
109 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN, 110 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
110 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | 111 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
111 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000); 112 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
112 if (ret < 0) { 113 if (ret < 0) {
113 iwl_write32(bus, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI); 114 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
114 return -EIO; 115 return -EIO;
115 } 116 }
116 117
117 return 0; 118 return 0;
118} 119}
119 120
120int iwl_grab_nic_access(struct iwl_bus *bus) 121int iwl_grab_nic_access(struct iwl_trans *trans)
121{ 122{
122 int ret = iwl_grab_nic_access_silent(bus); 123 int ret = iwl_grab_nic_access_silent(trans);
123 if (ret) { 124 if (ret) {
124 u32 val = iwl_read32(bus, CSR_GP_CNTRL); 125 u32 val = iwl_read32(trans, CSR_GP_CNTRL);
125 IWL_ERR(bus, 126 IWL_ERR(trans,
126 "MAC is in deep sleep!. CSR_GP_CNTRL = 0x%08X\n", val); 127 "MAC is in deep sleep!. CSR_GP_CNTRL = 0x%08X\n", val);
127 } 128 }
128 129
129 return ret; 130 return ret;
130} 131}
131 132
132void iwl_release_nic_access(struct iwl_bus *bus) 133void iwl_release_nic_access(struct iwl_trans *trans)
133{ 134{
134 lockdep_assert_held(&bus->reg_lock); 135 lockdep_assert_held(&trans->reg_lock);
135 __iwl_clear_bit(bus, CSR_GP_CNTRL, 136 __iwl_clear_bit(trans, CSR_GP_CNTRL,
136 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 137 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
137} 138}
138 139
139u32 iwl_read_direct32(struct iwl_bus *bus, u32 reg) 140u32 iwl_read_direct32(struct iwl_trans *trans, u32 reg)
140{ 141{
141 u32 value; 142 u32 value;
142 unsigned long flags; 143 unsigned long flags;
143 144
144 spin_lock_irqsave(&bus->reg_lock, flags); 145 spin_lock_irqsave(&trans->reg_lock, flags);
145 iwl_grab_nic_access(bus); 146 iwl_grab_nic_access(trans);
146 value = iwl_read32(bus, reg); 147 value = iwl_read32(trans, reg);
147 iwl_release_nic_access(bus); 148 iwl_release_nic_access(trans);
148 spin_unlock_irqrestore(&bus->reg_lock, flags); 149 spin_unlock_irqrestore(&trans->reg_lock, flags);
149 150
150 return value; 151 return value;
151} 152}
152 153
153void iwl_write_direct32(struct iwl_bus *bus, u32 reg, u32 value) 154void iwl_write_direct32(struct iwl_trans *trans, u32 reg, u32 value)
154{ 155{
155 unsigned long flags; 156 unsigned long flags;
156 157
157 spin_lock_irqsave(&bus->reg_lock, flags); 158 spin_lock_irqsave(&trans->reg_lock, flags);
158 if (!iwl_grab_nic_access(bus)) { 159 if (!iwl_grab_nic_access(trans)) {
159 iwl_write32(bus, reg, value); 160 iwl_write32(trans, reg, value);
160 iwl_release_nic_access(bus); 161 iwl_release_nic_access(trans);
161 } 162 }
162 spin_unlock_irqrestore(&bus->reg_lock, flags); 163 spin_unlock_irqrestore(&trans->reg_lock, flags);
163} 164}
164 165
165int iwl_poll_direct_bit(struct iwl_bus *bus, u32 addr, u32 mask, 166int iwl_poll_direct_bit(struct iwl_trans *trans, u32 addr, u32 mask,
166 int timeout) 167 int timeout)
167{ 168{
168 int t = 0; 169 int t = 0;
169 170
170 do { 171 do {
171 if ((iwl_read_direct32(bus, addr) & mask) == mask) 172 if ((iwl_read_direct32(trans, addr) & mask) == mask)
172 return t; 173 return t;
173 udelay(IWL_POLL_INTERVAL); 174 udelay(IWL_POLL_INTERVAL);
174 t += IWL_POLL_INTERVAL; 175 t += IWL_POLL_INTERVAL;
@@ -177,135 +178,135 @@ int iwl_poll_direct_bit(struct iwl_bus *bus, u32 addr, u32 mask,
177 return -ETIMEDOUT; 178 return -ETIMEDOUT;
178} 179}
179 180
180static inline u32 __iwl_read_prph(struct iwl_bus *bus, u32 reg) 181static inline u32 __iwl_read_prph(struct iwl_trans *trans, u32 reg)
181{ 182{
182 iwl_write32(bus, HBUS_TARG_PRPH_RADDR, reg | (3 << 24)); 183 iwl_write32(trans, HBUS_TARG_PRPH_RADDR, reg | (3 << 24));
183 rmb(); 184 rmb();
184 return iwl_read32(bus, HBUS_TARG_PRPH_RDAT); 185 return iwl_read32(trans, HBUS_TARG_PRPH_RDAT);
185} 186}
186 187
187static inline void __iwl_write_prph(struct iwl_bus *bus, u32 addr, u32 val) 188static inline void __iwl_write_prph(struct iwl_trans *trans, u32 addr, u32 val)
188{ 189{
189 iwl_write32(bus, HBUS_TARG_PRPH_WADDR, 190 iwl_write32(trans, HBUS_TARG_PRPH_WADDR,
190 ((addr & 0x0000FFFF) | (3 << 24))); 191 ((addr & 0x0000FFFF) | (3 << 24)));
191 wmb(); 192 wmb();
192 iwl_write32(bus, HBUS_TARG_PRPH_WDAT, val); 193 iwl_write32(trans, HBUS_TARG_PRPH_WDAT, val);
193} 194}
194 195
195u32 iwl_read_prph(struct iwl_bus *bus, u32 reg) 196u32 iwl_read_prph(struct iwl_trans *trans, u32 reg)
196{ 197{
197 unsigned long flags; 198 unsigned long flags;
198 u32 val; 199 u32 val;
199 200
200 spin_lock_irqsave(&bus->reg_lock, flags); 201 spin_lock_irqsave(&trans->reg_lock, flags);
201 iwl_grab_nic_access(bus); 202 iwl_grab_nic_access(trans);
202 val = __iwl_read_prph(bus, reg); 203 val = __iwl_read_prph(trans, reg);
203 iwl_release_nic_access(bus); 204 iwl_release_nic_access(trans);
204 spin_unlock_irqrestore(&bus->reg_lock, flags); 205 spin_unlock_irqrestore(&trans->reg_lock, flags);
205 return val; 206 return val;
206} 207}
207 208
208void iwl_write_prph(struct iwl_bus *bus, u32 addr, u32 val) 209void iwl_write_prph(struct iwl_trans *trans, u32 addr, u32 val)
209{ 210{
210 unsigned long flags; 211 unsigned long flags;
211 212
212 spin_lock_irqsave(&bus->reg_lock, flags); 213 spin_lock_irqsave(&trans->reg_lock, flags);
213 if (!iwl_grab_nic_access(bus)) { 214 if (!iwl_grab_nic_access(trans)) {
214 __iwl_write_prph(bus, addr, val); 215 __iwl_write_prph(trans, addr, val);
215 iwl_release_nic_access(bus); 216 iwl_release_nic_access(trans);
216 } 217 }
217 spin_unlock_irqrestore(&bus->reg_lock, flags); 218 spin_unlock_irqrestore(&trans->reg_lock, flags);
218} 219}
219 220
220void iwl_set_bits_prph(struct iwl_bus *bus, u32 reg, u32 mask) 221void iwl_set_bits_prph(struct iwl_trans *trans, u32 reg, u32 mask)
221{ 222{
222 unsigned long flags; 223 unsigned long flags;
223 224
224 spin_lock_irqsave(&bus->reg_lock, flags); 225 spin_lock_irqsave(&trans->reg_lock, flags);
225 iwl_grab_nic_access(bus); 226 iwl_grab_nic_access(trans);
226 __iwl_write_prph(bus, reg, __iwl_read_prph(bus, reg) | mask); 227 __iwl_write_prph(trans, reg, __iwl_read_prph(trans, reg) | mask);
227 iwl_release_nic_access(bus); 228 iwl_release_nic_access(trans);
228 spin_unlock_irqrestore(&bus->reg_lock, flags); 229 spin_unlock_irqrestore(&trans->reg_lock, flags);
229} 230}
230 231
231void iwl_set_bits_mask_prph(struct iwl_bus *bus, u32 reg, 232void iwl_set_bits_mask_prph(struct iwl_trans *trans, u32 reg,
232 u32 bits, u32 mask) 233 u32 bits, u32 mask)
233{ 234{
234 unsigned long flags; 235 unsigned long flags;
235 236
236 spin_lock_irqsave(&bus->reg_lock, flags); 237 spin_lock_irqsave(&trans->reg_lock, flags);
237 iwl_grab_nic_access(bus); 238 iwl_grab_nic_access(trans);
238 __iwl_write_prph(bus, reg, 239 __iwl_write_prph(trans, reg,
239 (__iwl_read_prph(bus, reg) & mask) | bits); 240 (__iwl_read_prph(trans, reg) & mask) | bits);
240 iwl_release_nic_access(bus); 241 iwl_release_nic_access(trans);
241 spin_unlock_irqrestore(&bus->reg_lock, flags); 242 spin_unlock_irqrestore(&trans->reg_lock, flags);
242} 243}
243 244
244void iwl_clear_bits_prph(struct iwl_bus *bus, u32 reg, u32 mask) 245void iwl_clear_bits_prph(struct iwl_trans *trans, u32 reg, u32 mask)
245{ 246{
246 unsigned long flags; 247 unsigned long flags;
247 u32 val; 248 u32 val;
248 249
249 spin_lock_irqsave(&bus->reg_lock, flags); 250 spin_lock_irqsave(&trans->reg_lock, flags);
250 iwl_grab_nic_access(bus); 251 iwl_grab_nic_access(trans);
251 val = __iwl_read_prph(bus, reg); 252 val = __iwl_read_prph(trans, reg);
252 __iwl_write_prph(bus, reg, (val & ~mask)); 253 __iwl_write_prph(trans, reg, (val & ~mask));
253 iwl_release_nic_access(bus); 254 iwl_release_nic_access(trans);
254 spin_unlock_irqrestore(&bus->reg_lock, flags); 255 spin_unlock_irqrestore(&trans->reg_lock, flags);
255} 256}
256 257
257void _iwl_read_targ_mem_words(struct iwl_bus *bus, u32 addr, 258void _iwl_read_targ_mem_words(struct iwl_trans *trans, u32 addr,
258 void *buf, int words) 259 void *buf, int words)
259{ 260{
260 unsigned long flags; 261 unsigned long flags;
261 int offs; 262 int offs;
262 u32 *vals = buf; 263 u32 *vals = buf;
263 264
264 spin_lock_irqsave(&bus->reg_lock, flags); 265 spin_lock_irqsave(&trans->reg_lock, flags);
265 iwl_grab_nic_access(bus); 266 iwl_grab_nic_access(trans);
266 267
267 iwl_write32(bus, HBUS_TARG_MEM_RADDR, addr); 268 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
268 rmb(); 269 rmb();
269 270
270 for (offs = 0; offs < words; offs++) 271 for (offs = 0; offs < words; offs++)
271 vals[offs] = iwl_read32(bus, HBUS_TARG_MEM_RDAT); 272 vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
272 273
273 iwl_release_nic_access(bus); 274 iwl_release_nic_access(trans);
274 spin_unlock_irqrestore(&bus->reg_lock, flags); 275 spin_unlock_irqrestore(&trans->reg_lock, flags);
275} 276}
276 277
277u32 iwl_read_targ_mem(struct iwl_bus *bus, u32 addr) 278u32 iwl_read_targ_mem(struct iwl_trans *trans, u32 addr)
278{ 279{
279 u32 value; 280 u32 value;
280 281
281 _iwl_read_targ_mem_words(bus, addr, &value, 1); 282 _iwl_read_targ_mem_words(trans, addr, &value, 1);
282 283
283 return value; 284 return value;
284} 285}
285 286
286int _iwl_write_targ_mem_words(struct iwl_bus *bus, u32 addr, 287int _iwl_write_targ_mem_words(struct iwl_trans *trans, u32 addr,
287 void *buf, int words) 288 void *buf, int words)
288{ 289{
289 unsigned long flags; 290 unsigned long flags;
290 int offs, result = 0; 291 int offs, result = 0;
291 u32 *vals = buf; 292 u32 *vals = buf;
292 293
293 spin_lock_irqsave(&bus->reg_lock, flags); 294 spin_lock_irqsave(&trans->reg_lock, flags);
294 if (!iwl_grab_nic_access(bus)) { 295 if (!iwl_grab_nic_access(trans)) {
295 iwl_write32(bus, HBUS_TARG_MEM_WADDR, addr); 296 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
296 wmb(); 297 wmb();
297 298
298 for (offs = 0; offs < words; offs++) 299 for (offs = 0; offs < words; offs++)
299 iwl_write32(bus, HBUS_TARG_MEM_WDAT, vals[offs]); 300 iwl_write32(trans, HBUS_TARG_MEM_WDAT, vals[offs]);
300 iwl_release_nic_access(bus); 301 iwl_release_nic_access(trans);
301 } else 302 } else
302 result = -EBUSY; 303 result = -EBUSY;
303 spin_unlock_irqrestore(&bus->reg_lock, flags); 304 spin_unlock_irqrestore(&trans->reg_lock, flags);
304 305
305 return result; 306 return result;
306} 307}
307 308
308int iwl_write_targ_mem(struct iwl_bus *bus, u32 addr, u32 val) 309int iwl_write_targ_mem(struct iwl_trans *trans, u32 addr, u32 val)
309{ 310{
310 return _iwl_write_targ_mem_words(bus, addr, &val, 1); 311 return _iwl_write_targ_mem_words(trans, addr, &val, 1);
311} 312}
diff --git a/drivers/net/wireless/iwlwifi/iwl-io.h b/drivers/net/wireless/iwlwifi/iwl-io.h
index b8e00cd7b1f..782486fc2f8 100644
--- a/drivers/net/wireless/iwlwifi/iwl-io.h
+++ b/drivers/net/wireless/iwlwifi/iwl-io.h
@@ -31,68 +31,63 @@
31 31
32#include "iwl-devtrace.h" 32#include "iwl-devtrace.h"
33#include "iwl-shared.h" 33#include "iwl-shared.h"
34/* TODO: remove when not needed any more */
35#include "iwl-bus.h"
36#include "iwl-trans.h" 34#include "iwl-trans.h"
37 35
38static inline void iwl_write8(struct iwl_bus *bus, u32 ofs, u8 val) 36static inline void iwl_write8(struct iwl_trans *trans, u32 ofs, u8 val)
39{ 37{
40 /* TODO: get trans instead of bus */ 38 trace_iwlwifi_dev_iowrite8(priv(trans), ofs, val);
41 trace_iwlwifi_dev_iowrite8(priv(bus), ofs, val); 39 iwl_trans_write8(trans, ofs, val);
42 iwl_trans_write8(trans(bus), ofs, val);
43} 40}
44 41
45static inline void iwl_write32(struct iwl_bus *bus, u32 ofs, u32 val) 42static inline void iwl_write32(struct iwl_trans *trans, u32 ofs, u32 val)
46{ 43{
47 /* TODO: get trans instead of bus */ 44 trace_iwlwifi_dev_iowrite32(priv(trans), ofs, val);
48 trace_iwlwifi_dev_iowrite32(priv(bus), ofs, val); 45 iwl_trans_write32(trans, ofs, val);
49 iwl_trans_write32(trans(bus), ofs, val);
50} 46}
51 47
52static inline u32 iwl_read32(struct iwl_bus *bus, u32 ofs) 48static inline u32 iwl_read32(struct iwl_trans *trans, u32 ofs)
53{ 49{
54 /* TODO: get trans instead of bus */ 50 u32 val = iwl_trans_read32(trans, ofs);
55 u32 val = iwl_trans_read32(trans(bus), ofs); 51 trace_iwlwifi_dev_ioread32(priv(trans), ofs, val);
56 trace_iwlwifi_dev_ioread32(priv(bus), ofs, val);
57 return val; 52 return val;
58} 53}
59 54
60void iwl_set_bit(struct iwl_bus *bus, u32 reg, u32 mask); 55void iwl_set_bit(struct iwl_trans *trans, u32 reg, u32 mask);
61void iwl_clear_bit(struct iwl_bus *bus, u32 reg, u32 mask); 56void iwl_clear_bit(struct iwl_trans *trans, u32 reg, u32 mask);
62 57
63int iwl_poll_bit(struct iwl_bus *bus, u32 addr, 58int iwl_poll_bit(struct iwl_trans *trans, u32 addr,
64 u32 bits, u32 mask, int timeout); 59 u32 bits, u32 mask, int timeout);
65int iwl_poll_direct_bit(struct iwl_bus *bus, u32 addr, u32 mask, 60int iwl_poll_direct_bit(struct iwl_trans *trans, u32 addr, u32 mask,
66 int timeout); 61 int timeout);
67 62
68int iwl_grab_nic_access_silent(struct iwl_bus *bus); 63int iwl_grab_nic_access_silent(struct iwl_trans *trans);
69int iwl_grab_nic_access(struct iwl_bus *bus); 64int iwl_grab_nic_access(struct iwl_trans *trans);
70void iwl_release_nic_access(struct iwl_bus *bus); 65void iwl_release_nic_access(struct iwl_trans *trans);
71 66
72u32 iwl_read_direct32(struct iwl_bus *bus, u32 reg); 67u32 iwl_read_direct32(struct iwl_trans *trans, u32 reg);
73void iwl_write_direct32(struct iwl_bus *bus, u32 reg, u32 value); 68void iwl_write_direct32(struct iwl_trans *trans, u32 reg, u32 value);
74 69
75 70
76u32 iwl_read_prph(struct iwl_bus *bus, u32 reg); 71u32 iwl_read_prph(struct iwl_trans *trans, u32 reg);
77void iwl_write_prph(struct iwl_bus *bus, u32 addr, u32 val); 72void iwl_write_prph(struct iwl_trans *trans, u32 addr, u32 val);
78void iwl_set_bits_prph(struct iwl_bus *bus, u32 reg, u32 mask); 73void iwl_set_bits_prph(struct iwl_trans *trans, u32 reg, u32 mask);
79void iwl_set_bits_mask_prph(struct iwl_bus *bus, u32 reg, 74void iwl_set_bits_mask_prph(struct iwl_trans *trans, u32 reg,
80 u32 bits, u32 mask); 75 u32 bits, u32 mask);
81void iwl_clear_bits_prph(struct iwl_bus *bus, u32 reg, u32 mask); 76void iwl_clear_bits_prph(struct iwl_trans *trans, u32 reg, u32 mask);
82 77
83void _iwl_read_targ_mem_words(struct iwl_bus *bus, u32 addr, 78void _iwl_read_targ_mem_words(struct iwl_trans *trans, u32 addr,
84 void *buf, int words); 79 void *buf, int words);
85 80
86#define iwl_read_targ_mem_words(bus, addr, buf, bufsize) \ 81#define iwl_read_targ_mem_words(trans, addr, buf, bufsize) \
87 do { \ 82 do { \
88 BUILD_BUG_ON((bufsize) % sizeof(u32)); \ 83 BUILD_BUG_ON((bufsize) % sizeof(u32)); \
89 _iwl_read_targ_mem_words(bus, addr, buf, \ 84 _iwl_read_targ_mem_words(trans, addr, buf, \
90 (bufsize) / sizeof(u32));\ 85 (bufsize) / sizeof(u32));\
91 } while (0) 86 } while (0)
92 87
93int _iwl_write_targ_mem_words(struct iwl_bus *bus, u32 addr, 88int _iwl_write_targ_mem_words(struct iwl_trans *trans, u32 addr,
94 void *buf, int words); 89 void *buf, int words);
95 90
96u32 iwl_read_targ_mem(struct iwl_bus *bus, u32 addr); 91u32 iwl_read_targ_mem(struct iwl_trans *trans, u32 addr);
97int iwl_write_targ_mem(struct iwl_bus *bus, u32 addr, u32 val); 92int iwl_write_targ_mem(struct iwl_trans *trans, u32 addr, u32 val);
98#endif 93#endif
diff --git a/drivers/net/wireless/iwlwifi/iwl-led.c b/drivers/net/wireless/iwlwifi/iwl-led.c
index 8761438f153..5c7741f07aa 100644
--- a/drivers/net/wireless/iwlwifi/iwl-led.c
+++ b/drivers/net/wireless/iwlwifi/iwl-led.c
@@ -71,7 +71,7 @@ static const struct ieee80211_tpt_blink iwl_blink[] = {
71/* Set led register off */ 71/* Set led register off */
72void iwlagn_led_enable(struct iwl_priv *priv) 72void iwlagn_led_enable(struct iwl_priv *priv)
73{ 73{
74 iwl_write32(bus(priv), CSR_LED_REG, CSR_LED_REG_TRUN_ON); 74 iwl_write32(trans(priv), CSR_LED_REG, CSR_LED_REG_TRUN_ON);
75} 75}
76 76
77/* 77/*
@@ -107,9 +107,10 @@ static int iwl_send_led_cmd(struct iwl_priv *priv, struct iwl_led_cmd *led_cmd)
107 }; 107 };
108 u32 reg; 108 u32 reg;
109 109
110 reg = iwl_read32(bus(priv), CSR_LED_REG); 110 reg = iwl_read32(trans(priv), CSR_LED_REG);
111 if (reg != (reg & CSR_LED_BSM_CTRL_MSK)) 111 if (reg != (reg & CSR_LED_BSM_CTRL_MSK))
112 iwl_write32(bus(priv), CSR_LED_REG, reg & CSR_LED_BSM_CTRL_MSK); 112 iwl_write32(trans(priv), CSR_LED_REG,
113 reg & CSR_LED_BSM_CTRL_MSK);
113 114
114 return iwl_trans_send_cmd(trans(priv), &cmd); 115 return iwl_trans_send_cmd(trans(priv), &cmd);
115} 116}
@@ -206,7 +207,7 @@ void iwl_leds_init(struct iwl_priv *priv)
206 break; 207 break;
207 } 208 }
208 209
209 ret = led_classdev_register(bus(priv)->dev, &priv->led); 210 ret = led_classdev_register(trans(priv)->dev, &priv->led);
210 if (ret) { 211 if (ret) {
211 kfree(priv->led.name); 212 kfree(priv->led.name);
212 return; 213 return;
diff --git a/drivers/net/wireless/iwlwifi/iwl-mac80211.c b/drivers/net/wireless/iwlwifi/iwl-mac80211.c
index 965d0475aff..b911837b04f 100644
--- a/drivers/net/wireless/iwlwifi/iwl-mac80211.c
+++ b/drivers/net/wireless/iwlwifi/iwl-mac80211.c
@@ -196,7 +196,7 @@ int iwlagn_mac_setup_register(struct iwl_priv *priv,
196 WIPHY_FLAG_IBSS_RSN; 196 WIPHY_FLAG_IBSS_RSN;
197 197
198 if (trans(priv)->ucode_wowlan.code.len && 198 if (trans(priv)->ucode_wowlan.code.len &&
199 device_can_wakeup(bus(priv)->dev)) { 199 device_can_wakeup(trans(priv)->dev)) {
200 hw->wiphy->wowlan.flags = WIPHY_WOWLAN_MAGIC_PKT | 200 hw->wiphy->wowlan.flags = WIPHY_WOWLAN_MAGIC_PKT |
201 WIPHY_WOWLAN_DISCONNECT | 201 WIPHY_WOWLAN_DISCONNECT |
202 WIPHY_WOWLAN_EAP_IDENTITY_REQ | 202 WIPHY_WOWLAN_EAP_IDENTITY_REQ |
@@ -347,7 +347,7 @@ static void iwlagn_mac_stop(struct ieee80211_hw *hw)
347 347
348 /* User space software may expect getting rfkill changes 348 /* User space software may expect getting rfkill changes
349 * even if interface is down */ 349 * even if interface is down */
350 iwl_write32(bus(priv), CSR_INT, 0xFFFFFFFF); 350 iwl_write32(trans(priv), CSR_INT, 0xFFFFFFFF);
351 iwl_enable_rfkill_int(priv); 351 iwl_enable_rfkill_int(priv);
352 352
353 IWL_DEBUG_MAC80211(priv, "leave\n"); 353 IWL_DEBUG_MAC80211(priv, "leave\n");
@@ -405,10 +405,10 @@ static int iwlagn_mac_suspend(struct ieee80211_hw *hw,
405 if (ret) 405 if (ret)
406 goto error; 406 goto error;
407 407
408 device_set_wakeup_enable(bus(priv)->dev, true); 408 device_set_wakeup_enable(trans(priv)->dev, true);
409 409
410 /* Now let the ucode operate on its own */ 410 /* Now let the ucode operate on its own */
411 iwl_write32(bus(priv), CSR_UCODE_DRV_GP1_SET, 411 iwl_write32(trans(priv), CSR_UCODE_DRV_GP1_SET,
412 CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE); 412 CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE);
413 413
414 goto out; 414 goto out;
@@ -436,19 +436,19 @@ static int iwlagn_mac_resume(struct ieee80211_hw *hw)
436 IWL_DEBUG_MAC80211(priv, "enter\n"); 436 IWL_DEBUG_MAC80211(priv, "enter\n");
437 mutex_lock(&priv->shrd->mutex); 437 mutex_lock(&priv->shrd->mutex);
438 438
439 iwl_write32(bus(priv), CSR_UCODE_DRV_GP1_CLR, 439 iwl_write32(trans(priv), CSR_UCODE_DRV_GP1_CLR,
440 CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE); 440 CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE);
441 441
442 base = priv->shrd->device_pointers.error_event_table; 442 base = priv->shrd->device_pointers.error_event_table;
443 if (iwlagn_hw_valid_rtc_data_addr(base)) { 443 if (iwlagn_hw_valid_rtc_data_addr(base)) {
444 spin_lock_irqsave(&bus(priv)->reg_lock, flags); 444 spin_lock_irqsave(&trans(priv)->reg_lock, flags);
445 ret = iwl_grab_nic_access_silent(bus(priv)); 445 ret = iwl_grab_nic_access_silent(trans(priv));
446 if (ret == 0) { 446 if (ret == 0) {
447 iwl_write32(bus(priv), HBUS_TARG_MEM_RADDR, base); 447 iwl_write32(trans(priv), HBUS_TARG_MEM_RADDR, base);
448 status = iwl_read32(bus(priv), HBUS_TARG_MEM_RDAT); 448 status = iwl_read32(trans(priv), HBUS_TARG_MEM_RDAT);
449 iwl_release_nic_access(bus(priv)); 449 iwl_release_nic_access(trans(priv));
450 } 450 }
451 spin_unlock_irqrestore(&bus(priv)->reg_lock, flags); 451 spin_unlock_irqrestore(&trans(priv)->reg_lock, flags);
452 452
453#ifdef CONFIG_IWLWIFI_DEBUGFS 453#ifdef CONFIG_IWLWIFI_DEBUGFS
454 if (ret == 0) { 454 if (ret == 0) {
@@ -460,7 +460,8 @@ static int iwlagn_mac_resume(struct ieee80211_hw *hw)
460 460
461 if (priv->wowlan_sram) 461 if (priv->wowlan_sram)
462 _iwl_read_targ_mem_words( 462 _iwl_read_targ_mem_words(
463 bus(priv), 0x800000, priv->wowlan_sram, 463 trans(priv), 0x800000,
464 priv->wowlan_sram,
464 trans->ucode_wowlan.data.len / 4); 465 trans->ucode_wowlan.data.len / 4);
465 } 466 }
466#endif 467#endif
@@ -471,7 +472,7 @@ static int iwlagn_mac_resume(struct ieee80211_hw *hw)
471 472
472 priv->shrd->wowlan = false; 473 priv->shrd->wowlan = false;
473 474
474 device_set_wakeup_enable(bus(priv)->dev, false); 475 device_set_wakeup_enable(trans(priv)->dev, false);
475 476
476 iwlagn_prepare_restart(priv); 477 iwlagn_prepare_restart(priv);
477 478
diff --git a/drivers/net/wireless/iwlwifi/iwl-pci.c b/drivers/net/wireless/iwlwifi/iwl-pci.c
index ab462337d7a..7bab8192848 100644
--- a/drivers/net/wireless/iwlwifi/iwl-pci.c
+++ b/drivers/net/wireless/iwlwifi/iwl-pci.c
@@ -121,12 +121,12 @@ static void iwl_pci_apm_config(struct iwl_bus *bus)
121 if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) == 121 if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
122 PCI_CFG_LINK_CTRL_VAL_L1_EN) { 122 PCI_CFG_LINK_CTRL_VAL_L1_EN) {
123 /* L1-ASPM enabled; disable(!) L0S */ 123 /* L1-ASPM enabled; disable(!) L0S */
124 iwl_set_bit(bus, CSR_GIO_REG, 124 iwl_set_bit(trans(bus), CSR_GIO_REG,
125 CSR_GIO_REG_VAL_L0S_ENABLED); 125 CSR_GIO_REG_VAL_L0S_ENABLED);
126 dev_printk(KERN_INFO, bus->dev, "L1 Enabled; Disabling L0S\n"); 126 dev_printk(KERN_INFO, bus->dev, "L1 Enabled; Disabling L0S\n");
127 } else { 127 } else {
128 /* L1-ASPM disabled; enable(!) L0S */ 128 /* L1-ASPM disabled; enable(!) L0S */
129 iwl_clear_bit(bus, CSR_GIO_REG, 129 iwl_clear_bit(trans(bus), CSR_GIO_REG,
130 CSR_GIO_REG_VAL_L0S_ENABLED); 130 CSR_GIO_REG_VAL_L0S_ENABLED);
131 dev_printk(KERN_INFO, bus->dev, "L1 Disabled; Enabling L0S\n"); 131 dev_printk(KERN_INFO, bus->dev, "L1 Disabled; Enabling L0S\n");
132 } 132 }
diff --git a/drivers/net/wireless/iwlwifi/iwl-testmode.c b/drivers/net/wireless/iwlwifi/iwl-testmode.c
index a56a77b8f92..922d841faba 100644
--- a/drivers/net/wireless/iwlwifi/iwl-testmode.c
+++ b/drivers/net/wireless/iwlwifi/iwl-testmode.c
@@ -208,7 +208,7 @@ static void iwl_trace_cleanup(struct iwl_priv *priv)
208 if (priv->testmode_trace.trace_enabled) { 208 if (priv->testmode_trace.trace_enabled) {
209 if (priv->testmode_trace.cpu_addr && 209 if (priv->testmode_trace.cpu_addr &&
210 priv->testmode_trace.dma_addr) 210 priv->testmode_trace.dma_addr)
211 dma_free_coherent(bus(priv)->dev, 211 dma_free_coherent(trans(priv)->dev,
212 priv->testmode_trace.total_size, 212 priv->testmode_trace.total_size,
213 priv->testmode_trace.cpu_addr, 213 priv->testmode_trace.cpu_addr,
214 priv->testmode_trace.dma_addr); 214 priv->testmode_trace.dma_addr);
@@ -302,7 +302,7 @@ static int iwl_testmode_reg(struct ieee80211_hw *hw, struct nlattr **tb)
302 302
303 switch (nla_get_u32(tb[IWL_TM_ATTR_COMMAND])) { 303 switch (nla_get_u32(tb[IWL_TM_ATTR_COMMAND])) {
304 case IWL_TM_CMD_APP2DEV_DIRECT_REG_READ32: 304 case IWL_TM_CMD_APP2DEV_DIRECT_REG_READ32:
305 val32 = iwl_read_direct32(bus(priv), ofs); 305 val32 = iwl_read_direct32(trans(priv), ofs);
306 IWL_INFO(priv, "32bit value to read 0x%x\n", val32); 306 IWL_INFO(priv, "32bit value to read 0x%x\n", val32);
307 307
308 skb = cfg80211_testmode_alloc_reply_skb(hw->wiphy, 20); 308 skb = cfg80211_testmode_alloc_reply_skb(hw->wiphy, 20);
@@ -324,7 +324,7 @@ static int iwl_testmode_reg(struct ieee80211_hw *hw, struct nlattr **tb)
324 } else { 324 } else {
325 val32 = nla_get_u32(tb[IWL_TM_ATTR_REG_VALUE32]); 325 val32 = nla_get_u32(tb[IWL_TM_ATTR_REG_VALUE32]);
326 IWL_INFO(priv, "32bit value to write 0x%x\n", val32); 326 IWL_INFO(priv, "32bit value to write 0x%x\n", val32);
327 iwl_write_direct32(bus(priv), ofs, val32); 327 iwl_write_direct32(trans(priv), ofs, val32);
328 } 328 }
329 break; 329 break;
330 case IWL_TM_CMD_APP2DEV_DIRECT_REG_WRITE8: 330 case IWL_TM_CMD_APP2DEV_DIRECT_REG_WRITE8:
@@ -334,11 +334,11 @@ static int iwl_testmode_reg(struct ieee80211_hw *hw, struct nlattr **tb)
334 } else { 334 } else {
335 val8 = nla_get_u8(tb[IWL_TM_ATTR_REG_VALUE8]); 335 val8 = nla_get_u8(tb[IWL_TM_ATTR_REG_VALUE8]);
336 IWL_INFO(priv, "8bit value to write 0x%x\n", val8); 336 IWL_INFO(priv, "8bit value to write 0x%x\n", val8);
337 iwl_write8(bus(priv), ofs, val8); 337 iwl_write8(trans(priv), ofs, val8);
338 } 338 }
339 break; 339 break;
340 case IWL_TM_CMD_APP2DEV_INDIRECT_REG_READ32: 340 case IWL_TM_CMD_APP2DEV_INDIRECT_REG_READ32:
341 val32 = iwl_read_prph(bus(priv), ofs); 341 val32 = iwl_read_prph(trans(priv), ofs);
342 IWL_INFO(priv, "32bit value to read 0x%x\n", val32); 342 IWL_INFO(priv, "32bit value to read 0x%x\n", val32);
343 343
344 skb = cfg80211_testmode_alloc_reply_skb(hw->wiphy, 20); 344 skb = cfg80211_testmode_alloc_reply_skb(hw->wiphy, 20);
@@ -360,7 +360,7 @@ static int iwl_testmode_reg(struct ieee80211_hw *hw, struct nlattr **tb)
360 } else { 360 } else {
361 val32 = nla_get_u32(tb[IWL_TM_ATTR_REG_VALUE32]); 361 val32 = nla_get_u32(tb[IWL_TM_ATTR_REG_VALUE32]);
362 IWL_INFO(priv, "32bit value to write 0x%x\n", val32); 362 IWL_INFO(priv, "32bit value to write 0x%x\n", val32);
363 iwl_write_prph(bus(priv), ofs, val32); 363 iwl_write_prph(trans(priv), ofs, val32);
364 } 364 }
365 break; 365 break;
366 default: 366 default:
@@ -615,7 +615,7 @@ static int iwl_testmode_trace(struct ieee80211_hw *hw, struct nlattr **tb)
615 struct iwl_priv *priv = hw->priv; 615 struct iwl_priv *priv = hw->priv;
616 struct sk_buff *skb; 616 struct sk_buff *skb;
617 int status = 0; 617 int status = 0;
618 struct device *dev = bus(priv)->dev; 618 struct device *dev = trans(priv)->dev;
619 619
620 switch (nla_get_u32(tb[IWL_TM_ATTR_COMMAND])) { 620 switch (nla_get_u32(tb[IWL_TM_ATTR_COMMAND])) {
621 case IWL_TM_CMD_APP2DEV_BEGIN_TRACE: 621 case IWL_TM_CMD_APP2DEV_BEGIN_TRACE:
@@ -814,7 +814,7 @@ static int iwl_testmode_sram(struct ieee80211_hw *hw, struct nlattr **tb)
814 IWL_ERR(priv, "Error allocating memory\n"); 814 IWL_ERR(priv, "Error allocating memory\n");
815 return -ENOMEM; 815 return -ENOMEM;
816 } 816 }
817 _iwl_read_targ_mem_words(bus(priv), ofs, 817 _iwl_read_targ_mem_words(trans(priv), ofs,
818 priv->testmode_sram.buff_addr, 818 priv->testmode_sram.buff_addr,
819 priv->testmode_sram.buff_size / 4); 819 priv->testmode_sram.buff_size / 4);
820 priv->testmode_sram.num_chunks = 820 priv->testmode_sram.num_chunks =
diff --git a/drivers/net/wireless/iwlwifi/iwl-trans-pcie-int.h b/drivers/net/wireless/iwlwifi/iwl-trans-pcie-int.h
index 47d27bdf2df..555175ff4f9 100644
--- a/drivers/net/wireless/iwlwifi/iwl-trans-pcie-int.h
+++ b/drivers/net/wireless/iwlwifi/iwl-trans-pcie-int.h
@@ -317,12 +317,12 @@ static inline void iwl_disable_interrupts(struct iwl_trans *trans)
317 clear_bit(STATUS_INT_ENABLED, &trans->shrd->status); 317 clear_bit(STATUS_INT_ENABLED, &trans->shrd->status);
318 318
319 /* disable interrupts from uCode/NIC to host */ 319 /* disable interrupts from uCode/NIC to host */
320 iwl_write32(bus(trans), CSR_INT_MASK, 0x00000000); 320 iwl_write32(trans, CSR_INT_MASK, 0x00000000);
321 321
322 /* acknowledge/clear/reset any interrupts still pending 322 /* acknowledge/clear/reset any interrupts still pending
323 * from uCode or flow handler (Rx/Tx DMA) */ 323 * from uCode or flow handler (Rx/Tx DMA) */
324 iwl_write32(bus(trans), CSR_INT, 0xffffffff); 324 iwl_write32(trans, CSR_INT, 0xffffffff);
325 iwl_write32(bus(trans), CSR_FH_INT_STATUS, 0xffffffff); 325 iwl_write32(trans, CSR_FH_INT_STATUS, 0xffffffff);
326 IWL_DEBUG_ISR(trans, "Disabled interrupts\n"); 326 IWL_DEBUG_ISR(trans, "Disabled interrupts\n");
327} 327}
328 328
@@ -333,7 +333,7 @@ static inline void iwl_enable_interrupts(struct iwl_trans *trans)
333 333
334 IWL_DEBUG_ISR(trans, "Enabling interrupts\n"); 334 IWL_DEBUG_ISR(trans, "Enabling interrupts\n");
335 set_bit(STATUS_INT_ENABLED, &trans->shrd->status); 335 set_bit(STATUS_INT_ENABLED, &trans->shrd->status);
336 iwl_write32(bus(trans), CSR_INT_MASK, trans_pcie->inta_mask); 336 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
337} 337}
338 338
339/* 339/*
diff --git a/drivers/net/wireless/iwlwifi/iwl-trans-pcie-rx.c b/drivers/net/wireless/iwlwifi/iwl-trans-pcie-rx.c
index b94c95370b7..ebea2435dac 100644
--- a/drivers/net/wireless/iwlwifi/iwl-trans-pcie-rx.c
+++ b/drivers/net/wireless/iwlwifi/iwl-trans-pcie-rx.c
@@ -144,30 +144,30 @@ void iwl_rx_queue_update_write_ptr(struct iwl_trans *trans,
144 /* shadow register enabled */ 144 /* shadow register enabled */
145 /* Device expects a multiple of 8 */ 145 /* Device expects a multiple of 8 */
146 q->write_actual = (q->write & ~0x7); 146 q->write_actual = (q->write & ~0x7);
147 iwl_write32(bus(trans), FH_RSCSR_CHNL0_WPTR, q->write_actual); 147 iwl_write32(trans, FH_RSCSR_CHNL0_WPTR, q->write_actual);
148 } else { 148 } else {
149 /* If power-saving is in use, make sure device is awake */ 149 /* If power-saving is in use, make sure device is awake */
150 if (test_bit(STATUS_POWER_PMI, &trans->shrd->status)) { 150 if (test_bit(STATUS_POWER_PMI, &trans->shrd->status)) {
151 reg = iwl_read32(bus(trans), CSR_UCODE_DRV_GP1); 151 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
152 152
153 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { 153 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
154 IWL_DEBUG_INFO(trans, 154 IWL_DEBUG_INFO(trans,
155 "Rx queue requesting wakeup," 155 "Rx queue requesting wakeup,"
156 " GP1 = 0x%x\n", reg); 156 " GP1 = 0x%x\n", reg);
157 iwl_set_bit(bus(trans), CSR_GP_CNTRL, 157 iwl_set_bit(trans, CSR_GP_CNTRL,
158 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 158 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
159 goto exit_unlock; 159 goto exit_unlock;
160 } 160 }
161 161
162 q->write_actual = (q->write & ~0x7); 162 q->write_actual = (q->write & ~0x7);
163 iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_WPTR, 163 iwl_write_direct32(trans, FH_RSCSR_CHNL0_WPTR,
164 q->write_actual); 164 q->write_actual);
165 165
166 /* Else device is assumed to be awake */ 166 /* Else device is assumed to be awake */
167 } else { 167 } else {
168 /* Device expects a multiple of 8 */ 168 /* Device expects a multiple of 8 */
169 q->write_actual = (q->write & ~0x7); 169 q->write_actual = (q->write & ~0x7);
170 iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_WPTR, 170 iwl_write_direct32(trans, FH_RSCSR_CHNL0_WPTR,
171 q->write_actual); 171 q->write_actual);
172 } 172 }
173 } 173 }
@@ -312,7 +312,7 @@ static void iwlagn_rx_allocate(struct iwl_trans *trans, gfp_t priority)
312 BUG_ON(rxb->page); 312 BUG_ON(rxb->page);
313 rxb->page = page; 313 rxb->page = page;
314 /* Get physical address of the RB */ 314 /* Get physical address of the RB */
315 rxb->page_dma = dma_map_page(bus(trans)->dev, page, 0, 315 rxb->page_dma = dma_map_page(trans->dev, page, 0,
316 PAGE_SIZE << hw_params(trans).rx_page_order, 316 PAGE_SIZE << hw_params(trans).rx_page_order,
317 DMA_FROM_DEVICE); 317 DMA_FROM_DEVICE);
318 /* dma address must be no more than 36 bits */ 318 /* dma address must be no more than 36 bits */
@@ -418,7 +418,7 @@ static void iwl_rx_handle(struct iwl_trans *trans)
418 418
419 rxq->queue[i] = NULL; 419 rxq->queue[i] = NULL;
420 420
421 dma_unmap_page(bus(trans)->dev, rxb->page_dma, 421 dma_unmap_page(trans->dev, rxb->page_dma,
422 PAGE_SIZE << hw_params(trans).rx_page_order, 422 PAGE_SIZE << hw_params(trans).rx_page_order,
423 DMA_FROM_DEVICE); 423 DMA_FROM_DEVICE);
424 pkt = rxb_addr(rxb); 424 pkt = rxb_addr(rxb);
@@ -489,7 +489,7 @@ static void iwl_rx_handle(struct iwl_trans *trans)
489 * rx_free list for reuse later. */ 489 * rx_free list for reuse later. */
490 spin_lock_irqsave(&rxq->lock, flags); 490 spin_lock_irqsave(&rxq->lock, flags);
491 if (rxb->page != NULL) { 491 if (rxb->page != NULL) {
492 rxb->page_dma = dma_map_page(bus(trans)->dev, rxb->page, 492 rxb->page_dma = dma_map_page(trans->dev, rxb->page,
493 0, PAGE_SIZE << 493 0, PAGE_SIZE <<
494 hw_params(trans).rx_page_order, 494 hw_params(trans).rx_page_order,
495 DMA_FROM_DEVICE); 495 DMA_FROM_DEVICE);
@@ -616,7 +616,7 @@ static void iwl_dump_nic_error_log(struct iwl_trans *trans)
616 return; 616 return;
617 } 617 }
618 618
619 iwl_read_targ_mem_words(bus(priv), base, &table, sizeof(table)); 619 iwl_read_targ_mem_words(trans(priv), base, &table, sizeof(table));
620 620
621 if (ERROR_START_OFFSET <= table.valid * ERROR_ELEM_SIZE) { 621 if (ERROR_START_OFFSET <= table.valid * ERROR_ELEM_SIZE) {
622 IWL_ERR(trans, "Start IWL Error Log Dump:\n"); 622 IWL_ERR(trans, "Start IWL Error Log Dump:\n");
@@ -677,9 +677,9 @@ static void iwl_irq_handle_error(struct iwl_trans *trans)
677 struct iwl_priv *priv = priv(trans); 677 struct iwl_priv *priv = priv(trans);
678 /* W/A for WiFi/WiMAX coex and WiMAX own the RF */ 678 /* W/A for WiFi/WiMAX coex and WiMAX own the RF */
679 if (cfg(priv)->internal_wimax_coex && 679 if (cfg(priv)->internal_wimax_coex &&
680 (!(iwl_read_prph(bus(trans), APMG_CLK_CTRL_REG) & 680 (!(iwl_read_prph(trans, APMG_CLK_CTRL_REG) &
681 APMS_CLK_VAL_MRB_FUNC_MODE) || 681 APMS_CLK_VAL_MRB_FUNC_MODE) ||
682 (iwl_read_prph(bus(trans), APMG_PS_CTRL_REG) & 682 (iwl_read_prph(trans, APMG_PS_CTRL_REG) &
683 APMG_PS_CTRL_VAL_RESET_REQ))) { 683 APMG_PS_CTRL_VAL_RESET_REQ))) {
684 /* 684 /*
685 * Keep the restart process from trying to send host 685 * Keep the restart process from trying to send host
@@ -745,18 +745,18 @@ static int iwl_print_event_log(struct iwl_trans *trans, u32 start_idx,
745 ptr = base + EVENT_START_OFFSET + (start_idx * event_size); 745 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
746 746
747 /* Make sure device is powered up for SRAM reads */ 747 /* Make sure device is powered up for SRAM reads */
748 spin_lock_irqsave(&bus(trans)->reg_lock, reg_flags); 748 spin_lock_irqsave(&trans->reg_lock, reg_flags);
749 iwl_grab_nic_access(bus(trans)); 749 iwl_grab_nic_access(trans);
750 750
751 /* Set starting address; reads will auto-increment */ 751 /* Set starting address; reads will auto-increment */
752 iwl_write32(bus(trans), HBUS_TARG_MEM_RADDR, ptr); 752 iwl_write32(trans, HBUS_TARG_MEM_RADDR, ptr);
753 rmb(); 753 rmb();
754 754
755 /* "time" is actually "data" for mode 0 (no timestamp). 755 /* "time" is actually "data" for mode 0 (no timestamp).
756 * place event id # at far right for easier visual parsing. */ 756 * place event id # at far right for easier visual parsing. */
757 for (i = 0; i < num_events; i++) { 757 for (i = 0; i < num_events; i++) {
758 ev = iwl_read32(bus(trans), HBUS_TARG_MEM_RDAT); 758 ev = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
759 time = iwl_read32(bus(trans), HBUS_TARG_MEM_RDAT); 759 time = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
760 if (mode == 0) { 760 if (mode == 0) {
761 /* data, ev */ 761 /* data, ev */
762 if (bufsz) { 762 if (bufsz) {
@@ -770,7 +770,7 @@ static int iwl_print_event_log(struct iwl_trans *trans, u32 start_idx,
770 time, ev); 770 time, ev);
771 } 771 }
772 } else { 772 } else {
773 data = iwl_read32(bus(trans), HBUS_TARG_MEM_RDAT); 773 data = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
774 if (bufsz) { 774 if (bufsz) {
775 pos += scnprintf(*buf + pos, bufsz - pos, 775 pos += scnprintf(*buf + pos, bufsz - pos,
776 "EVT_LOGT:%010u:0x%08x:%04u\n", 776 "EVT_LOGT:%010u:0x%08x:%04u\n",
@@ -785,8 +785,8 @@ static int iwl_print_event_log(struct iwl_trans *trans, u32 start_idx,
785 } 785 }
786 786
787 /* Allow device to power down */ 787 /* Allow device to power down */
788 iwl_release_nic_access(bus(trans)); 788 iwl_release_nic_access(trans);
789 spin_unlock_irqrestore(&bus(trans)->reg_lock, reg_flags); 789 spin_unlock_irqrestore(&trans->reg_lock, reg_flags);
790 return pos; 790 return pos;
791} 791}
792 792
@@ -863,10 +863,10 @@ int iwl_dump_nic_event_log(struct iwl_trans *trans, bool full_log,
863 } 863 }
864 864
865 /* event log header */ 865 /* event log header */
866 capacity = iwl_read_targ_mem(bus(trans), base); 866 capacity = iwl_read_targ_mem(trans, base);
867 mode = iwl_read_targ_mem(bus(trans), base + (1 * sizeof(u32))); 867 mode = iwl_read_targ_mem(trans, base + (1 * sizeof(u32)));
868 num_wraps = iwl_read_targ_mem(bus(trans), base + (2 * sizeof(u32))); 868 num_wraps = iwl_read_targ_mem(trans, base + (2 * sizeof(u32)));
869 next_entry = iwl_read_targ_mem(bus(trans), base + (3 * sizeof(u32))); 869 next_entry = iwl_read_targ_mem(trans, base + (3 * sizeof(u32)));
870 870
871 if (capacity > logsize) { 871 if (capacity > logsize) {
872 IWL_ERR(trans, "Log capacity %d is bogus, limit to %d " 872 IWL_ERR(trans, "Log capacity %d is bogus, limit to %d "
@@ -962,7 +962,7 @@ void iwl_irq_tasklet(struct iwl_trans *trans)
962 * hardware bugs here by ACKing all the possible interrupts so that 962 * hardware bugs here by ACKing all the possible interrupts so that
963 * interrupt coalescing can still be achieved. 963 * interrupt coalescing can still be achieved.
964 */ 964 */
965 iwl_write32(bus(trans), CSR_INT, 965 iwl_write32(trans, CSR_INT,
966 trans_pcie->inta | ~trans_pcie->inta_mask); 966 trans_pcie->inta | ~trans_pcie->inta_mask);
967 967
968 inta = trans_pcie->inta; 968 inta = trans_pcie->inta;
@@ -970,7 +970,7 @@ void iwl_irq_tasklet(struct iwl_trans *trans)
970#ifdef CONFIG_IWLWIFI_DEBUG 970#ifdef CONFIG_IWLWIFI_DEBUG
971 if (iwl_get_debug_level(trans->shrd) & IWL_DL_ISR) { 971 if (iwl_get_debug_level(trans->shrd) & IWL_DL_ISR) {
972 /* just for debug */ 972 /* just for debug */
973 inta_mask = iwl_read32(bus(trans), CSR_INT_MASK); 973 inta_mask = iwl_read32(trans, CSR_INT_MASK);
974 IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n ", 974 IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n ",
975 inta, inta_mask); 975 inta, inta_mask);
976 } 976 }
@@ -1018,7 +1018,7 @@ void iwl_irq_tasklet(struct iwl_trans *trans)
1018 /* HW RF KILL switch toggled */ 1018 /* HW RF KILL switch toggled */
1019 if (inta & CSR_INT_BIT_RF_KILL) { 1019 if (inta & CSR_INT_BIT_RF_KILL) {
1020 int hw_rf_kill = 0; 1020 int hw_rf_kill = 0;
1021 if (!(iwl_read32(bus(trans), CSR_GP_CNTRL) & 1021 if (!(iwl_read32(trans, CSR_GP_CNTRL) &
1022 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)) 1022 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1023 hw_rf_kill = 1; 1023 hw_rf_kill = 1;
1024 1024
@@ -1082,12 +1082,12 @@ void iwl_irq_tasklet(struct iwl_trans *trans)
1082 IWL_DEBUG_ISR(trans, "Rx interrupt\n"); 1082 IWL_DEBUG_ISR(trans, "Rx interrupt\n");
1083 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { 1083 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1084 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); 1084 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1085 iwl_write32(bus(trans), CSR_FH_INT_STATUS, 1085 iwl_write32(trans, CSR_FH_INT_STATUS,
1086 CSR_FH_INT_RX_MASK); 1086 CSR_FH_INT_RX_MASK);
1087 } 1087 }
1088 if (inta & CSR_INT_BIT_RX_PERIODIC) { 1088 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1089 handled |= CSR_INT_BIT_RX_PERIODIC; 1089 handled |= CSR_INT_BIT_RX_PERIODIC;
1090 iwl_write32(bus(trans), 1090 iwl_write32(trans,
1091 CSR_INT, CSR_INT_BIT_RX_PERIODIC); 1091 CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1092 } 1092 }
1093 /* Sending RX interrupt require many steps to be done in the 1093 /* Sending RX interrupt require many steps to be done in the
@@ -1102,7 +1102,7 @@ void iwl_irq_tasklet(struct iwl_trans *trans)
1102 */ 1102 */
1103 1103
1104 /* Disable periodic interrupt; we use it as just a one-shot. */ 1104 /* Disable periodic interrupt; we use it as just a one-shot. */
1105 iwl_write8(bus(trans), CSR_INT_PERIODIC_REG, 1105 iwl_write8(trans, CSR_INT_PERIODIC_REG,
1106 CSR_INT_PERIODIC_DIS); 1106 CSR_INT_PERIODIC_DIS);
1107#ifdef CONFIG_IWLWIFI_IDI 1107#ifdef CONFIG_IWLWIFI_IDI
1108 iwl_amfh_rx_handler(); 1108 iwl_amfh_rx_handler();
@@ -1117,7 +1117,7 @@ void iwl_irq_tasklet(struct iwl_trans *trans)
1117 * to extend the periodic interrupt; one-shot is enough. 1117 * to extend the periodic interrupt; one-shot is enough.
1118 */ 1118 */
1119 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) 1119 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1120 iwl_write8(bus(trans), CSR_INT_PERIODIC_REG, 1120 iwl_write8(trans, CSR_INT_PERIODIC_REG,
1121 CSR_INT_PERIODIC_ENA); 1121 CSR_INT_PERIODIC_ENA);
1122 1122
1123 isr_stats->rx++; 1123 isr_stats->rx++;
@@ -1125,7 +1125,7 @@ void iwl_irq_tasklet(struct iwl_trans *trans)
1125 1125
1126 /* This "Tx" DMA channel is used only for loading uCode */ 1126 /* This "Tx" DMA channel is used only for loading uCode */
1127 if (inta & CSR_INT_BIT_FH_TX) { 1127 if (inta & CSR_INT_BIT_FH_TX) {
1128 iwl_write32(bus(trans), CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK); 1128 iwl_write32(trans, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
1129 IWL_DEBUG_ISR(trans, "uCode load interrupt\n"); 1129 IWL_DEBUG_ISR(trans, "uCode load interrupt\n");
1130 isr_stats->tx++; 1130 isr_stats->tx++;
1131 handled |= CSR_INT_BIT_FH_TX; 1131 handled |= CSR_INT_BIT_FH_TX;
@@ -1175,7 +1175,7 @@ void iwl_free_isr_ict(struct iwl_trans *trans)
1175 IWL_TRANS_GET_PCIE_TRANS(trans); 1175 IWL_TRANS_GET_PCIE_TRANS(trans);
1176 1176
1177 if (trans_pcie->ict_tbl) { 1177 if (trans_pcie->ict_tbl) {
1178 dma_free_coherent(bus(trans)->dev, ICT_SIZE, 1178 dma_free_coherent(trans->dev, ICT_SIZE,
1179 trans_pcie->ict_tbl, 1179 trans_pcie->ict_tbl,
1180 trans_pcie->ict_tbl_dma); 1180 trans_pcie->ict_tbl_dma);
1181 trans_pcie->ict_tbl = NULL; 1181 trans_pcie->ict_tbl = NULL;
@@ -1195,7 +1195,7 @@ int iwl_alloc_isr_ict(struct iwl_trans *trans)
1195 IWL_TRANS_GET_PCIE_TRANS(trans); 1195 IWL_TRANS_GET_PCIE_TRANS(trans);
1196 1196
1197 trans_pcie->ict_tbl = 1197 trans_pcie->ict_tbl =
1198 dma_alloc_coherent(bus(trans)->dev, ICT_SIZE, 1198 dma_alloc_coherent(trans->dev, ICT_SIZE,
1199 &trans_pcie->ict_tbl_dma, 1199 &trans_pcie->ict_tbl_dma,
1200 GFP_KERNEL); 1200 GFP_KERNEL);
1201 if (!trans_pcie->ict_tbl) 1201 if (!trans_pcie->ict_tbl)
@@ -1246,10 +1246,10 @@ void iwl_reset_ict(struct iwl_trans *trans)
1246 1246
1247 IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%x\n", val); 1247 IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%x\n", val);
1248 1248
1249 iwl_write32(bus(trans), CSR_DRAM_INT_TBL_REG, val); 1249 iwl_write32(trans, CSR_DRAM_INT_TBL_REG, val);
1250 trans_pcie->use_ict = true; 1250 trans_pcie->use_ict = true;
1251 trans_pcie->ict_index = 0; 1251 trans_pcie->ict_index = 0;
1252 iwl_write32(bus(trans), CSR_INT, trans_pcie->inta_mask); 1252 iwl_write32(trans, CSR_INT, trans_pcie->inta_mask);
1253 iwl_enable_interrupts(trans); 1253 iwl_enable_interrupts(trans);
1254 spin_unlock_irqrestore(&trans->shrd->lock, flags); 1254 spin_unlock_irqrestore(&trans->shrd->lock, flags);
1255} 1255}
@@ -1289,11 +1289,11 @@ static irqreturn_t iwl_isr(int irq, void *data)
1289 * back-to-back ISRs and sporadic interrupts from our NIC. 1289 * back-to-back ISRs and sporadic interrupts from our NIC.
1290 * If we have something to service, the tasklet will re-enable ints. 1290 * If we have something to service, the tasklet will re-enable ints.
1291 * If we *don't* have something, we'll re-enable before leaving here. */ 1291 * If we *don't* have something, we'll re-enable before leaving here. */
1292 inta_mask = iwl_read32(bus(trans), CSR_INT_MASK); /* just for debug */ 1292 inta_mask = iwl_read32(trans, CSR_INT_MASK); /* just for debug */
1293 iwl_write32(bus(trans), CSR_INT_MASK, 0x00000000); 1293 iwl_write32(trans, CSR_INT_MASK, 0x00000000);
1294 1294
1295 /* Discover which interrupts are active/pending */ 1295 /* Discover which interrupts are active/pending */
1296 inta = iwl_read32(bus(trans), CSR_INT); 1296 inta = iwl_read32(trans, CSR_INT);
1297 1297
1298 /* Ignore interrupt if there's nothing in NIC to service. 1298 /* Ignore interrupt if there's nothing in NIC to service.
1299 * This may be due to IRQ shared with another device, 1299 * This may be due to IRQ shared with another device,
@@ -1312,7 +1312,7 @@ static irqreturn_t iwl_isr(int irq, void *data)
1312 1312
1313#ifdef CONFIG_IWLWIFI_DEBUG 1313#ifdef CONFIG_IWLWIFI_DEBUG
1314 if (iwl_get_debug_level(trans->shrd) & (IWL_DL_ISR)) { 1314 if (iwl_get_debug_level(trans->shrd) & (IWL_DL_ISR)) {
1315 inta_fh = iwl_read32(bus(trans), CSR_FH_INT_STATUS); 1315 inta_fh = iwl_read32(trans, CSR_FH_INT_STATUS);
1316 IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled 0x%08x, " 1316 IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled 0x%08x, "
1317 "fh 0x%08x\n", inta, inta_mask, inta_fh); 1317 "fh 0x%08x\n", inta, inta_mask, inta_fh);
1318 } 1318 }
@@ -1378,8 +1378,8 @@ irqreturn_t iwl_isr_ict(int irq, void *data)
1378 * If we have something to service, the tasklet will re-enable ints. 1378 * If we have something to service, the tasklet will re-enable ints.
1379 * If we *don't* have something, we'll re-enable before leaving here. 1379 * If we *don't* have something, we'll re-enable before leaving here.
1380 */ 1380 */
1381 inta_mask = iwl_read32(bus(trans), CSR_INT_MASK); /* just for debug */ 1381 inta_mask = iwl_read32(trans, CSR_INT_MASK); /* just for debug */
1382 iwl_write32(bus(trans), CSR_INT_MASK, 0x00000000); 1382 iwl_write32(trans, CSR_INT_MASK, 0x00000000);
1383 1383
1384 1384
1385 /* Ignore interrupt if there's nothing in NIC to service. 1385 /* Ignore interrupt if there's nothing in NIC to service.
diff --git a/drivers/net/wireless/iwlwifi/iwl-trans-pcie-tx.c b/drivers/net/wireless/iwlwifi/iwl-trans-pcie-tx.c
index 30814b55705..5e095ac5076 100644
--- a/drivers/net/wireless/iwlwifi/iwl-trans-pcie-tx.c
+++ b/drivers/net/wireless/iwlwifi/iwl-trans-pcie-tx.c
@@ -100,7 +100,7 @@ void iwl_txq_update_write_ptr(struct iwl_trans *trans, struct iwl_tx_queue *txq)
100 100
101 if (hw_params(trans).shadow_reg_enable) { 101 if (hw_params(trans).shadow_reg_enable) {
102 /* shadow register enabled */ 102 /* shadow register enabled */
103 iwl_write32(bus(trans), HBUS_TARG_WRPTR, 103 iwl_write32(trans, HBUS_TARG_WRPTR,
104 txq->q.write_ptr | (txq_id << 8)); 104 txq->q.write_ptr | (txq_id << 8));
105 } else { 105 } else {
106 /* if we're trying to save power */ 106 /* if we're trying to save power */
@@ -108,18 +108,18 @@ void iwl_txq_update_write_ptr(struct iwl_trans *trans, struct iwl_tx_queue *txq)
108 /* wake up nic if it's powered down ... 108 /* wake up nic if it's powered down ...
109 * uCode will wake up, and interrupt us again, so next 109 * uCode will wake up, and interrupt us again, so next
110 * time we'll skip this part. */ 110 * time we'll skip this part. */
111 reg = iwl_read32(bus(trans), CSR_UCODE_DRV_GP1); 111 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
112 112
113 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { 113 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
114 IWL_DEBUG_INFO(trans, 114 IWL_DEBUG_INFO(trans,
115 "Tx queue %d requesting wakeup," 115 "Tx queue %d requesting wakeup,"
116 " GP1 = 0x%x\n", txq_id, reg); 116 " GP1 = 0x%x\n", txq_id, reg);
117 iwl_set_bit(bus(trans), CSR_GP_CNTRL, 117 iwl_set_bit(trans, CSR_GP_CNTRL,
118 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 118 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
119 return; 119 return;
120 } 120 }
121 121
122 iwl_write_direct32(bus(trans), HBUS_TARG_WRPTR, 122 iwl_write_direct32(trans, HBUS_TARG_WRPTR,
123 txq->q.write_ptr | (txq_id << 8)); 123 txq->q.write_ptr | (txq_id << 8));
124 124
125 /* 125 /*
@@ -128,7 +128,7 @@ void iwl_txq_update_write_ptr(struct iwl_trans *trans, struct iwl_tx_queue *txq)
128 * trying to tx (during RFKILL, we're not trying to tx). 128 * trying to tx (during RFKILL, we're not trying to tx).
129 */ 129 */
130 } else 130 } else
131 iwl_write32(bus(trans), HBUS_TARG_WRPTR, 131 iwl_write32(trans, HBUS_TARG_WRPTR,
132 txq->q.write_ptr | (txq_id << 8)); 132 txq->q.write_ptr | (txq_id << 8));
133 } 133 }
134 txq->need_update = 0; 134 txq->need_update = 0;
@@ -190,14 +190,14 @@ static void iwlagn_unmap_tfd(struct iwl_trans *trans, struct iwl_cmd_meta *meta,
190 190
191 /* Unmap tx_cmd */ 191 /* Unmap tx_cmd */
192 if (num_tbs) 192 if (num_tbs)
193 dma_unmap_single(bus(trans)->dev, 193 dma_unmap_single(trans->dev,
194 dma_unmap_addr(meta, mapping), 194 dma_unmap_addr(meta, mapping),
195 dma_unmap_len(meta, len), 195 dma_unmap_len(meta, len),
196 DMA_BIDIRECTIONAL); 196 DMA_BIDIRECTIONAL);
197 197
198 /* Unmap chunks, if any. */ 198 /* Unmap chunks, if any. */
199 for (i = 1; i < num_tbs; i++) 199 for (i = 1; i < num_tbs; i++)
200 dma_unmap_single(bus(trans)->dev, iwl_tfd_tb_get_addr(tfd, i), 200 dma_unmap_single(trans->dev, iwl_tfd_tb_get_addr(tfd, i),
201 iwl_tfd_tb_get_len(tfd, i), dma_dir); 201 iwl_tfd_tb_get_len(tfd, i), dma_dir);
202} 202}
203 203
@@ -383,14 +383,14 @@ static int iwlagn_tx_queue_set_q2ratid(struct iwl_trans *trans, u16 ra_tid,
383 tbl_dw_addr = trans_pcie->scd_base_addr + 383 tbl_dw_addr = trans_pcie->scd_base_addr +
384 SCD_TRANS_TBL_OFFSET_QUEUE(txq_id); 384 SCD_TRANS_TBL_OFFSET_QUEUE(txq_id);
385 385
386 tbl_dw = iwl_read_targ_mem(bus(trans), tbl_dw_addr); 386 tbl_dw = iwl_read_targ_mem(trans, tbl_dw_addr);
387 387
388 if (txq_id & 0x1) 388 if (txq_id & 0x1)
389 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF); 389 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
390 else 390 else
391 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000); 391 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
392 392
393 iwl_write_targ_mem(bus(trans), tbl_dw_addr, tbl_dw); 393 iwl_write_targ_mem(trans, tbl_dw_addr, tbl_dw);
394 394
395 return 0; 395 return 0;
396} 396}
@@ -399,7 +399,7 @@ static void iwlagn_tx_queue_stop_scheduler(struct iwl_trans *trans, u16 txq_id)
399{ 399{
400 /* Simply stop the queue, but don't change any configuration; 400 /* Simply stop the queue, but don't change any configuration;
401 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */ 401 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
402 iwl_write_prph(bus(trans), 402 iwl_write_prph(trans,
403 SCD_QUEUE_STATUS_BITS(txq_id), 403 SCD_QUEUE_STATUS_BITS(txq_id),
404 (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)| 404 (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)|
405 (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN)); 405 (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
@@ -409,9 +409,9 @@ void iwl_trans_set_wr_ptrs(struct iwl_trans *trans,
409 int txq_id, u32 index) 409 int txq_id, u32 index)
410{ 410{
411 IWL_DEBUG_TX_QUEUES(trans, "Q %d WrPtr: %d", txq_id, index & 0xff); 411 IWL_DEBUG_TX_QUEUES(trans, "Q %d WrPtr: %d", txq_id, index & 0xff);
412 iwl_write_direct32(bus(trans), HBUS_TARG_WRPTR, 412 iwl_write_direct32(trans, HBUS_TARG_WRPTR,
413 (index & 0xff) | (txq_id << 8)); 413 (index & 0xff) | (txq_id << 8));
414 iwl_write_prph(bus(trans), SCD_QUEUE_RDPTR(txq_id), index); 414 iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), index);
415} 415}
416 416
417void iwl_trans_tx_queue_set_status(struct iwl_trans *trans, 417void iwl_trans_tx_queue_set_status(struct iwl_trans *trans,
@@ -423,7 +423,7 @@ void iwl_trans_tx_queue_set_status(struct iwl_trans *trans,
423 int active = 423 int active =
424 test_bit(txq_id, &trans_pcie->txq_ctx_active_msk) ? 1 : 0; 424 test_bit(txq_id, &trans_pcie->txq_ctx_active_msk) ? 1 : 0;
425 425
426 iwl_write_prph(bus(trans), SCD_QUEUE_STATUS_BITS(txq_id), 426 iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id),
427 (active << SCD_QUEUE_STTS_REG_POS_ACTIVE) | 427 (active << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
428 (tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) | 428 (tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) |
429 (1 << SCD_QUEUE_STTS_REG_POS_WSL) | 429 (1 << SCD_QUEUE_STTS_REG_POS_WSL) |
@@ -498,10 +498,10 @@ void iwl_trans_pcie_tx_agg_setup(struct iwl_trans *trans,
498 iwlagn_tx_queue_set_q2ratid(trans, ra_tid, txq_id); 498 iwlagn_tx_queue_set_q2ratid(trans, ra_tid, txq_id);
499 499
500 /* Set this queue as a chain-building queue */ 500 /* Set this queue as a chain-building queue */
501 iwl_set_bits_prph(bus(trans), SCD_QUEUECHAIN_SEL, (1<<txq_id)); 501 iwl_set_bits_prph(trans, SCD_QUEUECHAIN_SEL, (1<<txq_id));
502 502
503 /* enable aggregations for the queue */ 503 /* enable aggregations for the queue */
504 iwl_set_bits_prph(bus(trans), SCD_AGGR_SEL, (1<<txq_id)); 504 iwl_set_bits_prph(trans, SCD_AGGR_SEL, (1<<txq_id));
505 505
506 /* Place first TFD at index corresponding to start sequence number. 506 /* Place first TFD at index corresponding to start sequence number.
507 * Assumes that ssn_idx is valid (!= 0xFFF) */ 507 * Assumes that ssn_idx is valid (!= 0xFFF) */
@@ -510,7 +510,7 @@ void iwl_trans_pcie_tx_agg_setup(struct iwl_trans *trans,
510 iwl_trans_set_wr_ptrs(trans, txq_id, ssn); 510 iwl_trans_set_wr_ptrs(trans, txq_id, ssn);
511 511
512 /* Set up Tx window size and frame limit for this queue */ 512 /* Set up Tx window size and frame limit for this queue */
513 iwl_write_targ_mem(bus(trans), trans_pcie->scd_base_addr + 513 iwl_write_targ_mem(trans, trans_pcie->scd_base_addr +
514 SCD_CONTEXT_QUEUE_OFFSET(txq_id) + 514 SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
515 sizeof(u32), 515 sizeof(u32),
516 ((frame_limit << 516 ((frame_limit <<
@@ -520,7 +520,7 @@ void iwl_trans_pcie_tx_agg_setup(struct iwl_trans *trans,
520 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & 520 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
521 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); 521 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
522 522
523 iwl_set_bits_prph(bus(trans), SCD_INTERRUPT_MASK, (1 << txq_id)); 523 iwl_set_bits_prph(trans, SCD_INTERRUPT_MASK, (1 << txq_id));
524 524
525 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */ 525 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
526 iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[txq_id], 526 iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[txq_id],
@@ -584,7 +584,7 @@ int iwl_trans_pcie_tx_agg_disable(struct iwl_trans *trans, int sta_id, int tid)
584 584
585 iwlagn_tx_queue_stop_scheduler(trans, txq_id); 585 iwlagn_tx_queue_stop_scheduler(trans, txq_id);
586 586
587 iwl_clear_bits_prph(bus(trans), SCD_AGGR_SEL, (1 << txq_id)); 587 iwl_clear_bits_prph(trans, SCD_AGGR_SEL, (1 << txq_id));
588 588
589 trans_pcie->agg_txq[sta_id][tid] = 0; 589 trans_pcie->agg_txq[sta_id][tid] = 0;
590 trans_pcie->txq[txq_id].q.read_ptr = 0; 590 trans_pcie->txq[txq_id].q.read_ptr = 0;
@@ -592,7 +592,7 @@ int iwl_trans_pcie_tx_agg_disable(struct iwl_trans *trans, int sta_id, int tid)
592 /* supposes that ssn_idx is valid (!= 0xFFF) */ 592 /* supposes that ssn_idx is valid (!= 0xFFF) */
593 iwl_trans_set_wr_ptrs(trans, txq_id, 0); 593 iwl_trans_set_wr_ptrs(trans, txq_id, 0);
594 594
595 iwl_clear_bits_prph(bus(trans), SCD_INTERRUPT_MASK, (1 << txq_id)); 595 iwl_clear_bits_prph(trans, SCD_INTERRUPT_MASK, (1 << txq_id));
596 iwl_txq_ctx_deactivate(trans_pcie, txq_id); 596 iwl_txq_ctx_deactivate(trans_pcie, txq_id);
597 iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[txq_id], 0, 0); 597 iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[txq_id], 0, 0);
598 return 0; 598 return 0;
@@ -725,9 +725,9 @@ static int iwl_enqueue_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
725 le16_to_cpu(out_cmd->hdr.sequence), cmd_size, 725 le16_to_cpu(out_cmd->hdr.sequence), cmd_size,
726 q->write_ptr, idx, trans->shrd->cmd_queue); 726 q->write_ptr, idx, trans->shrd->cmd_queue);
727 727
728 phys_addr = dma_map_single(bus(trans)->dev, &out_cmd->hdr, copy_size, 728 phys_addr = dma_map_single(trans->dev, &out_cmd->hdr, copy_size,
729 DMA_BIDIRECTIONAL); 729 DMA_BIDIRECTIONAL);
730 if (unlikely(dma_mapping_error(bus(trans)->dev, phys_addr))) { 730 if (unlikely(dma_mapping_error(trans->dev, phys_addr))) {
731 idx = -ENOMEM; 731 idx = -ENOMEM;
732 goto out; 732 goto out;
733 } 733 }
@@ -748,10 +748,10 @@ static int iwl_enqueue_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
748 continue; 748 continue;
749 if (!(cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY)) 749 if (!(cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY))
750 continue; 750 continue;
751 phys_addr = dma_map_single(bus(trans)->dev, 751 phys_addr = dma_map_single(trans->dev,
752 (void *)cmd->data[i], 752 (void *)cmd->data[i],
753 cmd->len[i], DMA_BIDIRECTIONAL); 753 cmd->len[i], DMA_BIDIRECTIONAL);
754 if (dma_mapping_error(bus(trans)->dev, phys_addr)) { 754 if (dma_mapping_error(trans->dev, phys_addr)) {
755 iwlagn_unmap_tfd(trans, out_meta, 755 iwlagn_unmap_tfd(trans, out_meta,
756 &txq->tfds[q->write_ptr], 756 &txq->tfds[q->write_ptr],
757 DMA_BIDIRECTIONAL); 757 DMA_BIDIRECTIONAL);
diff --git a/drivers/net/wireless/iwlwifi/iwl-trans-pcie.c b/drivers/net/wireless/iwlwifi/iwl-trans-pcie.c
index 80f531844f3..a1ee2e4b0ce 100644
--- a/drivers/net/wireless/iwlwifi/iwl-trans-pcie.c
+++ b/drivers/net/wireless/iwlwifi/iwl-trans-pcie.c
@@ -80,7 +80,7 @@ static int iwl_trans_rx_alloc(struct iwl_trans *trans)
80 struct iwl_trans_pcie *trans_pcie = 80 struct iwl_trans_pcie *trans_pcie =
81 IWL_TRANS_GET_PCIE_TRANS(trans); 81 IWL_TRANS_GET_PCIE_TRANS(trans);
82 struct iwl_rx_queue *rxq = &trans_pcie->rxq; 82 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
83 struct device *dev = bus(trans)->dev; 83 struct device *dev = trans->dev;
84 84
85 memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq)); 85 memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq));
86 86
@@ -124,7 +124,7 @@ static void iwl_trans_rxq_free_rx_bufs(struct iwl_trans *trans)
124 /* In the reset function, these buffers may have been allocated 124 /* In the reset function, these buffers may have been allocated
125 * to an SKB, so we need to unmap and free potential storage */ 125 * to an SKB, so we need to unmap and free potential storage */
126 if (rxq->pool[i].page != NULL) { 126 if (rxq->pool[i].page != NULL) {
127 dma_unmap_page(bus(trans)->dev, rxq->pool[i].page_dma, 127 dma_unmap_page(trans->dev, rxq->pool[i].page_dma,
128 PAGE_SIZE << hw_params(trans).rx_page_order, 128 PAGE_SIZE << hw_params(trans).rx_page_order,
129 DMA_FROM_DEVICE); 129 DMA_FROM_DEVICE);
130 __free_pages(rxq->pool[i].page, 130 __free_pages(rxq->pool[i].page,
@@ -148,17 +148,17 @@ static void iwl_trans_rx_hw_init(struct iwl_trans *trans,
148 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K; 148 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
149 149
150 /* Stop Rx DMA */ 150 /* Stop Rx DMA */
151 iwl_write_direct32(bus(trans), FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); 151 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
152 152
153 /* Reset driver's Rx queue write index */ 153 /* Reset driver's Rx queue write index */
154 iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0); 154 iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
155 155
156 /* Tell device where to find RBD circular buffer in DRAM */ 156 /* Tell device where to find RBD circular buffer in DRAM */
157 iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_RBDCB_BASE_REG, 157 iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
158 (u32)(rxq->bd_dma >> 8)); 158 (u32)(rxq->bd_dma >> 8));
159 159
160 /* Tell device where in DRAM to update its Rx status */ 160 /* Tell device where in DRAM to update its Rx status */
161 iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_STTS_WPTR_REG, 161 iwl_write_direct32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG,
162 rxq->rb_stts_dma >> 4); 162 rxq->rb_stts_dma >> 4);
163 163
164 /* Enable Rx DMA 164 /* Enable Rx DMA
@@ -169,7 +169,7 @@ static void iwl_trans_rx_hw_init(struct iwl_trans *trans,
169 * RB timeout 0x10 169 * RB timeout 0x10
170 * 256 RBDs 170 * 256 RBDs
171 */ 171 */
172 iwl_write_direct32(bus(trans), FH_MEM_RCSR_CHNL0_CONFIG_REG, 172 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG,
173 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL | 173 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
174 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY | 174 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
175 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL | 175 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
@@ -179,7 +179,7 @@ static void iwl_trans_rx_hw_init(struct iwl_trans *trans,
179 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS)); 179 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
180 180
181 /* Set interrupt coalescing timer to default (2048 usecs) */ 181 /* Set interrupt coalescing timer to default (2048 usecs) */
182 iwl_write8(bus(trans), CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF); 182 iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
183} 183}
184 184
185static int iwl_rx_init(struct iwl_trans *trans) 185static int iwl_rx_init(struct iwl_trans *trans)
@@ -244,13 +244,13 @@ static void iwl_trans_pcie_rx_free(struct iwl_trans *trans)
244 iwl_trans_rxq_free_rx_bufs(trans); 244 iwl_trans_rxq_free_rx_bufs(trans);
245 spin_unlock_irqrestore(&rxq->lock, flags); 245 spin_unlock_irqrestore(&rxq->lock, flags);
246 246
247 dma_free_coherent(bus(trans)->dev, sizeof(__le32) * RX_QUEUE_SIZE, 247 dma_free_coherent(trans->dev, sizeof(__le32) * RX_QUEUE_SIZE,
248 rxq->bd, rxq->bd_dma); 248 rxq->bd, rxq->bd_dma);
249 memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma)); 249 memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
250 rxq->bd = NULL; 250 rxq->bd = NULL;
251 251
252 if (rxq->rb_stts) 252 if (rxq->rb_stts)
253 dma_free_coherent(bus(trans)->dev, 253 dma_free_coherent(trans->dev,
254 sizeof(struct iwl_rb_status), 254 sizeof(struct iwl_rb_status),
255 rxq->rb_stts, rxq->rb_stts_dma); 255 rxq->rb_stts, rxq->rb_stts_dma);
256 else 256 else
@@ -263,8 +263,8 @@ static int iwl_trans_rx_stop(struct iwl_trans *trans)
263{ 263{
264 264
265 /* stop Rx DMA */ 265 /* stop Rx DMA */
266 iwl_write_direct32(bus(trans), FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); 266 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
267 return iwl_poll_direct_bit(bus(trans), FH_MEM_RSSR_RX_STATUS_REG, 267 return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG,
268 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000); 268 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
269} 269}
270 270
@@ -274,7 +274,7 @@ static inline int iwlagn_alloc_dma_ptr(struct iwl_trans *trans,
274 if (WARN_ON(ptr->addr)) 274 if (WARN_ON(ptr->addr))
275 return -EINVAL; 275 return -EINVAL;
276 276
277 ptr->addr = dma_alloc_coherent(bus(trans)->dev, size, 277 ptr->addr = dma_alloc_coherent(trans->dev, size,
278 &ptr->dma, GFP_KERNEL); 278 &ptr->dma, GFP_KERNEL);
279 if (!ptr->addr) 279 if (!ptr->addr)
280 return -ENOMEM; 280 return -ENOMEM;
@@ -288,7 +288,7 @@ static inline void iwlagn_free_dma_ptr(struct iwl_trans *trans,
288 if (unlikely(!ptr->addr)) 288 if (unlikely(!ptr->addr))
289 return; 289 return;
290 290
291 dma_free_coherent(bus(trans)->dev, ptr->size, ptr->addr, ptr->dma); 291 dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma);
292 memset(ptr, 0, sizeof(*ptr)); 292 memset(ptr, 0, sizeof(*ptr));
293} 293}
294 294
@@ -335,7 +335,7 @@ static int iwl_trans_txq_alloc(struct iwl_trans *trans,
335 335
336 /* Circular buffer of transmit frame descriptors (TFDs), 336 /* Circular buffer of transmit frame descriptors (TFDs),
337 * shared with device */ 337 * shared with device */
338 txq->tfds = dma_alloc_coherent(bus(trans)->dev, tfd_sz, 338 txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz,
339 &txq->q.dma_addr, GFP_KERNEL); 339 &txq->q.dma_addr, GFP_KERNEL);
340 if (!txq->tfds) { 340 if (!txq->tfds) {
341 IWL_ERR(trans, "dma_alloc_coherent(%zd) failed\n", tfd_sz); 341 IWL_ERR(trans, "dma_alloc_coherent(%zd) failed\n", tfd_sz);
@@ -391,7 +391,7 @@ static int iwl_trans_txq_init(struct iwl_trans *trans, struct iwl_tx_queue *txq,
391 * Tell nic where to find circular buffer of Tx Frame Descriptors for 391 * Tell nic where to find circular buffer of Tx Frame Descriptors for
392 * given Tx queue, and enable the DMA channel used for that queue. 392 * given Tx queue, and enable the DMA channel used for that queue.
393 * Circular buffer (TFD queue in DRAM) physical base address */ 393 * Circular buffer (TFD queue in DRAM) physical base address */
394 iwl_write_direct32(bus(trans), FH_MEM_CBBC_QUEUE(txq_id), 394 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
395 txq->q.dma_addr >> 8); 395 txq->q.dma_addr >> 8);
396 396
397 return 0; 397 return 0;
@@ -445,7 +445,7 @@ static void iwl_tx_queue_free(struct iwl_trans *trans, int txq_id)
445{ 445{
446 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 446 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
447 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id]; 447 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
448 struct device *dev = bus(trans)->dev; 448 struct device *dev = trans->dev;
449 int i; 449 int i;
450 if (WARN_ON(!txq)) 450 if (WARN_ON(!txq))
451 return; 451 return;
@@ -586,10 +586,10 @@ static int iwl_tx_init(struct iwl_trans *trans)
586 spin_lock_irqsave(&trans->shrd->lock, flags); 586 spin_lock_irqsave(&trans->shrd->lock, flags);
587 587
588 /* Turn off all Tx DMA fifos */ 588 /* Turn off all Tx DMA fifos */
589 iwl_write_prph(bus(trans), SCD_TXFACT, 0); 589 iwl_write_prph(trans, SCD_TXFACT, 0);
590 590
591 /* Tell NIC where to find the "keep warm" buffer */ 591 /* Tell NIC where to find the "keep warm" buffer */
592 iwl_write_direct32(bus(trans), FH_KW_MEM_ADDR_REG, 592 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
593 trans_pcie->kw.dma >> 4); 593 trans_pcie->kw.dma >> 4);
594 594
595 spin_unlock_irqrestore(&trans->shrd->lock, flags); 595 spin_unlock_irqrestore(&trans->shrd->lock, flags);
@@ -621,12 +621,12 @@ static void iwl_set_pwr_vmain(struct iwl_trans *trans)
621 * to set power to V_AUX, do: 621 * to set power to V_AUX, do:
622 622
623 if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) 623 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
624 iwl_set_bits_mask_prph(bus(trans), APMG_PS_CTRL_REG, 624 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
625 APMG_PS_CTRL_VAL_PWR_SRC_VAUX, 625 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
626 ~APMG_PS_CTRL_MSK_PWR_SRC); 626 ~APMG_PS_CTRL_MSK_PWR_SRC);
627 */ 627 */
628 628
629 iwl_set_bits_mask_prph(bus(trans), APMG_PS_CTRL_REG, 629 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
630 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, 630 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
631 ~APMG_PS_CTRL_MSK_PWR_SRC); 631 ~APMG_PS_CTRL_MSK_PWR_SRC);
632} 632}
@@ -640,7 +640,7 @@ static int iwl_nic_init(struct iwl_trans *trans)
640 iwl_apm_init(priv(trans)); 640 iwl_apm_init(priv(trans));
641 641
642 /* Set interrupt coalescing calibration timer to default (512 usecs) */ 642 /* Set interrupt coalescing calibration timer to default (512 usecs) */
643 iwl_write8(bus(trans), CSR_INT_COALESCING, 643 iwl_write8(trans, CSR_INT_COALESCING,
644 IWL_HOST_INT_CALIB_TIMEOUT_DEF); 644 IWL_HOST_INT_CALIB_TIMEOUT_DEF);
645 645
646 spin_unlock_irqrestore(&trans->shrd->lock, flags); 646 spin_unlock_irqrestore(&trans->shrd->lock, flags);
@@ -660,7 +660,7 @@ static int iwl_nic_init(struct iwl_trans *trans)
660 660
661 if (hw_params(trans).shadow_reg_enable) { 661 if (hw_params(trans).shadow_reg_enable) {
662 /* enable shadow regs in HW */ 662 /* enable shadow regs in HW */
663 iwl_set_bit(bus(trans), CSR_MAC_SHADOW_REG_CTRL, 663 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL,
664 0x800FFFFF); 664 0x800FFFFF);
665 } 665 }
666 666
@@ -676,11 +676,11 @@ static int iwl_set_hw_ready(struct iwl_trans *trans)
676{ 676{
677 int ret; 677 int ret;
678 678
679 iwl_set_bit(bus(trans), CSR_HW_IF_CONFIG_REG, 679 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
680 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); 680 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
681 681
682 /* See if we got it */ 682 /* See if we got it */
683 ret = iwl_poll_bit(bus(trans), CSR_HW_IF_CONFIG_REG, 683 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
684 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 684 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
685 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 685 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
686 HW_READY_TIMEOUT); 686 HW_READY_TIMEOUT);
@@ -701,10 +701,10 @@ static int iwl_trans_pcie_prepare_card_hw(struct iwl_trans *trans)
701 return 0; 701 return 0;
702 702
703 /* If HW is not ready, prepare the conditions to check again */ 703 /* If HW is not ready, prepare the conditions to check again */
704 iwl_set_bit(bus(trans), CSR_HW_IF_CONFIG_REG, 704 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
705 CSR_HW_IF_CONFIG_REG_PREPARE); 705 CSR_HW_IF_CONFIG_REG_PREPARE);
706 706
707 ret = iwl_poll_bit(bus(trans), CSR_HW_IF_CONFIG_REG, 707 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
708 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 708 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
709 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000); 709 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
710 710
@@ -794,7 +794,7 @@ static int iwl_trans_pcie_start_device(struct iwl_trans *trans)
794 } 794 }
795 795
796 /* If platform's RF_KILL switch is NOT set to KILL */ 796 /* If platform's RF_KILL switch is NOT set to KILL */
797 if (iwl_read32(bus(trans), CSR_GP_CNTRL) & 797 if (iwl_read32(trans, CSR_GP_CNTRL) &
798 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) 798 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
799 clear_bit(STATUS_RF_KILL_HW, &trans->shrd->status); 799 clear_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
800 else 800 else
@@ -806,7 +806,7 @@ static int iwl_trans_pcie_start_device(struct iwl_trans *trans)
806 return -ERFKILL; 806 return -ERFKILL;
807 } 807 }
808 808
809 iwl_write32(bus(trans), CSR_INT, 0xFFFFFFFF); 809 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
810 810
811 ret = iwl_nic_init(trans); 811 ret = iwl_nic_init(trans);
812 if (ret) { 812 if (ret) {
@@ -815,17 +815,17 @@ static int iwl_trans_pcie_start_device(struct iwl_trans *trans)
815 } 815 }
816 816
817 /* make sure rfkill handshake bits are cleared */ 817 /* make sure rfkill handshake bits are cleared */
818 iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 818 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
819 iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR, 819 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
820 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 820 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
821 821
822 /* clear (again), then enable host interrupts */ 822 /* clear (again), then enable host interrupts */
823 iwl_write32(bus(trans), CSR_INT, 0xFFFFFFFF); 823 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
824 iwl_enable_interrupts(trans); 824 iwl_enable_interrupts(trans);
825 825
826 /* really make sure rfkill handshake bits are cleared */ 826 /* really make sure rfkill handshake bits are cleared */
827 iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 827 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
828 iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 828 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
829 829
830 return 0; 830 return 0;
831} 831}
@@ -836,7 +836,7 @@ static int iwl_trans_pcie_start_device(struct iwl_trans *trans)
836 */ 836 */
837static void iwl_trans_txq_set_sched(struct iwl_trans *trans, u32 mask) 837static void iwl_trans_txq_set_sched(struct iwl_trans *trans, u32 mask)
838{ 838{
839 iwl_write_prph(bus(trans), SCD_TXFACT, mask); 839 iwl_write_prph(trans, SCD_TXFACT, mask);
840} 840}
841 841
842static void iwl_tx_start(struct iwl_trans *trans) 842static void iwl_tx_start(struct iwl_trans *trans)
@@ -852,46 +852,46 @@ static void iwl_tx_start(struct iwl_trans *trans)
852 spin_lock_irqsave(&trans->shrd->lock, flags); 852 spin_lock_irqsave(&trans->shrd->lock, flags);
853 853
854 trans_pcie->scd_base_addr = 854 trans_pcie->scd_base_addr =
855 iwl_read_prph(bus(trans), SCD_SRAM_BASE_ADDR); 855 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR);
856 a = trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_LOWER_BOUND; 856 a = trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_LOWER_BOUND;
857 /* reset conext data memory */ 857 /* reset conext data memory */
858 for (; a < trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND; 858 for (; a < trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND;
859 a += 4) 859 a += 4)
860 iwl_write_targ_mem(bus(trans), a, 0); 860 iwl_write_targ_mem(trans, a, 0);
861 /* reset tx status memory */ 861 /* reset tx status memory */
862 for (; a < trans_pcie->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND; 862 for (; a < trans_pcie->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND;
863 a += 4) 863 a += 4)
864 iwl_write_targ_mem(bus(trans), a, 0); 864 iwl_write_targ_mem(trans, a, 0);
865 for (; a < trans_pcie->scd_base_addr + 865 for (; a < trans_pcie->scd_base_addr +
866 SCD_TRANS_TBL_OFFSET_QUEUE(hw_params(trans).max_txq_num); 866 SCD_TRANS_TBL_OFFSET_QUEUE(hw_params(trans).max_txq_num);
867 a += 4) 867 a += 4)
868 iwl_write_targ_mem(bus(trans), a, 0); 868 iwl_write_targ_mem(trans, a, 0);
869 869
870 iwl_write_prph(bus(trans), SCD_DRAM_BASE_ADDR, 870 iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
871 trans_pcie->scd_bc_tbls.dma >> 10); 871 trans_pcie->scd_bc_tbls.dma >> 10);
872 872
873 /* Enable DMA channel */ 873 /* Enable DMA channel */
874 for (chan = 0; chan < FH_TCSR_CHNL_NUM ; chan++) 874 for (chan = 0; chan < FH_TCSR_CHNL_NUM ; chan++)
875 iwl_write_direct32(bus(trans), FH_TCSR_CHNL_TX_CONFIG_REG(chan), 875 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
876 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 876 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
877 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE); 877 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
878 878
879 /* Update FH chicken bits */ 879 /* Update FH chicken bits */
880 reg_val = iwl_read_direct32(bus(trans), FH_TX_CHICKEN_BITS_REG); 880 reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);
881 iwl_write_direct32(bus(trans), FH_TX_CHICKEN_BITS_REG, 881 iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,
882 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN); 882 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
883 883
884 iwl_write_prph(bus(trans), SCD_QUEUECHAIN_SEL, 884 iwl_write_prph(trans, SCD_QUEUECHAIN_SEL,
885 SCD_QUEUECHAIN_SEL_ALL(trans)); 885 SCD_QUEUECHAIN_SEL_ALL(trans));
886 iwl_write_prph(bus(trans), SCD_AGGR_SEL, 0); 886 iwl_write_prph(trans, SCD_AGGR_SEL, 0);
887 887
888 /* initiate the queues */ 888 /* initiate the queues */
889 for (i = 0; i < hw_params(trans).max_txq_num; i++) { 889 for (i = 0; i < hw_params(trans).max_txq_num; i++) {
890 iwl_write_prph(bus(trans), SCD_QUEUE_RDPTR(i), 0); 890 iwl_write_prph(trans, SCD_QUEUE_RDPTR(i), 0);
891 iwl_write_direct32(bus(trans), HBUS_TARG_WRPTR, 0 | (i << 8)); 891 iwl_write_direct32(trans, HBUS_TARG_WRPTR, 0 | (i << 8));
892 iwl_write_targ_mem(bus(trans), trans_pcie->scd_base_addr + 892 iwl_write_targ_mem(trans, trans_pcie->scd_base_addr +
893 SCD_CONTEXT_QUEUE_OFFSET(i), 0); 893 SCD_CONTEXT_QUEUE_OFFSET(i), 0);
894 iwl_write_targ_mem(bus(trans), trans_pcie->scd_base_addr + 894 iwl_write_targ_mem(trans, trans_pcie->scd_base_addr +
895 SCD_CONTEXT_QUEUE_OFFSET(i) + 895 SCD_CONTEXT_QUEUE_OFFSET(i) +
896 sizeof(u32), 896 sizeof(u32),
897 ((SCD_WIN_SIZE << 897 ((SCD_WIN_SIZE <<
@@ -902,7 +902,7 @@ static void iwl_tx_start(struct iwl_trans *trans)
902 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); 902 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
903 } 903 }
904 904
905 iwl_write_prph(bus(trans), SCD_INTERRUPT_MASK, 905 iwl_write_prph(trans, SCD_INTERRUPT_MASK,
906 IWL_MASK(0, hw_params(trans).max_txq_num)); 906 IWL_MASK(0, hw_params(trans).max_txq_num));
907 907
908 /* Activate all Tx DMA/FIFO channels */ 908 /* Activate all Tx DMA/FIFO channels */
@@ -948,7 +948,7 @@ static void iwl_tx_start(struct iwl_trans *trans)
948 spin_unlock_irqrestore(&trans->shrd->lock, flags); 948 spin_unlock_irqrestore(&trans->shrd->lock, flags);
949 949
950 /* Enable L1-Active */ 950 /* Enable L1-Active */
951 iwl_clear_bits_prph(bus(trans), APMG_PCIDEV_STT_REG, 951 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
952 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 952 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
953} 953}
954 954
@@ -974,14 +974,14 @@ static int iwl_trans_tx_stop(struct iwl_trans *trans)
974 974
975 /* Stop each Tx DMA channel, and wait for it to be idle */ 975 /* Stop each Tx DMA channel, and wait for it to be idle */
976 for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) { 976 for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
977 iwl_write_direct32(bus(trans), 977 iwl_write_direct32(trans,
978 FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0); 978 FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
979 if (iwl_poll_direct_bit(bus(trans), FH_TSSR_TX_STATUS_REG, 979 if (iwl_poll_direct_bit(trans, FH_TSSR_TX_STATUS_REG,
980 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch), 980 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
981 1000)) 981 1000))
982 IWL_ERR(trans, "Failing on timeout while stopping" 982 IWL_ERR(trans, "Failing on timeout while stopping"
983 " DMA channel %d [0x%08x]", ch, 983 " DMA channel %d [0x%08x]", ch,
984 iwl_read_direct32(bus(trans), 984 iwl_read_direct32(trans,
985 FH_TSSR_TX_STATUS_REG)); 985 FH_TSSR_TX_STATUS_REG));
986 } 986 }
987 spin_unlock_irqrestore(&trans->shrd->lock, flags); 987 spin_unlock_irqrestore(&trans->shrd->lock, flags);
@@ -1024,13 +1024,13 @@ static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
1024 iwl_trans_rx_stop(trans); 1024 iwl_trans_rx_stop(trans);
1025#endif 1025#endif
1026 /* Power-down device's busmaster DMA clocks */ 1026 /* Power-down device's busmaster DMA clocks */
1027 iwl_write_prph(bus(trans), APMG_CLK_DIS_REG, 1027 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1028 APMG_CLK_VAL_DMA_CLK_RQT); 1028 APMG_CLK_VAL_DMA_CLK_RQT);
1029 udelay(5); 1029 udelay(5);
1030 } 1030 }
1031 1031
1032 /* Make sure (redundant) we've released our request to stay awake */ 1032 /* Make sure (redundant) we've released our request to stay awake */
1033 iwl_clear_bit(bus(trans), CSR_GP_CNTRL, 1033 iwl_clear_bit(trans, CSR_GP_CNTRL,
1034 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1034 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1035 1035
1036 /* Stop the device, and put it in low power state */ 1036 /* Stop the device, and put it in low power state */
@@ -1048,7 +1048,7 @@ static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
1048 tasklet_kill(&trans_pcie->irq_tasklet); 1048 tasklet_kill(&trans_pcie->irq_tasklet);
1049 1049
1050 /* stop and reset the on-board processor */ 1050 /* stop and reset the on-board processor */
1051 iwl_write32(bus(trans), CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); 1051 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
1052} 1052}
1053 1053
1054static int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb, 1054static int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
@@ -1145,10 +1145,10 @@ static int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
1145 1145
1146 /* Physical address of this Tx command's header (not MAC header!), 1146 /* Physical address of this Tx command's header (not MAC header!),
1147 * within command buffer array. */ 1147 * within command buffer array. */
1148 txcmd_phys = dma_map_single(bus(trans)->dev, 1148 txcmd_phys = dma_map_single(trans->dev,
1149 &dev_cmd->hdr, firstlen, 1149 &dev_cmd->hdr, firstlen,
1150 DMA_BIDIRECTIONAL); 1150 DMA_BIDIRECTIONAL);
1151 if (unlikely(dma_mapping_error(bus(trans)->dev, txcmd_phys))) 1151 if (unlikely(dma_mapping_error(trans->dev, txcmd_phys)))
1152 return -1; 1152 return -1;
1153 dma_unmap_addr_set(out_meta, mapping, txcmd_phys); 1153 dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
1154 dma_unmap_len_set(out_meta, len, firstlen); 1154 dma_unmap_len_set(out_meta, len, firstlen);
@@ -1164,10 +1164,10 @@ static int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
1164 * if any (802.11 null frames have no payload). */ 1164 * if any (802.11 null frames have no payload). */
1165 secondlen = skb->len - hdr_len; 1165 secondlen = skb->len - hdr_len;
1166 if (secondlen > 0) { 1166 if (secondlen > 0) {
1167 phys_addr = dma_map_single(bus(trans)->dev, skb->data + hdr_len, 1167 phys_addr = dma_map_single(trans->dev, skb->data + hdr_len,
1168 secondlen, DMA_TO_DEVICE); 1168 secondlen, DMA_TO_DEVICE);
1169 if (unlikely(dma_mapping_error(bus(trans)->dev, phys_addr))) { 1169 if (unlikely(dma_mapping_error(trans->dev, phys_addr))) {
1170 dma_unmap_single(bus(trans)->dev, 1170 dma_unmap_single(trans->dev,
1171 dma_unmap_addr(out_meta, mapping), 1171 dma_unmap_addr(out_meta, mapping),
1172 dma_unmap_len(out_meta, len), 1172 dma_unmap_len(out_meta, len),
1173 DMA_BIDIRECTIONAL); 1173 DMA_BIDIRECTIONAL);
@@ -1185,7 +1185,7 @@ static int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
1185 offsetof(struct iwl_tx_cmd, scratch); 1185 offsetof(struct iwl_tx_cmd, scratch);
1186 1186
1187 /* take back ownership of DMA buffer to enable update */ 1187 /* take back ownership of DMA buffer to enable update */
1188 dma_sync_single_for_cpu(bus(trans)->dev, txcmd_phys, firstlen, 1188 dma_sync_single_for_cpu(trans->dev, txcmd_phys, firstlen,
1189 DMA_BIDIRECTIONAL); 1189 DMA_BIDIRECTIONAL);
1190 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys); 1190 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1191 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys); 1191 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
@@ -1199,7 +1199,7 @@ static int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
1199 /* Set up entry for this TFD in Tx byte-count array */ 1199 /* Set up entry for this TFD in Tx byte-count array */
1200 iwl_trans_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len)); 1200 iwl_trans_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len));
1201 1201
1202 dma_sync_single_for_device(bus(trans)->dev, txcmd_phys, firstlen, 1202 dma_sync_single_for_device(trans->dev, txcmd_phys, firstlen,
1203 DMA_BIDIRECTIONAL); 1203 DMA_BIDIRECTIONAL);
1204 1204
1205 trace_iwlwifi_dev_tx(priv(trans), 1205 trace_iwlwifi_dev_tx(priv(trans),
@@ -1232,7 +1232,7 @@ static int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
1232static void iwl_trans_pcie_kick_nic(struct iwl_trans *trans) 1232static void iwl_trans_pcie_kick_nic(struct iwl_trans *trans)
1233{ 1233{
1234 /* Remove all resets to allow NIC to operate */ 1234 /* Remove all resets to allow NIC to operate */
1235 iwl_write32(bus(trans), CSR_RESET, 0); 1235 iwl_write32(trans, CSR_RESET, 0);
1236} 1236}
1237 1237
1238static int iwl_trans_pcie_request_irq(struct iwl_trans *trans) 1238static int iwl_trans_pcie_request_irq(struct iwl_trans *trans)
@@ -1355,7 +1355,7 @@ static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
1355 iwl_apm_stop(priv(trans)); 1355 iwl_apm_stop(priv(trans));
1356 } else { 1356 } else {
1357 iwl_disable_interrupts(trans); 1357 iwl_disable_interrupts(trans);
1358 iwl_clear_bit(bus(trans), CSR_GP_CNTRL, 1358 iwl_clear_bit(trans, CSR_GP_CNTRL,
1359 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1359 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1360 } 1360 }
1361 1361
@@ -1368,7 +1368,7 @@ static int iwl_trans_pcie_resume(struct iwl_trans *trans)
1368 1368
1369 iwl_enable_interrupts(trans); 1369 iwl_enable_interrupts(trans);
1370 1370
1371 if (!(iwl_read32(bus(trans), CSR_GP_CNTRL) & 1371 if (!(iwl_read32(trans, CSR_GP_CNTRL) &
1372 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)) 1372 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1373 hw_rfkill = true; 1373 hw_rfkill = true;
1374 1374
@@ -1464,9 +1464,9 @@ static int iwl_trans_pcie_check_stuck_queue(struct iwl_trans *trans, int cnt)
1464 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n", 1464 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1465 q->read_ptr, q->write_ptr); 1465 q->read_ptr, q->write_ptr);
1466 IWL_ERR(trans, "Current HW read_ptr %d write_ptr %d\n", 1466 IWL_ERR(trans, "Current HW read_ptr %d write_ptr %d\n",
1467 iwl_read_prph(bus(trans), SCD_QUEUE_RDPTR(cnt)) 1467 iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt))
1468 & (TFD_QUEUE_SIZE_MAX - 1), 1468 & (TFD_QUEUE_SIZE_MAX - 1),
1469 iwl_read_prph(bus(trans), SCD_QUEUE_WRPTR(cnt))); 1469 iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1470 return 1; 1470 return 1;
1471 } 1471 }
1472 1472
@@ -1520,7 +1520,7 @@ int iwl_dump_fh(struct iwl_trans *trans, char **buf, bool display)
1520 pos += scnprintf(*buf + pos, bufsz - pos, 1520 pos += scnprintf(*buf + pos, bufsz - pos,
1521 " %34s: 0X%08x\n", 1521 " %34s: 0X%08x\n",
1522 get_fh_string(fh_tbl[i]), 1522 get_fh_string(fh_tbl[i]),
1523 iwl_read_direct32(bus(trans), fh_tbl[i])); 1523 iwl_read_direct32(trans, fh_tbl[i]));
1524 } 1524 }
1525 return pos; 1525 return pos;
1526 } 1526 }
@@ -1529,7 +1529,7 @@ int iwl_dump_fh(struct iwl_trans *trans, char **buf, bool display)
1529 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) { 1529 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1530 IWL_ERR(trans, " %34s: 0X%08x\n", 1530 IWL_ERR(trans, " %34s: 0X%08x\n",
1531 get_fh_string(fh_tbl[i]), 1531 get_fh_string(fh_tbl[i]),
1532 iwl_read_direct32(bus(trans), fh_tbl[i])); 1532 iwl_read_direct32(trans, fh_tbl[i]));
1533 } 1533 }
1534 return 0; 1534 return 0;
1535} 1535}
@@ -1599,7 +1599,7 @@ void iwl_dump_csr(struct iwl_trans *trans)
1599 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { 1599 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
1600 IWL_ERR(trans, " %25s: 0X%08x\n", 1600 IWL_ERR(trans, " %25s: 0X%08x\n",
1601 get_csr_string(csr_tbl[i]), 1601 get_csr_string(csr_tbl[i]),
1602 iwl_read32(bus(trans), csr_tbl[i])); 1602 iwl_read32(trans, csr_tbl[i]));
1603 } 1603 }
1604} 1604}
1605 1605
diff --git a/drivers/net/wireless/iwlwifi/iwl-trans.h b/drivers/net/wireless/iwlwifi/iwl-trans.h
index 0a3727dac6a..dec935a84a7 100644
--- a/drivers/net/wireless/iwlwifi/iwl-trans.h
+++ b/drivers/net/wireless/iwlwifi/iwl-trans.h
@@ -234,6 +234,7 @@ struct iwl_calib_result {
234 * @ops - pointer to iwl_trans_ops 234 * @ops - pointer to iwl_trans_ops
235 * @shrd - pointer to iwl_shared which holds shared data from the upper layer 235 * @shrd - pointer to iwl_shared which holds shared data from the upper layer
236 * @hcmd_lock: protects HCMD 236 * @hcmd_lock: protects HCMD
237 * @reg_lock - protect hw register access
237 * @dev - pointer to struct device * that represents the device 238 * @dev - pointer to struct device * that represents the device
238 * @irq - the irq number for the device 239 * @irq - the irq number for the device
239 * @ucode_write_complete: indicates that the ucode has been copied. 240 * @ucode_write_complete: indicates that the ucode has been copied.
@@ -247,6 +248,7 @@ struct iwl_trans {
247 const struct iwl_trans_ops *ops; 248 const struct iwl_trans_ops *ops;
248 struct iwl_shared *shrd; 249 struct iwl_shared *shrd;
249 spinlock_t hcmd_lock; 250 spinlock_t hcmd_lock;
251 spinlock_t reg_lock;
250 252
251 struct device *dev; 253 struct device *dev;
252 unsigned int irq; 254 unsigned int irq;
diff --git a/drivers/net/wireless/iwlwifi/iwl-ucode.c b/drivers/net/wireless/iwlwifi/iwl-ucode.c
index 0d7f207ac61..5de8b5beb09 100644
--- a/drivers/net/wireless/iwlwifi/iwl-ucode.c
+++ b/drivers/net/wireless/iwlwifi/iwl-ucode.c
@@ -126,42 +126,41 @@ int iwl_alloc_fw_desc(struct iwl_bus *bus, struct fw_desc *desc,
126static int iwl_load_section(struct iwl_trans *trans, const char *name, 126static int iwl_load_section(struct iwl_trans *trans, const char *name,
127 struct fw_desc *image, u32 dst_addr) 127 struct fw_desc *image, u32 dst_addr)
128{ 128{
129 struct iwl_bus *bus = bus(trans);
130 dma_addr_t phy_addr = image->p_addr; 129 dma_addr_t phy_addr = image->p_addr;
131 u32 byte_cnt = image->len; 130 u32 byte_cnt = image->len;
132 int ret; 131 int ret;
133 132
134 trans->ucode_write_complete = 0; 133 trans->ucode_write_complete = 0;
135 134
136 iwl_write_direct32(bus, 135 iwl_write_direct32(trans,
137 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 136 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
138 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); 137 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
139 138
140 iwl_write_direct32(bus, 139 iwl_write_direct32(trans,
141 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr); 140 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
142 141
143 iwl_write_direct32(bus, 142 iwl_write_direct32(trans,
144 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), 143 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
145 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); 144 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
146 145
147 iwl_write_direct32(bus, 146 iwl_write_direct32(trans,
148 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), 147 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
149 (iwl_get_dma_hi_addr(phy_addr) 148 (iwl_get_dma_hi_addr(phy_addr)
150 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); 149 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
151 150
152 iwl_write_direct32(bus, 151 iwl_write_direct32(trans,
153 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), 152 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
154 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM | 153 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
155 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX | 154 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
156 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); 155 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
157 156
158 iwl_write_direct32(bus, 157 iwl_write_direct32(trans,
159 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 158 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
160 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 159 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
161 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | 160 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
162 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); 161 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
163 162
164 IWL_DEBUG_FW(bus, "%s uCode section being loaded...\n", name); 163 IWL_DEBUG_FW(trans, "%s uCode section being loaded...\n", name);
165 ret = wait_event_timeout(trans->shrd->wait_command_queue, 164 ret = wait_event_timeout(trans->shrd->wait_command_queue,
166 trans->ucode_write_complete, 5 * HZ); 165 trans->ucode_write_complete, 5 * HZ);
167 if (!ret) { 166 if (!ret) {
@@ -470,7 +469,7 @@ static int iwl_alive_notify(struct iwl_trans *trans)
470 * using sample data 100 bytes apart. If these sample points are good, 469 * using sample data 100 bytes apart. If these sample points are good,
471 * it's a pretty good bet that everything between them is good, too. 470 * it's a pretty good bet that everything between them is good, too.
472 */ 471 */
473static int iwl_verify_inst_sparse(struct iwl_bus *bus, 472static int iwl_verify_inst_sparse(struct iwl_trans *trans,
474 struct fw_desc *fw_desc) 473 struct fw_desc *fw_desc)
475{ 474{
476 __le32 *image = (__le32 *)fw_desc->v_addr; 475 __le32 *image = (__le32 *)fw_desc->v_addr;
@@ -478,15 +477,15 @@ static int iwl_verify_inst_sparse(struct iwl_bus *bus,
478 u32 val; 477 u32 val;
479 u32 i; 478 u32 i;
480 479
481 IWL_DEBUG_FW(bus, "ucode inst image size is %u\n", len); 480 IWL_DEBUG_FW(trans, "ucode inst image size is %u\n", len);
482 481
483 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) { 482 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
484 /* read data comes through single port, auto-incr addr */ 483 /* read data comes through single port, auto-incr addr */
485 /* NOTE: Use the debugless read so we don't flood kernel log 484 /* NOTE: Use the debugless read so we don't flood kernel log
486 * if IWL_DL_IO is set */ 485 * if IWL_DL_IO is set */
487 iwl_write_direct32(bus, HBUS_TARG_MEM_RADDR, 486 iwl_write_direct32(trans, HBUS_TARG_MEM_RADDR,
488 i + IWLAGN_RTC_INST_LOWER_BOUND); 487 i + IWLAGN_RTC_INST_LOWER_BOUND);
489 val = iwl_read32(bus, HBUS_TARG_MEM_RDAT); 488 val = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
490 if (val != le32_to_cpu(*image)) 489 if (val != le32_to_cpu(*image))
491 return -EIO; 490 return -EIO;
492 } 491 }
@@ -494,7 +493,7 @@ static int iwl_verify_inst_sparse(struct iwl_bus *bus,
494 return 0; 493 return 0;
495} 494}
496 495
497static void iwl_print_mismatch_inst(struct iwl_bus *bus, 496static void iwl_print_mismatch_inst(struct iwl_trans *trans,
498 struct fw_desc *fw_desc) 497 struct fw_desc *fw_desc)
499{ 498{
500 __le32 *image = (__le32 *)fw_desc->v_addr; 499 __le32 *image = (__le32 *)fw_desc->v_addr;
@@ -503,18 +502,18 @@ static void iwl_print_mismatch_inst(struct iwl_bus *bus,
503 u32 offs; 502 u32 offs;
504 int errors = 0; 503 int errors = 0;
505 504
506 IWL_DEBUG_FW(bus, "ucode inst image size is %u\n", len); 505 IWL_DEBUG_FW(trans, "ucode inst image size is %u\n", len);
507 506
508 iwl_write_direct32(bus, HBUS_TARG_MEM_RADDR, 507 iwl_write_direct32(trans, HBUS_TARG_MEM_RADDR,
509 IWLAGN_RTC_INST_LOWER_BOUND); 508 IWLAGN_RTC_INST_LOWER_BOUND);
510 509
511 for (offs = 0; 510 for (offs = 0;
512 offs < len && errors < 20; 511 offs < len && errors < 20;
513 offs += sizeof(u32), image++) { 512 offs += sizeof(u32), image++) {
514 /* read data comes through single port, auto-incr addr */ 513 /* read data comes through single port, auto-incr addr */
515 val = iwl_read32(bus, HBUS_TARG_MEM_RDAT); 514 val = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
516 if (val != le32_to_cpu(*image)) { 515 if (val != le32_to_cpu(*image)) {
517 IWL_ERR(bus, "uCode INST section at " 516 IWL_ERR(trans, "uCode INST section at "
518 "offset 0x%x, is 0x%x, s/b 0x%x\n", 517 "offset 0x%x, is 0x%x, s/b 0x%x\n",
519 offs, val, le32_to_cpu(*image)); 518 offs, val, le32_to_cpu(*image));
520 errors++; 519 errors++;
@@ -536,14 +535,14 @@ static int iwl_verify_ucode(struct iwl_trans *trans,
536 return -EINVAL; 535 return -EINVAL;
537 } 536 }
538 537
539 if (!iwl_verify_inst_sparse(bus(trans), &img->code)) { 538 if (!iwl_verify_inst_sparse(trans, &img->code)) {
540 IWL_DEBUG_FW(trans, "uCode is good in inst SRAM\n"); 539 IWL_DEBUG_FW(trans, "uCode is good in inst SRAM\n");
541 return 0; 540 return 0;
542 } 541 }
543 542
544 IWL_ERR(trans, "UCODE IMAGE IN INSTRUCTION SRAM NOT VALID!!\n"); 543 IWL_ERR(trans, "UCODE IMAGE IN INSTRUCTION SRAM NOT VALID!!\n");
545 544
546 iwl_print_mismatch_inst(bus(trans), &img->code); 545 iwl_print_mismatch_inst(trans, &img->code);
547 return -EIO; 546 return -EIO;
548} 547}
549 548
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-21 11:19:49 -0400